1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _
2 // Test host codegen.
3 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck  %s --check-prefix=CHECK1
4 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
5 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck  %s --check-prefix=CHECK2
6 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck  %s --check-prefix=CHECK3
7 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
8 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck  %s --check-prefix=CHECK4
9 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=50 -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck  %s --check-prefix=CHECK5
10 // RUN: %clang_cc1 -fopenmp -fopenmp-version=50 -DOMP5 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
11 // RUN: %clang_cc1 -fopenmp -fopenmp-version=50 -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck  %s --check-prefix=CHECK6
12 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=50 -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck  %s --check-prefix=CHECK7
13 // RUN: %clang_cc1 -fopenmp -fopenmp-version=50 -DOMP5 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
14 // RUN: %clang_cc1 -fopenmp -fopenmp-version=50 -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck  %s --check-prefix=CHECK8
15 
16 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck  %s --check-prefix=CHECK9
17 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
18 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck  %s --check-prefix=CHECK10
19 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck  %s --check-prefix=CHECK11
20 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
21 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck  %s --check-prefix=CHECK12
22 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=50 -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck  %s --check-prefix=CHECK13
23 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -DOMP5 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
24 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck  %s --check-prefix=CHECK14
25 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=50 -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck  %s --check-prefix=CHECK15
26 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -DOMP5 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
27 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck  %s --check-prefix=CHECK16
28 
29 // Test target codegen - host bc file has to be created first.
30 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc
31 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck  %s --check-prefix=CHECK17
32 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s
33 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck  %s --check-prefix=CHECK18
34 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc
35 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck  %s --check-prefix=CHECK19
36 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s
37 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck  %s --check-prefix=CHECK20
38 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=50 -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc
39 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=50 -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck  %s --check-prefix=CHECK21
40 // RUN: %clang_cc1 -fopenmp -fopenmp-version=50 -DOMP5 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s
41 // RUN: %clang_cc1 -fopenmp -fopenmp-version=50 -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck  %s --check-prefix=CHECK22
42 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=50 -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc
43 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=50 -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck  %s --check-prefix=CHECK23
44 // RUN: %clang_cc1 -fopenmp -fopenmp-version=50 -DOMP5 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s
45 // RUN: %clang_cc1 -fopenmp -fopenmp-version=50 -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck  %s --check-prefix=CHECK24
46 
47 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc
48 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck  %s --check-prefix=CHECK25
49 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s
50 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck  %s --check-prefix=CHECK26
51 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc
52 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck  %s --check-prefix=CHECK27
53 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s
54 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck  %s --check-prefix=CHECK28
55 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=50 -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc
56 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=50 -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck  %s --check-prefix=CHECK29
57 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -DOMP5 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s
58 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck  %s --check-prefix=CHECK30
59 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=50 -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc
60 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=50 -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck  %s --check-prefix=CHECK31
61 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -DOMP5 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s
62 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck  %s --check-prefix=CHECK32
63 // expected-no-diagnostics
64 
65 #ifndef HEADER
66 #define HEADER
67 
68 
69 
70 
71 // We have 8 target regions, but only 7 that actually will generate offloading
72 // code, only 6 will have mapped arguments, and only 4 have all-constant map
73 // sizes.
74 
75 
76 
77 // Check target registration is registered as a Ctor.
78 
79 
80 template<typename tx, typename ty>
81 struct TT{
82   tx X;
83   ty Y;
84 };
85 
86 int global;
87 
88 int foo(int n) {
89   int a = 0;
90   short aa = 0;
91   float b[10];
92   float bn[n];
93   double c[5][10];
94   double cn[5][n];
95   TT<long long, char> d;
96 
97   #pragma omp target teams distribute simd num_teams(a) thread_limit(a) firstprivate(aa) simdlen(16) nowait
98   for (int i = 0; i < 10; ++i) {
99   }
100 
101 #ifdef OMP5
102   #pragma omp target teams distribute simd if(target: 0) safelen(32) linear(a) if(simd: 1) nontemporal(a)
103 #else
104   #pragma omp target teams distribute simd if(target: 0) safelen(32) linear(a)
105 #endif // OMP5
106   for (a = 0; a < 10; ++a) {
107     a += 1;
108   }
109 
110 
111   #pragma omp target teams distribute simd if(target: 1)
112   for (int i = 0; i < 10; ++i) {
113     aa += 1;
114   }
115 
116 
117 
118   #pragma omp target teams distribute simd if(target: n>10)
119   for (int i = 0; i < 10; ++i) {
120     a += 1;
121     aa += 1;
122   }
123 
124   // We capture 3 VLA sizes in this target region
125 
126 
127 
128 
129 
130   // The names below are not necessarily consistent with the names used for the
131   // addresses above as some are repeated.
132 
133 
134 
135 
136 
137 
138 
139 
140 
141 
142   #pragma omp target teams distribute simd if(target: n>20) aligned(b)
143   for (int i = 0; i < 10; ++i) {
144     a += 1;
145     b[2] += 1.0;
146     bn[3] += 1.0;
147     c[1][2] += 1.0;
148     cn[1][3] += 1.0;
149     d.X += 1;
150     d.Y += 1;
151   }
152 
153   return a;
154 }
155 
156 // Check that the offloading functions are emitted and that the arguments are
157 // correct and loaded correctly for the target regions in foo().
158 
159 
160 
161 
162 // Create stack storage and store argument in there.
163 
164 // Create stack storage and store argument in there.
165 
166 // Create stack storage and store argument in there.
167 
168 // Create local storage for each capture.
169 
170 
171 
172 // To reduce complexity, we're only going as far as validating the signature of the outlined parallel function.
173 
174 template<typename tx>
175 tx ftemplate(int n) {
176   tx a = 0;
177   short aa = 0;
178   tx b[10];
179 
180   #pragma omp target teams distribute simd if(target: n>40)
181   for (int i = 0; i < 10; ++i) {
182     a += 1;
183     aa += 1;
184     b[2] += 1;
185   }
186 
187   return a;
188 }
189 
190 static
191 int fstatic(int n) {
192   int a = 0;
193   short aa = 0;
194   char aaa = 0;
195   int b[10];
196 
197   #pragma omp target teams distribute simd if(target: n>50)
198   for (int i = a; i < n; ++i) {
199     a += 1;
200     aa += 1;
201     aaa += 1;
202     b[2] += 1;
203   }
204 
205   return a;
206 }
207 
208 struct S1 {
209   double a;
210 
211   int r1(int n){
212     int b = n+1;
213     short int c[2][n];
214 
215     #pragma omp target teams distribute simd if(n>60)
216     for (int i = 0; i < 10; ++i) {
217       this->a = (double)b + 1.5;
218       c[1][1] = ++a;
219     }
220 
221     return c[1][1] + (int)b;
222   }
223 };
224 
225 int bar(int n){
226   int a = 0;
227 
228   a += foo(n);
229 
230   S1 S;
231   a += S.r1(n);
232 
233   a += fstatic(n);
234 
235   a += ftemplate<int>(n);
236 
237   return a;
238 }
239 
240 
241 
242 // We capture 2 VLA sizes in this target region
243 
244 
245 // The names below are not necessarily consistent with the names used for the
246 // addresses above as some are repeated.
247 
248 
249 
250 
251 
252 
253 
254 
255 
256 
257 
258 
259 
260 
261 
262 
263 
264 
265 
266 
267 
268 
269 // Check that the offloading functions are emitted and that the arguments are
270 // correct and loaded correctly for the target regions of the callees of bar().
271 
272 // Create local storage for each capture.
273 // Store captures in the context.
274 
275 
276 // To reduce complexity, we're only going as far as validating the signature of the outlined parallel function.
277 
278 
279 // Create local storage for each capture.
280 // Store captures in the context.
281 
282 
283 
284 
285 // To reduce complexity, we're only going as far as validating the signature of the outlined parallel function.
286 
287 // Create local storage for each capture.
288 // Store captures in the context.
289 
290 
291 
292 // To reduce complexity, we're only going as far as validating the signature of the outlined parallel function.
293 
294 
295 #endif
296 // CHECK1-LABEL: define {{[^@]+}}@_Z3fooi
297 // CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0:[0-9]+]] {
298 // CHECK1-NEXT:  entry:
299 // CHECK1-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
300 // CHECK1-NEXT:    [[A:%.*]] = alloca i32, align 4
301 // CHECK1-NEXT:    [[AA:%.*]] = alloca i16, align 2
302 // CHECK1-NEXT:    [[B:%.*]] = alloca [10 x float], align 4
303 // CHECK1-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 8
304 // CHECK1-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
305 // CHECK1-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 8
306 // CHECK1-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i64, align 8
307 // CHECK1-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8
308 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
309 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
310 // CHECK1-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
311 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
312 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR__CASTED4:%.*]] = alloca i64, align 8
313 // CHECK1-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8
314 // CHECK1-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8
315 // CHECK1-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8
316 // CHECK1-NEXT:    [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4
317 // CHECK1-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
318 // CHECK1-NEXT:    [[AA_CASTED7:%.*]] = alloca i64, align 8
319 // CHECK1-NEXT:    [[DOTOFFLOAD_BASEPTRS9:%.*]] = alloca [1 x i8*], align 8
320 // CHECK1-NEXT:    [[DOTOFFLOAD_PTRS10:%.*]] = alloca [1 x i8*], align 8
321 // CHECK1-NEXT:    [[DOTOFFLOAD_MAPPERS11:%.*]] = alloca [1 x i8*], align 8
322 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
323 // CHECK1-NEXT:    [[A_CASTED12:%.*]] = alloca i64, align 8
324 // CHECK1-NEXT:    [[AA_CASTED14:%.*]] = alloca i64, align 8
325 // CHECK1-NEXT:    [[DOTOFFLOAD_BASEPTRS16:%.*]] = alloca [2 x i8*], align 8
326 // CHECK1-NEXT:    [[DOTOFFLOAD_PTRS17:%.*]] = alloca [2 x i8*], align 8
327 // CHECK1-NEXT:    [[DOTOFFLOAD_MAPPERS18:%.*]] = alloca [2 x i8*], align 8
328 // CHECK1-NEXT:    [[_TMP19:%.*]] = alloca i32, align 4
329 // CHECK1-NEXT:    [[A_CASTED22:%.*]] = alloca i64, align 8
330 // CHECK1-NEXT:    [[DOTOFFLOAD_BASEPTRS26:%.*]] = alloca [9 x i8*], align 8
331 // CHECK1-NEXT:    [[DOTOFFLOAD_PTRS27:%.*]] = alloca [9 x i8*], align 8
332 // CHECK1-NEXT:    [[DOTOFFLOAD_MAPPERS28:%.*]] = alloca [9 x i8*], align 8
333 // CHECK1-NEXT:    [[DOTOFFLOAD_SIZES:%.*]] = alloca [9 x i64], align 8
334 // CHECK1-NEXT:    [[_TMP29:%.*]] = alloca i32, align 4
335 // CHECK1-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]])
336 // CHECK1-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
337 // CHECK1-NEXT:    store i32 0, i32* [[A]], align 4
338 // CHECK1-NEXT:    store i16 0, i16* [[AA]], align 2
339 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
340 // CHECK1-NEXT:    [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
341 // CHECK1-NEXT:    [[TMP3:%.*]] = call i8* @llvm.stacksave()
342 // CHECK1-NEXT:    store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8
343 // CHECK1-NEXT:    [[VLA:%.*]] = alloca float, i64 [[TMP2]], align 4
344 // CHECK1-NEXT:    store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8
345 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
346 // CHECK1-NEXT:    [[TMP5:%.*]] = zext i32 [[TMP4]] to i64
347 // CHECK1-NEXT:    [[TMP6:%.*]] = mul nuw i64 5, [[TMP5]]
348 // CHECK1-NEXT:    [[VLA1:%.*]] = alloca double, i64 [[TMP6]], align 8
349 // CHECK1-NEXT:    store i64 [[TMP5]], i64* [[__VLA_EXPR1]], align 8
350 // CHECK1-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
351 // CHECK1-NEXT:    store i32 [[TMP7]], i32* [[DOTCAPTURE_EXPR_]], align 4
352 // CHECK1-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
353 // CHECK1-NEXT:    store i32 [[TMP8]], i32* [[DOTCAPTURE_EXPR_2]], align 4
354 // CHECK1-NEXT:    [[TMP9:%.*]] = load i16, i16* [[AA]], align 2
355 // CHECK1-NEXT:    [[CONV:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
356 // CHECK1-NEXT:    store i16 [[TMP9]], i16* [[CONV]], align 2
357 // CHECK1-NEXT:    [[TMP10:%.*]] = load i64, i64* [[AA_CASTED]], align 8
358 // CHECK1-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
359 // CHECK1-NEXT:    [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
360 // CHECK1-NEXT:    store i32 [[TMP11]], i32* [[CONV3]], align 4
361 // CHECK1-NEXT:    [[TMP12:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
362 // CHECK1-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
363 // CHECK1-NEXT:    [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED4]] to i32*
364 // CHECK1-NEXT:    store i32 [[TMP13]], i32* [[CONV5]], align 4
365 // CHECK1-NEXT:    [[TMP14:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED4]], align 8
366 // CHECK1-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
367 // CHECK1-NEXT:    [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i64*
368 // CHECK1-NEXT:    store i64 [[TMP10]], i64* [[TMP16]], align 8
369 // CHECK1-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
370 // CHECK1-NEXT:    [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64*
371 // CHECK1-NEXT:    store i64 [[TMP10]], i64* [[TMP18]], align 8
372 // CHECK1-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
373 // CHECK1-NEXT:    store i8* null, i8** [[TMP19]], align 8
374 // CHECK1-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
375 // CHECK1-NEXT:    [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i64*
376 // CHECK1-NEXT:    store i64 [[TMP12]], i64* [[TMP21]], align 8
377 // CHECK1-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
378 // CHECK1-NEXT:    [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i64*
379 // CHECK1-NEXT:    store i64 [[TMP12]], i64* [[TMP23]], align 8
380 // CHECK1-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
381 // CHECK1-NEXT:    store i8* null, i8** [[TMP24]], align 8
382 // CHECK1-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
383 // CHECK1-NEXT:    [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i64*
384 // CHECK1-NEXT:    store i64 [[TMP14]], i64* [[TMP26]], align 8
385 // CHECK1-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
386 // CHECK1-NEXT:    [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i64*
387 // CHECK1-NEXT:    store i64 [[TMP14]], i64* [[TMP28]], align 8
388 // CHECK1-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
389 // CHECK1-NEXT:    store i8* null, i8** [[TMP29]], align 8
390 // CHECK1-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
391 // CHECK1-NEXT:    [[TMP31:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
392 // CHECK1-NEXT:    [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 0
393 // CHECK1-NEXT:    [[TMP33:%.*]] = load i16, i16* [[AA]], align 2
394 // CHECK1-NEXT:    store i16 [[TMP33]], i16* [[TMP32]], align 4
395 // CHECK1-NEXT:    [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 1
396 // CHECK1-NEXT:    [[TMP35:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
397 // CHECK1-NEXT:    store i32 [[TMP35]], i32* [[TMP34]], align 4
398 // CHECK1-NEXT:    [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 2
399 // CHECK1-NEXT:    [[TMP37:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
400 // CHECK1-NEXT:    store i32 [[TMP37]], i32* [[TMP36]], align 4
401 // CHECK1-NEXT:    [[TMP38:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 1, i64 120, i64 12, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1)
402 // CHECK1-NEXT:    [[TMP39:%.*]] = bitcast i8* [[TMP38]] to %struct.kmp_task_t_with_privates*
403 // CHECK1-NEXT:    [[TMP40:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP39]], i32 0, i32 0
404 // CHECK1-NEXT:    [[TMP41:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP40]], i32 0, i32 0
405 // CHECK1-NEXT:    [[TMP42:%.*]] = load i8*, i8** [[TMP41]], align 8
406 // CHECK1-NEXT:    [[TMP43:%.*]] = bitcast %struct.anon* [[AGG_CAPTURED]] to i8*
407 // CHECK1-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP42]], i8* align 4 [[TMP43]], i64 12, i1 false)
408 // CHECK1-NEXT:    [[TMP44:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP39]], i32 0, i32 1
409 // CHECK1-NEXT:    [[TMP45:%.*]] = bitcast i8* [[TMP42]] to %struct.anon*
410 // CHECK1-NEXT:    [[TMP46:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 0
411 // CHECK1-NEXT:    [[TMP47:%.*]] = bitcast [3 x i8*]* [[TMP46]] to i8*
412 // CHECK1-NEXT:    [[TMP48:%.*]] = bitcast i8** [[TMP30]] to i8*
413 // CHECK1-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP47]], i8* align 8 [[TMP48]], i64 24, i1 false)
414 // CHECK1-NEXT:    [[TMP49:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 1
415 // CHECK1-NEXT:    [[TMP50:%.*]] = bitcast [3 x i8*]* [[TMP49]] to i8*
416 // CHECK1-NEXT:    [[TMP51:%.*]] = bitcast i8** [[TMP31]] to i8*
417 // CHECK1-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP50]], i8* align 8 [[TMP51]], i64 24, i1 false)
418 // CHECK1-NEXT:    [[TMP52:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 2
419 // CHECK1-NEXT:    [[TMP53:%.*]] = bitcast [3 x i64]* [[TMP52]] to i8*
420 // CHECK1-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP53]], i8* align 8 bitcast ([3 x i64]* @.offload_sizes to i8*), i64 24, i1 false)
421 // CHECK1-NEXT:    [[TMP54:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 3
422 // CHECK1-NEXT:    [[TMP55:%.*]] = load i16, i16* [[AA]], align 2
423 // CHECK1-NEXT:    store i16 [[TMP55]], i16* [[TMP54]], align 8
424 // CHECK1-NEXT:    [[TMP56:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i8* [[TMP38]])
425 // CHECK1-NEXT:    [[TMP57:%.*]] = load i32, i32* [[A]], align 4
426 // CHECK1-NEXT:    [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32*
427 // CHECK1-NEXT:    store i32 [[TMP57]], i32* [[CONV6]], align 4
428 // CHECK1-NEXT:    [[TMP58:%.*]] = load i64, i64* [[A_CASTED]], align 8
429 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104(i64 [[TMP58]]) #[[ATTR4:[0-9]+]]
430 // CHECK1-NEXT:    [[TMP59:%.*]] = load i16, i16* [[AA]], align 2
431 // CHECK1-NEXT:    [[CONV8:%.*]] = bitcast i64* [[AA_CASTED7]] to i16*
432 // CHECK1-NEXT:    store i16 [[TMP59]], i16* [[CONV8]], align 2
433 // CHECK1-NEXT:    [[TMP60:%.*]] = load i64, i64* [[AA_CASTED7]], align 8
434 // CHECK1-NEXT:    [[TMP61:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS9]], i32 0, i32 0
435 // CHECK1-NEXT:    [[TMP62:%.*]] = bitcast i8** [[TMP61]] to i64*
436 // CHECK1-NEXT:    store i64 [[TMP60]], i64* [[TMP62]], align 8
437 // CHECK1-NEXT:    [[TMP63:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS10]], i32 0, i32 0
438 // CHECK1-NEXT:    [[TMP64:%.*]] = bitcast i8** [[TMP63]] to i64*
439 // CHECK1-NEXT:    store i64 [[TMP60]], i64* [[TMP64]], align 8
440 // CHECK1-NEXT:    [[TMP65:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS11]], i64 0, i64 0
441 // CHECK1-NEXT:    store i8* null, i8** [[TMP65]], align 8
442 // CHECK1-NEXT:    [[TMP66:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS9]], i32 0, i32 0
443 // CHECK1-NEXT:    [[TMP67:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS10]], i32 0, i32 0
444 // CHECK1-NEXT:    call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10)
445 // CHECK1-NEXT:    [[TMP68:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.region_id, i32 1, i8** [[TMP66]], i8** [[TMP67]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.4, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.5, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1)
446 // CHECK1-NEXT:    [[TMP69:%.*]] = icmp ne i32 [[TMP68]], 0
447 // CHECK1-NEXT:    br i1 [[TMP69]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
448 // CHECK1:       omp_offload.failed:
449 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111(i64 [[TMP60]]) #[[ATTR4]]
450 // CHECK1-NEXT:    br label [[OMP_OFFLOAD_CONT]]
451 // CHECK1:       omp_offload.cont:
452 // CHECK1-NEXT:    [[TMP70:%.*]] = load i32, i32* [[A]], align 4
453 // CHECK1-NEXT:    [[CONV13:%.*]] = bitcast i64* [[A_CASTED12]] to i32*
454 // CHECK1-NEXT:    store i32 [[TMP70]], i32* [[CONV13]], align 4
455 // CHECK1-NEXT:    [[TMP71:%.*]] = load i64, i64* [[A_CASTED12]], align 8
456 // CHECK1-NEXT:    [[TMP72:%.*]] = load i16, i16* [[AA]], align 2
457 // CHECK1-NEXT:    [[CONV15:%.*]] = bitcast i64* [[AA_CASTED14]] to i16*
458 // CHECK1-NEXT:    store i16 [[TMP72]], i16* [[CONV15]], align 2
459 // CHECK1-NEXT:    [[TMP73:%.*]] = load i64, i64* [[AA_CASTED14]], align 8
460 // CHECK1-NEXT:    [[TMP74:%.*]] = load i32, i32* [[N_ADDR]], align 4
461 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP74]], 10
462 // CHECK1-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
463 // CHECK1:       omp_if.then:
464 // CHECK1-NEXT:    [[TMP75:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 0
465 // CHECK1-NEXT:    [[TMP76:%.*]] = bitcast i8** [[TMP75]] to i64*
466 // CHECK1-NEXT:    store i64 [[TMP71]], i64* [[TMP76]], align 8
467 // CHECK1-NEXT:    [[TMP77:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 0
468 // CHECK1-NEXT:    [[TMP78:%.*]] = bitcast i8** [[TMP77]] to i64*
469 // CHECK1-NEXT:    store i64 [[TMP71]], i64* [[TMP78]], align 8
470 // CHECK1-NEXT:    [[TMP79:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 0
471 // CHECK1-NEXT:    store i8* null, i8** [[TMP79]], align 8
472 // CHECK1-NEXT:    [[TMP80:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 1
473 // CHECK1-NEXT:    [[TMP81:%.*]] = bitcast i8** [[TMP80]] to i64*
474 // CHECK1-NEXT:    store i64 [[TMP73]], i64* [[TMP81]], align 8
475 // CHECK1-NEXT:    [[TMP82:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 1
476 // CHECK1-NEXT:    [[TMP83:%.*]] = bitcast i8** [[TMP82]] to i64*
477 // CHECK1-NEXT:    store i64 [[TMP73]], i64* [[TMP83]], align 8
478 // CHECK1-NEXT:    [[TMP84:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 1
479 // CHECK1-NEXT:    store i8* null, i8** [[TMP84]], align 8
480 // CHECK1-NEXT:    [[TMP85:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 0
481 // CHECK1-NEXT:    [[TMP86:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 0
482 // CHECK1-NEXT:    call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10)
483 // CHECK1-NEXT:    [[TMP87:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.region_id, i32 2, i8** [[TMP85]], i8** [[TMP86]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.7, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.8, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1)
484 // CHECK1-NEXT:    [[TMP88:%.*]] = icmp ne i32 [[TMP87]], 0
485 // CHECK1-NEXT:    br i1 [[TMP88]], label [[OMP_OFFLOAD_FAILED20:%.*]], label [[OMP_OFFLOAD_CONT21:%.*]]
486 // CHECK1:       omp_offload.failed20:
487 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i64 [[TMP71]], i64 [[TMP73]]) #[[ATTR4]]
488 // CHECK1-NEXT:    br label [[OMP_OFFLOAD_CONT21]]
489 // CHECK1:       omp_offload.cont21:
490 // CHECK1-NEXT:    br label [[OMP_IF_END:%.*]]
491 // CHECK1:       omp_if.else:
492 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i64 [[TMP71]], i64 [[TMP73]]) #[[ATTR4]]
493 // CHECK1-NEXT:    br label [[OMP_IF_END]]
494 // CHECK1:       omp_if.end:
495 // CHECK1-NEXT:    [[TMP89:%.*]] = load i32, i32* [[A]], align 4
496 // CHECK1-NEXT:    [[CONV23:%.*]] = bitcast i64* [[A_CASTED22]] to i32*
497 // CHECK1-NEXT:    store i32 [[TMP89]], i32* [[CONV23]], align 4
498 // CHECK1-NEXT:    [[TMP90:%.*]] = load i64, i64* [[A_CASTED22]], align 8
499 // CHECK1-NEXT:    [[TMP91:%.*]] = load i32, i32* [[N_ADDR]], align 4
500 // CHECK1-NEXT:    [[CMP24:%.*]] = icmp sgt i32 [[TMP91]], 20
501 // CHECK1-NEXT:    br i1 [[CMP24]], label [[OMP_IF_THEN25:%.*]], label [[OMP_IF_ELSE32:%.*]]
502 // CHECK1:       omp_if.then25:
503 // CHECK1-NEXT:    [[TMP92:%.*]] = mul nuw i64 [[TMP2]], 4
504 // CHECK1-NEXT:    [[TMP93:%.*]] = mul nuw i64 5, [[TMP5]]
505 // CHECK1-NEXT:    [[TMP94:%.*]] = mul nuw i64 [[TMP93]], 8
506 // CHECK1-NEXT:    [[TMP95:%.*]] = bitcast [9 x i64]* [[DOTOFFLOAD_SIZES]] to i8*
507 // CHECK1-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP95]], i8* align 8 bitcast ([9 x i64]* @.offload_sizes.10 to i8*), i64 72, i1 false)
508 // CHECK1-NEXT:    [[TMP96:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS26]], i32 0, i32 0
509 // CHECK1-NEXT:    [[TMP97:%.*]] = bitcast i8** [[TMP96]] to i64*
510 // CHECK1-NEXT:    store i64 [[TMP90]], i64* [[TMP97]], align 8
511 // CHECK1-NEXT:    [[TMP98:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS27]], i32 0, i32 0
512 // CHECK1-NEXT:    [[TMP99:%.*]] = bitcast i8** [[TMP98]] to i64*
513 // CHECK1-NEXT:    store i64 [[TMP90]], i64* [[TMP99]], align 8
514 // CHECK1-NEXT:    [[TMP100:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS28]], i64 0, i64 0
515 // CHECK1-NEXT:    store i8* null, i8** [[TMP100]], align 8
516 // CHECK1-NEXT:    [[TMP101:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS26]], i32 0, i32 1
517 // CHECK1-NEXT:    [[TMP102:%.*]] = bitcast i8** [[TMP101]] to [10 x float]**
518 // CHECK1-NEXT:    store [10 x float]* [[B]], [10 x float]** [[TMP102]], align 8
519 // CHECK1-NEXT:    [[TMP103:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS27]], i32 0, i32 1
520 // CHECK1-NEXT:    [[TMP104:%.*]] = bitcast i8** [[TMP103]] to [10 x float]**
521 // CHECK1-NEXT:    store [10 x float]* [[B]], [10 x float]** [[TMP104]], align 8
522 // CHECK1-NEXT:    [[TMP105:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS28]], i64 0, i64 1
523 // CHECK1-NEXT:    store i8* null, i8** [[TMP105]], align 8
524 // CHECK1-NEXT:    [[TMP106:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS26]], i32 0, i32 2
525 // CHECK1-NEXT:    [[TMP107:%.*]] = bitcast i8** [[TMP106]] to i64*
526 // CHECK1-NEXT:    store i64 [[TMP2]], i64* [[TMP107]], align 8
527 // CHECK1-NEXT:    [[TMP108:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS27]], i32 0, i32 2
528 // CHECK1-NEXT:    [[TMP109:%.*]] = bitcast i8** [[TMP108]] to i64*
529 // CHECK1-NEXT:    store i64 [[TMP2]], i64* [[TMP109]], align 8
530 // CHECK1-NEXT:    [[TMP110:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS28]], i64 0, i64 2
531 // CHECK1-NEXT:    store i8* null, i8** [[TMP110]], align 8
532 // CHECK1-NEXT:    [[TMP111:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS26]], i32 0, i32 3
533 // CHECK1-NEXT:    [[TMP112:%.*]] = bitcast i8** [[TMP111]] to float**
534 // CHECK1-NEXT:    store float* [[VLA]], float** [[TMP112]], align 8
535 // CHECK1-NEXT:    [[TMP113:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS27]], i32 0, i32 3
536 // CHECK1-NEXT:    [[TMP114:%.*]] = bitcast i8** [[TMP113]] to float**
537 // CHECK1-NEXT:    store float* [[VLA]], float** [[TMP114]], align 8
538 // CHECK1-NEXT:    [[TMP115:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3
539 // CHECK1-NEXT:    store i64 [[TMP92]], i64* [[TMP115]], align 8
540 // CHECK1-NEXT:    [[TMP116:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS28]], i64 0, i64 3
541 // CHECK1-NEXT:    store i8* null, i8** [[TMP116]], align 8
542 // CHECK1-NEXT:    [[TMP117:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS26]], i32 0, i32 4
543 // CHECK1-NEXT:    [[TMP118:%.*]] = bitcast i8** [[TMP117]] to [5 x [10 x double]]**
544 // CHECK1-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP118]], align 8
545 // CHECK1-NEXT:    [[TMP119:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS27]], i32 0, i32 4
546 // CHECK1-NEXT:    [[TMP120:%.*]] = bitcast i8** [[TMP119]] to [5 x [10 x double]]**
547 // CHECK1-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP120]], align 8
548 // CHECK1-NEXT:    [[TMP121:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS28]], i64 0, i64 4
549 // CHECK1-NEXT:    store i8* null, i8** [[TMP121]], align 8
550 // CHECK1-NEXT:    [[TMP122:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS26]], i32 0, i32 5
551 // CHECK1-NEXT:    [[TMP123:%.*]] = bitcast i8** [[TMP122]] to i64*
552 // CHECK1-NEXT:    store i64 5, i64* [[TMP123]], align 8
553 // CHECK1-NEXT:    [[TMP124:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS27]], i32 0, i32 5
554 // CHECK1-NEXT:    [[TMP125:%.*]] = bitcast i8** [[TMP124]] to i64*
555 // CHECK1-NEXT:    store i64 5, i64* [[TMP125]], align 8
556 // CHECK1-NEXT:    [[TMP126:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS28]], i64 0, i64 5
557 // CHECK1-NEXT:    store i8* null, i8** [[TMP126]], align 8
558 // CHECK1-NEXT:    [[TMP127:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS26]], i32 0, i32 6
559 // CHECK1-NEXT:    [[TMP128:%.*]] = bitcast i8** [[TMP127]] to i64*
560 // CHECK1-NEXT:    store i64 [[TMP5]], i64* [[TMP128]], align 8
561 // CHECK1-NEXT:    [[TMP129:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS27]], i32 0, i32 6
562 // CHECK1-NEXT:    [[TMP130:%.*]] = bitcast i8** [[TMP129]] to i64*
563 // CHECK1-NEXT:    store i64 [[TMP5]], i64* [[TMP130]], align 8
564 // CHECK1-NEXT:    [[TMP131:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS28]], i64 0, i64 6
565 // CHECK1-NEXT:    store i8* null, i8** [[TMP131]], align 8
566 // CHECK1-NEXT:    [[TMP132:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS26]], i32 0, i32 7
567 // CHECK1-NEXT:    [[TMP133:%.*]] = bitcast i8** [[TMP132]] to double**
568 // CHECK1-NEXT:    store double* [[VLA1]], double** [[TMP133]], align 8
569 // CHECK1-NEXT:    [[TMP134:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS27]], i32 0, i32 7
570 // CHECK1-NEXT:    [[TMP135:%.*]] = bitcast i8** [[TMP134]] to double**
571 // CHECK1-NEXT:    store double* [[VLA1]], double** [[TMP135]], align 8
572 // CHECK1-NEXT:    [[TMP136:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7
573 // CHECK1-NEXT:    store i64 [[TMP94]], i64* [[TMP136]], align 8
574 // CHECK1-NEXT:    [[TMP137:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS28]], i64 0, i64 7
575 // CHECK1-NEXT:    store i8* null, i8** [[TMP137]], align 8
576 // CHECK1-NEXT:    [[TMP138:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS26]], i32 0, i32 8
577 // CHECK1-NEXT:    [[TMP139:%.*]] = bitcast i8** [[TMP138]] to %struct.TT**
578 // CHECK1-NEXT:    store %struct.TT* [[D]], %struct.TT** [[TMP139]], align 8
579 // CHECK1-NEXT:    [[TMP140:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS27]], i32 0, i32 8
580 // CHECK1-NEXT:    [[TMP141:%.*]] = bitcast i8** [[TMP140]] to %struct.TT**
581 // CHECK1-NEXT:    store %struct.TT* [[D]], %struct.TT** [[TMP141]], align 8
582 // CHECK1-NEXT:    [[TMP142:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS28]], i64 0, i64 8
583 // CHECK1-NEXT:    store i8* null, i8** [[TMP142]], align 8
584 // CHECK1-NEXT:    [[TMP143:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS26]], i32 0, i32 0
585 // CHECK1-NEXT:    [[TMP144:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS27]], i32 0, i32 0
586 // CHECK1-NEXT:    [[TMP145:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
587 // CHECK1-NEXT:    call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10)
588 // CHECK1-NEXT:    [[TMP146:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142.region_id, i32 9, i8** [[TMP143]], i8** [[TMP144]], i64* [[TMP145]], i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_maptypes.11, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1)
589 // CHECK1-NEXT:    [[TMP147:%.*]] = icmp ne i32 [[TMP146]], 0
590 // CHECK1-NEXT:    br i1 [[TMP147]], label [[OMP_OFFLOAD_FAILED30:%.*]], label [[OMP_OFFLOAD_CONT31:%.*]]
591 // CHECK1:       omp_offload.failed30:
592 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i64 [[TMP90]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR4]]
593 // CHECK1-NEXT:    br label [[OMP_OFFLOAD_CONT31]]
594 // CHECK1:       omp_offload.cont31:
595 // CHECK1-NEXT:    br label [[OMP_IF_END33:%.*]]
596 // CHECK1:       omp_if.else32:
597 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i64 [[TMP90]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR4]]
598 // CHECK1-NEXT:    br label [[OMP_IF_END33]]
599 // CHECK1:       omp_if.end33:
600 // CHECK1-NEXT:    [[TMP148:%.*]] = load i32, i32* [[A]], align 4
601 // CHECK1-NEXT:    [[TMP149:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
602 // CHECK1-NEXT:    call void @llvm.stackrestore(i8* [[TMP149]])
603 // CHECK1-NEXT:    ret i32 [[TMP148]]
604 //
605 //
606 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97
607 // CHECK1-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] {
608 // CHECK1-NEXT:  entry:
609 // CHECK1-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
610 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
611 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8
612 // CHECK1-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
613 // CHECK1-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]])
614 // CHECK1-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
615 // CHECK1-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
616 // CHECK1-NEXT:    store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8
617 // CHECK1-NEXT:    [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
618 // CHECK1-NEXT:    [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
619 // CHECK1-NEXT:    [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32*
620 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 4
621 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 4
622 // CHECK1-NEXT:    call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
623 // CHECK1-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
624 // CHECK1-NEXT:    [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
625 // CHECK1-NEXT:    store i16 [[TMP3]], i16* [[CONV5]], align 2
626 // CHECK1-NEXT:    [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
627 // CHECK1-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]])
628 // CHECK1-NEXT:    ret void
629 //
630 //
631 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined.
632 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR3:[0-9]+]] {
633 // CHECK1-NEXT:  entry:
634 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
635 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
636 // CHECK1-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
637 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
638 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
639 // CHECK1-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
640 // CHECK1-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
641 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
642 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
643 // CHECK1-NEXT:    [[I:%.*]] = alloca i32, align 4
644 // CHECK1-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
645 // CHECK1-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
646 // CHECK1-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
647 // CHECK1-NEXT:    [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
648 // CHECK1-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
649 // CHECK1-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
650 // CHECK1-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
651 // CHECK1-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
652 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
653 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
654 // CHECK1-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
655 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
656 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
657 // CHECK1-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
658 // CHECK1:       cond.true:
659 // CHECK1-NEXT:    br label [[COND_END:%.*]]
660 // CHECK1:       cond.false:
661 // CHECK1-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
662 // CHECK1-NEXT:    br label [[COND_END]]
663 // CHECK1:       cond.end:
664 // CHECK1-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
665 // CHECK1-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
666 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
667 // CHECK1-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
668 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
669 // CHECK1:       omp.inner.for.cond:
670 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
671 // CHECK1-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !10
672 // CHECK1-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
673 // CHECK1-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
674 // CHECK1:       omp.inner.for.body:
675 // CHECK1-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
676 // CHECK1-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
677 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
678 // CHECK1-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10
679 // CHECK1-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
680 // CHECK1:       omp.body.continue:
681 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
682 // CHECK1:       omp.inner.for.inc:
683 // CHECK1-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
684 // CHECK1-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
685 // CHECK1-NEXT:    store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
686 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]
687 // CHECK1:       omp.inner.for.end:
688 // CHECK1-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
689 // CHECK1:       omp.loop.exit:
690 // CHECK1-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
691 // CHECK1-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
692 // CHECK1-NEXT:    [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0
693 // CHECK1-NEXT:    br i1 [[TMP10]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
694 // CHECK1:       .omp.final.then:
695 // CHECK1-NEXT:    store i32 10, i32* [[I]], align 4
696 // CHECK1-NEXT:    br label [[DOTOMP_FINAL_DONE]]
697 // CHECK1:       .omp.final.done:
698 // CHECK1-NEXT:    ret void
699 //
700 //
701 // CHECK1-LABEL: define {{[^@]+}}@.omp_task_privates_map.
702 // CHECK1-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], i16** noalias noundef [[TMP1:%.*]], [3 x i8*]** noalias noundef [[TMP2:%.*]], [3 x i8*]** noalias noundef [[TMP3:%.*]], [3 x i64]** noalias noundef [[TMP4:%.*]]) #[[ATTR5:[0-9]+]] {
703 // CHECK1-NEXT:  entry:
704 // CHECK1-NEXT:    [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 8
705 // CHECK1-NEXT:    [[DOTADDR1:%.*]] = alloca i16**, align 8
706 // CHECK1-NEXT:    [[DOTADDR2:%.*]] = alloca [3 x i8*]**, align 8
707 // CHECK1-NEXT:    [[DOTADDR3:%.*]] = alloca [3 x i8*]**, align 8
708 // CHECK1-NEXT:    [[DOTADDR4:%.*]] = alloca [3 x i64]**, align 8
709 // CHECK1-NEXT:    store %struct..kmp_privates.t* [[TMP0]], %struct..kmp_privates.t** [[DOTADDR]], align 8
710 // CHECK1-NEXT:    store i16** [[TMP1]], i16*** [[DOTADDR1]], align 8
711 // CHECK1-NEXT:    store [3 x i8*]** [[TMP2]], [3 x i8*]*** [[DOTADDR2]], align 8
712 // CHECK1-NEXT:    store [3 x i8*]** [[TMP3]], [3 x i8*]*** [[DOTADDR3]], align 8
713 // CHECK1-NEXT:    store [3 x i64]** [[TMP4]], [3 x i64]*** [[DOTADDR4]], align 8
714 // CHECK1-NEXT:    [[TMP5:%.*]] = load %struct..kmp_privates.t*, %struct..kmp_privates.t** [[DOTADDR]], align 8
715 // CHECK1-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 0
716 // CHECK1-NEXT:    [[TMP7:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR2]], align 8
717 // CHECK1-NEXT:    store [3 x i8*]* [[TMP6]], [3 x i8*]** [[TMP7]], align 8
718 // CHECK1-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 1
719 // CHECK1-NEXT:    [[TMP9:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR3]], align 8
720 // CHECK1-NEXT:    store [3 x i8*]* [[TMP8]], [3 x i8*]** [[TMP9]], align 8
721 // CHECK1-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 2
722 // CHECK1-NEXT:    [[TMP11:%.*]] = load [3 x i64]**, [3 x i64]*** [[DOTADDR4]], align 8
723 // CHECK1-NEXT:    store [3 x i64]* [[TMP10]], [3 x i64]** [[TMP11]], align 8
724 // CHECK1-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 3
725 // CHECK1-NEXT:    [[TMP13:%.*]] = load i16**, i16*** [[DOTADDR1]], align 8
726 // CHECK1-NEXT:    store i16* [[TMP12]], i16** [[TMP13]], align 8
727 // CHECK1-NEXT:    ret void
728 //
729 //
730 // CHECK1-LABEL: define {{[^@]+}}@.omp_task_entry.
731 // CHECK1-SAME: (i32 noundef signext [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] {
732 // CHECK1-NEXT:  entry:
733 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
734 // CHECK1-NEXT:    [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8
735 // CHECK1-NEXT:    [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8
736 // CHECK1-NEXT:    [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8
737 // CHECK1-NEXT:    [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8
738 // CHECK1-NEXT:    [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 8
739 // CHECK1-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca i16*, align 8
740 // CHECK1-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca [3 x i8*]*, align 8
741 // CHECK1-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca [3 x i8*]*, align 8
742 // CHECK1-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca [3 x i64]*, align 8
743 // CHECK1-NEXT:    [[AA_CASTED_I:%.*]] = alloca i64, align 8
744 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR__CASTED_I:%.*]] = alloca i64, align 8
745 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR__CASTED5_I:%.*]] = alloca i64, align 8
746 // CHECK1-NEXT:    [[DOTADDR:%.*]] = alloca i32, align 4
747 // CHECK1-NEXT:    [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8
748 // CHECK1-NEXT:    store i32 [[TMP0]], i32* [[DOTADDR]], align 4
749 // CHECK1-NEXT:    store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8
750 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4
751 // CHECK1-NEXT:    [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8
752 // CHECK1-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
753 // CHECK1-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
754 // CHECK1-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0
755 // CHECK1-NEXT:    [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8
756 // CHECK1-NEXT:    [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon*
757 // CHECK1-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1
758 // CHECK1-NEXT:    [[TMP10:%.*]] = bitcast %struct..kmp_privates.t* [[TMP9]] to i8*
759 // CHECK1-NEXT:    [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8*
760 // CHECK1-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META17:![0-9]+]])
761 // CHECK1-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]])
762 // CHECK1-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META22:![0-9]+]])
763 // CHECK1-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META24:![0-9]+]])
764 // CHECK1-NEXT:    store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !26
765 // CHECK1-NEXT:    store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !26
766 // CHECK1-NEXT:    store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !26
767 // CHECK1-NEXT:    store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* @.omp_task_privates_map. to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !26
768 // CHECK1-NEXT:    store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !26
769 // CHECK1-NEXT:    store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !26
770 // CHECK1-NEXT:    [[TMP12:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !26
771 // CHECK1-NEXT:    [[TMP13:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !26
772 // CHECK1-NEXT:    [[TMP14:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !26
773 // CHECK1-NEXT:    [[TMP15:%.*]] = bitcast void (i8*, ...)* [[TMP13]] to void (i8*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)*
774 // CHECK1-NEXT:    call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR4]]
775 // CHECK1-NEXT:    [[TMP16:%.*]] = load i16*, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !26
776 // CHECK1-NEXT:    [[TMP17:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !26
777 // CHECK1-NEXT:    [[TMP18:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 8, !noalias !26
778 // CHECK1-NEXT:    [[TMP19:%.*]] = load [3 x i64]*, [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 8, !noalias !26
779 // CHECK1-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP17]], i64 0, i64 0
780 // CHECK1-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP18]], i64 0, i64 0
781 // CHECK1-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[TMP19]], i64 0, i64 0
782 // CHECK1-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP12]], i32 0, i32 1
783 // CHECK1-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[TMP12]], i32 0, i32 2
784 // CHECK1-NEXT:    [[TMP25:%.*]] = load i32, i32* [[TMP23]], align 4
785 // CHECK1-NEXT:    call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) #[[ATTR4]]
786 // CHECK1-NEXT:    [[TMP26:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 [[TMP25]], i32 1, i32 0, i8* null, i32 0, i8* null) #[[ATTR4]]
787 // CHECK1-NEXT:    [[TMP27:%.*]] = icmp ne i32 [[TMP26]], 0
788 // CHECK1-NEXT:    br i1 [[TMP27]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]]
789 // CHECK1:       omp_offload.failed.i:
790 // CHECK1-NEXT:    [[TMP28:%.*]] = load i16, i16* [[TMP16]], align 2
791 // CHECK1-NEXT:    [[CONV_I:%.*]] = bitcast i64* [[AA_CASTED_I]] to i16*
792 // CHECK1-NEXT:    store i16 [[TMP28]], i16* [[CONV_I]], align 2, !noalias !26
793 // CHECK1-NEXT:    [[TMP29:%.*]] = load i64, i64* [[AA_CASTED_I]], align 8, !noalias !26
794 // CHECK1-NEXT:    [[TMP30:%.*]] = load i32, i32* [[TMP23]], align 4
795 // CHECK1-NEXT:    [[CONV4_I:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED_I]] to i32*
796 // CHECK1-NEXT:    store i32 [[TMP30]], i32* [[CONV4_I]], align 4, !noalias !26
797 // CHECK1-NEXT:    [[TMP31:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED_I]], align 8, !noalias !26
798 // CHECK1-NEXT:    [[TMP32:%.*]] = load i32, i32* [[TMP24]], align 4
799 // CHECK1-NEXT:    [[CONV6_I:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED5_I]] to i32*
800 // CHECK1-NEXT:    store i32 [[TMP32]], i32* [[CONV6_I]], align 4, !noalias !26
801 // CHECK1-NEXT:    [[TMP33:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED5_I]], align 8, !noalias !26
802 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97(i64 [[TMP29]], i64 [[TMP31]], i64 [[TMP33]]) #[[ATTR4]]
803 // CHECK1-NEXT:    br label [[DOTOMP_OUTLINED__1_EXIT]]
804 // CHECK1:       .omp_outlined..1.exit:
805 // CHECK1-NEXT:    ret i32 0
806 //
807 //
808 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104
809 // CHECK1-SAME: (i64 noundef [[A:%.*]]) #[[ATTR3]] {
810 // CHECK1-NEXT:  entry:
811 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
812 // CHECK1-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
813 // CHECK1-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
814 // CHECK1-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
815 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
816 // CHECK1-NEXT:    [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32*
817 // CHECK1-NEXT:    store i32 [[TMP0]], i32* [[CONV1]], align 4
818 // CHECK1-NEXT:    [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
819 // CHECK1-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]])
820 // CHECK1-NEXT:    ret void
821 //
822 //
823 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..2
824 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]]) #[[ATTR3]] {
825 // CHECK1-NEXT:  entry:
826 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
827 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
828 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
829 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
830 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
831 // CHECK1-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
832 // CHECK1-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
833 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
834 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
835 // CHECK1-NEXT:    [[A1:%.*]] = alloca i32, align 4
836 // CHECK1-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
837 // CHECK1-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
838 // CHECK1-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
839 // CHECK1-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
840 // CHECK1-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
841 // CHECK1-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
842 // CHECK1-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
843 // CHECK1-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
844 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
845 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
846 // CHECK1-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
847 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
848 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
849 // CHECK1-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
850 // CHECK1:       cond.true:
851 // CHECK1-NEXT:    br label [[COND_END:%.*]]
852 // CHECK1:       cond.false:
853 // CHECK1-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
854 // CHECK1-NEXT:    br label [[COND_END]]
855 // CHECK1:       cond.end:
856 // CHECK1-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
857 // CHECK1-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
858 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
859 // CHECK1-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
860 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
861 // CHECK1:       omp.inner.for.cond:
862 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
863 // CHECK1-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
864 // CHECK1-NEXT:    [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
865 // CHECK1-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
866 // CHECK1:       omp.inner.for.body:
867 // CHECK1-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
868 // CHECK1-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
869 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
870 // CHECK1-NEXT:    store i32 [[ADD]], i32* [[A1]], align 4
871 // CHECK1-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A1]], align 4
872 // CHECK1-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
873 // CHECK1-NEXT:    store i32 [[ADD3]], i32* [[A1]], align 4
874 // CHECK1-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
875 // CHECK1:       omp.body.continue:
876 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
877 // CHECK1:       omp.inner.for.inc:
878 // CHECK1-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
879 // CHECK1-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP9]], 1
880 // CHECK1-NEXT:    store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4
881 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP27:![0-9]+]]
882 // CHECK1:       omp.inner.for.end:
883 // CHECK1-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
884 // CHECK1:       omp.loop.exit:
885 // CHECK1-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
886 // CHECK1-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
887 // CHECK1-NEXT:    [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0
888 // CHECK1-NEXT:    br i1 [[TMP11]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
889 // CHECK1:       .omp.final.then:
890 // CHECK1-NEXT:    store i32 10, i32* [[CONV]], align 4
891 // CHECK1-NEXT:    br label [[DOTOMP_FINAL_DONE]]
892 // CHECK1:       .omp.final.done:
893 // CHECK1-NEXT:    ret void
894 //
895 //
896 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111
897 // CHECK1-SAME: (i64 noundef [[AA:%.*]]) #[[ATTR2]] {
898 // CHECK1-NEXT:  entry:
899 // CHECK1-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
900 // CHECK1-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
901 // CHECK1-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
902 // CHECK1-NEXT:    [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
903 // CHECK1-NEXT:    [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
904 // CHECK1-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
905 // CHECK1-NEXT:    store i16 [[TMP0]], i16* [[CONV1]], align 2
906 // CHECK1-NEXT:    [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
907 // CHECK1-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP1]])
908 // CHECK1-NEXT:    ret void
909 //
910 //
911 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..3
912 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR3]] {
913 // CHECK1-NEXT:  entry:
914 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
915 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
916 // CHECK1-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
917 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
918 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
919 // CHECK1-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
920 // CHECK1-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
921 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
922 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
923 // CHECK1-NEXT:    [[I:%.*]] = alloca i32, align 4
924 // CHECK1-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
925 // CHECK1-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
926 // CHECK1-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
927 // CHECK1-NEXT:    [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
928 // CHECK1-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
929 // CHECK1-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
930 // CHECK1-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
931 // CHECK1-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
932 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
933 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
934 // CHECK1-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
935 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
936 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
937 // CHECK1-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
938 // CHECK1:       cond.true:
939 // CHECK1-NEXT:    br label [[COND_END:%.*]]
940 // CHECK1:       cond.false:
941 // CHECK1-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
942 // CHECK1-NEXT:    br label [[COND_END]]
943 // CHECK1:       cond.end:
944 // CHECK1-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
945 // CHECK1-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
946 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
947 // CHECK1-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
948 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
949 // CHECK1:       omp.inner.for.cond:
950 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !29
951 // CHECK1-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !29
952 // CHECK1-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
953 // CHECK1-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
954 // CHECK1:       omp.inner.for.body:
955 // CHECK1-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !29
956 // CHECK1-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
957 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
958 // CHECK1-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !29
959 // CHECK1-NEXT:    [[TMP8:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !29
960 // CHECK1-NEXT:    [[CONV2:%.*]] = sext i16 [[TMP8]] to i32
961 // CHECK1-NEXT:    [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
962 // CHECK1-NEXT:    [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
963 // CHECK1-NEXT:    store i16 [[CONV4]], i16* [[CONV]], align 2, !llvm.access.group !29
964 // CHECK1-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
965 // CHECK1:       omp.body.continue:
966 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
967 // CHECK1:       omp.inner.for.inc:
968 // CHECK1-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !29
969 // CHECK1-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP9]], 1
970 // CHECK1-NEXT:    store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !29
971 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP30:![0-9]+]]
972 // CHECK1:       omp.inner.for.end:
973 // CHECK1-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
974 // CHECK1:       omp.loop.exit:
975 // CHECK1-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
976 // CHECK1-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
977 // CHECK1-NEXT:    [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0
978 // CHECK1-NEXT:    br i1 [[TMP11]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
979 // CHECK1:       .omp.final.then:
980 // CHECK1-NEXT:    store i32 10, i32* [[I]], align 4
981 // CHECK1-NEXT:    br label [[DOTOMP_FINAL_DONE]]
982 // CHECK1:       .omp.final.done:
983 // CHECK1-NEXT:    ret void
984 //
985 //
986 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118
987 // CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] {
988 // CHECK1-NEXT:  entry:
989 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
990 // CHECK1-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
991 // CHECK1-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
992 // CHECK1-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
993 // CHECK1-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
994 // CHECK1-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
995 // CHECK1-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
996 // CHECK1-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
997 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
998 // CHECK1-NEXT:    [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
999 // CHECK1-NEXT:    store i32 [[TMP0]], i32* [[CONV2]], align 4
1000 // CHECK1-NEXT:    [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
1001 // CHECK1-NEXT:    [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
1002 // CHECK1-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
1003 // CHECK1-NEXT:    store i16 [[TMP2]], i16* [[CONV3]], align 2
1004 // CHECK1-NEXT:    [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
1005 // CHECK1-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
1006 // CHECK1-NEXT:    ret void
1007 //
1008 //
1009 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..6
1010 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR3]] {
1011 // CHECK1-NEXT:  entry:
1012 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
1013 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
1014 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
1015 // CHECK1-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
1016 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
1017 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
1018 // CHECK1-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
1019 // CHECK1-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
1020 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1021 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1022 // CHECK1-NEXT:    [[I:%.*]] = alloca i32, align 4
1023 // CHECK1-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
1024 // CHECK1-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
1025 // CHECK1-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
1026 // CHECK1-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
1027 // CHECK1-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
1028 // CHECK1-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
1029 // CHECK1-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
1030 // CHECK1-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
1031 // CHECK1-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
1032 // CHECK1-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
1033 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
1034 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
1035 // CHECK1-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
1036 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1037 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
1038 // CHECK1-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1039 // CHECK1:       cond.true:
1040 // CHECK1-NEXT:    br label [[COND_END:%.*]]
1041 // CHECK1:       cond.false:
1042 // CHECK1-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1043 // CHECK1-NEXT:    br label [[COND_END]]
1044 // CHECK1:       cond.end:
1045 // CHECK1-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
1046 // CHECK1-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
1047 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
1048 // CHECK1-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
1049 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
1050 // CHECK1:       omp.inner.for.cond:
1051 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !32
1052 // CHECK1-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !32
1053 // CHECK1-NEXT:    [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
1054 // CHECK1-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1055 // CHECK1:       omp.inner.for.body:
1056 // CHECK1-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !32
1057 // CHECK1-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
1058 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1059 // CHECK1-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !32
1060 // CHECK1-NEXT:    [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !32
1061 // CHECK1-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
1062 // CHECK1-NEXT:    store i32 [[ADD3]], i32* [[CONV]], align 4, !llvm.access.group !32
1063 // CHECK1-NEXT:    [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 2, !llvm.access.group !32
1064 // CHECK1-NEXT:    [[CONV4:%.*]] = sext i16 [[TMP9]] to i32
1065 // CHECK1-NEXT:    [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
1066 // CHECK1-NEXT:    [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
1067 // CHECK1-NEXT:    store i16 [[CONV6]], i16* [[CONV1]], align 2, !llvm.access.group !32
1068 // CHECK1-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
1069 // CHECK1:       omp.body.continue:
1070 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
1071 // CHECK1:       omp.inner.for.inc:
1072 // CHECK1-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !32
1073 // CHECK1-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1
1074 // CHECK1-NEXT:    store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !32
1075 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP33:![0-9]+]]
1076 // CHECK1:       omp.inner.for.end:
1077 // CHECK1-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
1078 // CHECK1:       omp.loop.exit:
1079 // CHECK1-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
1080 // CHECK1-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
1081 // CHECK1-NEXT:    [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
1082 // CHECK1-NEXT:    br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
1083 // CHECK1:       .omp.final.then:
1084 // CHECK1-NEXT:    store i32 10, i32* [[I]], align 4
1085 // CHECK1-NEXT:    br label [[DOTOMP_FINAL_DONE]]
1086 // CHECK1:       .omp.final.done:
1087 // CHECK1-NEXT:    ret void
1088 //
1089 //
1090 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142
1091 // CHECK1-SAME: (i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] {
1092 // CHECK1-NEXT:  entry:
1093 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
1094 // CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
1095 // CHECK1-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
1096 // CHECK1-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 8
1097 // CHECK1-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
1098 // CHECK1-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
1099 // CHECK1-NEXT:    [[VLA_ADDR4:%.*]] = alloca i64, align 8
1100 // CHECK1-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 8
1101 // CHECK1-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
1102 // CHECK1-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
1103 // CHECK1-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
1104 // CHECK1-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
1105 // CHECK1-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
1106 // CHECK1-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 8
1107 // CHECK1-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
1108 // CHECK1-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
1109 // CHECK1-NEXT:    store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
1110 // CHECK1-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 8
1111 // CHECK1-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
1112 // CHECK1-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
1113 // CHECK1-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
1114 // CHECK1-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
1115 // CHECK1-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
1116 // CHECK1-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
1117 // CHECK1-NEXT:    [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
1118 // CHECK1-NEXT:    [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
1119 // CHECK1-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
1120 // CHECK1-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
1121 // CHECK1-NEXT:    [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
1122 // CHECK1-NEXT:    [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
1123 // CHECK1-NEXT:    store i32 [[TMP8]], i32* [[CONV5]], align 4
1124 // CHECK1-NEXT:    [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
1125 // CHECK1-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]])
1126 // CHECK1-NEXT:    ret void
1127 //
1128 //
1129 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..9
1130 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR3]] {
1131 // CHECK1-NEXT:  entry:
1132 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
1133 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
1134 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
1135 // CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
1136 // CHECK1-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
1137 // CHECK1-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 8
1138 // CHECK1-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
1139 // CHECK1-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
1140 // CHECK1-NEXT:    [[VLA_ADDR4:%.*]] = alloca i64, align 8
1141 // CHECK1-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 8
1142 // CHECK1-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
1143 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
1144 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
1145 // CHECK1-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
1146 // CHECK1-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
1147 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1148 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1149 // CHECK1-NEXT:    [[I:%.*]] = alloca i32, align 4
1150 // CHECK1-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
1151 // CHECK1-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
1152 // CHECK1-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
1153 // CHECK1-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
1154 // CHECK1-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
1155 // CHECK1-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 8
1156 // CHECK1-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
1157 // CHECK1-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
1158 // CHECK1-NEXT:    store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
1159 // CHECK1-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 8
1160 // CHECK1-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
1161 // CHECK1-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
1162 // CHECK1-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
1163 // CHECK1-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
1164 // CHECK1-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
1165 // CHECK1-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
1166 // CHECK1-NEXT:    [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
1167 // CHECK1-NEXT:    [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
1168 // CHECK1-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
1169 // CHECK1-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
1170 // CHECK1-NEXT:    [[ARRAYDECAY:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 0
1171 // CHECK1-NEXT:    call void @llvm.assume(i1 true) [ "align"(float* [[ARRAYDECAY]], i64 16) ]
1172 // CHECK1-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
1173 // CHECK1-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
1174 // CHECK1-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
1175 // CHECK1-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
1176 // CHECK1-NEXT:    [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
1177 // CHECK1-NEXT:    [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4
1178 // CHECK1-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
1179 // CHECK1-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1180 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP10]], 9
1181 // CHECK1-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1182 // CHECK1:       cond.true:
1183 // CHECK1-NEXT:    br label [[COND_END:%.*]]
1184 // CHECK1:       cond.false:
1185 // CHECK1-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1186 // CHECK1-NEXT:    br label [[COND_END]]
1187 // CHECK1:       cond.end:
1188 // CHECK1-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ]
1189 // CHECK1-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
1190 // CHECK1-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
1191 // CHECK1-NEXT:    store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4
1192 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
1193 // CHECK1:       omp.inner.for.cond:
1194 // CHECK1-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !35
1195 // CHECK1-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !35
1196 // CHECK1-NEXT:    [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
1197 // CHECK1-NEXT:    br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1198 // CHECK1:       omp.inner.for.body:
1199 // CHECK1-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !35
1200 // CHECK1-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1
1201 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1202 // CHECK1-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !35
1203 // CHECK1-NEXT:    [[TMP16:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !35
1204 // CHECK1-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP16]], 1
1205 // CHECK1-NEXT:    store i32 [[ADD6]], i32* [[CONV]], align 4, !llvm.access.group !35
1206 // CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
1207 // CHECK1-NEXT:    [[TMP17:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !35
1208 // CHECK1-NEXT:    [[CONV7:%.*]] = fpext float [[TMP17]] to double
1209 // CHECK1-NEXT:    [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00
1210 // CHECK1-NEXT:    [[CONV9:%.*]] = fptrunc double [[ADD8]] to float
1211 // CHECK1-NEXT:    store float [[CONV9]], float* [[ARRAYIDX]], align 4, !llvm.access.group !35
1212 // CHECK1-NEXT:    [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3
1213 // CHECK1-NEXT:    [[TMP18:%.*]] = load float, float* [[ARRAYIDX10]], align 4, !llvm.access.group !35
1214 // CHECK1-NEXT:    [[CONV11:%.*]] = fpext float [[TMP18]] to double
1215 // CHECK1-NEXT:    [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00
1216 // CHECK1-NEXT:    [[CONV13:%.*]] = fptrunc double [[ADD12]] to float
1217 // CHECK1-NEXT:    store float [[CONV13]], float* [[ARRAYIDX10]], align 4, !llvm.access.group !35
1218 // CHECK1-NEXT:    [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1
1219 // CHECK1-NEXT:    [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX14]], i64 0, i64 2
1220 // CHECK1-NEXT:    [[TMP19:%.*]] = load double, double* [[ARRAYIDX15]], align 8, !llvm.access.group !35
1221 // CHECK1-NEXT:    [[ADD16:%.*]] = fadd double [[TMP19]], 1.000000e+00
1222 // CHECK1-NEXT:    store double [[ADD16]], double* [[ARRAYIDX15]], align 8, !llvm.access.group !35
1223 // CHECK1-NEXT:    [[TMP20:%.*]] = mul nsw i64 1, [[TMP5]]
1224 // CHECK1-NEXT:    [[ARRAYIDX17:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP20]]
1225 // CHECK1-NEXT:    [[ARRAYIDX18:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX17]], i64 3
1226 // CHECK1-NEXT:    [[TMP21:%.*]] = load double, double* [[ARRAYIDX18]], align 8, !llvm.access.group !35
1227 // CHECK1-NEXT:    [[ADD19:%.*]] = fadd double [[TMP21]], 1.000000e+00
1228 // CHECK1-NEXT:    store double [[ADD19]], double* [[ARRAYIDX18]], align 8, !llvm.access.group !35
1229 // CHECK1-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0
1230 // CHECK1-NEXT:    [[TMP22:%.*]] = load i64, i64* [[X]], align 8, !llvm.access.group !35
1231 // CHECK1-NEXT:    [[ADD20:%.*]] = add nsw i64 [[TMP22]], 1
1232 // CHECK1-NEXT:    store i64 [[ADD20]], i64* [[X]], align 8, !llvm.access.group !35
1233 // CHECK1-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1
1234 // CHECK1-NEXT:    [[TMP23:%.*]] = load i8, i8* [[Y]], align 8, !llvm.access.group !35
1235 // CHECK1-NEXT:    [[CONV21:%.*]] = sext i8 [[TMP23]] to i32
1236 // CHECK1-NEXT:    [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1
1237 // CHECK1-NEXT:    [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8
1238 // CHECK1-NEXT:    store i8 [[CONV23]], i8* [[Y]], align 8, !llvm.access.group !35
1239 // CHECK1-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
1240 // CHECK1:       omp.body.continue:
1241 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
1242 // CHECK1:       omp.inner.for.inc:
1243 // CHECK1-NEXT:    [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !35
1244 // CHECK1-NEXT:    [[ADD24:%.*]] = add nsw i32 [[TMP24]], 1
1245 // CHECK1-NEXT:    store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !35
1246 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP36:![0-9]+]]
1247 // CHECK1:       omp.inner.for.end:
1248 // CHECK1-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
1249 // CHECK1:       omp.loop.exit:
1250 // CHECK1-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]])
1251 // CHECK1-NEXT:    [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
1252 // CHECK1-NEXT:    [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
1253 // CHECK1-NEXT:    br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
1254 // CHECK1:       .omp.final.then:
1255 // CHECK1-NEXT:    store i32 10, i32* [[I]], align 4
1256 // CHECK1-NEXT:    br label [[DOTOMP_FINAL_DONE]]
1257 // CHECK1:       .omp.final.done:
1258 // CHECK1-NEXT:    ret void
1259 //
1260 //
1261 // CHECK1-LABEL: define {{[^@]+}}@_Z3bari
1262 // CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {
1263 // CHECK1-NEXT:  entry:
1264 // CHECK1-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
1265 // CHECK1-NEXT:    [[A:%.*]] = alloca i32, align 4
1266 // CHECK1-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8
1267 // CHECK1-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
1268 // CHECK1-NEXT:    store i32 0, i32* [[A]], align 4
1269 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
1270 // CHECK1-NEXT:    [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]])
1271 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
1272 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
1273 // CHECK1-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
1274 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
1275 // CHECK1-NEXT:    [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP2]])
1276 // CHECK1-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
1277 // CHECK1-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
1278 // CHECK1-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
1279 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
1280 // CHECK1-NEXT:    [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]])
1281 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
1282 // CHECK1-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
1283 // CHECK1-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
1284 // CHECK1-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
1285 // CHECK1-NEXT:    [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]])
1286 // CHECK1-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
1287 // CHECK1-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
1288 // CHECK1-NEXT:    store i32 [[ADD6]], i32* [[A]], align 4
1289 // CHECK1-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
1290 // CHECK1-NEXT:    ret i32 [[TMP8]]
1291 //
1292 //
1293 // CHECK1-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
1294 // CHECK1-SAME: (%struct.S1* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 {
1295 // CHECK1-NEXT:  entry:
1296 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
1297 // CHECK1-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
1298 // CHECK1-NEXT:    [[B:%.*]] = alloca i32, align 4
1299 // CHECK1-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 8
1300 // CHECK1-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
1301 // CHECK1-NEXT:    [[B_CASTED:%.*]] = alloca i64, align 8
1302 // CHECK1-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8
1303 // CHECK1-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8
1304 // CHECK1-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8
1305 // CHECK1-NEXT:    [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 8
1306 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
1307 // CHECK1-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
1308 // CHECK1-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
1309 // CHECK1-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
1310 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
1311 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
1312 // CHECK1-NEXT:    store i32 [[ADD]], i32* [[B]], align 4
1313 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
1314 // CHECK1-NEXT:    [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
1315 // CHECK1-NEXT:    [[TMP3:%.*]] = call i8* @llvm.stacksave()
1316 // CHECK1-NEXT:    store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8
1317 // CHECK1-NEXT:    [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]
1318 // CHECK1-NEXT:    [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2
1319 // CHECK1-NEXT:    store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8
1320 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, i32* [[B]], align 4
1321 // CHECK1-NEXT:    [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32*
1322 // CHECK1-NEXT:    store i32 [[TMP5]], i32* [[CONV]], align 4
1323 // CHECK1-NEXT:    [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8
1324 // CHECK1-NEXT:    [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4
1325 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 60
1326 // CHECK1-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
1327 // CHECK1:       omp_if.then:
1328 // CHECK1-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
1329 // CHECK1-NEXT:    [[TMP8:%.*]] = mul nuw i64 2, [[TMP2]]
1330 // CHECK1-NEXT:    [[TMP9:%.*]] = mul nuw i64 [[TMP8]], 2
1331 // CHECK1-NEXT:    [[TMP10:%.*]] = bitcast [5 x i64]* [[DOTOFFLOAD_SIZES]] to i8*
1332 // CHECK1-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP10]], i8* align 8 bitcast ([5 x i64]* @.offload_sizes.13 to i8*), i64 40, i1 false)
1333 // CHECK1-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1334 // CHECK1-NEXT:    [[TMP12:%.*]] = bitcast i8** [[TMP11]] to %struct.S1**
1335 // CHECK1-NEXT:    store %struct.S1* [[THIS1]], %struct.S1** [[TMP12]], align 8
1336 // CHECK1-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1337 // CHECK1-NEXT:    [[TMP14:%.*]] = bitcast i8** [[TMP13]] to double**
1338 // CHECK1-NEXT:    store double* [[A]], double** [[TMP14]], align 8
1339 // CHECK1-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
1340 // CHECK1-NEXT:    store i8* null, i8** [[TMP15]], align 8
1341 // CHECK1-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
1342 // CHECK1-NEXT:    [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64*
1343 // CHECK1-NEXT:    store i64 [[TMP6]], i64* [[TMP17]], align 8
1344 // CHECK1-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
1345 // CHECK1-NEXT:    [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64*
1346 // CHECK1-NEXT:    store i64 [[TMP6]], i64* [[TMP19]], align 8
1347 // CHECK1-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
1348 // CHECK1-NEXT:    store i8* null, i8** [[TMP20]], align 8
1349 // CHECK1-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
1350 // CHECK1-NEXT:    [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i64*
1351 // CHECK1-NEXT:    store i64 2, i64* [[TMP22]], align 8
1352 // CHECK1-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
1353 // CHECK1-NEXT:    [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i64*
1354 // CHECK1-NEXT:    store i64 2, i64* [[TMP24]], align 8
1355 // CHECK1-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
1356 // CHECK1-NEXT:    store i8* null, i8** [[TMP25]], align 8
1357 // CHECK1-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
1358 // CHECK1-NEXT:    [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64*
1359 // CHECK1-NEXT:    store i64 [[TMP2]], i64* [[TMP27]], align 8
1360 // CHECK1-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
1361 // CHECK1-NEXT:    [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i64*
1362 // CHECK1-NEXT:    store i64 [[TMP2]], i64* [[TMP29]], align 8
1363 // CHECK1-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
1364 // CHECK1-NEXT:    store i8* null, i8** [[TMP30]], align 8
1365 // CHECK1-NEXT:    [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
1366 // CHECK1-NEXT:    [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i16**
1367 // CHECK1-NEXT:    store i16* [[VLA]], i16** [[TMP32]], align 8
1368 // CHECK1-NEXT:    [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
1369 // CHECK1-NEXT:    [[TMP34:%.*]] = bitcast i8** [[TMP33]] to i16**
1370 // CHECK1-NEXT:    store i16* [[VLA]], i16** [[TMP34]], align 8
1371 // CHECK1-NEXT:    [[TMP35:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4
1372 // CHECK1-NEXT:    store i64 [[TMP9]], i64* [[TMP35]], align 8
1373 // CHECK1-NEXT:    [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4
1374 // CHECK1-NEXT:    store i8* null, i8** [[TMP36]], align 8
1375 // CHECK1-NEXT:    [[TMP37:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1376 // CHECK1-NEXT:    [[TMP38:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1377 // CHECK1-NEXT:    [[TMP39:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
1378 // CHECK1-NEXT:    call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10)
1379 // CHECK1-NEXT:    [[TMP40:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215.region_id, i32 5, i8** [[TMP37]], i8** [[TMP38]], i64* [[TMP39]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.14, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1)
1380 // CHECK1-NEXT:    [[TMP41:%.*]] = icmp ne i32 [[TMP40]], 0
1381 // CHECK1-NEXT:    br i1 [[TMP41]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
1382 // CHECK1:       omp_offload.failed:
1383 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR4]]
1384 // CHECK1-NEXT:    br label [[OMP_OFFLOAD_CONT]]
1385 // CHECK1:       omp_offload.cont:
1386 // CHECK1-NEXT:    br label [[OMP_IF_END:%.*]]
1387 // CHECK1:       omp_if.else:
1388 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR4]]
1389 // CHECK1-NEXT:    br label [[OMP_IF_END]]
1390 // CHECK1:       omp_if.end:
1391 // CHECK1-NEXT:    [[TMP42:%.*]] = mul nsw i64 1, [[TMP2]]
1392 // CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP42]]
1393 // CHECK1-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
1394 // CHECK1-NEXT:    [[TMP43:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2
1395 // CHECK1-NEXT:    [[CONV3:%.*]] = sext i16 [[TMP43]] to i32
1396 // CHECK1-NEXT:    [[TMP44:%.*]] = load i32, i32* [[B]], align 4
1397 // CHECK1-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], [[TMP44]]
1398 // CHECK1-NEXT:    [[TMP45:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
1399 // CHECK1-NEXT:    call void @llvm.stackrestore(i8* [[TMP45]])
1400 // CHECK1-NEXT:    ret i32 [[ADD4]]
1401 //
1402 //
1403 // CHECK1-LABEL: define {{[^@]+}}@_ZL7fstatici
1404 // CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {
1405 // CHECK1-NEXT:  entry:
1406 // CHECK1-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
1407 // CHECK1-NEXT:    [[A:%.*]] = alloca i32, align 4
1408 // CHECK1-NEXT:    [[AA:%.*]] = alloca i16, align 2
1409 // CHECK1-NEXT:    [[AAA:%.*]] = alloca i8, align 1
1410 // CHECK1-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
1411 // CHECK1-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
1412 // CHECK1-NEXT:    [[N_CASTED:%.*]] = alloca i64, align 8
1413 // CHECK1-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
1414 // CHECK1-NEXT:    [[AAA_CASTED:%.*]] = alloca i64, align 8
1415 // CHECK1-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8
1416 // CHECK1-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8
1417 // CHECK1-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8
1418 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
1419 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
1420 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4
1421 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR_5:%.*]] = alloca i32, align 4
1422 // CHECK1-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
1423 // CHECK1-NEXT:    store i32 0, i32* [[A]], align 4
1424 // CHECK1-NEXT:    store i16 0, i16* [[AA]], align 2
1425 // CHECK1-NEXT:    store i8 0, i8* [[AAA]], align 1
1426 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
1427 // CHECK1-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32*
1428 // CHECK1-NEXT:    store i32 [[TMP0]], i32* [[CONV]], align 4
1429 // CHECK1-NEXT:    [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
1430 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
1431 // CHECK1-NEXT:    [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32*
1432 // CHECK1-NEXT:    store i32 [[TMP2]], i32* [[CONV1]], align 4
1433 // CHECK1-NEXT:    [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8
1434 // CHECK1-NEXT:    [[TMP4:%.*]] = load i16, i16* [[AA]], align 2
1435 // CHECK1-NEXT:    [[CONV2:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
1436 // CHECK1-NEXT:    store i16 [[TMP4]], i16* [[CONV2]], align 2
1437 // CHECK1-NEXT:    [[TMP5:%.*]] = load i64, i64* [[AA_CASTED]], align 8
1438 // CHECK1-NEXT:    [[TMP6:%.*]] = load i8, i8* [[AAA]], align 1
1439 // CHECK1-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
1440 // CHECK1-NEXT:    store i8 [[TMP6]], i8* [[CONV3]], align 1
1441 // CHECK1-NEXT:    [[TMP7:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
1442 // CHECK1-NEXT:    [[TMP8:%.*]] = load i32, i32* [[N_ADDR]], align 4
1443 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP8]], 50
1444 // CHECK1-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
1445 // CHECK1:       omp_if.then:
1446 // CHECK1-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1447 // CHECK1-NEXT:    [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64*
1448 // CHECK1-NEXT:    store i64 [[TMP1]], i64* [[TMP10]], align 8
1449 // CHECK1-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1450 // CHECK1-NEXT:    [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64*
1451 // CHECK1-NEXT:    store i64 [[TMP1]], i64* [[TMP12]], align 8
1452 // CHECK1-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
1453 // CHECK1-NEXT:    store i8* null, i8** [[TMP13]], align 8
1454 // CHECK1-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
1455 // CHECK1-NEXT:    [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64*
1456 // CHECK1-NEXT:    store i64 [[TMP3]], i64* [[TMP15]], align 8
1457 // CHECK1-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
1458 // CHECK1-NEXT:    [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64*
1459 // CHECK1-NEXT:    store i64 [[TMP3]], i64* [[TMP17]], align 8
1460 // CHECK1-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
1461 // CHECK1-NEXT:    store i8* null, i8** [[TMP18]], align 8
1462 // CHECK1-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
1463 // CHECK1-NEXT:    [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64*
1464 // CHECK1-NEXT:    store i64 [[TMP5]], i64* [[TMP20]], align 8
1465 // CHECK1-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
1466 // CHECK1-NEXT:    [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i64*
1467 // CHECK1-NEXT:    store i64 [[TMP5]], i64* [[TMP22]], align 8
1468 // CHECK1-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
1469 // CHECK1-NEXT:    store i8* null, i8** [[TMP23]], align 8
1470 // CHECK1-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
1471 // CHECK1-NEXT:    [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i64*
1472 // CHECK1-NEXT:    store i64 [[TMP7]], i64* [[TMP25]], align 8
1473 // CHECK1-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
1474 // CHECK1-NEXT:    [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64*
1475 // CHECK1-NEXT:    store i64 [[TMP7]], i64* [[TMP27]], align 8
1476 // CHECK1-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
1477 // CHECK1-NEXT:    store i8* null, i8** [[TMP28]], align 8
1478 // CHECK1-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
1479 // CHECK1-NEXT:    [[TMP30:%.*]] = bitcast i8** [[TMP29]] to [10 x i32]**
1480 // CHECK1-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP30]], align 8
1481 // CHECK1-NEXT:    [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
1482 // CHECK1-NEXT:    [[TMP32:%.*]] = bitcast i8** [[TMP31]] to [10 x i32]**
1483 // CHECK1-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP32]], align 8
1484 // CHECK1-NEXT:    [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4
1485 // CHECK1-NEXT:    store i8* null, i8** [[TMP33]], align 8
1486 // CHECK1-NEXT:    [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1487 // CHECK1-NEXT:    [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1488 // CHECK1-NEXT:    [[TMP36:%.*]] = load i32, i32* [[A]], align 4
1489 // CHECK1-NEXT:    store i32 [[TMP36]], i32* [[DOTCAPTURE_EXPR_]], align 4
1490 // CHECK1-NEXT:    [[TMP37:%.*]] = load i32, i32* [[N_ADDR]], align 4
1491 // CHECK1-NEXT:    store i32 [[TMP37]], i32* [[DOTCAPTURE_EXPR_4]], align 4
1492 // CHECK1-NEXT:    [[TMP38:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4
1493 // CHECK1-NEXT:    [[TMP39:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
1494 // CHECK1-NEXT:    [[SUB:%.*]] = sub i32 [[TMP38]], [[TMP39]]
1495 // CHECK1-NEXT:    [[SUB6:%.*]] = sub i32 [[SUB]], 1
1496 // CHECK1-NEXT:    [[ADD:%.*]] = add i32 [[SUB6]], 1
1497 // CHECK1-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], 1
1498 // CHECK1-NEXT:    [[SUB7:%.*]] = sub i32 [[DIV]], 1
1499 // CHECK1-NEXT:    store i32 [[SUB7]], i32* [[DOTCAPTURE_EXPR_5]], align 4
1500 // CHECK1-NEXT:    [[TMP40:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4
1501 // CHECK1-NEXT:    [[ADD8:%.*]] = add i32 [[TMP40]], 1
1502 // CHECK1-NEXT:    [[TMP41:%.*]] = zext i32 [[ADD8]] to i64
1503 // CHECK1-NEXT:    call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 [[TMP41]])
1504 // CHECK1-NEXT:    [[TMP42:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197.region_id, i32 5, i8** [[TMP34]], i8** [[TMP35]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes.16, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.17, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1)
1505 // CHECK1-NEXT:    [[TMP43:%.*]] = icmp ne i32 [[TMP42]], 0
1506 // CHECK1-NEXT:    br i1 [[TMP43]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
1507 // CHECK1:       omp_offload.failed:
1508 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], i64 [[TMP7]], [10 x i32]* [[B]]) #[[ATTR4]]
1509 // CHECK1-NEXT:    br label [[OMP_OFFLOAD_CONT]]
1510 // CHECK1:       omp_offload.cont:
1511 // CHECK1-NEXT:    br label [[OMP_IF_END:%.*]]
1512 // CHECK1:       omp_if.else:
1513 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], i64 [[TMP7]], [10 x i32]* [[B]]) #[[ATTR4]]
1514 // CHECK1-NEXT:    br label [[OMP_IF_END]]
1515 // CHECK1:       omp_if.end:
1516 // CHECK1-NEXT:    [[TMP44:%.*]] = load i32, i32* [[A]], align 4
1517 // CHECK1-NEXT:    ret i32 [[TMP44]]
1518 //
1519 //
1520 // CHECK1-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
1521 // CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat {
1522 // CHECK1-NEXT:  entry:
1523 // CHECK1-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
1524 // CHECK1-NEXT:    [[A:%.*]] = alloca i32, align 4
1525 // CHECK1-NEXT:    [[AA:%.*]] = alloca i16, align 2
1526 // CHECK1-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
1527 // CHECK1-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
1528 // CHECK1-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
1529 // CHECK1-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8
1530 // CHECK1-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8
1531 // CHECK1-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8
1532 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
1533 // CHECK1-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
1534 // CHECK1-NEXT:    store i32 0, i32* [[A]], align 4
1535 // CHECK1-NEXT:    store i16 0, i16* [[AA]], align 2
1536 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
1537 // CHECK1-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32*
1538 // CHECK1-NEXT:    store i32 [[TMP0]], i32* [[CONV]], align 4
1539 // CHECK1-NEXT:    [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
1540 // CHECK1-NEXT:    [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
1541 // CHECK1-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
1542 // CHECK1-NEXT:    store i16 [[TMP2]], i16* [[CONV1]], align 2
1543 // CHECK1-NEXT:    [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
1544 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
1545 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40
1546 // CHECK1-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
1547 // CHECK1:       omp_if.then:
1548 // CHECK1-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1549 // CHECK1-NEXT:    [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64*
1550 // CHECK1-NEXT:    store i64 [[TMP1]], i64* [[TMP6]], align 8
1551 // CHECK1-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1552 // CHECK1-NEXT:    [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64*
1553 // CHECK1-NEXT:    store i64 [[TMP1]], i64* [[TMP8]], align 8
1554 // CHECK1-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
1555 // CHECK1-NEXT:    store i8* null, i8** [[TMP9]], align 8
1556 // CHECK1-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
1557 // CHECK1-NEXT:    [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i64*
1558 // CHECK1-NEXT:    store i64 [[TMP3]], i64* [[TMP11]], align 8
1559 // CHECK1-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
1560 // CHECK1-NEXT:    [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64*
1561 // CHECK1-NEXT:    store i64 [[TMP3]], i64* [[TMP13]], align 8
1562 // CHECK1-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
1563 // CHECK1-NEXT:    store i8* null, i8** [[TMP14]], align 8
1564 // CHECK1-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
1565 // CHECK1-NEXT:    [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]**
1566 // CHECK1-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 8
1567 // CHECK1-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
1568 // CHECK1-NEXT:    [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]**
1569 // CHECK1-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 8
1570 // CHECK1-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
1571 // CHECK1-NEXT:    store i8* null, i8** [[TMP19]], align 8
1572 // CHECK1-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1573 // CHECK1-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1574 // CHECK1-NEXT:    call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10)
1575 // CHECK1-NEXT:    [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.19, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.20, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1)
1576 // CHECK1-NEXT:    [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0
1577 // CHECK1-NEXT:    br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
1578 // CHECK1:       omp_offload.failed:
1579 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]]
1580 // CHECK1-NEXT:    br label [[OMP_OFFLOAD_CONT]]
1581 // CHECK1:       omp_offload.cont:
1582 // CHECK1-NEXT:    br label [[OMP_IF_END:%.*]]
1583 // CHECK1:       omp_if.else:
1584 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]]
1585 // CHECK1-NEXT:    br label [[OMP_IF_END]]
1586 // CHECK1:       omp_if.end:
1587 // CHECK1-NEXT:    [[TMP24:%.*]] = load i32, i32* [[A]], align 4
1588 // CHECK1-NEXT:    ret i32 [[TMP24]]
1589 //
1590 //
1591 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215
1592 // CHECK1-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {
1593 // CHECK1-NEXT:  entry:
1594 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
1595 // CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
1596 // CHECK1-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
1597 // CHECK1-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
1598 // CHECK1-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 8
1599 // CHECK1-NEXT:    [[B_CASTED:%.*]] = alloca i64, align 8
1600 // CHECK1-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
1601 // CHECK1-NEXT:    store i64 [[B]], i64* [[B_ADDR]], align 8
1602 // CHECK1-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
1603 // CHECK1-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
1604 // CHECK1-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 8
1605 // CHECK1-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
1606 // CHECK1-NEXT:    [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
1607 // CHECK1-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
1608 // CHECK1-NEXT:    [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
1609 // CHECK1-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
1610 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
1611 // CHECK1-NEXT:    [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32*
1612 // CHECK1-NEXT:    store i32 [[TMP4]], i32* [[CONV3]], align 4
1613 // CHECK1-NEXT:    [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
1614 // CHECK1-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..12 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]])
1615 // CHECK1-NEXT:    ret void
1616 //
1617 //
1618 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..12
1619 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] {
1620 // CHECK1-NEXT:  entry:
1621 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
1622 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
1623 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
1624 // CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
1625 // CHECK1-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
1626 // CHECK1-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
1627 // CHECK1-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 8
1628 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
1629 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
1630 // CHECK1-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
1631 // CHECK1-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
1632 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1633 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1634 // CHECK1-NEXT:    [[I:%.*]] = alloca i32, align 4
1635 // CHECK1-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
1636 // CHECK1-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
1637 // CHECK1-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
1638 // CHECK1-NEXT:    store i64 [[B]], i64* [[B_ADDR]], align 8
1639 // CHECK1-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
1640 // CHECK1-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
1641 // CHECK1-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 8
1642 // CHECK1-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
1643 // CHECK1-NEXT:    [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
1644 // CHECK1-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
1645 // CHECK1-NEXT:    [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
1646 // CHECK1-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
1647 // CHECK1-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
1648 // CHECK1-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
1649 // CHECK1-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
1650 // CHECK1-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
1651 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
1652 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
1653 // CHECK1-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
1654 // CHECK1-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1655 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 9
1656 // CHECK1-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1657 // CHECK1:       cond.true:
1658 // CHECK1-NEXT:    br label [[COND_END:%.*]]
1659 // CHECK1:       cond.false:
1660 // CHECK1-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1661 // CHECK1-NEXT:    br label [[COND_END]]
1662 // CHECK1:       cond.end:
1663 // CHECK1-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
1664 // CHECK1-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
1665 // CHECK1-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
1666 // CHECK1-NEXT:    store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
1667 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
1668 // CHECK1:       omp.inner.for.cond:
1669 // CHECK1-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !38
1670 // CHECK1-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !38
1671 // CHECK1-NEXT:    [[CMP3:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
1672 // CHECK1-NEXT:    br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1673 // CHECK1:       omp.inner.for.body:
1674 // CHECK1-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !38
1675 // CHECK1-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
1676 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1677 // CHECK1-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !38
1678 // CHECK1-NEXT:    [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !38
1679 // CHECK1-NEXT:    [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double
1680 // CHECK1-NEXT:    [[ADD5:%.*]] = fadd double [[CONV4]], 1.500000e+00
1681 // CHECK1-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
1682 // CHECK1-NEXT:    store double [[ADD5]], double* [[A]], align 8, !llvm.access.group !38
1683 // CHECK1-NEXT:    [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
1684 // CHECK1-NEXT:    [[TMP13:%.*]] = load double, double* [[A6]], align 8, !llvm.access.group !38
1685 // CHECK1-NEXT:    [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00
1686 // CHECK1-NEXT:    store double [[INC]], double* [[A6]], align 8, !llvm.access.group !38
1687 // CHECK1-NEXT:    [[CONV7:%.*]] = fptosi double [[INC]] to i16
1688 // CHECK1-NEXT:    [[TMP14:%.*]] = mul nsw i64 1, [[TMP2]]
1689 // CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP14]]
1690 // CHECK1-NEXT:    [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
1691 // CHECK1-NEXT:    store i16 [[CONV7]], i16* [[ARRAYIDX8]], align 2, !llvm.access.group !38
1692 // CHECK1-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
1693 // CHECK1:       omp.body.continue:
1694 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
1695 // CHECK1:       omp.inner.for.inc:
1696 // CHECK1-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !38
1697 // CHECK1-NEXT:    [[ADD9:%.*]] = add nsw i32 [[TMP15]], 1
1698 // CHECK1-NEXT:    store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !38
1699 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP39:![0-9]+]]
1700 // CHECK1:       omp.inner.for.end:
1701 // CHECK1-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
1702 // CHECK1:       omp.loop.exit:
1703 // CHECK1-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
1704 // CHECK1-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
1705 // CHECK1-NEXT:    [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0
1706 // CHECK1-NEXT:    br i1 [[TMP17]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
1707 // CHECK1:       .omp.final.then:
1708 // CHECK1-NEXT:    store i32 10, i32* [[I]], align 4
1709 // CHECK1-NEXT:    br label [[DOTOMP_FINAL_DONE]]
1710 // CHECK1:       .omp.final.done:
1711 // CHECK1-NEXT:    ret void
1712 //
1713 //
1714 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197
1715 // CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[N:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
1716 // CHECK1-NEXT:  entry:
1717 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
1718 // CHECK1-NEXT:    [[N_ADDR:%.*]] = alloca i64, align 8
1719 // CHECK1-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
1720 // CHECK1-NEXT:    [[AAA_ADDR:%.*]] = alloca i64, align 8
1721 // CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
1722 // CHECK1-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
1723 // CHECK1-NEXT:    [[N_CASTED:%.*]] = alloca i64, align 8
1724 // CHECK1-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
1725 // CHECK1-NEXT:    [[AAA_CASTED:%.*]] = alloca i64, align 8
1726 // CHECK1-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
1727 // CHECK1-NEXT:    store i64 [[N]], i64* [[N_ADDR]], align 8
1728 // CHECK1-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
1729 // CHECK1-NEXT:    store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
1730 // CHECK1-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
1731 // CHECK1-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
1732 // CHECK1-NEXT:    [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32*
1733 // CHECK1-NEXT:    [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
1734 // CHECK1-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
1735 // CHECK1-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
1736 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
1737 // CHECK1-NEXT:    [[CONV4:%.*]] = bitcast i64* [[A_CASTED]] to i32*
1738 // CHECK1-NEXT:    store i32 [[TMP1]], i32* [[CONV4]], align 4
1739 // CHECK1-NEXT:    [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
1740 // CHECK1-NEXT:    [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 4
1741 // CHECK1-NEXT:    [[CONV5:%.*]] = bitcast i64* [[N_CASTED]] to i32*
1742 // CHECK1-NEXT:    store i32 [[TMP3]], i32* [[CONV5]], align 4
1743 // CHECK1-NEXT:    [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8
1744 // CHECK1-NEXT:    [[TMP5:%.*]] = load i16, i16* [[CONV2]], align 2
1745 // CHECK1-NEXT:    [[CONV6:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
1746 // CHECK1-NEXT:    store i16 [[TMP5]], i16* [[CONV6]], align 2
1747 // CHECK1-NEXT:    [[TMP6:%.*]] = load i64, i64* [[AA_CASTED]], align 8
1748 // CHECK1-NEXT:    [[TMP7:%.*]] = load i8, i8* [[CONV3]], align 1
1749 // CHECK1-NEXT:    [[CONV7:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
1750 // CHECK1-NEXT:    store i8 [[TMP7]], i8* [[CONV7]], align 1
1751 // CHECK1-NEXT:    [[TMP8:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
1752 // CHECK1-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, [10 x i32]*)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]], [10 x i32]* [[TMP0]])
1753 // CHECK1-NEXT:    ret void
1754 //
1755 //
1756 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..15
1757 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[N:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] {
1758 // CHECK1-NEXT:  entry:
1759 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
1760 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
1761 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
1762 // CHECK1-NEXT:    [[N_ADDR:%.*]] = alloca i64, align 8
1763 // CHECK1-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
1764 // CHECK1-NEXT:    [[AAA_ADDR:%.*]] = alloca i64, align 8
1765 // CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
1766 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
1767 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
1768 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
1769 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4
1770 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR_5:%.*]] = alloca i32, align 4
1771 // CHECK1-NEXT:    [[I:%.*]] = alloca i32, align 4
1772 // CHECK1-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
1773 // CHECK1-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
1774 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1775 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1776 // CHECK1-NEXT:    [[I8:%.*]] = alloca i32, align 4
1777 // CHECK1-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
1778 // CHECK1-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
1779 // CHECK1-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
1780 // CHECK1-NEXT:    store i64 [[N]], i64* [[N_ADDR]], align 8
1781 // CHECK1-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
1782 // CHECK1-NEXT:    store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
1783 // CHECK1-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
1784 // CHECK1-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
1785 // CHECK1-NEXT:    [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32*
1786 // CHECK1-NEXT:    [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
1787 // CHECK1-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
1788 // CHECK1-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
1789 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
1790 // CHECK1-NEXT:    store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
1791 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4
1792 // CHECK1-NEXT:    store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_4]], align 4
1793 // CHECK1-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4
1794 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
1795 // CHECK1-NEXT:    [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]]
1796 // CHECK1-NEXT:    [[SUB6:%.*]] = sub i32 [[SUB]], 1
1797 // CHECK1-NEXT:    [[ADD:%.*]] = add i32 [[SUB6]], 1
1798 // CHECK1-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], 1
1799 // CHECK1-NEXT:    [[SUB7:%.*]] = sub i32 [[DIV]], 1
1800 // CHECK1-NEXT:    store i32 [[SUB7]], i32* [[DOTCAPTURE_EXPR_5]], align 4
1801 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
1802 // CHECK1-NEXT:    store i32 [[TMP5]], i32* [[I]], align 4
1803 // CHECK1-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
1804 // CHECK1-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4
1805 // CHECK1-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]]
1806 // CHECK1-NEXT:    br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
1807 // CHECK1:       omp.precond.then:
1808 // CHECK1-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
1809 // CHECK1-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4
1810 // CHECK1-NEXT:    store i32 [[TMP8]], i32* [[DOTOMP_UB]], align 4
1811 // CHECK1-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
1812 // CHECK1-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
1813 // CHECK1-NEXT:    [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
1814 // CHECK1-NEXT:    [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
1815 // CHECK1-NEXT:    call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
1816 // CHECK1-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1817 // CHECK1-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4
1818 // CHECK1-NEXT:    [[CMP9:%.*]] = icmp ugt i32 [[TMP11]], [[TMP12]]
1819 // CHECK1-NEXT:    br i1 [[CMP9]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1820 // CHECK1:       cond.true:
1821 // CHECK1-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4
1822 // CHECK1-NEXT:    br label [[COND_END:%.*]]
1823 // CHECK1:       cond.false:
1824 // CHECK1-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1825 // CHECK1-NEXT:    br label [[COND_END]]
1826 // CHECK1:       cond.end:
1827 // CHECK1-NEXT:    [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ]
1828 // CHECK1-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
1829 // CHECK1-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
1830 // CHECK1-NEXT:    store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4
1831 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
1832 // CHECK1:       omp.inner.for.cond:
1833 // CHECK1-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !41
1834 // CHECK1-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !41
1835 // CHECK1-NEXT:    [[ADD10:%.*]] = add i32 [[TMP17]], 1
1836 // CHECK1-NEXT:    [[CMP11:%.*]] = icmp ult i32 [[TMP16]], [[ADD10]]
1837 // CHECK1-NEXT:    br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1838 // CHECK1:       omp.inner.for.body:
1839 // CHECK1-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group !41
1840 // CHECK1-NEXT:    [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !41
1841 // CHECK1-NEXT:    [[MUL:%.*]] = mul i32 [[TMP19]], 1
1842 // CHECK1-NEXT:    [[ADD12:%.*]] = add i32 [[TMP18]], [[MUL]]
1843 // CHECK1-NEXT:    store i32 [[ADD12]], i32* [[I8]], align 4, !llvm.access.group !41
1844 // CHECK1-NEXT:    [[TMP20:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !41
1845 // CHECK1-NEXT:    [[ADD13:%.*]] = add nsw i32 [[TMP20]], 1
1846 // CHECK1-NEXT:    store i32 [[ADD13]], i32* [[CONV]], align 4, !llvm.access.group !41
1847 // CHECK1-NEXT:    [[TMP21:%.*]] = load i16, i16* [[CONV2]], align 2, !llvm.access.group !41
1848 // CHECK1-NEXT:    [[CONV14:%.*]] = sext i16 [[TMP21]] to i32
1849 // CHECK1-NEXT:    [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1
1850 // CHECK1-NEXT:    [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16
1851 // CHECK1-NEXT:    store i16 [[CONV16]], i16* [[CONV2]], align 2, !llvm.access.group !41
1852 // CHECK1-NEXT:    [[TMP22:%.*]] = load i8, i8* [[CONV3]], align 1, !llvm.access.group !41
1853 // CHECK1-NEXT:    [[CONV17:%.*]] = sext i8 [[TMP22]] to i32
1854 // CHECK1-NEXT:    [[ADD18:%.*]] = add nsw i32 [[CONV17]], 1
1855 // CHECK1-NEXT:    [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8
1856 // CHECK1-NEXT:    store i8 [[CONV19]], i8* [[CONV3]], align 1, !llvm.access.group !41
1857 // CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
1858 // CHECK1-NEXT:    [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !41
1859 // CHECK1-NEXT:    [[ADD20:%.*]] = add nsw i32 [[TMP23]], 1
1860 // CHECK1-NEXT:    store i32 [[ADD20]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !41
1861 // CHECK1-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
1862 // CHECK1:       omp.body.continue:
1863 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
1864 // CHECK1:       omp.inner.for.inc:
1865 // CHECK1-NEXT:    [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !41
1866 // CHECK1-NEXT:    [[ADD21:%.*]] = add i32 [[TMP24]], 1
1867 // CHECK1-NEXT:    store i32 [[ADD21]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !41
1868 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP42:![0-9]+]]
1869 // CHECK1:       omp.inner.for.end:
1870 // CHECK1-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
1871 // CHECK1:       omp.loop.exit:
1872 // CHECK1-NEXT:    [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
1873 // CHECK1-NEXT:    [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4
1874 // CHECK1-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]])
1875 // CHECK1-NEXT:    [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
1876 // CHECK1-NEXT:    [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0
1877 // CHECK1-NEXT:    br i1 [[TMP28]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
1878 // CHECK1:       .omp.final.then:
1879 // CHECK1-NEXT:    [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
1880 // CHECK1-NEXT:    [[TMP30:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4
1881 // CHECK1-NEXT:    [[TMP31:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
1882 // CHECK1-NEXT:    [[SUB22:%.*]] = sub i32 [[TMP30]], [[TMP31]]
1883 // CHECK1-NEXT:    [[SUB23:%.*]] = sub i32 [[SUB22]], 1
1884 // CHECK1-NEXT:    [[ADD24:%.*]] = add i32 [[SUB23]], 1
1885 // CHECK1-NEXT:    [[DIV25:%.*]] = udiv i32 [[ADD24]], 1
1886 // CHECK1-NEXT:    [[MUL26:%.*]] = mul i32 [[DIV25]], 1
1887 // CHECK1-NEXT:    [[ADD27:%.*]] = add i32 [[TMP29]], [[MUL26]]
1888 // CHECK1-NEXT:    store i32 [[ADD27]], i32* [[I8]], align 4
1889 // CHECK1-NEXT:    br label [[DOTOMP_FINAL_DONE]]
1890 // CHECK1:       .omp.final.done:
1891 // CHECK1-NEXT:    br label [[OMP_PRECOND_END]]
1892 // CHECK1:       omp.precond.end:
1893 // CHECK1-NEXT:    ret void
1894 //
1895 //
1896 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180
1897 // CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
1898 // CHECK1-NEXT:  entry:
1899 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
1900 // CHECK1-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
1901 // CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
1902 // CHECK1-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
1903 // CHECK1-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
1904 // CHECK1-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
1905 // CHECK1-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
1906 // CHECK1-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
1907 // CHECK1-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
1908 // CHECK1-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
1909 // CHECK1-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
1910 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
1911 // CHECK1-NEXT:    [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
1912 // CHECK1-NEXT:    store i32 [[TMP1]], i32* [[CONV2]], align 4
1913 // CHECK1-NEXT:    [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
1914 // CHECK1-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
1915 // CHECK1-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
1916 // CHECK1-NEXT:    store i16 [[TMP3]], i16* [[CONV3]], align 2
1917 // CHECK1-NEXT:    [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
1918 // CHECK1-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..18 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]])
1919 // CHECK1-NEXT:    ret void
1920 //
1921 //
1922 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..18
1923 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] {
1924 // CHECK1-NEXT:  entry:
1925 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
1926 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
1927 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
1928 // CHECK1-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
1929 // CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
1930 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
1931 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
1932 // CHECK1-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
1933 // CHECK1-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
1934 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1935 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1936 // CHECK1-NEXT:    [[I:%.*]] = alloca i32, align 4
1937 // CHECK1-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
1938 // CHECK1-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
1939 // CHECK1-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
1940 // CHECK1-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
1941 // CHECK1-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
1942 // CHECK1-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
1943 // CHECK1-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
1944 // CHECK1-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
1945 // CHECK1-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
1946 // CHECK1-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
1947 // CHECK1-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
1948 // CHECK1-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
1949 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
1950 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
1951 // CHECK1-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
1952 // CHECK1-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1953 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9
1954 // CHECK1-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1955 // CHECK1:       cond.true:
1956 // CHECK1-NEXT:    br label [[COND_END:%.*]]
1957 // CHECK1:       cond.false:
1958 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1959 // CHECK1-NEXT:    br label [[COND_END]]
1960 // CHECK1:       cond.end:
1961 // CHECK1-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
1962 // CHECK1-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
1963 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
1964 // CHECK1-NEXT:    store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
1965 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
1966 // CHECK1:       omp.inner.for.cond:
1967 // CHECK1-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !44
1968 // CHECK1-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !44
1969 // CHECK1-NEXT:    [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
1970 // CHECK1-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1971 // CHECK1:       omp.inner.for.body:
1972 // CHECK1-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !44
1973 // CHECK1-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
1974 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1975 // CHECK1-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !44
1976 // CHECK1-NEXT:    [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !44
1977 // CHECK1-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1
1978 // CHECK1-NEXT:    store i32 [[ADD3]], i32* [[CONV]], align 4, !llvm.access.group !44
1979 // CHECK1-NEXT:    [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 2, !llvm.access.group !44
1980 // CHECK1-NEXT:    [[CONV4:%.*]] = sext i16 [[TMP10]] to i32
1981 // CHECK1-NEXT:    [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
1982 // CHECK1-NEXT:    [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
1983 // CHECK1-NEXT:    store i16 [[CONV6]], i16* [[CONV1]], align 2, !llvm.access.group !44
1984 // CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
1985 // CHECK1-NEXT:    [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !44
1986 // CHECK1-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1
1987 // CHECK1-NEXT:    store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !44
1988 // CHECK1-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
1989 // CHECK1:       omp.body.continue:
1990 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
1991 // CHECK1:       omp.inner.for.inc:
1992 // CHECK1-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !44
1993 // CHECK1-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP12]], 1
1994 // CHECK1-NEXT:    store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !44
1995 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP45:![0-9]+]]
1996 // CHECK1:       omp.inner.for.end:
1997 // CHECK1-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
1998 // CHECK1:       omp.loop.exit:
1999 // CHECK1-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
2000 // CHECK1-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
2001 // CHECK1-NEXT:    [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
2002 // CHECK1-NEXT:    br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
2003 // CHECK1:       .omp.final.then:
2004 // CHECK1-NEXT:    store i32 10, i32* [[I]], align 4
2005 // CHECK1-NEXT:    br label [[DOTOMP_FINAL_DONE]]
2006 // CHECK1:       .omp.final.done:
2007 // CHECK1-NEXT:    ret void
2008 //
2009 //
2010 // CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
2011 // CHECK1-SAME: () #[[ATTR5]] {
2012 // CHECK1-NEXT:  entry:
2013 // CHECK1-NEXT:    call void @__tgt_register_requires(i64 1)
2014 // CHECK1-NEXT:    ret void
2015 //
2016 //
2017 // CHECK2-LABEL: define {{[^@]+}}@_Z3fooi
2018 // CHECK2-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0:[0-9]+]] {
2019 // CHECK2-NEXT:  entry:
2020 // CHECK2-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
2021 // CHECK2-NEXT:    [[A:%.*]] = alloca i32, align 4
2022 // CHECK2-NEXT:    [[AA:%.*]] = alloca i16, align 2
2023 // CHECK2-NEXT:    [[B:%.*]] = alloca [10 x float], align 4
2024 // CHECK2-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 8
2025 // CHECK2-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
2026 // CHECK2-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 8
2027 // CHECK2-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i64, align 8
2028 // CHECK2-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8
2029 // CHECK2-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
2030 // CHECK2-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
2031 // CHECK2-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
2032 // CHECK2-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
2033 // CHECK2-NEXT:    [[DOTCAPTURE_EXPR__CASTED4:%.*]] = alloca i64, align 8
2034 // CHECK2-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8
2035 // CHECK2-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8
2036 // CHECK2-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8
2037 // CHECK2-NEXT:    [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4
2038 // CHECK2-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
2039 // CHECK2-NEXT:    [[AA_CASTED7:%.*]] = alloca i64, align 8
2040 // CHECK2-NEXT:    [[DOTOFFLOAD_BASEPTRS9:%.*]] = alloca [1 x i8*], align 8
2041 // CHECK2-NEXT:    [[DOTOFFLOAD_PTRS10:%.*]] = alloca [1 x i8*], align 8
2042 // CHECK2-NEXT:    [[DOTOFFLOAD_MAPPERS11:%.*]] = alloca [1 x i8*], align 8
2043 // CHECK2-NEXT:    [[TMP:%.*]] = alloca i32, align 4
2044 // CHECK2-NEXT:    [[A_CASTED12:%.*]] = alloca i64, align 8
2045 // CHECK2-NEXT:    [[AA_CASTED14:%.*]] = alloca i64, align 8
2046 // CHECK2-NEXT:    [[DOTOFFLOAD_BASEPTRS16:%.*]] = alloca [2 x i8*], align 8
2047 // CHECK2-NEXT:    [[DOTOFFLOAD_PTRS17:%.*]] = alloca [2 x i8*], align 8
2048 // CHECK2-NEXT:    [[DOTOFFLOAD_MAPPERS18:%.*]] = alloca [2 x i8*], align 8
2049 // CHECK2-NEXT:    [[_TMP19:%.*]] = alloca i32, align 4
2050 // CHECK2-NEXT:    [[A_CASTED22:%.*]] = alloca i64, align 8
2051 // CHECK2-NEXT:    [[DOTOFFLOAD_BASEPTRS26:%.*]] = alloca [9 x i8*], align 8
2052 // CHECK2-NEXT:    [[DOTOFFLOAD_PTRS27:%.*]] = alloca [9 x i8*], align 8
2053 // CHECK2-NEXT:    [[DOTOFFLOAD_MAPPERS28:%.*]] = alloca [9 x i8*], align 8
2054 // CHECK2-NEXT:    [[DOTOFFLOAD_SIZES:%.*]] = alloca [9 x i64], align 8
2055 // CHECK2-NEXT:    [[_TMP29:%.*]] = alloca i32, align 4
2056 // CHECK2-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]])
2057 // CHECK2-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
2058 // CHECK2-NEXT:    store i32 0, i32* [[A]], align 4
2059 // CHECK2-NEXT:    store i16 0, i16* [[AA]], align 2
2060 // CHECK2-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
2061 // CHECK2-NEXT:    [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
2062 // CHECK2-NEXT:    [[TMP3:%.*]] = call i8* @llvm.stacksave()
2063 // CHECK2-NEXT:    store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8
2064 // CHECK2-NEXT:    [[VLA:%.*]] = alloca float, i64 [[TMP2]], align 4
2065 // CHECK2-NEXT:    store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8
2066 // CHECK2-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
2067 // CHECK2-NEXT:    [[TMP5:%.*]] = zext i32 [[TMP4]] to i64
2068 // CHECK2-NEXT:    [[TMP6:%.*]] = mul nuw i64 5, [[TMP5]]
2069 // CHECK2-NEXT:    [[VLA1:%.*]] = alloca double, i64 [[TMP6]], align 8
2070 // CHECK2-NEXT:    store i64 [[TMP5]], i64* [[__VLA_EXPR1]], align 8
2071 // CHECK2-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
2072 // CHECK2-NEXT:    store i32 [[TMP7]], i32* [[DOTCAPTURE_EXPR_]], align 4
2073 // CHECK2-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
2074 // CHECK2-NEXT:    store i32 [[TMP8]], i32* [[DOTCAPTURE_EXPR_2]], align 4
2075 // CHECK2-NEXT:    [[TMP9:%.*]] = load i16, i16* [[AA]], align 2
2076 // CHECK2-NEXT:    [[CONV:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
2077 // CHECK2-NEXT:    store i16 [[TMP9]], i16* [[CONV]], align 2
2078 // CHECK2-NEXT:    [[TMP10:%.*]] = load i64, i64* [[AA_CASTED]], align 8
2079 // CHECK2-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
2080 // CHECK2-NEXT:    [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
2081 // CHECK2-NEXT:    store i32 [[TMP11]], i32* [[CONV3]], align 4
2082 // CHECK2-NEXT:    [[TMP12:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
2083 // CHECK2-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
2084 // CHECK2-NEXT:    [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED4]] to i32*
2085 // CHECK2-NEXT:    store i32 [[TMP13]], i32* [[CONV5]], align 4
2086 // CHECK2-NEXT:    [[TMP14:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED4]], align 8
2087 // CHECK2-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
2088 // CHECK2-NEXT:    [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i64*
2089 // CHECK2-NEXT:    store i64 [[TMP10]], i64* [[TMP16]], align 8
2090 // CHECK2-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
2091 // CHECK2-NEXT:    [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64*
2092 // CHECK2-NEXT:    store i64 [[TMP10]], i64* [[TMP18]], align 8
2093 // CHECK2-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
2094 // CHECK2-NEXT:    store i8* null, i8** [[TMP19]], align 8
2095 // CHECK2-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
2096 // CHECK2-NEXT:    [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i64*
2097 // CHECK2-NEXT:    store i64 [[TMP12]], i64* [[TMP21]], align 8
2098 // CHECK2-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
2099 // CHECK2-NEXT:    [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i64*
2100 // CHECK2-NEXT:    store i64 [[TMP12]], i64* [[TMP23]], align 8
2101 // CHECK2-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
2102 // CHECK2-NEXT:    store i8* null, i8** [[TMP24]], align 8
2103 // CHECK2-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
2104 // CHECK2-NEXT:    [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i64*
2105 // CHECK2-NEXT:    store i64 [[TMP14]], i64* [[TMP26]], align 8
2106 // CHECK2-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
2107 // CHECK2-NEXT:    [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i64*
2108 // CHECK2-NEXT:    store i64 [[TMP14]], i64* [[TMP28]], align 8
2109 // CHECK2-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
2110 // CHECK2-NEXT:    store i8* null, i8** [[TMP29]], align 8
2111 // CHECK2-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
2112 // CHECK2-NEXT:    [[TMP31:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
2113 // CHECK2-NEXT:    [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 0
2114 // CHECK2-NEXT:    [[TMP33:%.*]] = load i16, i16* [[AA]], align 2
2115 // CHECK2-NEXT:    store i16 [[TMP33]], i16* [[TMP32]], align 4
2116 // CHECK2-NEXT:    [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 1
2117 // CHECK2-NEXT:    [[TMP35:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
2118 // CHECK2-NEXT:    store i32 [[TMP35]], i32* [[TMP34]], align 4
2119 // CHECK2-NEXT:    [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 2
2120 // CHECK2-NEXT:    [[TMP37:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
2121 // CHECK2-NEXT:    store i32 [[TMP37]], i32* [[TMP36]], align 4
2122 // CHECK2-NEXT:    [[TMP38:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 1, i64 120, i64 12, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1)
2123 // CHECK2-NEXT:    [[TMP39:%.*]] = bitcast i8* [[TMP38]] to %struct.kmp_task_t_with_privates*
2124 // CHECK2-NEXT:    [[TMP40:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP39]], i32 0, i32 0
2125 // CHECK2-NEXT:    [[TMP41:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP40]], i32 0, i32 0
2126 // CHECK2-NEXT:    [[TMP42:%.*]] = load i8*, i8** [[TMP41]], align 8
2127 // CHECK2-NEXT:    [[TMP43:%.*]] = bitcast %struct.anon* [[AGG_CAPTURED]] to i8*
2128 // CHECK2-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP42]], i8* align 4 [[TMP43]], i64 12, i1 false)
2129 // CHECK2-NEXT:    [[TMP44:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP39]], i32 0, i32 1
2130 // CHECK2-NEXT:    [[TMP45:%.*]] = bitcast i8* [[TMP42]] to %struct.anon*
2131 // CHECK2-NEXT:    [[TMP46:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 0
2132 // CHECK2-NEXT:    [[TMP47:%.*]] = bitcast [3 x i8*]* [[TMP46]] to i8*
2133 // CHECK2-NEXT:    [[TMP48:%.*]] = bitcast i8** [[TMP30]] to i8*
2134 // CHECK2-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP47]], i8* align 8 [[TMP48]], i64 24, i1 false)
2135 // CHECK2-NEXT:    [[TMP49:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 1
2136 // CHECK2-NEXT:    [[TMP50:%.*]] = bitcast [3 x i8*]* [[TMP49]] to i8*
2137 // CHECK2-NEXT:    [[TMP51:%.*]] = bitcast i8** [[TMP31]] to i8*
2138 // CHECK2-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP50]], i8* align 8 [[TMP51]], i64 24, i1 false)
2139 // CHECK2-NEXT:    [[TMP52:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 2
2140 // CHECK2-NEXT:    [[TMP53:%.*]] = bitcast [3 x i64]* [[TMP52]] to i8*
2141 // CHECK2-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP53]], i8* align 8 bitcast ([3 x i64]* @.offload_sizes to i8*), i64 24, i1 false)
2142 // CHECK2-NEXT:    [[TMP54:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 3
2143 // CHECK2-NEXT:    [[TMP55:%.*]] = load i16, i16* [[AA]], align 2
2144 // CHECK2-NEXT:    store i16 [[TMP55]], i16* [[TMP54]], align 8
2145 // CHECK2-NEXT:    [[TMP56:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i8* [[TMP38]])
2146 // CHECK2-NEXT:    [[TMP57:%.*]] = load i32, i32* [[A]], align 4
2147 // CHECK2-NEXT:    [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32*
2148 // CHECK2-NEXT:    store i32 [[TMP57]], i32* [[CONV6]], align 4
2149 // CHECK2-NEXT:    [[TMP58:%.*]] = load i64, i64* [[A_CASTED]], align 8
2150 // CHECK2-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104(i64 [[TMP58]]) #[[ATTR4:[0-9]+]]
2151 // CHECK2-NEXT:    [[TMP59:%.*]] = load i16, i16* [[AA]], align 2
2152 // CHECK2-NEXT:    [[CONV8:%.*]] = bitcast i64* [[AA_CASTED7]] to i16*
2153 // CHECK2-NEXT:    store i16 [[TMP59]], i16* [[CONV8]], align 2
2154 // CHECK2-NEXT:    [[TMP60:%.*]] = load i64, i64* [[AA_CASTED7]], align 8
2155 // CHECK2-NEXT:    [[TMP61:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS9]], i32 0, i32 0
2156 // CHECK2-NEXT:    [[TMP62:%.*]] = bitcast i8** [[TMP61]] to i64*
2157 // CHECK2-NEXT:    store i64 [[TMP60]], i64* [[TMP62]], align 8
2158 // CHECK2-NEXT:    [[TMP63:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS10]], i32 0, i32 0
2159 // CHECK2-NEXT:    [[TMP64:%.*]] = bitcast i8** [[TMP63]] to i64*
2160 // CHECK2-NEXT:    store i64 [[TMP60]], i64* [[TMP64]], align 8
2161 // CHECK2-NEXT:    [[TMP65:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS11]], i64 0, i64 0
2162 // CHECK2-NEXT:    store i8* null, i8** [[TMP65]], align 8
2163 // CHECK2-NEXT:    [[TMP66:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS9]], i32 0, i32 0
2164 // CHECK2-NEXT:    [[TMP67:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS10]], i32 0, i32 0
2165 // CHECK2-NEXT:    call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10)
2166 // CHECK2-NEXT:    [[TMP68:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.region_id, i32 1, i8** [[TMP66]], i8** [[TMP67]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.4, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.5, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1)
2167 // CHECK2-NEXT:    [[TMP69:%.*]] = icmp ne i32 [[TMP68]], 0
2168 // CHECK2-NEXT:    br i1 [[TMP69]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
2169 // CHECK2:       omp_offload.failed:
2170 // CHECK2-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111(i64 [[TMP60]]) #[[ATTR4]]
2171 // CHECK2-NEXT:    br label [[OMP_OFFLOAD_CONT]]
2172 // CHECK2:       omp_offload.cont:
2173 // CHECK2-NEXT:    [[TMP70:%.*]] = load i32, i32* [[A]], align 4
2174 // CHECK2-NEXT:    [[CONV13:%.*]] = bitcast i64* [[A_CASTED12]] to i32*
2175 // CHECK2-NEXT:    store i32 [[TMP70]], i32* [[CONV13]], align 4
2176 // CHECK2-NEXT:    [[TMP71:%.*]] = load i64, i64* [[A_CASTED12]], align 8
2177 // CHECK2-NEXT:    [[TMP72:%.*]] = load i16, i16* [[AA]], align 2
2178 // CHECK2-NEXT:    [[CONV15:%.*]] = bitcast i64* [[AA_CASTED14]] to i16*
2179 // CHECK2-NEXT:    store i16 [[TMP72]], i16* [[CONV15]], align 2
2180 // CHECK2-NEXT:    [[TMP73:%.*]] = load i64, i64* [[AA_CASTED14]], align 8
2181 // CHECK2-NEXT:    [[TMP74:%.*]] = load i32, i32* [[N_ADDR]], align 4
2182 // CHECK2-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP74]], 10
2183 // CHECK2-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
2184 // CHECK2:       omp_if.then:
2185 // CHECK2-NEXT:    [[TMP75:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 0
2186 // CHECK2-NEXT:    [[TMP76:%.*]] = bitcast i8** [[TMP75]] to i64*
2187 // CHECK2-NEXT:    store i64 [[TMP71]], i64* [[TMP76]], align 8
2188 // CHECK2-NEXT:    [[TMP77:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 0
2189 // CHECK2-NEXT:    [[TMP78:%.*]] = bitcast i8** [[TMP77]] to i64*
2190 // CHECK2-NEXT:    store i64 [[TMP71]], i64* [[TMP78]], align 8
2191 // CHECK2-NEXT:    [[TMP79:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 0
2192 // CHECK2-NEXT:    store i8* null, i8** [[TMP79]], align 8
2193 // CHECK2-NEXT:    [[TMP80:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 1
2194 // CHECK2-NEXT:    [[TMP81:%.*]] = bitcast i8** [[TMP80]] to i64*
2195 // CHECK2-NEXT:    store i64 [[TMP73]], i64* [[TMP81]], align 8
2196 // CHECK2-NEXT:    [[TMP82:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 1
2197 // CHECK2-NEXT:    [[TMP83:%.*]] = bitcast i8** [[TMP82]] to i64*
2198 // CHECK2-NEXT:    store i64 [[TMP73]], i64* [[TMP83]], align 8
2199 // CHECK2-NEXT:    [[TMP84:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 1
2200 // CHECK2-NEXT:    store i8* null, i8** [[TMP84]], align 8
2201 // CHECK2-NEXT:    [[TMP85:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 0
2202 // CHECK2-NEXT:    [[TMP86:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 0
2203 // CHECK2-NEXT:    call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10)
2204 // CHECK2-NEXT:    [[TMP87:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.region_id, i32 2, i8** [[TMP85]], i8** [[TMP86]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.7, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.8, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1)
2205 // CHECK2-NEXT:    [[TMP88:%.*]] = icmp ne i32 [[TMP87]], 0
2206 // CHECK2-NEXT:    br i1 [[TMP88]], label [[OMP_OFFLOAD_FAILED20:%.*]], label [[OMP_OFFLOAD_CONT21:%.*]]
2207 // CHECK2:       omp_offload.failed20:
2208 // CHECK2-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i64 [[TMP71]], i64 [[TMP73]]) #[[ATTR4]]
2209 // CHECK2-NEXT:    br label [[OMP_OFFLOAD_CONT21]]
2210 // CHECK2:       omp_offload.cont21:
2211 // CHECK2-NEXT:    br label [[OMP_IF_END:%.*]]
2212 // CHECK2:       omp_if.else:
2213 // CHECK2-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i64 [[TMP71]], i64 [[TMP73]]) #[[ATTR4]]
2214 // CHECK2-NEXT:    br label [[OMP_IF_END]]
2215 // CHECK2:       omp_if.end:
2216 // CHECK2-NEXT:    [[TMP89:%.*]] = load i32, i32* [[A]], align 4
2217 // CHECK2-NEXT:    [[CONV23:%.*]] = bitcast i64* [[A_CASTED22]] to i32*
2218 // CHECK2-NEXT:    store i32 [[TMP89]], i32* [[CONV23]], align 4
2219 // CHECK2-NEXT:    [[TMP90:%.*]] = load i64, i64* [[A_CASTED22]], align 8
2220 // CHECK2-NEXT:    [[TMP91:%.*]] = load i32, i32* [[N_ADDR]], align 4
2221 // CHECK2-NEXT:    [[CMP24:%.*]] = icmp sgt i32 [[TMP91]], 20
2222 // CHECK2-NEXT:    br i1 [[CMP24]], label [[OMP_IF_THEN25:%.*]], label [[OMP_IF_ELSE32:%.*]]
2223 // CHECK2:       omp_if.then25:
2224 // CHECK2-NEXT:    [[TMP92:%.*]] = mul nuw i64 [[TMP2]], 4
2225 // CHECK2-NEXT:    [[TMP93:%.*]] = mul nuw i64 5, [[TMP5]]
2226 // CHECK2-NEXT:    [[TMP94:%.*]] = mul nuw i64 [[TMP93]], 8
2227 // CHECK2-NEXT:    [[TMP95:%.*]] = bitcast [9 x i64]* [[DOTOFFLOAD_SIZES]] to i8*
2228 // CHECK2-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP95]], i8* align 8 bitcast ([9 x i64]* @.offload_sizes.10 to i8*), i64 72, i1 false)
2229 // CHECK2-NEXT:    [[TMP96:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS26]], i32 0, i32 0
2230 // CHECK2-NEXT:    [[TMP97:%.*]] = bitcast i8** [[TMP96]] to i64*
2231 // CHECK2-NEXT:    store i64 [[TMP90]], i64* [[TMP97]], align 8
2232 // CHECK2-NEXT:    [[TMP98:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS27]], i32 0, i32 0
2233 // CHECK2-NEXT:    [[TMP99:%.*]] = bitcast i8** [[TMP98]] to i64*
2234 // CHECK2-NEXT:    store i64 [[TMP90]], i64* [[TMP99]], align 8
2235 // CHECK2-NEXT:    [[TMP100:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS28]], i64 0, i64 0
2236 // CHECK2-NEXT:    store i8* null, i8** [[TMP100]], align 8
2237 // CHECK2-NEXT:    [[TMP101:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS26]], i32 0, i32 1
2238 // CHECK2-NEXT:    [[TMP102:%.*]] = bitcast i8** [[TMP101]] to [10 x float]**
2239 // CHECK2-NEXT:    store [10 x float]* [[B]], [10 x float]** [[TMP102]], align 8
2240 // CHECK2-NEXT:    [[TMP103:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS27]], i32 0, i32 1
2241 // CHECK2-NEXT:    [[TMP104:%.*]] = bitcast i8** [[TMP103]] to [10 x float]**
2242 // CHECK2-NEXT:    store [10 x float]* [[B]], [10 x float]** [[TMP104]], align 8
2243 // CHECK2-NEXT:    [[TMP105:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS28]], i64 0, i64 1
2244 // CHECK2-NEXT:    store i8* null, i8** [[TMP105]], align 8
2245 // CHECK2-NEXT:    [[TMP106:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS26]], i32 0, i32 2
2246 // CHECK2-NEXT:    [[TMP107:%.*]] = bitcast i8** [[TMP106]] to i64*
2247 // CHECK2-NEXT:    store i64 [[TMP2]], i64* [[TMP107]], align 8
2248 // CHECK2-NEXT:    [[TMP108:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS27]], i32 0, i32 2
2249 // CHECK2-NEXT:    [[TMP109:%.*]] = bitcast i8** [[TMP108]] to i64*
2250 // CHECK2-NEXT:    store i64 [[TMP2]], i64* [[TMP109]], align 8
2251 // CHECK2-NEXT:    [[TMP110:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS28]], i64 0, i64 2
2252 // CHECK2-NEXT:    store i8* null, i8** [[TMP110]], align 8
2253 // CHECK2-NEXT:    [[TMP111:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS26]], i32 0, i32 3
2254 // CHECK2-NEXT:    [[TMP112:%.*]] = bitcast i8** [[TMP111]] to float**
2255 // CHECK2-NEXT:    store float* [[VLA]], float** [[TMP112]], align 8
2256 // CHECK2-NEXT:    [[TMP113:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS27]], i32 0, i32 3
2257 // CHECK2-NEXT:    [[TMP114:%.*]] = bitcast i8** [[TMP113]] to float**
2258 // CHECK2-NEXT:    store float* [[VLA]], float** [[TMP114]], align 8
2259 // CHECK2-NEXT:    [[TMP115:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3
2260 // CHECK2-NEXT:    store i64 [[TMP92]], i64* [[TMP115]], align 8
2261 // CHECK2-NEXT:    [[TMP116:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS28]], i64 0, i64 3
2262 // CHECK2-NEXT:    store i8* null, i8** [[TMP116]], align 8
2263 // CHECK2-NEXT:    [[TMP117:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS26]], i32 0, i32 4
2264 // CHECK2-NEXT:    [[TMP118:%.*]] = bitcast i8** [[TMP117]] to [5 x [10 x double]]**
2265 // CHECK2-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP118]], align 8
2266 // CHECK2-NEXT:    [[TMP119:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS27]], i32 0, i32 4
2267 // CHECK2-NEXT:    [[TMP120:%.*]] = bitcast i8** [[TMP119]] to [5 x [10 x double]]**
2268 // CHECK2-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP120]], align 8
2269 // CHECK2-NEXT:    [[TMP121:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS28]], i64 0, i64 4
2270 // CHECK2-NEXT:    store i8* null, i8** [[TMP121]], align 8
2271 // CHECK2-NEXT:    [[TMP122:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS26]], i32 0, i32 5
2272 // CHECK2-NEXT:    [[TMP123:%.*]] = bitcast i8** [[TMP122]] to i64*
2273 // CHECK2-NEXT:    store i64 5, i64* [[TMP123]], align 8
2274 // CHECK2-NEXT:    [[TMP124:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS27]], i32 0, i32 5
2275 // CHECK2-NEXT:    [[TMP125:%.*]] = bitcast i8** [[TMP124]] to i64*
2276 // CHECK2-NEXT:    store i64 5, i64* [[TMP125]], align 8
2277 // CHECK2-NEXT:    [[TMP126:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS28]], i64 0, i64 5
2278 // CHECK2-NEXT:    store i8* null, i8** [[TMP126]], align 8
2279 // CHECK2-NEXT:    [[TMP127:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS26]], i32 0, i32 6
2280 // CHECK2-NEXT:    [[TMP128:%.*]] = bitcast i8** [[TMP127]] to i64*
2281 // CHECK2-NEXT:    store i64 [[TMP5]], i64* [[TMP128]], align 8
2282 // CHECK2-NEXT:    [[TMP129:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS27]], i32 0, i32 6
2283 // CHECK2-NEXT:    [[TMP130:%.*]] = bitcast i8** [[TMP129]] to i64*
2284 // CHECK2-NEXT:    store i64 [[TMP5]], i64* [[TMP130]], align 8
2285 // CHECK2-NEXT:    [[TMP131:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS28]], i64 0, i64 6
2286 // CHECK2-NEXT:    store i8* null, i8** [[TMP131]], align 8
2287 // CHECK2-NEXT:    [[TMP132:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS26]], i32 0, i32 7
2288 // CHECK2-NEXT:    [[TMP133:%.*]] = bitcast i8** [[TMP132]] to double**
2289 // CHECK2-NEXT:    store double* [[VLA1]], double** [[TMP133]], align 8
2290 // CHECK2-NEXT:    [[TMP134:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS27]], i32 0, i32 7
2291 // CHECK2-NEXT:    [[TMP135:%.*]] = bitcast i8** [[TMP134]] to double**
2292 // CHECK2-NEXT:    store double* [[VLA1]], double** [[TMP135]], align 8
2293 // CHECK2-NEXT:    [[TMP136:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7
2294 // CHECK2-NEXT:    store i64 [[TMP94]], i64* [[TMP136]], align 8
2295 // CHECK2-NEXT:    [[TMP137:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS28]], i64 0, i64 7
2296 // CHECK2-NEXT:    store i8* null, i8** [[TMP137]], align 8
2297 // CHECK2-NEXT:    [[TMP138:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS26]], i32 0, i32 8
2298 // CHECK2-NEXT:    [[TMP139:%.*]] = bitcast i8** [[TMP138]] to %struct.TT**
2299 // CHECK2-NEXT:    store %struct.TT* [[D]], %struct.TT** [[TMP139]], align 8
2300 // CHECK2-NEXT:    [[TMP140:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS27]], i32 0, i32 8
2301 // CHECK2-NEXT:    [[TMP141:%.*]] = bitcast i8** [[TMP140]] to %struct.TT**
2302 // CHECK2-NEXT:    store %struct.TT* [[D]], %struct.TT** [[TMP141]], align 8
2303 // CHECK2-NEXT:    [[TMP142:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS28]], i64 0, i64 8
2304 // CHECK2-NEXT:    store i8* null, i8** [[TMP142]], align 8
2305 // CHECK2-NEXT:    [[TMP143:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS26]], i32 0, i32 0
2306 // CHECK2-NEXT:    [[TMP144:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS27]], i32 0, i32 0
2307 // CHECK2-NEXT:    [[TMP145:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
2308 // CHECK2-NEXT:    call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10)
2309 // CHECK2-NEXT:    [[TMP146:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142.region_id, i32 9, i8** [[TMP143]], i8** [[TMP144]], i64* [[TMP145]], i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_maptypes.11, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1)
2310 // CHECK2-NEXT:    [[TMP147:%.*]] = icmp ne i32 [[TMP146]], 0
2311 // CHECK2-NEXT:    br i1 [[TMP147]], label [[OMP_OFFLOAD_FAILED30:%.*]], label [[OMP_OFFLOAD_CONT31:%.*]]
2312 // CHECK2:       omp_offload.failed30:
2313 // CHECK2-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i64 [[TMP90]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR4]]
2314 // CHECK2-NEXT:    br label [[OMP_OFFLOAD_CONT31]]
2315 // CHECK2:       omp_offload.cont31:
2316 // CHECK2-NEXT:    br label [[OMP_IF_END33:%.*]]
2317 // CHECK2:       omp_if.else32:
2318 // CHECK2-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i64 [[TMP90]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR4]]
2319 // CHECK2-NEXT:    br label [[OMP_IF_END33]]
2320 // CHECK2:       omp_if.end33:
2321 // CHECK2-NEXT:    [[TMP148:%.*]] = load i32, i32* [[A]], align 4
2322 // CHECK2-NEXT:    [[TMP149:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
2323 // CHECK2-NEXT:    call void @llvm.stackrestore(i8* [[TMP149]])
2324 // CHECK2-NEXT:    ret i32 [[TMP148]]
2325 //
2326 //
2327 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97
2328 // CHECK2-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] {
2329 // CHECK2-NEXT:  entry:
2330 // CHECK2-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
2331 // CHECK2-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
2332 // CHECK2-NEXT:    [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8
2333 // CHECK2-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
2334 // CHECK2-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]])
2335 // CHECK2-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
2336 // CHECK2-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
2337 // CHECK2-NEXT:    store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8
2338 // CHECK2-NEXT:    [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
2339 // CHECK2-NEXT:    [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
2340 // CHECK2-NEXT:    [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32*
2341 // CHECK2-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 4
2342 // CHECK2-NEXT:    [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 4
2343 // CHECK2-NEXT:    call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
2344 // CHECK2-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
2345 // CHECK2-NEXT:    [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
2346 // CHECK2-NEXT:    store i16 [[TMP3]], i16* [[CONV5]], align 2
2347 // CHECK2-NEXT:    [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
2348 // CHECK2-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]])
2349 // CHECK2-NEXT:    ret void
2350 //
2351 //
2352 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined.
2353 // CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR3:[0-9]+]] {
2354 // CHECK2-NEXT:  entry:
2355 // CHECK2-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
2356 // CHECK2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
2357 // CHECK2-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
2358 // CHECK2-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
2359 // CHECK2-NEXT:    [[TMP:%.*]] = alloca i32, align 4
2360 // CHECK2-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
2361 // CHECK2-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
2362 // CHECK2-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2363 // CHECK2-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2364 // CHECK2-NEXT:    [[I:%.*]] = alloca i32, align 4
2365 // CHECK2-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
2366 // CHECK2-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
2367 // CHECK2-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
2368 // CHECK2-NEXT:    [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
2369 // CHECK2-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
2370 // CHECK2-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
2371 // CHECK2-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
2372 // CHECK2-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
2373 // CHECK2-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
2374 // CHECK2-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
2375 // CHECK2-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
2376 // CHECK2-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2377 // CHECK2-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
2378 // CHECK2-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2379 // CHECK2:       cond.true:
2380 // CHECK2-NEXT:    br label [[COND_END:%.*]]
2381 // CHECK2:       cond.false:
2382 // CHECK2-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2383 // CHECK2-NEXT:    br label [[COND_END]]
2384 // CHECK2:       cond.end:
2385 // CHECK2-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
2386 // CHECK2-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
2387 // CHECK2-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
2388 // CHECK2-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
2389 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
2390 // CHECK2:       omp.inner.for.cond:
2391 // CHECK2-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
2392 // CHECK2-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !10
2393 // CHECK2-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
2394 // CHECK2-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2395 // CHECK2:       omp.inner.for.body:
2396 // CHECK2-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
2397 // CHECK2-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
2398 // CHECK2-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
2399 // CHECK2-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10
2400 // CHECK2-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
2401 // CHECK2:       omp.body.continue:
2402 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
2403 // CHECK2:       omp.inner.for.inc:
2404 // CHECK2-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
2405 // CHECK2-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
2406 // CHECK2-NEXT:    store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
2407 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]
2408 // CHECK2:       omp.inner.for.end:
2409 // CHECK2-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
2410 // CHECK2:       omp.loop.exit:
2411 // CHECK2-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
2412 // CHECK2-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
2413 // CHECK2-NEXT:    [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0
2414 // CHECK2-NEXT:    br i1 [[TMP10]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
2415 // CHECK2:       .omp.final.then:
2416 // CHECK2-NEXT:    store i32 10, i32* [[I]], align 4
2417 // CHECK2-NEXT:    br label [[DOTOMP_FINAL_DONE]]
2418 // CHECK2:       .omp.final.done:
2419 // CHECK2-NEXT:    ret void
2420 //
2421 //
2422 // CHECK2-LABEL: define {{[^@]+}}@.omp_task_privates_map.
2423 // CHECK2-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], i16** noalias noundef [[TMP1:%.*]], [3 x i8*]** noalias noundef [[TMP2:%.*]], [3 x i8*]** noalias noundef [[TMP3:%.*]], [3 x i64]** noalias noundef [[TMP4:%.*]]) #[[ATTR5:[0-9]+]] {
2424 // CHECK2-NEXT:  entry:
2425 // CHECK2-NEXT:    [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 8
2426 // CHECK2-NEXT:    [[DOTADDR1:%.*]] = alloca i16**, align 8
2427 // CHECK2-NEXT:    [[DOTADDR2:%.*]] = alloca [3 x i8*]**, align 8
2428 // CHECK2-NEXT:    [[DOTADDR3:%.*]] = alloca [3 x i8*]**, align 8
2429 // CHECK2-NEXT:    [[DOTADDR4:%.*]] = alloca [3 x i64]**, align 8
2430 // CHECK2-NEXT:    store %struct..kmp_privates.t* [[TMP0]], %struct..kmp_privates.t** [[DOTADDR]], align 8
2431 // CHECK2-NEXT:    store i16** [[TMP1]], i16*** [[DOTADDR1]], align 8
2432 // CHECK2-NEXT:    store [3 x i8*]** [[TMP2]], [3 x i8*]*** [[DOTADDR2]], align 8
2433 // CHECK2-NEXT:    store [3 x i8*]** [[TMP3]], [3 x i8*]*** [[DOTADDR3]], align 8
2434 // CHECK2-NEXT:    store [3 x i64]** [[TMP4]], [3 x i64]*** [[DOTADDR4]], align 8
2435 // CHECK2-NEXT:    [[TMP5:%.*]] = load %struct..kmp_privates.t*, %struct..kmp_privates.t** [[DOTADDR]], align 8
2436 // CHECK2-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 0
2437 // CHECK2-NEXT:    [[TMP7:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR2]], align 8
2438 // CHECK2-NEXT:    store [3 x i8*]* [[TMP6]], [3 x i8*]** [[TMP7]], align 8
2439 // CHECK2-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 1
2440 // CHECK2-NEXT:    [[TMP9:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR3]], align 8
2441 // CHECK2-NEXT:    store [3 x i8*]* [[TMP8]], [3 x i8*]** [[TMP9]], align 8
2442 // CHECK2-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 2
2443 // CHECK2-NEXT:    [[TMP11:%.*]] = load [3 x i64]**, [3 x i64]*** [[DOTADDR4]], align 8
2444 // CHECK2-NEXT:    store [3 x i64]* [[TMP10]], [3 x i64]** [[TMP11]], align 8
2445 // CHECK2-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 3
2446 // CHECK2-NEXT:    [[TMP13:%.*]] = load i16**, i16*** [[DOTADDR1]], align 8
2447 // CHECK2-NEXT:    store i16* [[TMP12]], i16** [[TMP13]], align 8
2448 // CHECK2-NEXT:    ret void
2449 //
2450 //
2451 // CHECK2-LABEL: define {{[^@]+}}@.omp_task_entry.
2452 // CHECK2-SAME: (i32 noundef signext [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] {
2453 // CHECK2-NEXT:  entry:
2454 // CHECK2-NEXT:    [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
2455 // CHECK2-NEXT:    [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8
2456 // CHECK2-NEXT:    [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8
2457 // CHECK2-NEXT:    [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8
2458 // CHECK2-NEXT:    [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8
2459 // CHECK2-NEXT:    [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 8
2460 // CHECK2-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca i16*, align 8
2461 // CHECK2-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca [3 x i8*]*, align 8
2462 // CHECK2-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca [3 x i8*]*, align 8
2463 // CHECK2-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca [3 x i64]*, align 8
2464 // CHECK2-NEXT:    [[AA_CASTED_I:%.*]] = alloca i64, align 8
2465 // CHECK2-NEXT:    [[DOTCAPTURE_EXPR__CASTED_I:%.*]] = alloca i64, align 8
2466 // CHECK2-NEXT:    [[DOTCAPTURE_EXPR__CASTED5_I:%.*]] = alloca i64, align 8
2467 // CHECK2-NEXT:    [[DOTADDR:%.*]] = alloca i32, align 4
2468 // CHECK2-NEXT:    [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8
2469 // CHECK2-NEXT:    store i32 [[TMP0]], i32* [[DOTADDR]], align 4
2470 // CHECK2-NEXT:    store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8
2471 // CHECK2-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4
2472 // CHECK2-NEXT:    [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8
2473 // CHECK2-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
2474 // CHECK2-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
2475 // CHECK2-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0
2476 // CHECK2-NEXT:    [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8
2477 // CHECK2-NEXT:    [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon*
2478 // CHECK2-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1
2479 // CHECK2-NEXT:    [[TMP10:%.*]] = bitcast %struct..kmp_privates.t* [[TMP9]] to i8*
2480 // CHECK2-NEXT:    [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8*
2481 // CHECK2-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META17:![0-9]+]])
2482 // CHECK2-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]])
2483 // CHECK2-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META22:![0-9]+]])
2484 // CHECK2-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META24:![0-9]+]])
2485 // CHECK2-NEXT:    store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !26
2486 // CHECK2-NEXT:    store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !26
2487 // CHECK2-NEXT:    store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !26
2488 // CHECK2-NEXT:    store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* @.omp_task_privates_map. to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !26
2489 // CHECK2-NEXT:    store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !26
2490 // CHECK2-NEXT:    store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !26
2491 // CHECK2-NEXT:    [[TMP12:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !26
2492 // CHECK2-NEXT:    [[TMP13:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !26
2493 // CHECK2-NEXT:    [[TMP14:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !26
2494 // CHECK2-NEXT:    [[TMP15:%.*]] = bitcast void (i8*, ...)* [[TMP13]] to void (i8*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)*
2495 // CHECK2-NEXT:    call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR4]]
2496 // CHECK2-NEXT:    [[TMP16:%.*]] = load i16*, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !26
2497 // CHECK2-NEXT:    [[TMP17:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !26
2498 // CHECK2-NEXT:    [[TMP18:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 8, !noalias !26
2499 // CHECK2-NEXT:    [[TMP19:%.*]] = load [3 x i64]*, [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 8, !noalias !26
2500 // CHECK2-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP17]], i64 0, i64 0
2501 // CHECK2-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP18]], i64 0, i64 0
2502 // CHECK2-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[TMP19]], i64 0, i64 0
2503 // CHECK2-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP12]], i32 0, i32 1
2504 // CHECK2-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[TMP12]], i32 0, i32 2
2505 // CHECK2-NEXT:    [[TMP25:%.*]] = load i32, i32* [[TMP23]], align 4
2506 // CHECK2-NEXT:    call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) #[[ATTR4]]
2507 // CHECK2-NEXT:    [[TMP26:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 [[TMP25]], i32 1, i32 0, i8* null, i32 0, i8* null) #[[ATTR4]]
2508 // CHECK2-NEXT:    [[TMP27:%.*]] = icmp ne i32 [[TMP26]], 0
2509 // CHECK2-NEXT:    br i1 [[TMP27]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]]
2510 // CHECK2:       omp_offload.failed.i:
2511 // CHECK2-NEXT:    [[TMP28:%.*]] = load i16, i16* [[TMP16]], align 2
2512 // CHECK2-NEXT:    [[CONV_I:%.*]] = bitcast i64* [[AA_CASTED_I]] to i16*
2513 // CHECK2-NEXT:    store i16 [[TMP28]], i16* [[CONV_I]], align 2, !noalias !26
2514 // CHECK2-NEXT:    [[TMP29:%.*]] = load i64, i64* [[AA_CASTED_I]], align 8, !noalias !26
2515 // CHECK2-NEXT:    [[TMP30:%.*]] = load i32, i32* [[TMP23]], align 4
2516 // CHECK2-NEXT:    [[CONV4_I:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED_I]] to i32*
2517 // CHECK2-NEXT:    store i32 [[TMP30]], i32* [[CONV4_I]], align 4, !noalias !26
2518 // CHECK2-NEXT:    [[TMP31:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED_I]], align 8, !noalias !26
2519 // CHECK2-NEXT:    [[TMP32:%.*]] = load i32, i32* [[TMP24]], align 4
2520 // CHECK2-NEXT:    [[CONV6_I:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED5_I]] to i32*
2521 // CHECK2-NEXT:    store i32 [[TMP32]], i32* [[CONV6_I]], align 4, !noalias !26
2522 // CHECK2-NEXT:    [[TMP33:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED5_I]], align 8, !noalias !26
2523 // CHECK2-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97(i64 [[TMP29]], i64 [[TMP31]], i64 [[TMP33]]) #[[ATTR4]]
2524 // CHECK2-NEXT:    br label [[DOTOMP_OUTLINED__1_EXIT]]
2525 // CHECK2:       .omp_outlined..1.exit:
2526 // CHECK2-NEXT:    ret i32 0
2527 //
2528 //
2529 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104
2530 // CHECK2-SAME: (i64 noundef [[A:%.*]]) #[[ATTR3]] {
2531 // CHECK2-NEXT:  entry:
2532 // CHECK2-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
2533 // CHECK2-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
2534 // CHECK2-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
2535 // CHECK2-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
2536 // CHECK2-NEXT:    [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
2537 // CHECK2-NEXT:    [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32*
2538 // CHECK2-NEXT:    store i32 [[TMP0]], i32* [[CONV1]], align 4
2539 // CHECK2-NEXT:    [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
2540 // CHECK2-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]])
2541 // CHECK2-NEXT:    ret void
2542 //
2543 //
2544 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..2
2545 // CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]]) #[[ATTR3]] {
2546 // CHECK2-NEXT:  entry:
2547 // CHECK2-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
2548 // CHECK2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
2549 // CHECK2-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
2550 // CHECK2-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
2551 // CHECK2-NEXT:    [[TMP:%.*]] = alloca i32, align 4
2552 // CHECK2-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
2553 // CHECK2-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
2554 // CHECK2-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2555 // CHECK2-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2556 // CHECK2-NEXT:    [[A1:%.*]] = alloca i32, align 4
2557 // CHECK2-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
2558 // CHECK2-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
2559 // CHECK2-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
2560 // CHECK2-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
2561 // CHECK2-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
2562 // CHECK2-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
2563 // CHECK2-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
2564 // CHECK2-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
2565 // CHECK2-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
2566 // CHECK2-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
2567 // CHECK2-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
2568 // CHECK2-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2569 // CHECK2-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
2570 // CHECK2-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2571 // CHECK2:       cond.true:
2572 // CHECK2-NEXT:    br label [[COND_END:%.*]]
2573 // CHECK2:       cond.false:
2574 // CHECK2-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2575 // CHECK2-NEXT:    br label [[COND_END]]
2576 // CHECK2:       cond.end:
2577 // CHECK2-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
2578 // CHECK2-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
2579 // CHECK2-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
2580 // CHECK2-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
2581 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
2582 // CHECK2:       omp.inner.for.cond:
2583 // CHECK2-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2584 // CHECK2-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2585 // CHECK2-NEXT:    [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
2586 // CHECK2-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2587 // CHECK2:       omp.inner.for.body:
2588 // CHECK2-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2589 // CHECK2-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
2590 // CHECK2-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
2591 // CHECK2-NEXT:    store i32 [[ADD]], i32* [[A1]], align 4
2592 // CHECK2-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A1]], align 4
2593 // CHECK2-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
2594 // CHECK2-NEXT:    store i32 [[ADD3]], i32* [[A1]], align 4
2595 // CHECK2-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
2596 // CHECK2:       omp.body.continue:
2597 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
2598 // CHECK2:       omp.inner.for.inc:
2599 // CHECK2-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2600 // CHECK2-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP9]], 1
2601 // CHECK2-NEXT:    store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4
2602 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP27:![0-9]+]]
2603 // CHECK2:       omp.inner.for.end:
2604 // CHECK2-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
2605 // CHECK2:       omp.loop.exit:
2606 // CHECK2-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
2607 // CHECK2-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
2608 // CHECK2-NEXT:    [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0
2609 // CHECK2-NEXT:    br i1 [[TMP11]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
2610 // CHECK2:       .omp.final.then:
2611 // CHECK2-NEXT:    store i32 10, i32* [[CONV]], align 4
2612 // CHECK2-NEXT:    br label [[DOTOMP_FINAL_DONE]]
2613 // CHECK2:       .omp.final.done:
2614 // CHECK2-NEXT:    ret void
2615 //
2616 //
2617 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111
2618 // CHECK2-SAME: (i64 noundef [[AA:%.*]]) #[[ATTR2]] {
2619 // CHECK2-NEXT:  entry:
2620 // CHECK2-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
2621 // CHECK2-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
2622 // CHECK2-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
2623 // CHECK2-NEXT:    [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
2624 // CHECK2-NEXT:    [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
2625 // CHECK2-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
2626 // CHECK2-NEXT:    store i16 [[TMP0]], i16* [[CONV1]], align 2
2627 // CHECK2-NEXT:    [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
2628 // CHECK2-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP1]])
2629 // CHECK2-NEXT:    ret void
2630 //
2631 //
2632 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..3
2633 // CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR3]] {
2634 // CHECK2-NEXT:  entry:
2635 // CHECK2-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
2636 // CHECK2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
2637 // CHECK2-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
2638 // CHECK2-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
2639 // CHECK2-NEXT:    [[TMP:%.*]] = alloca i32, align 4
2640 // CHECK2-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
2641 // CHECK2-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
2642 // CHECK2-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2643 // CHECK2-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2644 // CHECK2-NEXT:    [[I:%.*]] = alloca i32, align 4
2645 // CHECK2-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
2646 // CHECK2-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
2647 // CHECK2-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
2648 // CHECK2-NEXT:    [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
2649 // CHECK2-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
2650 // CHECK2-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
2651 // CHECK2-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
2652 // CHECK2-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
2653 // CHECK2-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
2654 // CHECK2-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
2655 // CHECK2-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
2656 // CHECK2-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2657 // CHECK2-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
2658 // CHECK2-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2659 // CHECK2:       cond.true:
2660 // CHECK2-NEXT:    br label [[COND_END:%.*]]
2661 // CHECK2:       cond.false:
2662 // CHECK2-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2663 // CHECK2-NEXT:    br label [[COND_END]]
2664 // CHECK2:       cond.end:
2665 // CHECK2-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
2666 // CHECK2-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
2667 // CHECK2-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
2668 // CHECK2-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
2669 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
2670 // CHECK2:       omp.inner.for.cond:
2671 // CHECK2-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !29
2672 // CHECK2-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !29
2673 // CHECK2-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
2674 // CHECK2-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2675 // CHECK2:       omp.inner.for.body:
2676 // CHECK2-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !29
2677 // CHECK2-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
2678 // CHECK2-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
2679 // CHECK2-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !29
2680 // CHECK2-NEXT:    [[TMP8:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !29
2681 // CHECK2-NEXT:    [[CONV2:%.*]] = sext i16 [[TMP8]] to i32
2682 // CHECK2-NEXT:    [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
2683 // CHECK2-NEXT:    [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
2684 // CHECK2-NEXT:    store i16 [[CONV4]], i16* [[CONV]], align 2, !llvm.access.group !29
2685 // CHECK2-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
2686 // CHECK2:       omp.body.continue:
2687 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
2688 // CHECK2:       omp.inner.for.inc:
2689 // CHECK2-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !29
2690 // CHECK2-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP9]], 1
2691 // CHECK2-NEXT:    store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !29
2692 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP30:![0-9]+]]
2693 // CHECK2:       omp.inner.for.end:
2694 // CHECK2-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
2695 // CHECK2:       omp.loop.exit:
2696 // CHECK2-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
2697 // CHECK2-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
2698 // CHECK2-NEXT:    [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0
2699 // CHECK2-NEXT:    br i1 [[TMP11]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
2700 // CHECK2:       .omp.final.then:
2701 // CHECK2-NEXT:    store i32 10, i32* [[I]], align 4
2702 // CHECK2-NEXT:    br label [[DOTOMP_FINAL_DONE]]
2703 // CHECK2:       .omp.final.done:
2704 // CHECK2-NEXT:    ret void
2705 //
2706 //
2707 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118
2708 // CHECK2-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] {
2709 // CHECK2-NEXT:  entry:
2710 // CHECK2-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
2711 // CHECK2-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
2712 // CHECK2-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
2713 // CHECK2-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
2714 // CHECK2-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
2715 // CHECK2-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
2716 // CHECK2-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
2717 // CHECK2-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
2718 // CHECK2-NEXT:    [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
2719 // CHECK2-NEXT:    [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
2720 // CHECK2-NEXT:    store i32 [[TMP0]], i32* [[CONV2]], align 4
2721 // CHECK2-NEXT:    [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
2722 // CHECK2-NEXT:    [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
2723 // CHECK2-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
2724 // CHECK2-NEXT:    store i16 [[TMP2]], i16* [[CONV3]], align 2
2725 // CHECK2-NEXT:    [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
2726 // CHECK2-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
2727 // CHECK2-NEXT:    ret void
2728 //
2729 //
2730 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..6
2731 // CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR3]] {
2732 // CHECK2-NEXT:  entry:
2733 // CHECK2-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
2734 // CHECK2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
2735 // CHECK2-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
2736 // CHECK2-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
2737 // CHECK2-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
2738 // CHECK2-NEXT:    [[TMP:%.*]] = alloca i32, align 4
2739 // CHECK2-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
2740 // CHECK2-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
2741 // CHECK2-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2742 // CHECK2-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2743 // CHECK2-NEXT:    [[I:%.*]] = alloca i32, align 4
2744 // CHECK2-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
2745 // CHECK2-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
2746 // CHECK2-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
2747 // CHECK2-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
2748 // CHECK2-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
2749 // CHECK2-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
2750 // CHECK2-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
2751 // CHECK2-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
2752 // CHECK2-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
2753 // CHECK2-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
2754 // CHECK2-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
2755 // CHECK2-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
2756 // CHECK2-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
2757 // CHECK2-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2758 // CHECK2-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
2759 // CHECK2-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2760 // CHECK2:       cond.true:
2761 // CHECK2-NEXT:    br label [[COND_END:%.*]]
2762 // CHECK2:       cond.false:
2763 // CHECK2-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2764 // CHECK2-NEXT:    br label [[COND_END]]
2765 // CHECK2:       cond.end:
2766 // CHECK2-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
2767 // CHECK2-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
2768 // CHECK2-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
2769 // CHECK2-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
2770 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
2771 // CHECK2:       omp.inner.for.cond:
2772 // CHECK2-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !32
2773 // CHECK2-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !32
2774 // CHECK2-NEXT:    [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
2775 // CHECK2-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2776 // CHECK2:       omp.inner.for.body:
2777 // CHECK2-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !32
2778 // CHECK2-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
2779 // CHECK2-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
2780 // CHECK2-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !32
2781 // CHECK2-NEXT:    [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !32
2782 // CHECK2-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
2783 // CHECK2-NEXT:    store i32 [[ADD3]], i32* [[CONV]], align 4, !llvm.access.group !32
2784 // CHECK2-NEXT:    [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 2, !llvm.access.group !32
2785 // CHECK2-NEXT:    [[CONV4:%.*]] = sext i16 [[TMP9]] to i32
2786 // CHECK2-NEXT:    [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
2787 // CHECK2-NEXT:    [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
2788 // CHECK2-NEXT:    store i16 [[CONV6]], i16* [[CONV1]], align 2, !llvm.access.group !32
2789 // CHECK2-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
2790 // CHECK2:       omp.body.continue:
2791 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
2792 // CHECK2:       omp.inner.for.inc:
2793 // CHECK2-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !32
2794 // CHECK2-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1
2795 // CHECK2-NEXT:    store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !32
2796 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP33:![0-9]+]]
2797 // CHECK2:       omp.inner.for.end:
2798 // CHECK2-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
2799 // CHECK2:       omp.loop.exit:
2800 // CHECK2-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
2801 // CHECK2-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
2802 // CHECK2-NEXT:    [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
2803 // CHECK2-NEXT:    br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
2804 // CHECK2:       .omp.final.then:
2805 // CHECK2-NEXT:    store i32 10, i32* [[I]], align 4
2806 // CHECK2-NEXT:    br label [[DOTOMP_FINAL_DONE]]
2807 // CHECK2:       .omp.final.done:
2808 // CHECK2-NEXT:    ret void
2809 //
2810 //
2811 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142
2812 // CHECK2-SAME: (i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] {
2813 // CHECK2-NEXT:  entry:
2814 // CHECK2-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
2815 // CHECK2-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
2816 // CHECK2-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
2817 // CHECK2-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 8
2818 // CHECK2-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
2819 // CHECK2-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
2820 // CHECK2-NEXT:    [[VLA_ADDR4:%.*]] = alloca i64, align 8
2821 // CHECK2-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 8
2822 // CHECK2-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
2823 // CHECK2-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
2824 // CHECK2-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
2825 // CHECK2-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
2826 // CHECK2-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
2827 // CHECK2-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 8
2828 // CHECK2-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
2829 // CHECK2-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
2830 // CHECK2-NEXT:    store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
2831 // CHECK2-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 8
2832 // CHECK2-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
2833 // CHECK2-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
2834 // CHECK2-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
2835 // CHECK2-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
2836 // CHECK2-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
2837 // CHECK2-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
2838 // CHECK2-NEXT:    [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
2839 // CHECK2-NEXT:    [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
2840 // CHECK2-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
2841 // CHECK2-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
2842 // CHECK2-NEXT:    [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
2843 // CHECK2-NEXT:    [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
2844 // CHECK2-NEXT:    store i32 [[TMP8]], i32* [[CONV5]], align 4
2845 // CHECK2-NEXT:    [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
2846 // CHECK2-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]])
2847 // CHECK2-NEXT:    ret void
2848 //
2849 //
2850 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..9
2851 // CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR3]] {
2852 // CHECK2-NEXT:  entry:
2853 // CHECK2-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
2854 // CHECK2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
2855 // CHECK2-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
2856 // CHECK2-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
2857 // CHECK2-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
2858 // CHECK2-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 8
2859 // CHECK2-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
2860 // CHECK2-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
2861 // CHECK2-NEXT:    [[VLA_ADDR4:%.*]] = alloca i64, align 8
2862 // CHECK2-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 8
2863 // CHECK2-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
2864 // CHECK2-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
2865 // CHECK2-NEXT:    [[TMP:%.*]] = alloca i32, align 4
2866 // CHECK2-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
2867 // CHECK2-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
2868 // CHECK2-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2869 // CHECK2-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2870 // CHECK2-NEXT:    [[I:%.*]] = alloca i32, align 4
2871 // CHECK2-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
2872 // CHECK2-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
2873 // CHECK2-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
2874 // CHECK2-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
2875 // CHECK2-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
2876 // CHECK2-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 8
2877 // CHECK2-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
2878 // CHECK2-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
2879 // CHECK2-NEXT:    store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
2880 // CHECK2-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 8
2881 // CHECK2-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
2882 // CHECK2-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
2883 // CHECK2-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
2884 // CHECK2-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
2885 // CHECK2-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
2886 // CHECK2-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
2887 // CHECK2-NEXT:    [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
2888 // CHECK2-NEXT:    [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
2889 // CHECK2-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
2890 // CHECK2-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
2891 // CHECK2-NEXT:    [[ARRAYDECAY:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 0
2892 // CHECK2-NEXT:    call void @llvm.assume(i1 true) [ "align"(float* [[ARRAYDECAY]], i64 16) ]
2893 // CHECK2-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
2894 // CHECK2-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
2895 // CHECK2-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
2896 // CHECK2-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
2897 // CHECK2-NEXT:    [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
2898 // CHECK2-NEXT:    [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4
2899 // CHECK2-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
2900 // CHECK2-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2901 // CHECK2-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP10]], 9
2902 // CHECK2-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2903 // CHECK2:       cond.true:
2904 // CHECK2-NEXT:    br label [[COND_END:%.*]]
2905 // CHECK2:       cond.false:
2906 // CHECK2-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2907 // CHECK2-NEXT:    br label [[COND_END]]
2908 // CHECK2:       cond.end:
2909 // CHECK2-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ]
2910 // CHECK2-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
2911 // CHECK2-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
2912 // CHECK2-NEXT:    store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4
2913 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
2914 // CHECK2:       omp.inner.for.cond:
2915 // CHECK2-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !35
2916 // CHECK2-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !35
2917 // CHECK2-NEXT:    [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
2918 // CHECK2-NEXT:    br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2919 // CHECK2:       omp.inner.for.body:
2920 // CHECK2-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !35
2921 // CHECK2-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1
2922 // CHECK2-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
2923 // CHECK2-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !35
2924 // CHECK2-NEXT:    [[TMP16:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !35
2925 // CHECK2-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP16]], 1
2926 // CHECK2-NEXT:    store i32 [[ADD6]], i32* [[CONV]], align 4, !llvm.access.group !35
2927 // CHECK2-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
2928 // CHECK2-NEXT:    [[TMP17:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !35
2929 // CHECK2-NEXT:    [[CONV7:%.*]] = fpext float [[TMP17]] to double
2930 // CHECK2-NEXT:    [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00
2931 // CHECK2-NEXT:    [[CONV9:%.*]] = fptrunc double [[ADD8]] to float
2932 // CHECK2-NEXT:    store float [[CONV9]], float* [[ARRAYIDX]], align 4, !llvm.access.group !35
2933 // CHECK2-NEXT:    [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3
2934 // CHECK2-NEXT:    [[TMP18:%.*]] = load float, float* [[ARRAYIDX10]], align 4, !llvm.access.group !35
2935 // CHECK2-NEXT:    [[CONV11:%.*]] = fpext float [[TMP18]] to double
2936 // CHECK2-NEXT:    [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00
2937 // CHECK2-NEXT:    [[CONV13:%.*]] = fptrunc double [[ADD12]] to float
2938 // CHECK2-NEXT:    store float [[CONV13]], float* [[ARRAYIDX10]], align 4, !llvm.access.group !35
2939 // CHECK2-NEXT:    [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1
2940 // CHECK2-NEXT:    [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX14]], i64 0, i64 2
2941 // CHECK2-NEXT:    [[TMP19:%.*]] = load double, double* [[ARRAYIDX15]], align 8, !llvm.access.group !35
2942 // CHECK2-NEXT:    [[ADD16:%.*]] = fadd double [[TMP19]], 1.000000e+00
2943 // CHECK2-NEXT:    store double [[ADD16]], double* [[ARRAYIDX15]], align 8, !llvm.access.group !35
2944 // CHECK2-NEXT:    [[TMP20:%.*]] = mul nsw i64 1, [[TMP5]]
2945 // CHECK2-NEXT:    [[ARRAYIDX17:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP20]]
2946 // CHECK2-NEXT:    [[ARRAYIDX18:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX17]], i64 3
2947 // CHECK2-NEXT:    [[TMP21:%.*]] = load double, double* [[ARRAYIDX18]], align 8, !llvm.access.group !35
2948 // CHECK2-NEXT:    [[ADD19:%.*]] = fadd double [[TMP21]], 1.000000e+00
2949 // CHECK2-NEXT:    store double [[ADD19]], double* [[ARRAYIDX18]], align 8, !llvm.access.group !35
2950 // CHECK2-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0
2951 // CHECK2-NEXT:    [[TMP22:%.*]] = load i64, i64* [[X]], align 8, !llvm.access.group !35
2952 // CHECK2-NEXT:    [[ADD20:%.*]] = add nsw i64 [[TMP22]], 1
2953 // CHECK2-NEXT:    store i64 [[ADD20]], i64* [[X]], align 8, !llvm.access.group !35
2954 // CHECK2-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1
2955 // CHECK2-NEXT:    [[TMP23:%.*]] = load i8, i8* [[Y]], align 8, !llvm.access.group !35
2956 // CHECK2-NEXT:    [[CONV21:%.*]] = sext i8 [[TMP23]] to i32
2957 // CHECK2-NEXT:    [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1
2958 // CHECK2-NEXT:    [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8
2959 // CHECK2-NEXT:    store i8 [[CONV23]], i8* [[Y]], align 8, !llvm.access.group !35
2960 // CHECK2-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
2961 // CHECK2:       omp.body.continue:
2962 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
2963 // CHECK2:       omp.inner.for.inc:
2964 // CHECK2-NEXT:    [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !35
2965 // CHECK2-NEXT:    [[ADD24:%.*]] = add nsw i32 [[TMP24]], 1
2966 // CHECK2-NEXT:    store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !35
2967 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP36:![0-9]+]]
2968 // CHECK2:       omp.inner.for.end:
2969 // CHECK2-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
2970 // CHECK2:       omp.loop.exit:
2971 // CHECK2-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]])
2972 // CHECK2-NEXT:    [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
2973 // CHECK2-NEXT:    [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
2974 // CHECK2-NEXT:    br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
2975 // CHECK2:       .omp.final.then:
2976 // CHECK2-NEXT:    store i32 10, i32* [[I]], align 4
2977 // CHECK2-NEXT:    br label [[DOTOMP_FINAL_DONE]]
2978 // CHECK2:       .omp.final.done:
2979 // CHECK2-NEXT:    ret void
2980 //
2981 //
2982 // CHECK2-LABEL: define {{[^@]+}}@_Z3bari
2983 // CHECK2-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {
2984 // CHECK2-NEXT:  entry:
2985 // CHECK2-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
2986 // CHECK2-NEXT:    [[A:%.*]] = alloca i32, align 4
2987 // CHECK2-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8
2988 // CHECK2-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
2989 // CHECK2-NEXT:    store i32 0, i32* [[A]], align 4
2990 // CHECK2-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
2991 // CHECK2-NEXT:    [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]])
2992 // CHECK2-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
2993 // CHECK2-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
2994 // CHECK2-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
2995 // CHECK2-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
2996 // CHECK2-NEXT:    [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP2]])
2997 // CHECK2-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
2998 // CHECK2-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
2999 // CHECK2-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
3000 // CHECK2-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
3001 // CHECK2-NEXT:    [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]])
3002 // CHECK2-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
3003 // CHECK2-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
3004 // CHECK2-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
3005 // CHECK2-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
3006 // CHECK2-NEXT:    [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]])
3007 // CHECK2-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
3008 // CHECK2-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
3009 // CHECK2-NEXT:    store i32 [[ADD6]], i32* [[A]], align 4
3010 // CHECK2-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
3011 // CHECK2-NEXT:    ret i32 [[TMP8]]
3012 //
3013 //
3014 // CHECK2-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
3015 // CHECK2-SAME: (%struct.S1* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 {
3016 // CHECK2-NEXT:  entry:
3017 // CHECK2-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
3018 // CHECK2-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
3019 // CHECK2-NEXT:    [[B:%.*]] = alloca i32, align 4
3020 // CHECK2-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 8
3021 // CHECK2-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
3022 // CHECK2-NEXT:    [[B_CASTED:%.*]] = alloca i64, align 8
3023 // CHECK2-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8
3024 // CHECK2-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8
3025 // CHECK2-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8
3026 // CHECK2-NEXT:    [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 8
3027 // CHECK2-NEXT:    [[TMP:%.*]] = alloca i32, align 4
3028 // CHECK2-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
3029 // CHECK2-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
3030 // CHECK2-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
3031 // CHECK2-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
3032 // CHECK2-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
3033 // CHECK2-NEXT:    store i32 [[ADD]], i32* [[B]], align 4
3034 // CHECK2-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
3035 // CHECK2-NEXT:    [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
3036 // CHECK2-NEXT:    [[TMP3:%.*]] = call i8* @llvm.stacksave()
3037 // CHECK2-NEXT:    store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8
3038 // CHECK2-NEXT:    [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]
3039 // CHECK2-NEXT:    [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2
3040 // CHECK2-NEXT:    store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8
3041 // CHECK2-NEXT:    [[TMP5:%.*]] = load i32, i32* [[B]], align 4
3042 // CHECK2-NEXT:    [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32*
3043 // CHECK2-NEXT:    store i32 [[TMP5]], i32* [[CONV]], align 4
3044 // CHECK2-NEXT:    [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8
3045 // CHECK2-NEXT:    [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4
3046 // CHECK2-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 60
3047 // CHECK2-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
3048 // CHECK2:       omp_if.then:
3049 // CHECK2-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
3050 // CHECK2-NEXT:    [[TMP8:%.*]] = mul nuw i64 2, [[TMP2]]
3051 // CHECK2-NEXT:    [[TMP9:%.*]] = mul nuw i64 [[TMP8]], 2
3052 // CHECK2-NEXT:    [[TMP10:%.*]] = bitcast [5 x i64]* [[DOTOFFLOAD_SIZES]] to i8*
3053 // CHECK2-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP10]], i8* align 8 bitcast ([5 x i64]* @.offload_sizes.13 to i8*), i64 40, i1 false)
3054 // CHECK2-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
3055 // CHECK2-NEXT:    [[TMP12:%.*]] = bitcast i8** [[TMP11]] to %struct.S1**
3056 // CHECK2-NEXT:    store %struct.S1* [[THIS1]], %struct.S1** [[TMP12]], align 8
3057 // CHECK2-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
3058 // CHECK2-NEXT:    [[TMP14:%.*]] = bitcast i8** [[TMP13]] to double**
3059 // CHECK2-NEXT:    store double* [[A]], double** [[TMP14]], align 8
3060 // CHECK2-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
3061 // CHECK2-NEXT:    store i8* null, i8** [[TMP15]], align 8
3062 // CHECK2-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
3063 // CHECK2-NEXT:    [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64*
3064 // CHECK2-NEXT:    store i64 [[TMP6]], i64* [[TMP17]], align 8
3065 // CHECK2-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
3066 // CHECK2-NEXT:    [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64*
3067 // CHECK2-NEXT:    store i64 [[TMP6]], i64* [[TMP19]], align 8
3068 // CHECK2-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
3069 // CHECK2-NEXT:    store i8* null, i8** [[TMP20]], align 8
3070 // CHECK2-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
3071 // CHECK2-NEXT:    [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i64*
3072 // CHECK2-NEXT:    store i64 2, i64* [[TMP22]], align 8
3073 // CHECK2-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
3074 // CHECK2-NEXT:    [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i64*
3075 // CHECK2-NEXT:    store i64 2, i64* [[TMP24]], align 8
3076 // CHECK2-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
3077 // CHECK2-NEXT:    store i8* null, i8** [[TMP25]], align 8
3078 // CHECK2-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
3079 // CHECK2-NEXT:    [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64*
3080 // CHECK2-NEXT:    store i64 [[TMP2]], i64* [[TMP27]], align 8
3081 // CHECK2-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
3082 // CHECK2-NEXT:    [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i64*
3083 // CHECK2-NEXT:    store i64 [[TMP2]], i64* [[TMP29]], align 8
3084 // CHECK2-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
3085 // CHECK2-NEXT:    store i8* null, i8** [[TMP30]], align 8
3086 // CHECK2-NEXT:    [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
3087 // CHECK2-NEXT:    [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i16**
3088 // CHECK2-NEXT:    store i16* [[VLA]], i16** [[TMP32]], align 8
3089 // CHECK2-NEXT:    [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
3090 // CHECK2-NEXT:    [[TMP34:%.*]] = bitcast i8** [[TMP33]] to i16**
3091 // CHECK2-NEXT:    store i16* [[VLA]], i16** [[TMP34]], align 8
3092 // CHECK2-NEXT:    [[TMP35:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4
3093 // CHECK2-NEXT:    store i64 [[TMP9]], i64* [[TMP35]], align 8
3094 // CHECK2-NEXT:    [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4
3095 // CHECK2-NEXT:    store i8* null, i8** [[TMP36]], align 8
3096 // CHECK2-NEXT:    [[TMP37:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
3097 // CHECK2-NEXT:    [[TMP38:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
3098 // CHECK2-NEXT:    [[TMP39:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
3099 // CHECK2-NEXT:    call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10)
3100 // CHECK2-NEXT:    [[TMP40:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215.region_id, i32 5, i8** [[TMP37]], i8** [[TMP38]], i64* [[TMP39]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.14, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1)
3101 // CHECK2-NEXT:    [[TMP41:%.*]] = icmp ne i32 [[TMP40]], 0
3102 // CHECK2-NEXT:    br i1 [[TMP41]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
3103 // CHECK2:       omp_offload.failed:
3104 // CHECK2-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR4]]
3105 // CHECK2-NEXT:    br label [[OMP_OFFLOAD_CONT]]
3106 // CHECK2:       omp_offload.cont:
3107 // CHECK2-NEXT:    br label [[OMP_IF_END:%.*]]
3108 // CHECK2:       omp_if.else:
3109 // CHECK2-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR4]]
3110 // CHECK2-NEXT:    br label [[OMP_IF_END]]
3111 // CHECK2:       omp_if.end:
3112 // CHECK2-NEXT:    [[TMP42:%.*]] = mul nsw i64 1, [[TMP2]]
3113 // CHECK2-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP42]]
3114 // CHECK2-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
3115 // CHECK2-NEXT:    [[TMP43:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2
3116 // CHECK2-NEXT:    [[CONV3:%.*]] = sext i16 [[TMP43]] to i32
3117 // CHECK2-NEXT:    [[TMP44:%.*]] = load i32, i32* [[B]], align 4
3118 // CHECK2-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], [[TMP44]]
3119 // CHECK2-NEXT:    [[TMP45:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
3120 // CHECK2-NEXT:    call void @llvm.stackrestore(i8* [[TMP45]])
3121 // CHECK2-NEXT:    ret i32 [[ADD4]]
3122 //
3123 //
3124 // CHECK2-LABEL: define {{[^@]+}}@_ZL7fstatici
3125 // CHECK2-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {
3126 // CHECK2-NEXT:  entry:
3127 // CHECK2-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
3128 // CHECK2-NEXT:    [[A:%.*]] = alloca i32, align 4
3129 // CHECK2-NEXT:    [[AA:%.*]] = alloca i16, align 2
3130 // CHECK2-NEXT:    [[AAA:%.*]] = alloca i8, align 1
3131 // CHECK2-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
3132 // CHECK2-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
3133 // CHECK2-NEXT:    [[N_CASTED:%.*]] = alloca i64, align 8
3134 // CHECK2-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
3135 // CHECK2-NEXT:    [[AAA_CASTED:%.*]] = alloca i64, align 8
3136 // CHECK2-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8
3137 // CHECK2-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8
3138 // CHECK2-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8
3139 // CHECK2-NEXT:    [[TMP:%.*]] = alloca i32, align 4
3140 // CHECK2-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
3141 // CHECK2-NEXT:    [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4
3142 // CHECK2-NEXT:    [[DOTCAPTURE_EXPR_5:%.*]] = alloca i32, align 4
3143 // CHECK2-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
3144 // CHECK2-NEXT:    store i32 0, i32* [[A]], align 4
3145 // CHECK2-NEXT:    store i16 0, i16* [[AA]], align 2
3146 // CHECK2-NEXT:    store i8 0, i8* [[AAA]], align 1
3147 // CHECK2-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
3148 // CHECK2-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32*
3149 // CHECK2-NEXT:    store i32 [[TMP0]], i32* [[CONV]], align 4
3150 // CHECK2-NEXT:    [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
3151 // CHECK2-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
3152 // CHECK2-NEXT:    [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32*
3153 // CHECK2-NEXT:    store i32 [[TMP2]], i32* [[CONV1]], align 4
3154 // CHECK2-NEXT:    [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8
3155 // CHECK2-NEXT:    [[TMP4:%.*]] = load i16, i16* [[AA]], align 2
3156 // CHECK2-NEXT:    [[CONV2:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
3157 // CHECK2-NEXT:    store i16 [[TMP4]], i16* [[CONV2]], align 2
3158 // CHECK2-NEXT:    [[TMP5:%.*]] = load i64, i64* [[AA_CASTED]], align 8
3159 // CHECK2-NEXT:    [[TMP6:%.*]] = load i8, i8* [[AAA]], align 1
3160 // CHECK2-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
3161 // CHECK2-NEXT:    store i8 [[TMP6]], i8* [[CONV3]], align 1
3162 // CHECK2-NEXT:    [[TMP7:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
3163 // CHECK2-NEXT:    [[TMP8:%.*]] = load i32, i32* [[N_ADDR]], align 4
3164 // CHECK2-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP8]], 50
3165 // CHECK2-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
3166 // CHECK2:       omp_if.then:
3167 // CHECK2-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
3168 // CHECK2-NEXT:    [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64*
3169 // CHECK2-NEXT:    store i64 [[TMP1]], i64* [[TMP10]], align 8
3170 // CHECK2-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
3171 // CHECK2-NEXT:    [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64*
3172 // CHECK2-NEXT:    store i64 [[TMP1]], i64* [[TMP12]], align 8
3173 // CHECK2-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
3174 // CHECK2-NEXT:    store i8* null, i8** [[TMP13]], align 8
3175 // CHECK2-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
3176 // CHECK2-NEXT:    [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64*
3177 // CHECK2-NEXT:    store i64 [[TMP3]], i64* [[TMP15]], align 8
3178 // CHECK2-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
3179 // CHECK2-NEXT:    [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64*
3180 // CHECK2-NEXT:    store i64 [[TMP3]], i64* [[TMP17]], align 8
3181 // CHECK2-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
3182 // CHECK2-NEXT:    store i8* null, i8** [[TMP18]], align 8
3183 // CHECK2-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
3184 // CHECK2-NEXT:    [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64*
3185 // CHECK2-NEXT:    store i64 [[TMP5]], i64* [[TMP20]], align 8
3186 // CHECK2-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
3187 // CHECK2-NEXT:    [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i64*
3188 // CHECK2-NEXT:    store i64 [[TMP5]], i64* [[TMP22]], align 8
3189 // CHECK2-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
3190 // CHECK2-NEXT:    store i8* null, i8** [[TMP23]], align 8
3191 // CHECK2-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
3192 // CHECK2-NEXT:    [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i64*
3193 // CHECK2-NEXT:    store i64 [[TMP7]], i64* [[TMP25]], align 8
3194 // CHECK2-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
3195 // CHECK2-NEXT:    [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64*
3196 // CHECK2-NEXT:    store i64 [[TMP7]], i64* [[TMP27]], align 8
3197 // CHECK2-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
3198 // CHECK2-NEXT:    store i8* null, i8** [[TMP28]], align 8
3199 // CHECK2-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
3200 // CHECK2-NEXT:    [[TMP30:%.*]] = bitcast i8** [[TMP29]] to [10 x i32]**
3201 // CHECK2-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP30]], align 8
3202 // CHECK2-NEXT:    [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
3203 // CHECK2-NEXT:    [[TMP32:%.*]] = bitcast i8** [[TMP31]] to [10 x i32]**
3204 // CHECK2-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP32]], align 8
3205 // CHECK2-NEXT:    [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4
3206 // CHECK2-NEXT:    store i8* null, i8** [[TMP33]], align 8
3207 // CHECK2-NEXT:    [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
3208 // CHECK2-NEXT:    [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
3209 // CHECK2-NEXT:    [[TMP36:%.*]] = load i32, i32* [[A]], align 4
3210 // CHECK2-NEXT:    store i32 [[TMP36]], i32* [[DOTCAPTURE_EXPR_]], align 4
3211 // CHECK2-NEXT:    [[TMP37:%.*]] = load i32, i32* [[N_ADDR]], align 4
3212 // CHECK2-NEXT:    store i32 [[TMP37]], i32* [[DOTCAPTURE_EXPR_4]], align 4
3213 // CHECK2-NEXT:    [[TMP38:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4
3214 // CHECK2-NEXT:    [[TMP39:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
3215 // CHECK2-NEXT:    [[SUB:%.*]] = sub i32 [[TMP38]], [[TMP39]]
3216 // CHECK2-NEXT:    [[SUB6:%.*]] = sub i32 [[SUB]], 1
3217 // CHECK2-NEXT:    [[ADD:%.*]] = add i32 [[SUB6]], 1
3218 // CHECK2-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], 1
3219 // CHECK2-NEXT:    [[SUB7:%.*]] = sub i32 [[DIV]], 1
3220 // CHECK2-NEXT:    store i32 [[SUB7]], i32* [[DOTCAPTURE_EXPR_5]], align 4
3221 // CHECK2-NEXT:    [[TMP40:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4
3222 // CHECK2-NEXT:    [[ADD8:%.*]] = add i32 [[TMP40]], 1
3223 // CHECK2-NEXT:    [[TMP41:%.*]] = zext i32 [[ADD8]] to i64
3224 // CHECK2-NEXT:    call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 [[TMP41]])
3225 // CHECK2-NEXT:    [[TMP42:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197.region_id, i32 5, i8** [[TMP34]], i8** [[TMP35]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes.16, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.17, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1)
3226 // CHECK2-NEXT:    [[TMP43:%.*]] = icmp ne i32 [[TMP42]], 0
3227 // CHECK2-NEXT:    br i1 [[TMP43]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
3228 // CHECK2:       omp_offload.failed:
3229 // CHECK2-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], i64 [[TMP7]], [10 x i32]* [[B]]) #[[ATTR4]]
3230 // CHECK2-NEXT:    br label [[OMP_OFFLOAD_CONT]]
3231 // CHECK2:       omp_offload.cont:
3232 // CHECK2-NEXT:    br label [[OMP_IF_END:%.*]]
3233 // CHECK2:       omp_if.else:
3234 // CHECK2-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], i64 [[TMP7]], [10 x i32]* [[B]]) #[[ATTR4]]
3235 // CHECK2-NEXT:    br label [[OMP_IF_END]]
3236 // CHECK2:       omp_if.end:
3237 // CHECK2-NEXT:    [[TMP44:%.*]] = load i32, i32* [[A]], align 4
3238 // CHECK2-NEXT:    ret i32 [[TMP44]]
3239 //
3240 //
3241 // CHECK2-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
3242 // CHECK2-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat {
3243 // CHECK2-NEXT:  entry:
3244 // CHECK2-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
3245 // CHECK2-NEXT:    [[A:%.*]] = alloca i32, align 4
3246 // CHECK2-NEXT:    [[AA:%.*]] = alloca i16, align 2
3247 // CHECK2-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
3248 // CHECK2-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
3249 // CHECK2-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
3250 // CHECK2-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8
3251 // CHECK2-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8
3252 // CHECK2-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8
3253 // CHECK2-NEXT:    [[TMP:%.*]] = alloca i32, align 4
3254 // CHECK2-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
3255 // CHECK2-NEXT:    store i32 0, i32* [[A]], align 4
3256 // CHECK2-NEXT:    store i16 0, i16* [[AA]], align 2
3257 // CHECK2-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
3258 // CHECK2-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32*
3259 // CHECK2-NEXT:    store i32 [[TMP0]], i32* [[CONV]], align 4
3260 // CHECK2-NEXT:    [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
3261 // CHECK2-NEXT:    [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
3262 // CHECK2-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
3263 // CHECK2-NEXT:    store i16 [[TMP2]], i16* [[CONV1]], align 2
3264 // CHECK2-NEXT:    [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
3265 // CHECK2-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
3266 // CHECK2-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40
3267 // CHECK2-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
3268 // CHECK2:       omp_if.then:
3269 // CHECK2-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
3270 // CHECK2-NEXT:    [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64*
3271 // CHECK2-NEXT:    store i64 [[TMP1]], i64* [[TMP6]], align 8
3272 // CHECK2-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
3273 // CHECK2-NEXT:    [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64*
3274 // CHECK2-NEXT:    store i64 [[TMP1]], i64* [[TMP8]], align 8
3275 // CHECK2-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
3276 // CHECK2-NEXT:    store i8* null, i8** [[TMP9]], align 8
3277 // CHECK2-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
3278 // CHECK2-NEXT:    [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i64*
3279 // CHECK2-NEXT:    store i64 [[TMP3]], i64* [[TMP11]], align 8
3280 // CHECK2-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
3281 // CHECK2-NEXT:    [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64*
3282 // CHECK2-NEXT:    store i64 [[TMP3]], i64* [[TMP13]], align 8
3283 // CHECK2-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
3284 // CHECK2-NEXT:    store i8* null, i8** [[TMP14]], align 8
3285 // CHECK2-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
3286 // CHECK2-NEXT:    [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]**
3287 // CHECK2-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 8
3288 // CHECK2-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
3289 // CHECK2-NEXT:    [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]**
3290 // CHECK2-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 8
3291 // CHECK2-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
3292 // CHECK2-NEXT:    store i8* null, i8** [[TMP19]], align 8
3293 // CHECK2-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
3294 // CHECK2-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
3295 // CHECK2-NEXT:    call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10)
3296 // CHECK2-NEXT:    [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.19, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.20, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1)
3297 // CHECK2-NEXT:    [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0
3298 // CHECK2-NEXT:    br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
3299 // CHECK2:       omp_offload.failed:
3300 // CHECK2-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]]
3301 // CHECK2-NEXT:    br label [[OMP_OFFLOAD_CONT]]
3302 // CHECK2:       omp_offload.cont:
3303 // CHECK2-NEXT:    br label [[OMP_IF_END:%.*]]
3304 // CHECK2:       omp_if.else:
3305 // CHECK2-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]]
3306 // CHECK2-NEXT:    br label [[OMP_IF_END]]
3307 // CHECK2:       omp_if.end:
3308 // CHECK2-NEXT:    [[TMP24:%.*]] = load i32, i32* [[A]], align 4
3309 // CHECK2-NEXT:    ret i32 [[TMP24]]
3310 //
3311 //
3312 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215
3313 // CHECK2-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {
3314 // CHECK2-NEXT:  entry:
3315 // CHECK2-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
3316 // CHECK2-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
3317 // CHECK2-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
3318 // CHECK2-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
3319 // CHECK2-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 8
3320 // CHECK2-NEXT:    [[B_CASTED:%.*]] = alloca i64, align 8
3321 // CHECK2-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
3322 // CHECK2-NEXT:    store i64 [[B]], i64* [[B_ADDR]], align 8
3323 // CHECK2-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
3324 // CHECK2-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
3325 // CHECK2-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 8
3326 // CHECK2-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
3327 // CHECK2-NEXT:    [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
3328 // CHECK2-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
3329 // CHECK2-NEXT:    [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
3330 // CHECK2-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
3331 // CHECK2-NEXT:    [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
3332 // CHECK2-NEXT:    [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32*
3333 // CHECK2-NEXT:    store i32 [[TMP4]], i32* [[CONV3]], align 4
3334 // CHECK2-NEXT:    [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
3335 // CHECK2-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..12 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]])
3336 // CHECK2-NEXT:    ret void
3337 //
3338 //
3339 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..12
3340 // CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] {
3341 // CHECK2-NEXT:  entry:
3342 // CHECK2-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
3343 // CHECK2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
3344 // CHECK2-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
3345 // CHECK2-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
3346 // CHECK2-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
3347 // CHECK2-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
3348 // CHECK2-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 8
3349 // CHECK2-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
3350 // CHECK2-NEXT:    [[TMP:%.*]] = alloca i32, align 4
3351 // CHECK2-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
3352 // CHECK2-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
3353 // CHECK2-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
3354 // CHECK2-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
3355 // CHECK2-NEXT:    [[I:%.*]] = alloca i32, align 4
3356 // CHECK2-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
3357 // CHECK2-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
3358 // CHECK2-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
3359 // CHECK2-NEXT:    store i64 [[B]], i64* [[B_ADDR]], align 8
3360 // CHECK2-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
3361 // CHECK2-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
3362 // CHECK2-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 8
3363 // CHECK2-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
3364 // CHECK2-NEXT:    [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
3365 // CHECK2-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
3366 // CHECK2-NEXT:    [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
3367 // CHECK2-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
3368 // CHECK2-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
3369 // CHECK2-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
3370 // CHECK2-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
3371 // CHECK2-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
3372 // CHECK2-NEXT:    [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
3373 // CHECK2-NEXT:    [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
3374 // CHECK2-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
3375 // CHECK2-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
3376 // CHECK2-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 9
3377 // CHECK2-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
3378 // CHECK2:       cond.true:
3379 // CHECK2-NEXT:    br label [[COND_END:%.*]]
3380 // CHECK2:       cond.false:
3381 // CHECK2-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
3382 // CHECK2-NEXT:    br label [[COND_END]]
3383 // CHECK2:       cond.end:
3384 // CHECK2-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
3385 // CHECK2-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
3386 // CHECK2-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
3387 // CHECK2-NEXT:    store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
3388 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
3389 // CHECK2:       omp.inner.for.cond:
3390 // CHECK2-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !38
3391 // CHECK2-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !38
3392 // CHECK2-NEXT:    [[CMP3:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
3393 // CHECK2-NEXT:    br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
3394 // CHECK2:       omp.inner.for.body:
3395 // CHECK2-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !38
3396 // CHECK2-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
3397 // CHECK2-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
3398 // CHECK2-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !38
3399 // CHECK2-NEXT:    [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !38
3400 // CHECK2-NEXT:    [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double
3401 // CHECK2-NEXT:    [[ADD5:%.*]] = fadd double [[CONV4]], 1.500000e+00
3402 // CHECK2-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
3403 // CHECK2-NEXT:    store double [[ADD5]], double* [[A]], align 8, !llvm.access.group !38
3404 // CHECK2-NEXT:    [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
3405 // CHECK2-NEXT:    [[TMP13:%.*]] = load double, double* [[A6]], align 8, !llvm.access.group !38
3406 // CHECK2-NEXT:    [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00
3407 // CHECK2-NEXT:    store double [[INC]], double* [[A6]], align 8, !llvm.access.group !38
3408 // CHECK2-NEXT:    [[CONV7:%.*]] = fptosi double [[INC]] to i16
3409 // CHECK2-NEXT:    [[TMP14:%.*]] = mul nsw i64 1, [[TMP2]]
3410 // CHECK2-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP14]]
3411 // CHECK2-NEXT:    [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
3412 // CHECK2-NEXT:    store i16 [[CONV7]], i16* [[ARRAYIDX8]], align 2, !llvm.access.group !38
3413 // CHECK2-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
3414 // CHECK2:       omp.body.continue:
3415 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
3416 // CHECK2:       omp.inner.for.inc:
3417 // CHECK2-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !38
3418 // CHECK2-NEXT:    [[ADD9:%.*]] = add nsw i32 [[TMP15]], 1
3419 // CHECK2-NEXT:    store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !38
3420 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP39:![0-9]+]]
3421 // CHECK2:       omp.inner.for.end:
3422 // CHECK2-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
3423 // CHECK2:       omp.loop.exit:
3424 // CHECK2-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
3425 // CHECK2-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
3426 // CHECK2-NEXT:    [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0
3427 // CHECK2-NEXT:    br i1 [[TMP17]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
3428 // CHECK2:       .omp.final.then:
3429 // CHECK2-NEXT:    store i32 10, i32* [[I]], align 4
3430 // CHECK2-NEXT:    br label [[DOTOMP_FINAL_DONE]]
3431 // CHECK2:       .omp.final.done:
3432 // CHECK2-NEXT:    ret void
3433 //
3434 //
3435 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197
3436 // CHECK2-SAME: (i64 noundef [[A:%.*]], i64 noundef [[N:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
3437 // CHECK2-NEXT:  entry:
3438 // CHECK2-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
3439 // CHECK2-NEXT:    [[N_ADDR:%.*]] = alloca i64, align 8
3440 // CHECK2-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
3441 // CHECK2-NEXT:    [[AAA_ADDR:%.*]] = alloca i64, align 8
3442 // CHECK2-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
3443 // CHECK2-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
3444 // CHECK2-NEXT:    [[N_CASTED:%.*]] = alloca i64, align 8
3445 // CHECK2-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
3446 // CHECK2-NEXT:    [[AAA_CASTED:%.*]] = alloca i64, align 8
3447 // CHECK2-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
3448 // CHECK2-NEXT:    store i64 [[N]], i64* [[N_ADDR]], align 8
3449 // CHECK2-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
3450 // CHECK2-NEXT:    store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
3451 // CHECK2-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
3452 // CHECK2-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
3453 // CHECK2-NEXT:    [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32*
3454 // CHECK2-NEXT:    [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
3455 // CHECK2-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
3456 // CHECK2-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
3457 // CHECK2-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
3458 // CHECK2-NEXT:    [[CONV4:%.*]] = bitcast i64* [[A_CASTED]] to i32*
3459 // CHECK2-NEXT:    store i32 [[TMP1]], i32* [[CONV4]], align 4
3460 // CHECK2-NEXT:    [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
3461 // CHECK2-NEXT:    [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 4
3462 // CHECK2-NEXT:    [[CONV5:%.*]] = bitcast i64* [[N_CASTED]] to i32*
3463 // CHECK2-NEXT:    store i32 [[TMP3]], i32* [[CONV5]], align 4
3464 // CHECK2-NEXT:    [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8
3465 // CHECK2-NEXT:    [[TMP5:%.*]] = load i16, i16* [[CONV2]], align 2
3466 // CHECK2-NEXT:    [[CONV6:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
3467 // CHECK2-NEXT:    store i16 [[TMP5]], i16* [[CONV6]], align 2
3468 // CHECK2-NEXT:    [[TMP6:%.*]] = load i64, i64* [[AA_CASTED]], align 8
3469 // CHECK2-NEXT:    [[TMP7:%.*]] = load i8, i8* [[CONV3]], align 1
3470 // CHECK2-NEXT:    [[CONV7:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
3471 // CHECK2-NEXT:    store i8 [[TMP7]], i8* [[CONV7]], align 1
3472 // CHECK2-NEXT:    [[TMP8:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
3473 // CHECK2-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, [10 x i32]*)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]], [10 x i32]* [[TMP0]])
3474 // CHECK2-NEXT:    ret void
3475 //
3476 //
3477 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..15
3478 // CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[N:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] {
3479 // CHECK2-NEXT:  entry:
3480 // CHECK2-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
3481 // CHECK2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
3482 // CHECK2-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
3483 // CHECK2-NEXT:    [[N_ADDR:%.*]] = alloca i64, align 8
3484 // CHECK2-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
3485 // CHECK2-NEXT:    [[AAA_ADDR:%.*]] = alloca i64, align 8
3486 // CHECK2-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
3487 // CHECK2-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
3488 // CHECK2-NEXT:    [[TMP:%.*]] = alloca i32, align 4
3489 // CHECK2-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
3490 // CHECK2-NEXT:    [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4
3491 // CHECK2-NEXT:    [[DOTCAPTURE_EXPR_5:%.*]] = alloca i32, align 4
3492 // CHECK2-NEXT:    [[I:%.*]] = alloca i32, align 4
3493 // CHECK2-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
3494 // CHECK2-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
3495 // CHECK2-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
3496 // CHECK2-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
3497 // CHECK2-NEXT:    [[I8:%.*]] = alloca i32, align 4
3498 // CHECK2-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
3499 // CHECK2-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
3500 // CHECK2-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
3501 // CHECK2-NEXT:    store i64 [[N]], i64* [[N_ADDR]], align 8
3502 // CHECK2-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
3503 // CHECK2-NEXT:    store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
3504 // CHECK2-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
3505 // CHECK2-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
3506 // CHECK2-NEXT:    [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32*
3507 // CHECK2-NEXT:    [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
3508 // CHECK2-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
3509 // CHECK2-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
3510 // CHECK2-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
3511 // CHECK2-NEXT:    store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
3512 // CHECK2-NEXT:    [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4
3513 // CHECK2-NEXT:    store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_4]], align 4
3514 // CHECK2-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4
3515 // CHECK2-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
3516 // CHECK2-NEXT:    [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]]
3517 // CHECK2-NEXT:    [[SUB6:%.*]] = sub i32 [[SUB]], 1
3518 // CHECK2-NEXT:    [[ADD:%.*]] = add i32 [[SUB6]], 1
3519 // CHECK2-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], 1
3520 // CHECK2-NEXT:    [[SUB7:%.*]] = sub i32 [[DIV]], 1
3521 // CHECK2-NEXT:    store i32 [[SUB7]], i32* [[DOTCAPTURE_EXPR_5]], align 4
3522 // CHECK2-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
3523 // CHECK2-NEXT:    store i32 [[TMP5]], i32* [[I]], align 4
3524 // CHECK2-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
3525 // CHECK2-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4
3526 // CHECK2-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]]
3527 // CHECK2-NEXT:    br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
3528 // CHECK2:       omp.precond.then:
3529 // CHECK2-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
3530 // CHECK2-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4
3531 // CHECK2-NEXT:    store i32 [[TMP8]], i32* [[DOTOMP_UB]], align 4
3532 // CHECK2-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
3533 // CHECK2-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
3534 // CHECK2-NEXT:    [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
3535 // CHECK2-NEXT:    [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
3536 // CHECK2-NEXT:    call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
3537 // CHECK2-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
3538 // CHECK2-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4
3539 // CHECK2-NEXT:    [[CMP9:%.*]] = icmp ugt i32 [[TMP11]], [[TMP12]]
3540 // CHECK2-NEXT:    br i1 [[CMP9]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
3541 // CHECK2:       cond.true:
3542 // CHECK2-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4
3543 // CHECK2-NEXT:    br label [[COND_END:%.*]]
3544 // CHECK2:       cond.false:
3545 // CHECK2-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
3546 // CHECK2-NEXT:    br label [[COND_END]]
3547 // CHECK2:       cond.end:
3548 // CHECK2-NEXT:    [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ]
3549 // CHECK2-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
3550 // CHECK2-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
3551 // CHECK2-NEXT:    store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4
3552 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
3553 // CHECK2:       omp.inner.for.cond:
3554 // CHECK2-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !41
3555 // CHECK2-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !41
3556 // CHECK2-NEXT:    [[ADD10:%.*]] = add i32 [[TMP17]], 1
3557 // CHECK2-NEXT:    [[CMP11:%.*]] = icmp ult i32 [[TMP16]], [[ADD10]]
3558 // CHECK2-NEXT:    br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
3559 // CHECK2:       omp.inner.for.body:
3560 // CHECK2-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group !41
3561 // CHECK2-NEXT:    [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !41
3562 // CHECK2-NEXT:    [[MUL:%.*]] = mul i32 [[TMP19]], 1
3563 // CHECK2-NEXT:    [[ADD12:%.*]] = add i32 [[TMP18]], [[MUL]]
3564 // CHECK2-NEXT:    store i32 [[ADD12]], i32* [[I8]], align 4, !llvm.access.group !41
3565 // CHECK2-NEXT:    [[TMP20:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !41
3566 // CHECK2-NEXT:    [[ADD13:%.*]] = add nsw i32 [[TMP20]], 1
3567 // CHECK2-NEXT:    store i32 [[ADD13]], i32* [[CONV]], align 4, !llvm.access.group !41
3568 // CHECK2-NEXT:    [[TMP21:%.*]] = load i16, i16* [[CONV2]], align 2, !llvm.access.group !41
3569 // CHECK2-NEXT:    [[CONV14:%.*]] = sext i16 [[TMP21]] to i32
3570 // CHECK2-NEXT:    [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1
3571 // CHECK2-NEXT:    [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16
3572 // CHECK2-NEXT:    store i16 [[CONV16]], i16* [[CONV2]], align 2, !llvm.access.group !41
3573 // CHECK2-NEXT:    [[TMP22:%.*]] = load i8, i8* [[CONV3]], align 1, !llvm.access.group !41
3574 // CHECK2-NEXT:    [[CONV17:%.*]] = sext i8 [[TMP22]] to i32
3575 // CHECK2-NEXT:    [[ADD18:%.*]] = add nsw i32 [[CONV17]], 1
3576 // CHECK2-NEXT:    [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8
3577 // CHECK2-NEXT:    store i8 [[CONV19]], i8* [[CONV3]], align 1, !llvm.access.group !41
3578 // CHECK2-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
3579 // CHECK2-NEXT:    [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !41
3580 // CHECK2-NEXT:    [[ADD20:%.*]] = add nsw i32 [[TMP23]], 1
3581 // CHECK2-NEXT:    store i32 [[ADD20]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !41
3582 // CHECK2-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
3583 // CHECK2:       omp.body.continue:
3584 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
3585 // CHECK2:       omp.inner.for.inc:
3586 // CHECK2-NEXT:    [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !41
3587 // CHECK2-NEXT:    [[ADD21:%.*]] = add i32 [[TMP24]], 1
3588 // CHECK2-NEXT:    store i32 [[ADD21]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !41
3589 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP42:![0-9]+]]
3590 // CHECK2:       omp.inner.for.end:
3591 // CHECK2-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
3592 // CHECK2:       omp.loop.exit:
3593 // CHECK2-NEXT:    [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
3594 // CHECK2-NEXT:    [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4
3595 // CHECK2-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]])
3596 // CHECK2-NEXT:    [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
3597 // CHECK2-NEXT:    [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0
3598 // CHECK2-NEXT:    br i1 [[TMP28]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
3599 // CHECK2:       .omp.final.then:
3600 // CHECK2-NEXT:    [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
3601 // CHECK2-NEXT:    [[TMP30:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4
3602 // CHECK2-NEXT:    [[TMP31:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
3603 // CHECK2-NEXT:    [[SUB22:%.*]] = sub i32 [[TMP30]], [[TMP31]]
3604 // CHECK2-NEXT:    [[SUB23:%.*]] = sub i32 [[SUB22]], 1
3605 // CHECK2-NEXT:    [[ADD24:%.*]] = add i32 [[SUB23]], 1
3606 // CHECK2-NEXT:    [[DIV25:%.*]] = udiv i32 [[ADD24]], 1
3607 // CHECK2-NEXT:    [[MUL26:%.*]] = mul i32 [[DIV25]], 1
3608 // CHECK2-NEXT:    [[ADD27:%.*]] = add i32 [[TMP29]], [[MUL26]]
3609 // CHECK2-NEXT:    store i32 [[ADD27]], i32* [[I8]], align 4
3610 // CHECK2-NEXT:    br label [[DOTOMP_FINAL_DONE]]
3611 // CHECK2:       .omp.final.done:
3612 // CHECK2-NEXT:    br label [[OMP_PRECOND_END]]
3613 // CHECK2:       omp.precond.end:
3614 // CHECK2-NEXT:    ret void
3615 //
3616 //
3617 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180
3618 // CHECK2-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
3619 // CHECK2-NEXT:  entry:
3620 // CHECK2-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
3621 // CHECK2-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
3622 // CHECK2-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
3623 // CHECK2-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
3624 // CHECK2-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
3625 // CHECK2-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
3626 // CHECK2-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
3627 // CHECK2-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
3628 // CHECK2-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
3629 // CHECK2-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
3630 // CHECK2-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
3631 // CHECK2-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
3632 // CHECK2-NEXT:    [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
3633 // CHECK2-NEXT:    store i32 [[TMP1]], i32* [[CONV2]], align 4
3634 // CHECK2-NEXT:    [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
3635 // CHECK2-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
3636 // CHECK2-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
3637 // CHECK2-NEXT:    store i16 [[TMP3]], i16* [[CONV3]], align 2
3638 // CHECK2-NEXT:    [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
3639 // CHECK2-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..18 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]])
3640 // CHECK2-NEXT:    ret void
3641 //
3642 //
3643 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..18
3644 // CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] {
3645 // CHECK2-NEXT:  entry:
3646 // CHECK2-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
3647 // CHECK2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
3648 // CHECK2-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
3649 // CHECK2-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
3650 // CHECK2-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
3651 // CHECK2-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
3652 // CHECK2-NEXT:    [[TMP:%.*]] = alloca i32, align 4
3653 // CHECK2-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
3654 // CHECK2-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
3655 // CHECK2-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
3656 // CHECK2-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
3657 // CHECK2-NEXT:    [[I:%.*]] = alloca i32, align 4
3658 // CHECK2-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
3659 // CHECK2-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
3660 // CHECK2-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
3661 // CHECK2-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
3662 // CHECK2-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
3663 // CHECK2-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
3664 // CHECK2-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
3665 // CHECK2-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
3666 // CHECK2-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
3667 // CHECK2-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
3668 // CHECK2-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
3669 // CHECK2-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
3670 // CHECK2-NEXT:    [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
3671 // CHECK2-NEXT:    [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
3672 // CHECK2-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
3673 // CHECK2-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
3674 // CHECK2-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9
3675 // CHECK2-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
3676 // CHECK2:       cond.true:
3677 // CHECK2-NEXT:    br label [[COND_END:%.*]]
3678 // CHECK2:       cond.false:
3679 // CHECK2-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
3680 // CHECK2-NEXT:    br label [[COND_END]]
3681 // CHECK2:       cond.end:
3682 // CHECK2-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
3683 // CHECK2-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
3684 // CHECK2-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
3685 // CHECK2-NEXT:    store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
3686 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
3687 // CHECK2:       omp.inner.for.cond:
3688 // CHECK2-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !44
3689 // CHECK2-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !44
3690 // CHECK2-NEXT:    [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
3691 // CHECK2-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
3692 // CHECK2:       omp.inner.for.body:
3693 // CHECK2-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !44
3694 // CHECK2-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
3695 // CHECK2-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
3696 // CHECK2-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !44
3697 // CHECK2-NEXT:    [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !44
3698 // CHECK2-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1
3699 // CHECK2-NEXT:    store i32 [[ADD3]], i32* [[CONV]], align 4, !llvm.access.group !44
3700 // CHECK2-NEXT:    [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 2, !llvm.access.group !44
3701 // CHECK2-NEXT:    [[CONV4:%.*]] = sext i16 [[TMP10]] to i32
3702 // CHECK2-NEXT:    [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
3703 // CHECK2-NEXT:    [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
3704 // CHECK2-NEXT:    store i16 [[CONV6]], i16* [[CONV1]], align 2, !llvm.access.group !44
3705 // CHECK2-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
3706 // CHECK2-NEXT:    [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !44
3707 // CHECK2-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1
3708 // CHECK2-NEXT:    store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !44
3709 // CHECK2-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
3710 // CHECK2:       omp.body.continue:
3711 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
3712 // CHECK2:       omp.inner.for.inc:
3713 // CHECK2-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !44
3714 // CHECK2-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP12]], 1
3715 // CHECK2-NEXT:    store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !44
3716 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP45:![0-9]+]]
3717 // CHECK2:       omp.inner.for.end:
3718 // CHECK2-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
3719 // CHECK2:       omp.loop.exit:
3720 // CHECK2-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
3721 // CHECK2-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
3722 // CHECK2-NEXT:    [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
3723 // CHECK2-NEXT:    br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
3724 // CHECK2:       .omp.final.then:
3725 // CHECK2-NEXT:    store i32 10, i32* [[I]], align 4
3726 // CHECK2-NEXT:    br label [[DOTOMP_FINAL_DONE]]
3727 // CHECK2:       .omp.final.done:
3728 // CHECK2-NEXT:    ret void
3729 //
3730 //
3731 // CHECK2-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
3732 // CHECK2-SAME: () #[[ATTR5]] {
3733 // CHECK2-NEXT:  entry:
3734 // CHECK2-NEXT:    call void @__tgt_register_requires(i64 1)
3735 // CHECK2-NEXT:    ret void
3736 //
3737 //
3738 // CHECK3-LABEL: define {{[^@]+}}@_Z3fooi
3739 // CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0:[0-9]+]] {
3740 // CHECK3-NEXT:  entry:
3741 // CHECK3-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
3742 // CHECK3-NEXT:    [[A:%.*]] = alloca i32, align 4
3743 // CHECK3-NEXT:    [[AA:%.*]] = alloca i16, align 2
3744 // CHECK3-NEXT:    [[B:%.*]] = alloca [10 x float], align 4
3745 // CHECK3-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 4
3746 // CHECK3-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 4
3747 // CHECK3-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 8
3748 // CHECK3-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i32, align 4
3749 // CHECK3-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4
3750 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
3751 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
3752 // CHECK3-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
3753 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
3754 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR__CASTED3:%.*]] = alloca i32, align 4
3755 // CHECK3-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4
3756 // CHECK3-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4
3757 // CHECK3-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4
3758 // CHECK3-NEXT:    [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4
3759 // CHECK3-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
3760 // CHECK3-NEXT:    [[AA_CASTED4:%.*]] = alloca i32, align 4
3761 // CHECK3-NEXT:    [[DOTOFFLOAD_BASEPTRS6:%.*]] = alloca [1 x i8*], align 4
3762 // CHECK3-NEXT:    [[DOTOFFLOAD_PTRS7:%.*]] = alloca [1 x i8*], align 4
3763 // CHECK3-NEXT:    [[DOTOFFLOAD_MAPPERS8:%.*]] = alloca [1 x i8*], align 4
3764 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 4
3765 // CHECK3-NEXT:    [[A_CASTED9:%.*]] = alloca i32, align 4
3766 // CHECK3-NEXT:    [[AA_CASTED10:%.*]] = alloca i32, align 4
3767 // CHECK3-NEXT:    [[DOTOFFLOAD_BASEPTRS12:%.*]] = alloca [2 x i8*], align 4
3768 // CHECK3-NEXT:    [[DOTOFFLOAD_PTRS13:%.*]] = alloca [2 x i8*], align 4
3769 // CHECK3-NEXT:    [[DOTOFFLOAD_MAPPERS14:%.*]] = alloca [2 x i8*], align 4
3770 // CHECK3-NEXT:    [[_TMP15:%.*]] = alloca i32, align 4
3771 // CHECK3-NEXT:    [[A_CASTED18:%.*]] = alloca i32, align 4
3772 // CHECK3-NEXT:    [[DOTOFFLOAD_BASEPTRS21:%.*]] = alloca [9 x i8*], align 4
3773 // CHECK3-NEXT:    [[DOTOFFLOAD_PTRS22:%.*]] = alloca [9 x i8*], align 4
3774 // CHECK3-NEXT:    [[DOTOFFLOAD_MAPPERS23:%.*]] = alloca [9 x i8*], align 4
3775 // CHECK3-NEXT:    [[DOTOFFLOAD_SIZES:%.*]] = alloca [9 x i64], align 4
3776 // CHECK3-NEXT:    [[_TMP24:%.*]] = alloca i32, align 4
3777 // CHECK3-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]])
3778 // CHECK3-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
3779 // CHECK3-NEXT:    store i32 0, i32* [[A]], align 4
3780 // CHECK3-NEXT:    store i16 0, i16* [[AA]], align 2
3781 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
3782 // CHECK3-NEXT:    [[TMP2:%.*]] = call i8* @llvm.stacksave()
3783 // CHECK3-NEXT:    store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4
3784 // CHECK3-NEXT:    [[VLA:%.*]] = alloca float, i32 [[TMP1]], align 4
3785 // CHECK3-NEXT:    store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
3786 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
3787 // CHECK3-NEXT:    [[TMP4:%.*]] = mul nuw i32 5, [[TMP3]]
3788 // CHECK3-NEXT:    [[VLA1:%.*]] = alloca double, i32 [[TMP4]], align 8
3789 // CHECK3-NEXT:    store i32 [[TMP3]], i32* [[__VLA_EXPR1]], align 4
3790 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
3791 // CHECK3-NEXT:    store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_]], align 4
3792 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, i32* [[A]], align 4
3793 // CHECK3-NEXT:    store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_2]], align 4
3794 // CHECK3-NEXT:    [[TMP7:%.*]] = load i16, i16* [[AA]], align 2
3795 // CHECK3-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
3796 // CHECK3-NEXT:    store i16 [[TMP7]], i16* [[CONV]], align 2
3797 // CHECK3-NEXT:    [[TMP8:%.*]] = load i32, i32* [[AA_CASTED]], align 4
3798 // CHECK3-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
3799 // CHECK3-NEXT:    store i32 [[TMP9]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
3800 // CHECK3-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
3801 // CHECK3-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
3802 // CHECK3-NEXT:    store i32 [[TMP11]], i32* [[DOTCAPTURE_EXPR__CASTED3]], align 4
3803 // CHECK3-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED3]], align 4
3804 // CHECK3-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
3805 // CHECK3-NEXT:    [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i32*
3806 // CHECK3-NEXT:    store i32 [[TMP8]], i32* [[TMP14]], align 4
3807 // CHECK3-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
3808 // CHECK3-NEXT:    [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i32*
3809 // CHECK3-NEXT:    store i32 [[TMP8]], i32* [[TMP16]], align 4
3810 // CHECK3-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
3811 // CHECK3-NEXT:    store i8* null, i8** [[TMP17]], align 4
3812 // CHECK3-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
3813 // CHECK3-NEXT:    [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32*
3814 // CHECK3-NEXT:    store i32 [[TMP10]], i32* [[TMP19]], align 4
3815 // CHECK3-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
3816 // CHECK3-NEXT:    [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32*
3817 // CHECK3-NEXT:    store i32 [[TMP10]], i32* [[TMP21]], align 4
3818 // CHECK3-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
3819 // CHECK3-NEXT:    store i8* null, i8** [[TMP22]], align 4
3820 // CHECK3-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
3821 // CHECK3-NEXT:    [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i32*
3822 // CHECK3-NEXT:    store i32 [[TMP12]], i32* [[TMP24]], align 4
3823 // CHECK3-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
3824 // CHECK3-NEXT:    [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i32*
3825 // CHECK3-NEXT:    store i32 [[TMP12]], i32* [[TMP26]], align 4
3826 // CHECK3-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
3827 // CHECK3-NEXT:    store i8* null, i8** [[TMP27]], align 4
3828 // CHECK3-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
3829 // CHECK3-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
3830 // CHECK3-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 0
3831 // CHECK3-NEXT:    [[TMP31:%.*]] = load i16, i16* [[AA]], align 2
3832 // CHECK3-NEXT:    store i16 [[TMP31]], i16* [[TMP30]], align 4
3833 // CHECK3-NEXT:    [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 1
3834 // CHECK3-NEXT:    [[TMP33:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
3835 // CHECK3-NEXT:    store i32 [[TMP33]], i32* [[TMP32]], align 4
3836 // CHECK3-NEXT:    [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 2
3837 // CHECK3-NEXT:    [[TMP35:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
3838 // CHECK3-NEXT:    store i32 [[TMP35]], i32* [[TMP34]], align 4
3839 // CHECK3-NEXT:    [[TMP36:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 1, i32 72, i32 12, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1)
3840 // CHECK3-NEXT:    [[TMP37:%.*]] = bitcast i8* [[TMP36]] to %struct.kmp_task_t_with_privates*
3841 // CHECK3-NEXT:    [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP37]], i32 0, i32 0
3842 // CHECK3-NEXT:    [[TMP39:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP38]], i32 0, i32 0
3843 // CHECK3-NEXT:    [[TMP40:%.*]] = load i8*, i8** [[TMP39]], align 4
3844 // CHECK3-NEXT:    [[TMP41:%.*]] = bitcast %struct.anon* [[AGG_CAPTURED]] to i8*
3845 // CHECK3-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP40]], i8* align 4 [[TMP41]], i32 12, i1 false)
3846 // CHECK3-NEXT:    [[TMP42:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP37]], i32 0, i32 1
3847 // CHECK3-NEXT:    [[TMP43:%.*]] = bitcast i8* [[TMP40]] to %struct.anon*
3848 // CHECK3-NEXT:    [[TMP44:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 0
3849 // CHECK3-NEXT:    [[TMP45:%.*]] = bitcast [3 x i64]* [[TMP44]] to i8*
3850 // CHECK3-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP45]], i8* align 4 bitcast ([3 x i64]* @.offload_sizes to i8*), i32 24, i1 false)
3851 // CHECK3-NEXT:    [[TMP46:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 1
3852 // CHECK3-NEXT:    [[TMP47:%.*]] = bitcast [3 x i8*]* [[TMP46]] to i8*
3853 // CHECK3-NEXT:    [[TMP48:%.*]] = bitcast i8** [[TMP28]] to i8*
3854 // CHECK3-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP47]], i8* align 4 [[TMP48]], i32 12, i1 false)
3855 // CHECK3-NEXT:    [[TMP49:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 2
3856 // CHECK3-NEXT:    [[TMP50:%.*]] = bitcast [3 x i8*]* [[TMP49]] to i8*
3857 // CHECK3-NEXT:    [[TMP51:%.*]] = bitcast i8** [[TMP29]] to i8*
3858 // CHECK3-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP50]], i8* align 4 [[TMP51]], i32 12, i1 false)
3859 // CHECK3-NEXT:    [[TMP52:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 3
3860 // CHECK3-NEXT:    [[TMP53:%.*]] = load i16, i16* [[AA]], align 2
3861 // CHECK3-NEXT:    store i16 [[TMP53]], i16* [[TMP52]], align 4
3862 // CHECK3-NEXT:    [[TMP54:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i8* [[TMP36]])
3863 // CHECK3-NEXT:    [[TMP55:%.*]] = load i32, i32* [[A]], align 4
3864 // CHECK3-NEXT:    store i32 [[TMP55]], i32* [[A_CASTED]], align 4
3865 // CHECK3-NEXT:    [[TMP56:%.*]] = load i32, i32* [[A_CASTED]], align 4
3866 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104(i32 [[TMP56]]) #[[ATTR4:[0-9]+]]
3867 // CHECK3-NEXT:    [[TMP57:%.*]] = load i16, i16* [[AA]], align 2
3868 // CHECK3-NEXT:    [[CONV5:%.*]] = bitcast i32* [[AA_CASTED4]] to i16*
3869 // CHECK3-NEXT:    store i16 [[TMP57]], i16* [[CONV5]], align 2
3870 // CHECK3-NEXT:    [[TMP58:%.*]] = load i32, i32* [[AA_CASTED4]], align 4
3871 // CHECK3-NEXT:    [[TMP59:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0
3872 // CHECK3-NEXT:    [[TMP60:%.*]] = bitcast i8** [[TMP59]] to i32*
3873 // CHECK3-NEXT:    store i32 [[TMP58]], i32* [[TMP60]], align 4
3874 // CHECK3-NEXT:    [[TMP61:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0
3875 // CHECK3-NEXT:    [[TMP62:%.*]] = bitcast i8** [[TMP61]] to i32*
3876 // CHECK3-NEXT:    store i32 [[TMP58]], i32* [[TMP62]], align 4
3877 // CHECK3-NEXT:    [[TMP63:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS8]], i32 0, i32 0
3878 // CHECK3-NEXT:    store i8* null, i8** [[TMP63]], align 4
3879 // CHECK3-NEXT:    [[TMP64:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0
3880 // CHECK3-NEXT:    [[TMP65:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0
3881 // CHECK3-NEXT:    call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10)
3882 // CHECK3-NEXT:    [[TMP66:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.region_id, i32 1, i8** [[TMP64]], i8** [[TMP65]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.4, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.5, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1)
3883 // CHECK3-NEXT:    [[TMP67:%.*]] = icmp ne i32 [[TMP66]], 0
3884 // CHECK3-NEXT:    br i1 [[TMP67]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
3885 // CHECK3:       omp_offload.failed:
3886 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111(i32 [[TMP58]]) #[[ATTR4]]
3887 // CHECK3-NEXT:    br label [[OMP_OFFLOAD_CONT]]
3888 // CHECK3:       omp_offload.cont:
3889 // CHECK3-NEXT:    [[TMP68:%.*]] = load i32, i32* [[A]], align 4
3890 // CHECK3-NEXT:    store i32 [[TMP68]], i32* [[A_CASTED9]], align 4
3891 // CHECK3-NEXT:    [[TMP69:%.*]] = load i32, i32* [[A_CASTED9]], align 4
3892 // CHECK3-NEXT:    [[TMP70:%.*]] = load i16, i16* [[AA]], align 2
3893 // CHECK3-NEXT:    [[CONV11:%.*]] = bitcast i32* [[AA_CASTED10]] to i16*
3894 // CHECK3-NEXT:    store i16 [[TMP70]], i16* [[CONV11]], align 2
3895 // CHECK3-NEXT:    [[TMP71:%.*]] = load i32, i32* [[AA_CASTED10]], align 4
3896 // CHECK3-NEXT:    [[TMP72:%.*]] = load i32, i32* [[N_ADDR]], align 4
3897 // CHECK3-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP72]], 10
3898 // CHECK3-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
3899 // CHECK3:       omp_if.then:
3900 // CHECK3-NEXT:    [[TMP73:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS12]], i32 0, i32 0
3901 // CHECK3-NEXT:    [[TMP74:%.*]] = bitcast i8** [[TMP73]] to i32*
3902 // CHECK3-NEXT:    store i32 [[TMP69]], i32* [[TMP74]], align 4
3903 // CHECK3-NEXT:    [[TMP75:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS13]], i32 0, i32 0
3904 // CHECK3-NEXT:    [[TMP76:%.*]] = bitcast i8** [[TMP75]] to i32*
3905 // CHECK3-NEXT:    store i32 [[TMP69]], i32* [[TMP76]], align 4
3906 // CHECK3-NEXT:    [[TMP77:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS14]], i32 0, i32 0
3907 // CHECK3-NEXT:    store i8* null, i8** [[TMP77]], align 4
3908 // CHECK3-NEXT:    [[TMP78:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS12]], i32 0, i32 1
3909 // CHECK3-NEXT:    [[TMP79:%.*]] = bitcast i8** [[TMP78]] to i32*
3910 // CHECK3-NEXT:    store i32 [[TMP71]], i32* [[TMP79]], align 4
3911 // CHECK3-NEXT:    [[TMP80:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS13]], i32 0, i32 1
3912 // CHECK3-NEXT:    [[TMP81:%.*]] = bitcast i8** [[TMP80]] to i32*
3913 // CHECK3-NEXT:    store i32 [[TMP71]], i32* [[TMP81]], align 4
3914 // CHECK3-NEXT:    [[TMP82:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS14]], i32 0, i32 1
3915 // CHECK3-NEXT:    store i8* null, i8** [[TMP82]], align 4
3916 // CHECK3-NEXT:    [[TMP83:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS12]], i32 0, i32 0
3917 // CHECK3-NEXT:    [[TMP84:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS13]], i32 0, i32 0
3918 // CHECK3-NEXT:    call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10)
3919 // CHECK3-NEXT:    [[TMP85:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.region_id, i32 2, i8** [[TMP83]], i8** [[TMP84]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.7, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.8, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1)
3920 // CHECK3-NEXT:    [[TMP86:%.*]] = icmp ne i32 [[TMP85]], 0
3921 // CHECK3-NEXT:    br i1 [[TMP86]], label [[OMP_OFFLOAD_FAILED16:%.*]], label [[OMP_OFFLOAD_CONT17:%.*]]
3922 // CHECK3:       omp_offload.failed16:
3923 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i32 [[TMP69]], i32 [[TMP71]]) #[[ATTR4]]
3924 // CHECK3-NEXT:    br label [[OMP_OFFLOAD_CONT17]]
3925 // CHECK3:       omp_offload.cont17:
3926 // CHECK3-NEXT:    br label [[OMP_IF_END:%.*]]
3927 // CHECK3:       omp_if.else:
3928 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i32 [[TMP69]], i32 [[TMP71]]) #[[ATTR4]]
3929 // CHECK3-NEXT:    br label [[OMP_IF_END]]
3930 // CHECK3:       omp_if.end:
3931 // CHECK3-NEXT:    [[TMP87:%.*]] = load i32, i32* [[A]], align 4
3932 // CHECK3-NEXT:    store i32 [[TMP87]], i32* [[A_CASTED18]], align 4
3933 // CHECK3-NEXT:    [[TMP88:%.*]] = load i32, i32* [[A_CASTED18]], align 4
3934 // CHECK3-NEXT:    [[TMP89:%.*]] = load i32, i32* [[N_ADDR]], align 4
3935 // CHECK3-NEXT:    [[CMP19:%.*]] = icmp sgt i32 [[TMP89]], 20
3936 // CHECK3-NEXT:    br i1 [[CMP19]], label [[OMP_IF_THEN20:%.*]], label [[OMP_IF_ELSE27:%.*]]
3937 // CHECK3:       omp_if.then20:
3938 // CHECK3-NEXT:    [[TMP90:%.*]] = mul nuw i32 [[TMP1]], 4
3939 // CHECK3-NEXT:    [[TMP91:%.*]] = sext i32 [[TMP90]] to i64
3940 // CHECK3-NEXT:    [[TMP92:%.*]] = mul nuw i32 5, [[TMP3]]
3941 // CHECK3-NEXT:    [[TMP93:%.*]] = mul nuw i32 [[TMP92]], 8
3942 // CHECK3-NEXT:    [[TMP94:%.*]] = sext i32 [[TMP93]] to i64
3943 // CHECK3-NEXT:    [[TMP95:%.*]] = bitcast [9 x i64]* [[DOTOFFLOAD_SIZES]] to i8*
3944 // CHECK3-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP95]], i8* align 4 bitcast ([9 x i64]* @.offload_sizes.10 to i8*), i32 72, i1 false)
3945 // CHECK3-NEXT:    [[TMP96:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 0
3946 // CHECK3-NEXT:    [[TMP97:%.*]] = bitcast i8** [[TMP96]] to i32*
3947 // CHECK3-NEXT:    store i32 [[TMP88]], i32* [[TMP97]], align 4
3948 // CHECK3-NEXT:    [[TMP98:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 0
3949 // CHECK3-NEXT:    [[TMP99:%.*]] = bitcast i8** [[TMP98]] to i32*
3950 // CHECK3-NEXT:    store i32 [[TMP88]], i32* [[TMP99]], align 4
3951 // CHECK3-NEXT:    [[TMP100:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i32 0, i32 0
3952 // CHECK3-NEXT:    store i8* null, i8** [[TMP100]], align 4
3953 // CHECK3-NEXT:    [[TMP101:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 1
3954 // CHECK3-NEXT:    [[TMP102:%.*]] = bitcast i8** [[TMP101]] to [10 x float]**
3955 // CHECK3-NEXT:    store [10 x float]* [[B]], [10 x float]** [[TMP102]], align 4
3956 // CHECK3-NEXT:    [[TMP103:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 1
3957 // CHECK3-NEXT:    [[TMP104:%.*]] = bitcast i8** [[TMP103]] to [10 x float]**
3958 // CHECK3-NEXT:    store [10 x float]* [[B]], [10 x float]** [[TMP104]], align 4
3959 // CHECK3-NEXT:    [[TMP105:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i32 0, i32 1
3960 // CHECK3-NEXT:    store i8* null, i8** [[TMP105]], align 4
3961 // CHECK3-NEXT:    [[TMP106:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 2
3962 // CHECK3-NEXT:    [[TMP107:%.*]] = bitcast i8** [[TMP106]] to i32*
3963 // CHECK3-NEXT:    store i32 [[TMP1]], i32* [[TMP107]], align 4
3964 // CHECK3-NEXT:    [[TMP108:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 2
3965 // CHECK3-NEXT:    [[TMP109:%.*]] = bitcast i8** [[TMP108]] to i32*
3966 // CHECK3-NEXT:    store i32 [[TMP1]], i32* [[TMP109]], align 4
3967 // CHECK3-NEXT:    [[TMP110:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i32 0, i32 2
3968 // CHECK3-NEXT:    store i8* null, i8** [[TMP110]], align 4
3969 // CHECK3-NEXT:    [[TMP111:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 3
3970 // CHECK3-NEXT:    [[TMP112:%.*]] = bitcast i8** [[TMP111]] to float**
3971 // CHECK3-NEXT:    store float* [[VLA]], float** [[TMP112]], align 4
3972 // CHECK3-NEXT:    [[TMP113:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 3
3973 // CHECK3-NEXT:    [[TMP114:%.*]] = bitcast i8** [[TMP113]] to float**
3974 // CHECK3-NEXT:    store float* [[VLA]], float** [[TMP114]], align 4
3975 // CHECK3-NEXT:    [[TMP115:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3
3976 // CHECK3-NEXT:    store i64 [[TMP91]], i64* [[TMP115]], align 4
3977 // CHECK3-NEXT:    [[TMP116:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i32 0, i32 3
3978 // CHECK3-NEXT:    store i8* null, i8** [[TMP116]], align 4
3979 // CHECK3-NEXT:    [[TMP117:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 4
3980 // CHECK3-NEXT:    [[TMP118:%.*]] = bitcast i8** [[TMP117]] to [5 x [10 x double]]**
3981 // CHECK3-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP118]], align 4
3982 // CHECK3-NEXT:    [[TMP119:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 4
3983 // CHECK3-NEXT:    [[TMP120:%.*]] = bitcast i8** [[TMP119]] to [5 x [10 x double]]**
3984 // CHECK3-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP120]], align 4
3985 // CHECK3-NEXT:    [[TMP121:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i32 0, i32 4
3986 // CHECK3-NEXT:    store i8* null, i8** [[TMP121]], align 4
3987 // CHECK3-NEXT:    [[TMP122:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 5
3988 // CHECK3-NEXT:    [[TMP123:%.*]] = bitcast i8** [[TMP122]] to i32*
3989 // CHECK3-NEXT:    store i32 5, i32* [[TMP123]], align 4
3990 // CHECK3-NEXT:    [[TMP124:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 5
3991 // CHECK3-NEXT:    [[TMP125:%.*]] = bitcast i8** [[TMP124]] to i32*
3992 // CHECK3-NEXT:    store i32 5, i32* [[TMP125]], align 4
3993 // CHECK3-NEXT:    [[TMP126:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i32 0, i32 5
3994 // CHECK3-NEXT:    store i8* null, i8** [[TMP126]], align 4
3995 // CHECK3-NEXT:    [[TMP127:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 6
3996 // CHECK3-NEXT:    [[TMP128:%.*]] = bitcast i8** [[TMP127]] to i32*
3997 // CHECK3-NEXT:    store i32 [[TMP3]], i32* [[TMP128]], align 4
3998 // CHECK3-NEXT:    [[TMP129:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 6
3999 // CHECK3-NEXT:    [[TMP130:%.*]] = bitcast i8** [[TMP129]] to i32*
4000 // CHECK3-NEXT:    store i32 [[TMP3]], i32* [[TMP130]], align 4
4001 // CHECK3-NEXT:    [[TMP131:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i32 0, i32 6
4002 // CHECK3-NEXT:    store i8* null, i8** [[TMP131]], align 4
4003 // CHECK3-NEXT:    [[TMP132:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 7
4004 // CHECK3-NEXT:    [[TMP133:%.*]] = bitcast i8** [[TMP132]] to double**
4005 // CHECK3-NEXT:    store double* [[VLA1]], double** [[TMP133]], align 4
4006 // CHECK3-NEXT:    [[TMP134:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 7
4007 // CHECK3-NEXT:    [[TMP135:%.*]] = bitcast i8** [[TMP134]] to double**
4008 // CHECK3-NEXT:    store double* [[VLA1]], double** [[TMP135]], align 4
4009 // CHECK3-NEXT:    [[TMP136:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7
4010 // CHECK3-NEXT:    store i64 [[TMP94]], i64* [[TMP136]], align 4
4011 // CHECK3-NEXT:    [[TMP137:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i32 0, i32 7
4012 // CHECK3-NEXT:    store i8* null, i8** [[TMP137]], align 4
4013 // CHECK3-NEXT:    [[TMP138:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 8
4014 // CHECK3-NEXT:    [[TMP139:%.*]] = bitcast i8** [[TMP138]] to %struct.TT**
4015 // CHECK3-NEXT:    store %struct.TT* [[D]], %struct.TT** [[TMP139]], align 4
4016 // CHECK3-NEXT:    [[TMP140:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 8
4017 // CHECK3-NEXT:    [[TMP141:%.*]] = bitcast i8** [[TMP140]] to %struct.TT**
4018 // CHECK3-NEXT:    store %struct.TT* [[D]], %struct.TT** [[TMP141]], align 4
4019 // CHECK3-NEXT:    [[TMP142:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i32 0, i32 8
4020 // CHECK3-NEXT:    store i8* null, i8** [[TMP142]], align 4
4021 // CHECK3-NEXT:    [[TMP143:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 0
4022 // CHECK3-NEXT:    [[TMP144:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 0
4023 // CHECK3-NEXT:    [[TMP145:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
4024 // CHECK3-NEXT:    call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10)
4025 // CHECK3-NEXT:    [[TMP146:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142.region_id, i32 9, i8** [[TMP143]], i8** [[TMP144]], i64* [[TMP145]], i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_maptypes.11, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1)
4026 // CHECK3-NEXT:    [[TMP147:%.*]] = icmp ne i32 [[TMP146]], 0
4027 // CHECK3-NEXT:    br i1 [[TMP147]], label [[OMP_OFFLOAD_FAILED25:%.*]], label [[OMP_OFFLOAD_CONT26:%.*]]
4028 // CHECK3:       omp_offload.failed25:
4029 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i32 [[TMP88]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR4]]
4030 // CHECK3-NEXT:    br label [[OMP_OFFLOAD_CONT26]]
4031 // CHECK3:       omp_offload.cont26:
4032 // CHECK3-NEXT:    br label [[OMP_IF_END28:%.*]]
4033 // CHECK3:       omp_if.else27:
4034 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i32 [[TMP88]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR4]]
4035 // CHECK3-NEXT:    br label [[OMP_IF_END28]]
4036 // CHECK3:       omp_if.end28:
4037 // CHECK3-NEXT:    [[TMP148:%.*]] = load i32, i32* [[A]], align 4
4038 // CHECK3-NEXT:    [[TMP149:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
4039 // CHECK3-NEXT:    call void @llvm.stackrestore(i8* [[TMP149]])
4040 // CHECK3-NEXT:    ret i32 [[TMP148]]
4041 //
4042 //
4043 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97
4044 // CHECK3-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]], i32 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] {
4045 // CHECK3-NEXT:  entry:
4046 // CHECK3-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
4047 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
4048 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4
4049 // CHECK3-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
4050 // CHECK3-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]])
4051 // CHECK3-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
4052 // CHECK3-NEXT:    store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
4053 // CHECK3-NEXT:    store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4
4054 // CHECK3-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
4055 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
4056 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4
4057 // CHECK3-NEXT:    call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
4058 // CHECK3-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
4059 // CHECK3-NEXT:    [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
4060 // CHECK3-NEXT:    store i16 [[TMP3]], i16* [[CONV3]], align 2
4061 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
4062 // CHECK3-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]])
4063 // CHECK3-NEXT:    ret void
4064 //
4065 //
4066 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined.
4067 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR3:[0-9]+]] {
4068 // CHECK3-NEXT:  entry:
4069 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
4070 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
4071 // CHECK3-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
4072 // CHECK3-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
4073 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 4
4074 // CHECK3-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
4075 // CHECK3-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
4076 // CHECK3-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
4077 // CHECK3-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
4078 // CHECK3-NEXT:    [[I:%.*]] = alloca i32, align 4
4079 // CHECK3-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
4080 // CHECK3-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
4081 // CHECK3-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
4082 // CHECK3-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
4083 // CHECK3-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
4084 // CHECK3-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
4085 // CHECK3-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
4086 // CHECK3-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
4087 // CHECK3-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
4088 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
4089 // CHECK3-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
4090 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
4091 // CHECK3-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
4092 // CHECK3-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
4093 // CHECK3:       cond.true:
4094 // CHECK3-NEXT:    br label [[COND_END:%.*]]
4095 // CHECK3:       cond.false:
4096 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
4097 // CHECK3-NEXT:    br label [[COND_END]]
4098 // CHECK3:       cond.end:
4099 // CHECK3-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
4100 // CHECK3-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
4101 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
4102 // CHECK3-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
4103 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
4104 // CHECK3:       omp.inner.for.cond:
4105 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
4106 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !11
4107 // CHECK3-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
4108 // CHECK3-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
4109 // CHECK3:       omp.inner.for.body:
4110 // CHECK3-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
4111 // CHECK3-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
4112 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
4113 // CHECK3-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11
4114 // CHECK3-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
4115 // CHECK3:       omp.body.continue:
4116 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
4117 // CHECK3:       omp.inner.for.inc:
4118 // CHECK3-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
4119 // CHECK3-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
4120 // CHECK3-NEXT:    store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
4121 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]
4122 // CHECK3:       omp.inner.for.end:
4123 // CHECK3-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
4124 // CHECK3:       omp.loop.exit:
4125 // CHECK3-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
4126 // CHECK3-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
4127 // CHECK3-NEXT:    [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0
4128 // CHECK3-NEXT:    br i1 [[TMP10]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
4129 // CHECK3:       .omp.final.then:
4130 // CHECK3-NEXT:    store i32 10, i32* [[I]], align 4
4131 // CHECK3-NEXT:    br label [[DOTOMP_FINAL_DONE]]
4132 // CHECK3:       .omp.final.done:
4133 // CHECK3-NEXT:    ret void
4134 //
4135 //
4136 // CHECK3-LABEL: define {{[^@]+}}@.omp_task_privates_map.
4137 // CHECK3-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], i16** noalias noundef [[TMP1:%.*]], [3 x i8*]** noalias noundef [[TMP2:%.*]], [3 x i8*]** noalias noundef [[TMP3:%.*]], [3 x i64]** noalias noundef [[TMP4:%.*]]) #[[ATTR5:[0-9]+]] {
4138 // CHECK3-NEXT:  entry:
4139 // CHECK3-NEXT:    [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 4
4140 // CHECK3-NEXT:    [[DOTADDR1:%.*]] = alloca i16**, align 4
4141 // CHECK3-NEXT:    [[DOTADDR2:%.*]] = alloca [3 x i8*]**, align 4
4142 // CHECK3-NEXT:    [[DOTADDR3:%.*]] = alloca [3 x i8*]**, align 4
4143 // CHECK3-NEXT:    [[DOTADDR4:%.*]] = alloca [3 x i64]**, align 4
4144 // CHECK3-NEXT:    store %struct..kmp_privates.t* [[TMP0]], %struct..kmp_privates.t** [[DOTADDR]], align 4
4145 // CHECK3-NEXT:    store i16** [[TMP1]], i16*** [[DOTADDR1]], align 4
4146 // CHECK3-NEXT:    store [3 x i8*]** [[TMP2]], [3 x i8*]*** [[DOTADDR2]], align 4
4147 // CHECK3-NEXT:    store [3 x i8*]** [[TMP3]], [3 x i8*]*** [[DOTADDR3]], align 4
4148 // CHECK3-NEXT:    store [3 x i64]** [[TMP4]], [3 x i64]*** [[DOTADDR4]], align 4
4149 // CHECK3-NEXT:    [[TMP5:%.*]] = load %struct..kmp_privates.t*, %struct..kmp_privates.t** [[DOTADDR]], align 4
4150 // CHECK3-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 0
4151 // CHECK3-NEXT:    [[TMP7:%.*]] = load [3 x i64]**, [3 x i64]*** [[DOTADDR4]], align 4
4152 // CHECK3-NEXT:    store [3 x i64]* [[TMP6]], [3 x i64]** [[TMP7]], align 4
4153 // CHECK3-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 1
4154 // CHECK3-NEXT:    [[TMP9:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR2]], align 4
4155 // CHECK3-NEXT:    store [3 x i8*]* [[TMP8]], [3 x i8*]** [[TMP9]], align 4
4156 // CHECK3-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 2
4157 // CHECK3-NEXT:    [[TMP11:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR3]], align 4
4158 // CHECK3-NEXT:    store [3 x i8*]* [[TMP10]], [3 x i8*]** [[TMP11]], align 4
4159 // CHECK3-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 3
4160 // CHECK3-NEXT:    [[TMP13:%.*]] = load i16**, i16*** [[DOTADDR1]], align 4
4161 // CHECK3-NEXT:    store i16* [[TMP12]], i16** [[TMP13]], align 4
4162 // CHECK3-NEXT:    ret void
4163 //
4164 //
4165 // CHECK3-LABEL: define {{[^@]+}}@.omp_task_entry.
4166 // CHECK3-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] {
4167 // CHECK3-NEXT:  entry:
4168 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
4169 // CHECK3-NEXT:    [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 4
4170 // CHECK3-NEXT:    [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 4
4171 // CHECK3-NEXT:    [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 4
4172 // CHECK3-NEXT:    [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 4
4173 // CHECK3-NEXT:    [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 4
4174 // CHECK3-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca i16*, align 4
4175 // CHECK3-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca [3 x i8*]*, align 4
4176 // CHECK3-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca [3 x i8*]*, align 4
4177 // CHECK3-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca [3 x i64]*, align 4
4178 // CHECK3-NEXT:    [[AA_CASTED_I:%.*]] = alloca i32, align 4
4179 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR__CASTED_I:%.*]] = alloca i32, align 4
4180 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR__CASTED4_I:%.*]] = alloca i32, align 4
4181 // CHECK3-NEXT:    [[DOTADDR:%.*]] = alloca i32, align 4
4182 // CHECK3-NEXT:    [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 4
4183 // CHECK3-NEXT:    store i32 [[TMP0]], i32* [[DOTADDR]], align 4
4184 // CHECK3-NEXT:    store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4
4185 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4
4186 // CHECK3-NEXT:    [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4
4187 // CHECK3-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
4188 // CHECK3-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
4189 // CHECK3-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0
4190 // CHECK3-NEXT:    [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 4
4191 // CHECK3-NEXT:    [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon*
4192 // CHECK3-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1
4193 // CHECK3-NEXT:    [[TMP10:%.*]] = bitcast %struct..kmp_privates.t* [[TMP9]] to i8*
4194 // CHECK3-NEXT:    [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8*
4195 // CHECK3-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]])
4196 // CHECK3-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META21:![0-9]+]])
4197 // CHECK3-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META23:![0-9]+]])
4198 // CHECK3-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META25:![0-9]+]])
4199 // CHECK3-NEXT:    store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !27
4200 // CHECK3-NEXT:    store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 4, !noalias !27
4201 // CHECK3-NEXT:    store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !27
4202 // CHECK3-NEXT:    store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* @.omp_task_privates_map. to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !27
4203 // CHECK3-NEXT:    store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 4, !noalias !27
4204 // CHECK3-NEXT:    store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !27
4205 // CHECK3-NEXT:    [[TMP12:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !27
4206 // CHECK3-NEXT:    [[TMP13:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !27
4207 // CHECK3-NEXT:    [[TMP14:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !27
4208 // CHECK3-NEXT:    [[TMP15:%.*]] = bitcast void (i8*, ...)* [[TMP13]] to void (i8*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)*
4209 // CHECK3-NEXT:    call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR4]]
4210 // CHECK3-NEXT:    [[TMP16:%.*]] = load i16*, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 4, !noalias !27
4211 // CHECK3-NEXT:    [[TMP17:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 4, !noalias !27
4212 // CHECK3-NEXT:    [[TMP18:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 4, !noalias !27
4213 // CHECK3-NEXT:    [[TMP19:%.*]] = load [3 x i64]*, [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 4, !noalias !27
4214 // CHECK3-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP17]], i32 0, i32 0
4215 // CHECK3-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP18]], i32 0, i32 0
4216 // CHECK3-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[TMP19]], i32 0, i32 0
4217 // CHECK3-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP12]], i32 0, i32 1
4218 // CHECK3-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[TMP12]], i32 0, i32 2
4219 // CHECK3-NEXT:    [[TMP25:%.*]] = load i32, i32* [[TMP23]], align 4
4220 // CHECK3-NEXT:    call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) #[[ATTR4]]
4221 // CHECK3-NEXT:    [[TMP26:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 [[TMP25]], i32 1, i32 0, i8* null, i32 0, i8* null) #[[ATTR4]]
4222 // CHECK3-NEXT:    [[TMP27:%.*]] = icmp ne i32 [[TMP26]], 0
4223 // CHECK3-NEXT:    br i1 [[TMP27]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]]
4224 // CHECK3:       omp_offload.failed.i:
4225 // CHECK3-NEXT:    [[TMP28:%.*]] = load i16, i16* [[TMP16]], align 2
4226 // CHECK3-NEXT:    [[CONV_I:%.*]] = bitcast i32* [[AA_CASTED_I]] to i16*
4227 // CHECK3-NEXT:    store i16 [[TMP28]], i16* [[CONV_I]], align 2, !noalias !27
4228 // CHECK3-NEXT:    [[TMP29:%.*]] = load i32, i32* [[AA_CASTED_I]], align 4, !noalias !27
4229 // CHECK3-NEXT:    [[TMP30:%.*]] = load i32, i32* [[TMP23]], align 4
4230 // CHECK3-NEXT:    store i32 [[TMP30]], i32* [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias !27
4231 // CHECK3-NEXT:    [[TMP31:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias !27
4232 // CHECK3-NEXT:    [[TMP32:%.*]] = load i32, i32* [[TMP24]], align 4
4233 // CHECK3-NEXT:    store i32 [[TMP32]], i32* [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias !27
4234 // CHECK3-NEXT:    [[TMP33:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias !27
4235 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97(i32 [[TMP29]], i32 [[TMP31]], i32 [[TMP33]]) #[[ATTR4]]
4236 // CHECK3-NEXT:    br label [[DOTOMP_OUTLINED__1_EXIT]]
4237 // CHECK3:       .omp_outlined..1.exit:
4238 // CHECK3-NEXT:    ret i32 0
4239 //
4240 //
4241 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104
4242 // CHECK3-SAME: (i32 noundef [[A:%.*]]) #[[ATTR3]] {
4243 // CHECK3-NEXT:  entry:
4244 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
4245 // CHECK3-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
4246 // CHECK3-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
4247 // CHECK3-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
4248 // CHECK3-NEXT:    store i32 [[TMP0]], i32* [[A_CASTED]], align 4
4249 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
4250 // CHECK3-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]])
4251 // CHECK3-NEXT:    ret void
4252 //
4253 //
4254 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..2
4255 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]]) #[[ATTR3]] {
4256 // CHECK3-NEXT:  entry:
4257 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
4258 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
4259 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
4260 // CHECK3-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
4261 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 4
4262 // CHECK3-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
4263 // CHECK3-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
4264 // CHECK3-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
4265 // CHECK3-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
4266 // CHECK3-NEXT:    [[A1:%.*]] = alloca i32, align 4
4267 // CHECK3-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
4268 // CHECK3-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
4269 // CHECK3-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
4270 // CHECK3-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
4271 // CHECK3-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
4272 // CHECK3-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
4273 // CHECK3-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
4274 // CHECK3-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
4275 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
4276 // CHECK3-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
4277 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
4278 // CHECK3-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
4279 // CHECK3-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
4280 // CHECK3:       cond.true:
4281 // CHECK3-NEXT:    br label [[COND_END:%.*]]
4282 // CHECK3:       cond.false:
4283 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
4284 // CHECK3-NEXT:    br label [[COND_END]]
4285 // CHECK3:       cond.end:
4286 // CHECK3-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
4287 // CHECK3-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
4288 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
4289 // CHECK3-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
4290 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
4291 // CHECK3:       omp.inner.for.cond:
4292 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
4293 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
4294 // CHECK3-NEXT:    [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
4295 // CHECK3-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
4296 // CHECK3:       omp.inner.for.body:
4297 // CHECK3-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
4298 // CHECK3-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
4299 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
4300 // CHECK3-NEXT:    store i32 [[ADD]], i32* [[A1]], align 4
4301 // CHECK3-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A1]], align 4
4302 // CHECK3-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
4303 // CHECK3-NEXT:    store i32 [[ADD3]], i32* [[A1]], align 4
4304 // CHECK3-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
4305 // CHECK3:       omp.body.continue:
4306 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
4307 // CHECK3:       omp.inner.for.inc:
4308 // CHECK3-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
4309 // CHECK3-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP9]], 1
4310 // CHECK3-NEXT:    store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4
4311 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]]
4312 // CHECK3:       omp.inner.for.end:
4313 // CHECK3-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
4314 // CHECK3:       omp.loop.exit:
4315 // CHECK3-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
4316 // CHECK3-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
4317 // CHECK3-NEXT:    [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0
4318 // CHECK3-NEXT:    br i1 [[TMP11]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
4319 // CHECK3:       .omp.final.then:
4320 // CHECK3-NEXT:    store i32 10, i32* [[A_ADDR]], align 4
4321 // CHECK3-NEXT:    br label [[DOTOMP_FINAL_DONE]]
4322 // CHECK3:       .omp.final.done:
4323 // CHECK3-NEXT:    ret void
4324 //
4325 //
4326 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111
4327 // CHECK3-SAME: (i32 noundef [[AA:%.*]]) #[[ATTR2]] {
4328 // CHECK3-NEXT:  entry:
4329 // CHECK3-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
4330 // CHECK3-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
4331 // CHECK3-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
4332 // CHECK3-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
4333 // CHECK3-NEXT:    [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
4334 // CHECK3-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
4335 // CHECK3-NEXT:    store i16 [[TMP0]], i16* [[CONV1]], align 2
4336 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
4337 // CHECK3-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP1]])
4338 // CHECK3-NEXT:    ret void
4339 //
4340 //
4341 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..3
4342 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR3]] {
4343 // CHECK3-NEXT:  entry:
4344 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
4345 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
4346 // CHECK3-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
4347 // CHECK3-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
4348 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 4
4349 // CHECK3-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
4350 // CHECK3-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
4351 // CHECK3-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
4352 // CHECK3-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
4353 // CHECK3-NEXT:    [[I:%.*]] = alloca i32, align 4
4354 // CHECK3-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
4355 // CHECK3-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
4356 // CHECK3-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
4357 // CHECK3-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
4358 // CHECK3-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
4359 // CHECK3-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
4360 // CHECK3-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
4361 // CHECK3-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
4362 // CHECK3-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
4363 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
4364 // CHECK3-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
4365 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
4366 // CHECK3-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
4367 // CHECK3-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
4368 // CHECK3:       cond.true:
4369 // CHECK3-NEXT:    br label [[COND_END:%.*]]
4370 // CHECK3:       cond.false:
4371 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
4372 // CHECK3-NEXT:    br label [[COND_END]]
4373 // CHECK3:       cond.end:
4374 // CHECK3-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
4375 // CHECK3-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
4376 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
4377 // CHECK3-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
4378 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
4379 // CHECK3:       omp.inner.for.cond:
4380 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30
4381 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !30
4382 // CHECK3-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
4383 // CHECK3-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
4384 // CHECK3:       omp.inner.for.body:
4385 // CHECK3-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30
4386 // CHECK3-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
4387 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
4388 // CHECK3-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !30
4389 // CHECK3-NEXT:    [[TMP8:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !30
4390 // CHECK3-NEXT:    [[CONV2:%.*]] = sext i16 [[TMP8]] to i32
4391 // CHECK3-NEXT:    [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
4392 // CHECK3-NEXT:    [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
4393 // CHECK3-NEXT:    store i16 [[CONV4]], i16* [[CONV]], align 2, !llvm.access.group !30
4394 // CHECK3-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
4395 // CHECK3:       omp.body.continue:
4396 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
4397 // CHECK3:       omp.inner.for.inc:
4398 // CHECK3-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30
4399 // CHECK3-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP9]], 1
4400 // CHECK3-NEXT:    store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30
4401 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP31:![0-9]+]]
4402 // CHECK3:       omp.inner.for.end:
4403 // CHECK3-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
4404 // CHECK3:       omp.loop.exit:
4405 // CHECK3-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
4406 // CHECK3-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
4407 // CHECK3-NEXT:    [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0
4408 // CHECK3-NEXT:    br i1 [[TMP11]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
4409 // CHECK3:       .omp.final.then:
4410 // CHECK3-NEXT:    store i32 10, i32* [[I]], align 4
4411 // CHECK3-NEXT:    br label [[DOTOMP_FINAL_DONE]]
4412 // CHECK3:       .omp.final.done:
4413 // CHECK3-NEXT:    ret void
4414 //
4415 //
4416 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118
4417 // CHECK3-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] {
4418 // CHECK3-NEXT:  entry:
4419 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
4420 // CHECK3-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
4421 // CHECK3-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
4422 // CHECK3-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
4423 // CHECK3-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
4424 // CHECK3-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
4425 // CHECK3-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
4426 // CHECK3-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
4427 // CHECK3-NEXT:    store i32 [[TMP0]], i32* [[A_CASTED]], align 4
4428 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
4429 // CHECK3-NEXT:    [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
4430 // CHECK3-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
4431 // CHECK3-NEXT:    store i16 [[TMP2]], i16* [[CONV1]], align 2
4432 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
4433 // CHECK3-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]])
4434 // CHECK3-NEXT:    ret void
4435 //
4436 //
4437 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..6
4438 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR3]] {
4439 // CHECK3-NEXT:  entry:
4440 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
4441 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
4442 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
4443 // CHECK3-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
4444 // CHECK3-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
4445 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 4
4446 // CHECK3-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
4447 // CHECK3-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
4448 // CHECK3-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
4449 // CHECK3-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
4450 // CHECK3-NEXT:    [[I:%.*]] = alloca i32, align 4
4451 // CHECK3-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
4452 // CHECK3-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
4453 // CHECK3-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
4454 // CHECK3-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
4455 // CHECK3-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
4456 // CHECK3-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
4457 // CHECK3-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
4458 // CHECK3-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
4459 // CHECK3-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
4460 // CHECK3-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
4461 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
4462 // CHECK3-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
4463 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
4464 // CHECK3-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
4465 // CHECK3-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
4466 // CHECK3:       cond.true:
4467 // CHECK3-NEXT:    br label [[COND_END:%.*]]
4468 // CHECK3:       cond.false:
4469 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
4470 // CHECK3-NEXT:    br label [[COND_END]]
4471 // CHECK3:       cond.end:
4472 // CHECK3-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
4473 // CHECK3-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
4474 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
4475 // CHECK3-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
4476 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
4477 // CHECK3:       omp.inner.for.cond:
4478 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33
4479 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !33
4480 // CHECK3-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
4481 // CHECK3-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
4482 // CHECK3:       omp.inner.for.body:
4483 // CHECK3-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33
4484 // CHECK3-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
4485 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
4486 // CHECK3-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !33
4487 // CHECK3-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !33
4488 // CHECK3-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
4489 // CHECK3-NEXT:    store i32 [[ADD2]], i32* [[A_ADDR]], align 4, !llvm.access.group !33
4490 // CHECK3-NEXT:    [[TMP9:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !33
4491 // CHECK3-NEXT:    [[CONV3:%.*]] = sext i16 [[TMP9]] to i32
4492 // CHECK3-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
4493 // CHECK3-NEXT:    [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
4494 // CHECK3-NEXT:    store i16 [[CONV5]], i16* [[CONV]], align 2, !llvm.access.group !33
4495 // CHECK3-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
4496 // CHECK3:       omp.body.continue:
4497 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
4498 // CHECK3:       omp.inner.for.inc:
4499 // CHECK3-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33
4500 // CHECK3-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP10]], 1
4501 // CHECK3-NEXT:    store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33
4502 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP34:![0-9]+]]
4503 // CHECK3:       omp.inner.for.end:
4504 // CHECK3-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
4505 // CHECK3:       omp.loop.exit:
4506 // CHECK3-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
4507 // CHECK3-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
4508 // CHECK3-NEXT:    [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
4509 // CHECK3-NEXT:    br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
4510 // CHECK3:       .omp.final.then:
4511 // CHECK3-NEXT:    store i32 10, i32* [[I]], align 4
4512 // CHECK3-NEXT:    br label [[DOTOMP_FINAL_DONE]]
4513 // CHECK3:       .omp.final.done:
4514 // CHECK3-NEXT:    ret void
4515 //
4516 //
4517 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142
4518 // CHECK3-SAME: (i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] {
4519 // CHECK3-NEXT:  entry:
4520 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
4521 // CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
4522 // CHECK3-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
4523 // CHECK3-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 4
4524 // CHECK3-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
4525 // CHECK3-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
4526 // CHECK3-NEXT:    [[VLA_ADDR4:%.*]] = alloca i32, align 4
4527 // CHECK3-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 4
4528 // CHECK3-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
4529 // CHECK3-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
4530 // CHECK3-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
4531 // CHECK3-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
4532 // CHECK3-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
4533 // CHECK3-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 4
4534 // CHECK3-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
4535 // CHECK3-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
4536 // CHECK3-NEXT:    store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
4537 // CHECK3-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 4
4538 // CHECK3-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
4539 // CHECK3-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
4540 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
4541 // CHECK3-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
4542 // CHECK3-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
4543 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
4544 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
4545 // CHECK3-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
4546 // CHECK3-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
4547 // CHECK3-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
4548 // CHECK3-NEXT:    store i32 [[TMP8]], i32* [[A_CASTED]], align 4
4549 // CHECK3-NEXT:    [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4
4550 // CHECK3-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]])
4551 // CHECK3-NEXT:    ret void
4552 //
4553 //
4554 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..9
4555 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR3]] {
4556 // CHECK3-NEXT:  entry:
4557 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
4558 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
4559 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
4560 // CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
4561 // CHECK3-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
4562 // CHECK3-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 4
4563 // CHECK3-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
4564 // CHECK3-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
4565 // CHECK3-NEXT:    [[VLA_ADDR4:%.*]] = alloca i32, align 4
4566 // CHECK3-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 4
4567 // CHECK3-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
4568 // CHECK3-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
4569 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 4
4570 // CHECK3-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
4571 // CHECK3-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
4572 // CHECK3-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
4573 // CHECK3-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
4574 // CHECK3-NEXT:    [[I:%.*]] = alloca i32, align 4
4575 // CHECK3-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
4576 // CHECK3-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
4577 // CHECK3-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
4578 // CHECK3-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
4579 // CHECK3-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
4580 // CHECK3-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 4
4581 // CHECK3-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
4582 // CHECK3-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
4583 // CHECK3-NEXT:    store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
4584 // CHECK3-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 4
4585 // CHECK3-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
4586 // CHECK3-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
4587 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
4588 // CHECK3-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
4589 // CHECK3-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
4590 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
4591 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
4592 // CHECK3-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
4593 // CHECK3-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
4594 // CHECK3-NEXT:    [[ARRAYDECAY:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 0
4595 // CHECK3-NEXT:    call void @llvm.assume(i1 true) [ "align"(float* [[ARRAYDECAY]], i32 16) ]
4596 // CHECK3-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
4597 // CHECK3-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
4598 // CHECK3-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
4599 // CHECK3-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
4600 // CHECK3-NEXT:    [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
4601 // CHECK3-NEXT:    [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4
4602 // CHECK3-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
4603 // CHECK3-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
4604 // CHECK3-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP10]], 9
4605 // CHECK3-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
4606 // CHECK3:       cond.true:
4607 // CHECK3-NEXT:    br label [[COND_END:%.*]]
4608 // CHECK3:       cond.false:
4609 // CHECK3-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
4610 // CHECK3-NEXT:    br label [[COND_END]]
4611 // CHECK3:       cond.end:
4612 // CHECK3-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ]
4613 // CHECK3-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
4614 // CHECK3-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
4615 // CHECK3-NEXT:    store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4
4616 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
4617 // CHECK3:       omp.inner.for.cond:
4618 // CHECK3-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36
4619 // CHECK3-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !36
4620 // CHECK3-NEXT:    [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
4621 // CHECK3-NEXT:    br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
4622 // CHECK3:       omp.inner.for.body:
4623 // CHECK3-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36
4624 // CHECK3-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1
4625 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
4626 // CHECK3-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !36
4627 // CHECK3-NEXT:    [[TMP16:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !36
4628 // CHECK3-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP16]], 1
4629 // CHECK3-NEXT:    store i32 [[ADD6]], i32* [[A_ADDR]], align 4, !llvm.access.group !36
4630 // CHECK3-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2
4631 // CHECK3-NEXT:    [[TMP17:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !36
4632 // CHECK3-NEXT:    [[CONV:%.*]] = fpext float [[TMP17]] to double
4633 // CHECK3-NEXT:    [[ADD7:%.*]] = fadd double [[CONV]], 1.000000e+00
4634 // CHECK3-NEXT:    [[CONV8:%.*]] = fptrunc double [[ADD7]] to float
4635 // CHECK3-NEXT:    store float [[CONV8]], float* [[ARRAYIDX]], align 4, !llvm.access.group !36
4636 // CHECK3-NEXT:    [[ARRAYIDX9:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3
4637 // CHECK3-NEXT:    [[TMP18:%.*]] = load float, float* [[ARRAYIDX9]], align 4, !llvm.access.group !36
4638 // CHECK3-NEXT:    [[CONV10:%.*]] = fpext float [[TMP18]] to double
4639 // CHECK3-NEXT:    [[ADD11:%.*]] = fadd double [[CONV10]], 1.000000e+00
4640 // CHECK3-NEXT:    [[CONV12:%.*]] = fptrunc double [[ADD11]] to float
4641 // CHECK3-NEXT:    store float [[CONV12]], float* [[ARRAYIDX9]], align 4, !llvm.access.group !36
4642 // CHECK3-NEXT:    [[ARRAYIDX13:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1
4643 // CHECK3-NEXT:    [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX13]], i32 0, i32 2
4644 // CHECK3-NEXT:    [[TMP19:%.*]] = load double, double* [[ARRAYIDX14]], align 8, !llvm.access.group !36
4645 // CHECK3-NEXT:    [[ADD15:%.*]] = fadd double [[TMP19]], 1.000000e+00
4646 // CHECK3-NEXT:    store double [[ADD15]], double* [[ARRAYIDX14]], align 8, !llvm.access.group !36
4647 // CHECK3-NEXT:    [[TMP20:%.*]] = mul nsw i32 1, [[TMP5]]
4648 // CHECK3-NEXT:    [[ARRAYIDX16:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP20]]
4649 // CHECK3-NEXT:    [[ARRAYIDX17:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX16]], i32 3
4650 // CHECK3-NEXT:    [[TMP21:%.*]] = load double, double* [[ARRAYIDX17]], align 8, !llvm.access.group !36
4651 // CHECK3-NEXT:    [[ADD18:%.*]] = fadd double [[TMP21]], 1.000000e+00
4652 // CHECK3-NEXT:    store double [[ADD18]], double* [[ARRAYIDX17]], align 8, !llvm.access.group !36
4653 // CHECK3-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0
4654 // CHECK3-NEXT:    [[TMP22:%.*]] = load i64, i64* [[X]], align 4, !llvm.access.group !36
4655 // CHECK3-NEXT:    [[ADD19:%.*]] = add nsw i64 [[TMP22]], 1
4656 // CHECK3-NEXT:    store i64 [[ADD19]], i64* [[X]], align 4, !llvm.access.group !36
4657 // CHECK3-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1
4658 // CHECK3-NEXT:    [[TMP23:%.*]] = load i8, i8* [[Y]], align 4, !llvm.access.group !36
4659 // CHECK3-NEXT:    [[CONV20:%.*]] = sext i8 [[TMP23]] to i32
4660 // CHECK3-NEXT:    [[ADD21:%.*]] = add nsw i32 [[CONV20]], 1
4661 // CHECK3-NEXT:    [[CONV22:%.*]] = trunc i32 [[ADD21]] to i8
4662 // CHECK3-NEXT:    store i8 [[CONV22]], i8* [[Y]], align 4, !llvm.access.group !36
4663 // CHECK3-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
4664 // CHECK3:       omp.body.continue:
4665 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
4666 // CHECK3:       omp.inner.for.inc:
4667 // CHECK3-NEXT:    [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36
4668 // CHECK3-NEXT:    [[ADD23:%.*]] = add nsw i32 [[TMP24]], 1
4669 // CHECK3-NEXT:    store i32 [[ADD23]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36
4670 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP37:![0-9]+]]
4671 // CHECK3:       omp.inner.for.end:
4672 // CHECK3-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
4673 // CHECK3:       omp.loop.exit:
4674 // CHECK3-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]])
4675 // CHECK3-NEXT:    [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
4676 // CHECK3-NEXT:    [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
4677 // CHECK3-NEXT:    br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
4678 // CHECK3:       .omp.final.then:
4679 // CHECK3-NEXT:    store i32 10, i32* [[I]], align 4
4680 // CHECK3-NEXT:    br label [[DOTOMP_FINAL_DONE]]
4681 // CHECK3:       .omp.final.done:
4682 // CHECK3-NEXT:    ret void
4683 //
4684 //
4685 // CHECK3-LABEL: define {{[^@]+}}@_Z3bari
4686 // CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {
4687 // CHECK3-NEXT:  entry:
4688 // CHECK3-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
4689 // CHECK3-NEXT:    [[A:%.*]] = alloca i32, align 4
4690 // CHECK3-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4
4691 // CHECK3-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
4692 // CHECK3-NEXT:    store i32 0, i32* [[A]], align 4
4693 // CHECK3-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
4694 // CHECK3-NEXT:    [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]])
4695 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
4696 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
4697 // CHECK3-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
4698 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
4699 // CHECK3-NEXT:    [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP2]])
4700 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
4701 // CHECK3-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
4702 // CHECK3-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
4703 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
4704 // CHECK3-NEXT:    [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]])
4705 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
4706 // CHECK3-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
4707 // CHECK3-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
4708 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
4709 // CHECK3-NEXT:    [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]])
4710 // CHECK3-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
4711 // CHECK3-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
4712 // CHECK3-NEXT:    store i32 [[ADD6]], i32* [[A]], align 4
4713 // CHECK3-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
4714 // CHECK3-NEXT:    ret i32 [[TMP8]]
4715 //
4716 //
4717 // CHECK3-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
4718 // CHECK3-SAME: (%struct.S1* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 {
4719 // CHECK3-NEXT:  entry:
4720 // CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
4721 // CHECK3-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
4722 // CHECK3-NEXT:    [[B:%.*]] = alloca i32, align 4
4723 // CHECK3-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 4
4724 // CHECK3-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 4
4725 // CHECK3-NEXT:    [[B_CASTED:%.*]] = alloca i32, align 4
4726 // CHECK3-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4
4727 // CHECK3-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4
4728 // CHECK3-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4
4729 // CHECK3-NEXT:    [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 4
4730 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 4
4731 // CHECK3-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
4732 // CHECK3-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
4733 // CHECK3-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
4734 // CHECK3-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
4735 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
4736 // CHECK3-NEXT:    store i32 [[ADD]], i32* [[B]], align 4
4737 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
4738 // CHECK3-NEXT:    [[TMP2:%.*]] = call i8* @llvm.stacksave()
4739 // CHECK3-NEXT:    store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4
4740 // CHECK3-NEXT:    [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]
4741 // CHECK3-NEXT:    [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2
4742 // CHECK3-NEXT:    store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
4743 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, i32* [[B]], align 4
4744 // CHECK3-NEXT:    store i32 [[TMP4]], i32* [[B_CASTED]], align 4
4745 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4
4746 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
4747 // CHECK3-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 60
4748 // CHECK3-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
4749 // CHECK3:       omp_if.then:
4750 // CHECK3-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
4751 // CHECK3-NEXT:    [[TMP7:%.*]] = mul nuw i32 2, [[TMP1]]
4752 // CHECK3-NEXT:    [[TMP8:%.*]] = mul nuw i32 [[TMP7]], 2
4753 // CHECK3-NEXT:    [[TMP9:%.*]] = sext i32 [[TMP8]] to i64
4754 // CHECK3-NEXT:    [[TMP10:%.*]] = bitcast [5 x i64]* [[DOTOFFLOAD_SIZES]] to i8*
4755 // CHECK3-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP10]], i8* align 4 bitcast ([5 x i64]* @.offload_sizes.13 to i8*), i32 40, i1 false)
4756 // CHECK3-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
4757 // CHECK3-NEXT:    [[TMP12:%.*]] = bitcast i8** [[TMP11]] to %struct.S1**
4758 // CHECK3-NEXT:    store %struct.S1* [[THIS1]], %struct.S1** [[TMP12]], align 4
4759 // CHECK3-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
4760 // CHECK3-NEXT:    [[TMP14:%.*]] = bitcast i8** [[TMP13]] to double**
4761 // CHECK3-NEXT:    store double* [[A]], double** [[TMP14]], align 4
4762 // CHECK3-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
4763 // CHECK3-NEXT:    store i8* null, i8** [[TMP15]], align 4
4764 // CHECK3-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
4765 // CHECK3-NEXT:    [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32*
4766 // CHECK3-NEXT:    store i32 [[TMP5]], i32* [[TMP17]], align 4
4767 // CHECK3-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
4768 // CHECK3-NEXT:    [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32*
4769 // CHECK3-NEXT:    store i32 [[TMP5]], i32* [[TMP19]], align 4
4770 // CHECK3-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
4771 // CHECK3-NEXT:    store i8* null, i8** [[TMP20]], align 4
4772 // CHECK3-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
4773 // CHECK3-NEXT:    [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i32*
4774 // CHECK3-NEXT:    store i32 2, i32* [[TMP22]], align 4
4775 // CHECK3-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
4776 // CHECK3-NEXT:    [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i32*
4777 // CHECK3-NEXT:    store i32 2, i32* [[TMP24]], align 4
4778 // CHECK3-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
4779 // CHECK3-NEXT:    store i8* null, i8** [[TMP25]], align 4
4780 // CHECK3-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
4781 // CHECK3-NEXT:    [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i32*
4782 // CHECK3-NEXT:    store i32 [[TMP1]], i32* [[TMP27]], align 4
4783 // CHECK3-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
4784 // CHECK3-NEXT:    [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i32*
4785 // CHECK3-NEXT:    store i32 [[TMP1]], i32* [[TMP29]], align 4
4786 // CHECK3-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
4787 // CHECK3-NEXT:    store i8* null, i8** [[TMP30]], align 4
4788 // CHECK3-NEXT:    [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
4789 // CHECK3-NEXT:    [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i16**
4790 // CHECK3-NEXT:    store i16* [[VLA]], i16** [[TMP32]], align 4
4791 // CHECK3-NEXT:    [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
4792 // CHECK3-NEXT:    [[TMP34:%.*]] = bitcast i8** [[TMP33]] to i16**
4793 // CHECK3-NEXT:    store i16* [[VLA]], i16** [[TMP34]], align 4
4794 // CHECK3-NEXT:    [[TMP35:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4
4795 // CHECK3-NEXT:    store i64 [[TMP9]], i64* [[TMP35]], align 4
4796 // CHECK3-NEXT:    [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4
4797 // CHECK3-NEXT:    store i8* null, i8** [[TMP36]], align 4
4798 // CHECK3-NEXT:    [[TMP37:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
4799 // CHECK3-NEXT:    [[TMP38:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
4800 // CHECK3-NEXT:    [[TMP39:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
4801 // CHECK3-NEXT:    call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10)
4802 // CHECK3-NEXT:    [[TMP40:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215.region_id, i32 5, i8** [[TMP37]], i8** [[TMP38]], i64* [[TMP39]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.14, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1)
4803 // CHECK3-NEXT:    [[TMP41:%.*]] = icmp ne i32 [[TMP40]], 0
4804 // CHECK3-NEXT:    br i1 [[TMP41]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
4805 // CHECK3:       omp_offload.failed:
4806 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR4]]
4807 // CHECK3-NEXT:    br label [[OMP_OFFLOAD_CONT]]
4808 // CHECK3:       omp_offload.cont:
4809 // CHECK3-NEXT:    br label [[OMP_IF_END:%.*]]
4810 // CHECK3:       omp_if.else:
4811 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR4]]
4812 // CHECK3-NEXT:    br label [[OMP_IF_END]]
4813 // CHECK3:       omp_if.end:
4814 // CHECK3-NEXT:    [[TMP42:%.*]] = mul nsw i32 1, [[TMP1]]
4815 // CHECK3-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP42]]
4816 // CHECK3-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
4817 // CHECK3-NEXT:    [[TMP43:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2
4818 // CHECK3-NEXT:    [[CONV:%.*]] = sext i16 [[TMP43]] to i32
4819 // CHECK3-NEXT:    [[TMP44:%.*]] = load i32, i32* [[B]], align 4
4820 // CHECK3-NEXT:    [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP44]]
4821 // CHECK3-NEXT:    [[TMP45:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
4822 // CHECK3-NEXT:    call void @llvm.stackrestore(i8* [[TMP45]])
4823 // CHECK3-NEXT:    ret i32 [[ADD3]]
4824 //
4825 //
4826 // CHECK3-LABEL: define {{[^@]+}}@_ZL7fstatici
4827 // CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {
4828 // CHECK3-NEXT:  entry:
4829 // CHECK3-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
4830 // CHECK3-NEXT:    [[A:%.*]] = alloca i32, align 4
4831 // CHECK3-NEXT:    [[AA:%.*]] = alloca i16, align 2
4832 // CHECK3-NEXT:    [[AAA:%.*]] = alloca i8, align 1
4833 // CHECK3-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
4834 // CHECK3-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
4835 // CHECK3-NEXT:    [[N_CASTED:%.*]] = alloca i32, align 4
4836 // CHECK3-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
4837 // CHECK3-NEXT:    [[AAA_CASTED:%.*]] = alloca i32, align 4
4838 // CHECK3-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4
4839 // CHECK3-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4
4840 // CHECK3-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4
4841 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 4
4842 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
4843 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
4844 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4
4845 // CHECK3-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
4846 // CHECK3-NEXT:    store i32 0, i32* [[A]], align 4
4847 // CHECK3-NEXT:    store i16 0, i16* [[AA]], align 2
4848 // CHECK3-NEXT:    store i8 0, i8* [[AAA]], align 1
4849 // CHECK3-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
4850 // CHECK3-NEXT:    store i32 [[TMP0]], i32* [[A_CASTED]], align 4
4851 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
4852 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
4853 // CHECK3-NEXT:    store i32 [[TMP2]], i32* [[N_CASTED]], align 4
4854 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, i32* [[N_CASTED]], align 4
4855 // CHECK3-NEXT:    [[TMP4:%.*]] = load i16, i16* [[AA]], align 2
4856 // CHECK3-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
4857 // CHECK3-NEXT:    store i16 [[TMP4]], i16* [[CONV]], align 2
4858 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, i32* [[AA_CASTED]], align 4
4859 // CHECK3-NEXT:    [[TMP6:%.*]] = load i8, i8* [[AAA]], align 1
4860 // CHECK3-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
4861 // CHECK3-NEXT:    store i8 [[TMP6]], i8* [[CONV1]], align 1
4862 // CHECK3-NEXT:    [[TMP7:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
4863 // CHECK3-NEXT:    [[TMP8:%.*]] = load i32, i32* [[N_ADDR]], align 4
4864 // CHECK3-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP8]], 50
4865 // CHECK3-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
4866 // CHECK3:       omp_if.then:
4867 // CHECK3-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
4868 // CHECK3-NEXT:    [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32*
4869 // CHECK3-NEXT:    store i32 [[TMP1]], i32* [[TMP10]], align 4
4870 // CHECK3-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
4871 // CHECK3-NEXT:    [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32*
4872 // CHECK3-NEXT:    store i32 [[TMP1]], i32* [[TMP12]], align 4
4873 // CHECK3-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
4874 // CHECK3-NEXT:    store i8* null, i8** [[TMP13]], align 4
4875 // CHECK3-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
4876 // CHECK3-NEXT:    [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32*
4877 // CHECK3-NEXT:    store i32 [[TMP3]], i32* [[TMP15]], align 4
4878 // CHECK3-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
4879 // CHECK3-NEXT:    [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32*
4880 // CHECK3-NEXT:    store i32 [[TMP3]], i32* [[TMP17]], align 4
4881 // CHECK3-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
4882 // CHECK3-NEXT:    store i8* null, i8** [[TMP18]], align 4
4883 // CHECK3-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
4884 // CHECK3-NEXT:    [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32*
4885 // CHECK3-NEXT:    store i32 [[TMP5]], i32* [[TMP20]], align 4
4886 // CHECK3-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
4887 // CHECK3-NEXT:    [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i32*
4888 // CHECK3-NEXT:    store i32 [[TMP5]], i32* [[TMP22]], align 4
4889 // CHECK3-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
4890 // CHECK3-NEXT:    store i8* null, i8** [[TMP23]], align 4
4891 // CHECK3-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
4892 // CHECK3-NEXT:    [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i32*
4893 // CHECK3-NEXT:    store i32 [[TMP7]], i32* [[TMP25]], align 4
4894 // CHECK3-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
4895 // CHECK3-NEXT:    [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i32*
4896 // CHECK3-NEXT:    store i32 [[TMP7]], i32* [[TMP27]], align 4
4897 // CHECK3-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
4898 // CHECK3-NEXT:    store i8* null, i8** [[TMP28]], align 4
4899 // CHECK3-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
4900 // CHECK3-NEXT:    [[TMP30:%.*]] = bitcast i8** [[TMP29]] to [10 x i32]**
4901 // CHECK3-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP30]], align 4
4902 // CHECK3-NEXT:    [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
4903 // CHECK3-NEXT:    [[TMP32:%.*]] = bitcast i8** [[TMP31]] to [10 x i32]**
4904 // CHECK3-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP32]], align 4
4905 // CHECK3-NEXT:    [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4
4906 // CHECK3-NEXT:    store i8* null, i8** [[TMP33]], align 4
4907 // CHECK3-NEXT:    [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
4908 // CHECK3-NEXT:    [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
4909 // CHECK3-NEXT:    [[TMP36:%.*]] = load i32, i32* [[A]], align 4
4910 // CHECK3-NEXT:    store i32 [[TMP36]], i32* [[DOTCAPTURE_EXPR_]], align 4
4911 // CHECK3-NEXT:    [[TMP37:%.*]] = load i32, i32* [[N_ADDR]], align 4
4912 // CHECK3-NEXT:    store i32 [[TMP37]], i32* [[DOTCAPTURE_EXPR_2]], align 4
4913 // CHECK3-NEXT:    [[TMP38:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
4914 // CHECK3-NEXT:    [[TMP39:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
4915 // CHECK3-NEXT:    [[SUB:%.*]] = sub i32 [[TMP38]], [[TMP39]]
4916 // CHECK3-NEXT:    [[SUB4:%.*]] = sub i32 [[SUB]], 1
4917 // CHECK3-NEXT:    [[ADD:%.*]] = add i32 [[SUB4]], 1
4918 // CHECK3-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], 1
4919 // CHECK3-NEXT:    [[SUB5:%.*]] = sub i32 [[DIV]], 1
4920 // CHECK3-NEXT:    store i32 [[SUB5]], i32* [[DOTCAPTURE_EXPR_3]], align 4
4921 // CHECK3-NEXT:    [[TMP40:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
4922 // CHECK3-NEXT:    [[ADD6:%.*]] = add i32 [[TMP40]], 1
4923 // CHECK3-NEXT:    [[TMP41:%.*]] = zext i32 [[ADD6]] to i64
4924 // CHECK3-NEXT:    call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 [[TMP41]])
4925 // CHECK3-NEXT:    [[TMP42:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197.region_id, i32 5, i8** [[TMP34]], i8** [[TMP35]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes.16, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.17, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1)
4926 // CHECK3-NEXT:    [[TMP43:%.*]] = icmp ne i32 [[TMP42]], 0
4927 // CHECK3-NEXT:    br i1 [[TMP43]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
4928 // CHECK3:       omp_offload.failed:
4929 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], i32 [[TMP7]], [10 x i32]* [[B]]) #[[ATTR4]]
4930 // CHECK3-NEXT:    br label [[OMP_OFFLOAD_CONT]]
4931 // CHECK3:       omp_offload.cont:
4932 // CHECK3-NEXT:    br label [[OMP_IF_END:%.*]]
4933 // CHECK3:       omp_if.else:
4934 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], i32 [[TMP7]], [10 x i32]* [[B]]) #[[ATTR4]]
4935 // CHECK3-NEXT:    br label [[OMP_IF_END]]
4936 // CHECK3:       omp_if.end:
4937 // CHECK3-NEXT:    [[TMP44:%.*]] = load i32, i32* [[A]], align 4
4938 // CHECK3-NEXT:    ret i32 [[TMP44]]
4939 //
4940 //
4941 // CHECK3-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
4942 // CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat {
4943 // CHECK3-NEXT:  entry:
4944 // CHECK3-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
4945 // CHECK3-NEXT:    [[A:%.*]] = alloca i32, align 4
4946 // CHECK3-NEXT:    [[AA:%.*]] = alloca i16, align 2
4947 // CHECK3-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
4948 // CHECK3-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
4949 // CHECK3-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
4950 // CHECK3-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4
4951 // CHECK3-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4
4952 // CHECK3-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4
4953 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 4
4954 // CHECK3-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
4955 // CHECK3-NEXT:    store i32 0, i32* [[A]], align 4
4956 // CHECK3-NEXT:    store i16 0, i16* [[AA]], align 2
4957 // CHECK3-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
4958 // CHECK3-NEXT:    store i32 [[TMP0]], i32* [[A_CASTED]], align 4
4959 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
4960 // CHECK3-NEXT:    [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
4961 // CHECK3-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
4962 // CHECK3-NEXT:    store i16 [[TMP2]], i16* [[CONV]], align 2
4963 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
4964 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
4965 // CHECK3-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40
4966 // CHECK3-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
4967 // CHECK3:       omp_if.then:
4968 // CHECK3-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
4969 // CHECK3-NEXT:    [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i32*
4970 // CHECK3-NEXT:    store i32 [[TMP1]], i32* [[TMP6]], align 4
4971 // CHECK3-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
4972 // CHECK3-NEXT:    [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32*
4973 // CHECK3-NEXT:    store i32 [[TMP1]], i32* [[TMP8]], align 4
4974 // CHECK3-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
4975 // CHECK3-NEXT:    store i8* null, i8** [[TMP9]], align 4
4976 // CHECK3-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
4977 // CHECK3-NEXT:    [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i32*
4978 // CHECK3-NEXT:    store i32 [[TMP3]], i32* [[TMP11]], align 4
4979 // CHECK3-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
4980 // CHECK3-NEXT:    [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32*
4981 // CHECK3-NEXT:    store i32 [[TMP3]], i32* [[TMP13]], align 4
4982 // CHECK3-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
4983 // CHECK3-NEXT:    store i8* null, i8** [[TMP14]], align 4
4984 // CHECK3-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
4985 // CHECK3-NEXT:    [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]**
4986 // CHECK3-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 4
4987 // CHECK3-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
4988 // CHECK3-NEXT:    [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]**
4989 // CHECK3-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 4
4990 // CHECK3-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
4991 // CHECK3-NEXT:    store i8* null, i8** [[TMP19]], align 4
4992 // CHECK3-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
4993 // CHECK3-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
4994 // CHECK3-NEXT:    call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10)
4995 // CHECK3-NEXT:    [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.19, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.20, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1)
4996 // CHECK3-NEXT:    [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0
4997 // CHECK3-NEXT:    br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
4998 // CHECK3:       omp_offload.failed:
4999 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]]
5000 // CHECK3-NEXT:    br label [[OMP_OFFLOAD_CONT]]
5001 // CHECK3:       omp_offload.cont:
5002 // CHECK3-NEXT:    br label [[OMP_IF_END:%.*]]
5003 // CHECK3:       omp_if.else:
5004 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]]
5005 // CHECK3-NEXT:    br label [[OMP_IF_END]]
5006 // CHECK3:       omp_if.end:
5007 // CHECK3-NEXT:    [[TMP24:%.*]] = load i32, i32* [[A]], align 4
5008 // CHECK3-NEXT:    ret i32 [[TMP24]]
5009 //
5010 //
5011 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215
5012 // CHECK3-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {
5013 // CHECK3-NEXT:  entry:
5014 // CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
5015 // CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
5016 // CHECK3-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
5017 // CHECK3-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
5018 // CHECK3-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 4
5019 // CHECK3-NEXT:    [[B_CASTED:%.*]] = alloca i32, align 4
5020 // CHECK3-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
5021 // CHECK3-NEXT:    store i32 [[B]], i32* [[B_ADDR]], align 4
5022 // CHECK3-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
5023 // CHECK3-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
5024 // CHECK3-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 4
5025 // CHECK3-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
5026 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
5027 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
5028 // CHECK3-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
5029 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4
5030 // CHECK3-NEXT:    store i32 [[TMP4]], i32* [[B_CASTED]], align 4
5031 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4
5032 // CHECK3-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..12 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]])
5033 // CHECK3-NEXT:    ret void
5034 //
5035 //
5036 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..12
5037 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] {
5038 // CHECK3-NEXT:  entry:
5039 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
5040 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
5041 // CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
5042 // CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
5043 // CHECK3-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
5044 // CHECK3-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
5045 // CHECK3-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 4
5046 // CHECK3-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
5047 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 4
5048 // CHECK3-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
5049 // CHECK3-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
5050 // CHECK3-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
5051 // CHECK3-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
5052 // CHECK3-NEXT:    [[I:%.*]] = alloca i32, align 4
5053 // CHECK3-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
5054 // CHECK3-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
5055 // CHECK3-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
5056 // CHECK3-NEXT:    store i32 [[B]], i32* [[B_ADDR]], align 4
5057 // CHECK3-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
5058 // CHECK3-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
5059 // CHECK3-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 4
5060 // CHECK3-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
5061 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
5062 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
5063 // CHECK3-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
5064 // CHECK3-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
5065 // CHECK3-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
5066 // CHECK3-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
5067 // CHECK3-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
5068 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
5069 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
5070 // CHECK3-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
5071 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
5072 // CHECK3-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 9
5073 // CHECK3-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
5074 // CHECK3:       cond.true:
5075 // CHECK3-NEXT:    br label [[COND_END:%.*]]
5076 // CHECK3:       cond.false:
5077 // CHECK3-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
5078 // CHECK3-NEXT:    br label [[COND_END]]
5079 // CHECK3:       cond.end:
5080 // CHECK3-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
5081 // CHECK3-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
5082 // CHECK3-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
5083 // CHECK3-NEXT:    store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
5084 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
5085 // CHECK3:       omp.inner.for.cond:
5086 // CHECK3-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39
5087 // CHECK3-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !39
5088 // CHECK3-NEXT:    [[CMP3:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
5089 // CHECK3-NEXT:    br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
5090 // CHECK3:       omp.inner.for.body:
5091 // CHECK3-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39
5092 // CHECK3-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
5093 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
5094 // CHECK3-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !39
5095 // CHECK3-NEXT:    [[TMP12:%.*]] = load i32, i32* [[B_ADDR]], align 4, !llvm.access.group !39
5096 // CHECK3-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP12]] to double
5097 // CHECK3-NEXT:    [[ADD4:%.*]] = fadd double [[CONV]], 1.500000e+00
5098 // CHECK3-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
5099 // CHECK3-NEXT:    store double [[ADD4]], double* [[A]], align 4, !llvm.access.group !39
5100 // CHECK3-NEXT:    [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
5101 // CHECK3-NEXT:    [[TMP13:%.*]] = load double, double* [[A5]], align 4, !llvm.access.group !39
5102 // CHECK3-NEXT:    [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00
5103 // CHECK3-NEXT:    store double [[INC]], double* [[A5]], align 4, !llvm.access.group !39
5104 // CHECK3-NEXT:    [[CONV6:%.*]] = fptosi double [[INC]] to i16
5105 // CHECK3-NEXT:    [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]]
5106 // CHECK3-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP14]]
5107 // CHECK3-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
5108 // CHECK3-NEXT:    store i16 [[CONV6]], i16* [[ARRAYIDX7]], align 2, !llvm.access.group !39
5109 // CHECK3-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
5110 // CHECK3:       omp.body.continue:
5111 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
5112 // CHECK3:       omp.inner.for.inc:
5113 // CHECK3-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39
5114 // CHECK3-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP15]], 1
5115 // CHECK3-NEXT:    store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39
5116 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP40:![0-9]+]]
5117 // CHECK3:       omp.inner.for.end:
5118 // CHECK3-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
5119 // CHECK3:       omp.loop.exit:
5120 // CHECK3-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
5121 // CHECK3-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
5122 // CHECK3-NEXT:    [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0
5123 // CHECK3-NEXT:    br i1 [[TMP17]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
5124 // CHECK3:       .omp.final.then:
5125 // CHECK3-NEXT:    store i32 10, i32* [[I]], align 4
5126 // CHECK3-NEXT:    br label [[DOTOMP_FINAL_DONE]]
5127 // CHECK3:       .omp.final.done:
5128 // CHECK3-NEXT:    ret void
5129 //
5130 //
5131 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197
5132 // CHECK3-SAME: (i32 noundef [[A:%.*]], i32 noundef [[N:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
5133 // CHECK3-NEXT:  entry:
5134 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
5135 // CHECK3-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
5136 // CHECK3-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
5137 // CHECK3-NEXT:    [[AAA_ADDR:%.*]] = alloca i32, align 4
5138 // CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
5139 // CHECK3-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
5140 // CHECK3-NEXT:    [[N_CASTED:%.*]] = alloca i32, align 4
5141 // CHECK3-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
5142 // CHECK3-NEXT:    [[AAA_CASTED:%.*]] = alloca i32, align 4
5143 // CHECK3-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
5144 // CHECK3-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
5145 // CHECK3-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
5146 // CHECK3-NEXT:    store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
5147 // CHECK3-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
5148 // CHECK3-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
5149 // CHECK3-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
5150 // CHECK3-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
5151 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
5152 // CHECK3-NEXT:    store i32 [[TMP1]], i32* [[A_CASTED]], align 4
5153 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
5154 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
5155 // CHECK3-NEXT:    store i32 [[TMP3]], i32* [[N_CASTED]], align 4
5156 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_CASTED]], align 4
5157 // CHECK3-NEXT:    [[TMP5:%.*]] = load i16, i16* [[CONV]], align 2
5158 // CHECK3-NEXT:    [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
5159 // CHECK3-NEXT:    store i16 [[TMP5]], i16* [[CONV2]], align 2
5160 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, i32* [[AA_CASTED]], align 4
5161 // CHECK3-NEXT:    [[TMP7:%.*]] = load i8, i8* [[CONV1]], align 1
5162 // CHECK3-NEXT:    [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
5163 // CHECK3-NEXT:    store i8 [[TMP7]], i8* [[CONV3]], align 1
5164 // CHECK3-NEXT:    [[TMP8:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
5165 // CHECK3-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, [10 x i32]*)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP8]], [10 x i32]* [[TMP0]])
5166 // CHECK3-NEXT:    ret void
5167 //
5168 //
5169 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..15
5170 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[N:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] {
5171 // CHECK3-NEXT:  entry:
5172 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
5173 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
5174 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
5175 // CHECK3-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
5176 // CHECK3-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
5177 // CHECK3-NEXT:    [[AAA_ADDR:%.*]] = alloca i32, align 4
5178 // CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
5179 // CHECK3-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
5180 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 4
5181 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
5182 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
5183 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4
5184 // CHECK3-NEXT:    [[I:%.*]] = alloca i32, align 4
5185 // CHECK3-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
5186 // CHECK3-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
5187 // CHECK3-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
5188 // CHECK3-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
5189 // CHECK3-NEXT:    [[I6:%.*]] = alloca i32, align 4
5190 // CHECK3-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
5191 // CHECK3-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
5192 // CHECK3-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
5193 // CHECK3-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
5194 // CHECK3-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
5195 // CHECK3-NEXT:    store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
5196 // CHECK3-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
5197 // CHECK3-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
5198 // CHECK3-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
5199 // CHECK3-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
5200 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
5201 // CHECK3-NEXT:    store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
5202 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
5203 // CHECK3-NEXT:    store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4
5204 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
5205 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
5206 // CHECK3-NEXT:    [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]]
5207 // CHECK3-NEXT:    [[SUB4:%.*]] = sub i32 [[SUB]], 1
5208 // CHECK3-NEXT:    [[ADD:%.*]] = add i32 [[SUB4]], 1
5209 // CHECK3-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], 1
5210 // CHECK3-NEXT:    [[SUB5:%.*]] = sub i32 [[DIV]], 1
5211 // CHECK3-NEXT:    store i32 [[SUB5]], i32* [[DOTCAPTURE_EXPR_3]], align 4
5212 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
5213 // CHECK3-NEXT:    store i32 [[TMP5]], i32* [[I]], align 4
5214 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
5215 // CHECK3-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
5216 // CHECK3-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]]
5217 // CHECK3-NEXT:    br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
5218 // CHECK3:       omp.precond.then:
5219 // CHECK3-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
5220 // CHECK3-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
5221 // CHECK3-NEXT:    store i32 [[TMP8]], i32* [[DOTOMP_UB]], align 4
5222 // CHECK3-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
5223 // CHECK3-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
5224 // CHECK3-NEXT:    [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
5225 // CHECK3-NEXT:    [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
5226 // CHECK3-NEXT:    call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
5227 // CHECK3-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
5228 // CHECK3-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
5229 // CHECK3-NEXT:    [[CMP7:%.*]] = icmp ugt i32 [[TMP11]], [[TMP12]]
5230 // CHECK3-NEXT:    br i1 [[CMP7]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
5231 // CHECK3:       cond.true:
5232 // CHECK3-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
5233 // CHECK3-NEXT:    br label [[COND_END:%.*]]
5234 // CHECK3:       cond.false:
5235 // CHECK3-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
5236 // CHECK3-NEXT:    br label [[COND_END]]
5237 // CHECK3:       cond.end:
5238 // CHECK3-NEXT:    [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ]
5239 // CHECK3-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
5240 // CHECK3-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
5241 // CHECK3-NEXT:    store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4
5242 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
5243 // CHECK3:       omp.inner.for.cond:
5244 // CHECK3-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !42
5245 // CHECK3-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !42
5246 // CHECK3-NEXT:    [[ADD8:%.*]] = add i32 [[TMP17]], 1
5247 // CHECK3-NEXT:    [[CMP9:%.*]] = icmp ult i32 [[TMP16]], [[ADD8]]
5248 // CHECK3-NEXT:    br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
5249 // CHECK3:       omp.inner.for.body:
5250 // CHECK3-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group !42
5251 // CHECK3-NEXT:    [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !42
5252 // CHECK3-NEXT:    [[MUL:%.*]] = mul i32 [[TMP19]], 1
5253 // CHECK3-NEXT:    [[ADD10:%.*]] = add i32 [[TMP18]], [[MUL]]
5254 // CHECK3-NEXT:    store i32 [[ADD10]], i32* [[I6]], align 4, !llvm.access.group !42
5255 // CHECK3-NEXT:    [[TMP20:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !42
5256 // CHECK3-NEXT:    [[ADD11:%.*]] = add nsw i32 [[TMP20]], 1
5257 // CHECK3-NEXT:    store i32 [[ADD11]], i32* [[A_ADDR]], align 4, !llvm.access.group !42
5258 // CHECK3-NEXT:    [[TMP21:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !42
5259 // CHECK3-NEXT:    [[CONV12:%.*]] = sext i16 [[TMP21]] to i32
5260 // CHECK3-NEXT:    [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1
5261 // CHECK3-NEXT:    [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16
5262 // CHECK3-NEXT:    store i16 [[CONV14]], i16* [[CONV]], align 2, !llvm.access.group !42
5263 // CHECK3-NEXT:    [[TMP22:%.*]] = load i8, i8* [[CONV1]], align 1, !llvm.access.group !42
5264 // CHECK3-NEXT:    [[CONV15:%.*]] = sext i8 [[TMP22]] to i32
5265 // CHECK3-NEXT:    [[ADD16:%.*]] = add nsw i32 [[CONV15]], 1
5266 // CHECK3-NEXT:    [[CONV17:%.*]] = trunc i32 [[ADD16]] to i8
5267 // CHECK3-NEXT:    store i8 [[CONV17]], i8* [[CONV1]], align 1, !llvm.access.group !42
5268 // CHECK3-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
5269 // CHECK3-NEXT:    [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !42
5270 // CHECK3-NEXT:    [[ADD18:%.*]] = add nsw i32 [[TMP23]], 1
5271 // CHECK3-NEXT:    store i32 [[ADD18]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !42
5272 // CHECK3-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
5273 // CHECK3:       omp.body.continue:
5274 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
5275 // CHECK3:       omp.inner.for.inc:
5276 // CHECK3-NEXT:    [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !42
5277 // CHECK3-NEXT:    [[ADD19:%.*]] = add i32 [[TMP24]], 1
5278 // CHECK3-NEXT:    store i32 [[ADD19]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !42
5279 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP43:![0-9]+]]
5280 // CHECK3:       omp.inner.for.end:
5281 // CHECK3-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
5282 // CHECK3:       omp.loop.exit:
5283 // CHECK3-NEXT:    [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
5284 // CHECK3-NEXT:    [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4
5285 // CHECK3-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]])
5286 // CHECK3-NEXT:    [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
5287 // CHECK3-NEXT:    [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0
5288 // CHECK3-NEXT:    br i1 [[TMP28]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
5289 // CHECK3:       .omp.final.then:
5290 // CHECK3-NEXT:    [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
5291 // CHECK3-NEXT:    [[TMP30:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
5292 // CHECK3-NEXT:    [[TMP31:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
5293 // CHECK3-NEXT:    [[SUB20:%.*]] = sub i32 [[TMP30]], [[TMP31]]
5294 // CHECK3-NEXT:    [[SUB21:%.*]] = sub i32 [[SUB20]], 1
5295 // CHECK3-NEXT:    [[ADD22:%.*]] = add i32 [[SUB21]], 1
5296 // CHECK3-NEXT:    [[DIV23:%.*]] = udiv i32 [[ADD22]], 1
5297 // CHECK3-NEXT:    [[MUL24:%.*]] = mul i32 [[DIV23]], 1
5298 // CHECK3-NEXT:    [[ADD25:%.*]] = add i32 [[TMP29]], [[MUL24]]
5299 // CHECK3-NEXT:    store i32 [[ADD25]], i32* [[I6]], align 4
5300 // CHECK3-NEXT:    br label [[DOTOMP_FINAL_DONE]]
5301 // CHECK3:       .omp.final.done:
5302 // CHECK3-NEXT:    br label [[OMP_PRECOND_END]]
5303 // CHECK3:       omp.precond.end:
5304 // CHECK3-NEXT:    ret void
5305 //
5306 //
5307 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180
5308 // CHECK3-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
5309 // CHECK3-NEXT:  entry:
5310 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
5311 // CHECK3-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
5312 // CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
5313 // CHECK3-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
5314 // CHECK3-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
5315 // CHECK3-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
5316 // CHECK3-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
5317 // CHECK3-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
5318 // CHECK3-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
5319 // CHECK3-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
5320 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
5321 // CHECK3-NEXT:    store i32 [[TMP1]], i32* [[A_CASTED]], align 4
5322 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
5323 // CHECK3-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
5324 // CHECK3-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
5325 // CHECK3-NEXT:    store i16 [[TMP3]], i16* [[CONV1]], align 2
5326 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
5327 // CHECK3-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..18 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]])
5328 // CHECK3-NEXT:    ret void
5329 //
5330 //
5331 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..18
5332 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] {
5333 // CHECK3-NEXT:  entry:
5334 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
5335 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
5336 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
5337 // CHECK3-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
5338 // CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
5339 // CHECK3-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
5340 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 4
5341 // CHECK3-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
5342 // CHECK3-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
5343 // CHECK3-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
5344 // CHECK3-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
5345 // CHECK3-NEXT:    [[I:%.*]] = alloca i32, align 4
5346 // CHECK3-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
5347 // CHECK3-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
5348 // CHECK3-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
5349 // CHECK3-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
5350 // CHECK3-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
5351 // CHECK3-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
5352 // CHECK3-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
5353 // CHECK3-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
5354 // CHECK3-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
5355 // CHECK3-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
5356 // CHECK3-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
5357 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
5358 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
5359 // CHECK3-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
5360 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
5361 // CHECK3-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9
5362 // CHECK3-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
5363 // CHECK3:       cond.true:
5364 // CHECK3-NEXT:    br label [[COND_END:%.*]]
5365 // CHECK3:       cond.false:
5366 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
5367 // CHECK3-NEXT:    br label [[COND_END]]
5368 // CHECK3:       cond.end:
5369 // CHECK3-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
5370 // CHECK3-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
5371 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
5372 // CHECK3-NEXT:    store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
5373 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
5374 // CHECK3:       omp.inner.for.cond:
5375 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !45
5376 // CHECK3-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !45
5377 // CHECK3-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
5378 // CHECK3-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
5379 // CHECK3:       omp.inner.for.body:
5380 // CHECK3-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !45
5381 // CHECK3-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
5382 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
5383 // CHECK3-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !45
5384 // CHECK3-NEXT:    [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !45
5385 // CHECK3-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
5386 // CHECK3-NEXT:    store i32 [[ADD2]], i32* [[A_ADDR]], align 4, !llvm.access.group !45
5387 // CHECK3-NEXT:    [[TMP10:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !45
5388 // CHECK3-NEXT:    [[CONV3:%.*]] = sext i16 [[TMP10]] to i32
5389 // CHECK3-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
5390 // CHECK3-NEXT:    [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
5391 // CHECK3-NEXT:    store i16 [[CONV5]], i16* [[CONV]], align 2, !llvm.access.group !45
5392 // CHECK3-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
5393 // CHECK3-NEXT:    [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !45
5394 // CHECK3-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1
5395 // CHECK3-NEXT:    store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !45
5396 // CHECK3-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
5397 // CHECK3:       omp.body.continue:
5398 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
5399 // CHECK3:       omp.inner.for.inc:
5400 // CHECK3-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !45
5401 // CHECK3-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP12]], 1
5402 // CHECK3-NEXT:    store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !45
5403 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP46:![0-9]+]]
5404 // CHECK3:       omp.inner.for.end:
5405 // CHECK3-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
5406 // CHECK3:       omp.loop.exit:
5407 // CHECK3-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
5408 // CHECK3-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
5409 // CHECK3-NEXT:    [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
5410 // CHECK3-NEXT:    br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
5411 // CHECK3:       .omp.final.then:
5412 // CHECK3-NEXT:    store i32 10, i32* [[I]], align 4
5413 // CHECK3-NEXT:    br label [[DOTOMP_FINAL_DONE]]
5414 // CHECK3:       .omp.final.done:
5415 // CHECK3-NEXT:    ret void
5416 //
5417 //
5418 // CHECK3-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
5419 // CHECK3-SAME: () #[[ATTR5]] {
5420 // CHECK3-NEXT:  entry:
5421 // CHECK3-NEXT:    call void @__tgt_register_requires(i64 1)
5422 // CHECK3-NEXT:    ret void
5423 //
5424 //
5425 // CHECK4-LABEL: define {{[^@]+}}@_Z3fooi
5426 // CHECK4-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0:[0-9]+]] {
5427 // CHECK4-NEXT:  entry:
5428 // CHECK4-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
5429 // CHECK4-NEXT:    [[A:%.*]] = alloca i32, align 4
5430 // CHECK4-NEXT:    [[AA:%.*]] = alloca i16, align 2
5431 // CHECK4-NEXT:    [[B:%.*]] = alloca [10 x float], align 4
5432 // CHECK4-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 4
5433 // CHECK4-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 4
5434 // CHECK4-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 8
5435 // CHECK4-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i32, align 4
5436 // CHECK4-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4
5437 // CHECK4-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
5438 // CHECK4-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
5439 // CHECK4-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
5440 // CHECK4-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
5441 // CHECK4-NEXT:    [[DOTCAPTURE_EXPR__CASTED3:%.*]] = alloca i32, align 4
5442 // CHECK4-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4
5443 // CHECK4-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4
5444 // CHECK4-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4
5445 // CHECK4-NEXT:    [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4
5446 // CHECK4-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
5447 // CHECK4-NEXT:    [[AA_CASTED4:%.*]] = alloca i32, align 4
5448 // CHECK4-NEXT:    [[DOTOFFLOAD_BASEPTRS6:%.*]] = alloca [1 x i8*], align 4
5449 // CHECK4-NEXT:    [[DOTOFFLOAD_PTRS7:%.*]] = alloca [1 x i8*], align 4
5450 // CHECK4-NEXT:    [[DOTOFFLOAD_MAPPERS8:%.*]] = alloca [1 x i8*], align 4
5451 // CHECK4-NEXT:    [[TMP:%.*]] = alloca i32, align 4
5452 // CHECK4-NEXT:    [[A_CASTED9:%.*]] = alloca i32, align 4
5453 // CHECK4-NEXT:    [[AA_CASTED10:%.*]] = alloca i32, align 4
5454 // CHECK4-NEXT:    [[DOTOFFLOAD_BASEPTRS12:%.*]] = alloca [2 x i8*], align 4
5455 // CHECK4-NEXT:    [[DOTOFFLOAD_PTRS13:%.*]] = alloca [2 x i8*], align 4
5456 // CHECK4-NEXT:    [[DOTOFFLOAD_MAPPERS14:%.*]] = alloca [2 x i8*], align 4
5457 // CHECK4-NEXT:    [[_TMP15:%.*]] = alloca i32, align 4
5458 // CHECK4-NEXT:    [[A_CASTED18:%.*]] = alloca i32, align 4
5459 // CHECK4-NEXT:    [[DOTOFFLOAD_BASEPTRS21:%.*]] = alloca [9 x i8*], align 4
5460 // CHECK4-NEXT:    [[DOTOFFLOAD_PTRS22:%.*]] = alloca [9 x i8*], align 4
5461 // CHECK4-NEXT:    [[DOTOFFLOAD_MAPPERS23:%.*]] = alloca [9 x i8*], align 4
5462 // CHECK4-NEXT:    [[DOTOFFLOAD_SIZES:%.*]] = alloca [9 x i64], align 4
5463 // CHECK4-NEXT:    [[_TMP24:%.*]] = alloca i32, align 4
5464 // CHECK4-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]])
5465 // CHECK4-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
5466 // CHECK4-NEXT:    store i32 0, i32* [[A]], align 4
5467 // CHECK4-NEXT:    store i16 0, i16* [[AA]], align 2
5468 // CHECK4-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
5469 // CHECK4-NEXT:    [[TMP2:%.*]] = call i8* @llvm.stacksave()
5470 // CHECK4-NEXT:    store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4
5471 // CHECK4-NEXT:    [[VLA:%.*]] = alloca float, i32 [[TMP1]], align 4
5472 // CHECK4-NEXT:    store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
5473 // CHECK4-NEXT:    [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
5474 // CHECK4-NEXT:    [[TMP4:%.*]] = mul nuw i32 5, [[TMP3]]
5475 // CHECK4-NEXT:    [[VLA1:%.*]] = alloca double, i32 [[TMP4]], align 8
5476 // CHECK4-NEXT:    store i32 [[TMP3]], i32* [[__VLA_EXPR1]], align 4
5477 // CHECK4-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
5478 // CHECK4-NEXT:    store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_]], align 4
5479 // CHECK4-NEXT:    [[TMP6:%.*]] = load i32, i32* [[A]], align 4
5480 // CHECK4-NEXT:    store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_2]], align 4
5481 // CHECK4-NEXT:    [[TMP7:%.*]] = load i16, i16* [[AA]], align 2
5482 // CHECK4-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
5483 // CHECK4-NEXT:    store i16 [[TMP7]], i16* [[CONV]], align 2
5484 // CHECK4-NEXT:    [[TMP8:%.*]] = load i32, i32* [[AA_CASTED]], align 4
5485 // CHECK4-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
5486 // CHECK4-NEXT:    store i32 [[TMP9]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
5487 // CHECK4-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
5488 // CHECK4-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
5489 // CHECK4-NEXT:    store i32 [[TMP11]], i32* [[DOTCAPTURE_EXPR__CASTED3]], align 4
5490 // CHECK4-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED3]], align 4
5491 // CHECK4-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
5492 // CHECK4-NEXT:    [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i32*
5493 // CHECK4-NEXT:    store i32 [[TMP8]], i32* [[TMP14]], align 4
5494 // CHECK4-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
5495 // CHECK4-NEXT:    [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i32*
5496 // CHECK4-NEXT:    store i32 [[TMP8]], i32* [[TMP16]], align 4
5497 // CHECK4-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
5498 // CHECK4-NEXT:    store i8* null, i8** [[TMP17]], align 4
5499 // CHECK4-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
5500 // CHECK4-NEXT:    [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32*
5501 // CHECK4-NEXT:    store i32 [[TMP10]], i32* [[TMP19]], align 4
5502 // CHECK4-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
5503 // CHECK4-NEXT:    [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32*
5504 // CHECK4-NEXT:    store i32 [[TMP10]], i32* [[TMP21]], align 4
5505 // CHECK4-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
5506 // CHECK4-NEXT:    store i8* null, i8** [[TMP22]], align 4
5507 // CHECK4-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
5508 // CHECK4-NEXT:    [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i32*
5509 // CHECK4-NEXT:    store i32 [[TMP12]], i32* [[TMP24]], align 4
5510 // CHECK4-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
5511 // CHECK4-NEXT:    [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i32*
5512 // CHECK4-NEXT:    store i32 [[TMP12]], i32* [[TMP26]], align 4
5513 // CHECK4-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
5514 // CHECK4-NEXT:    store i8* null, i8** [[TMP27]], align 4
5515 // CHECK4-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
5516 // CHECK4-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
5517 // CHECK4-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 0
5518 // CHECK4-NEXT:    [[TMP31:%.*]] = load i16, i16* [[AA]], align 2
5519 // CHECK4-NEXT:    store i16 [[TMP31]], i16* [[TMP30]], align 4
5520 // CHECK4-NEXT:    [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 1
5521 // CHECK4-NEXT:    [[TMP33:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
5522 // CHECK4-NEXT:    store i32 [[TMP33]], i32* [[TMP32]], align 4
5523 // CHECK4-NEXT:    [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 2
5524 // CHECK4-NEXT:    [[TMP35:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
5525 // CHECK4-NEXT:    store i32 [[TMP35]], i32* [[TMP34]], align 4
5526 // CHECK4-NEXT:    [[TMP36:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 1, i32 72, i32 12, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1)
5527 // CHECK4-NEXT:    [[TMP37:%.*]] = bitcast i8* [[TMP36]] to %struct.kmp_task_t_with_privates*
5528 // CHECK4-NEXT:    [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP37]], i32 0, i32 0
5529 // CHECK4-NEXT:    [[TMP39:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP38]], i32 0, i32 0
5530 // CHECK4-NEXT:    [[TMP40:%.*]] = load i8*, i8** [[TMP39]], align 4
5531 // CHECK4-NEXT:    [[TMP41:%.*]] = bitcast %struct.anon* [[AGG_CAPTURED]] to i8*
5532 // CHECK4-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP40]], i8* align 4 [[TMP41]], i32 12, i1 false)
5533 // CHECK4-NEXT:    [[TMP42:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP37]], i32 0, i32 1
5534 // CHECK4-NEXT:    [[TMP43:%.*]] = bitcast i8* [[TMP40]] to %struct.anon*
5535 // CHECK4-NEXT:    [[TMP44:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 0
5536 // CHECK4-NEXT:    [[TMP45:%.*]] = bitcast [3 x i64]* [[TMP44]] to i8*
5537 // CHECK4-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP45]], i8* align 4 bitcast ([3 x i64]* @.offload_sizes to i8*), i32 24, i1 false)
5538 // CHECK4-NEXT:    [[TMP46:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 1
5539 // CHECK4-NEXT:    [[TMP47:%.*]] = bitcast [3 x i8*]* [[TMP46]] to i8*
5540 // CHECK4-NEXT:    [[TMP48:%.*]] = bitcast i8** [[TMP28]] to i8*
5541 // CHECK4-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP47]], i8* align 4 [[TMP48]], i32 12, i1 false)
5542 // CHECK4-NEXT:    [[TMP49:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 2
5543 // CHECK4-NEXT:    [[TMP50:%.*]] = bitcast [3 x i8*]* [[TMP49]] to i8*
5544 // CHECK4-NEXT:    [[TMP51:%.*]] = bitcast i8** [[TMP29]] to i8*
5545 // CHECK4-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP50]], i8* align 4 [[TMP51]], i32 12, i1 false)
5546 // CHECK4-NEXT:    [[TMP52:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 3
5547 // CHECK4-NEXT:    [[TMP53:%.*]] = load i16, i16* [[AA]], align 2
5548 // CHECK4-NEXT:    store i16 [[TMP53]], i16* [[TMP52]], align 4
5549 // CHECK4-NEXT:    [[TMP54:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i8* [[TMP36]])
5550 // CHECK4-NEXT:    [[TMP55:%.*]] = load i32, i32* [[A]], align 4
5551 // CHECK4-NEXT:    store i32 [[TMP55]], i32* [[A_CASTED]], align 4
5552 // CHECK4-NEXT:    [[TMP56:%.*]] = load i32, i32* [[A_CASTED]], align 4
5553 // CHECK4-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104(i32 [[TMP56]]) #[[ATTR4:[0-9]+]]
5554 // CHECK4-NEXT:    [[TMP57:%.*]] = load i16, i16* [[AA]], align 2
5555 // CHECK4-NEXT:    [[CONV5:%.*]] = bitcast i32* [[AA_CASTED4]] to i16*
5556 // CHECK4-NEXT:    store i16 [[TMP57]], i16* [[CONV5]], align 2
5557 // CHECK4-NEXT:    [[TMP58:%.*]] = load i32, i32* [[AA_CASTED4]], align 4
5558 // CHECK4-NEXT:    [[TMP59:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0
5559 // CHECK4-NEXT:    [[TMP60:%.*]] = bitcast i8** [[TMP59]] to i32*
5560 // CHECK4-NEXT:    store i32 [[TMP58]], i32* [[TMP60]], align 4
5561 // CHECK4-NEXT:    [[TMP61:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0
5562 // CHECK4-NEXT:    [[TMP62:%.*]] = bitcast i8** [[TMP61]] to i32*
5563 // CHECK4-NEXT:    store i32 [[TMP58]], i32* [[TMP62]], align 4
5564 // CHECK4-NEXT:    [[TMP63:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS8]], i32 0, i32 0
5565 // CHECK4-NEXT:    store i8* null, i8** [[TMP63]], align 4
5566 // CHECK4-NEXT:    [[TMP64:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0
5567 // CHECK4-NEXT:    [[TMP65:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0
5568 // CHECK4-NEXT:    call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10)
5569 // CHECK4-NEXT:    [[TMP66:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.region_id, i32 1, i8** [[TMP64]], i8** [[TMP65]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.4, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.5, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1)
5570 // CHECK4-NEXT:    [[TMP67:%.*]] = icmp ne i32 [[TMP66]], 0
5571 // CHECK4-NEXT:    br i1 [[TMP67]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
5572 // CHECK4:       omp_offload.failed:
5573 // CHECK4-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111(i32 [[TMP58]]) #[[ATTR4]]
5574 // CHECK4-NEXT:    br label [[OMP_OFFLOAD_CONT]]
5575 // CHECK4:       omp_offload.cont:
5576 // CHECK4-NEXT:    [[TMP68:%.*]] = load i32, i32* [[A]], align 4
5577 // CHECK4-NEXT:    store i32 [[TMP68]], i32* [[A_CASTED9]], align 4
5578 // CHECK4-NEXT:    [[TMP69:%.*]] = load i32, i32* [[A_CASTED9]], align 4
5579 // CHECK4-NEXT:    [[TMP70:%.*]] = load i16, i16* [[AA]], align 2
5580 // CHECK4-NEXT:    [[CONV11:%.*]] = bitcast i32* [[AA_CASTED10]] to i16*
5581 // CHECK4-NEXT:    store i16 [[TMP70]], i16* [[CONV11]], align 2
5582 // CHECK4-NEXT:    [[TMP71:%.*]] = load i32, i32* [[AA_CASTED10]], align 4
5583 // CHECK4-NEXT:    [[TMP72:%.*]] = load i32, i32* [[N_ADDR]], align 4
5584 // CHECK4-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP72]], 10
5585 // CHECK4-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
5586 // CHECK4:       omp_if.then:
5587 // CHECK4-NEXT:    [[TMP73:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS12]], i32 0, i32 0
5588 // CHECK4-NEXT:    [[TMP74:%.*]] = bitcast i8** [[TMP73]] to i32*
5589 // CHECK4-NEXT:    store i32 [[TMP69]], i32* [[TMP74]], align 4
5590 // CHECK4-NEXT:    [[TMP75:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS13]], i32 0, i32 0
5591 // CHECK4-NEXT:    [[TMP76:%.*]] = bitcast i8** [[TMP75]] to i32*
5592 // CHECK4-NEXT:    store i32 [[TMP69]], i32* [[TMP76]], align 4
5593 // CHECK4-NEXT:    [[TMP77:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS14]], i32 0, i32 0
5594 // CHECK4-NEXT:    store i8* null, i8** [[TMP77]], align 4
5595 // CHECK4-NEXT:    [[TMP78:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS12]], i32 0, i32 1
5596 // CHECK4-NEXT:    [[TMP79:%.*]] = bitcast i8** [[TMP78]] to i32*
5597 // CHECK4-NEXT:    store i32 [[TMP71]], i32* [[TMP79]], align 4
5598 // CHECK4-NEXT:    [[TMP80:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS13]], i32 0, i32 1
5599 // CHECK4-NEXT:    [[TMP81:%.*]] = bitcast i8** [[TMP80]] to i32*
5600 // CHECK4-NEXT:    store i32 [[TMP71]], i32* [[TMP81]], align 4
5601 // CHECK4-NEXT:    [[TMP82:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS14]], i32 0, i32 1
5602 // CHECK4-NEXT:    store i8* null, i8** [[TMP82]], align 4
5603 // CHECK4-NEXT:    [[TMP83:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS12]], i32 0, i32 0
5604 // CHECK4-NEXT:    [[TMP84:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS13]], i32 0, i32 0
5605 // CHECK4-NEXT:    call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10)
5606 // CHECK4-NEXT:    [[TMP85:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.region_id, i32 2, i8** [[TMP83]], i8** [[TMP84]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.7, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.8, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1)
5607 // CHECK4-NEXT:    [[TMP86:%.*]] = icmp ne i32 [[TMP85]], 0
5608 // CHECK4-NEXT:    br i1 [[TMP86]], label [[OMP_OFFLOAD_FAILED16:%.*]], label [[OMP_OFFLOAD_CONT17:%.*]]
5609 // CHECK4:       omp_offload.failed16:
5610 // CHECK4-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i32 [[TMP69]], i32 [[TMP71]]) #[[ATTR4]]
5611 // CHECK4-NEXT:    br label [[OMP_OFFLOAD_CONT17]]
5612 // CHECK4:       omp_offload.cont17:
5613 // CHECK4-NEXT:    br label [[OMP_IF_END:%.*]]
5614 // CHECK4:       omp_if.else:
5615 // CHECK4-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i32 [[TMP69]], i32 [[TMP71]]) #[[ATTR4]]
5616 // CHECK4-NEXT:    br label [[OMP_IF_END]]
5617 // CHECK4:       omp_if.end:
5618 // CHECK4-NEXT:    [[TMP87:%.*]] = load i32, i32* [[A]], align 4
5619 // CHECK4-NEXT:    store i32 [[TMP87]], i32* [[A_CASTED18]], align 4
5620 // CHECK4-NEXT:    [[TMP88:%.*]] = load i32, i32* [[A_CASTED18]], align 4
5621 // CHECK4-NEXT:    [[TMP89:%.*]] = load i32, i32* [[N_ADDR]], align 4
5622 // CHECK4-NEXT:    [[CMP19:%.*]] = icmp sgt i32 [[TMP89]], 20
5623 // CHECK4-NEXT:    br i1 [[CMP19]], label [[OMP_IF_THEN20:%.*]], label [[OMP_IF_ELSE27:%.*]]
5624 // CHECK4:       omp_if.then20:
5625 // CHECK4-NEXT:    [[TMP90:%.*]] = mul nuw i32 [[TMP1]], 4
5626 // CHECK4-NEXT:    [[TMP91:%.*]] = sext i32 [[TMP90]] to i64
5627 // CHECK4-NEXT:    [[TMP92:%.*]] = mul nuw i32 5, [[TMP3]]
5628 // CHECK4-NEXT:    [[TMP93:%.*]] = mul nuw i32 [[TMP92]], 8
5629 // CHECK4-NEXT:    [[TMP94:%.*]] = sext i32 [[TMP93]] to i64
5630 // CHECK4-NEXT:    [[TMP95:%.*]] = bitcast [9 x i64]* [[DOTOFFLOAD_SIZES]] to i8*
5631 // CHECK4-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP95]], i8* align 4 bitcast ([9 x i64]* @.offload_sizes.10 to i8*), i32 72, i1 false)
5632 // CHECK4-NEXT:    [[TMP96:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 0
5633 // CHECK4-NEXT:    [[TMP97:%.*]] = bitcast i8** [[TMP96]] to i32*
5634 // CHECK4-NEXT:    store i32 [[TMP88]], i32* [[TMP97]], align 4
5635 // CHECK4-NEXT:    [[TMP98:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 0
5636 // CHECK4-NEXT:    [[TMP99:%.*]] = bitcast i8** [[TMP98]] to i32*
5637 // CHECK4-NEXT:    store i32 [[TMP88]], i32* [[TMP99]], align 4
5638 // CHECK4-NEXT:    [[TMP100:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i32 0, i32 0
5639 // CHECK4-NEXT:    store i8* null, i8** [[TMP100]], align 4
5640 // CHECK4-NEXT:    [[TMP101:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 1
5641 // CHECK4-NEXT:    [[TMP102:%.*]] = bitcast i8** [[TMP101]] to [10 x float]**
5642 // CHECK4-NEXT:    store [10 x float]* [[B]], [10 x float]** [[TMP102]], align 4
5643 // CHECK4-NEXT:    [[TMP103:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 1
5644 // CHECK4-NEXT:    [[TMP104:%.*]] = bitcast i8** [[TMP103]] to [10 x float]**
5645 // CHECK4-NEXT:    store [10 x float]* [[B]], [10 x float]** [[TMP104]], align 4
5646 // CHECK4-NEXT:    [[TMP105:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i32 0, i32 1
5647 // CHECK4-NEXT:    store i8* null, i8** [[TMP105]], align 4
5648 // CHECK4-NEXT:    [[TMP106:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 2
5649 // CHECK4-NEXT:    [[TMP107:%.*]] = bitcast i8** [[TMP106]] to i32*
5650 // CHECK4-NEXT:    store i32 [[TMP1]], i32* [[TMP107]], align 4
5651 // CHECK4-NEXT:    [[TMP108:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 2
5652 // CHECK4-NEXT:    [[TMP109:%.*]] = bitcast i8** [[TMP108]] to i32*
5653 // CHECK4-NEXT:    store i32 [[TMP1]], i32* [[TMP109]], align 4
5654 // CHECK4-NEXT:    [[TMP110:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i32 0, i32 2
5655 // CHECK4-NEXT:    store i8* null, i8** [[TMP110]], align 4
5656 // CHECK4-NEXT:    [[TMP111:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 3
5657 // CHECK4-NEXT:    [[TMP112:%.*]] = bitcast i8** [[TMP111]] to float**
5658 // CHECK4-NEXT:    store float* [[VLA]], float** [[TMP112]], align 4
5659 // CHECK4-NEXT:    [[TMP113:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 3
5660 // CHECK4-NEXT:    [[TMP114:%.*]] = bitcast i8** [[TMP113]] to float**
5661 // CHECK4-NEXT:    store float* [[VLA]], float** [[TMP114]], align 4
5662 // CHECK4-NEXT:    [[TMP115:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3
5663 // CHECK4-NEXT:    store i64 [[TMP91]], i64* [[TMP115]], align 4
5664 // CHECK4-NEXT:    [[TMP116:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i32 0, i32 3
5665 // CHECK4-NEXT:    store i8* null, i8** [[TMP116]], align 4
5666 // CHECK4-NEXT:    [[TMP117:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 4
5667 // CHECK4-NEXT:    [[TMP118:%.*]] = bitcast i8** [[TMP117]] to [5 x [10 x double]]**
5668 // CHECK4-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP118]], align 4
5669 // CHECK4-NEXT:    [[TMP119:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 4
5670 // CHECK4-NEXT:    [[TMP120:%.*]] = bitcast i8** [[TMP119]] to [5 x [10 x double]]**
5671 // CHECK4-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP120]], align 4
5672 // CHECK4-NEXT:    [[TMP121:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i32 0, i32 4
5673 // CHECK4-NEXT:    store i8* null, i8** [[TMP121]], align 4
5674 // CHECK4-NEXT:    [[TMP122:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 5
5675 // CHECK4-NEXT:    [[TMP123:%.*]] = bitcast i8** [[TMP122]] to i32*
5676 // CHECK4-NEXT:    store i32 5, i32* [[TMP123]], align 4
5677 // CHECK4-NEXT:    [[TMP124:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 5
5678 // CHECK4-NEXT:    [[TMP125:%.*]] = bitcast i8** [[TMP124]] to i32*
5679 // CHECK4-NEXT:    store i32 5, i32* [[TMP125]], align 4
5680 // CHECK4-NEXT:    [[TMP126:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i32 0, i32 5
5681 // CHECK4-NEXT:    store i8* null, i8** [[TMP126]], align 4
5682 // CHECK4-NEXT:    [[TMP127:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 6
5683 // CHECK4-NEXT:    [[TMP128:%.*]] = bitcast i8** [[TMP127]] to i32*
5684 // CHECK4-NEXT:    store i32 [[TMP3]], i32* [[TMP128]], align 4
5685 // CHECK4-NEXT:    [[TMP129:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 6
5686 // CHECK4-NEXT:    [[TMP130:%.*]] = bitcast i8** [[TMP129]] to i32*
5687 // CHECK4-NEXT:    store i32 [[TMP3]], i32* [[TMP130]], align 4
5688 // CHECK4-NEXT:    [[TMP131:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i32 0, i32 6
5689 // CHECK4-NEXT:    store i8* null, i8** [[TMP131]], align 4
5690 // CHECK4-NEXT:    [[TMP132:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 7
5691 // CHECK4-NEXT:    [[TMP133:%.*]] = bitcast i8** [[TMP132]] to double**
5692 // CHECK4-NEXT:    store double* [[VLA1]], double** [[TMP133]], align 4
5693 // CHECK4-NEXT:    [[TMP134:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 7
5694 // CHECK4-NEXT:    [[TMP135:%.*]] = bitcast i8** [[TMP134]] to double**
5695 // CHECK4-NEXT:    store double* [[VLA1]], double** [[TMP135]], align 4
5696 // CHECK4-NEXT:    [[TMP136:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7
5697 // CHECK4-NEXT:    store i64 [[TMP94]], i64* [[TMP136]], align 4
5698 // CHECK4-NEXT:    [[TMP137:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i32 0, i32 7
5699 // CHECK4-NEXT:    store i8* null, i8** [[TMP137]], align 4
5700 // CHECK4-NEXT:    [[TMP138:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 8
5701 // CHECK4-NEXT:    [[TMP139:%.*]] = bitcast i8** [[TMP138]] to %struct.TT**
5702 // CHECK4-NEXT:    store %struct.TT* [[D]], %struct.TT** [[TMP139]], align 4
5703 // CHECK4-NEXT:    [[TMP140:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 8
5704 // CHECK4-NEXT:    [[TMP141:%.*]] = bitcast i8** [[TMP140]] to %struct.TT**
5705 // CHECK4-NEXT:    store %struct.TT* [[D]], %struct.TT** [[TMP141]], align 4
5706 // CHECK4-NEXT:    [[TMP142:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i32 0, i32 8
5707 // CHECK4-NEXT:    store i8* null, i8** [[TMP142]], align 4
5708 // CHECK4-NEXT:    [[TMP143:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 0
5709 // CHECK4-NEXT:    [[TMP144:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 0
5710 // CHECK4-NEXT:    [[TMP145:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
5711 // CHECK4-NEXT:    call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10)
5712 // CHECK4-NEXT:    [[TMP146:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142.region_id, i32 9, i8** [[TMP143]], i8** [[TMP144]], i64* [[TMP145]], i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_maptypes.11, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1)
5713 // CHECK4-NEXT:    [[TMP147:%.*]] = icmp ne i32 [[TMP146]], 0
5714 // CHECK4-NEXT:    br i1 [[TMP147]], label [[OMP_OFFLOAD_FAILED25:%.*]], label [[OMP_OFFLOAD_CONT26:%.*]]
5715 // CHECK4:       omp_offload.failed25:
5716 // CHECK4-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i32 [[TMP88]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR4]]
5717 // CHECK4-NEXT:    br label [[OMP_OFFLOAD_CONT26]]
5718 // CHECK4:       omp_offload.cont26:
5719 // CHECK4-NEXT:    br label [[OMP_IF_END28:%.*]]
5720 // CHECK4:       omp_if.else27:
5721 // CHECK4-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i32 [[TMP88]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR4]]
5722 // CHECK4-NEXT:    br label [[OMP_IF_END28]]
5723 // CHECK4:       omp_if.end28:
5724 // CHECK4-NEXT:    [[TMP148:%.*]] = load i32, i32* [[A]], align 4
5725 // CHECK4-NEXT:    [[TMP149:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
5726 // CHECK4-NEXT:    call void @llvm.stackrestore(i8* [[TMP149]])
5727 // CHECK4-NEXT:    ret i32 [[TMP148]]
5728 //
5729 //
5730 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97
5731 // CHECK4-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]], i32 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] {
5732 // CHECK4-NEXT:  entry:
5733 // CHECK4-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
5734 // CHECK4-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
5735 // CHECK4-NEXT:    [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4
5736 // CHECK4-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
5737 // CHECK4-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]])
5738 // CHECK4-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
5739 // CHECK4-NEXT:    store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
5740 // CHECK4-NEXT:    store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4
5741 // CHECK4-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
5742 // CHECK4-NEXT:    [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
5743 // CHECK4-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4
5744 // CHECK4-NEXT:    call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
5745 // CHECK4-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
5746 // CHECK4-NEXT:    [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
5747 // CHECK4-NEXT:    store i16 [[TMP3]], i16* [[CONV3]], align 2
5748 // CHECK4-NEXT:    [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
5749 // CHECK4-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]])
5750 // CHECK4-NEXT:    ret void
5751 //
5752 //
5753 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined.
5754 // CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR3:[0-9]+]] {
5755 // CHECK4-NEXT:  entry:
5756 // CHECK4-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
5757 // CHECK4-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
5758 // CHECK4-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
5759 // CHECK4-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
5760 // CHECK4-NEXT:    [[TMP:%.*]] = alloca i32, align 4
5761 // CHECK4-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
5762 // CHECK4-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
5763 // CHECK4-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
5764 // CHECK4-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
5765 // CHECK4-NEXT:    [[I:%.*]] = alloca i32, align 4
5766 // CHECK4-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
5767 // CHECK4-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
5768 // CHECK4-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
5769 // CHECK4-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
5770 // CHECK4-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
5771 // CHECK4-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
5772 // CHECK4-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
5773 // CHECK4-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
5774 // CHECK4-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
5775 // CHECK4-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
5776 // CHECK4-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
5777 // CHECK4-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
5778 // CHECK4-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
5779 // CHECK4-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
5780 // CHECK4:       cond.true:
5781 // CHECK4-NEXT:    br label [[COND_END:%.*]]
5782 // CHECK4:       cond.false:
5783 // CHECK4-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
5784 // CHECK4-NEXT:    br label [[COND_END]]
5785 // CHECK4:       cond.end:
5786 // CHECK4-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
5787 // CHECK4-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
5788 // CHECK4-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
5789 // CHECK4-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
5790 // CHECK4-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
5791 // CHECK4:       omp.inner.for.cond:
5792 // CHECK4-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
5793 // CHECK4-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !11
5794 // CHECK4-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
5795 // CHECK4-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
5796 // CHECK4:       omp.inner.for.body:
5797 // CHECK4-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
5798 // CHECK4-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
5799 // CHECK4-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
5800 // CHECK4-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11
5801 // CHECK4-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
5802 // CHECK4:       omp.body.continue:
5803 // CHECK4-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
5804 // CHECK4:       omp.inner.for.inc:
5805 // CHECK4-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
5806 // CHECK4-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
5807 // CHECK4-NEXT:    store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
5808 // CHECK4-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]
5809 // CHECK4:       omp.inner.for.end:
5810 // CHECK4-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
5811 // CHECK4:       omp.loop.exit:
5812 // CHECK4-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
5813 // CHECK4-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
5814 // CHECK4-NEXT:    [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0
5815 // CHECK4-NEXT:    br i1 [[TMP10]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
5816 // CHECK4:       .omp.final.then:
5817 // CHECK4-NEXT:    store i32 10, i32* [[I]], align 4
5818 // CHECK4-NEXT:    br label [[DOTOMP_FINAL_DONE]]
5819 // CHECK4:       .omp.final.done:
5820 // CHECK4-NEXT:    ret void
5821 //
5822 //
5823 // CHECK4-LABEL: define {{[^@]+}}@.omp_task_privates_map.
5824 // CHECK4-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], i16** noalias noundef [[TMP1:%.*]], [3 x i8*]** noalias noundef [[TMP2:%.*]], [3 x i8*]** noalias noundef [[TMP3:%.*]], [3 x i64]** noalias noundef [[TMP4:%.*]]) #[[ATTR5:[0-9]+]] {
5825 // CHECK4-NEXT:  entry:
5826 // CHECK4-NEXT:    [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 4
5827 // CHECK4-NEXT:    [[DOTADDR1:%.*]] = alloca i16**, align 4
5828 // CHECK4-NEXT:    [[DOTADDR2:%.*]] = alloca [3 x i8*]**, align 4
5829 // CHECK4-NEXT:    [[DOTADDR3:%.*]] = alloca [3 x i8*]**, align 4
5830 // CHECK4-NEXT:    [[DOTADDR4:%.*]] = alloca [3 x i64]**, align 4
5831 // CHECK4-NEXT:    store %struct..kmp_privates.t* [[TMP0]], %struct..kmp_privates.t** [[DOTADDR]], align 4
5832 // CHECK4-NEXT:    store i16** [[TMP1]], i16*** [[DOTADDR1]], align 4
5833 // CHECK4-NEXT:    store [3 x i8*]** [[TMP2]], [3 x i8*]*** [[DOTADDR2]], align 4
5834 // CHECK4-NEXT:    store [3 x i8*]** [[TMP3]], [3 x i8*]*** [[DOTADDR3]], align 4
5835 // CHECK4-NEXT:    store [3 x i64]** [[TMP4]], [3 x i64]*** [[DOTADDR4]], align 4
5836 // CHECK4-NEXT:    [[TMP5:%.*]] = load %struct..kmp_privates.t*, %struct..kmp_privates.t** [[DOTADDR]], align 4
5837 // CHECK4-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 0
5838 // CHECK4-NEXT:    [[TMP7:%.*]] = load [3 x i64]**, [3 x i64]*** [[DOTADDR4]], align 4
5839 // CHECK4-NEXT:    store [3 x i64]* [[TMP6]], [3 x i64]** [[TMP7]], align 4
5840 // CHECK4-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 1
5841 // CHECK4-NEXT:    [[TMP9:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR2]], align 4
5842 // CHECK4-NEXT:    store [3 x i8*]* [[TMP8]], [3 x i8*]** [[TMP9]], align 4
5843 // CHECK4-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 2
5844 // CHECK4-NEXT:    [[TMP11:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR3]], align 4
5845 // CHECK4-NEXT:    store [3 x i8*]* [[TMP10]], [3 x i8*]** [[TMP11]], align 4
5846 // CHECK4-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 3
5847 // CHECK4-NEXT:    [[TMP13:%.*]] = load i16**, i16*** [[DOTADDR1]], align 4
5848 // CHECK4-NEXT:    store i16* [[TMP12]], i16** [[TMP13]], align 4
5849 // CHECK4-NEXT:    ret void
5850 //
5851 //
5852 // CHECK4-LABEL: define {{[^@]+}}@.omp_task_entry.
5853 // CHECK4-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] {
5854 // CHECK4-NEXT:  entry:
5855 // CHECK4-NEXT:    [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
5856 // CHECK4-NEXT:    [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 4
5857 // CHECK4-NEXT:    [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 4
5858 // CHECK4-NEXT:    [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 4
5859 // CHECK4-NEXT:    [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 4
5860 // CHECK4-NEXT:    [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 4
5861 // CHECK4-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca i16*, align 4
5862 // CHECK4-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca [3 x i8*]*, align 4
5863 // CHECK4-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca [3 x i8*]*, align 4
5864 // CHECK4-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca [3 x i64]*, align 4
5865 // CHECK4-NEXT:    [[AA_CASTED_I:%.*]] = alloca i32, align 4
5866 // CHECK4-NEXT:    [[DOTCAPTURE_EXPR__CASTED_I:%.*]] = alloca i32, align 4
5867 // CHECK4-NEXT:    [[DOTCAPTURE_EXPR__CASTED4_I:%.*]] = alloca i32, align 4
5868 // CHECK4-NEXT:    [[DOTADDR:%.*]] = alloca i32, align 4
5869 // CHECK4-NEXT:    [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 4
5870 // CHECK4-NEXT:    store i32 [[TMP0]], i32* [[DOTADDR]], align 4
5871 // CHECK4-NEXT:    store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4
5872 // CHECK4-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4
5873 // CHECK4-NEXT:    [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4
5874 // CHECK4-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
5875 // CHECK4-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
5876 // CHECK4-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0
5877 // CHECK4-NEXT:    [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 4
5878 // CHECK4-NEXT:    [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon*
5879 // CHECK4-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1
5880 // CHECK4-NEXT:    [[TMP10:%.*]] = bitcast %struct..kmp_privates.t* [[TMP9]] to i8*
5881 // CHECK4-NEXT:    [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8*
5882 // CHECK4-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]])
5883 // CHECK4-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META21:![0-9]+]])
5884 // CHECK4-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META23:![0-9]+]])
5885 // CHECK4-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META25:![0-9]+]])
5886 // CHECK4-NEXT:    store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !27
5887 // CHECK4-NEXT:    store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 4, !noalias !27
5888 // CHECK4-NEXT:    store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !27
5889 // CHECK4-NEXT:    store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* @.omp_task_privates_map. to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !27
5890 // CHECK4-NEXT:    store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 4, !noalias !27
5891 // CHECK4-NEXT:    store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !27
5892 // CHECK4-NEXT:    [[TMP12:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !27
5893 // CHECK4-NEXT:    [[TMP13:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !27
5894 // CHECK4-NEXT:    [[TMP14:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !27
5895 // CHECK4-NEXT:    [[TMP15:%.*]] = bitcast void (i8*, ...)* [[TMP13]] to void (i8*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)*
5896 // CHECK4-NEXT:    call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR4]]
5897 // CHECK4-NEXT:    [[TMP16:%.*]] = load i16*, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 4, !noalias !27
5898 // CHECK4-NEXT:    [[TMP17:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 4, !noalias !27
5899 // CHECK4-NEXT:    [[TMP18:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 4, !noalias !27
5900 // CHECK4-NEXT:    [[TMP19:%.*]] = load [3 x i64]*, [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 4, !noalias !27
5901 // CHECK4-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP17]], i32 0, i32 0
5902 // CHECK4-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP18]], i32 0, i32 0
5903 // CHECK4-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[TMP19]], i32 0, i32 0
5904 // CHECK4-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP12]], i32 0, i32 1
5905 // CHECK4-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[TMP12]], i32 0, i32 2
5906 // CHECK4-NEXT:    [[TMP25:%.*]] = load i32, i32* [[TMP23]], align 4
5907 // CHECK4-NEXT:    call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) #[[ATTR4]]
5908 // CHECK4-NEXT:    [[TMP26:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 [[TMP25]], i32 1, i32 0, i8* null, i32 0, i8* null) #[[ATTR4]]
5909 // CHECK4-NEXT:    [[TMP27:%.*]] = icmp ne i32 [[TMP26]], 0
5910 // CHECK4-NEXT:    br i1 [[TMP27]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]]
5911 // CHECK4:       omp_offload.failed.i:
5912 // CHECK4-NEXT:    [[TMP28:%.*]] = load i16, i16* [[TMP16]], align 2
5913 // CHECK4-NEXT:    [[CONV_I:%.*]] = bitcast i32* [[AA_CASTED_I]] to i16*
5914 // CHECK4-NEXT:    store i16 [[TMP28]], i16* [[CONV_I]], align 2, !noalias !27
5915 // CHECK4-NEXT:    [[TMP29:%.*]] = load i32, i32* [[AA_CASTED_I]], align 4, !noalias !27
5916 // CHECK4-NEXT:    [[TMP30:%.*]] = load i32, i32* [[TMP23]], align 4
5917 // CHECK4-NEXT:    store i32 [[TMP30]], i32* [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias !27
5918 // CHECK4-NEXT:    [[TMP31:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias !27
5919 // CHECK4-NEXT:    [[TMP32:%.*]] = load i32, i32* [[TMP24]], align 4
5920 // CHECK4-NEXT:    store i32 [[TMP32]], i32* [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias !27
5921 // CHECK4-NEXT:    [[TMP33:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias !27
5922 // CHECK4-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97(i32 [[TMP29]], i32 [[TMP31]], i32 [[TMP33]]) #[[ATTR4]]
5923 // CHECK4-NEXT:    br label [[DOTOMP_OUTLINED__1_EXIT]]
5924 // CHECK4:       .omp_outlined..1.exit:
5925 // CHECK4-NEXT:    ret i32 0
5926 //
5927 //
5928 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104
5929 // CHECK4-SAME: (i32 noundef [[A:%.*]]) #[[ATTR3]] {
5930 // CHECK4-NEXT:  entry:
5931 // CHECK4-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
5932 // CHECK4-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
5933 // CHECK4-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
5934 // CHECK4-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
5935 // CHECK4-NEXT:    store i32 [[TMP0]], i32* [[A_CASTED]], align 4
5936 // CHECK4-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
5937 // CHECK4-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]])
5938 // CHECK4-NEXT:    ret void
5939 //
5940 //
5941 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..2
5942 // CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]]) #[[ATTR3]] {
5943 // CHECK4-NEXT:  entry:
5944 // CHECK4-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
5945 // CHECK4-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
5946 // CHECK4-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
5947 // CHECK4-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
5948 // CHECK4-NEXT:    [[TMP:%.*]] = alloca i32, align 4
5949 // CHECK4-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
5950 // CHECK4-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
5951 // CHECK4-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
5952 // CHECK4-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
5953 // CHECK4-NEXT:    [[A1:%.*]] = alloca i32, align 4
5954 // CHECK4-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
5955 // CHECK4-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
5956 // CHECK4-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
5957 // CHECK4-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
5958 // CHECK4-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
5959 // CHECK4-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
5960 // CHECK4-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
5961 // CHECK4-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
5962 // CHECK4-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
5963 // CHECK4-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
5964 // CHECK4-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
5965 // CHECK4-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
5966 // CHECK4-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
5967 // CHECK4:       cond.true:
5968 // CHECK4-NEXT:    br label [[COND_END:%.*]]
5969 // CHECK4:       cond.false:
5970 // CHECK4-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
5971 // CHECK4-NEXT:    br label [[COND_END]]
5972 // CHECK4:       cond.end:
5973 // CHECK4-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
5974 // CHECK4-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
5975 // CHECK4-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
5976 // CHECK4-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
5977 // CHECK4-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
5978 // CHECK4:       omp.inner.for.cond:
5979 // CHECK4-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
5980 // CHECK4-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
5981 // CHECK4-NEXT:    [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
5982 // CHECK4-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
5983 // CHECK4:       omp.inner.for.body:
5984 // CHECK4-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
5985 // CHECK4-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
5986 // CHECK4-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
5987 // CHECK4-NEXT:    store i32 [[ADD]], i32* [[A1]], align 4
5988 // CHECK4-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A1]], align 4
5989 // CHECK4-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
5990 // CHECK4-NEXT:    store i32 [[ADD3]], i32* [[A1]], align 4
5991 // CHECK4-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
5992 // CHECK4:       omp.body.continue:
5993 // CHECK4-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
5994 // CHECK4:       omp.inner.for.inc:
5995 // CHECK4-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
5996 // CHECK4-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP9]], 1
5997 // CHECK4-NEXT:    store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4
5998 // CHECK4-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]]
5999 // CHECK4:       omp.inner.for.end:
6000 // CHECK4-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
6001 // CHECK4:       omp.loop.exit:
6002 // CHECK4-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
6003 // CHECK4-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
6004 // CHECK4-NEXT:    [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0
6005 // CHECK4-NEXT:    br i1 [[TMP11]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
6006 // CHECK4:       .omp.final.then:
6007 // CHECK4-NEXT:    store i32 10, i32* [[A_ADDR]], align 4
6008 // CHECK4-NEXT:    br label [[DOTOMP_FINAL_DONE]]
6009 // CHECK4:       .omp.final.done:
6010 // CHECK4-NEXT:    ret void
6011 //
6012 //
6013 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111
6014 // CHECK4-SAME: (i32 noundef [[AA:%.*]]) #[[ATTR2]] {
6015 // CHECK4-NEXT:  entry:
6016 // CHECK4-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
6017 // CHECK4-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
6018 // CHECK4-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
6019 // CHECK4-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
6020 // CHECK4-NEXT:    [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
6021 // CHECK4-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
6022 // CHECK4-NEXT:    store i16 [[TMP0]], i16* [[CONV1]], align 2
6023 // CHECK4-NEXT:    [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
6024 // CHECK4-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP1]])
6025 // CHECK4-NEXT:    ret void
6026 //
6027 //
6028 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..3
6029 // CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR3]] {
6030 // CHECK4-NEXT:  entry:
6031 // CHECK4-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
6032 // CHECK4-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
6033 // CHECK4-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
6034 // CHECK4-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
6035 // CHECK4-NEXT:    [[TMP:%.*]] = alloca i32, align 4
6036 // CHECK4-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
6037 // CHECK4-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
6038 // CHECK4-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
6039 // CHECK4-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
6040 // CHECK4-NEXT:    [[I:%.*]] = alloca i32, align 4
6041 // CHECK4-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
6042 // CHECK4-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
6043 // CHECK4-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
6044 // CHECK4-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
6045 // CHECK4-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
6046 // CHECK4-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
6047 // CHECK4-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
6048 // CHECK4-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
6049 // CHECK4-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
6050 // CHECK4-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
6051 // CHECK4-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
6052 // CHECK4-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
6053 // CHECK4-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
6054 // CHECK4-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
6055 // CHECK4:       cond.true:
6056 // CHECK4-NEXT:    br label [[COND_END:%.*]]
6057 // CHECK4:       cond.false:
6058 // CHECK4-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
6059 // CHECK4-NEXT:    br label [[COND_END]]
6060 // CHECK4:       cond.end:
6061 // CHECK4-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
6062 // CHECK4-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
6063 // CHECK4-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
6064 // CHECK4-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
6065 // CHECK4-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
6066 // CHECK4:       omp.inner.for.cond:
6067 // CHECK4-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30
6068 // CHECK4-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !30
6069 // CHECK4-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
6070 // CHECK4-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
6071 // CHECK4:       omp.inner.for.body:
6072 // CHECK4-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30
6073 // CHECK4-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
6074 // CHECK4-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
6075 // CHECK4-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !30
6076 // CHECK4-NEXT:    [[TMP8:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !30
6077 // CHECK4-NEXT:    [[CONV2:%.*]] = sext i16 [[TMP8]] to i32
6078 // CHECK4-NEXT:    [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
6079 // CHECK4-NEXT:    [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
6080 // CHECK4-NEXT:    store i16 [[CONV4]], i16* [[CONV]], align 2, !llvm.access.group !30
6081 // CHECK4-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
6082 // CHECK4:       omp.body.continue:
6083 // CHECK4-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
6084 // CHECK4:       omp.inner.for.inc:
6085 // CHECK4-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30
6086 // CHECK4-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP9]], 1
6087 // CHECK4-NEXT:    store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30
6088 // CHECK4-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP31:![0-9]+]]
6089 // CHECK4:       omp.inner.for.end:
6090 // CHECK4-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
6091 // CHECK4:       omp.loop.exit:
6092 // CHECK4-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
6093 // CHECK4-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
6094 // CHECK4-NEXT:    [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0
6095 // CHECK4-NEXT:    br i1 [[TMP11]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
6096 // CHECK4:       .omp.final.then:
6097 // CHECK4-NEXT:    store i32 10, i32* [[I]], align 4
6098 // CHECK4-NEXT:    br label [[DOTOMP_FINAL_DONE]]
6099 // CHECK4:       .omp.final.done:
6100 // CHECK4-NEXT:    ret void
6101 //
6102 //
6103 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118
6104 // CHECK4-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] {
6105 // CHECK4-NEXT:  entry:
6106 // CHECK4-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
6107 // CHECK4-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
6108 // CHECK4-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
6109 // CHECK4-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
6110 // CHECK4-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
6111 // CHECK4-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
6112 // CHECK4-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
6113 // CHECK4-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
6114 // CHECK4-NEXT:    store i32 [[TMP0]], i32* [[A_CASTED]], align 4
6115 // CHECK4-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
6116 // CHECK4-NEXT:    [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
6117 // CHECK4-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
6118 // CHECK4-NEXT:    store i16 [[TMP2]], i16* [[CONV1]], align 2
6119 // CHECK4-NEXT:    [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
6120 // CHECK4-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]])
6121 // CHECK4-NEXT:    ret void
6122 //
6123 //
6124 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..6
6125 // CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR3]] {
6126 // CHECK4-NEXT:  entry:
6127 // CHECK4-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
6128 // CHECK4-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
6129 // CHECK4-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
6130 // CHECK4-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
6131 // CHECK4-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
6132 // CHECK4-NEXT:    [[TMP:%.*]] = alloca i32, align 4
6133 // CHECK4-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
6134 // CHECK4-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
6135 // CHECK4-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
6136 // CHECK4-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
6137 // CHECK4-NEXT:    [[I:%.*]] = alloca i32, align 4
6138 // CHECK4-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
6139 // CHECK4-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
6140 // CHECK4-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
6141 // CHECK4-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
6142 // CHECK4-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
6143 // CHECK4-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
6144 // CHECK4-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
6145 // CHECK4-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
6146 // CHECK4-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
6147 // CHECK4-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
6148 // CHECK4-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
6149 // CHECK4-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
6150 // CHECK4-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
6151 // CHECK4-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
6152 // CHECK4-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
6153 // CHECK4:       cond.true:
6154 // CHECK4-NEXT:    br label [[COND_END:%.*]]
6155 // CHECK4:       cond.false:
6156 // CHECK4-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
6157 // CHECK4-NEXT:    br label [[COND_END]]
6158 // CHECK4:       cond.end:
6159 // CHECK4-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
6160 // CHECK4-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
6161 // CHECK4-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
6162 // CHECK4-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
6163 // CHECK4-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
6164 // CHECK4:       omp.inner.for.cond:
6165 // CHECK4-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33
6166 // CHECK4-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !33
6167 // CHECK4-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
6168 // CHECK4-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
6169 // CHECK4:       omp.inner.for.body:
6170 // CHECK4-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33
6171 // CHECK4-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
6172 // CHECK4-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
6173 // CHECK4-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !33
6174 // CHECK4-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !33
6175 // CHECK4-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
6176 // CHECK4-NEXT:    store i32 [[ADD2]], i32* [[A_ADDR]], align 4, !llvm.access.group !33
6177 // CHECK4-NEXT:    [[TMP9:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !33
6178 // CHECK4-NEXT:    [[CONV3:%.*]] = sext i16 [[TMP9]] to i32
6179 // CHECK4-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
6180 // CHECK4-NEXT:    [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
6181 // CHECK4-NEXT:    store i16 [[CONV5]], i16* [[CONV]], align 2, !llvm.access.group !33
6182 // CHECK4-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
6183 // CHECK4:       omp.body.continue:
6184 // CHECK4-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
6185 // CHECK4:       omp.inner.for.inc:
6186 // CHECK4-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33
6187 // CHECK4-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP10]], 1
6188 // CHECK4-NEXT:    store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33
6189 // CHECK4-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP34:![0-9]+]]
6190 // CHECK4:       omp.inner.for.end:
6191 // CHECK4-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
6192 // CHECK4:       omp.loop.exit:
6193 // CHECK4-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
6194 // CHECK4-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
6195 // CHECK4-NEXT:    [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
6196 // CHECK4-NEXT:    br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
6197 // CHECK4:       .omp.final.then:
6198 // CHECK4-NEXT:    store i32 10, i32* [[I]], align 4
6199 // CHECK4-NEXT:    br label [[DOTOMP_FINAL_DONE]]
6200 // CHECK4:       .omp.final.done:
6201 // CHECK4-NEXT:    ret void
6202 //
6203 //
6204 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142
6205 // CHECK4-SAME: (i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] {
6206 // CHECK4-NEXT:  entry:
6207 // CHECK4-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
6208 // CHECK4-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
6209 // CHECK4-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
6210 // CHECK4-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 4
6211 // CHECK4-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
6212 // CHECK4-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
6213 // CHECK4-NEXT:    [[VLA_ADDR4:%.*]] = alloca i32, align 4
6214 // CHECK4-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 4
6215 // CHECK4-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
6216 // CHECK4-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
6217 // CHECK4-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
6218 // CHECK4-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
6219 // CHECK4-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
6220 // CHECK4-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 4
6221 // CHECK4-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
6222 // CHECK4-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
6223 // CHECK4-NEXT:    store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
6224 // CHECK4-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 4
6225 // CHECK4-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
6226 // CHECK4-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
6227 // CHECK4-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
6228 // CHECK4-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
6229 // CHECK4-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
6230 // CHECK4-NEXT:    [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
6231 // CHECK4-NEXT:    [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
6232 // CHECK4-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
6233 // CHECK4-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
6234 // CHECK4-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
6235 // CHECK4-NEXT:    store i32 [[TMP8]], i32* [[A_CASTED]], align 4
6236 // CHECK4-NEXT:    [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4
6237 // CHECK4-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]])
6238 // CHECK4-NEXT:    ret void
6239 //
6240 //
6241 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..9
6242 // CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR3]] {
6243 // CHECK4-NEXT:  entry:
6244 // CHECK4-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
6245 // CHECK4-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
6246 // CHECK4-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
6247 // CHECK4-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
6248 // CHECK4-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
6249 // CHECK4-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 4
6250 // CHECK4-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
6251 // CHECK4-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
6252 // CHECK4-NEXT:    [[VLA_ADDR4:%.*]] = alloca i32, align 4
6253 // CHECK4-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 4
6254 // CHECK4-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
6255 // CHECK4-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
6256 // CHECK4-NEXT:    [[TMP:%.*]] = alloca i32, align 4
6257 // CHECK4-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
6258 // CHECK4-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
6259 // CHECK4-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
6260 // CHECK4-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
6261 // CHECK4-NEXT:    [[I:%.*]] = alloca i32, align 4
6262 // CHECK4-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
6263 // CHECK4-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
6264 // CHECK4-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
6265 // CHECK4-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
6266 // CHECK4-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
6267 // CHECK4-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 4
6268 // CHECK4-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
6269 // CHECK4-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
6270 // CHECK4-NEXT:    store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
6271 // CHECK4-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 4
6272 // CHECK4-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
6273 // CHECK4-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
6274 // CHECK4-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
6275 // CHECK4-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
6276 // CHECK4-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
6277 // CHECK4-NEXT:    [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
6278 // CHECK4-NEXT:    [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
6279 // CHECK4-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
6280 // CHECK4-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
6281 // CHECK4-NEXT:    [[ARRAYDECAY:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 0
6282 // CHECK4-NEXT:    call void @llvm.assume(i1 true) [ "align"(float* [[ARRAYDECAY]], i32 16) ]
6283 // CHECK4-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
6284 // CHECK4-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
6285 // CHECK4-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
6286 // CHECK4-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
6287 // CHECK4-NEXT:    [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
6288 // CHECK4-NEXT:    [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4
6289 // CHECK4-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
6290 // CHECK4-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
6291 // CHECK4-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP10]], 9
6292 // CHECK4-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
6293 // CHECK4:       cond.true:
6294 // CHECK4-NEXT:    br label [[COND_END:%.*]]
6295 // CHECK4:       cond.false:
6296 // CHECK4-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
6297 // CHECK4-NEXT:    br label [[COND_END]]
6298 // CHECK4:       cond.end:
6299 // CHECK4-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ]
6300 // CHECK4-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
6301 // CHECK4-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
6302 // CHECK4-NEXT:    store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4
6303 // CHECK4-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
6304 // CHECK4:       omp.inner.for.cond:
6305 // CHECK4-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36
6306 // CHECK4-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !36
6307 // CHECK4-NEXT:    [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
6308 // CHECK4-NEXT:    br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
6309 // CHECK4:       omp.inner.for.body:
6310 // CHECK4-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36
6311 // CHECK4-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1
6312 // CHECK4-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
6313 // CHECK4-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !36
6314 // CHECK4-NEXT:    [[TMP16:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !36
6315 // CHECK4-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP16]], 1
6316 // CHECK4-NEXT:    store i32 [[ADD6]], i32* [[A_ADDR]], align 4, !llvm.access.group !36
6317 // CHECK4-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2
6318 // CHECK4-NEXT:    [[TMP17:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !36
6319 // CHECK4-NEXT:    [[CONV:%.*]] = fpext float [[TMP17]] to double
6320 // CHECK4-NEXT:    [[ADD7:%.*]] = fadd double [[CONV]], 1.000000e+00
6321 // CHECK4-NEXT:    [[CONV8:%.*]] = fptrunc double [[ADD7]] to float
6322 // CHECK4-NEXT:    store float [[CONV8]], float* [[ARRAYIDX]], align 4, !llvm.access.group !36
6323 // CHECK4-NEXT:    [[ARRAYIDX9:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3
6324 // CHECK4-NEXT:    [[TMP18:%.*]] = load float, float* [[ARRAYIDX9]], align 4, !llvm.access.group !36
6325 // CHECK4-NEXT:    [[CONV10:%.*]] = fpext float [[TMP18]] to double
6326 // CHECK4-NEXT:    [[ADD11:%.*]] = fadd double [[CONV10]], 1.000000e+00
6327 // CHECK4-NEXT:    [[CONV12:%.*]] = fptrunc double [[ADD11]] to float
6328 // CHECK4-NEXT:    store float [[CONV12]], float* [[ARRAYIDX9]], align 4, !llvm.access.group !36
6329 // CHECK4-NEXT:    [[ARRAYIDX13:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1
6330 // CHECK4-NEXT:    [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX13]], i32 0, i32 2
6331 // CHECK4-NEXT:    [[TMP19:%.*]] = load double, double* [[ARRAYIDX14]], align 8, !llvm.access.group !36
6332 // CHECK4-NEXT:    [[ADD15:%.*]] = fadd double [[TMP19]], 1.000000e+00
6333 // CHECK4-NEXT:    store double [[ADD15]], double* [[ARRAYIDX14]], align 8, !llvm.access.group !36
6334 // CHECK4-NEXT:    [[TMP20:%.*]] = mul nsw i32 1, [[TMP5]]
6335 // CHECK4-NEXT:    [[ARRAYIDX16:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP20]]
6336 // CHECK4-NEXT:    [[ARRAYIDX17:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX16]], i32 3
6337 // CHECK4-NEXT:    [[TMP21:%.*]] = load double, double* [[ARRAYIDX17]], align 8, !llvm.access.group !36
6338 // CHECK4-NEXT:    [[ADD18:%.*]] = fadd double [[TMP21]], 1.000000e+00
6339 // CHECK4-NEXT:    store double [[ADD18]], double* [[ARRAYIDX17]], align 8, !llvm.access.group !36
6340 // CHECK4-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0
6341 // CHECK4-NEXT:    [[TMP22:%.*]] = load i64, i64* [[X]], align 4, !llvm.access.group !36
6342 // CHECK4-NEXT:    [[ADD19:%.*]] = add nsw i64 [[TMP22]], 1
6343 // CHECK4-NEXT:    store i64 [[ADD19]], i64* [[X]], align 4, !llvm.access.group !36
6344 // CHECK4-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1
6345 // CHECK4-NEXT:    [[TMP23:%.*]] = load i8, i8* [[Y]], align 4, !llvm.access.group !36
6346 // CHECK4-NEXT:    [[CONV20:%.*]] = sext i8 [[TMP23]] to i32
6347 // CHECK4-NEXT:    [[ADD21:%.*]] = add nsw i32 [[CONV20]], 1
6348 // CHECK4-NEXT:    [[CONV22:%.*]] = trunc i32 [[ADD21]] to i8
6349 // CHECK4-NEXT:    store i8 [[CONV22]], i8* [[Y]], align 4, !llvm.access.group !36
6350 // CHECK4-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
6351 // CHECK4:       omp.body.continue:
6352 // CHECK4-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
6353 // CHECK4:       omp.inner.for.inc:
6354 // CHECK4-NEXT:    [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36
6355 // CHECK4-NEXT:    [[ADD23:%.*]] = add nsw i32 [[TMP24]], 1
6356 // CHECK4-NEXT:    store i32 [[ADD23]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36
6357 // CHECK4-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP37:![0-9]+]]
6358 // CHECK4:       omp.inner.for.end:
6359 // CHECK4-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
6360 // CHECK4:       omp.loop.exit:
6361 // CHECK4-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]])
6362 // CHECK4-NEXT:    [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
6363 // CHECK4-NEXT:    [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
6364 // CHECK4-NEXT:    br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
6365 // CHECK4:       .omp.final.then:
6366 // CHECK4-NEXT:    store i32 10, i32* [[I]], align 4
6367 // CHECK4-NEXT:    br label [[DOTOMP_FINAL_DONE]]
6368 // CHECK4:       .omp.final.done:
6369 // CHECK4-NEXT:    ret void
6370 //
6371 //
6372 // CHECK4-LABEL: define {{[^@]+}}@_Z3bari
6373 // CHECK4-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {
6374 // CHECK4-NEXT:  entry:
6375 // CHECK4-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
6376 // CHECK4-NEXT:    [[A:%.*]] = alloca i32, align 4
6377 // CHECK4-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4
6378 // CHECK4-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
6379 // CHECK4-NEXT:    store i32 0, i32* [[A]], align 4
6380 // CHECK4-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
6381 // CHECK4-NEXT:    [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]])
6382 // CHECK4-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
6383 // CHECK4-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
6384 // CHECK4-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
6385 // CHECK4-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
6386 // CHECK4-NEXT:    [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP2]])
6387 // CHECK4-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
6388 // CHECK4-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
6389 // CHECK4-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
6390 // CHECK4-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
6391 // CHECK4-NEXT:    [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]])
6392 // CHECK4-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
6393 // CHECK4-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
6394 // CHECK4-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
6395 // CHECK4-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
6396 // CHECK4-NEXT:    [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]])
6397 // CHECK4-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
6398 // CHECK4-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
6399 // CHECK4-NEXT:    store i32 [[ADD6]], i32* [[A]], align 4
6400 // CHECK4-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
6401 // CHECK4-NEXT:    ret i32 [[TMP8]]
6402 //
6403 //
6404 // CHECK4-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
6405 // CHECK4-SAME: (%struct.S1* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 {
6406 // CHECK4-NEXT:  entry:
6407 // CHECK4-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
6408 // CHECK4-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
6409 // CHECK4-NEXT:    [[B:%.*]] = alloca i32, align 4
6410 // CHECK4-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 4
6411 // CHECK4-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 4
6412 // CHECK4-NEXT:    [[B_CASTED:%.*]] = alloca i32, align 4
6413 // CHECK4-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4
6414 // CHECK4-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4
6415 // CHECK4-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4
6416 // CHECK4-NEXT:    [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 4
6417 // CHECK4-NEXT:    [[TMP:%.*]] = alloca i32, align 4
6418 // CHECK4-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
6419 // CHECK4-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
6420 // CHECK4-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
6421 // CHECK4-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
6422 // CHECK4-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
6423 // CHECK4-NEXT:    store i32 [[ADD]], i32* [[B]], align 4
6424 // CHECK4-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
6425 // CHECK4-NEXT:    [[TMP2:%.*]] = call i8* @llvm.stacksave()
6426 // CHECK4-NEXT:    store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4
6427 // CHECK4-NEXT:    [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]
6428 // CHECK4-NEXT:    [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2
6429 // CHECK4-NEXT:    store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
6430 // CHECK4-NEXT:    [[TMP4:%.*]] = load i32, i32* [[B]], align 4
6431 // CHECK4-NEXT:    store i32 [[TMP4]], i32* [[B_CASTED]], align 4
6432 // CHECK4-NEXT:    [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4
6433 // CHECK4-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
6434 // CHECK4-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 60
6435 // CHECK4-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
6436 // CHECK4:       omp_if.then:
6437 // CHECK4-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
6438 // CHECK4-NEXT:    [[TMP7:%.*]] = mul nuw i32 2, [[TMP1]]
6439 // CHECK4-NEXT:    [[TMP8:%.*]] = mul nuw i32 [[TMP7]], 2
6440 // CHECK4-NEXT:    [[TMP9:%.*]] = sext i32 [[TMP8]] to i64
6441 // CHECK4-NEXT:    [[TMP10:%.*]] = bitcast [5 x i64]* [[DOTOFFLOAD_SIZES]] to i8*
6442 // CHECK4-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP10]], i8* align 4 bitcast ([5 x i64]* @.offload_sizes.13 to i8*), i32 40, i1 false)
6443 // CHECK4-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
6444 // CHECK4-NEXT:    [[TMP12:%.*]] = bitcast i8** [[TMP11]] to %struct.S1**
6445 // CHECK4-NEXT:    store %struct.S1* [[THIS1]], %struct.S1** [[TMP12]], align 4
6446 // CHECK4-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
6447 // CHECK4-NEXT:    [[TMP14:%.*]] = bitcast i8** [[TMP13]] to double**
6448 // CHECK4-NEXT:    store double* [[A]], double** [[TMP14]], align 4
6449 // CHECK4-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
6450 // CHECK4-NEXT:    store i8* null, i8** [[TMP15]], align 4
6451 // CHECK4-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
6452 // CHECK4-NEXT:    [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32*
6453 // CHECK4-NEXT:    store i32 [[TMP5]], i32* [[TMP17]], align 4
6454 // CHECK4-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
6455 // CHECK4-NEXT:    [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32*
6456 // CHECK4-NEXT:    store i32 [[TMP5]], i32* [[TMP19]], align 4
6457 // CHECK4-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
6458 // CHECK4-NEXT:    store i8* null, i8** [[TMP20]], align 4
6459 // CHECK4-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
6460 // CHECK4-NEXT:    [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i32*
6461 // CHECK4-NEXT:    store i32 2, i32* [[TMP22]], align 4
6462 // CHECK4-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
6463 // CHECK4-NEXT:    [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i32*
6464 // CHECK4-NEXT:    store i32 2, i32* [[TMP24]], align 4
6465 // CHECK4-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
6466 // CHECK4-NEXT:    store i8* null, i8** [[TMP25]], align 4
6467 // CHECK4-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
6468 // CHECK4-NEXT:    [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i32*
6469 // CHECK4-NEXT:    store i32 [[TMP1]], i32* [[TMP27]], align 4
6470 // CHECK4-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
6471 // CHECK4-NEXT:    [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i32*
6472 // CHECK4-NEXT:    store i32 [[TMP1]], i32* [[TMP29]], align 4
6473 // CHECK4-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
6474 // CHECK4-NEXT:    store i8* null, i8** [[TMP30]], align 4
6475 // CHECK4-NEXT:    [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
6476 // CHECK4-NEXT:    [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i16**
6477 // CHECK4-NEXT:    store i16* [[VLA]], i16** [[TMP32]], align 4
6478 // CHECK4-NEXT:    [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
6479 // CHECK4-NEXT:    [[TMP34:%.*]] = bitcast i8** [[TMP33]] to i16**
6480 // CHECK4-NEXT:    store i16* [[VLA]], i16** [[TMP34]], align 4
6481 // CHECK4-NEXT:    [[TMP35:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4
6482 // CHECK4-NEXT:    store i64 [[TMP9]], i64* [[TMP35]], align 4
6483 // CHECK4-NEXT:    [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4
6484 // CHECK4-NEXT:    store i8* null, i8** [[TMP36]], align 4
6485 // CHECK4-NEXT:    [[TMP37:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
6486 // CHECK4-NEXT:    [[TMP38:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
6487 // CHECK4-NEXT:    [[TMP39:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
6488 // CHECK4-NEXT:    call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10)
6489 // CHECK4-NEXT:    [[TMP40:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215.region_id, i32 5, i8** [[TMP37]], i8** [[TMP38]], i64* [[TMP39]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.14, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1)
6490 // CHECK4-NEXT:    [[TMP41:%.*]] = icmp ne i32 [[TMP40]], 0
6491 // CHECK4-NEXT:    br i1 [[TMP41]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
6492 // CHECK4:       omp_offload.failed:
6493 // CHECK4-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR4]]
6494 // CHECK4-NEXT:    br label [[OMP_OFFLOAD_CONT]]
6495 // CHECK4:       omp_offload.cont:
6496 // CHECK4-NEXT:    br label [[OMP_IF_END:%.*]]
6497 // CHECK4:       omp_if.else:
6498 // CHECK4-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR4]]
6499 // CHECK4-NEXT:    br label [[OMP_IF_END]]
6500 // CHECK4:       omp_if.end:
6501 // CHECK4-NEXT:    [[TMP42:%.*]] = mul nsw i32 1, [[TMP1]]
6502 // CHECK4-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP42]]
6503 // CHECK4-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
6504 // CHECK4-NEXT:    [[TMP43:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2
6505 // CHECK4-NEXT:    [[CONV:%.*]] = sext i16 [[TMP43]] to i32
6506 // CHECK4-NEXT:    [[TMP44:%.*]] = load i32, i32* [[B]], align 4
6507 // CHECK4-NEXT:    [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP44]]
6508 // CHECK4-NEXT:    [[TMP45:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
6509 // CHECK4-NEXT:    call void @llvm.stackrestore(i8* [[TMP45]])
6510 // CHECK4-NEXT:    ret i32 [[ADD3]]
6511 //
6512 //
6513 // CHECK4-LABEL: define {{[^@]+}}@_ZL7fstatici
6514 // CHECK4-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {
6515 // CHECK4-NEXT:  entry:
6516 // CHECK4-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
6517 // CHECK4-NEXT:    [[A:%.*]] = alloca i32, align 4
6518 // CHECK4-NEXT:    [[AA:%.*]] = alloca i16, align 2
6519 // CHECK4-NEXT:    [[AAA:%.*]] = alloca i8, align 1
6520 // CHECK4-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
6521 // CHECK4-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
6522 // CHECK4-NEXT:    [[N_CASTED:%.*]] = alloca i32, align 4
6523 // CHECK4-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
6524 // CHECK4-NEXT:    [[AAA_CASTED:%.*]] = alloca i32, align 4
6525 // CHECK4-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4
6526 // CHECK4-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4
6527 // CHECK4-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4
6528 // CHECK4-NEXT:    [[TMP:%.*]] = alloca i32, align 4
6529 // CHECK4-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
6530 // CHECK4-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
6531 // CHECK4-NEXT:    [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4
6532 // CHECK4-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
6533 // CHECK4-NEXT:    store i32 0, i32* [[A]], align 4
6534 // CHECK4-NEXT:    store i16 0, i16* [[AA]], align 2
6535 // CHECK4-NEXT:    store i8 0, i8* [[AAA]], align 1
6536 // CHECK4-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
6537 // CHECK4-NEXT:    store i32 [[TMP0]], i32* [[A_CASTED]], align 4
6538 // CHECK4-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
6539 // CHECK4-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
6540 // CHECK4-NEXT:    store i32 [[TMP2]], i32* [[N_CASTED]], align 4
6541 // CHECK4-NEXT:    [[TMP3:%.*]] = load i32, i32* [[N_CASTED]], align 4
6542 // CHECK4-NEXT:    [[TMP4:%.*]] = load i16, i16* [[AA]], align 2
6543 // CHECK4-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
6544 // CHECK4-NEXT:    store i16 [[TMP4]], i16* [[CONV]], align 2
6545 // CHECK4-NEXT:    [[TMP5:%.*]] = load i32, i32* [[AA_CASTED]], align 4
6546 // CHECK4-NEXT:    [[TMP6:%.*]] = load i8, i8* [[AAA]], align 1
6547 // CHECK4-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
6548 // CHECK4-NEXT:    store i8 [[TMP6]], i8* [[CONV1]], align 1
6549 // CHECK4-NEXT:    [[TMP7:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
6550 // CHECK4-NEXT:    [[TMP8:%.*]] = load i32, i32* [[N_ADDR]], align 4
6551 // CHECK4-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP8]], 50
6552 // CHECK4-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
6553 // CHECK4:       omp_if.then:
6554 // CHECK4-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
6555 // CHECK4-NEXT:    [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32*
6556 // CHECK4-NEXT:    store i32 [[TMP1]], i32* [[TMP10]], align 4
6557 // CHECK4-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
6558 // CHECK4-NEXT:    [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32*
6559 // CHECK4-NEXT:    store i32 [[TMP1]], i32* [[TMP12]], align 4
6560 // CHECK4-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
6561 // CHECK4-NEXT:    store i8* null, i8** [[TMP13]], align 4
6562 // CHECK4-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
6563 // CHECK4-NEXT:    [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32*
6564 // CHECK4-NEXT:    store i32 [[TMP3]], i32* [[TMP15]], align 4
6565 // CHECK4-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
6566 // CHECK4-NEXT:    [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32*
6567 // CHECK4-NEXT:    store i32 [[TMP3]], i32* [[TMP17]], align 4
6568 // CHECK4-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
6569 // CHECK4-NEXT:    store i8* null, i8** [[TMP18]], align 4
6570 // CHECK4-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
6571 // CHECK4-NEXT:    [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32*
6572 // CHECK4-NEXT:    store i32 [[TMP5]], i32* [[TMP20]], align 4
6573 // CHECK4-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
6574 // CHECK4-NEXT:    [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i32*
6575 // CHECK4-NEXT:    store i32 [[TMP5]], i32* [[TMP22]], align 4
6576 // CHECK4-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
6577 // CHECK4-NEXT:    store i8* null, i8** [[TMP23]], align 4
6578 // CHECK4-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
6579 // CHECK4-NEXT:    [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i32*
6580 // CHECK4-NEXT:    store i32 [[TMP7]], i32* [[TMP25]], align 4
6581 // CHECK4-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
6582 // CHECK4-NEXT:    [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i32*
6583 // CHECK4-NEXT:    store i32 [[TMP7]], i32* [[TMP27]], align 4
6584 // CHECK4-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
6585 // CHECK4-NEXT:    store i8* null, i8** [[TMP28]], align 4
6586 // CHECK4-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
6587 // CHECK4-NEXT:    [[TMP30:%.*]] = bitcast i8** [[TMP29]] to [10 x i32]**
6588 // CHECK4-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP30]], align 4
6589 // CHECK4-NEXT:    [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
6590 // CHECK4-NEXT:    [[TMP32:%.*]] = bitcast i8** [[TMP31]] to [10 x i32]**
6591 // CHECK4-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP32]], align 4
6592 // CHECK4-NEXT:    [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4
6593 // CHECK4-NEXT:    store i8* null, i8** [[TMP33]], align 4
6594 // CHECK4-NEXT:    [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
6595 // CHECK4-NEXT:    [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
6596 // CHECK4-NEXT:    [[TMP36:%.*]] = load i32, i32* [[A]], align 4
6597 // CHECK4-NEXT:    store i32 [[TMP36]], i32* [[DOTCAPTURE_EXPR_]], align 4
6598 // CHECK4-NEXT:    [[TMP37:%.*]] = load i32, i32* [[N_ADDR]], align 4
6599 // CHECK4-NEXT:    store i32 [[TMP37]], i32* [[DOTCAPTURE_EXPR_2]], align 4
6600 // CHECK4-NEXT:    [[TMP38:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
6601 // CHECK4-NEXT:    [[TMP39:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
6602 // CHECK4-NEXT:    [[SUB:%.*]] = sub i32 [[TMP38]], [[TMP39]]
6603 // CHECK4-NEXT:    [[SUB4:%.*]] = sub i32 [[SUB]], 1
6604 // CHECK4-NEXT:    [[ADD:%.*]] = add i32 [[SUB4]], 1
6605 // CHECK4-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], 1
6606 // CHECK4-NEXT:    [[SUB5:%.*]] = sub i32 [[DIV]], 1
6607 // CHECK4-NEXT:    store i32 [[SUB5]], i32* [[DOTCAPTURE_EXPR_3]], align 4
6608 // CHECK4-NEXT:    [[TMP40:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
6609 // CHECK4-NEXT:    [[ADD6:%.*]] = add i32 [[TMP40]], 1
6610 // CHECK4-NEXT:    [[TMP41:%.*]] = zext i32 [[ADD6]] to i64
6611 // CHECK4-NEXT:    call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 [[TMP41]])
6612 // CHECK4-NEXT:    [[TMP42:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197.region_id, i32 5, i8** [[TMP34]], i8** [[TMP35]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes.16, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.17, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1)
6613 // CHECK4-NEXT:    [[TMP43:%.*]] = icmp ne i32 [[TMP42]], 0
6614 // CHECK4-NEXT:    br i1 [[TMP43]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
6615 // CHECK4:       omp_offload.failed:
6616 // CHECK4-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], i32 [[TMP7]], [10 x i32]* [[B]]) #[[ATTR4]]
6617 // CHECK4-NEXT:    br label [[OMP_OFFLOAD_CONT]]
6618 // CHECK4:       omp_offload.cont:
6619 // CHECK4-NEXT:    br label [[OMP_IF_END:%.*]]
6620 // CHECK4:       omp_if.else:
6621 // CHECK4-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], i32 [[TMP7]], [10 x i32]* [[B]]) #[[ATTR4]]
6622 // CHECK4-NEXT:    br label [[OMP_IF_END]]
6623 // CHECK4:       omp_if.end:
6624 // CHECK4-NEXT:    [[TMP44:%.*]] = load i32, i32* [[A]], align 4
6625 // CHECK4-NEXT:    ret i32 [[TMP44]]
6626 //
6627 //
6628 // CHECK4-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
6629 // CHECK4-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat {
6630 // CHECK4-NEXT:  entry:
6631 // CHECK4-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
6632 // CHECK4-NEXT:    [[A:%.*]] = alloca i32, align 4
6633 // CHECK4-NEXT:    [[AA:%.*]] = alloca i16, align 2
6634 // CHECK4-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
6635 // CHECK4-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
6636 // CHECK4-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
6637 // CHECK4-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4
6638 // CHECK4-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4
6639 // CHECK4-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4
6640 // CHECK4-NEXT:    [[TMP:%.*]] = alloca i32, align 4
6641 // CHECK4-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
6642 // CHECK4-NEXT:    store i32 0, i32* [[A]], align 4
6643 // CHECK4-NEXT:    store i16 0, i16* [[AA]], align 2
6644 // CHECK4-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
6645 // CHECK4-NEXT:    store i32 [[TMP0]], i32* [[A_CASTED]], align 4
6646 // CHECK4-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
6647 // CHECK4-NEXT:    [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
6648 // CHECK4-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
6649 // CHECK4-NEXT:    store i16 [[TMP2]], i16* [[CONV]], align 2
6650 // CHECK4-NEXT:    [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
6651 // CHECK4-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
6652 // CHECK4-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40
6653 // CHECK4-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
6654 // CHECK4:       omp_if.then:
6655 // CHECK4-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
6656 // CHECK4-NEXT:    [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i32*
6657 // CHECK4-NEXT:    store i32 [[TMP1]], i32* [[TMP6]], align 4
6658 // CHECK4-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
6659 // CHECK4-NEXT:    [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32*
6660 // CHECK4-NEXT:    store i32 [[TMP1]], i32* [[TMP8]], align 4
6661 // CHECK4-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
6662 // CHECK4-NEXT:    store i8* null, i8** [[TMP9]], align 4
6663 // CHECK4-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
6664 // CHECK4-NEXT:    [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i32*
6665 // CHECK4-NEXT:    store i32 [[TMP3]], i32* [[TMP11]], align 4
6666 // CHECK4-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
6667 // CHECK4-NEXT:    [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32*
6668 // CHECK4-NEXT:    store i32 [[TMP3]], i32* [[TMP13]], align 4
6669 // CHECK4-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
6670 // CHECK4-NEXT:    store i8* null, i8** [[TMP14]], align 4
6671 // CHECK4-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
6672 // CHECK4-NEXT:    [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]**
6673 // CHECK4-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 4
6674 // CHECK4-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
6675 // CHECK4-NEXT:    [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]**
6676 // CHECK4-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 4
6677 // CHECK4-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
6678 // CHECK4-NEXT:    store i8* null, i8** [[TMP19]], align 4
6679 // CHECK4-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
6680 // CHECK4-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
6681 // CHECK4-NEXT:    call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10)
6682 // CHECK4-NEXT:    [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.19, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.20, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1)
6683 // CHECK4-NEXT:    [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0
6684 // CHECK4-NEXT:    br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
6685 // CHECK4:       omp_offload.failed:
6686 // CHECK4-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]]
6687 // CHECK4-NEXT:    br label [[OMP_OFFLOAD_CONT]]
6688 // CHECK4:       omp_offload.cont:
6689 // CHECK4-NEXT:    br label [[OMP_IF_END:%.*]]
6690 // CHECK4:       omp_if.else:
6691 // CHECK4-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]]
6692 // CHECK4-NEXT:    br label [[OMP_IF_END]]
6693 // CHECK4:       omp_if.end:
6694 // CHECK4-NEXT:    [[TMP24:%.*]] = load i32, i32* [[A]], align 4
6695 // CHECK4-NEXT:    ret i32 [[TMP24]]
6696 //
6697 //
6698 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215
6699 // CHECK4-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {
6700 // CHECK4-NEXT:  entry:
6701 // CHECK4-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
6702 // CHECK4-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
6703 // CHECK4-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
6704 // CHECK4-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
6705 // CHECK4-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 4
6706 // CHECK4-NEXT:    [[B_CASTED:%.*]] = alloca i32, align 4
6707 // CHECK4-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
6708 // CHECK4-NEXT:    store i32 [[B]], i32* [[B_ADDR]], align 4
6709 // CHECK4-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
6710 // CHECK4-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
6711 // CHECK4-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 4
6712 // CHECK4-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
6713 // CHECK4-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
6714 // CHECK4-NEXT:    [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
6715 // CHECK4-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
6716 // CHECK4-NEXT:    [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4
6717 // CHECK4-NEXT:    store i32 [[TMP4]], i32* [[B_CASTED]], align 4
6718 // CHECK4-NEXT:    [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4
6719 // CHECK4-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..12 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]])
6720 // CHECK4-NEXT:    ret void
6721 //
6722 //
6723 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..12
6724 // CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] {
6725 // CHECK4-NEXT:  entry:
6726 // CHECK4-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
6727 // CHECK4-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
6728 // CHECK4-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
6729 // CHECK4-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
6730 // CHECK4-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
6731 // CHECK4-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
6732 // CHECK4-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 4
6733 // CHECK4-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
6734 // CHECK4-NEXT:    [[TMP:%.*]] = alloca i32, align 4
6735 // CHECK4-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
6736 // CHECK4-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
6737 // CHECK4-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
6738 // CHECK4-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
6739 // CHECK4-NEXT:    [[I:%.*]] = alloca i32, align 4
6740 // CHECK4-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
6741 // CHECK4-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
6742 // CHECK4-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
6743 // CHECK4-NEXT:    store i32 [[B]], i32* [[B_ADDR]], align 4
6744 // CHECK4-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
6745 // CHECK4-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
6746 // CHECK4-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 4
6747 // CHECK4-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
6748 // CHECK4-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
6749 // CHECK4-NEXT:    [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
6750 // CHECK4-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
6751 // CHECK4-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
6752 // CHECK4-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
6753 // CHECK4-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
6754 // CHECK4-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
6755 // CHECK4-NEXT:    [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
6756 // CHECK4-NEXT:    [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
6757 // CHECK4-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
6758 // CHECK4-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
6759 // CHECK4-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 9
6760 // CHECK4-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
6761 // CHECK4:       cond.true:
6762 // CHECK4-NEXT:    br label [[COND_END:%.*]]
6763 // CHECK4:       cond.false:
6764 // CHECK4-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
6765 // CHECK4-NEXT:    br label [[COND_END]]
6766 // CHECK4:       cond.end:
6767 // CHECK4-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
6768 // CHECK4-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
6769 // CHECK4-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
6770 // CHECK4-NEXT:    store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
6771 // CHECK4-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
6772 // CHECK4:       omp.inner.for.cond:
6773 // CHECK4-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39
6774 // CHECK4-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !39
6775 // CHECK4-NEXT:    [[CMP3:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
6776 // CHECK4-NEXT:    br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
6777 // CHECK4:       omp.inner.for.body:
6778 // CHECK4-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39
6779 // CHECK4-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
6780 // CHECK4-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
6781 // CHECK4-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !39
6782 // CHECK4-NEXT:    [[TMP12:%.*]] = load i32, i32* [[B_ADDR]], align 4, !llvm.access.group !39
6783 // CHECK4-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP12]] to double
6784 // CHECK4-NEXT:    [[ADD4:%.*]] = fadd double [[CONV]], 1.500000e+00
6785 // CHECK4-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
6786 // CHECK4-NEXT:    store double [[ADD4]], double* [[A]], align 4, !llvm.access.group !39
6787 // CHECK4-NEXT:    [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
6788 // CHECK4-NEXT:    [[TMP13:%.*]] = load double, double* [[A5]], align 4, !llvm.access.group !39
6789 // CHECK4-NEXT:    [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00
6790 // CHECK4-NEXT:    store double [[INC]], double* [[A5]], align 4, !llvm.access.group !39
6791 // CHECK4-NEXT:    [[CONV6:%.*]] = fptosi double [[INC]] to i16
6792 // CHECK4-NEXT:    [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]]
6793 // CHECK4-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP14]]
6794 // CHECK4-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
6795 // CHECK4-NEXT:    store i16 [[CONV6]], i16* [[ARRAYIDX7]], align 2, !llvm.access.group !39
6796 // CHECK4-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
6797 // CHECK4:       omp.body.continue:
6798 // CHECK4-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
6799 // CHECK4:       omp.inner.for.inc:
6800 // CHECK4-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39
6801 // CHECK4-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP15]], 1
6802 // CHECK4-NEXT:    store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39
6803 // CHECK4-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP40:![0-9]+]]
6804 // CHECK4:       omp.inner.for.end:
6805 // CHECK4-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
6806 // CHECK4:       omp.loop.exit:
6807 // CHECK4-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
6808 // CHECK4-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
6809 // CHECK4-NEXT:    [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0
6810 // CHECK4-NEXT:    br i1 [[TMP17]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
6811 // CHECK4:       .omp.final.then:
6812 // CHECK4-NEXT:    store i32 10, i32* [[I]], align 4
6813 // CHECK4-NEXT:    br label [[DOTOMP_FINAL_DONE]]
6814 // CHECK4:       .omp.final.done:
6815 // CHECK4-NEXT:    ret void
6816 //
6817 //
6818 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197
6819 // CHECK4-SAME: (i32 noundef [[A:%.*]], i32 noundef [[N:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
6820 // CHECK4-NEXT:  entry:
6821 // CHECK4-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
6822 // CHECK4-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
6823 // CHECK4-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
6824 // CHECK4-NEXT:    [[AAA_ADDR:%.*]] = alloca i32, align 4
6825 // CHECK4-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
6826 // CHECK4-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
6827 // CHECK4-NEXT:    [[N_CASTED:%.*]] = alloca i32, align 4
6828 // CHECK4-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
6829 // CHECK4-NEXT:    [[AAA_CASTED:%.*]] = alloca i32, align 4
6830 // CHECK4-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
6831 // CHECK4-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
6832 // CHECK4-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
6833 // CHECK4-NEXT:    store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
6834 // CHECK4-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
6835 // CHECK4-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
6836 // CHECK4-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
6837 // CHECK4-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
6838 // CHECK4-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
6839 // CHECK4-NEXT:    store i32 [[TMP1]], i32* [[A_CASTED]], align 4
6840 // CHECK4-NEXT:    [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
6841 // CHECK4-NEXT:    [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
6842 // CHECK4-NEXT:    store i32 [[TMP3]], i32* [[N_CASTED]], align 4
6843 // CHECK4-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_CASTED]], align 4
6844 // CHECK4-NEXT:    [[TMP5:%.*]] = load i16, i16* [[CONV]], align 2
6845 // CHECK4-NEXT:    [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
6846 // CHECK4-NEXT:    store i16 [[TMP5]], i16* [[CONV2]], align 2
6847 // CHECK4-NEXT:    [[TMP6:%.*]] = load i32, i32* [[AA_CASTED]], align 4
6848 // CHECK4-NEXT:    [[TMP7:%.*]] = load i8, i8* [[CONV1]], align 1
6849 // CHECK4-NEXT:    [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
6850 // CHECK4-NEXT:    store i8 [[TMP7]], i8* [[CONV3]], align 1
6851 // CHECK4-NEXT:    [[TMP8:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
6852 // CHECK4-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, [10 x i32]*)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP8]], [10 x i32]* [[TMP0]])
6853 // CHECK4-NEXT:    ret void
6854 //
6855 //
6856 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..15
6857 // CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[N:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] {
6858 // CHECK4-NEXT:  entry:
6859 // CHECK4-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
6860 // CHECK4-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
6861 // CHECK4-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
6862 // CHECK4-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
6863 // CHECK4-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
6864 // CHECK4-NEXT:    [[AAA_ADDR:%.*]] = alloca i32, align 4
6865 // CHECK4-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
6866 // CHECK4-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
6867 // CHECK4-NEXT:    [[TMP:%.*]] = alloca i32, align 4
6868 // CHECK4-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
6869 // CHECK4-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
6870 // CHECK4-NEXT:    [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4
6871 // CHECK4-NEXT:    [[I:%.*]] = alloca i32, align 4
6872 // CHECK4-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
6873 // CHECK4-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
6874 // CHECK4-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
6875 // CHECK4-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
6876 // CHECK4-NEXT:    [[I6:%.*]] = alloca i32, align 4
6877 // CHECK4-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
6878 // CHECK4-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
6879 // CHECK4-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
6880 // CHECK4-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
6881 // CHECK4-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
6882 // CHECK4-NEXT:    store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
6883 // CHECK4-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
6884 // CHECK4-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
6885 // CHECK4-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
6886 // CHECK4-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
6887 // CHECK4-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
6888 // CHECK4-NEXT:    store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
6889 // CHECK4-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
6890 // CHECK4-NEXT:    store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4
6891 // CHECK4-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
6892 // CHECK4-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
6893 // CHECK4-NEXT:    [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]]
6894 // CHECK4-NEXT:    [[SUB4:%.*]] = sub i32 [[SUB]], 1
6895 // CHECK4-NEXT:    [[ADD:%.*]] = add i32 [[SUB4]], 1
6896 // CHECK4-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], 1
6897 // CHECK4-NEXT:    [[SUB5:%.*]] = sub i32 [[DIV]], 1
6898 // CHECK4-NEXT:    store i32 [[SUB5]], i32* [[DOTCAPTURE_EXPR_3]], align 4
6899 // CHECK4-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
6900 // CHECK4-NEXT:    store i32 [[TMP5]], i32* [[I]], align 4
6901 // CHECK4-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
6902 // CHECK4-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
6903 // CHECK4-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]]
6904 // CHECK4-NEXT:    br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
6905 // CHECK4:       omp.precond.then:
6906 // CHECK4-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
6907 // CHECK4-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
6908 // CHECK4-NEXT:    store i32 [[TMP8]], i32* [[DOTOMP_UB]], align 4
6909 // CHECK4-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
6910 // CHECK4-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
6911 // CHECK4-NEXT:    [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
6912 // CHECK4-NEXT:    [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
6913 // CHECK4-NEXT:    call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
6914 // CHECK4-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
6915 // CHECK4-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
6916 // CHECK4-NEXT:    [[CMP7:%.*]] = icmp ugt i32 [[TMP11]], [[TMP12]]
6917 // CHECK4-NEXT:    br i1 [[CMP7]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
6918 // CHECK4:       cond.true:
6919 // CHECK4-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
6920 // CHECK4-NEXT:    br label [[COND_END:%.*]]
6921 // CHECK4:       cond.false:
6922 // CHECK4-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
6923 // CHECK4-NEXT:    br label [[COND_END]]
6924 // CHECK4:       cond.end:
6925 // CHECK4-NEXT:    [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ]
6926 // CHECK4-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
6927 // CHECK4-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
6928 // CHECK4-NEXT:    store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4
6929 // CHECK4-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
6930 // CHECK4:       omp.inner.for.cond:
6931 // CHECK4-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !42
6932 // CHECK4-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !42
6933 // CHECK4-NEXT:    [[ADD8:%.*]] = add i32 [[TMP17]], 1
6934 // CHECK4-NEXT:    [[CMP9:%.*]] = icmp ult i32 [[TMP16]], [[ADD8]]
6935 // CHECK4-NEXT:    br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
6936 // CHECK4:       omp.inner.for.body:
6937 // CHECK4-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group !42
6938 // CHECK4-NEXT:    [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !42
6939 // CHECK4-NEXT:    [[MUL:%.*]] = mul i32 [[TMP19]], 1
6940 // CHECK4-NEXT:    [[ADD10:%.*]] = add i32 [[TMP18]], [[MUL]]
6941 // CHECK4-NEXT:    store i32 [[ADD10]], i32* [[I6]], align 4, !llvm.access.group !42
6942 // CHECK4-NEXT:    [[TMP20:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !42
6943 // CHECK4-NEXT:    [[ADD11:%.*]] = add nsw i32 [[TMP20]], 1
6944 // CHECK4-NEXT:    store i32 [[ADD11]], i32* [[A_ADDR]], align 4, !llvm.access.group !42
6945 // CHECK4-NEXT:    [[TMP21:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !42
6946 // CHECK4-NEXT:    [[CONV12:%.*]] = sext i16 [[TMP21]] to i32
6947 // CHECK4-NEXT:    [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1
6948 // CHECK4-NEXT:    [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16
6949 // CHECK4-NEXT:    store i16 [[CONV14]], i16* [[CONV]], align 2, !llvm.access.group !42
6950 // CHECK4-NEXT:    [[TMP22:%.*]] = load i8, i8* [[CONV1]], align 1, !llvm.access.group !42
6951 // CHECK4-NEXT:    [[CONV15:%.*]] = sext i8 [[TMP22]] to i32
6952 // CHECK4-NEXT:    [[ADD16:%.*]] = add nsw i32 [[CONV15]], 1
6953 // CHECK4-NEXT:    [[CONV17:%.*]] = trunc i32 [[ADD16]] to i8
6954 // CHECK4-NEXT:    store i8 [[CONV17]], i8* [[CONV1]], align 1, !llvm.access.group !42
6955 // CHECK4-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
6956 // CHECK4-NEXT:    [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !42
6957 // CHECK4-NEXT:    [[ADD18:%.*]] = add nsw i32 [[TMP23]], 1
6958 // CHECK4-NEXT:    store i32 [[ADD18]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !42
6959 // CHECK4-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
6960 // CHECK4:       omp.body.continue:
6961 // CHECK4-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
6962 // CHECK4:       omp.inner.for.inc:
6963 // CHECK4-NEXT:    [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !42
6964 // CHECK4-NEXT:    [[ADD19:%.*]] = add i32 [[TMP24]], 1
6965 // CHECK4-NEXT:    store i32 [[ADD19]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !42
6966 // CHECK4-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP43:![0-9]+]]
6967 // CHECK4:       omp.inner.for.end:
6968 // CHECK4-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
6969 // CHECK4:       omp.loop.exit:
6970 // CHECK4-NEXT:    [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
6971 // CHECK4-NEXT:    [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4
6972 // CHECK4-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]])
6973 // CHECK4-NEXT:    [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
6974 // CHECK4-NEXT:    [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0
6975 // CHECK4-NEXT:    br i1 [[TMP28]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
6976 // CHECK4:       .omp.final.then:
6977 // CHECK4-NEXT:    [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
6978 // CHECK4-NEXT:    [[TMP30:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
6979 // CHECK4-NEXT:    [[TMP31:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
6980 // CHECK4-NEXT:    [[SUB20:%.*]] = sub i32 [[TMP30]], [[TMP31]]
6981 // CHECK4-NEXT:    [[SUB21:%.*]] = sub i32 [[SUB20]], 1
6982 // CHECK4-NEXT:    [[ADD22:%.*]] = add i32 [[SUB21]], 1
6983 // CHECK4-NEXT:    [[DIV23:%.*]] = udiv i32 [[ADD22]], 1
6984 // CHECK4-NEXT:    [[MUL24:%.*]] = mul i32 [[DIV23]], 1
6985 // CHECK4-NEXT:    [[ADD25:%.*]] = add i32 [[TMP29]], [[MUL24]]
6986 // CHECK4-NEXT:    store i32 [[ADD25]], i32* [[I6]], align 4
6987 // CHECK4-NEXT:    br label [[DOTOMP_FINAL_DONE]]
6988 // CHECK4:       .omp.final.done:
6989 // CHECK4-NEXT:    br label [[OMP_PRECOND_END]]
6990 // CHECK4:       omp.precond.end:
6991 // CHECK4-NEXT:    ret void
6992 //
6993 //
6994 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180
6995 // CHECK4-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
6996 // CHECK4-NEXT:  entry:
6997 // CHECK4-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
6998 // CHECK4-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
6999 // CHECK4-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
7000 // CHECK4-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
7001 // CHECK4-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
7002 // CHECK4-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
7003 // CHECK4-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
7004 // CHECK4-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
7005 // CHECK4-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
7006 // CHECK4-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
7007 // CHECK4-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
7008 // CHECK4-NEXT:    store i32 [[TMP1]], i32* [[A_CASTED]], align 4
7009 // CHECK4-NEXT:    [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
7010 // CHECK4-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
7011 // CHECK4-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
7012 // CHECK4-NEXT:    store i16 [[TMP3]], i16* [[CONV1]], align 2
7013 // CHECK4-NEXT:    [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
7014 // CHECK4-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..18 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]])
7015 // CHECK4-NEXT:    ret void
7016 //
7017 //
7018 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..18
7019 // CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] {
7020 // CHECK4-NEXT:  entry:
7021 // CHECK4-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
7022 // CHECK4-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
7023 // CHECK4-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
7024 // CHECK4-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
7025 // CHECK4-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
7026 // CHECK4-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
7027 // CHECK4-NEXT:    [[TMP:%.*]] = alloca i32, align 4
7028 // CHECK4-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
7029 // CHECK4-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
7030 // CHECK4-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
7031 // CHECK4-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
7032 // CHECK4-NEXT:    [[I:%.*]] = alloca i32, align 4
7033 // CHECK4-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
7034 // CHECK4-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
7035 // CHECK4-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
7036 // CHECK4-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
7037 // CHECK4-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
7038 // CHECK4-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
7039 // CHECK4-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
7040 // CHECK4-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
7041 // CHECK4-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
7042 // CHECK4-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
7043 // CHECK4-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
7044 // CHECK4-NEXT:    [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
7045 // CHECK4-NEXT:    [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
7046 // CHECK4-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
7047 // CHECK4-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
7048 // CHECK4-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9
7049 // CHECK4-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
7050 // CHECK4:       cond.true:
7051 // CHECK4-NEXT:    br label [[COND_END:%.*]]
7052 // CHECK4:       cond.false:
7053 // CHECK4-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
7054 // CHECK4-NEXT:    br label [[COND_END]]
7055 // CHECK4:       cond.end:
7056 // CHECK4-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
7057 // CHECK4-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
7058 // CHECK4-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
7059 // CHECK4-NEXT:    store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
7060 // CHECK4-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
7061 // CHECK4:       omp.inner.for.cond:
7062 // CHECK4-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !45
7063 // CHECK4-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !45
7064 // CHECK4-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
7065 // CHECK4-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
7066 // CHECK4:       omp.inner.for.body:
7067 // CHECK4-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !45
7068 // CHECK4-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
7069 // CHECK4-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
7070 // CHECK4-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !45
7071 // CHECK4-NEXT:    [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !45
7072 // CHECK4-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
7073 // CHECK4-NEXT:    store i32 [[ADD2]], i32* [[A_ADDR]], align 4, !llvm.access.group !45
7074 // CHECK4-NEXT:    [[TMP10:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !45
7075 // CHECK4-NEXT:    [[CONV3:%.*]] = sext i16 [[TMP10]] to i32
7076 // CHECK4-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
7077 // CHECK4-NEXT:    [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
7078 // CHECK4-NEXT:    store i16 [[CONV5]], i16* [[CONV]], align 2, !llvm.access.group !45
7079 // CHECK4-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
7080 // CHECK4-NEXT:    [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !45
7081 // CHECK4-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1
7082 // CHECK4-NEXT:    store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !45
7083 // CHECK4-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
7084 // CHECK4:       omp.body.continue:
7085 // CHECK4-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
7086 // CHECK4:       omp.inner.for.inc:
7087 // CHECK4-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !45
7088 // CHECK4-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP12]], 1
7089 // CHECK4-NEXT:    store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !45
7090 // CHECK4-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP46:![0-9]+]]
7091 // CHECK4:       omp.inner.for.end:
7092 // CHECK4-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
7093 // CHECK4:       omp.loop.exit:
7094 // CHECK4-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
7095 // CHECK4-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
7096 // CHECK4-NEXT:    [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
7097 // CHECK4-NEXT:    br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
7098 // CHECK4:       .omp.final.then:
7099 // CHECK4-NEXT:    store i32 10, i32* [[I]], align 4
7100 // CHECK4-NEXT:    br label [[DOTOMP_FINAL_DONE]]
7101 // CHECK4:       .omp.final.done:
7102 // CHECK4-NEXT:    ret void
7103 //
7104 //
7105 // CHECK4-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
7106 // CHECK4-SAME: () #[[ATTR5]] {
7107 // CHECK4-NEXT:  entry:
7108 // CHECK4-NEXT:    call void @__tgt_register_requires(i64 1)
7109 // CHECK4-NEXT:    ret void
7110 //
7111 //
7112 // CHECK5-LABEL: define {{[^@]+}}@_Z3fooi
7113 // CHECK5-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0:[0-9]+]] {
7114 // CHECK5-NEXT:  entry:
7115 // CHECK5-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
7116 // CHECK5-NEXT:    [[A:%.*]] = alloca i32, align 4
7117 // CHECK5-NEXT:    [[AA:%.*]] = alloca i16, align 2
7118 // CHECK5-NEXT:    [[B:%.*]] = alloca [10 x float], align 4
7119 // CHECK5-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 8
7120 // CHECK5-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
7121 // CHECK5-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 8
7122 // CHECK5-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i64, align 8
7123 // CHECK5-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8
7124 // CHECK5-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
7125 // CHECK5-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
7126 // CHECK5-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
7127 // CHECK5-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
7128 // CHECK5-NEXT:    [[DOTCAPTURE_EXPR__CASTED4:%.*]] = alloca i64, align 8
7129 // CHECK5-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8
7130 // CHECK5-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8
7131 // CHECK5-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8
7132 // CHECK5-NEXT:    [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4
7133 // CHECK5-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
7134 // CHECK5-NEXT:    [[AA_CASTED7:%.*]] = alloca i64, align 8
7135 // CHECK5-NEXT:    [[DOTOFFLOAD_BASEPTRS9:%.*]] = alloca [1 x i8*], align 8
7136 // CHECK5-NEXT:    [[DOTOFFLOAD_PTRS10:%.*]] = alloca [1 x i8*], align 8
7137 // CHECK5-NEXT:    [[DOTOFFLOAD_MAPPERS11:%.*]] = alloca [1 x i8*], align 8
7138 // CHECK5-NEXT:    [[TMP:%.*]] = alloca i32, align 4
7139 // CHECK5-NEXT:    [[A_CASTED12:%.*]] = alloca i64, align 8
7140 // CHECK5-NEXT:    [[AA_CASTED14:%.*]] = alloca i64, align 8
7141 // CHECK5-NEXT:    [[DOTOFFLOAD_BASEPTRS16:%.*]] = alloca [2 x i8*], align 8
7142 // CHECK5-NEXT:    [[DOTOFFLOAD_PTRS17:%.*]] = alloca [2 x i8*], align 8
7143 // CHECK5-NEXT:    [[DOTOFFLOAD_MAPPERS18:%.*]] = alloca [2 x i8*], align 8
7144 // CHECK5-NEXT:    [[_TMP19:%.*]] = alloca i32, align 4
7145 // CHECK5-NEXT:    [[A_CASTED22:%.*]] = alloca i64, align 8
7146 // CHECK5-NEXT:    [[DOTOFFLOAD_BASEPTRS26:%.*]] = alloca [9 x i8*], align 8
7147 // CHECK5-NEXT:    [[DOTOFFLOAD_PTRS27:%.*]] = alloca [9 x i8*], align 8
7148 // CHECK5-NEXT:    [[DOTOFFLOAD_MAPPERS28:%.*]] = alloca [9 x i8*], align 8
7149 // CHECK5-NEXT:    [[DOTOFFLOAD_SIZES:%.*]] = alloca [9 x i64], align 8
7150 // CHECK5-NEXT:    [[_TMP29:%.*]] = alloca i32, align 4
7151 // CHECK5-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]])
7152 // CHECK5-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
7153 // CHECK5-NEXT:    store i32 0, i32* [[A]], align 4
7154 // CHECK5-NEXT:    store i16 0, i16* [[AA]], align 2
7155 // CHECK5-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
7156 // CHECK5-NEXT:    [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
7157 // CHECK5-NEXT:    [[TMP3:%.*]] = call i8* @llvm.stacksave()
7158 // CHECK5-NEXT:    store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8
7159 // CHECK5-NEXT:    [[VLA:%.*]] = alloca float, i64 [[TMP2]], align 4
7160 // CHECK5-NEXT:    store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8
7161 // CHECK5-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
7162 // CHECK5-NEXT:    [[TMP5:%.*]] = zext i32 [[TMP4]] to i64
7163 // CHECK5-NEXT:    [[TMP6:%.*]] = mul nuw i64 5, [[TMP5]]
7164 // CHECK5-NEXT:    [[VLA1:%.*]] = alloca double, i64 [[TMP6]], align 8
7165 // CHECK5-NEXT:    store i64 [[TMP5]], i64* [[__VLA_EXPR1]], align 8
7166 // CHECK5-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
7167 // CHECK5-NEXT:    store i32 [[TMP7]], i32* [[DOTCAPTURE_EXPR_]], align 4
7168 // CHECK5-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
7169 // CHECK5-NEXT:    store i32 [[TMP8]], i32* [[DOTCAPTURE_EXPR_2]], align 4
7170 // CHECK5-NEXT:    [[TMP9:%.*]] = load i16, i16* [[AA]], align 2
7171 // CHECK5-NEXT:    [[CONV:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
7172 // CHECK5-NEXT:    store i16 [[TMP9]], i16* [[CONV]], align 2
7173 // CHECK5-NEXT:    [[TMP10:%.*]] = load i64, i64* [[AA_CASTED]], align 8
7174 // CHECK5-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
7175 // CHECK5-NEXT:    [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
7176 // CHECK5-NEXT:    store i32 [[TMP11]], i32* [[CONV3]], align 4
7177 // CHECK5-NEXT:    [[TMP12:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
7178 // CHECK5-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
7179 // CHECK5-NEXT:    [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED4]] to i32*
7180 // CHECK5-NEXT:    store i32 [[TMP13]], i32* [[CONV5]], align 4
7181 // CHECK5-NEXT:    [[TMP14:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED4]], align 8
7182 // CHECK5-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
7183 // CHECK5-NEXT:    [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i64*
7184 // CHECK5-NEXT:    store i64 [[TMP10]], i64* [[TMP16]], align 8
7185 // CHECK5-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
7186 // CHECK5-NEXT:    [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64*
7187 // CHECK5-NEXT:    store i64 [[TMP10]], i64* [[TMP18]], align 8
7188 // CHECK5-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
7189 // CHECK5-NEXT:    store i8* null, i8** [[TMP19]], align 8
7190 // CHECK5-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
7191 // CHECK5-NEXT:    [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i64*
7192 // CHECK5-NEXT:    store i64 [[TMP12]], i64* [[TMP21]], align 8
7193 // CHECK5-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
7194 // CHECK5-NEXT:    [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i64*
7195 // CHECK5-NEXT:    store i64 [[TMP12]], i64* [[TMP23]], align 8
7196 // CHECK5-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
7197 // CHECK5-NEXT:    store i8* null, i8** [[TMP24]], align 8
7198 // CHECK5-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
7199 // CHECK5-NEXT:    [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i64*
7200 // CHECK5-NEXT:    store i64 [[TMP14]], i64* [[TMP26]], align 8
7201 // CHECK5-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
7202 // CHECK5-NEXT:    [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i64*
7203 // CHECK5-NEXT:    store i64 [[TMP14]], i64* [[TMP28]], align 8
7204 // CHECK5-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
7205 // CHECK5-NEXT:    store i8* null, i8** [[TMP29]], align 8
7206 // CHECK5-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
7207 // CHECK5-NEXT:    [[TMP31:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
7208 // CHECK5-NEXT:    [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 0
7209 // CHECK5-NEXT:    [[TMP33:%.*]] = load i16, i16* [[AA]], align 2
7210 // CHECK5-NEXT:    store i16 [[TMP33]], i16* [[TMP32]], align 4
7211 // CHECK5-NEXT:    [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 1
7212 // CHECK5-NEXT:    [[TMP35:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
7213 // CHECK5-NEXT:    store i32 [[TMP35]], i32* [[TMP34]], align 4
7214 // CHECK5-NEXT:    [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 2
7215 // CHECK5-NEXT:    [[TMP37:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
7216 // CHECK5-NEXT:    store i32 [[TMP37]], i32* [[TMP36]], align 4
7217 // CHECK5-NEXT:    [[TMP38:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 1, i64 120, i64 12, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1)
7218 // CHECK5-NEXT:    [[TMP39:%.*]] = bitcast i8* [[TMP38]] to %struct.kmp_task_t_with_privates*
7219 // CHECK5-NEXT:    [[TMP40:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP39]], i32 0, i32 0
7220 // CHECK5-NEXT:    [[TMP41:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP40]], i32 0, i32 0
7221 // CHECK5-NEXT:    [[TMP42:%.*]] = load i8*, i8** [[TMP41]], align 8
7222 // CHECK5-NEXT:    [[TMP43:%.*]] = bitcast %struct.anon* [[AGG_CAPTURED]] to i8*
7223 // CHECK5-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP42]], i8* align 4 [[TMP43]], i64 12, i1 false)
7224 // CHECK5-NEXT:    [[TMP44:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP39]], i32 0, i32 1
7225 // CHECK5-NEXT:    [[TMP45:%.*]] = bitcast i8* [[TMP42]] to %struct.anon*
7226 // CHECK5-NEXT:    [[TMP46:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 0
7227 // CHECK5-NEXT:    [[TMP47:%.*]] = bitcast [3 x i8*]* [[TMP46]] to i8*
7228 // CHECK5-NEXT:    [[TMP48:%.*]] = bitcast i8** [[TMP30]] to i8*
7229 // CHECK5-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP47]], i8* align 8 [[TMP48]], i64 24, i1 false)
7230 // CHECK5-NEXT:    [[TMP49:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 1
7231 // CHECK5-NEXT:    [[TMP50:%.*]] = bitcast [3 x i8*]* [[TMP49]] to i8*
7232 // CHECK5-NEXT:    [[TMP51:%.*]] = bitcast i8** [[TMP31]] to i8*
7233 // CHECK5-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP50]], i8* align 8 [[TMP51]], i64 24, i1 false)
7234 // CHECK5-NEXT:    [[TMP52:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 2
7235 // CHECK5-NEXT:    [[TMP53:%.*]] = bitcast [3 x i64]* [[TMP52]] to i8*
7236 // CHECK5-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP53]], i8* align 8 bitcast ([3 x i64]* @.offload_sizes to i8*), i64 24, i1 false)
7237 // CHECK5-NEXT:    [[TMP54:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 3
7238 // CHECK5-NEXT:    [[TMP55:%.*]] = load i16, i16* [[AA]], align 2
7239 // CHECK5-NEXT:    store i16 [[TMP55]], i16* [[TMP54]], align 8
7240 // CHECK5-NEXT:    [[TMP56:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i8* [[TMP38]])
7241 // CHECK5-NEXT:    [[TMP57:%.*]] = load i32, i32* [[A]], align 4
7242 // CHECK5-NEXT:    [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32*
7243 // CHECK5-NEXT:    store i32 [[TMP57]], i32* [[CONV6]], align 4
7244 // CHECK5-NEXT:    [[TMP58:%.*]] = load i64, i64* [[A_CASTED]], align 8
7245 // CHECK5-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l102(i64 [[TMP58]]) #[[ATTR4:[0-9]+]]
7246 // CHECK5-NEXT:    [[TMP59:%.*]] = load i16, i16* [[AA]], align 2
7247 // CHECK5-NEXT:    [[CONV8:%.*]] = bitcast i64* [[AA_CASTED7]] to i16*
7248 // CHECK5-NEXT:    store i16 [[TMP59]], i16* [[CONV8]], align 2
7249 // CHECK5-NEXT:    [[TMP60:%.*]] = load i64, i64* [[AA_CASTED7]], align 8
7250 // CHECK5-NEXT:    [[TMP61:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS9]], i32 0, i32 0
7251 // CHECK5-NEXT:    [[TMP62:%.*]] = bitcast i8** [[TMP61]] to i64*
7252 // CHECK5-NEXT:    store i64 [[TMP60]], i64* [[TMP62]], align 8
7253 // CHECK5-NEXT:    [[TMP63:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS10]], i32 0, i32 0
7254 // CHECK5-NEXT:    [[TMP64:%.*]] = bitcast i8** [[TMP63]] to i64*
7255 // CHECK5-NEXT:    store i64 [[TMP60]], i64* [[TMP64]], align 8
7256 // CHECK5-NEXT:    [[TMP65:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS11]], i64 0, i64 0
7257 // CHECK5-NEXT:    store i8* null, i8** [[TMP65]], align 8
7258 // CHECK5-NEXT:    [[TMP66:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS9]], i32 0, i32 0
7259 // CHECK5-NEXT:    [[TMP67:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS10]], i32 0, i32 0
7260 // CHECK5-NEXT:    call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10)
7261 // CHECK5-NEXT:    [[TMP68:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.region_id, i32 1, i8** [[TMP66]], i8** [[TMP67]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.4, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.5, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1)
7262 // CHECK5-NEXT:    [[TMP69:%.*]] = icmp ne i32 [[TMP68]], 0
7263 // CHECK5-NEXT:    br i1 [[TMP69]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
7264 // CHECK5:       omp_offload.failed:
7265 // CHECK5-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111(i64 [[TMP60]]) #[[ATTR4]]
7266 // CHECK5-NEXT:    br label [[OMP_OFFLOAD_CONT]]
7267 // CHECK5:       omp_offload.cont:
7268 // CHECK5-NEXT:    [[TMP70:%.*]] = load i32, i32* [[A]], align 4
7269 // CHECK5-NEXT:    [[CONV13:%.*]] = bitcast i64* [[A_CASTED12]] to i32*
7270 // CHECK5-NEXT:    store i32 [[TMP70]], i32* [[CONV13]], align 4
7271 // CHECK5-NEXT:    [[TMP71:%.*]] = load i64, i64* [[A_CASTED12]], align 8
7272 // CHECK5-NEXT:    [[TMP72:%.*]] = load i16, i16* [[AA]], align 2
7273 // CHECK5-NEXT:    [[CONV15:%.*]] = bitcast i64* [[AA_CASTED14]] to i16*
7274 // CHECK5-NEXT:    store i16 [[TMP72]], i16* [[CONV15]], align 2
7275 // CHECK5-NEXT:    [[TMP73:%.*]] = load i64, i64* [[AA_CASTED14]], align 8
7276 // CHECK5-NEXT:    [[TMP74:%.*]] = load i32, i32* [[N_ADDR]], align 4
7277 // CHECK5-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP74]], 10
7278 // CHECK5-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
7279 // CHECK5:       omp_if.then:
7280 // CHECK5-NEXT:    [[TMP75:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 0
7281 // CHECK5-NEXT:    [[TMP76:%.*]] = bitcast i8** [[TMP75]] to i64*
7282 // CHECK5-NEXT:    store i64 [[TMP71]], i64* [[TMP76]], align 8
7283 // CHECK5-NEXT:    [[TMP77:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 0
7284 // CHECK5-NEXT:    [[TMP78:%.*]] = bitcast i8** [[TMP77]] to i64*
7285 // CHECK5-NEXT:    store i64 [[TMP71]], i64* [[TMP78]], align 8
7286 // CHECK5-NEXT:    [[TMP79:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 0
7287 // CHECK5-NEXT:    store i8* null, i8** [[TMP79]], align 8
7288 // CHECK5-NEXT:    [[TMP80:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 1
7289 // CHECK5-NEXT:    [[TMP81:%.*]] = bitcast i8** [[TMP80]] to i64*
7290 // CHECK5-NEXT:    store i64 [[TMP73]], i64* [[TMP81]], align 8
7291 // CHECK5-NEXT:    [[TMP82:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 1
7292 // CHECK5-NEXT:    [[TMP83:%.*]] = bitcast i8** [[TMP82]] to i64*
7293 // CHECK5-NEXT:    store i64 [[TMP73]], i64* [[TMP83]], align 8
7294 // CHECK5-NEXT:    [[TMP84:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 1
7295 // CHECK5-NEXT:    store i8* null, i8** [[TMP84]], align 8
7296 // CHECK5-NEXT:    [[TMP85:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 0
7297 // CHECK5-NEXT:    [[TMP86:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 0
7298 // CHECK5-NEXT:    call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10)
7299 // CHECK5-NEXT:    [[TMP87:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.region_id, i32 2, i8** [[TMP85]], i8** [[TMP86]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.7, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.8, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1)
7300 // CHECK5-NEXT:    [[TMP88:%.*]] = icmp ne i32 [[TMP87]], 0
7301 // CHECK5-NEXT:    br i1 [[TMP88]], label [[OMP_OFFLOAD_FAILED20:%.*]], label [[OMP_OFFLOAD_CONT21:%.*]]
7302 // CHECK5:       omp_offload.failed20:
7303 // CHECK5-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i64 [[TMP71]], i64 [[TMP73]]) #[[ATTR4]]
7304 // CHECK5-NEXT:    br label [[OMP_OFFLOAD_CONT21]]
7305 // CHECK5:       omp_offload.cont21:
7306 // CHECK5-NEXT:    br label [[OMP_IF_END:%.*]]
7307 // CHECK5:       omp_if.else:
7308 // CHECK5-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i64 [[TMP71]], i64 [[TMP73]]) #[[ATTR4]]
7309 // CHECK5-NEXT:    br label [[OMP_IF_END]]
7310 // CHECK5:       omp_if.end:
7311 // CHECK5-NEXT:    [[TMP89:%.*]] = load i32, i32* [[A]], align 4
7312 // CHECK5-NEXT:    [[CONV23:%.*]] = bitcast i64* [[A_CASTED22]] to i32*
7313 // CHECK5-NEXT:    store i32 [[TMP89]], i32* [[CONV23]], align 4
7314 // CHECK5-NEXT:    [[TMP90:%.*]] = load i64, i64* [[A_CASTED22]], align 8
7315 // CHECK5-NEXT:    [[TMP91:%.*]] = load i32, i32* [[N_ADDR]], align 4
7316 // CHECK5-NEXT:    [[CMP24:%.*]] = icmp sgt i32 [[TMP91]], 20
7317 // CHECK5-NEXT:    br i1 [[CMP24]], label [[OMP_IF_THEN25:%.*]], label [[OMP_IF_ELSE32:%.*]]
7318 // CHECK5:       omp_if.then25:
7319 // CHECK5-NEXT:    [[TMP92:%.*]] = mul nuw i64 [[TMP2]], 4
7320 // CHECK5-NEXT:    [[TMP93:%.*]] = mul nuw i64 5, [[TMP5]]
7321 // CHECK5-NEXT:    [[TMP94:%.*]] = mul nuw i64 [[TMP93]], 8
7322 // CHECK5-NEXT:    [[TMP95:%.*]] = bitcast [9 x i64]* [[DOTOFFLOAD_SIZES]] to i8*
7323 // CHECK5-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP95]], i8* align 8 bitcast ([9 x i64]* @.offload_sizes.10 to i8*), i64 72, i1 false)
7324 // CHECK5-NEXT:    [[TMP96:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS26]], i32 0, i32 0
7325 // CHECK5-NEXT:    [[TMP97:%.*]] = bitcast i8** [[TMP96]] to i64*
7326 // CHECK5-NEXT:    store i64 [[TMP90]], i64* [[TMP97]], align 8
7327 // CHECK5-NEXT:    [[TMP98:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS27]], i32 0, i32 0
7328 // CHECK5-NEXT:    [[TMP99:%.*]] = bitcast i8** [[TMP98]] to i64*
7329 // CHECK5-NEXT:    store i64 [[TMP90]], i64* [[TMP99]], align 8
7330 // CHECK5-NEXT:    [[TMP100:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS28]], i64 0, i64 0
7331 // CHECK5-NEXT:    store i8* null, i8** [[TMP100]], align 8
7332 // CHECK5-NEXT:    [[TMP101:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS26]], i32 0, i32 1
7333 // CHECK5-NEXT:    [[TMP102:%.*]] = bitcast i8** [[TMP101]] to [10 x float]**
7334 // CHECK5-NEXT:    store [10 x float]* [[B]], [10 x float]** [[TMP102]], align 8
7335 // CHECK5-NEXT:    [[TMP103:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS27]], i32 0, i32 1
7336 // CHECK5-NEXT:    [[TMP104:%.*]] = bitcast i8** [[TMP103]] to [10 x float]**
7337 // CHECK5-NEXT:    store [10 x float]* [[B]], [10 x float]** [[TMP104]], align 8
7338 // CHECK5-NEXT:    [[TMP105:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS28]], i64 0, i64 1
7339 // CHECK5-NEXT:    store i8* null, i8** [[TMP105]], align 8
7340 // CHECK5-NEXT:    [[TMP106:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS26]], i32 0, i32 2
7341 // CHECK5-NEXT:    [[TMP107:%.*]] = bitcast i8** [[TMP106]] to i64*
7342 // CHECK5-NEXT:    store i64 [[TMP2]], i64* [[TMP107]], align 8
7343 // CHECK5-NEXT:    [[TMP108:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS27]], i32 0, i32 2
7344 // CHECK5-NEXT:    [[TMP109:%.*]] = bitcast i8** [[TMP108]] to i64*
7345 // CHECK5-NEXT:    store i64 [[TMP2]], i64* [[TMP109]], align 8
7346 // CHECK5-NEXT:    [[TMP110:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS28]], i64 0, i64 2
7347 // CHECK5-NEXT:    store i8* null, i8** [[TMP110]], align 8
7348 // CHECK5-NEXT:    [[TMP111:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS26]], i32 0, i32 3
7349 // CHECK5-NEXT:    [[TMP112:%.*]] = bitcast i8** [[TMP111]] to float**
7350 // CHECK5-NEXT:    store float* [[VLA]], float** [[TMP112]], align 8
7351 // CHECK5-NEXT:    [[TMP113:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS27]], i32 0, i32 3
7352 // CHECK5-NEXT:    [[TMP114:%.*]] = bitcast i8** [[TMP113]] to float**
7353 // CHECK5-NEXT:    store float* [[VLA]], float** [[TMP114]], align 8
7354 // CHECK5-NEXT:    [[TMP115:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3
7355 // CHECK5-NEXT:    store i64 [[TMP92]], i64* [[TMP115]], align 8
7356 // CHECK5-NEXT:    [[TMP116:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS28]], i64 0, i64 3
7357 // CHECK5-NEXT:    store i8* null, i8** [[TMP116]], align 8
7358 // CHECK5-NEXT:    [[TMP117:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS26]], i32 0, i32 4
7359 // CHECK5-NEXT:    [[TMP118:%.*]] = bitcast i8** [[TMP117]] to [5 x [10 x double]]**
7360 // CHECK5-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP118]], align 8
7361 // CHECK5-NEXT:    [[TMP119:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS27]], i32 0, i32 4
7362 // CHECK5-NEXT:    [[TMP120:%.*]] = bitcast i8** [[TMP119]] to [5 x [10 x double]]**
7363 // CHECK5-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP120]], align 8
7364 // CHECK5-NEXT:    [[TMP121:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS28]], i64 0, i64 4
7365 // CHECK5-NEXT:    store i8* null, i8** [[TMP121]], align 8
7366 // CHECK5-NEXT:    [[TMP122:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS26]], i32 0, i32 5
7367 // CHECK5-NEXT:    [[TMP123:%.*]] = bitcast i8** [[TMP122]] to i64*
7368 // CHECK5-NEXT:    store i64 5, i64* [[TMP123]], align 8
7369 // CHECK5-NEXT:    [[TMP124:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS27]], i32 0, i32 5
7370 // CHECK5-NEXT:    [[TMP125:%.*]] = bitcast i8** [[TMP124]] to i64*
7371 // CHECK5-NEXT:    store i64 5, i64* [[TMP125]], align 8
7372 // CHECK5-NEXT:    [[TMP126:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS28]], i64 0, i64 5
7373 // CHECK5-NEXT:    store i8* null, i8** [[TMP126]], align 8
7374 // CHECK5-NEXT:    [[TMP127:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS26]], i32 0, i32 6
7375 // CHECK5-NEXT:    [[TMP128:%.*]] = bitcast i8** [[TMP127]] to i64*
7376 // CHECK5-NEXT:    store i64 [[TMP5]], i64* [[TMP128]], align 8
7377 // CHECK5-NEXT:    [[TMP129:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS27]], i32 0, i32 6
7378 // CHECK5-NEXT:    [[TMP130:%.*]] = bitcast i8** [[TMP129]] to i64*
7379 // CHECK5-NEXT:    store i64 [[TMP5]], i64* [[TMP130]], align 8
7380 // CHECK5-NEXT:    [[TMP131:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS28]], i64 0, i64 6
7381 // CHECK5-NEXT:    store i8* null, i8** [[TMP131]], align 8
7382 // CHECK5-NEXT:    [[TMP132:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS26]], i32 0, i32 7
7383 // CHECK5-NEXT:    [[TMP133:%.*]] = bitcast i8** [[TMP132]] to double**
7384 // CHECK5-NEXT:    store double* [[VLA1]], double** [[TMP133]], align 8
7385 // CHECK5-NEXT:    [[TMP134:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS27]], i32 0, i32 7
7386 // CHECK5-NEXT:    [[TMP135:%.*]] = bitcast i8** [[TMP134]] to double**
7387 // CHECK5-NEXT:    store double* [[VLA1]], double** [[TMP135]], align 8
7388 // CHECK5-NEXT:    [[TMP136:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7
7389 // CHECK5-NEXT:    store i64 [[TMP94]], i64* [[TMP136]], align 8
7390 // CHECK5-NEXT:    [[TMP137:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS28]], i64 0, i64 7
7391 // CHECK5-NEXT:    store i8* null, i8** [[TMP137]], align 8
7392 // CHECK5-NEXT:    [[TMP138:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS26]], i32 0, i32 8
7393 // CHECK5-NEXT:    [[TMP139:%.*]] = bitcast i8** [[TMP138]] to %struct.TT**
7394 // CHECK5-NEXT:    store %struct.TT* [[D]], %struct.TT** [[TMP139]], align 8
7395 // CHECK5-NEXT:    [[TMP140:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS27]], i32 0, i32 8
7396 // CHECK5-NEXT:    [[TMP141:%.*]] = bitcast i8** [[TMP140]] to %struct.TT**
7397 // CHECK5-NEXT:    store %struct.TT* [[D]], %struct.TT** [[TMP141]], align 8
7398 // CHECK5-NEXT:    [[TMP142:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS28]], i64 0, i64 8
7399 // CHECK5-NEXT:    store i8* null, i8** [[TMP142]], align 8
7400 // CHECK5-NEXT:    [[TMP143:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS26]], i32 0, i32 0
7401 // CHECK5-NEXT:    [[TMP144:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS27]], i32 0, i32 0
7402 // CHECK5-NEXT:    [[TMP145:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
7403 // CHECK5-NEXT:    call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10)
7404 // CHECK5-NEXT:    [[TMP146:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142.region_id, i32 9, i8** [[TMP143]], i8** [[TMP144]], i64* [[TMP145]], i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_maptypes.11, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1)
7405 // CHECK5-NEXT:    [[TMP147:%.*]] = icmp ne i32 [[TMP146]], 0
7406 // CHECK5-NEXT:    br i1 [[TMP147]], label [[OMP_OFFLOAD_FAILED30:%.*]], label [[OMP_OFFLOAD_CONT31:%.*]]
7407 // CHECK5:       omp_offload.failed30:
7408 // CHECK5-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i64 [[TMP90]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR4]]
7409 // CHECK5-NEXT:    br label [[OMP_OFFLOAD_CONT31]]
7410 // CHECK5:       omp_offload.cont31:
7411 // CHECK5-NEXT:    br label [[OMP_IF_END33:%.*]]
7412 // CHECK5:       omp_if.else32:
7413 // CHECK5-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i64 [[TMP90]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR4]]
7414 // CHECK5-NEXT:    br label [[OMP_IF_END33]]
7415 // CHECK5:       omp_if.end33:
7416 // CHECK5-NEXT:    [[TMP148:%.*]] = load i32, i32* [[A]], align 4
7417 // CHECK5-NEXT:    [[TMP149:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
7418 // CHECK5-NEXT:    call void @llvm.stackrestore(i8* [[TMP149]])
7419 // CHECK5-NEXT:    ret i32 [[TMP148]]
7420 //
7421 //
7422 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97
7423 // CHECK5-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] {
7424 // CHECK5-NEXT:  entry:
7425 // CHECK5-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
7426 // CHECK5-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
7427 // CHECK5-NEXT:    [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8
7428 // CHECK5-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
7429 // CHECK5-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]])
7430 // CHECK5-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
7431 // CHECK5-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
7432 // CHECK5-NEXT:    store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8
7433 // CHECK5-NEXT:    [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
7434 // CHECK5-NEXT:    [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
7435 // CHECK5-NEXT:    [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32*
7436 // CHECK5-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 4
7437 // CHECK5-NEXT:    [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 4
7438 // CHECK5-NEXT:    call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
7439 // CHECK5-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
7440 // CHECK5-NEXT:    [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
7441 // CHECK5-NEXT:    store i16 [[TMP3]], i16* [[CONV5]], align 2
7442 // CHECK5-NEXT:    [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
7443 // CHECK5-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]])
7444 // CHECK5-NEXT:    ret void
7445 //
7446 //
7447 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined.
7448 // CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR3:[0-9]+]] {
7449 // CHECK5-NEXT:  entry:
7450 // CHECK5-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
7451 // CHECK5-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
7452 // CHECK5-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
7453 // CHECK5-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
7454 // CHECK5-NEXT:    [[TMP:%.*]] = alloca i32, align 4
7455 // CHECK5-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
7456 // CHECK5-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
7457 // CHECK5-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
7458 // CHECK5-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
7459 // CHECK5-NEXT:    [[I:%.*]] = alloca i32, align 4
7460 // CHECK5-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
7461 // CHECK5-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
7462 // CHECK5-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
7463 // CHECK5-NEXT:    [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
7464 // CHECK5-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
7465 // CHECK5-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
7466 // CHECK5-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
7467 // CHECK5-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
7468 // CHECK5-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
7469 // CHECK5-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
7470 // CHECK5-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
7471 // CHECK5-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
7472 // CHECK5-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
7473 // CHECK5-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
7474 // CHECK5:       cond.true:
7475 // CHECK5-NEXT:    br label [[COND_END:%.*]]
7476 // CHECK5:       cond.false:
7477 // CHECK5-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
7478 // CHECK5-NEXT:    br label [[COND_END]]
7479 // CHECK5:       cond.end:
7480 // CHECK5-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
7481 // CHECK5-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
7482 // CHECK5-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
7483 // CHECK5-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
7484 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
7485 // CHECK5:       omp.inner.for.cond:
7486 // CHECK5-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
7487 // CHECK5-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !10
7488 // CHECK5-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
7489 // CHECK5-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
7490 // CHECK5:       omp.inner.for.body:
7491 // CHECK5-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
7492 // CHECK5-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
7493 // CHECK5-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
7494 // CHECK5-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10
7495 // CHECK5-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
7496 // CHECK5:       omp.body.continue:
7497 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
7498 // CHECK5:       omp.inner.for.inc:
7499 // CHECK5-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
7500 // CHECK5-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
7501 // CHECK5-NEXT:    store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
7502 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]
7503 // CHECK5:       omp.inner.for.end:
7504 // CHECK5-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
7505 // CHECK5:       omp.loop.exit:
7506 // CHECK5-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
7507 // CHECK5-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
7508 // CHECK5-NEXT:    [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0
7509 // CHECK5-NEXT:    br i1 [[TMP10]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
7510 // CHECK5:       .omp.final.then:
7511 // CHECK5-NEXT:    store i32 10, i32* [[I]], align 4
7512 // CHECK5-NEXT:    br label [[DOTOMP_FINAL_DONE]]
7513 // CHECK5:       .omp.final.done:
7514 // CHECK5-NEXT:    ret void
7515 //
7516 //
7517 // CHECK5-LABEL: define {{[^@]+}}@.omp_task_privates_map.
7518 // CHECK5-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], i16** noalias noundef [[TMP1:%.*]], [3 x i8*]** noalias noundef [[TMP2:%.*]], [3 x i8*]** noalias noundef [[TMP3:%.*]], [3 x i64]** noalias noundef [[TMP4:%.*]]) #[[ATTR5:[0-9]+]] {
7519 // CHECK5-NEXT:  entry:
7520 // CHECK5-NEXT:    [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 8
7521 // CHECK5-NEXT:    [[DOTADDR1:%.*]] = alloca i16**, align 8
7522 // CHECK5-NEXT:    [[DOTADDR2:%.*]] = alloca [3 x i8*]**, align 8
7523 // CHECK5-NEXT:    [[DOTADDR3:%.*]] = alloca [3 x i8*]**, align 8
7524 // CHECK5-NEXT:    [[DOTADDR4:%.*]] = alloca [3 x i64]**, align 8
7525 // CHECK5-NEXT:    store %struct..kmp_privates.t* [[TMP0]], %struct..kmp_privates.t** [[DOTADDR]], align 8
7526 // CHECK5-NEXT:    store i16** [[TMP1]], i16*** [[DOTADDR1]], align 8
7527 // CHECK5-NEXT:    store [3 x i8*]** [[TMP2]], [3 x i8*]*** [[DOTADDR2]], align 8
7528 // CHECK5-NEXT:    store [3 x i8*]** [[TMP3]], [3 x i8*]*** [[DOTADDR3]], align 8
7529 // CHECK5-NEXT:    store [3 x i64]** [[TMP4]], [3 x i64]*** [[DOTADDR4]], align 8
7530 // CHECK5-NEXT:    [[TMP5:%.*]] = load %struct..kmp_privates.t*, %struct..kmp_privates.t** [[DOTADDR]], align 8
7531 // CHECK5-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 0
7532 // CHECK5-NEXT:    [[TMP7:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR2]], align 8
7533 // CHECK5-NEXT:    store [3 x i8*]* [[TMP6]], [3 x i8*]** [[TMP7]], align 8
7534 // CHECK5-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 1
7535 // CHECK5-NEXT:    [[TMP9:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR3]], align 8
7536 // CHECK5-NEXT:    store [3 x i8*]* [[TMP8]], [3 x i8*]** [[TMP9]], align 8
7537 // CHECK5-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 2
7538 // CHECK5-NEXT:    [[TMP11:%.*]] = load [3 x i64]**, [3 x i64]*** [[DOTADDR4]], align 8
7539 // CHECK5-NEXT:    store [3 x i64]* [[TMP10]], [3 x i64]** [[TMP11]], align 8
7540 // CHECK5-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 3
7541 // CHECK5-NEXT:    [[TMP13:%.*]] = load i16**, i16*** [[DOTADDR1]], align 8
7542 // CHECK5-NEXT:    store i16* [[TMP12]], i16** [[TMP13]], align 8
7543 // CHECK5-NEXT:    ret void
7544 //
7545 //
7546 // CHECK5-LABEL: define {{[^@]+}}@.omp_task_entry.
7547 // CHECK5-SAME: (i32 noundef signext [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] {
7548 // CHECK5-NEXT:  entry:
7549 // CHECK5-NEXT:    [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
7550 // CHECK5-NEXT:    [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8
7551 // CHECK5-NEXT:    [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8
7552 // CHECK5-NEXT:    [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8
7553 // CHECK5-NEXT:    [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8
7554 // CHECK5-NEXT:    [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 8
7555 // CHECK5-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca i16*, align 8
7556 // CHECK5-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca [3 x i8*]*, align 8
7557 // CHECK5-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca [3 x i8*]*, align 8
7558 // CHECK5-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca [3 x i64]*, align 8
7559 // CHECK5-NEXT:    [[AA_CASTED_I:%.*]] = alloca i64, align 8
7560 // CHECK5-NEXT:    [[DOTCAPTURE_EXPR__CASTED_I:%.*]] = alloca i64, align 8
7561 // CHECK5-NEXT:    [[DOTCAPTURE_EXPR__CASTED5_I:%.*]] = alloca i64, align 8
7562 // CHECK5-NEXT:    [[DOTADDR:%.*]] = alloca i32, align 4
7563 // CHECK5-NEXT:    [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8
7564 // CHECK5-NEXT:    store i32 [[TMP0]], i32* [[DOTADDR]], align 4
7565 // CHECK5-NEXT:    store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8
7566 // CHECK5-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4
7567 // CHECK5-NEXT:    [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8
7568 // CHECK5-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
7569 // CHECK5-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
7570 // CHECK5-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0
7571 // CHECK5-NEXT:    [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8
7572 // CHECK5-NEXT:    [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon*
7573 // CHECK5-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1
7574 // CHECK5-NEXT:    [[TMP10:%.*]] = bitcast %struct..kmp_privates.t* [[TMP9]] to i8*
7575 // CHECK5-NEXT:    [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8*
7576 // CHECK5-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META17:![0-9]+]])
7577 // CHECK5-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]])
7578 // CHECK5-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META22:![0-9]+]])
7579 // CHECK5-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META24:![0-9]+]])
7580 // CHECK5-NEXT:    store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !26
7581 // CHECK5-NEXT:    store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !26
7582 // CHECK5-NEXT:    store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !26
7583 // CHECK5-NEXT:    store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* @.omp_task_privates_map. to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !26
7584 // CHECK5-NEXT:    store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !26
7585 // CHECK5-NEXT:    store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !26
7586 // CHECK5-NEXT:    [[TMP12:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !26
7587 // CHECK5-NEXT:    [[TMP13:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !26
7588 // CHECK5-NEXT:    [[TMP14:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !26
7589 // CHECK5-NEXT:    [[TMP15:%.*]] = bitcast void (i8*, ...)* [[TMP13]] to void (i8*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)*
7590 // CHECK5-NEXT:    call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR4]]
7591 // CHECK5-NEXT:    [[TMP16:%.*]] = load i16*, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !26
7592 // CHECK5-NEXT:    [[TMP17:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !26
7593 // CHECK5-NEXT:    [[TMP18:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 8, !noalias !26
7594 // CHECK5-NEXT:    [[TMP19:%.*]] = load [3 x i64]*, [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 8, !noalias !26
7595 // CHECK5-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP17]], i64 0, i64 0
7596 // CHECK5-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP18]], i64 0, i64 0
7597 // CHECK5-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[TMP19]], i64 0, i64 0
7598 // CHECK5-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP12]], i32 0, i32 1
7599 // CHECK5-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[TMP12]], i32 0, i32 2
7600 // CHECK5-NEXT:    [[TMP25:%.*]] = load i32, i32* [[TMP23]], align 4
7601 // CHECK5-NEXT:    call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) #[[ATTR4]]
7602 // CHECK5-NEXT:    [[TMP26:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 [[TMP25]], i32 1, i32 0, i8* null, i32 0, i8* null) #[[ATTR4]]
7603 // CHECK5-NEXT:    [[TMP27:%.*]] = icmp ne i32 [[TMP26]], 0
7604 // CHECK5-NEXT:    br i1 [[TMP27]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]]
7605 // CHECK5:       omp_offload.failed.i:
7606 // CHECK5-NEXT:    [[TMP28:%.*]] = load i16, i16* [[TMP16]], align 2
7607 // CHECK5-NEXT:    [[CONV_I:%.*]] = bitcast i64* [[AA_CASTED_I]] to i16*
7608 // CHECK5-NEXT:    store i16 [[TMP28]], i16* [[CONV_I]], align 2, !noalias !26
7609 // CHECK5-NEXT:    [[TMP29:%.*]] = load i64, i64* [[AA_CASTED_I]], align 8, !noalias !26
7610 // CHECK5-NEXT:    [[TMP30:%.*]] = load i32, i32* [[TMP23]], align 4
7611 // CHECK5-NEXT:    [[CONV4_I:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED_I]] to i32*
7612 // CHECK5-NEXT:    store i32 [[TMP30]], i32* [[CONV4_I]], align 4, !noalias !26
7613 // CHECK5-NEXT:    [[TMP31:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED_I]], align 8, !noalias !26
7614 // CHECK5-NEXT:    [[TMP32:%.*]] = load i32, i32* [[TMP24]], align 4
7615 // CHECK5-NEXT:    [[CONV6_I:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED5_I]] to i32*
7616 // CHECK5-NEXT:    store i32 [[TMP32]], i32* [[CONV6_I]], align 4, !noalias !26
7617 // CHECK5-NEXT:    [[TMP33:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED5_I]], align 8, !noalias !26
7618 // CHECK5-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97(i64 [[TMP29]], i64 [[TMP31]], i64 [[TMP33]]) #[[ATTR4]]
7619 // CHECK5-NEXT:    br label [[DOTOMP_OUTLINED__1_EXIT]]
7620 // CHECK5:       .omp_outlined..1.exit:
7621 // CHECK5-NEXT:    ret i32 0
7622 //
7623 //
7624 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l102
7625 // CHECK5-SAME: (i64 noundef [[A:%.*]]) #[[ATTR3]] {
7626 // CHECK5-NEXT:  entry:
7627 // CHECK5-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
7628 // CHECK5-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
7629 // CHECK5-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
7630 // CHECK5-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
7631 // CHECK5-NEXT:    [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
7632 // CHECK5-NEXT:    [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32*
7633 // CHECK5-NEXT:    store i32 [[TMP0]], i32* [[CONV1]], align 4
7634 // CHECK5-NEXT:    [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
7635 // CHECK5-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]])
7636 // CHECK5-NEXT:    ret void
7637 //
7638 //
7639 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..2
7640 // CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]]) #[[ATTR3]] {
7641 // CHECK5-NEXT:  entry:
7642 // CHECK5-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
7643 // CHECK5-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
7644 // CHECK5-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
7645 // CHECK5-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
7646 // CHECK5-NEXT:    [[TMP:%.*]] = alloca i32, align 4
7647 // CHECK5-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
7648 // CHECK5-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
7649 // CHECK5-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
7650 // CHECK5-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
7651 // CHECK5-NEXT:    [[A1:%.*]] = alloca i32, align 4
7652 // CHECK5-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
7653 // CHECK5-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
7654 // CHECK5-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
7655 // CHECK5-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
7656 // CHECK5-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
7657 // CHECK5-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
7658 // CHECK5-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
7659 // CHECK5-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
7660 // CHECK5-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
7661 // CHECK5-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
7662 // CHECK5-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
7663 // CHECK5-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
7664 // CHECK5-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
7665 // CHECK5-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
7666 // CHECK5:       cond.true:
7667 // CHECK5-NEXT:    br label [[COND_END:%.*]]
7668 // CHECK5:       cond.false:
7669 // CHECK5-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
7670 // CHECK5-NEXT:    br label [[COND_END]]
7671 // CHECK5:       cond.end:
7672 // CHECK5-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
7673 // CHECK5-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
7674 // CHECK5-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
7675 // CHECK5-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
7676 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
7677 // CHECK5:       omp.inner.for.cond:
7678 // CHECK5-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
7679 // CHECK5-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
7680 // CHECK5-NEXT:    [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
7681 // CHECK5-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
7682 // CHECK5:       omp.inner.for.body:
7683 // CHECK5-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
7684 // CHECK5-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
7685 // CHECK5-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
7686 // CHECK5-NEXT:    store i32 [[ADD]], i32* [[A1]], align 4, !nontemporal !27
7687 // CHECK5-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A1]], align 4, !nontemporal !27
7688 // CHECK5-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
7689 // CHECK5-NEXT:    store i32 [[ADD3]], i32* [[A1]], align 4, !nontemporal !27
7690 // CHECK5-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
7691 // CHECK5:       omp.body.continue:
7692 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
7693 // CHECK5:       omp.inner.for.inc:
7694 // CHECK5-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
7695 // CHECK5-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP9]], 1
7696 // CHECK5-NEXT:    store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4
7697 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]]
7698 // CHECK5:       omp.inner.for.end:
7699 // CHECK5-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
7700 // CHECK5:       omp.loop.exit:
7701 // CHECK5-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
7702 // CHECK5-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
7703 // CHECK5-NEXT:    [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0
7704 // CHECK5-NEXT:    br i1 [[TMP11]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
7705 // CHECK5:       .omp.final.then:
7706 // CHECK5-NEXT:    store i32 10, i32* [[CONV]], align 4
7707 // CHECK5-NEXT:    br label [[DOTOMP_FINAL_DONE]]
7708 // CHECK5:       .omp.final.done:
7709 // CHECK5-NEXT:    ret void
7710 //
7711 //
7712 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111
7713 // CHECK5-SAME: (i64 noundef [[AA:%.*]]) #[[ATTR2]] {
7714 // CHECK5-NEXT:  entry:
7715 // CHECK5-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
7716 // CHECK5-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
7717 // CHECK5-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
7718 // CHECK5-NEXT:    [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
7719 // CHECK5-NEXT:    [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
7720 // CHECK5-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
7721 // CHECK5-NEXT:    store i16 [[TMP0]], i16* [[CONV1]], align 2
7722 // CHECK5-NEXT:    [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
7723 // CHECK5-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP1]])
7724 // CHECK5-NEXT:    ret void
7725 //
7726 //
7727 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..3
7728 // CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR3]] {
7729 // CHECK5-NEXT:  entry:
7730 // CHECK5-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
7731 // CHECK5-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
7732 // CHECK5-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
7733 // CHECK5-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
7734 // CHECK5-NEXT:    [[TMP:%.*]] = alloca i32, align 4
7735 // CHECK5-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
7736 // CHECK5-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
7737 // CHECK5-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
7738 // CHECK5-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
7739 // CHECK5-NEXT:    [[I:%.*]] = alloca i32, align 4
7740 // CHECK5-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
7741 // CHECK5-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
7742 // CHECK5-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
7743 // CHECK5-NEXT:    [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
7744 // CHECK5-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
7745 // CHECK5-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
7746 // CHECK5-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
7747 // CHECK5-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
7748 // CHECK5-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
7749 // CHECK5-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
7750 // CHECK5-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
7751 // CHECK5-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
7752 // CHECK5-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
7753 // CHECK5-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
7754 // CHECK5:       cond.true:
7755 // CHECK5-NEXT:    br label [[COND_END:%.*]]
7756 // CHECK5:       cond.false:
7757 // CHECK5-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
7758 // CHECK5-NEXT:    br label [[COND_END]]
7759 // CHECK5:       cond.end:
7760 // CHECK5-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
7761 // CHECK5-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
7762 // CHECK5-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
7763 // CHECK5-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
7764 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
7765 // CHECK5:       omp.inner.for.cond:
7766 // CHECK5-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30
7767 // CHECK5-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !30
7768 // CHECK5-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
7769 // CHECK5-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
7770 // CHECK5:       omp.inner.for.body:
7771 // CHECK5-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30
7772 // CHECK5-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
7773 // CHECK5-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
7774 // CHECK5-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !30
7775 // CHECK5-NEXT:    [[TMP8:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !30
7776 // CHECK5-NEXT:    [[CONV2:%.*]] = sext i16 [[TMP8]] to i32
7777 // CHECK5-NEXT:    [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
7778 // CHECK5-NEXT:    [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
7779 // CHECK5-NEXT:    store i16 [[CONV4]], i16* [[CONV]], align 2, !llvm.access.group !30
7780 // CHECK5-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
7781 // CHECK5:       omp.body.continue:
7782 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
7783 // CHECK5:       omp.inner.for.inc:
7784 // CHECK5-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30
7785 // CHECK5-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP9]], 1
7786 // CHECK5-NEXT:    store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30
7787 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP31:![0-9]+]]
7788 // CHECK5:       omp.inner.for.end:
7789 // CHECK5-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
7790 // CHECK5:       omp.loop.exit:
7791 // CHECK5-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
7792 // CHECK5-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
7793 // CHECK5-NEXT:    [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0
7794 // CHECK5-NEXT:    br i1 [[TMP11]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
7795 // CHECK5:       .omp.final.then:
7796 // CHECK5-NEXT:    store i32 10, i32* [[I]], align 4
7797 // CHECK5-NEXT:    br label [[DOTOMP_FINAL_DONE]]
7798 // CHECK5:       .omp.final.done:
7799 // CHECK5-NEXT:    ret void
7800 //
7801 //
7802 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118
7803 // CHECK5-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] {
7804 // CHECK5-NEXT:  entry:
7805 // CHECK5-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
7806 // CHECK5-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
7807 // CHECK5-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
7808 // CHECK5-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
7809 // CHECK5-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
7810 // CHECK5-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
7811 // CHECK5-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
7812 // CHECK5-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
7813 // CHECK5-NEXT:    [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
7814 // CHECK5-NEXT:    [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
7815 // CHECK5-NEXT:    store i32 [[TMP0]], i32* [[CONV2]], align 4
7816 // CHECK5-NEXT:    [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
7817 // CHECK5-NEXT:    [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
7818 // CHECK5-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
7819 // CHECK5-NEXT:    store i16 [[TMP2]], i16* [[CONV3]], align 2
7820 // CHECK5-NEXT:    [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
7821 // CHECK5-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
7822 // CHECK5-NEXT:    ret void
7823 //
7824 //
7825 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..6
7826 // CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR3]] {
7827 // CHECK5-NEXT:  entry:
7828 // CHECK5-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
7829 // CHECK5-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
7830 // CHECK5-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
7831 // CHECK5-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
7832 // CHECK5-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
7833 // CHECK5-NEXT:    [[TMP:%.*]] = alloca i32, align 4
7834 // CHECK5-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
7835 // CHECK5-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
7836 // CHECK5-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
7837 // CHECK5-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
7838 // CHECK5-NEXT:    [[I:%.*]] = alloca i32, align 4
7839 // CHECK5-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
7840 // CHECK5-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
7841 // CHECK5-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
7842 // CHECK5-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
7843 // CHECK5-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
7844 // CHECK5-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
7845 // CHECK5-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
7846 // CHECK5-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
7847 // CHECK5-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
7848 // CHECK5-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
7849 // CHECK5-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
7850 // CHECK5-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
7851 // CHECK5-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
7852 // CHECK5-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
7853 // CHECK5-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
7854 // CHECK5-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
7855 // CHECK5:       cond.true:
7856 // CHECK5-NEXT:    br label [[COND_END:%.*]]
7857 // CHECK5:       cond.false:
7858 // CHECK5-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
7859 // CHECK5-NEXT:    br label [[COND_END]]
7860 // CHECK5:       cond.end:
7861 // CHECK5-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
7862 // CHECK5-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
7863 // CHECK5-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
7864 // CHECK5-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
7865 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
7866 // CHECK5:       omp.inner.for.cond:
7867 // CHECK5-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33
7868 // CHECK5-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !33
7869 // CHECK5-NEXT:    [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
7870 // CHECK5-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
7871 // CHECK5:       omp.inner.for.body:
7872 // CHECK5-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33
7873 // CHECK5-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
7874 // CHECK5-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
7875 // CHECK5-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !33
7876 // CHECK5-NEXT:    [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !33
7877 // CHECK5-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
7878 // CHECK5-NEXT:    store i32 [[ADD3]], i32* [[CONV]], align 4, !llvm.access.group !33
7879 // CHECK5-NEXT:    [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 2, !llvm.access.group !33
7880 // CHECK5-NEXT:    [[CONV4:%.*]] = sext i16 [[TMP9]] to i32
7881 // CHECK5-NEXT:    [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
7882 // CHECK5-NEXT:    [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
7883 // CHECK5-NEXT:    store i16 [[CONV6]], i16* [[CONV1]], align 2, !llvm.access.group !33
7884 // CHECK5-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
7885 // CHECK5:       omp.body.continue:
7886 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
7887 // CHECK5:       omp.inner.for.inc:
7888 // CHECK5-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33
7889 // CHECK5-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1
7890 // CHECK5-NEXT:    store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33
7891 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP34:![0-9]+]]
7892 // CHECK5:       omp.inner.for.end:
7893 // CHECK5-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
7894 // CHECK5:       omp.loop.exit:
7895 // CHECK5-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
7896 // CHECK5-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
7897 // CHECK5-NEXT:    [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
7898 // CHECK5-NEXT:    br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
7899 // CHECK5:       .omp.final.then:
7900 // CHECK5-NEXT:    store i32 10, i32* [[I]], align 4
7901 // CHECK5-NEXT:    br label [[DOTOMP_FINAL_DONE]]
7902 // CHECK5:       .omp.final.done:
7903 // CHECK5-NEXT:    ret void
7904 //
7905 //
7906 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142
7907 // CHECK5-SAME: (i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] {
7908 // CHECK5-NEXT:  entry:
7909 // CHECK5-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
7910 // CHECK5-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
7911 // CHECK5-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
7912 // CHECK5-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 8
7913 // CHECK5-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
7914 // CHECK5-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
7915 // CHECK5-NEXT:    [[VLA_ADDR4:%.*]] = alloca i64, align 8
7916 // CHECK5-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 8
7917 // CHECK5-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
7918 // CHECK5-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
7919 // CHECK5-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
7920 // CHECK5-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
7921 // CHECK5-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
7922 // CHECK5-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 8
7923 // CHECK5-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
7924 // CHECK5-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
7925 // CHECK5-NEXT:    store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
7926 // CHECK5-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 8
7927 // CHECK5-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
7928 // CHECK5-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
7929 // CHECK5-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
7930 // CHECK5-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
7931 // CHECK5-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
7932 // CHECK5-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
7933 // CHECK5-NEXT:    [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
7934 // CHECK5-NEXT:    [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
7935 // CHECK5-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
7936 // CHECK5-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
7937 // CHECK5-NEXT:    [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
7938 // CHECK5-NEXT:    [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
7939 // CHECK5-NEXT:    store i32 [[TMP8]], i32* [[CONV5]], align 4
7940 // CHECK5-NEXT:    [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
7941 // CHECK5-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]])
7942 // CHECK5-NEXT:    ret void
7943 //
7944 //
7945 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..9
7946 // CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR3]] {
7947 // CHECK5-NEXT:  entry:
7948 // CHECK5-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
7949 // CHECK5-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
7950 // CHECK5-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
7951 // CHECK5-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
7952 // CHECK5-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
7953 // CHECK5-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 8
7954 // CHECK5-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
7955 // CHECK5-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
7956 // CHECK5-NEXT:    [[VLA_ADDR4:%.*]] = alloca i64, align 8
7957 // CHECK5-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 8
7958 // CHECK5-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
7959 // CHECK5-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
7960 // CHECK5-NEXT:    [[TMP:%.*]] = alloca i32, align 4
7961 // CHECK5-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
7962 // CHECK5-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
7963 // CHECK5-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
7964 // CHECK5-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
7965 // CHECK5-NEXT:    [[I:%.*]] = alloca i32, align 4
7966 // CHECK5-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
7967 // CHECK5-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
7968 // CHECK5-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
7969 // CHECK5-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
7970 // CHECK5-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
7971 // CHECK5-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 8
7972 // CHECK5-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
7973 // CHECK5-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
7974 // CHECK5-NEXT:    store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
7975 // CHECK5-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 8
7976 // CHECK5-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
7977 // CHECK5-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
7978 // CHECK5-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
7979 // CHECK5-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
7980 // CHECK5-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
7981 // CHECK5-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
7982 // CHECK5-NEXT:    [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
7983 // CHECK5-NEXT:    [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
7984 // CHECK5-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
7985 // CHECK5-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
7986 // CHECK5-NEXT:    [[ARRAYDECAY:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 0
7987 // CHECK5-NEXT:    call void @llvm.assume(i1 true) [ "align"(float* [[ARRAYDECAY]], i64 16) ]
7988 // CHECK5-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
7989 // CHECK5-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
7990 // CHECK5-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
7991 // CHECK5-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
7992 // CHECK5-NEXT:    [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
7993 // CHECK5-NEXT:    [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4
7994 // CHECK5-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
7995 // CHECK5-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
7996 // CHECK5-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP10]], 9
7997 // CHECK5-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
7998 // CHECK5:       cond.true:
7999 // CHECK5-NEXT:    br label [[COND_END:%.*]]
8000 // CHECK5:       cond.false:
8001 // CHECK5-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
8002 // CHECK5-NEXT:    br label [[COND_END]]
8003 // CHECK5:       cond.end:
8004 // CHECK5-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ]
8005 // CHECK5-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
8006 // CHECK5-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
8007 // CHECK5-NEXT:    store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4
8008 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
8009 // CHECK5:       omp.inner.for.cond:
8010 // CHECK5-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36
8011 // CHECK5-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !36
8012 // CHECK5-NEXT:    [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
8013 // CHECK5-NEXT:    br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
8014 // CHECK5:       omp.inner.for.body:
8015 // CHECK5-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36
8016 // CHECK5-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1
8017 // CHECK5-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
8018 // CHECK5-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !36
8019 // CHECK5-NEXT:    [[TMP16:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !36
8020 // CHECK5-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP16]], 1
8021 // CHECK5-NEXT:    store i32 [[ADD6]], i32* [[CONV]], align 4, !llvm.access.group !36
8022 // CHECK5-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
8023 // CHECK5-NEXT:    [[TMP17:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !36
8024 // CHECK5-NEXT:    [[CONV7:%.*]] = fpext float [[TMP17]] to double
8025 // CHECK5-NEXT:    [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00
8026 // CHECK5-NEXT:    [[CONV9:%.*]] = fptrunc double [[ADD8]] to float
8027 // CHECK5-NEXT:    store float [[CONV9]], float* [[ARRAYIDX]], align 4, !llvm.access.group !36
8028 // CHECK5-NEXT:    [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3
8029 // CHECK5-NEXT:    [[TMP18:%.*]] = load float, float* [[ARRAYIDX10]], align 4, !llvm.access.group !36
8030 // CHECK5-NEXT:    [[CONV11:%.*]] = fpext float [[TMP18]] to double
8031 // CHECK5-NEXT:    [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00
8032 // CHECK5-NEXT:    [[CONV13:%.*]] = fptrunc double [[ADD12]] to float
8033 // CHECK5-NEXT:    store float [[CONV13]], float* [[ARRAYIDX10]], align 4, !llvm.access.group !36
8034 // CHECK5-NEXT:    [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1
8035 // CHECK5-NEXT:    [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX14]], i64 0, i64 2
8036 // CHECK5-NEXT:    [[TMP19:%.*]] = load double, double* [[ARRAYIDX15]], align 8, !llvm.access.group !36
8037 // CHECK5-NEXT:    [[ADD16:%.*]] = fadd double [[TMP19]], 1.000000e+00
8038 // CHECK5-NEXT:    store double [[ADD16]], double* [[ARRAYIDX15]], align 8, !llvm.access.group !36
8039 // CHECK5-NEXT:    [[TMP20:%.*]] = mul nsw i64 1, [[TMP5]]
8040 // CHECK5-NEXT:    [[ARRAYIDX17:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP20]]
8041 // CHECK5-NEXT:    [[ARRAYIDX18:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX17]], i64 3
8042 // CHECK5-NEXT:    [[TMP21:%.*]] = load double, double* [[ARRAYIDX18]], align 8, !llvm.access.group !36
8043 // CHECK5-NEXT:    [[ADD19:%.*]] = fadd double [[TMP21]], 1.000000e+00
8044 // CHECK5-NEXT:    store double [[ADD19]], double* [[ARRAYIDX18]], align 8, !llvm.access.group !36
8045 // CHECK5-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0
8046 // CHECK5-NEXT:    [[TMP22:%.*]] = load i64, i64* [[X]], align 8, !llvm.access.group !36
8047 // CHECK5-NEXT:    [[ADD20:%.*]] = add nsw i64 [[TMP22]], 1
8048 // CHECK5-NEXT:    store i64 [[ADD20]], i64* [[X]], align 8, !llvm.access.group !36
8049 // CHECK5-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1
8050 // CHECK5-NEXT:    [[TMP23:%.*]] = load i8, i8* [[Y]], align 8, !llvm.access.group !36
8051 // CHECK5-NEXT:    [[CONV21:%.*]] = sext i8 [[TMP23]] to i32
8052 // CHECK5-NEXT:    [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1
8053 // CHECK5-NEXT:    [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8
8054 // CHECK5-NEXT:    store i8 [[CONV23]], i8* [[Y]], align 8, !llvm.access.group !36
8055 // CHECK5-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
8056 // CHECK5:       omp.body.continue:
8057 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
8058 // CHECK5:       omp.inner.for.inc:
8059 // CHECK5-NEXT:    [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36
8060 // CHECK5-NEXT:    [[ADD24:%.*]] = add nsw i32 [[TMP24]], 1
8061 // CHECK5-NEXT:    store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36
8062 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP37:![0-9]+]]
8063 // CHECK5:       omp.inner.for.end:
8064 // CHECK5-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
8065 // CHECK5:       omp.loop.exit:
8066 // CHECK5-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]])
8067 // CHECK5-NEXT:    [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
8068 // CHECK5-NEXT:    [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
8069 // CHECK5-NEXT:    br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
8070 // CHECK5:       .omp.final.then:
8071 // CHECK5-NEXT:    store i32 10, i32* [[I]], align 4
8072 // CHECK5-NEXT:    br label [[DOTOMP_FINAL_DONE]]
8073 // CHECK5:       .omp.final.done:
8074 // CHECK5-NEXT:    ret void
8075 //
8076 //
8077 // CHECK5-LABEL: define {{[^@]+}}@_Z3bari
8078 // CHECK5-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {
8079 // CHECK5-NEXT:  entry:
8080 // CHECK5-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
8081 // CHECK5-NEXT:    [[A:%.*]] = alloca i32, align 4
8082 // CHECK5-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8
8083 // CHECK5-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
8084 // CHECK5-NEXT:    store i32 0, i32* [[A]], align 4
8085 // CHECK5-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
8086 // CHECK5-NEXT:    [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]])
8087 // CHECK5-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
8088 // CHECK5-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
8089 // CHECK5-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
8090 // CHECK5-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
8091 // CHECK5-NEXT:    [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP2]])
8092 // CHECK5-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
8093 // CHECK5-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
8094 // CHECK5-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
8095 // CHECK5-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
8096 // CHECK5-NEXT:    [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]])
8097 // CHECK5-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
8098 // CHECK5-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
8099 // CHECK5-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
8100 // CHECK5-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
8101 // CHECK5-NEXT:    [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]])
8102 // CHECK5-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
8103 // CHECK5-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
8104 // CHECK5-NEXT:    store i32 [[ADD6]], i32* [[A]], align 4
8105 // CHECK5-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
8106 // CHECK5-NEXT:    ret i32 [[TMP8]]
8107 //
8108 //
8109 // CHECK5-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
8110 // CHECK5-SAME: (%struct.S1* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 {
8111 // CHECK5-NEXT:  entry:
8112 // CHECK5-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
8113 // CHECK5-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
8114 // CHECK5-NEXT:    [[B:%.*]] = alloca i32, align 4
8115 // CHECK5-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 8
8116 // CHECK5-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
8117 // CHECK5-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
8118 // CHECK5-NEXT:    [[B_CASTED:%.*]] = alloca i64, align 8
8119 // CHECK5-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
8120 // CHECK5-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [6 x i8*], align 8
8121 // CHECK5-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [6 x i8*], align 8
8122 // CHECK5-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [6 x i8*], align 8
8123 // CHECK5-NEXT:    [[DOTOFFLOAD_SIZES:%.*]] = alloca [6 x i64], align 8
8124 // CHECK5-NEXT:    [[TMP:%.*]] = alloca i32, align 4
8125 // CHECK5-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
8126 // CHECK5-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
8127 // CHECK5-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
8128 // CHECK5-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
8129 // CHECK5-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
8130 // CHECK5-NEXT:    store i32 [[ADD]], i32* [[B]], align 4
8131 // CHECK5-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
8132 // CHECK5-NEXT:    [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
8133 // CHECK5-NEXT:    [[TMP3:%.*]] = call i8* @llvm.stacksave()
8134 // CHECK5-NEXT:    store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8
8135 // CHECK5-NEXT:    [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]
8136 // CHECK5-NEXT:    [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2
8137 // CHECK5-NEXT:    store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8
8138 // CHECK5-NEXT:    [[TMP5:%.*]] = load i32, i32* [[N_ADDR]], align 4
8139 // CHECK5-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 60
8140 // CHECK5-NEXT:    [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8
8141 // CHECK5-NEXT:    store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
8142 // CHECK5-NEXT:    [[TMP6:%.*]] = load i32, i32* [[B]], align 4
8143 // CHECK5-NEXT:    [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32*
8144 // CHECK5-NEXT:    store i32 [[TMP6]], i32* [[CONV]], align 4
8145 // CHECK5-NEXT:    [[TMP7:%.*]] = load i64, i64* [[B_CASTED]], align 8
8146 // CHECK5-NEXT:    [[TMP8:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
8147 // CHECK5-NEXT:    [[TOBOOL:%.*]] = trunc i8 [[TMP8]] to i1
8148 // CHECK5-NEXT:    [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
8149 // CHECK5-NEXT:    [[FROMBOOL3:%.*]] = zext i1 [[TOBOOL]] to i8
8150 // CHECK5-NEXT:    store i8 [[FROMBOOL3]], i8* [[CONV2]], align 1
8151 // CHECK5-NEXT:    [[TMP9:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
8152 // CHECK5-NEXT:    [[TMP10:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
8153 // CHECK5-NEXT:    [[TOBOOL4:%.*]] = trunc i8 [[TMP10]] to i1
8154 // CHECK5-NEXT:    br i1 [[TOBOOL4]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
8155 // CHECK5:       omp_if.then:
8156 // CHECK5-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
8157 // CHECK5-NEXT:    [[TMP11:%.*]] = mul nuw i64 2, [[TMP2]]
8158 // CHECK5-NEXT:    [[TMP12:%.*]] = mul nuw i64 [[TMP11]], 2
8159 // CHECK5-NEXT:    [[TMP13:%.*]] = bitcast [6 x i64]* [[DOTOFFLOAD_SIZES]] to i8*
8160 // CHECK5-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP13]], i8* align 8 bitcast ([6 x i64]* @.offload_sizes.13 to i8*), i64 48, i1 false)
8161 // CHECK5-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
8162 // CHECK5-NEXT:    [[TMP15:%.*]] = bitcast i8** [[TMP14]] to %struct.S1**
8163 // CHECK5-NEXT:    store %struct.S1* [[THIS1]], %struct.S1** [[TMP15]], align 8
8164 // CHECK5-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
8165 // CHECK5-NEXT:    [[TMP17:%.*]] = bitcast i8** [[TMP16]] to double**
8166 // CHECK5-NEXT:    store double* [[A]], double** [[TMP17]], align 8
8167 // CHECK5-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
8168 // CHECK5-NEXT:    store i8* null, i8** [[TMP18]], align 8
8169 // CHECK5-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
8170 // CHECK5-NEXT:    [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64*
8171 // CHECK5-NEXT:    store i64 [[TMP7]], i64* [[TMP20]], align 8
8172 // CHECK5-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
8173 // CHECK5-NEXT:    [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i64*
8174 // CHECK5-NEXT:    store i64 [[TMP7]], i64* [[TMP22]], align 8
8175 // CHECK5-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
8176 // CHECK5-NEXT:    store i8* null, i8** [[TMP23]], align 8
8177 // CHECK5-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
8178 // CHECK5-NEXT:    [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i64*
8179 // CHECK5-NEXT:    store i64 2, i64* [[TMP25]], align 8
8180 // CHECK5-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
8181 // CHECK5-NEXT:    [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64*
8182 // CHECK5-NEXT:    store i64 2, i64* [[TMP27]], align 8
8183 // CHECK5-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
8184 // CHECK5-NEXT:    store i8* null, i8** [[TMP28]], align 8
8185 // CHECK5-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
8186 // CHECK5-NEXT:    [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i64*
8187 // CHECK5-NEXT:    store i64 [[TMP2]], i64* [[TMP30]], align 8
8188 // CHECK5-NEXT:    [[TMP31:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
8189 // CHECK5-NEXT:    [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i64*
8190 // CHECK5-NEXT:    store i64 [[TMP2]], i64* [[TMP32]], align 8
8191 // CHECK5-NEXT:    [[TMP33:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
8192 // CHECK5-NEXT:    store i8* null, i8** [[TMP33]], align 8
8193 // CHECK5-NEXT:    [[TMP34:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
8194 // CHECK5-NEXT:    [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i16**
8195 // CHECK5-NEXT:    store i16* [[VLA]], i16** [[TMP35]], align 8
8196 // CHECK5-NEXT:    [[TMP36:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
8197 // CHECK5-NEXT:    [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i16**
8198 // CHECK5-NEXT:    store i16* [[VLA]], i16** [[TMP37]], align 8
8199 // CHECK5-NEXT:    [[TMP38:%.*]] = getelementptr inbounds [6 x i64], [6 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4
8200 // CHECK5-NEXT:    store i64 [[TMP12]], i64* [[TMP38]], align 8
8201 // CHECK5-NEXT:    [[TMP39:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4
8202 // CHECK5-NEXT:    store i8* null, i8** [[TMP39]], align 8
8203 // CHECK5-NEXT:    [[TMP40:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 5
8204 // CHECK5-NEXT:    [[TMP41:%.*]] = bitcast i8** [[TMP40]] to i64*
8205 // CHECK5-NEXT:    store i64 [[TMP9]], i64* [[TMP41]], align 8
8206 // CHECK5-NEXT:    [[TMP42:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 5
8207 // CHECK5-NEXT:    [[TMP43:%.*]] = bitcast i8** [[TMP42]] to i64*
8208 // CHECK5-NEXT:    store i64 [[TMP9]], i64* [[TMP43]], align 8
8209 // CHECK5-NEXT:    [[TMP44:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 5
8210 // CHECK5-NEXT:    store i8* null, i8** [[TMP44]], align 8
8211 // CHECK5-NEXT:    [[TMP45:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
8212 // CHECK5-NEXT:    [[TMP46:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
8213 // CHECK5-NEXT:    [[TMP47:%.*]] = getelementptr inbounds [6 x i64], [6 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
8214 // CHECK5-NEXT:    call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10)
8215 // CHECK5-NEXT:    [[TMP48:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215.region_id, i32 6, i8** [[TMP45]], i8** [[TMP46]], i64* [[TMP47]], i64* getelementptr inbounds ([6 x i64], [6 x i64]* @.offload_maptypes.14, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1)
8216 // CHECK5-NEXT:    [[TMP49:%.*]] = icmp ne i32 [[TMP48]], 0
8217 // CHECK5-NEXT:    br i1 [[TMP49]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
8218 // CHECK5:       omp_offload.failed:
8219 // CHECK5-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215(%struct.S1* [[THIS1]], i64 [[TMP7]], i64 2, i64 [[TMP2]], i16* [[VLA]], i64 [[TMP9]]) #[[ATTR4]]
8220 // CHECK5-NEXT:    br label [[OMP_OFFLOAD_CONT]]
8221 // CHECK5:       omp_offload.cont:
8222 // CHECK5-NEXT:    br label [[OMP_IF_END:%.*]]
8223 // CHECK5:       omp_if.else:
8224 // CHECK5-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215(%struct.S1* [[THIS1]], i64 [[TMP7]], i64 2, i64 [[TMP2]], i16* [[VLA]], i64 [[TMP9]]) #[[ATTR4]]
8225 // CHECK5-NEXT:    br label [[OMP_IF_END]]
8226 // CHECK5:       omp_if.end:
8227 // CHECK5-NEXT:    [[TMP50:%.*]] = mul nsw i64 1, [[TMP2]]
8228 // CHECK5-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP50]]
8229 // CHECK5-NEXT:    [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
8230 // CHECK5-NEXT:    [[TMP51:%.*]] = load i16, i16* [[ARRAYIDX5]], align 2
8231 // CHECK5-NEXT:    [[CONV6:%.*]] = sext i16 [[TMP51]] to i32
8232 // CHECK5-NEXT:    [[TMP52:%.*]] = load i32, i32* [[B]], align 4
8233 // CHECK5-NEXT:    [[ADD7:%.*]] = add nsw i32 [[CONV6]], [[TMP52]]
8234 // CHECK5-NEXT:    [[TMP53:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
8235 // CHECK5-NEXT:    call void @llvm.stackrestore(i8* [[TMP53]])
8236 // CHECK5-NEXT:    ret i32 [[ADD7]]
8237 //
8238 //
8239 // CHECK5-LABEL: define {{[^@]+}}@_ZL7fstatici
8240 // CHECK5-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {
8241 // CHECK5-NEXT:  entry:
8242 // CHECK5-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
8243 // CHECK5-NEXT:    [[A:%.*]] = alloca i32, align 4
8244 // CHECK5-NEXT:    [[AA:%.*]] = alloca i16, align 2
8245 // CHECK5-NEXT:    [[AAA:%.*]] = alloca i8, align 1
8246 // CHECK5-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
8247 // CHECK5-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
8248 // CHECK5-NEXT:    [[N_CASTED:%.*]] = alloca i64, align 8
8249 // CHECK5-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
8250 // CHECK5-NEXT:    [[AAA_CASTED:%.*]] = alloca i64, align 8
8251 // CHECK5-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8
8252 // CHECK5-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8
8253 // CHECK5-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8
8254 // CHECK5-NEXT:    [[TMP:%.*]] = alloca i32, align 4
8255 // CHECK5-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
8256 // CHECK5-NEXT:    [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4
8257 // CHECK5-NEXT:    [[DOTCAPTURE_EXPR_5:%.*]] = alloca i32, align 4
8258 // CHECK5-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
8259 // CHECK5-NEXT:    store i32 0, i32* [[A]], align 4
8260 // CHECK5-NEXT:    store i16 0, i16* [[AA]], align 2
8261 // CHECK5-NEXT:    store i8 0, i8* [[AAA]], align 1
8262 // CHECK5-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
8263 // CHECK5-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32*
8264 // CHECK5-NEXT:    store i32 [[TMP0]], i32* [[CONV]], align 4
8265 // CHECK5-NEXT:    [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
8266 // CHECK5-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
8267 // CHECK5-NEXT:    [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32*
8268 // CHECK5-NEXT:    store i32 [[TMP2]], i32* [[CONV1]], align 4
8269 // CHECK5-NEXT:    [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8
8270 // CHECK5-NEXT:    [[TMP4:%.*]] = load i16, i16* [[AA]], align 2
8271 // CHECK5-NEXT:    [[CONV2:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
8272 // CHECK5-NEXT:    store i16 [[TMP4]], i16* [[CONV2]], align 2
8273 // CHECK5-NEXT:    [[TMP5:%.*]] = load i64, i64* [[AA_CASTED]], align 8
8274 // CHECK5-NEXT:    [[TMP6:%.*]] = load i8, i8* [[AAA]], align 1
8275 // CHECK5-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
8276 // CHECK5-NEXT:    store i8 [[TMP6]], i8* [[CONV3]], align 1
8277 // CHECK5-NEXT:    [[TMP7:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
8278 // CHECK5-NEXT:    [[TMP8:%.*]] = load i32, i32* [[N_ADDR]], align 4
8279 // CHECK5-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP8]], 50
8280 // CHECK5-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
8281 // CHECK5:       omp_if.then:
8282 // CHECK5-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
8283 // CHECK5-NEXT:    [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64*
8284 // CHECK5-NEXT:    store i64 [[TMP1]], i64* [[TMP10]], align 8
8285 // CHECK5-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
8286 // CHECK5-NEXT:    [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64*
8287 // CHECK5-NEXT:    store i64 [[TMP1]], i64* [[TMP12]], align 8
8288 // CHECK5-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
8289 // CHECK5-NEXT:    store i8* null, i8** [[TMP13]], align 8
8290 // CHECK5-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
8291 // CHECK5-NEXT:    [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64*
8292 // CHECK5-NEXT:    store i64 [[TMP3]], i64* [[TMP15]], align 8
8293 // CHECK5-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
8294 // CHECK5-NEXT:    [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64*
8295 // CHECK5-NEXT:    store i64 [[TMP3]], i64* [[TMP17]], align 8
8296 // CHECK5-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
8297 // CHECK5-NEXT:    store i8* null, i8** [[TMP18]], align 8
8298 // CHECK5-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
8299 // CHECK5-NEXT:    [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64*
8300 // CHECK5-NEXT:    store i64 [[TMP5]], i64* [[TMP20]], align 8
8301 // CHECK5-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
8302 // CHECK5-NEXT:    [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i64*
8303 // CHECK5-NEXT:    store i64 [[TMP5]], i64* [[TMP22]], align 8
8304 // CHECK5-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
8305 // CHECK5-NEXT:    store i8* null, i8** [[TMP23]], align 8
8306 // CHECK5-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
8307 // CHECK5-NEXT:    [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i64*
8308 // CHECK5-NEXT:    store i64 [[TMP7]], i64* [[TMP25]], align 8
8309 // CHECK5-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
8310 // CHECK5-NEXT:    [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64*
8311 // CHECK5-NEXT:    store i64 [[TMP7]], i64* [[TMP27]], align 8
8312 // CHECK5-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
8313 // CHECK5-NEXT:    store i8* null, i8** [[TMP28]], align 8
8314 // CHECK5-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
8315 // CHECK5-NEXT:    [[TMP30:%.*]] = bitcast i8** [[TMP29]] to [10 x i32]**
8316 // CHECK5-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP30]], align 8
8317 // CHECK5-NEXT:    [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
8318 // CHECK5-NEXT:    [[TMP32:%.*]] = bitcast i8** [[TMP31]] to [10 x i32]**
8319 // CHECK5-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP32]], align 8
8320 // CHECK5-NEXT:    [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4
8321 // CHECK5-NEXT:    store i8* null, i8** [[TMP33]], align 8
8322 // CHECK5-NEXT:    [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
8323 // CHECK5-NEXT:    [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
8324 // CHECK5-NEXT:    [[TMP36:%.*]] = load i32, i32* [[A]], align 4
8325 // CHECK5-NEXT:    store i32 [[TMP36]], i32* [[DOTCAPTURE_EXPR_]], align 4
8326 // CHECK5-NEXT:    [[TMP37:%.*]] = load i32, i32* [[N_ADDR]], align 4
8327 // CHECK5-NEXT:    store i32 [[TMP37]], i32* [[DOTCAPTURE_EXPR_4]], align 4
8328 // CHECK5-NEXT:    [[TMP38:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4
8329 // CHECK5-NEXT:    [[TMP39:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
8330 // CHECK5-NEXT:    [[SUB:%.*]] = sub i32 [[TMP38]], [[TMP39]]
8331 // CHECK5-NEXT:    [[SUB6:%.*]] = sub i32 [[SUB]], 1
8332 // CHECK5-NEXT:    [[ADD:%.*]] = add i32 [[SUB6]], 1
8333 // CHECK5-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], 1
8334 // CHECK5-NEXT:    [[SUB7:%.*]] = sub i32 [[DIV]], 1
8335 // CHECK5-NEXT:    store i32 [[SUB7]], i32* [[DOTCAPTURE_EXPR_5]], align 4
8336 // CHECK5-NEXT:    [[TMP40:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4
8337 // CHECK5-NEXT:    [[ADD8:%.*]] = add i32 [[TMP40]], 1
8338 // CHECK5-NEXT:    [[TMP41:%.*]] = zext i32 [[ADD8]] to i64
8339 // CHECK5-NEXT:    call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 [[TMP41]])
8340 // CHECK5-NEXT:    [[TMP42:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197.region_id, i32 5, i8** [[TMP34]], i8** [[TMP35]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes.16, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.17, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1)
8341 // CHECK5-NEXT:    [[TMP43:%.*]] = icmp ne i32 [[TMP42]], 0
8342 // CHECK5-NEXT:    br i1 [[TMP43]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
8343 // CHECK5:       omp_offload.failed:
8344 // CHECK5-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], i64 [[TMP7]], [10 x i32]* [[B]]) #[[ATTR4]]
8345 // CHECK5-NEXT:    br label [[OMP_OFFLOAD_CONT]]
8346 // CHECK5:       omp_offload.cont:
8347 // CHECK5-NEXT:    br label [[OMP_IF_END:%.*]]
8348 // CHECK5:       omp_if.else:
8349 // CHECK5-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], i64 [[TMP7]], [10 x i32]* [[B]]) #[[ATTR4]]
8350 // CHECK5-NEXT:    br label [[OMP_IF_END]]
8351 // CHECK5:       omp_if.end:
8352 // CHECK5-NEXT:    [[TMP44:%.*]] = load i32, i32* [[A]], align 4
8353 // CHECK5-NEXT:    ret i32 [[TMP44]]
8354 //
8355 //
8356 // CHECK5-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
8357 // CHECK5-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat {
8358 // CHECK5-NEXT:  entry:
8359 // CHECK5-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
8360 // CHECK5-NEXT:    [[A:%.*]] = alloca i32, align 4
8361 // CHECK5-NEXT:    [[AA:%.*]] = alloca i16, align 2
8362 // CHECK5-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
8363 // CHECK5-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
8364 // CHECK5-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
8365 // CHECK5-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8
8366 // CHECK5-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8
8367 // CHECK5-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8
8368 // CHECK5-NEXT:    [[TMP:%.*]] = alloca i32, align 4
8369 // CHECK5-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
8370 // CHECK5-NEXT:    store i32 0, i32* [[A]], align 4
8371 // CHECK5-NEXT:    store i16 0, i16* [[AA]], align 2
8372 // CHECK5-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
8373 // CHECK5-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32*
8374 // CHECK5-NEXT:    store i32 [[TMP0]], i32* [[CONV]], align 4
8375 // CHECK5-NEXT:    [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
8376 // CHECK5-NEXT:    [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
8377 // CHECK5-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
8378 // CHECK5-NEXT:    store i16 [[TMP2]], i16* [[CONV1]], align 2
8379 // CHECK5-NEXT:    [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
8380 // CHECK5-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
8381 // CHECK5-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40
8382 // CHECK5-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
8383 // CHECK5:       omp_if.then:
8384 // CHECK5-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
8385 // CHECK5-NEXT:    [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64*
8386 // CHECK5-NEXT:    store i64 [[TMP1]], i64* [[TMP6]], align 8
8387 // CHECK5-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
8388 // CHECK5-NEXT:    [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64*
8389 // CHECK5-NEXT:    store i64 [[TMP1]], i64* [[TMP8]], align 8
8390 // CHECK5-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
8391 // CHECK5-NEXT:    store i8* null, i8** [[TMP9]], align 8
8392 // CHECK5-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
8393 // CHECK5-NEXT:    [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i64*
8394 // CHECK5-NEXT:    store i64 [[TMP3]], i64* [[TMP11]], align 8
8395 // CHECK5-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
8396 // CHECK5-NEXT:    [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64*
8397 // CHECK5-NEXT:    store i64 [[TMP3]], i64* [[TMP13]], align 8
8398 // CHECK5-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
8399 // CHECK5-NEXT:    store i8* null, i8** [[TMP14]], align 8
8400 // CHECK5-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
8401 // CHECK5-NEXT:    [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]**
8402 // CHECK5-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 8
8403 // CHECK5-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
8404 // CHECK5-NEXT:    [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]**
8405 // CHECK5-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 8
8406 // CHECK5-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
8407 // CHECK5-NEXT:    store i8* null, i8** [[TMP19]], align 8
8408 // CHECK5-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
8409 // CHECK5-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
8410 // CHECK5-NEXT:    call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10)
8411 // CHECK5-NEXT:    [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.19, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.20, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1)
8412 // CHECK5-NEXT:    [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0
8413 // CHECK5-NEXT:    br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
8414 // CHECK5:       omp_offload.failed:
8415 // CHECK5-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]]
8416 // CHECK5-NEXT:    br label [[OMP_OFFLOAD_CONT]]
8417 // CHECK5:       omp_offload.cont:
8418 // CHECK5-NEXT:    br label [[OMP_IF_END:%.*]]
8419 // CHECK5:       omp_if.else:
8420 // CHECK5-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]]
8421 // CHECK5-NEXT:    br label [[OMP_IF_END]]
8422 // CHECK5:       omp_if.end:
8423 // CHECK5-NEXT:    [[TMP24:%.*]] = load i32, i32* [[A]], align 4
8424 // CHECK5-NEXT:    ret i32 [[TMP24]]
8425 //
8426 //
8427 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215
8428 // CHECK5-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] {
8429 // CHECK5-NEXT:  entry:
8430 // CHECK5-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
8431 // CHECK5-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
8432 // CHECK5-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
8433 // CHECK5-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
8434 // CHECK5-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 8
8435 // CHECK5-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
8436 // CHECK5-NEXT:    [[B_CASTED:%.*]] = alloca i64, align 8
8437 // CHECK5-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
8438 // CHECK5-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
8439 // CHECK5-NEXT:    store i64 [[B]], i64* [[B_ADDR]], align 8
8440 // CHECK5-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
8441 // CHECK5-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
8442 // CHECK5-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 8
8443 // CHECK5-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
8444 // CHECK5-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
8445 // CHECK5-NEXT:    [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
8446 // CHECK5-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
8447 // CHECK5-NEXT:    [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
8448 // CHECK5-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
8449 // CHECK5-NEXT:    [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
8450 // CHECK5-NEXT:    [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
8451 // CHECK5-NEXT:    [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i32*
8452 // CHECK5-NEXT:    store i32 [[TMP4]], i32* [[CONV4]], align 4
8453 // CHECK5-NEXT:    [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
8454 // CHECK5-NEXT:    [[TMP6:%.*]] = load i8, i8* [[CONV3]], align 1
8455 // CHECK5-NEXT:    [[TOBOOL:%.*]] = trunc i8 [[TMP6]] to i1
8456 // CHECK5-NEXT:    [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
8457 // CHECK5-NEXT:    [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
8458 // CHECK5-NEXT:    store i8 [[FROMBOOL]], i8* [[CONV5]], align 1
8459 // CHECK5-NEXT:    [[TMP7:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
8460 // CHECK5-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*, i64)* @.omp_outlined..12 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]], i64 [[TMP7]])
8461 // CHECK5-NEXT:    ret void
8462 //
8463 //
8464 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..12
8465 // CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] {
8466 // CHECK5-NEXT:  entry:
8467 // CHECK5-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
8468 // CHECK5-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
8469 // CHECK5-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
8470 // CHECK5-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
8471 // CHECK5-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
8472 // CHECK5-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
8473 // CHECK5-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 8
8474 // CHECK5-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
8475 // CHECK5-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
8476 // CHECK5-NEXT:    [[TMP:%.*]] = alloca i32, align 4
8477 // CHECK5-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
8478 // CHECK5-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
8479 // CHECK5-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
8480 // CHECK5-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
8481 // CHECK5-NEXT:    [[I:%.*]] = alloca i32, align 4
8482 // CHECK5-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
8483 // CHECK5-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
8484 // CHECK5-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
8485 // CHECK5-NEXT:    store i64 [[B]], i64* [[B_ADDR]], align 8
8486 // CHECK5-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
8487 // CHECK5-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
8488 // CHECK5-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 8
8489 // CHECK5-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
8490 // CHECK5-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
8491 // CHECK5-NEXT:    [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
8492 // CHECK5-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
8493 // CHECK5-NEXT:    [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
8494 // CHECK5-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
8495 // CHECK5-NEXT:    [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
8496 // CHECK5-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
8497 // CHECK5-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
8498 // CHECK5-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
8499 // CHECK5-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
8500 // CHECK5-NEXT:    [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
8501 // CHECK5-NEXT:    [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
8502 // CHECK5-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
8503 // CHECK5-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
8504 // CHECK5-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 9
8505 // CHECK5-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
8506 // CHECK5:       cond.true:
8507 // CHECK5-NEXT:    br label [[COND_END:%.*]]
8508 // CHECK5:       cond.false:
8509 // CHECK5-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
8510 // CHECK5-NEXT:    br label [[COND_END]]
8511 // CHECK5:       cond.end:
8512 // CHECK5-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
8513 // CHECK5-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
8514 // CHECK5-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
8515 // CHECK5-NEXT:    store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
8516 // CHECK5-NEXT:    [[TMP9:%.*]] = load i8, i8* [[CONV3]], align 1
8517 // CHECK5-NEXT:    [[TOBOOL:%.*]] = trunc i8 [[TMP9]] to i1
8518 // CHECK5-NEXT:    br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
8519 // CHECK5:       omp_if.then:
8520 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
8521 // CHECK5:       omp.inner.for.cond:
8522 // CHECK5-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39
8523 // CHECK5-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !39
8524 // CHECK5-NEXT:    [[CMP4:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]
8525 // CHECK5-NEXT:    br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
8526 // CHECK5:       omp.inner.for.body:
8527 // CHECK5-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39
8528 // CHECK5-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1
8529 // CHECK5-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
8530 // CHECK5-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !39
8531 // CHECK5-NEXT:    [[TMP13:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !39
8532 // CHECK5-NEXT:    [[CONV5:%.*]] = sitofp i32 [[TMP13]] to double
8533 // CHECK5-NEXT:    [[ADD6:%.*]] = fadd double [[CONV5]], 1.500000e+00
8534 // CHECK5-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
8535 // CHECK5-NEXT:    store double [[ADD6]], double* [[A]], align 8, !llvm.access.group !39
8536 // CHECK5-NEXT:    [[A7:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
8537 // CHECK5-NEXT:    [[TMP14:%.*]] = load double, double* [[A7]], align 8, !llvm.access.group !39
8538 // CHECK5-NEXT:    [[INC:%.*]] = fadd double [[TMP14]], 1.000000e+00
8539 // CHECK5-NEXT:    store double [[INC]], double* [[A7]], align 8, !llvm.access.group !39
8540 // CHECK5-NEXT:    [[CONV8:%.*]] = fptosi double [[INC]] to i16
8541 // CHECK5-NEXT:    [[TMP15:%.*]] = mul nsw i64 1, [[TMP2]]
8542 // CHECK5-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP15]]
8543 // CHECK5-NEXT:    [[ARRAYIDX9:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
8544 // CHECK5-NEXT:    store i16 [[CONV8]], i16* [[ARRAYIDX9]], align 2, !llvm.access.group !39
8545 // CHECK5-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
8546 // CHECK5:       omp.body.continue:
8547 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
8548 // CHECK5:       omp.inner.for.inc:
8549 // CHECK5-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39
8550 // CHECK5-NEXT:    [[ADD10:%.*]] = add nsw i32 [[TMP16]], 1
8551 // CHECK5-NEXT:    store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39
8552 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP40:![0-9]+]]
8553 // CHECK5:       omp.inner.for.end:
8554 // CHECK5-NEXT:    br label [[OMP_IF_END:%.*]]
8555 // CHECK5:       omp_if.else:
8556 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND11:%.*]]
8557 // CHECK5:       omp.inner.for.cond11:
8558 // CHECK5-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
8559 // CHECK5-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
8560 // CHECK5-NEXT:    [[CMP12:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]]
8561 // CHECK5-NEXT:    br i1 [[CMP12]], label [[OMP_INNER_FOR_BODY13:%.*]], label [[OMP_INNER_FOR_END27:%.*]]
8562 // CHECK5:       omp.inner.for.body13:
8563 // CHECK5-NEXT:    [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
8564 // CHECK5-NEXT:    [[MUL14:%.*]] = mul nsw i32 [[TMP19]], 1
8565 // CHECK5-NEXT:    [[ADD15:%.*]] = add nsw i32 0, [[MUL14]]
8566 // CHECK5-NEXT:    store i32 [[ADD15]], i32* [[I]], align 4
8567 // CHECK5-NEXT:    [[TMP20:%.*]] = load i32, i32* [[CONV]], align 4
8568 // CHECK5-NEXT:    [[CONV16:%.*]] = sitofp i32 [[TMP20]] to double
8569 // CHECK5-NEXT:    [[ADD17:%.*]] = fadd double [[CONV16]], 1.500000e+00
8570 // CHECK5-NEXT:    [[A18:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
8571 // CHECK5-NEXT:    store double [[ADD17]], double* [[A18]], align 8
8572 // CHECK5-NEXT:    [[A19:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
8573 // CHECK5-NEXT:    [[TMP21:%.*]] = load double, double* [[A19]], align 8
8574 // CHECK5-NEXT:    [[INC20:%.*]] = fadd double [[TMP21]], 1.000000e+00
8575 // CHECK5-NEXT:    store double [[INC20]], double* [[A19]], align 8
8576 // CHECK5-NEXT:    [[CONV21:%.*]] = fptosi double [[INC20]] to i16
8577 // CHECK5-NEXT:    [[TMP22:%.*]] = mul nsw i64 1, [[TMP2]]
8578 // CHECK5-NEXT:    [[ARRAYIDX22:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP22]]
8579 // CHECK5-NEXT:    [[ARRAYIDX23:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX22]], i64 1
8580 // CHECK5-NEXT:    store i16 [[CONV21]], i16* [[ARRAYIDX23]], align 2
8581 // CHECK5-NEXT:    br label [[OMP_BODY_CONTINUE24:%.*]]
8582 // CHECK5:       omp.body.continue24:
8583 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_INC25:%.*]]
8584 // CHECK5:       omp.inner.for.inc25:
8585 // CHECK5-NEXT:    [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
8586 // CHECK5-NEXT:    [[ADD26:%.*]] = add nsw i32 [[TMP23]], 1
8587 // CHECK5-NEXT:    store i32 [[ADD26]], i32* [[DOTOMP_IV]], align 4
8588 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND11]], !llvm.loop [[LOOP42:![0-9]+]]
8589 // CHECK5:       omp.inner.for.end27:
8590 // CHECK5-NEXT:    br label [[OMP_IF_END]]
8591 // CHECK5:       omp_if.end:
8592 // CHECK5-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
8593 // CHECK5:       omp.loop.exit:
8594 // CHECK5-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
8595 // CHECK5-NEXT:    [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
8596 // CHECK5-NEXT:    [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0
8597 // CHECK5-NEXT:    br i1 [[TMP25]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
8598 // CHECK5:       .omp.final.then:
8599 // CHECK5-NEXT:    store i32 10, i32* [[I]], align 4
8600 // CHECK5-NEXT:    br label [[DOTOMP_FINAL_DONE]]
8601 // CHECK5:       .omp.final.done:
8602 // CHECK5-NEXT:    ret void
8603 //
8604 //
8605 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197
8606 // CHECK5-SAME: (i64 noundef [[A:%.*]], i64 noundef [[N:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
8607 // CHECK5-NEXT:  entry:
8608 // CHECK5-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
8609 // CHECK5-NEXT:    [[N_ADDR:%.*]] = alloca i64, align 8
8610 // CHECK5-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
8611 // CHECK5-NEXT:    [[AAA_ADDR:%.*]] = alloca i64, align 8
8612 // CHECK5-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
8613 // CHECK5-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
8614 // CHECK5-NEXT:    [[N_CASTED:%.*]] = alloca i64, align 8
8615 // CHECK5-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
8616 // CHECK5-NEXT:    [[AAA_CASTED:%.*]] = alloca i64, align 8
8617 // CHECK5-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
8618 // CHECK5-NEXT:    store i64 [[N]], i64* [[N_ADDR]], align 8
8619 // CHECK5-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
8620 // CHECK5-NEXT:    store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
8621 // CHECK5-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
8622 // CHECK5-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
8623 // CHECK5-NEXT:    [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32*
8624 // CHECK5-NEXT:    [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
8625 // CHECK5-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
8626 // CHECK5-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
8627 // CHECK5-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
8628 // CHECK5-NEXT:    [[CONV4:%.*]] = bitcast i64* [[A_CASTED]] to i32*
8629 // CHECK5-NEXT:    store i32 [[TMP1]], i32* [[CONV4]], align 4
8630 // CHECK5-NEXT:    [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
8631 // CHECK5-NEXT:    [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 4
8632 // CHECK5-NEXT:    [[CONV5:%.*]] = bitcast i64* [[N_CASTED]] to i32*
8633 // CHECK5-NEXT:    store i32 [[TMP3]], i32* [[CONV5]], align 4
8634 // CHECK5-NEXT:    [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8
8635 // CHECK5-NEXT:    [[TMP5:%.*]] = load i16, i16* [[CONV2]], align 2
8636 // CHECK5-NEXT:    [[CONV6:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
8637 // CHECK5-NEXT:    store i16 [[TMP5]], i16* [[CONV6]], align 2
8638 // CHECK5-NEXT:    [[TMP6:%.*]] = load i64, i64* [[AA_CASTED]], align 8
8639 // CHECK5-NEXT:    [[TMP7:%.*]] = load i8, i8* [[CONV3]], align 1
8640 // CHECK5-NEXT:    [[CONV7:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
8641 // CHECK5-NEXT:    store i8 [[TMP7]], i8* [[CONV7]], align 1
8642 // CHECK5-NEXT:    [[TMP8:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
8643 // CHECK5-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, [10 x i32]*)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]], [10 x i32]* [[TMP0]])
8644 // CHECK5-NEXT:    ret void
8645 //
8646 //
8647 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..15
8648 // CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[N:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] {
8649 // CHECK5-NEXT:  entry:
8650 // CHECK5-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
8651 // CHECK5-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
8652 // CHECK5-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
8653 // CHECK5-NEXT:    [[N_ADDR:%.*]] = alloca i64, align 8
8654 // CHECK5-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
8655 // CHECK5-NEXT:    [[AAA_ADDR:%.*]] = alloca i64, align 8
8656 // CHECK5-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
8657 // CHECK5-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
8658 // CHECK5-NEXT:    [[TMP:%.*]] = alloca i32, align 4
8659 // CHECK5-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
8660 // CHECK5-NEXT:    [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4
8661 // CHECK5-NEXT:    [[DOTCAPTURE_EXPR_5:%.*]] = alloca i32, align 4
8662 // CHECK5-NEXT:    [[I:%.*]] = alloca i32, align 4
8663 // CHECK5-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
8664 // CHECK5-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
8665 // CHECK5-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
8666 // CHECK5-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
8667 // CHECK5-NEXT:    [[I8:%.*]] = alloca i32, align 4
8668 // CHECK5-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
8669 // CHECK5-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
8670 // CHECK5-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
8671 // CHECK5-NEXT:    store i64 [[N]], i64* [[N_ADDR]], align 8
8672 // CHECK5-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
8673 // CHECK5-NEXT:    store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
8674 // CHECK5-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
8675 // CHECK5-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
8676 // CHECK5-NEXT:    [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32*
8677 // CHECK5-NEXT:    [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
8678 // CHECK5-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
8679 // CHECK5-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
8680 // CHECK5-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
8681 // CHECK5-NEXT:    store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
8682 // CHECK5-NEXT:    [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4
8683 // CHECK5-NEXT:    store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_4]], align 4
8684 // CHECK5-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4
8685 // CHECK5-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
8686 // CHECK5-NEXT:    [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]]
8687 // CHECK5-NEXT:    [[SUB6:%.*]] = sub i32 [[SUB]], 1
8688 // CHECK5-NEXT:    [[ADD:%.*]] = add i32 [[SUB6]], 1
8689 // CHECK5-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], 1
8690 // CHECK5-NEXT:    [[SUB7:%.*]] = sub i32 [[DIV]], 1
8691 // CHECK5-NEXT:    store i32 [[SUB7]], i32* [[DOTCAPTURE_EXPR_5]], align 4
8692 // CHECK5-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
8693 // CHECK5-NEXT:    store i32 [[TMP5]], i32* [[I]], align 4
8694 // CHECK5-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
8695 // CHECK5-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4
8696 // CHECK5-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]]
8697 // CHECK5-NEXT:    br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
8698 // CHECK5:       omp.precond.then:
8699 // CHECK5-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
8700 // CHECK5-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4
8701 // CHECK5-NEXT:    store i32 [[TMP8]], i32* [[DOTOMP_UB]], align 4
8702 // CHECK5-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
8703 // CHECK5-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
8704 // CHECK5-NEXT:    [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
8705 // CHECK5-NEXT:    [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
8706 // CHECK5-NEXT:    call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
8707 // CHECK5-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
8708 // CHECK5-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4
8709 // CHECK5-NEXT:    [[CMP9:%.*]] = icmp ugt i32 [[TMP11]], [[TMP12]]
8710 // CHECK5-NEXT:    br i1 [[CMP9]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
8711 // CHECK5:       cond.true:
8712 // CHECK5-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4
8713 // CHECK5-NEXT:    br label [[COND_END:%.*]]
8714 // CHECK5:       cond.false:
8715 // CHECK5-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
8716 // CHECK5-NEXT:    br label [[COND_END]]
8717 // CHECK5:       cond.end:
8718 // CHECK5-NEXT:    [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ]
8719 // CHECK5-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
8720 // CHECK5-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
8721 // CHECK5-NEXT:    store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4
8722 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
8723 // CHECK5:       omp.inner.for.cond:
8724 // CHECK5-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !44
8725 // CHECK5-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !44
8726 // CHECK5-NEXT:    [[ADD10:%.*]] = add i32 [[TMP17]], 1
8727 // CHECK5-NEXT:    [[CMP11:%.*]] = icmp ult i32 [[TMP16]], [[ADD10]]
8728 // CHECK5-NEXT:    br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
8729 // CHECK5:       omp.inner.for.body:
8730 // CHECK5-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group !44
8731 // CHECK5-NEXT:    [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !44
8732 // CHECK5-NEXT:    [[MUL:%.*]] = mul i32 [[TMP19]], 1
8733 // CHECK5-NEXT:    [[ADD12:%.*]] = add i32 [[TMP18]], [[MUL]]
8734 // CHECK5-NEXT:    store i32 [[ADD12]], i32* [[I8]], align 4, !llvm.access.group !44
8735 // CHECK5-NEXT:    [[TMP20:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !44
8736 // CHECK5-NEXT:    [[ADD13:%.*]] = add nsw i32 [[TMP20]], 1
8737 // CHECK5-NEXT:    store i32 [[ADD13]], i32* [[CONV]], align 4, !llvm.access.group !44
8738 // CHECK5-NEXT:    [[TMP21:%.*]] = load i16, i16* [[CONV2]], align 2, !llvm.access.group !44
8739 // CHECK5-NEXT:    [[CONV14:%.*]] = sext i16 [[TMP21]] to i32
8740 // CHECK5-NEXT:    [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1
8741 // CHECK5-NEXT:    [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16
8742 // CHECK5-NEXT:    store i16 [[CONV16]], i16* [[CONV2]], align 2, !llvm.access.group !44
8743 // CHECK5-NEXT:    [[TMP22:%.*]] = load i8, i8* [[CONV3]], align 1, !llvm.access.group !44
8744 // CHECK5-NEXT:    [[CONV17:%.*]] = sext i8 [[TMP22]] to i32
8745 // CHECK5-NEXT:    [[ADD18:%.*]] = add nsw i32 [[CONV17]], 1
8746 // CHECK5-NEXT:    [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8
8747 // CHECK5-NEXT:    store i8 [[CONV19]], i8* [[CONV3]], align 1, !llvm.access.group !44
8748 // CHECK5-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
8749 // CHECK5-NEXT:    [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !44
8750 // CHECK5-NEXT:    [[ADD20:%.*]] = add nsw i32 [[TMP23]], 1
8751 // CHECK5-NEXT:    store i32 [[ADD20]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !44
8752 // CHECK5-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
8753 // CHECK5:       omp.body.continue:
8754 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
8755 // CHECK5:       omp.inner.for.inc:
8756 // CHECK5-NEXT:    [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !44
8757 // CHECK5-NEXT:    [[ADD21:%.*]] = add i32 [[TMP24]], 1
8758 // CHECK5-NEXT:    store i32 [[ADD21]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !44
8759 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP45:![0-9]+]]
8760 // CHECK5:       omp.inner.for.end:
8761 // CHECK5-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
8762 // CHECK5:       omp.loop.exit:
8763 // CHECK5-NEXT:    [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
8764 // CHECK5-NEXT:    [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4
8765 // CHECK5-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]])
8766 // CHECK5-NEXT:    [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
8767 // CHECK5-NEXT:    [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0
8768 // CHECK5-NEXT:    br i1 [[TMP28]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
8769 // CHECK5:       .omp.final.then:
8770 // CHECK5-NEXT:    [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
8771 // CHECK5-NEXT:    [[TMP30:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4
8772 // CHECK5-NEXT:    [[TMP31:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
8773 // CHECK5-NEXT:    [[SUB22:%.*]] = sub i32 [[TMP30]], [[TMP31]]
8774 // CHECK5-NEXT:    [[SUB23:%.*]] = sub i32 [[SUB22]], 1
8775 // CHECK5-NEXT:    [[ADD24:%.*]] = add i32 [[SUB23]], 1
8776 // CHECK5-NEXT:    [[DIV25:%.*]] = udiv i32 [[ADD24]], 1
8777 // CHECK5-NEXT:    [[MUL26:%.*]] = mul i32 [[DIV25]], 1
8778 // CHECK5-NEXT:    [[ADD27:%.*]] = add i32 [[TMP29]], [[MUL26]]
8779 // CHECK5-NEXT:    store i32 [[ADD27]], i32* [[I8]], align 4
8780 // CHECK5-NEXT:    br label [[DOTOMP_FINAL_DONE]]
8781 // CHECK5:       .omp.final.done:
8782 // CHECK5-NEXT:    br label [[OMP_PRECOND_END]]
8783 // CHECK5:       omp.precond.end:
8784 // CHECK5-NEXT:    ret void
8785 //
8786 //
8787 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180
8788 // CHECK5-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
8789 // CHECK5-NEXT:  entry:
8790 // CHECK5-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
8791 // CHECK5-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
8792 // CHECK5-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
8793 // CHECK5-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
8794 // CHECK5-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
8795 // CHECK5-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
8796 // CHECK5-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
8797 // CHECK5-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
8798 // CHECK5-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
8799 // CHECK5-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
8800 // CHECK5-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
8801 // CHECK5-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
8802 // CHECK5-NEXT:    [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
8803 // CHECK5-NEXT:    store i32 [[TMP1]], i32* [[CONV2]], align 4
8804 // CHECK5-NEXT:    [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
8805 // CHECK5-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
8806 // CHECK5-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
8807 // CHECK5-NEXT:    store i16 [[TMP3]], i16* [[CONV3]], align 2
8808 // CHECK5-NEXT:    [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
8809 // CHECK5-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..18 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]])
8810 // CHECK5-NEXT:    ret void
8811 //
8812 //
8813 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..18
8814 // CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] {
8815 // CHECK5-NEXT:  entry:
8816 // CHECK5-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
8817 // CHECK5-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
8818 // CHECK5-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
8819 // CHECK5-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
8820 // CHECK5-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
8821 // CHECK5-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
8822 // CHECK5-NEXT:    [[TMP:%.*]] = alloca i32, align 4
8823 // CHECK5-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
8824 // CHECK5-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
8825 // CHECK5-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
8826 // CHECK5-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
8827 // CHECK5-NEXT:    [[I:%.*]] = alloca i32, align 4
8828 // CHECK5-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
8829 // CHECK5-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
8830 // CHECK5-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
8831 // CHECK5-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
8832 // CHECK5-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
8833 // CHECK5-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
8834 // CHECK5-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
8835 // CHECK5-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
8836 // CHECK5-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
8837 // CHECK5-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
8838 // CHECK5-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
8839 // CHECK5-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
8840 // CHECK5-NEXT:    [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
8841 // CHECK5-NEXT:    [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
8842 // CHECK5-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
8843 // CHECK5-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
8844 // CHECK5-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9
8845 // CHECK5-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
8846 // CHECK5:       cond.true:
8847 // CHECK5-NEXT:    br label [[COND_END:%.*]]
8848 // CHECK5:       cond.false:
8849 // CHECK5-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
8850 // CHECK5-NEXT:    br label [[COND_END]]
8851 // CHECK5:       cond.end:
8852 // CHECK5-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
8853 // CHECK5-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
8854 // CHECK5-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
8855 // CHECK5-NEXT:    store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
8856 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
8857 // CHECK5:       omp.inner.for.cond:
8858 // CHECK5-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !47
8859 // CHECK5-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !47
8860 // CHECK5-NEXT:    [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
8861 // CHECK5-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
8862 // CHECK5:       omp.inner.for.body:
8863 // CHECK5-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !47
8864 // CHECK5-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
8865 // CHECK5-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
8866 // CHECK5-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !47
8867 // CHECK5-NEXT:    [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !47
8868 // CHECK5-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1
8869 // CHECK5-NEXT:    store i32 [[ADD3]], i32* [[CONV]], align 4, !llvm.access.group !47
8870 // CHECK5-NEXT:    [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 2, !llvm.access.group !47
8871 // CHECK5-NEXT:    [[CONV4:%.*]] = sext i16 [[TMP10]] to i32
8872 // CHECK5-NEXT:    [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
8873 // CHECK5-NEXT:    [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
8874 // CHECK5-NEXT:    store i16 [[CONV6]], i16* [[CONV1]], align 2, !llvm.access.group !47
8875 // CHECK5-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
8876 // CHECK5-NEXT:    [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !47
8877 // CHECK5-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1
8878 // CHECK5-NEXT:    store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !47
8879 // CHECK5-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
8880 // CHECK5:       omp.body.continue:
8881 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
8882 // CHECK5:       omp.inner.for.inc:
8883 // CHECK5-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !47
8884 // CHECK5-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP12]], 1
8885 // CHECK5-NEXT:    store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !47
8886 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP48:![0-9]+]]
8887 // CHECK5:       omp.inner.for.end:
8888 // CHECK5-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
8889 // CHECK5:       omp.loop.exit:
8890 // CHECK5-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
8891 // CHECK5-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
8892 // CHECK5-NEXT:    [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
8893 // CHECK5-NEXT:    br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
8894 // CHECK5:       .omp.final.then:
8895 // CHECK5-NEXT:    store i32 10, i32* [[I]], align 4
8896 // CHECK5-NEXT:    br label [[DOTOMP_FINAL_DONE]]
8897 // CHECK5:       .omp.final.done:
8898 // CHECK5-NEXT:    ret void
8899 //
8900 //
8901 // CHECK5-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
8902 // CHECK5-SAME: () #[[ATTR5]] {
8903 // CHECK5-NEXT:  entry:
8904 // CHECK5-NEXT:    call void @__tgt_register_requires(i64 1)
8905 // CHECK5-NEXT:    ret void
8906 //
8907 //
8908 // CHECK6-LABEL: define {{[^@]+}}@_Z3fooi
8909 // CHECK6-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0:[0-9]+]] {
8910 // CHECK6-NEXT:  entry:
8911 // CHECK6-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
8912 // CHECK6-NEXT:    [[A:%.*]] = alloca i32, align 4
8913 // CHECK6-NEXT:    [[AA:%.*]] = alloca i16, align 2
8914 // CHECK6-NEXT:    [[B:%.*]] = alloca [10 x float], align 4
8915 // CHECK6-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 8
8916 // CHECK6-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
8917 // CHECK6-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 8
8918 // CHECK6-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i64, align 8
8919 // CHECK6-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8
8920 // CHECK6-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
8921 // CHECK6-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
8922 // CHECK6-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
8923 // CHECK6-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
8924 // CHECK6-NEXT:    [[DOTCAPTURE_EXPR__CASTED4:%.*]] = alloca i64, align 8
8925 // CHECK6-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8
8926 // CHECK6-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8
8927 // CHECK6-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8
8928 // CHECK6-NEXT:    [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4
8929 // CHECK6-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
8930 // CHECK6-NEXT:    [[AA_CASTED7:%.*]] = alloca i64, align 8
8931 // CHECK6-NEXT:    [[DOTOFFLOAD_BASEPTRS9:%.*]] = alloca [1 x i8*], align 8
8932 // CHECK6-NEXT:    [[DOTOFFLOAD_PTRS10:%.*]] = alloca [1 x i8*], align 8
8933 // CHECK6-NEXT:    [[DOTOFFLOAD_MAPPERS11:%.*]] = alloca [1 x i8*], align 8
8934 // CHECK6-NEXT:    [[TMP:%.*]] = alloca i32, align 4
8935 // CHECK6-NEXT:    [[A_CASTED12:%.*]] = alloca i64, align 8
8936 // CHECK6-NEXT:    [[AA_CASTED14:%.*]] = alloca i64, align 8
8937 // CHECK6-NEXT:    [[DOTOFFLOAD_BASEPTRS16:%.*]] = alloca [2 x i8*], align 8
8938 // CHECK6-NEXT:    [[DOTOFFLOAD_PTRS17:%.*]] = alloca [2 x i8*], align 8
8939 // CHECK6-NEXT:    [[DOTOFFLOAD_MAPPERS18:%.*]] = alloca [2 x i8*], align 8
8940 // CHECK6-NEXT:    [[_TMP19:%.*]] = alloca i32, align 4
8941 // CHECK6-NEXT:    [[A_CASTED22:%.*]] = alloca i64, align 8
8942 // CHECK6-NEXT:    [[DOTOFFLOAD_BASEPTRS26:%.*]] = alloca [9 x i8*], align 8
8943 // CHECK6-NEXT:    [[DOTOFFLOAD_PTRS27:%.*]] = alloca [9 x i8*], align 8
8944 // CHECK6-NEXT:    [[DOTOFFLOAD_MAPPERS28:%.*]] = alloca [9 x i8*], align 8
8945 // CHECK6-NEXT:    [[DOTOFFLOAD_SIZES:%.*]] = alloca [9 x i64], align 8
8946 // CHECK6-NEXT:    [[_TMP29:%.*]] = alloca i32, align 4
8947 // CHECK6-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]])
8948 // CHECK6-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
8949 // CHECK6-NEXT:    store i32 0, i32* [[A]], align 4
8950 // CHECK6-NEXT:    store i16 0, i16* [[AA]], align 2
8951 // CHECK6-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
8952 // CHECK6-NEXT:    [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
8953 // CHECK6-NEXT:    [[TMP3:%.*]] = call i8* @llvm.stacksave()
8954 // CHECK6-NEXT:    store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8
8955 // CHECK6-NEXT:    [[VLA:%.*]] = alloca float, i64 [[TMP2]], align 4
8956 // CHECK6-NEXT:    store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8
8957 // CHECK6-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
8958 // CHECK6-NEXT:    [[TMP5:%.*]] = zext i32 [[TMP4]] to i64
8959 // CHECK6-NEXT:    [[TMP6:%.*]] = mul nuw i64 5, [[TMP5]]
8960 // CHECK6-NEXT:    [[VLA1:%.*]] = alloca double, i64 [[TMP6]], align 8
8961 // CHECK6-NEXT:    store i64 [[TMP5]], i64* [[__VLA_EXPR1]], align 8
8962 // CHECK6-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
8963 // CHECK6-NEXT:    store i32 [[TMP7]], i32* [[DOTCAPTURE_EXPR_]], align 4
8964 // CHECK6-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
8965 // CHECK6-NEXT:    store i32 [[TMP8]], i32* [[DOTCAPTURE_EXPR_2]], align 4
8966 // CHECK6-NEXT:    [[TMP9:%.*]] = load i16, i16* [[AA]], align 2
8967 // CHECK6-NEXT:    [[CONV:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
8968 // CHECK6-NEXT:    store i16 [[TMP9]], i16* [[CONV]], align 2
8969 // CHECK6-NEXT:    [[TMP10:%.*]] = load i64, i64* [[AA_CASTED]], align 8
8970 // CHECK6-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
8971 // CHECK6-NEXT:    [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
8972 // CHECK6-NEXT:    store i32 [[TMP11]], i32* [[CONV3]], align 4
8973 // CHECK6-NEXT:    [[TMP12:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
8974 // CHECK6-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
8975 // CHECK6-NEXT:    [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED4]] to i32*
8976 // CHECK6-NEXT:    store i32 [[TMP13]], i32* [[CONV5]], align 4
8977 // CHECK6-NEXT:    [[TMP14:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED4]], align 8
8978 // CHECK6-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
8979 // CHECK6-NEXT:    [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i64*
8980 // CHECK6-NEXT:    store i64 [[TMP10]], i64* [[TMP16]], align 8
8981 // CHECK6-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
8982 // CHECK6-NEXT:    [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64*
8983 // CHECK6-NEXT:    store i64 [[TMP10]], i64* [[TMP18]], align 8
8984 // CHECK6-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
8985 // CHECK6-NEXT:    store i8* null, i8** [[TMP19]], align 8
8986 // CHECK6-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
8987 // CHECK6-NEXT:    [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i64*
8988 // CHECK6-NEXT:    store i64 [[TMP12]], i64* [[TMP21]], align 8
8989 // CHECK6-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
8990 // CHECK6-NEXT:    [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i64*
8991 // CHECK6-NEXT:    store i64 [[TMP12]], i64* [[TMP23]], align 8
8992 // CHECK6-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
8993 // CHECK6-NEXT:    store i8* null, i8** [[TMP24]], align 8
8994 // CHECK6-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
8995 // CHECK6-NEXT:    [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i64*
8996 // CHECK6-NEXT:    store i64 [[TMP14]], i64* [[TMP26]], align 8
8997 // CHECK6-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
8998 // CHECK6-NEXT:    [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i64*
8999 // CHECK6-NEXT:    store i64 [[TMP14]], i64* [[TMP28]], align 8
9000 // CHECK6-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
9001 // CHECK6-NEXT:    store i8* null, i8** [[TMP29]], align 8
9002 // CHECK6-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
9003 // CHECK6-NEXT:    [[TMP31:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
9004 // CHECK6-NEXT:    [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 0
9005 // CHECK6-NEXT:    [[TMP33:%.*]] = load i16, i16* [[AA]], align 2
9006 // CHECK6-NEXT:    store i16 [[TMP33]], i16* [[TMP32]], align 4
9007 // CHECK6-NEXT:    [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 1
9008 // CHECK6-NEXT:    [[TMP35:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
9009 // CHECK6-NEXT:    store i32 [[TMP35]], i32* [[TMP34]], align 4
9010 // CHECK6-NEXT:    [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 2
9011 // CHECK6-NEXT:    [[TMP37:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
9012 // CHECK6-NEXT:    store i32 [[TMP37]], i32* [[TMP36]], align 4
9013 // CHECK6-NEXT:    [[TMP38:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 1, i64 120, i64 12, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1)
9014 // CHECK6-NEXT:    [[TMP39:%.*]] = bitcast i8* [[TMP38]] to %struct.kmp_task_t_with_privates*
9015 // CHECK6-NEXT:    [[TMP40:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP39]], i32 0, i32 0
9016 // CHECK6-NEXT:    [[TMP41:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP40]], i32 0, i32 0
9017 // CHECK6-NEXT:    [[TMP42:%.*]] = load i8*, i8** [[TMP41]], align 8
9018 // CHECK6-NEXT:    [[TMP43:%.*]] = bitcast %struct.anon* [[AGG_CAPTURED]] to i8*
9019 // CHECK6-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP42]], i8* align 4 [[TMP43]], i64 12, i1 false)
9020 // CHECK6-NEXT:    [[TMP44:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP39]], i32 0, i32 1
9021 // CHECK6-NEXT:    [[TMP45:%.*]] = bitcast i8* [[TMP42]] to %struct.anon*
9022 // CHECK6-NEXT:    [[TMP46:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 0
9023 // CHECK6-NEXT:    [[TMP47:%.*]] = bitcast [3 x i8*]* [[TMP46]] to i8*
9024 // CHECK6-NEXT:    [[TMP48:%.*]] = bitcast i8** [[TMP30]] to i8*
9025 // CHECK6-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP47]], i8* align 8 [[TMP48]], i64 24, i1 false)
9026 // CHECK6-NEXT:    [[TMP49:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 1
9027 // CHECK6-NEXT:    [[TMP50:%.*]] = bitcast [3 x i8*]* [[TMP49]] to i8*
9028 // CHECK6-NEXT:    [[TMP51:%.*]] = bitcast i8** [[TMP31]] to i8*
9029 // CHECK6-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP50]], i8* align 8 [[TMP51]], i64 24, i1 false)
9030 // CHECK6-NEXT:    [[TMP52:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 2
9031 // CHECK6-NEXT:    [[TMP53:%.*]] = bitcast [3 x i64]* [[TMP52]] to i8*
9032 // CHECK6-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP53]], i8* align 8 bitcast ([3 x i64]* @.offload_sizes to i8*), i64 24, i1 false)
9033 // CHECK6-NEXT:    [[TMP54:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 3
9034 // CHECK6-NEXT:    [[TMP55:%.*]] = load i16, i16* [[AA]], align 2
9035 // CHECK6-NEXT:    store i16 [[TMP55]], i16* [[TMP54]], align 8
9036 // CHECK6-NEXT:    [[TMP56:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i8* [[TMP38]])
9037 // CHECK6-NEXT:    [[TMP57:%.*]] = load i32, i32* [[A]], align 4
9038 // CHECK6-NEXT:    [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32*
9039 // CHECK6-NEXT:    store i32 [[TMP57]], i32* [[CONV6]], align 4
9040 // CHECK6-NEXT:    [[TMP58:%.*]] = load i64, i64* [[A_CASTED]], align 8
9041 // CHECK6-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l102(i64 [[TMP58]]) #[[ATTR4:[0-9]+]]
9042 // CHECK6-NEXT:    [[TMP59:%.*]] = load i16, i16* [[AA]], align 2
9043 // CHECK6-NEXT:    [[CONV8:%.*]] = bitcast i64* [[AA_CASTED7]] to i16*
9044 // CHECK6-NEXT:    store i16 [[TMP59]], i16* [[CONV8]], align 2
9045 // CHECK6-NEXT:    [[TMP60:%.*]] = load i64, i64* [[AA_CASTED7]], align 8
9046 // CHECK6-NEXT:    [[TMP61:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS9]], i32 0, i32 0
9047 // CHECK6-NEXT:    [[TMP62:%.*]] = bitcast i8** [[TMP61]] to i64*
9048 // CHECK6-NEXT:    store i64 [[TMP60]], i64* [[TMP62]], align 8
9049 // CHECK6-NEXT:    [[TMP63:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS10]], i32 0, i32 0
9050 // CHECK6-NEXT:    [[TMP64:%.*]] = bitcast i8** [[TMP63]] to i64*
9051 // CHECK6-NEXT:    store i64 [[TMP60]], i64* [[TMP64]], align 8
9052 // CHECK6-NEXT:    [[TMP65:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS11]], i64 0, i64 0
9053 // CHECK6-NEXT:    store i8* null, i8** [[TMP65]], align 8
9054 // CHECK6-NEXT:    [[TMP66:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS9]], i32 0, i32 0
9055 // CHECK6-NEXT:    [[TMP67:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS10]], i32 0, i32 0
9056 // CHECK6-NEXT:    call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10)
9057 // CHECK6-NEXT:    [[TMP68:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.region_id, i32 1, i8** [[TMP66]], i8** [[TMP67]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.4, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.5, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1)
9058 // CHECK6-NEXT:    [[TMP69:%.*]] = icmp ne i32 [[TMP68]], 0
9059 // CHECK6-NEXT:    br i1 [[TMP69]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
9060 // CHECK6:       omp_offload.failed:
9061 // CHECK6-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111(i64 [[TMP60]]) #[[ATTR4]]
9062 // CHECK6-NEXT:    br label [[OMP_OFFLOAD_CONT]]
9063 // CHECK6:       omp_offload.cont:
9064 // CHECK6-NEXT:    [[TMP70:%.*]] = load i32, i32* [[A]], align 4
9065 // CHECK6-NEXT:    [[CONV13:%.*]] = bitcast i64* [[A_CASTED12]] to i32*
9066 // CHECK6-NEXT:    store i32 [[TMP70]], i32* [[CONV13]], align 4
9067 // CHECK6-NEXT:    [[TMP71:%.*]] = load i64, i64* [[A_CASTED12]], align 8
9068 // CHECK6-NEXT:    [[TMP72:%.*]] = load i16, i16* [[AA]], align 2
9069 // CHECK6-NEXT:    [[CONV15:%.*]] = bitcast i64* [[AA_CASTED14]] to i16*
9070 // CHECK6-NEXT:    store i16 [[TMP72]], i16* [[CONV15]], align 2
9071 // CHECK6-NEXT:    [[TMP73:%.*]] = load i64, i64* [[AA_CASTED14]], align 8
9072 // CHECK6-NEXT:    [[TMP74:%.*]] = load i32, i32* [[N_ADDR]], align 4
9073 // CHECK6-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP74]], 10
9074 // CHECK6-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
9075 // CHECK6:       omp_if.then:
9076 // CHECK6-NEXT:    [[TMP75:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 0
9077 // CHECK6-NEXT:    [[TMP76:%.*]] = bitcast i8** [[TMP75]] to i64*
9078 // CHECK6-NEXT:    store i64 [[TMP71]], i64* [[TMP76]], align 8
9079 // CHECK6-NEXT:    [[TMP77:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 0
9080 // CHECK6-NEXT:    [[TMP78:%.*]] = bitcast i8** [[TMP77]] to i64*
9081 // CHECK6-NEXT:    store i64 [[TMP71]], i64* [[TMP78]], align 8
9082 // CHECK6-NEXT:    [[TMP79:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 0
9083 // CHECK6-NEXT:    store i8* null, i8** [[TMP79]], align 8
9084 // CHECK6-NEXT:    [[TMP80:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 1
9085 // CHECK6-NEXT:    [[TMP81:%.*]] = bitcast i8** [[TMP80]] to i64*
9086 // CHECK6-NEXT:    store i64 [[TMP73]], i64* [[TMP81]], align 8
9087 // CHECK6-NEXT:    [[TMP82:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 1
9088 // CHECK6-NEXT:    [[TMP83:%.*]] = bitcast i8** [[TMP82]] to i64*
9089 // CHECK6-NEXT:    store i64 [[TMP73]], i64* [[TMP83]], align 8
9090 // CHECK6-NEXT:    [[TMP84:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 1
9091 // CHECK6-NEXT:    store i8* null, i8** [[TMP84]], align 8
9092 // CHECK6-NEXT:    [[TMP85:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 0
9093 // CHECK6-NEXT:    [[TMP86:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 0
9094 // CHECK6-NEXT:    call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10)
9095 // CHECK6-NEXT:    [[TMP87:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.region_id, i32 2, i8** [[TMP85]], i8** [[TMP86]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.7, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.8, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1)
9096 // CHECK6-NEXT:    [[TMP88:%.*]] = icmp ne i32 [[TMP87]], 0
9097 // CHECK6-NEXT:    br i1 [[TMP88]], label [[OMP_OFFLOAD_FAILED20:%.*]], label [[OMP_OFFLOAD_CONT21:%.*]]
9098 // CHECK6:       omp_offload.failed20:
9099 // CHECK6-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i64 [[TMP71]], i64 [[TMP73]]) #[[ATTR4]]
9100 // CHECK6-NEXT:    br label [[OMP_OFFLOAD_CONT21]]
9101 // CHECK6:       omp_offload.cont21:
9102 // CHECK6-NEXT:    br label [[OMP_IF_END:%.*]]
9103 // CHECK6:       omp_if.else:
9104 // CHECK6-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i64 [[TMP71]], i64 [[TMP73]]) #[[ATTR4]]
9105 // CHECK6-NEXT:    br label [[OMP_IF_END]]
9106 // CHECK6:       omp_if.end:
9107 // CHECK6-NEXT:    [[TMP89:%.*]] = load i32, i32* [[A]], align 4
9108 // CHECK6-NEXT:    [[CONV23:%.*]] = bitcast i64* [[A_CASTED22]] to i32*
9109 // CHECK6-NEXT:    store i32 [[TMP89]], i32* [[CONV23]], align 4
9110 // CHECK6-NEXT:    [[TMP90:%.*]] = load i64, i64* [[A_CASTED22]], align 8
9111 // CHECK6-NEXT:    [[TMP91:%.*]] = load i32, i32* [[N_ADDR]], align 4
9112 // CHECK6-NEXT:    [[CMP24:%.*]] = icmp sgt i32 [[TMP91]], 20
9113 // CHECK6-NEXT:    br i1 [[CMP24]], label [[OMP_IF_THEN25:%.*]], label [[OMP_IF_ELSE32:%.*]]
9114 // CHECK6:       omp_if.then25:
9115 // CHECK6-NEXT:    [[TMP92:%.*]] = mul nuw i64 [[TMP2]], 4
9116 // CHECK6-NEXT:    [[TMP93:%.*]] = mul nuw i64 5, [[TMP5]]
9117 // CHECK6-NEXT:    [[TMP94:%.*]] = mul nuw i64 [[TMP93]], 8
9118 // CHECK6-NEXT:    [[TMP95:%.*]] = bitcast [9 x i64]* [[DOTOFFLOAD_SIZES]] to i8*
9119 // CHECK6-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP95]], i8* align 8 bitcast ([9 x i64]* @.offload_sizes.10 to i8*), i64 72, i1 false)
9120 // CHECK6-NEXT:    [[TMP96:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS26]], i32 0, i32 0
9121 // CHECK6-NEXT:    [[TMP97:%.*]] = bitcast i8** [[TMP96]] to i64*
9122 // CHECK6-NEXT:    store i64 [[TMP90]], i64* [[TMP97]], align 8
9123 // CHECK6-NEXT:    [[TMP98:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS27]], i32 0, i32 0
9124 // CHECK6-NEXT:    [[TMP99:%.*]] = bitcast i8** [[TMP98]] to i64*
9125 // CHECK6-NEXT:    store i64 [[TMP90]], i64* [[TMP99]], align 8
9126 // CHECK6-NEXT:    [[TMP100:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS28]], i64 0, i64 0
9127 // CHECK6-NEXT:    store i8* null, i8** [[TMP100]], align 8
9128 // CHECK6-NEXT:    [[TMP101:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS26]], i32 0, i32 1
9129 // CHECK6-NEXT:    [[TMP102:%.*]] = bitcast i8** [[TMP101]] to [10 x float]**
9130 // CHECK6-NEXT:    store [10 x float]* [[B]], [10 x float]** [[TMP102]], align 8
9131 // CHECK6-NEXT:    [[TMP103:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS27]], i32 0, i32 1
9132 // CHECK6-NEXT:    [[TMP104:%.*]] = bitcast i8** [[TMP103]] to [10 x float]**
9133 // CHECK6-NEXT:    store [10 x float]* [[B]], [10 x float]** [[TMP104]], align 8
9134 // CHECK6-NEXT:    [[TMP105:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS28]], i64 0, i64 1
9135 // CHECK6-NEXT:    store i8* null, i8** [[TMP105]], align 8
9136 // CHECK6-NEXT:    [[TMP106:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS26]], i32 0, i32 2
9137 // CHECK6-NEXT:    [[TMP107:%.*]] = bitcast i8** [[TMP106]] to i64*
9138 // CHECK6-NEXT:    store i64 [[TMP2]], i64* [[TMP107]], align 8
9139 // CHECK6-NEXT:    [[TMP108:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS27]], i32 0, i32 2
9140 // CHECK6-NEXT:    [[TMP109:%.*]] = bitcast i8** [[TMP108]] to i64*
9141 // CHECK6-NEXT:    store i64 [[TMP2]], i64* [[TMP109]], align 8
9142 // CHECK6-NEXT:    [[TMP110:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS28]], i64 0, i64 2
9143 // CHECK6-NEXT:    store i8* null, i8** [[TMP110]], align 8
9144 // CHECK6-NEXT:    [[TMP111:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS26]], i32 0, i32 3
9145 // CHECK6-NEXT:    [[TMP112:%.*]] = bitcast i8** [[TMP111]] to float**
9146 // CHECK6-NEXT:    store float* [[VLA]], float** [[TMP112]], align 8
9147 // CHECK6-NEXT:    [[TMP113:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS27]], i32 0, i32 3
9148 // CHECK6-NEXT:    [[TMP114:%.*]] = bitcast i8** [[TMP113]] to float**
9149 // CHECK6-NEXT:    store float* [[VLA]], float** [[TMP114]], align 8
9150 // CHECK6-NEXT:    [[TMP115:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3
9151 // CHECK6-NEXT:    store i64 [[TMP92]], i64* [[TMP115]], align 8
9152 // CHECK6-NEXT:    [[TMP116:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS28]], i64 0, i64 3
9153 // CHECK6-NEXT:    store i8* null, i8** [[TMP116]], align 8
9154 // CHECK6-NEXT:    [[TMP117:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS26]], i32 0, i32 4
9155 // CHECK6-NEXT:    [[TMP118:%.*]] = bitcast i8** [[TMP117]] to [5 x [10 x double]]**
9156 // CHECK6-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP118]], align 8
9157 // CHECK6-NEXT:    [[TMP119:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS27]], i32 0, i32 4
9158 // CHECK6-NEXT:    [[TMP120:%.*]] = bitcast i8** [[TMP119]] to [5 x [10 x double]]**
9159 // CHECK6-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP120]], align 8
9160 // CHECK6-NEXT:    [[TMP121:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS28]], i64 0, i64 4
9161 // CHECK6-NEXT:    store i8* null, i8** [[TMP121]], align 8
9162 // CHECK6-NEXT:    [[TMP122:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS26]], i32 0, i32 5
9163 // CHECK6-NEXT:    [[TMP123:%.*]] = bitcast i8** [[TMP122]] to i64*
9164 // CHECK6-NEXT:    store i64 5, i64* [[TMP123]], align 8
9165 // CHECK6-NEXT:    [[TMP124:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS27]], i32 0, i32 5
9166 // CHECK6-NEXT:    [[TMP125:%.*]] = bitcast i8** [[TMP124]] to i64*
9167 // CHECK6-NEXT:    store i64 5, i64* [[TMP125]], align 8
9168 // CHECK6-NEXT:    [[TMP126:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS28]], i64 0, i64 5
9169 // CHECK6-NEXT:    store i8* null, i8** [[TMP126]], align 8
9170 // CHECK6-NEXT:    [[TMP127:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS26]], i32 0, i32 6
9171 // CHECK6-NEXT:    [[TMP128:%.*]] = bitcast i8** [[TMP127]] to i64*
9172 // CHECK6-NEXT:    store i64 [[TMP5]], i64* [[TMP128]], align 8
9173 // CHECK6-NEXT:    [[TMP129:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS27]], i32 0, i32 6
9174 // CHECK6-NEXT:    [[TMP130:%.*]] = bitcast i8** [[TMP129]] to i64*
9175 // CHECK6-NEXT:    store i64 [[TMP5]], i64* [[TMP130]], align 8
9176 // CHECK6-NEXT:    [[TMP131:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS28]], i64 0, i64 6
9177 // CHECK6-NEXT:    store i8* null, i8** [[TMP131]], align 8
9178 // CHECK6-NEXT:    [[TMP132:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS26]], i32 0, i32 7
9179 // CHECK6-NEXT:    [[TMP133:%.*]] = bitcast i8** [[TMP132]] to double**
9180 // CHECK6-NEXT:    store double* [[VLA1]], double** [[TMP133]], align 8
9181 // CHECK6-NEXT:    [[TMP134:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS27]], i32 0, i32 7
9182 // CHECK6-NEXT:    [[TMP135:%.*]] = bitcast i8** [[TMP134]] to double**
9183 // CHECK6-NEXT:    store double* [[VLA1]], double** [[TMP135]], align 8
9184 // CHECK6-NEXT:    [[TMP136:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7
9185 // CHECK6-NEXT:    store i64 [[TMP94]], i64* [[TMP136]], align 8
9186 // CHECK6-NEXT:    [[TMP137:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS28]], i64 0, i64 7
9187 // CHECK6-NEXT:    store i8* null, i8** [[TMP137]], align 8
9188 // CHECK6-NEXT:    [[TMP138:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS26]], i32 0, i32 8
9189 // CHECK6-NEXT:    [[TMP139:%.*]] = bitcast i8** [[TMP138]] to %struct.TT**
9190 // CHECK6-NEXT:    store %struct.TT* [[D]], %struct.TT** [[TMP139]], align 8
9191 // CHECK6-NEXT:    [[TMP140:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS27]], i32 0, i32 8
9192 // CHECK6-NEXT:    [[TMP141:%.*]] = bitcast i8** [[TMP140]] to %struct.TT**
9193 // CHECK6-NEXT:    store %struct.TT* [[D]], %struct.TT** [[TMP141]], align 8
9194 // CHECK6-NEXT:    [[TMP142:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS28]], i64 0, i64 8
9195 // CHECK6-NEXT:    store i8* null, i8** [[TMP142]], align 8
9196 // CHECK6-NEXT:    [[TMP143:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS26]], i32 0, i32 0
9197 // CHECK6-NEXT:    [[TMP144:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS27]], i32 0, i32 0
9198 // CHECK6-NEXT:    [[TMP145:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
9199 // CHECK6-NEXT:    call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10)
9200 // CHECK6-NEXT:    [[TMP146:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142.region_id, i32 9, i8** [[TMP143]], i8** [[TMP144]], i64* [[TMP145]], i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_maptypes.11, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1)
9201 // CHECK6-NEXT:    [[TMP147:%.*]] = icmp ne i32 [[TMP146]], 0
9202 // CHECK6-NEXT:    br i1 [[TMP147]], label [[OMP_OFFLOAD_FAILED30:%.*]], label [[OMP_OFFLOAD_CONT31:%.*]]
9203 // CHECK6:       omp_offload.failed30:
9204 // CHECK6-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i64 [[TMP90]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR4]]
9205 // CHECK6-NEXT:    br label [[OMP_OFFLOAD_CONT31]]
9206 // CHECK6:       omp_offload.cont31:
9207 // CHECK6-NEXT:    br label [[OMP_IF_END33:%.*]]
9208 // CHECK6:       omp_if.else32:
9209 // CHECK6-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i64 [[TMP90]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR4]]
9210 // CHECK6-NEXT:    br label [[OMP_IF_END33]]
9211 // CHECK6:       omp_if.end33:
9212 // CHECK6-NEXT:    [[TMP148:%.*]] = load i32, i32* [[A]], align 4
9213 // CHECK6-NEXT:    [[TMP149:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
9214 // CHECK6-NEXT:    call void @llvm.stackrestore(i8* [[TMP149]])
9215 // CHECK6-NEXT:    ret i32 [[TMP148]]
9216 //
9217 //
9218 // CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97
9219 // CHECK6-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] {
9220 // CHECK6-NEXT:  entry:
9221 // CHECK6-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
9222 // CHECK6-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
9223 // CHECK6-NEXT:    [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8
9224 // CHECK6-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
9225 // CHECK6-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]])
9226 // CHECK6-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
9227 // CHECK6-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
9228 // CHECK6-NEXT:    store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8
9229 // CHECK6-NEXT:    [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
9230 // CHECK6-NEXT:    [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
9231 // CHECK6-NEXT:    [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32*
9232 // CHECK6-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 4
9233 // CHECK6-NEXT:    [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 4
9234 // CHECK6-NEXT:    call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
9235 // CHECK6-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
9236 // CHECK6-NEXT:    [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
9237 // CHECK6-NEXT:    store i16 [[TMP3]], i16* [[CONV5]], align 2
9238 // CHECK6-NEXT:    [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
9239 // CHECK6-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]])
9240 // CHECK6-NEXT:    ret void
9241 //
9242 //
9243 // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined.
9244 // CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR3:[0-9]+]] {
9245 // CHECK6-NEXT:  entry:
9246 // CHECK6-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
9247 // CHECK6-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
9248 // CHECK6-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
9249 // CHECK6-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
9250 // CHECK6-NEXT:    [[TMP:%.*]] = alloca i32, align 4
9251 // CHECK6-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
9252 // CHECK6-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
9253 // CHECK6-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
9254 // CHECK6-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
9255 // CHECK6-NEXT:    [[I:%.*]] = alloca i32, align 4
9256 // CHECK6-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
9257 // CHECK6-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
9258 // CHECK6-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
9259 // CHECK6-NEXT:    [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
9260 // CHECK6-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
9261 // CHECK6-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
9262 // CHECK6-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
9263 // CHECK6-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
9264 // CHECK6-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
9265 // CHECK6-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
9266 // CHECK6-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
9267 // CHECK6-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
9268 // CHECK6-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
9269 // CHECK6-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
9270 // CHECK6:       cond.true:
9271 // CHECK6-NEXT:    br label [[COND_END:%.*]]
9272 // CHECK6:       cond.false:
9273 // CHECK6-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
9274 // CHECK6-NEXT:    br label [[COND_END]]
9275 // CHECK6:       cond.end:
9276 // CHECK6-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
9277 // CHECK6-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
9278 // CHECK6-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
9279 // CHECK6-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
9280 // CHECK6-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
9281 // CHECK6:       omp.inner.for.cond:
9282 // CHECK6-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
9283 // CHECK6-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !10
9284 // CHECK6-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
9285 // CHECK6-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
9286 // CHECK6:       omp.inner.for.body:
9287 // CHECK6-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
9288 // CHECK6-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
9289 // CHECK6-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
9290 // CHECK6-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10
9291 // CHECK6-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
9292 // CHECK6:       omp.body.continue:
9293 // CHECK6-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
9294 // CHECK6:       omp.inner.for.inc:
9295 // CHECK6-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
9296 // CHECK6-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
9297 // CHECK6-NEXT:    store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
9298 // CHECK6-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]
9299 // CHECK6:       omp.inner.for.end:
9300 // CHECK6-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
9301 // CHECK6:       omp.loop.exit:
9302 // CHECK6-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
9303 // CHECK6-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
9304 // CHECK6-NEXT:    [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0
9305 // CHECK6-NEXT:    br i1 [[TMP10]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
9306 // CHECK6:       .omp.final.then:
9307 // CHECK6-NEXT:    store i32 10, i32* [[I]], align 4
9308 // CHECK6-NEXT:    br label [[DOTOMP_FINAL_DONE]]
9309 // CHECK6:       .omp.final.done:
9310 // CHECK6-NEXT:    ret void
9311 //
9312 //
9313 // CHECK6-LABEL: define {{[^@]+}}@.omp_task_privates_map.
9314 // CHECK6-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], i16** noalias noundef [[TMP1:%.*]], [3 x i8*]** noalias noundef [[TMP2:%.*]], [3 x i8*]** noalias noundef [[TMP3:%.*]], [3 x i64]** noalias noundef [[TMP4:%.*]]) #[[ATTR5:[0-9]+]] {
9315 // CHECK6-NEXT:  entry:
9316 // CHECK6-NEXT:    [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 8
9317 // CHECK6-NEXT:    [[DOTADDR1:%.*]] = alloca i16**, align 8
9318 // CHECK6-NEXT:    [[DOTADDR2:%.*]] = alloca [3 x i8*]**, align 8
9319 // CHECK6-NEXT:    [[DOTADDR3:%.*]] = alloca [3 x i8*]**, align 8
9320 // CHECK6-NEXT:    [[DOTADDR4:%.*]] = alloca [3 x i64]**, align 8
9321 // CHECK6-NEXT:    store %struct..kmp_privates.t* [[TMP0]], %struct..kmp_privates.t** [[DOTADDR]], align 8
9322 // CHECK6-NEXT:    store i16** [[TMP1]], i16*** [[DOTADDR1]], align 8
9323 // CHECK6-NEXT:    store [3 x i8*]** [[TMP2]], [3 x i8*]*** [[DOTADDR2]], align 8
9324 // CHECK6-NEXT:    store [3 x i8*]** [[TMP3]], [3 x i8*]*** [[DOTADDR3]], align 8
9325 // CHECK6-NEXT:    store [3 x i64]** [[TMP4]], [3 x i64]*** [[DOTADDR4]], align 8
9326 // CHECK6-NEXT:    [[TMP5:%.*]] = load %struct..kmp_privates.t*, %struct..kmp_privates.t** [[DOTADDR]], align 8
9327 // CHECK6-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 0
9328 // CHECK6-NEXT:    [[TMP7:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR2]], align 8
9329 // CHECK6-NEXT:    store [3 x i8*]* [[TMP6]], [3 x i8*]** [[TMP7]], align 8
9330 // CHECK6-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 1
9331 // CHECK6-NEXT:    [[TMP9:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR3]], align 8
9332 // CHECK6-NEXT:    store [3 x i8*]* [[TMP8]], [3 x i8*]** [[TMP9]], align 8
9333 // CHECK6-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 2
9334 // CHECK6-NEXT:    [[TMP11:%.*]] = load [3 x i64]**, [3 x i64]*** [[DOTADDR4]], align 8
9335 // CHECK6-NEXT:    store [3 x i64]* [[TMP10]], [3 x i64]** [[TMP11]], align 8
9336 // CHECK6-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 3
9337 // CHECK6-NEXT:    [[TMP13:%.*]] = load i16**, i16*** [[DOTADDR1]], align 8
9338 // CHECK6-NEXT:    store i16* [[TMP12]], i16** [[TMP13]], align 8
9339 // CHECK6-NEXT:    ret void
9340 //
9341 //
9342 // CHECK6-LABEL: define {{[^@]+}}@.omp_task_entry.
9343 // CHECK6-SAME: (i32 noundef signext [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] {
9344 // CHECK6-NEXT:  entry:
9345 // CHECK6-NEXT:    [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
9346 // CHECK6-NEXT:    [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8
9347 // CHECK6-NEXT:    [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8
9348 // CHECK6-NEXT:    [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8
9349 // CHECK6-NEXT:    [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8
9350 // CHECK6-NEXT:    [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 8
9351 // CHECK6-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca i16*, align 8
9352 // CHECK6-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca [3 x i8*]*, align 8
9353 // CHECK6-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca [3 x i8*]*, align 8
9354 // CHECK6-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca [3 x i64]*, align 8
9355 // CHECK6-NEXT:    [[AA_CASTED_I:%.*]] = alloca i64, align 8
9356 // CHECK6-NEXT:    [[DOTCAPTURE_EXPR__CASTED_I:%.*]] = alloca i64, align 8
9357 // CHECK6-NEXT:    [[DOTCAPTURE_EXPR__CASTED5_I:%.*]] = alloca i64, align 8
9358 // CHECK6-NEXT:    [[DOTADDR:%.*]] = alloca i32, align 4
9359 // CHECK6-NEXT:    [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8
9360 // CHECK6-NEXT:    store i32 [[TMP0]], i32* [[DOTADDR]], align 4
9361 // CHECK6-NEXT:    store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8
9362 // CHECK6-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4
9363 // CHECK6-NEXT:    [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8
9364 // CHECK6-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
9365 // CHECK6-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
9366 // CHECK6-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0
9367 // CHECK6-NEXT:    [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8
9368 // CHECK6-NEXT:    [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon*
9369 // CHECK6-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1
9370 // CHECK6-NEXT:    [[TMP10:%.*]] = bitcast %struct..kmp_privates.t* [[TMP9]] to i8*
9371 // CHECK6-NEXT:    [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8*
9372 // CHECK6-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META17:![0-9]+]])
9373 // CHECK6-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]])
9374 // CHECK6-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META22:![0-9]+]])
9375 // CHECK6-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META24:![0-9]+]])
9376 // CHECK6-NEXT:    store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !26
9377 // CHECK6-NEXT:    store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !26
9378 // CHECK6-NEXT:    store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !26
9379 // CHECK6-NEXT:    store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* @.omp_task_privates_map. to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !26
9380 // CHECK6-NEXT:    store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !26
9381 // CHECK6-NEXT:    store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !26
9382 // CHECK6-NEXT:    [[TMP12:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !26
9383 // CHECK6-NEXT:    [[TMP13:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !26
9384 // CHECK6-NEXT:    [[TMP14:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !26
9385 // CHECK6-NEXT:    [[TMP15:%.*]] = bitcast void (i8*, ...)* [[TMP13]] to void (i8*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)*
9386 // CHECK6-NEXT:    call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR4]]
9387 // CHECK6-NEXT:    [[TMP16:%.*]] = load i16*, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !26
9388 // CHECK6-NEXT:    [[TMP17:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !26
9389 // CHECK6-NEXT:    [[TMP18:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 8, !noalias !26
9390 // CHECK6-NEXT:    [[TMP19:%.*]] = load [3 x i64]*, [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 8, !noalias !26
9391 // CHECK6-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP17]], i64 0, i64 0
9392 // CHECK6-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP18]], i64 0, i64 0
9393 // CHECK6-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[TMP19]], i64 0, i64 0
9394 // CHECK6-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP12]], i32 0, i32 1
9395 // CHECK6-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[TMP12]], i32 0, i32 2
9396 // CHECK6-NEXT:    [[TMP25:%.*]] = load i32, i32* [[TMP23]], align 4
9397 // CHECK6-NEXT:    call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) #[[ATTR4]]
9398 // CHECK6-NEXT:    [[TMP26:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 [[TMP25]], i32 1, i32 0, i8* null, i32 0, i8* null) #[[ATTR4]]
9399 // CHECK6-NEXT:    [[TMP27:%.*]] = icmp ne i32 [[TMP26]], 0
9400 // CHECK6-NEXT:    br i1 [[TMP27]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]]
9401 // CHECK6:       omp_offload.failed.i:
9402 // CHECK6-NEXT:    [[TMP28:%.*]] = load i16, i16* [[TMP16]], align 2
9403 // CHECK6-NEXT:    [[CONV_I:%.*]] = bitcast i64* [[AA_CASTED_I]] to i16*
9404 // CHECK6-NEXT:    store i16 [[TMP28]], i16* [[CONV_I]], align 2, !noalias !26
9405 // CHECK6-NEXT:    [[TMP29:%.*]] = load i64, i64* [[AA_CASTED_I]], align 8, !noalias !26
9406 // CHECK6-NEXT:    [[TMP30:%.*]] = load i32, i32* [[TMP23]], align 4
9407 // CHECK6-NEXT:    [[CONV4_I:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED_I]] to i32*
9408 // CHECK6-NEXT:    store i32 [[TMP30]], i32* [[CONV4_I]], align 4, !noalias !26
9409 // CHECK6-NEXT:    [[TMP31:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED_I]], align 8, !noalias !26
9410 // CHECK6-NEXT:    [[TMP32:%.*]] = load i32, i32* [[TMP24]], align 4
9411 // CHECK6-NEXT:    [[CONV6_I:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED5_I]] to i32*
9412 // CHECK6-NEXT:    store i32 [[TMP32]], i32* [[CONV6_I]], align 4, !noalias !26
9413 // CHECK6-NEXT:    [[TMP33:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED5_I]], align 8, !noalias !26
9414 // CHECK6-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97(i64 [[TMP29]], i64 [[TMP31]], i64 [[TMP33]]) #[[ATTR4]]
9415 // CHECK6-NEXT:    br label [[DOTOMP_OUTLINED__1_EXIT]]
9416 // CHECK6:       .omp_outlined..1.exit:
9417 // CHECK6-NEXT:    ret i32 0
9418 //
9419 //
9420 // CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l102
9421 // CHECK6-SAME: (i64 noundef [[A:%.*]]) #[[ATTR3]] {
9422 // CHECK6-NEXT:  entry:
9423 // CHECK6-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
9424 // CHECK6-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
9425 // CHECK6-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
9426 // CHECK6-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
9427 // CHECK6-NEXT:    [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
9428 // CHECK6-NEXT:    [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32*
9429 // CHECK6-NEXT:    store i32 [[TMP0]], i32* [[CONV1]], align 4
9430 // CHECK6-NEXT:    [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
9431 // CHECK6-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]])
9432 // CHECK6-NEXT:    ret void
9433 //
9434 //
9435 // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..2
9436 // CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]]) #[[ATTR3]] {
9437 // CHECK6-NEXT:  entry:
9438 // CHECK6-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
9439 // CHECK6-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
9440 // CHECK6-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
9441 // CHECK6-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
9442 // CHECK6-NEXT:    [[TMP:%.*]] = alloca i32, align 4
9443 // CHECK6-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
9444 // CHECK6-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
9445 // CHECK6-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
9446 // CHECK6-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
9447 // CHECK6-NEXT:    [[A1:%.*]] = alloca i32, align 4
9448 // CHECK6-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
9449 // CHECK6-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
9450 // CHECK6-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
9451 // CHECK6-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
9452 // CHECK6-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
9453 // CHECK6-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
9454 // CHECK6-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
9455 // CHECK6-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
9456 // CHECK6-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
9457 // CHECK6-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
9458 // CHECK6-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
9459 // CHECK6-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
9460 // CHECK6-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
9461 // CHECK6-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
9462 // CHECK6:       cond.true:
9463 // CHECK6-NEXT:    br label [[COND_END:%.*]]
9464 // CHECK6:       cond.false:
9465 // CHECK6-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
9466 // CHECK6-NEXT:    br label [[COND_END]]
9467 // CHECK6:       cond.end:
9468 // CHECK6-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
9469 // CHECK6-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
9470 // CHECK6-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
9471 // CHECK6-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
9472 // CHECK6-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
9473 // CHECK6:       omp.inner.for.cond:
9474 // CHECK6-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
9475 // CHECK6-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
9476 // CHECK6-NEXT:    [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
9477 // CHECK6-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
9478 // CHECK6:       omp.inner.for.body:
9479 // CHECK6-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
9480 // CHECK6-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
9481 // CHECK6-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
9482 // CHECK6-NEXT:    store i32 [[ADD]], i32* [[A1]], align 4, !nontemporal !27
9483 // CHECK6-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A1]], align 4, !nontemporal !27
9484 // CHECK6-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
9485 // CHECK6-NEXT:    store i32 [[ADD3]], i32* [[A1]], align 4, !nontemporal !27
9486 // CHECK6-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
9487 // CHECK6:       omp.body.continue:
9488 // CHECK6-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
9489 // CHECK6:       omp.inner.for.inc:
9490 // CHECK6-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
9491 // CHECK6-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP9]], 1
9492 // CHECK6-NEXT:    store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4
9493 // CHECK6-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]]
9494 // CHECK6:       omp.inner.for.end:
9495 // CHECK6-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
9496 // CHECK6:       omp.loop.exit:
9497 // CHECK6-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
9498 // CHECK6-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
9499 // CHECK6-NEXT:    [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0
9500 // CHECK6-NEXT:    br i1 [[TMP11]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
9501 // CHECK6:       .omp.final.then:
9502 // CHECK6-NEXT:    store i32 10, i32* [[CONV]], align 4
9503 // CHECK6-NEXT:    br label [[DOTOMP_FINAL_DONE]]
9504 // CHECK6:       .omp.final.done:
9505 // CHECK6-NEXT:    ret void
9506 //
9507 //
9508 // CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111
9509 // CHECK6-SAME: (i64 noundef [[AA:%.*]]) #[[ATTR2]] {
9510 // CHECK6-NEXT:  entry:
9511 // CHECK6-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
9512 // CHECK6-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
9513 // CHECK6-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
9514 // CHECK6-NEXT:    [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
9515 // CHECK6-NEXT:    [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
9516 // CHECK6-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
9517 // CHECK6-NEXT:    store i16 [[TMP0]], i16* [[CONV1]], align 2
9518 // CHECK6-NEXT:    [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
9519 // CHECK6-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP1]])
9520 // CHECK6-NEXT:    ret void
9521 //
9522 //
9523 // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..3
9524 // CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR3]] {
9525 // CHECK6-NEXT:  entry:
9526 // CHECK6-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
9527 // CHECK6-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
9528 // CHECK6-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
9529 // CHECK6-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
9530 // CHECK6-NEXT:    [[TMP:%.*]] = alloca i32, align 4
9531 // CHECK6-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
9532 // CHECK6-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
9533 // CHECK6-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
9534 // CHECK6-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
9535 // CHECK6-NEXT:    [[I:%.*]] = alloca i32, align 4
9536 // CHECK6-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
9537 // CHECK6-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
9538 // CHECK6-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
9539 // CHECK6-NEXT:    [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
9540 // CHECK6-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
9541 // CHECK6-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
9542 // CHECK6-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
9543 // CHECK6-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
9544 // CHECK6-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
9545 // CHECK6-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
9546 // CHECK6-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
9547 // CHECK6-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
9548 // CHECK6-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
9549 // CHECK6-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
9550 // CHECK6:       cond.true:
9551 // CHECK6-NEXT:    br label [[COND_END:%.*]]
9552 // CHECK6:       cond.false:
9553 // CHECK6-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
9554 // CHECK6-NEXT:    br label [[COND_END]]
9555 // CHECK6:       cond.end:
9556 // CHECK6-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
9557 // CHECK6-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
9558 // CHECK6-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
9559 // CHECK6-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
9560 // CHECK6-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
9561 // CHECK6:       omp.inner.for.cond:
9562 // CHECK6-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30
9563 // CHECK6-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !30
9564 // CHECK6-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
9565 // CHECK6-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
9566 // CHECK6:       omp.inner.for.body:
9567 // CHECK6-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30
9568 // CHECK6-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
9569 // CHECK6-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
9570 // CHECK6-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !30
9571 // CHECK6-NEXT:    [[TMP8:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !30
9572 // CHECK6-NEXT:    [[CONV2:%.*]] = sext i16 [[TMP8]] to i32
9573 // CHECK6-NEXT:    [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
9574 // CHECK6-NEXT:    [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
9575 // CHECK6-NEXT:    store i16 [[CONV4]], i16* [[CONV]], align 2, !llvm.access.group !30
9576 // CHECK6-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
9577 // CHECK6:       omp.body.continue:
9578 // CHECK6-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
9579 // CHECK6:       omp.inner.for.inc:
9580 // CHECK6-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30
9581 // CHECK6-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP9]], 1
9582 // CHECK6-NEXT:    store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30
9583 // CHECK6-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP31:![0-9]+]]
9584 // CHECK6:       omp.inner.for.end:
9585 // CHECK6-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
9586 // CHECK6:       omp.loop.exit:
9587 // CHECK6-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
9588 // CHECK6-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
9589 // CHECK6-NEXT:    [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0
9590 // CHECK6-NEXT:    br i1 [[TMP11]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
9591 // CHECK6:       .omp.final.then:
9592 // CHECK6-NEXT:    store i32 10, i32* [[I]], align 4
9593 // CHECK6-NEXT:    br label [[DOTOMP_FINAL_DONE]]
9594 // CHECK6:       .omp.final.done:
9595 // CHECK6-NEXT:    ret void
9596 //
9597 //
9598 // CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118
9599 // CHECK6-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] {
9600 // CHECK6-NEXT:  entry:
9601 // CHECK6-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
9602 // CHECK6-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
9603 // CHECK6-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
9604 // CHECK6-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
9605 // CHECK6-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
9606 // CHECK6-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
9607 // CHECK6-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
9608 // CHECK6-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
9609 // CHECK6-NEXT:    [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
9610 // CHECK6-NEXT:    [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
9611 // CHECK6-NEXT:    store i32 [[TMP0]], i32* [[CONV2]], align 4
9612 // CHECK6-NEXT:    [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
9613 // CHECK6-NEXT:    [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
9614 // CHECK6-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
9615 // CHECK6-NEXT:    store i16 [[TMP2]], i16* [[CONV3]], align 2
9616 // CHECK6-NEXT:    [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
9617 // CHECK6-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
9618 // CHECK6-NEXT:    ret void
9619 //
9620 //
9621 // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..6
9622 // CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR3]] {
9623 // CHECK6-NEXT:  entry:
9624 // CHECK6-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
9625 // CHECK6-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
9626 // CHECK6-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
9627 // CHECK6-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
9628 // CHECK6-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
9629 // CHECK6-NEXT:    [[TMP:%.*]] = alloca i32, align 4
9630 // CHECK6-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
9631 // CHECK6-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
9632 // CHECK6-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
9633 // CHECK6-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
9634 // CHECK6-NEXT:    [[I:%.*]] = alloca i32, align 4
9635 // CHECK6-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
9636 // CHECK6-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
9637 // CHECK6-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
9638 // CHECK6-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
9639 // CHECK6-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
9640 // CHECK6-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
9641 // CHECK6-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
9642 // CHECK6-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
9643 // CHECK6-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
9644 // CHECK6-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
9645 // CHECK6-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
9646 // CHECK6-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
9647 // CHECK6-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
9648 // CHECK6-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
9649 // CHECK6-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
9650 // CHECK6-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
9651 // CHECK6:       cond.true:
9652 // CHECK6-NEXT:    br label [[COND_END:%.*]]
9653 // CHECK6:       cond.false:
9654 // CHECK6-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
9655 // CHECK6-NEXT:    br label [[COND_END]]
9656 // CHECK6:       cond.end:
9657 // CHECK6-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
9658 // CHECK6-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
9659 // CHECK6-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
9660 // CHECK6-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
9661 // CHECK6-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
9662 // CHECK6:       omp.inner.for.cond:
9663 // CHECK6-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33
9664 // CHECK6-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !33
9665 // CHECK6-NEXT:    [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
9666 // CHECK6-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
9667 // CHECK6:       omp.inner.for.body:
9668 // CHECK6-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33
9669 // CHECK6-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
9670 // CHECK6-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
9671 // CHECK6-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !33
9672 // CHECK6-NEXT:    [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !33
9673 // CHECK6-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
9674 // CHECK6-NEXT:    store i32 [[ADD3]], i32* [[CONV]], align 4, !llvm.access.group !33
9675 // CHECK6-NEXT:    [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 2, !llvm.access.group !33
9676 // CHECK6-NEXT:    [[CONV4:%.*]] = sext i16 [[TMP9]] to i32
9677 // CHECK6-NEXT:    [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
9678 // CHECK6-NEXT:    [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
9679 // CHECK6-NEXT:    store i16 [[CONV6]], i16* [[CONV1]], align 2, !llvm.access.group !33
9680 // CHECK6-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
9681 // CHECK6:       omp.body.continue:
9682 // CHECK6-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
9683 // CHECK6:       omp.inner.for.inc:
9684 // CHECK6-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33
9685 // CHECK6-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1
9686 // CHECK6-NEXT:    store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33
9687 // CHECK6-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP34:![0-9]+]]
9688 // CHECK6:       omp.inner.for.end:
9689 // CHECK6-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
9690 // CHECK6:       omp.loop.exit:
9691 // CHECK6-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
9692 // CHECK6-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
9693 // CHECK6-NEXT:    [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
9694 // CHECK6-NEXT:    br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
9695 // CHECK6:       .omp.final.then:
9696 // CHECK6-NEXT:    store i32 10, i32* [[I]], align 4
9697 // CHECK6-NEXT:    br label [[DOTOMP_FINAL_DONE]]
9698 // CHECK6:       .omp.final.done:
9699 // CHECK6-NEXT:    ret void
9700 //
9701 //
9702 // CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142
9703 // CHECK6-SAME: (i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] {
9704 // CHECK6-NEXT:  entry:
9705 // CHECK6-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
9706 // CHECK6-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
9707 // CHECK6-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
9708 // CHECK6-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 8
9709 // CHECK6-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
9710 // CHECK6-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
9711 // CHECK6-NEXT:    [[VLA_ADDR4:%.*]] = alloca i64, align 8
9712 // CHECK6-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 8
9713 // CHECK6-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
9714 // CHECK6-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
9715 // CHECK6-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
9716 // CHECK6-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
9717 // CHECK6-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
9718 // CHECK6-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 8
9719 // CHECK6-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
9720 // CHECK6-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
9721 // CHECK6-NEXT:    store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
9722 // CHECK6-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 8
9723 // CHECK6-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
9724 // CHECK6-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
9725 // CHECK6-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
9726 // CHECK6-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
9727 // CHECK6-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
9728 // CHECK6-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
9729 // CHECK6-NEXT:    [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
9730 // CHECK6-NEXT:    [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
9731 // CHECK6-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
9732 // CHECK6-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
9733 // CHECK6-NEXT:    [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
9734 // CHECK6-NEXT:    [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
9735 // CHECK6-NEXT:    store i32 [[TMP8]], i32* [[CONV5]], align 4
9736 // CHECK6-NEXT:    [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
9737 // CHECK6-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]])
9738 // CHECK6-NEXT:    ret void
9739 //
9740 //
9741 // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..9
9742 // CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR3]] {
9743 // CHECK6-NEXT:  entry:
9744 // CHECK6-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
9745 // CHECK6-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
9746 // CHECK6-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
9747 // CHECK6-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
9748 // CHECK6-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
9749 // CHECK6-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 8
9750 // CHECK6-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
9751 // CHECK6-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
9752 // CHECK6-NEXT:    [[VLA_ADDR4:%.*]] = alloca i64, align 8
9753 // CHECK6-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 8
9754 // CHECK6-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
9755 // CHECK6-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
9756 // CHECK6-NEXT:    [[TMP:%.*]] = alloca i32, align 4
9757 // CHECK6-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
9758 // CHECK6-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
9759 // CHECK6-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
9760 // CHECK6-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
9761 // CHECK6-NEXT:    [[I:%.*]] = alloca i32, align 4
9762 // CHECK6-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
9763 // CHECK6-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
9764 // CHECK6-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
9765 // CHECK6-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
9766 // CHECK6-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
9767 // CHECK6-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 8
9768 // CHECK6-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
9769 // CHECK6-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
9770 // CHECK6-NEXT:    store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
9771 // CHECK6-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 8
9772 // CHECK6-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
9773 // CHECK6-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
9774 // CHECK6-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
9775 // CHECK6-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
9776 // CHECK6-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
9777 // CHECK6-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
9778 // CHECK6-NEXT:    [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
9779 // CHECK6-NEXT:    [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
9780 // CHECK6-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
9781 // CHECK6-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
9782 // CHECK6-NEXT:    [[ARRAYDECAY:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 0
9783 // CHECK6-NEXT:    call void @llvm.assume(i1 true) [ "align"(float* [[ARRAYDECAY]], i64 16) ]
9784 // CHECK6-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
9785 // CHECK6-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
9786 // CHECK6-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
9787 // CHECK6-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
9788 // CHECK6-NEXT:    [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
9789 // CHECK6-NEXT:    [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4
9790 // CHECK6-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
9791 // CHECK6-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
9792 // CHECK6-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP10]], 9
9793 // CHECK6-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
9794 // CHECK6:       cond.true:
9795 // CHECK6-NEXT:    br label [[COND_END:%.*]]
9796 // CHECK6:       cond.false:
9797 // CHECK6-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
9798 // CHECK6-NEXT:    br label [[COND_END]]
9799 // CHECK6:       cond.end:
9800 // CHECK6-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ]
9801 // CHECK6-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
9802 // CHECK6-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
9803 // CHECK6-NEXT:    store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4
9804 // CHECK6-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
9805 // CHECK6:       omp.inner.for.cond:
9806 // CHECK6-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36
9807 // CHECK6-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !36
9808 // CHECK6-NEXT:    [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
9809 // CHECK6-NEXT:    br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
9810 // CHECK6:       omp.inner.for.body:
9811 // CHECK6-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36
9812 // CHECK6-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1
9813 // CHECK6-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
9814 // CHECK6-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !36
9815 // CHECK6-NEXT:    [[TMP16:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !36
9816 // CHECK6-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP16]], 1
9817 // CHECK6-NEXT:    store i32 [[ADD6]], i32* [[CONV]], align 4, !llvm.access.group !36
9818 // CHECK6-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
9819 // CHECK6-NEXT:    [[TMP17:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !36
9820 // CHECK6-NEXT:    [[CONV7:%.*]] = fpext float [[TMP17]] to double
9821 // CHECK6-NEXT:    [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00
9822 // CHECK6-NEXT:    [[CONV9:%.*]] = fptrunc double [[ADD8]] to float
9823 // CHECK6-NEXT:    store float [[CONV9]], float* [[ARRAYIDX]], align 4, !llvm.access.group !36
9824 // CHECK6-NEXT:    [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3
9825 // CHECK6-NEXT:    [[TMP18:%.*]] = load float, float* [[ARRAYIDX10]], align 4, !llvm.access.group !36
9826 // CHECK6-NEXT:    [[CONV11:%.*]] = fpext float [[TMP18]] to double
9827 // CHECK6-NEXT:    [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00
9828 // CHECK6-NEXT:    [[CONV13:%.*]] = fptrunc double [[ADD12]] to float
9829 // CHECK6-NEXT:    store float [[CONV13]], float* [[ARRAYIDX10]], align 4, !llvm.access.group !36
9830 // CHECK6-NEXT:    [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1
9831 // CHECK6-NEXT:    [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX14]], i64 0, i64 2
9832 // CHECK6-NEXT:    [[TMP19:%.*]] = load double, double* [[ARRAYIDX15]], align 8, !llvm.access.group !36
9833 // CHECK6-NEXT:    [[ADD16:%.*]] = fadd double [[TMP19]], 1.000000e+00
9834 // CHECK6-NEXT:    store double [[ADD16]], double* [[ARRAYIDX15]], align 8, !llvm.access.group !36
9835 // CHECK6-NEXT:    [[TMP20:%.*]] = mul nsw i64 1, [[TMP5]]
9836 // CHECK6-NEXT:    [[ARRAYIDX17:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP20]]
9837 // CHECK6-NEXT:    [[ARRAYIDX18:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX17]], i64 3
9838 // CHECK6-NEXT:    [[TMP21:%.*]] = load double, double* [[ARRAYIDX18]], align 8, !llvm.access.group !36
9839 // CHECK6-NEXT:    [[ADD19:%.*]] = fadd double [[TMP21]], 1.000000e+00
9840 // CHECK6-NEXT:    store double [[ADD19]], double* [[ARRAYIDX18]], align 8, !llvm.access.group !36
9841 // CHECK6-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0
9842 // CHECK6-NEXT:    [[TMP22:%.*]] = load i64, i64* [[X]], align 8, !llvm.access.group !36
9843 // CHECK6-NEXT:    [[ADD20:%.*]] = add nsw i64 [[TMP22]], 1
9844 // CHECK6-NEXT:    store i64 [[ADD20]], i64* [[X]], align 8, !llvm.access.group !36
9845 // CHECK6-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1
9846 // CHECK6-NEXT:    [[TMP23:%.*]] = load i8, i8* [[Y]], align 8, !llvm.access.group !36
9847 // CHECK6-NEXT:    [[CONV21:%.*]] = sext i8 [[TMP23]] to i32
9848 // CHECK6-NEXT:    [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1
9849 // CHECK6-NEXT:    [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8
9850 // CHECK6-NEXT:    store i8 [[CONV23]], i8* [[Y]], align 8, !llvm.access.group !36
9851 // CHECK6-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
9852 // CHECK6:       omp.body.continue:
9853 // CHECK6-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
9854 // CHECK6:       omp.inner.for.inc:
9855 // CHECK6-NEXT:    [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36
9856 // CHECK6-NEXT:    [[ADD24:%.*]] = add nsw i32 [[TMP24]], 1
9857 // CHECK6-NEXT:    store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36
9858 // CHECK6-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP37:![0-9]+]]
9859 // CHECK6:       omp.inner.for.end:
9860 // CHECK6-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
9861 // CHECK6:       omp.loop.exit:
9862 // CHECK6-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]])
9863 // CHECK6-NEXT:    [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
9864 // CHECK6-NEXT:    [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
9865 // CHECK6-NEXT:    br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
9866 // CHECK6:       .omp.final.then:
9867 // CHECK6-NEXT:    store i32 10, i32* [[I]], align 4
9868 // CHECK6-NEXT:    br label [[DOTOMP_FINAL_DONE]]
9869 // CHECK6:       .omp.final.done:
9870 // CHECK6-NEXT:    ret void
9871 //
9872 //
9873 // CHECK6-LABEL: define {{[^@]+}}@_Z3bari
9874 // CHECK6-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {
9875 // CHECK6-NEXT:  entry:
9876 // CHECK6-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
9877 // CHECK6-NEXT:    [[A:%.*]] = alloca i32, align 4
9878 // CHECK6-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8
9879 // CHECK6-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
9880 // CHECK6-NEXT:    store i32 0, i32* [[A]], align 4
9881 // CHECK6-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
9882 // CHECK6-NEXT:    [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]])
9883 // CHECK6-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
9884 // CHECK6-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
9885 // CHECK6-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
9886 // CHECK6-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
9887 // CHECK6-NEXT:    [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP2]])
9888 // CHECK6-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
9889 // CHECK6-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
9890 // CHECK6-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
9891 // CHECK6-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
9892 // CHECK6-NEXT:    [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]])
9893 // CHECK6-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
9894 // CHECK6-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
9895 // CHECK6-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
9896 // CHECK6-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
9897 // CHECK6-NEXT:    [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]])
9898 // CHECK6-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
9899 // CHECK6-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
9900 // CHECK6-NEXT:    store i32 [[ADD6]], i32* [[A]], align 4
9901 // CHECK6-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
9902 // CHECK6-NEXT:    ret i32 [[TMP8]]
9903 //
9904 //
9905 // CHECK6-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
9906 // CHECK6-SAME: (%struct.S1* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 {
9907 // CHECK6-NEXT:  entry:
9908 // CHECK6-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
9909 // CHECK6-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
9910 // CHECK6-NEXT:    [[B:%.*]] = alloca i32, align 4
9911 // CHECK6-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 8
9912 // CHECK6-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
9913 // CHECK6-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
9914 // CHECK6-NEXT:    [[B_CASTED:%.*]] = alloca i64, align 8
9915 // CHECK6-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
9916 // CHECK6-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [6 x i8*], align 8
9917 // CHECK6-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [6 x i8*], align 8
9918 // CHECK6-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [6 x i8*], align 8
9919 // CHECK6-NEXT:    [[DOTOFFLOAD_SIZES:%.*]] = alloca [6 x i64], align 8
9920 // CHECK6-NEXT:    [[TMP:%.*]] = alloca i32, align 4
9921 // CHECK6-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
9922 // CHECK6-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
9923 // CHECK6-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
9924 // CHECK6-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
9925 // CHECK6-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
9926 // CHECK6-NEXT:    store i32 [[ADD]], i32* [[B]], align 4
9927 // CHECK6-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
9928 // CHECK6-NEXT:    [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
9929 // CHECK6-NEXT:    [[TMP3:%.*]] = call i8* @llvm.stacksave()
9930 // CHECK6-NEXT:    store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8
9931 // CHECK6-NEXT:    [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]
9932 // CHECK6-NEXT:    [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2
9933 // CHECK6-NEXT:    store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8
9934 // CHECK6-NEXT:    [[TMP5:%.*]] = load i32, i32* [[N_ADDR]], align 4
9935 // CHECK6-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 60
9936 // CHECK6-NEXT:    [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8
9937 // CHECK6-NEXT:    store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
9938 // CHECK6-NEXT:    [[TMP6:%.*]] = load i32, i32* [[B]], align 4
9939 // CHECK6-NEXT:    [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32*
9940 // CHECK6-NEXT:    store i32 [[TMP6]], i32* [[CONV]], align 4
9941 // CHECK6-NEXT:    [[TMP7:%.*]] = load i64, i64* [[B_CASTED]], align 8
9942 // CHECK6-NEXT:    [[TMP8:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
9943 // CHECK6-NEXT:    [[TOBOOL:%.*]] = trunc i8 [[TMP8]] to i1
9944 // CHECK6-NEXT:    [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
9945 // CHECK6-NEXT:    [[FROMBOOL3:%.*]] = zext i1 [[TOBOOL]] to i8
9946 // CHECK6-NEXT:    store i8 [[FROMBOOL3]], i8* [[CONV2]], align 1
9947 // CHECK6-NEXT:    [[TMP9:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
9948 // CHECK6-NEXT:    [[TMP10:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
9949 // CHECK6-NEXT:    [[TOBOOL4:%.*]] = trunc i8 [[TMP10]] to i1
9950 // CHECK6-NEXT:    br i1 [[TOBOOL4]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
9951 // CHECK6:       omp_if.then:
9952 // CHECK6-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
9953 // CHECK6-NEXT:    [[TMP11:%.*]] = mul nuw i64 2, [[TMP2]]
9954 // CHECK6-NEXT:    [[TMP12:%.*]] = mul nuw i64 [[TMP11]], 2
9955 // CHECK6-NEXT:    [[TMP13:%.*]] = bitcast [6 x i64]* [[DOTOFFLOAD_SIZES]] to i8*
9956 // CHECK6-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP13]], i8* align 8 bitcast ([6 x i64]* @.offload_sizes.13 to i8*), i64 48, i1 false)
9957 // CHECK6-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
9958 // CHECK6-NEXT:    [[TMP15:%.*]] = bitcast i8** [[TMP14]] to %struct.S1**
9959 // CHECK6-NEXT:    store %struct.S1* [[THIS1]], %struct.S1** [[TMP15]], align 8
9960 // CHECK6-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
9961 // CHECK6-NEXT:    [[TMP17:%.*]] = bitcast i8** [[TMP16]] to double**
9962 // CHECK6-NEXT:    store double* [[A]], double** [[TMP17]], align 8
9963 // CHECK6-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
9964 // CHECK6-NEXT:    store i8* null, i8** [[TMP18]], align 8
9965 // CHECK6-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
9966 // CHECK6-NEXT:    [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64*
9967 // CHECK6-NEXT:    store i64 [[TMP7]], i64* [[TMP20]], align 8
9968 // CHECK6-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
9969 // CHECK6-NEXT:    [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i64*
9970 // CHECK6-NEXT:    store i64 [[TMP7]], i64* [[TMP22]], align 8
9971 // CHECK6-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
9972 // CHECK6-NEXT:    store i8* null, i8** [[TMP23]], align 8
9973 // CHECK6-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
9974 // CHECK6-NEXT:    [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i64*
9975 // CHECK6-NEXT:    store i64 2, i64* [[TMP25]], align 8
9976 // CHECK6-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
9977 // CHECK6-NEXT:    [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64*
9978 // CHECK6-NEXT:    store i64 2, i64* [[TMP27]], align 8
9979 // CHECK6-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
9980 // CHECK6-NEXT:    store i8* null, i8** [[TMP28]], align 8
9981 // CHECK6-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
9982 // CHECK6-NEXT:    [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i64*
9983 // CHECK6-NEXT:    store i64 [[TMP2]], i64* [[TMP30]], align 8
9984 // CHECK6-NEXT:    [[TMP31:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
9985 // CHECK6-NEXT:    [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i64*
9986 // CHECK6-NEXT:    store i64 [[TMP2]], i64* [[TMP32]], align 8
9987 // CHECK6-NEXT:    [[TMP33:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
9988 // CHECK6-NEXT:    store i8* null, i8** [[TMP33]], align 8
9989 // CHECK6-NEXT:    [[TMP34:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
9990 // CHECK6-NEXT:    [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i16**
9991 // CHECK6-NEXT:    store i16* [[VLA]], i16** [[TMP35]], align 8
9992 // CHECK6-NEXT:    [[TMP36:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
9993 // CHECK6-NEXT:    [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i16**
9994 // CHECK6-NEXT:    store i16* [[VLA]], i16** [[TMP37]], align 8
9995 // CHECK6-NEXT:    [[TMP38:%.*]] = getelementptr inbounds [6 x i64], [6 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4
9996 // CHECK6-NEXT:    store i64 [[TMP12]], i64* [[TMP38]], align 8
9997 // CHECK6-NEXT:    [[TMP39:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4
9998 // CHECK6-NEXT:    store i8* null, i8** [[TMP39]], align 8
9999 // CHECK6-NEXT:    [[TMP40:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 5
10000 // CHECK6-NEXT:    [[TMP41:%.*]] = bitcast i8** [[TMP40]] to i64*
10001 // CHECK6-NEXT:    store i64 [[TMP9]], i64* [[TMP41]], align 8
10002 // CHECK6-NEXT:    [[TMP42:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 5
10003 // CHECK6-NEXT:    [[TMP43:%.*]] = bitcast i8** [[TMP42]] to i64*
10004 // CHECK6-NEXT:    store i64 [[TMP9]], i64* [[TMP43]], align 8
10005 // CHECK6-NEXT:    [[TMP44:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 5
10006 // CHECK6-NEXT:    store i8* null, i8** [[TMP44]], align 8
10007 // CHECK6-NEXT:    [[TMP45:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
10008 // CHECK6-NEXT:    [[TMP46:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
10009 // CHECK6-NEXT:    [[TMP47:%.*]] = getelementptr inbounds [6 x i64], [6 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
10010 // CHECK6-NEXT:    call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10)
10011 // CHECK6-NEXT:    [[TMP48:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215.region_id, i32 6, i8** [[TMP45]], i8** [[TMP46]], i64* [[TMP47]], i64* getelementptr inbounds ([6 x i64], [6 x i64]* @.offload_maptypes.14, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1)
10012 // CHECK6-NEXT:    [[TMP49:%.*]] = icmp ne i32 [[TMP48]], 0
10013 // CHECK6-NEXT:    br i1 [[TMP49]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
10014 // CHECK6:       omp_offload.failed:
10015 // CHECK6-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215(%struct.S1* [[THIS1]], i64 [[TMP7]], i64 2, i64 [[TMP2]], i16* [[VLA]], i64 [[TMP9]]) #[[ATTR4]]
10016 // CHECK6-NEXT:    br label [[OMP_OFFLOAD_CONT]]
10017 // CHECK6:       omp_offload.cont:
10018 // CHECK6-NEXT:    br label [[OMP_IF_END:%.*]]
10019 // CHECK6:       omp_if.else:
10020 // CHECK6-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215(%struct.S1* [[THIS1]], i64 [[TMP7]], i64 2, i64 [[TMP2]], i16* [[VLA]], i64 [[TMP9]]) #[[ATTR4]]
10021 // CHECK6-NEXT:    br label [[OMP_IF_END]]
10022 // CHECK6:       omp_if.end:
10023 // CHECK6-NEXT:    [[TMP50:%.*]] = mul nsw i64 1, [[TMP2]]
10024 // CHECK6-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP50]]
10025 // CHECK6-NEXT:    [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
10026 // CHECK6-NEXT:    [[TMP51:%.*]] = load i16, i16* [[ARRAYIDX5]], align 2
10027 // CHECK6-NEXT:    [[CONV6:%.*]] = sext i16 [[TMP51]] to i32
10028 // CHECK6-NEXT:    [[TMP52:%.*]] = load i32, i32* [[B]], align 4
10029 // CHECK6-NEXT:    [[ADD7:%.*]] = add nsw i32 [[CONV6]], [[TMP52]]
10030 // CHECK6-NEXT:    [[TMP53:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
10031 // CHECK6-NEXT:    call void @llvm.stackrestore(i8* [[TMP53]])
10032 // CHECK6-NEXT:    ret i32 [[ADD7]]
10033 //
10034 //
10035 // CHECK6-LABEL: define {{[^@]+}}@_ZL7fstatici
10036 // CHECK6-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {
10037 // CHECK6-NEXT:  entry:
10038 // CHECK6-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
10039 // CHECK6-NEXT:    [[A:%.*]] = alloca i32, align 4
10040 // CHECK6-NEXT:    [[AA:%.*]] = alloca i16, align 2
10041 // CHECK6-NEXT:    [[AAA:%.*]] = alloca i8, align 1
10042 // CHECK6-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
10043 // CHECK6-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
10044 // CHECK6-NEXT:    [[N_CASTED:%.*]] = alloca i64, align 8
10045 // CHECK6-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
10046 // CHECK6-NEXT:    [[AAA_CASTED:%.*]] = alloca i64, align 8
10047 // CHECK6-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8
10048 // CHECK6-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8
10049 // CHECK6-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8
10050 // CHECK6-NEXT:    [[TMP:%.*]] = alloca i32, align 4
10051 // CHECK6-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
10052 // CHECK6-NEXT:    [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4
10053 // CHECK6-NEXT:    [[DOTCAPTURE_EXPR_5:%.*]] = alloca i32, align 4
10054 // CHECK6-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
10055 // CHECK6-NEXT:    store i32 0, i32* [[A]], align 4
10056 // CHECK6-NEXT:    store i16 0, i16* [[AA]], align 2
10057 // CHECK6-NEXT:    store i8 0, i8* [[AAA]], align 1
10058 // CHECK6-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
10059 // CHECK6-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32*
10060 // CHECK6-NEXT:    store i32 [[TMP0]], i32* [[CONV]], align 4
10061 // CHECK6-NEXT:    [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
10062 // CHECK6-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
10063 // CHECK6-NEXT:    [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32*
10064 // CHECK6-NEXT:    store i32 [[TMP2]], i32* [[CONV1]], align 4
10065 // CHECK6-NEXT:    [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8
10066 // CHECK6-NEXT:    [[TMP4:%.*]] = load i16, i16* [[AA]], align 2
10067 // CHECK6-NEXT:    [[CONV2:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
10068 // CHECK6-NEXT:    store i16 [[TMP4]], i16* [[CONV2]], align 2
10069 // CHECK6-NEXT:    [[TMP5:%.*]] = load i64, i64* [[AA_CASTED]], align 8
10070 // CHECK6-NEXT:    [[TMP6:%.*]] = load i8, i8* [[AAA]], align 1
10071 // CHECK6-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
10072 // CHECK6-NEXT:    store i8 [[TMP6]], i8* [[CONV3]], align 1
10073 // CHECK6-NEXT:    [[TMP7:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
10074 // CHECK6-NEXT:    [[TMP8:%.*]] = load i32, i32* [[N_ADDR]], align 4
10075 // CHECK6-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP8]], 50
10076 // CHECK6-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
10077 // CHECK6:       omp_if.then:
10078 // CHECK6-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
10079 // CHECK6-NEXT:    [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64*
10080 // CHECK6-NEXT:    store i64 [[TMP1]], i64* [[TMP10]], align 8
10081 // CHECK6-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
10082 // CHECK6-NEXT:    [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64*
10083 // CHECK6-NEXT:    store i64 [[TMP1]], i64* [[TMP12]], align 8
10084 // CHECK6-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
10085 // CHECK6-NEXT:    store i8* null, i8** [[TMP13]], align 8
10086 // CHECK6-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
10087 // CHECK6-NEXT:    [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64*
10088 // CHECK6-NEXT:    store i64 [[TMP3]], i64* [[TMP15]], align 8
10089 // CHECK6-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
10090 // CHECK6-NEXT:    [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64*
10091 // CHECK6-NEXT:    store i64 [[TMP3]], i64* [[TMP17]], align 8
10092 // CHECK6-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
10093 // CHECK6-NEXT:    store i8* null, i8** [[TMP18]], align 8
10094 // CHECK6-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
10095 // CHECK6-NEXT:    [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64*
10096 // CHECK6-NEXT:    store i64 [[TMP5]], i64* [[TMP20]], align 8
10097 // CHECK6-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
10098 // CHECK6-NEXT:    [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i64*
10099 // CHECK6-NEXT:    store i64 [[TMP5]], i64* [[TMP22]], align 8
10100 // CHECK6-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
10101 // CHECK6-NEXT:    store i8* null, i8** [[TMP23]], align 8
10102 // CHECK6-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
10103 // CHECK6-NEXT:    [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i64*
10104 // CHECK6-NEXT:    store i64 [[TMP7]], i64* [[TMP25]], align 8
10105 // CHECK6-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
10106 // CHECK6-NEXT:    [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64*
10107 // CHECK6-NEXT:    store i64 [[TMP7]], i64* [[TMP27]], align 8
10108 // CHECK6-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
10109 // CHECK6-NEXT:    store i8* null, i8** [[TMP28]], align 8
10110 // CHECK6-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
10111 // CHECK6-NEXT:    [[TMP30:%.*]] = bitcast i8** [[TMP29]] to [10 x i32]**
10112 // CHECK6-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP30]], align 8
10113 // CHECK6-NEXT:    [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
10114 // CHECK6-NEXT:    [[TMP32:%.*]] = bitcast i8** [[TMP31]] to [10 x i32]**
10115 // CHECK6-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP32]], align 8
10116 // CHECK6-NEXT:    [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4
10117 // CHECK6-NEXT:    store i8* null, i8** [[TMP33]], align 8
10118 // CHECK6-NEXT:    [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
10119 // CHECK6-NEXT:    [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
10120 // CHECK6-NEXT:    [[TMP36:%.*]] = load i32, i32* [[A]], align 4
10121 // CHECK6-NEXT:    store i32 [[TMP36]], i32* [[DOTCAPTURE_EXPR_]], align 4
10122 // CHECK6-NEXT:    [[TMP37:%.*]] = load i32, i32* [[N_ADDR]], align 4
10123 // CHECK6-NEXT:    store i32 [[TMP37]], i32* [[DOTCAPTURE_EXPR_4]], align 4
10124 // CHECK6-NEXT:    [[TMP38:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4
10125 // CHECK6-NEXT:    [[TMP39:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
10126 // CHECK6-NEXT:    [[SUB:%.*]] = sub i32 [[TMP38]], [[TMP39]]
10127 // CHECK6-NEXT:    [[SUB6:%.*]] = sub i32 [[SUB]], 1
10128 // CHECK6-NEXT:    [[ADD:%.*]] = add i32 [[SUB6]], 1
10129 // CHECK6-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], 1
10130 // CHECK6-NEXT:    [[SUB7:%.*]] = sub i32 [[DIV]], 1
10131 // CHECK6-NEXT:    store i32 [[SUB7]], i32* [[DOTCAPTURE_EXPR_5]], align 4
10132 // CHECK6-NEXT:    [[TMP40:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4
10133 // CHECK6-NEXT:    [[ADD8:%.*]] = add i32 [[TMP40]], 1
10134 // CHECK6-NEXT:    [[TMP41:%.*]] = zext i32 [[ADD8]] to i64
10135 // CHECK6-NEXT:    call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 [[TMP41]])
10136 // CHECK6-NEXT:    [[TMP42:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197.region_id, i32 5, i8** [[TMP34]], i8** [[TMP35]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes.16, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.17, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1)
10137 // CHECK6-NEXT:    [[TMP43:%.*]] = icmp ne i32 [[TMP42]], 0
10138 // CHECK6-NEXT:    br i1 [[TMP43]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
10139 // CHECK6:       omp_offload.failed:
10140 // CHECK6-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], i64 [[TMP7]], [10 x i32]* [[B]]) #[[ATTR4]]
10141 // CHECK6-NEXT:    br label [[OMP_OFFLOAD_CONT]]
10142 // CHECK6:       omp_offload.cont:
10143 // CHECK6-NEXT:    br label [[OMP_IF_END:%.*]]
10144 // CHECK6:       omp_if.else:
10145 // CHECK6-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], i64 [[TMP7]], [10 x i32]* [[B]]) #[[ATTR4]]
10146 // CHECK6-NEXT:    br label [[OMP_IF_END]]
10147 // CHECK6:       omp_if.end:
10148 // CHECK6-NEXT:    [[TMP44:%.*]] = load i32, i32* [[A]], align 4
10149 // CHECK6-NEXT:    ret i32 [[TMP44]]
10150 //
10151 //
10152 // CHECK6-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
10153 // CHECK6-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat {
10154 // CHECK6-NEXT:  entry:
10155 // CHECK6-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
10156 // CHECK6-NEXT:    [[A:%.*]] = alloca i32, align 4
10157 // CHECK6-NEXT:    [[AA:%.*]] = alloca i16, align 2
10158 // CHECK6-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
10159 // CHECK6-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
10160 // CHECK6-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
10161 // CHECK6-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8
10162 // CHECK6-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8
10163 // CHECK6-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8
10164 // CHECK6-NEXT:    [[TMP:%.*]] = alloca i32, align 4
10165 // CHECK6-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
10166 // CHECK6-NEXT:    store i32 0, i32* [[A]], align 4
10167 // CHECK6-NEXT:    store i16 0, i16* [[AA]], align 2
10168 // CHECK6-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
10169 // CHECK6-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32*
10170 // CHECK6-NEXT:    store i32 [[TMP0]], i32* [[CONV]], align 4
10171 // CHECK6-NEXT:    [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
10172 // CHECK6-NEXT:    [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
10173 // CHECK6-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
10174 // CHECK6-NEXT:    store i16 [[TMP2]], i16* [[CONV1]], align 2
10175 // CHECK6-NEXT:    [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
10176 // CHECK6-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
10177 // CHECK6-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40
10178 // CHECK6-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
10179 // CHECK6:       omp_if.then:
10180 // CHECK6-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
10181 // CHECK6-NEXT:    [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64*
10182 // CHECK6-NEXT:    store i64 [[TMP1]], i64* [[TMP6]], align 8
10183 // CHECK6-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
10184 // CHECK6-NEXT:    [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64*
10185 // CHECK6-NEXT:    store i64 [[TMP1]], i64* [[TMP8]], align 8
10186 // CHECK6-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
10187 // CHECK6-NEXT:    store i8* null, i8** [[TMP9]], align 8
10188 // CHECK6-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
10189 // CHECK6-NEXT:    [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i64*
10190 // CHECK6-NEXT:    store i64 [[TMP3]], i64* [[TMP11]], align 8
10191 // CHECK6-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
10192 // CHECK6-NEXT:    [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64*
10193 // CHECK6-NEXT:    store i64 [[TMP3]], i64* [[TMP13]], align 8
10194 // CHECK6-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
10195 // CHECK6-NEXT:    store i8* null, i8** [[TMP14]], align 8
10196 // CHECK6-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
10197 // CHECK6-NEXT:    [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]**
10198 // CHECK6-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 8
10199 // CHECK6-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
10200 // CHECK6-NEXT:    [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]**
10201 // CHECK6-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 8
10202 // CHECK6-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
10203 // CHECK6-NEXT:    store i8* null, i8** [[TMP19]], align 8
10204 // CHECK6-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
10205 // CHECK6-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
10206 // CHECK6-NEXT:    call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10)
10207 // CHECK6-NEXT:    [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.19, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.20, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1)
10208 // CHECK6-NEXT:    [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0
10209 // CHECK6-NEXT:    br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
10210 // CHECK6:       omp_offload.failed:
10211 // CHECK6-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]]
10212 // CHECK6-NEXT:    br label [[OMP_OFFLOAD_CONT]]
10213 // CHECK6:       omp_offload.cont:
10214 // CHECK6-NEXT:    br label [[OMP_IF_END:%.*]]
10215 // CHECK6:       omp_if.else:
10216 // CHECK6-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]]
10217 // CHECK6-NEXT:    br label [[OMP_IF_END]]
10218 // CHECK6:       omp_if.end:
10219 // CHECK6-NEXT:    [[TMP24:%.*]] = load i32, i32* [[A]], align 4
10220 // CHECK6-NEXT:    ret i32 [[TMP24]]
10221 //
10222 //
10223 // CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215
10224 // CHECK6-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] {
10225 // CHECK6-NEXT:  entry:
10226 // CHECK6-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
10227 // CHECK6-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
10228 // CHECK6-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
10229 // CHECK6-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
10230 // CHECK6-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 8
10231 // CHECK6-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
10232 // CHECK6-NEXT:    [[B_CASTED:%.*]] = alloca i64, align 8
10233 // CHECK6-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
10234 // CHECK6-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
10235 // CHECK6-NEXT:    store i64 [[B]], i64* [[B_ADDR]], align 8
10236 // CHECK6-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
10237 // CHECK6-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
10238 // CHECK6-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 8
10239 // CHECK6-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
10240 // CHECK6-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
10241 // CHECK6-NEXT:    [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
10242 // CHECK6-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
10243 // CHECK6-NEXT:    [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
10244 // CHECK6-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
10245 // CHECK6-NEXT:    [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
10246 // CHECK6-NEXT:    [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
10247 // CHECK6-NEXT:    [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i32*
10248 // CHECK6-NEXT:    store i32 [[TMP4]], i32* [[CONV4]], align 4
10249 // CHECK6-NEXT:    [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
10250 // CHECK6-NEXT:    [[TMP6:%.*]] = load i8, i8* [[CONV3]], align 1
10251 // CHECK6-NEXT:    [[TOBOOL:%.*]] = trunc i8 [[TMP6]] to i1
10252 // CHECK6-NEXT:    [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
10253 // CHECK6-NEXT:    [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
10254 // CHECK6-NEXT:    store i8 [[FROMBOOL]], i8* [[CONV5]], align 1
10255 // CHECK6-NEXT:    [[TMP7:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
10256 // CHECK6-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*, i64)* @.omp_outlined..12 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]], i64 [[TMP7]])
10257 // CHECK6-NEXT:    ret void
10258 //
10259 //
10260 // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..12
10261 // CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] {
10262 // CHECK6-NEXT:  entry:
10263 // CHECK6-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
10264 // CHECK6-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
10265 // CHECK6-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
10266 // CHECK6-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
10267 // CHECK6-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
10268 // CHECK6-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
10269 // CHECK6-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 8
10270 // CHECK6-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
10271 // CHECK6-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
10272 // CHECK6-NEXT:    [[TMP:%.*]] = alloca i32, align 4
10273 // CHECK6-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
10274 // CHECK6-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
10275 // CHECK6-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
10276 // CHECK6-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
10277 // CHECK6-NEXT:    [[I:%.*]] = alloca i32, align 4
10278 // CHECK6-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
10279 // CHECK6-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
10280 // CHECK6-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
10281 // CHECK6-NEXT:    store i64 [[B]], i64* [[B_ADDR]], align 8
10282 // CHECK6-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
10283 // CHECK6-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
10284 // CHECK6-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 8
10285 // CHECK6-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
10286 // CHECK6-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
10287 // CHECK6-NEXT:    [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
10288 // CHECK6-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
10289 // CHECK6-NEXT:    [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
10290 // CHECK6-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
10291 // CHECK6-NEXT:    [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
10292 // CHECK6-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
10293 // CHECK6-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
10294 // CHECK6-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
10295 // CHECK6-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
10296 // CHECK6-NEXT:    [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
10297 // CHECK6-NEXT:    [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
10298 // CHECK6-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
10299 // CHECK6-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
10300 // CHECK6-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 9
10301 // CHECK6-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
10302 // CHECK6:       cond.true:
10303 // CHECK6-NEXT:    br label [[COND_END:%.*]]
10304 // CHECK6:       cond.false:
10305 // CHECK6-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
10306 // CHECK6-NEXT:    br label [[COND_END]]
10307 // CHECK6:       cond.end:
10308 // CHECK6-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
10309 // CHECK6-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
10310 // CHECK6-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
10311 // CHECK6-NEXT:    store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
10312 // CHECK6-NEXT:    [[TMP9:%.*]] = load i8, i8* [[CONV3]], align 1
10313 // CHECK6-NEXT:    [[TOBOOL:%.*]] = trunc i8 [[TMP9]] to i1
10314 // CHECK6-NEXT:    br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
10315 // CHECK6:       omp_if.then:
10316 // CHECK6-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
10317 // CHECK6:       omp.inner.for.cond:
10318 // CHECK6-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39
10319 // CHECK6-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !39
10320 // CHECK6-NEXT:    [[CMP4:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]
10321 // CHECK6-NEXT:    br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
10322 // CHECK6:       omp.inner.for.body:
10323 // CHECK6-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39
10324 // CHECK6-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1
10325 // CHECK6-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
10326 // CHECK6-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !39
10327 // CHECK6-NEXT:    [[TMP13:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !39
10328 // CHECK6-NEXT:    [[CONV5:%.*]] = sitofp i32 [[TMP13]] to double
10329 // CHECK6-NEXT:    [[ADD6:%.*]] = fadd double [[CONV5]], 1.500000e+00
10330 // CHECK6-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
10331 // CHECK6-NEXT:    store double [[ADD6]], double* [[A]], align 8, !llvm.access.group !39
10332 // CHECK6-NEXT:    [[A7:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
10333 // CHECK6-NEXT:    [[TMP14:%.*]] = load double, double* [[A7]], align 8, !llvm.access.group !39
10334 // CHECK6-NEXT:    [[INC:%.*]] = fadd double [[TMP14]], 1.000000e+00
10335 // CHECK6-NEXT:    store double [[INC]], double* [[A7]], align 8, !llvm.access.group !39
10336 // CHECK6-NEXT:    [[CONV8:%.*]] = fptosi double [[INC]] to i16
10337 // CHECK6-NEXT:    [[TMP15:%.*]] = mul nsw i64 1, [[TMP2]]
10338 // CHECK6-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP15]]
10339 // CHECK6-NEXT:    [[ARRAYIDX9:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
10340 // CHECK6-NEXT:    store i16 [[CONV8]], i16* [[ARRAYIDX9]], align 2, !llvm.access.group !39
10341 // CHECK6-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
10342 // CHECK6:       omp.body.continue:
10343 // CHECK6-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
10344 // CHECK6:       omp.inner.for.inc:
10345 // CHECK6-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39
10346 // CHECK6-NEXT:    [[ADD10:%.*]] = add nsw i32 [[TMP16]], 1
10347 // CHECK6-NEXT:    store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39
10348 // CHECK6-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP40:![0-9]+]]
10349 // CHECK6:       omp.inner.for.end:
10350 // CHECK6-NEXT:    br label [[OMP_IF_END:%.*]]
10351 // CHECK6:       omp_if.else:
10352 // CHECK6-NEXT:    br label [[OMP_INNER_FOR_COND11:%.*]]
10353 // CHECK6:       omp.inner.for.cond11:
10354 // CHECK6-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
10355 // CHECK6-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
10356 // CHECK6-NEXT:    [[CMP12:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]]
10357 // CHECK6-NEXT:    br i1 [[CMP12]], label [[OMP_INNER_FOR_BODY13:%.*]], label [[OMP_INNER_FOR_END27:%.*]]
10358 // CHECK6:       omp.inner.for.body13:
10359 // CHECK6-NEXT:    [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
10360 // CHECK6-NEXT:    [[MUL14:%.*]] = mul nsw i32 [[TMP19]], 1
10361 // CHECK6-NEXT:    [[ADD15:%.*]] = add nsw i32 0, [[MUL14]]
10362 // CHECK6-NEXT:    store i32 [[ADD15]], i32* [[I]], align 4
10363 // CHECK6-NEXT:    [[TMP20:%.*]] = load i32, i32* [[CONV]], align 4
10364 // CHECK6-NEXT:    [[CONV16:%.*]] = sitofp i32 [[TMP20]] to double
10365 // CHECK6-NEXT:    [[ADD17:%.*]] = fadd double [[CONV16]], 1.500000e+00
10366 // CHECK6-NEXT:    [[A18:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
10367 // CHECK6-NEXT:    store double [[ADD17]], double* [[A18]], align 8
10368 // CHECK6-NEXT:    [[A19:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
10369 // CHECK6-NEXT:    [[TMP21:%.*]] = load double, double* [[A19]], align 8
10370 // CHECK6-NEXT:    [[INC20:%.*]] = fadd double [[TMP21]], 1.000000e+00
10371 // CHECK6-NEXT:    store double [[INC20]], double* [[A19]], align 8
10372 // CHECK6-NEXT:    [[CONV21:%.*]] = fptosi double [[INC20]] to i16
10373 // CHECK6-NEXT:    [[TMP22:%.*]] = mul nsw i64 1, [[TMP2]]
10374 // CHECK6-NEXT:    [[ARRAYIDX22:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP22]]
10375 // CHECK6-NEXT:    [[ARRAYIDX23:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX22]], i64 1
10376 // CHECK6-NEXT:    store i16 [[CONV21]], i16* [[ARRAYIDX23]], align 2
10377 // CHECK6-NEXT:    br label [[OMP_BODY_CONTINUE24:%.*]]
10378 // CHECK6:       omp.body.continue24:
10379 // CHECK6-NEXT:    br label [[OMP_INNER_FOR_INC25:%.*]]
10380 // CHECK6:       omp.inner.for.inc25:
10381 // CHECK6-NEXT:    [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
10382 // CHECK6-NEXT:    [[ADD26:%.*]] = add nsw i32 [[TMP23]], 1
10383 // CHECK6-NEXT:    store i32 [[ADD26]], i32* [[DOTOMP_IV]], align 4
10384 // CHECK6-NEXT:    br label [[OMP_INNER_FOR_COND11]], !llvm.loop [[LOOP42:![0-9]+]]
10385 // CHECK6:       omp.inner.for.end27:
10386 // CHECK6-NEXT:    br label [[OMP_IF_END]]
10387 // CHECK6:       omp_if.end:
10388 // CHECK6-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
10389 // CHECK6:       omp.loop.exit:
10390 // CHECK6-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
10391 // CHECK6-NEXT:    [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
10392 // CHECK6-NEXT:    [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0
10393 // CHECK6-NEXT:    br i1 [[TMP25]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
10394 // CHECK6:       .omp.final.then:
10395 // CHECK6-NEXT:    store i32 10, i32* [[I]], align 4
10396 // CHECK6-NEXT:    br label [[DOTOMP_FINAL_DONE]]
10397 // CHECK6:       .omp.final.done:
10398 // CHECK6-NEXT:    ret void
10399 //
10400 //
10401 // CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197
10402 // CHECK6-SAME: (i64 noundef [[A:%.*]], i64 noundef [[N:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
10403 // CHECK6-NEXT:  entry:
10404 // CHECK6-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
10405 // CHECK6-NEXT:    [[N_ADDR:%.*]] = alloca i64, align 8
10406 // CHECK6-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
10407 // CHECK6-NEXT:    [[AAA_ADDR:%.*]] = alloca i64, align 8
10408 // CHECK6-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
10409 // CHECK6-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
10410 // CHECK6-NEXT:    [[N_CASTED:%.*]] = alloca i64, align 8
10411 // CHECK6-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
10412 // CHECK6-NEXT:    [[AAA_CASTED:%.*]] = alloca i64, align 8
10413 // CHECK6-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
10414 // CHECK6-NEXT:    store i64 [[N]], i64* [[N_ADDR]], align 8
10415 // CHECK6-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
10416 // CHECK6-NEXT:    store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
10417 // CHECK6-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
10418 // CHECK6-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
10419 // CHECK6-NEXT:    [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32*
10420 // CHECK6-NEXT:    [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
10421 // CHECK6-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
10422 // CHECK6-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
10423 // CHECK6-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
10424 // CHECK6-NEXT:    [[CONV4:%.*]] = bitcast i64* [[A_CASTED]] to i32*
10425 // CHECK6-NEXT:    store i32 [[TMP1]], i32* [[CONV4]], align 4
10426 // CHECK6-NEXT:    [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
10427 // CHECK6-NEXT:    [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 4
10428 // CHECK6-NEXT:    [[CONV5:%.*]] = bitcast i64* [[N_CASTED]] to i32*
10429 // CHECK6-NEXT:    store i32 [[TMP3]], i32* [[CONV5]], align 4
10430 // CHECK6-NEXT:    [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8
10431 // CHECK6-NEXT:    [[TMP5:%.*]] = load i16, i16* [[CONV2]], align 2
10432 // CHECK6-NEXT:    [[CONV6:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
10433 // CHECK6-NEXT:    store i16 [[TMP5]], i16* [[CONV6]], align 2
10434 // CHECK6-NEXT:    [[TMP6:%.*]] = load i64, i64* [[AA_CASTED]], align 8
10435 // CHECK6-NEXT:    [[TMP7:%.*]] = load i8, i8* [[CONV3]], align 1
10436 // CHECK6-NEXT:    [[CONV7:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
10437 // CHECK6-NEXT:    store i8 [[TMP7]], i8* [[CONV7]], align 1
10438 // CHECK6-NEXT:    [[TMP8:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
10439 // CHECK6-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, [10 x i32]*)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]], [10 x i32]* [[TMP0]])
10440 // CHECK6-NEXT:    ret void
10441 //
10442 //
10443 // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..15
10444 // CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[N:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] {
10445 // CHECK6-NEXT:  entry:
10446 // CHECK6-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
10447 // CHECK6-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
10448 // CHECK6-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
10449 // CHECK6-NEXT:    [[N_ADDR:%.*]] = alloca i64, align 8
10450 // CHECK6-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
10451 // CHECK6-NEXT:    [[AAA_ADDR:%.*]] = alloca i64, align 8
10452 // CHECK6-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
10453 // CHECK6-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
10454 // CHECK6-NEXT:    [[TMP:%.*]] = alloca i32, align 4
10455 // CHECK6-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
10456 // CHECK6-NEXT:    [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4
10457 // CHECK6-NEXT:    [[DOTCAPTURE_EXPR_5:%.*]] = alloca i32, align 4
10458 // CHECK6-NEXT:    [[I:%.*]] = alloca i32, align 4
10459 // CHECK6-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
10460 // CHECK6-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
10461 // CHECK6-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
10462 // CHECK6-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
10463 // CHECK6-NEXT:    [[I8:%.*]] = alloca i32, align 4
10464 // CHECK6-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
10465 // CHECK6-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
10466 // CHECK6-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
10467 // CHECK6-NEXT:    store i64 [[N]], i64* [[N_ADDR]], align 8
10468 // CHECK6-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
10469 // CHECK6-NEXT:    store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
10470 // CHECK6-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
10471 // CHECK6-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
10472 // CHECK6-NEXT:    [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32*
10473 // CHECK6-NEXT:    [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
10474 // CHECK6-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
10475 // CHECK6-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
10476 // CHECK6-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
10477 // CHECK6-NEXT:    store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
10478 // CHECK6-NEXT:    [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4
10479 // CHECK6-NEXT:    store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_4]], align 4
10480 // CHECK6-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4
10481 // CHECK6-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
10482 // CHECK6-NEXT:    [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]]
10483 // CHECK6-NEXT:    [[SUB6:%.*]] = sub i32 [[SUB]], 1
10484 // CHECK6-NEXT:    [[ADD:%.*]] = add i32 [[SUB6]], 1
10485 // CHECK6-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], 1
10486 // CHECK6-NEXT:    [[SUB7:%.*]] = sub i32 [[DIV]], 1
10487 // CHECK6-NEXT:    store i32 [[SUB7]], i32* [[DOTCAPTURE_EXPR_5]], align 4
10488 // CHECK6-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
10489 // CHECK6-NEXT:    store i32 [[TMP5]], i32* [[I]], align 4
10490 // CHECK6-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
10491 // CHECK6-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4
10492 // CHECK6-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]]
10493 // CHECK6-NEXT:    br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
10494 // CHECK6:       omp.precond.then:
10495 // CHECK6-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
10496 // CHECK6-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4
10497 // CHECK6-NEXT:    store i32 [[TMP8]], i32* [[DOTOMP_UB]], align 4
10498 // CHECK6-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
10499 // CHECK6-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
10500 // CHECK6-NEXT:    [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
10501 // CHECK6-NEXT:    [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
10502 // CHECK6-NEXT:    call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
10503 // CHECK6-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
10504 // CHECK6-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4
10505 // CHECK6-NEXT:    [[CMP9:%.*]] = icmp ugt i32 [[TMP11]], [[TMP12]]
10506 // CHECK6-NEXT:    br i1 [[CMP9]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
10507 // CHECK6:       cond.true:
10508 // CHECK6-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4
10509 // CHECK6-NEXT:    br label [[COND_END:%.*]]
10510 // CHECK6:       cond.false:
10511 // CHECK6-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
10512 // CHECK6-NEXT:    br label [[COND_END]]
10513 // CHECK6:       cond.end:
10514 // CHECK6-NEXT:    [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ]
10515 // CHECK6-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
10516 // CHECK6-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
10517 // CHECK6-NEXT:    store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4
10518 // CHECK6-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
10519 // CHECK6:       omp.inner.for.cond:
10520 // CHECK6-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !44
10521 // CHECK6-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !44
10522 // CHECK6-NEXT:    [[ADD10:%.*]] = add i32 [[TMP17]], 1
10523 // CHECK6-NEXT:    [[CMP11:%.*]] = icmp ult i32 [[TMP16]], [[ADD10]]
10524 // CHECK6-NEXT:    br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
10525 // CHECK6:       omp.inner.for.body:
10526 // CHECK6-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group !44
10527 // CHECK6-NEXT:    [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !44
10528 // CHECK6-NEXT:    [[MUL:%.*]] = mul i32 [[TMP19]], 1
10529 // CHECK6-NEXT:    [[ADD12:%.*]] = add i32 [[TMP18]], [[MUL]]
10530 // CHECK6-NEXT:    store i32 [[ADD12]], i32* [[I8]], align 4, !llvm.access.group !44
10531 // CHECK6-NEXT:    [[TMP20:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !44
10532 // CHECK6-NEXT:    [[ADD13:%.*]] = add nsw i32 [[TMP20]], 1
10533 // CHECK6-NEXT:    store i32 [[ADD13]], i32* [[CONV]], align 4, !llvm.access.group !44
10534 // CHECK6-NEXT:    [[TMP21:%.*]] = load i16, i16* [[CONV2]], align 2, !llvm.access.group !44
10535 // CHECK6-NEXT:    [[CONV14:%.*]] = sext i16 [[TMP21]] to i32
10536 // CHECK6-NEXT:    [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1
10537 // CHECK6-NEXT:    [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16
10538 // CHECK6-NEXT:    store i16 [[CONV16]], i16* [[CONV2]], align 2, !llvm.access.group !44
10539 // CHECK6-NEXT:    [[TMP22:%.*]] = load i8, i8* [[CONV3]], align 1, !llvm.access.group !44
10540 // CHECK6-NEXT:    [[CONV17:%.*]] = sext i8 [[TMP22]] to i32
10541 // CHECK6-NEXT:    [[ADD18:%.*]] = add nsw i32 [[CONV17]], 1
10542 // CHECK6-NEXT:    [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8
10543 // CHECK6-NEXT:    store i8 [[CONV19]], i8* [[CONV3]], align 1, !llvm.access.group !44
10544 // CHECK6-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
10545 // CHECK6-NEXT:    [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !44
10546 // CHECK6-NEXT:    [[ADD20:%.*]] = add nsw i32 [[TMP23]], 1
10547 // CHECK6-NEXT:    store i32 [[ADD20]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !44
10548 // CHECK6-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
10549 // CHECK6:       omp.body.continue:
10550 // CHECK6-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
10551 // CHECK6:       omp.inner.for.inc:
10552 // CHECK6-NEXT:    [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !44
10553 // CHECK6-NEXT:    [[ADD21:%.*]] = add i32 [[TMP24]], 1
10554 // CHECK6-NEXT:    store i32 [[ADD21]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !44
10555 // CHECK6-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP45:![0-9]+]]
10556 // CHECK6:       omp.inner.for.end:
10557 // CHECK6-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
10558 // CHECK6:       omp.loop.exit:
10559 // CHECK6-NEXT:    [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
10560 // CHECK6-NEXT:    [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4
10561 // CHECK6-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]])
10562 // CHECK6-NEXT:    [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
10563 // CHECK6-NEXT:    [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0
10564 // CHECK6-NEXT:    br i1 [[TMP28]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
10565 // CHECK6:       .omp.final.then:
10566 // CHECK6-NEXT:    [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
10567 // CHECK6-NEXT:    [[TMP30:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4
10568 // CHECK6-NEXT:    [[TMP31:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
10569 // CHECK6-NEXT:    [[SUB22:%.*]] = sub i32 [[TMP30]], [[TMP31]]
10570 // CHECK6-NEXT:    [[SUB23:%.*]] = sub i32 [[SUB22]], 1
10571 // CHECK6-NEXT:    [[ADD24:%.*]] = add i32 [[SUB23]], 1
10572 // CHECK6-NEXT:    [[DIV25:%.*]] = udiv i32 [[ADD24]], 1
10573 // CHECK6-NEXT:    [[MUL26:%.*]] = mul i32 [[DIV25]], 1
10574 // CHECK6-NEXT:    [[ADD27:%.*]] = add i32 [[TMP29]], [[MUL26]]
10575 // CHECK6-NEXT:    store i32 [[ADD27]], i32* [[I8]], align 4
10576 // CHECK6-NEXT:    br label [[DOTOMP_FINAL_DONE]]
10577 // CHECK6:       .omp.final.done:
10578 // CHECK6-NEXT:    br label [[OMP_PRECOND_END]]
10579 // CHECK6:       omp.precond.end:
10580 // CHECK6-NEXT:    ret void
10581 //
10582 //
10583 // CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180
10584 // CHECK6-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
10585 // CHECK6-NEXT:  entry:
10586 // CHECK6-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
10587 // CHECK6-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
10588 // CHECK6-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
10589 // CHECK6-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
10590 // CHECK6-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
10591 // CHECK6-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
10592 // CHECK6-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
10593 // CHECK6-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
10594 // CHECK6-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
10595 // CHECK6-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
10596 // CHECK6-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
10597 // CHECK6-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
10598 // CHECK6-NEXT:    [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
10599 // CHECK6-NEXT:    store i32 [[TMP1]], i32* [[CONV2]], align 4
10600 // CHECK6-NEXT:    [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
10601 // CHECK6-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
10602 // CHECK6-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
10603 // CHECK6-NEXT:    store i16 [[TMP3]], i16* [[CONV3]], align 2
10604 // CHECK6-NEXT:    [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
10605 // CHECK6-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..18 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]])
10606 // CHECK6-NEXT:    ret void
10607 //
10608 //
10609 // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..18
10610 // CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] {
10611 // CHECK6-NEXT:  entry:
10612 // CHECK6-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
10613 // CHECK6-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
10614 // CHECK6-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
10615 // CHECK6-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
10616 // CHECK6-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
10617 // CHECK6-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
10618 // CHECK6-NEXT:    [[TMP:%.*]] = alloca i32, align 4
10619 // CHECK6-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
10620 // CHECK6-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
10621 // CHECK6-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
10622 // CHECK6-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
10623 // CHECK6-NEXT:    [[I:%.*]] = alloca i32, align 4
10624 // CHECK6-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
10625 // CHECK6-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
10626 // CHECK6-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
10627 // CHECK6-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
10628 // CHECK6-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
10629 // CHECK6-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
10630 // CHECK6-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
10631 // CHECK6-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
10632 // CHECK6-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
10633 // CHECK6-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
10634 // CHECK6-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
10635 // CHECK6-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
10636 // CHECK6-NEXT:    [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
10637 // CHECK6-NEXT:    [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
10638 // CHECK6-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
10639 // CHECK6-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
10640 // CHECK6-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9
10641 // CHECK6-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
10642 // CHECK6:       cond.true:
10643 // CHECK6-NEXT:    br label [[COND_END:%.*]]
10644 // CHECK6:       cond.false:
10645 // CHECK6-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
10646 // CHECK6-NEXT:    br label [[COND_END]]
10647 // CHECK6:       cond.end:
10648 // CHECK6-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
10649 // CHECK6-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
10650 // CHECK6-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
10651 // CHECK6-NEXT:    store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
10652 // CHECK6-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
10653 // CHECK6:       omp.inner.for.cond:
10654 // CHECK6-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !47
10655 // CHECK6-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !47
10656 // CHECK6-NEXT:    [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
10657 // CHECK6-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
10658 // CHECK6:       omp.inner.for.body:
10659 // CHECK6-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !47
10660 // CHECK6-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
10661 // CHECK6-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
10662 // CHECK6-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !47
10663 // CHECK6-NEXT:    [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !47
10664 // CHECK6-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1
10665 // CHECK6-NEXT:    store i32 [[ADD3]], i32* [[CONV]], align 4, !llvm.access.group !47
10666 // CHECK6-NEXT:    [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 2, !llvm.access.group !47
10667 // CHECK6-NEXT:    [[CONV4:%.*]] = sext i16 [[TMP10]] to i32
10668 // CHECK6-NEXT:    [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
10669 // CHECK6-NEXT:    [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
10670 // CHECK6-NEXT:    store i16 [[CONV6]], i16* [[CONV1]], align 2, !llvm.access.group !47
10671 // CHECK6-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
10672 // CHECK6-NEXT:    [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !47
10673 // CHECK6-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1
10674 // CHECK6-NEXT:    store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !47
10675 // CHECK6-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
10676 // CHECK6:       omp.body.continue:
10677 // CHECK6-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
10678 // CHECK6:       omp.inner.for.inc:
10679 // CHECK6-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !47
10680 // CHECK6-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP12]], 1
10681 // CHECK6-NEXT:    store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !47
10682 // CHECK6-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP48:![0-9]+]]
10683 // CHECK6:       omp.inner.for.end:
10684 // CHECK6-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
10685 // CHECK6:       omp.loop.exit:
10686 // CHECK6-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
10687 // CHECK6-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
10688 // CHECK6-NEXT:    [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
10689 // CHECK6-NEXT:    br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
10690 // CHECK6:       .omp.final.then:
10691 // CHECK6-NEXT:    store i32 10, i32* [[I]], align 4
10692 // CHECK6-NEXT:    br label [[DOTOMP_FINAL_DONE]]
10693 // CHECK6:       .omp.final.done:
10694 // CHECK6-NEXT:    ret void
10695 //
10696 //
10697 // CHECK6-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
10698 // CHECK6-SAME: () #[[ATTR5]] {
10699 // CHECK6-NEXT:  entry:
10700 // CHECK6-NEXT:    call void @__tgt_register_requires(i64 1)
10701 // CHECK6-NEXT:    ret void
10702 //
10703 //
10704 // CHECK7-LABEL: define {{[^@]+}}@_Z3fooi
10705 // CHECK7-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0:[0-9]+]] {
10706 // CHECK7-NEXT:  entry:
10707 // CHECK7-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
10708 // CHECK7-NEXT:    [[A:%.*]] = alloca i32, align 4
10709 // CHECK7-NEXT:    [[AA:%.*]] = alloca i16, align 2
10710 // CHECK7-NEXT:    [[B:%.*]] = alloca [10 x float], align 4
10711 // CHECK7-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 4
10712 // CHECK7-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 4
10713 // CHECK7-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 8
10714 // CHECK7-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i32, align 4
10715 // CHECK7-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4
10716 // CHECK7-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
10717 // CHECK7-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
10718 // CHECK7-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
10719 // CHECK7-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
10720 // CHECK7-NEXT:    [[DOTCAPTURE_EXPR__CASTED3:%.*]] = alloca i32, align 4
10721 // CHECK7-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4
10722 // CHECK7-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4
10723 // CHECK7-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4
10724 // CHECK7-NEXT:    [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4
10725 // CHECK7-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
10726 // CHECK7-NEXT:    [[AA_CASTED4:%.*]] = alloca i32, align 4
10727 // CHECK7-NEXT:    [[DOTOFFLOAD_BASEPTRS6:%.*]] = alloca [1 x i8*], align 4
10728 // CHECK7-NEXT:    [[DOTOFFLOAD_PTRS7:%.*]] = alloca [1 x i8*], align 4
10729 // CHECK7-NEXT:    [[DOTOFFLOAD_MAPPERS8:%.*]] = alloca [1 x i8*], align 4
10730 // CHECK7-NEXT:    [[TMP:%.*]] = alloca i32, align 4
10731 // CHECK7-NEXT:    [[A_CASTED9:%.*]] = alloca i32, align 4
10732 // CHECK7-NEXT:    [[AA_CASTED10:%.*]] = alloca i32, align 4
10733 // CHECK7-NEXT:    [[DOTOFFLOAD_BASEPTRS12:%.*]] = alloca [2 x i8*], align 4
10734 // CHECK7-NEXT:    [[DOTOFFLOAD_PTRS13:%.*]] = alloca [2 x i8*], align 4
10735 // CHECK7-NEXT:    [[DOTOFFLOAD_MAPPERS14:%.*]] = alloca [2 x i8*], align 4
10736 // CHECK7-NEXT:    [[_TMP15:%.*]] = alloca i32, align 4
10737 // CHECK7-NEXT:    [[A_CASTED18:%.*]] = alloca i32, align 4
10738 // CHECK7-NEXT:    [[DOTOFFLOAD_BASEPTRS21:%.*]] = alloca [9 x i8*], align 4
10739 // CHECK7-NEXT:    [[DOTOFFLOAD_PTRS22:%.*]] = alloca [9 x i8*], align 4
10740 // CHECK7-NEXT:    [[DOTOFFLOAD_MAPPERS23:%.*]] = alloca [9 x i8*], align 4
10741 // CHECK7-NEXT:    [[DOTOFFLOAD_SIZES:%.*]] = alloca [9 x i64], align 4
10742 // CHECK7-NEXT:    [[_TMP24:%.*]] = alloca i32, align 4
10743 // CHECK7-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]])
10744 // CHECK7-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
10745 // CHECK7-NEXT:    store i32 0, i32* [[A]], align 4
10746 // CHECK7-NEXT:    store i16 0, i16* [[AA]], align 2
10747 // CHECK7-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
10748 // CHECK7-NEXT:    [[TMP2:%.*]] = call i8* @llvm.stacksave()
10749 // CHECK7-NEXT:    store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4
10750 // CHECK7-NEXT:    [[VLA:%.*]] = alloca float, i32 [[TMP1]], align 4
10751 // CHECK7-NEXT:    store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
10752 // CHECK7-NEXT:    [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
10753 // CHECK7-NEXT:    [[TMP4:%.*]] = mul nuw i32 5, [[TMP3]]
10754 // CHECK7-NEXT:    [[VLA1:%.*]] = alloca double, i32 [[TMP4]], align 8
10755 // CHECK7-NEXT:    store i32 [[TMP3]], i32* [[__VLA_EXPR1]], align 4
10756 // CHECK7-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
10757 // CHECK7-NEXT:    store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_]], align 4
10758 // CHECK7-NEXT:    [[TMP6:%.*]] = load i32, i32* [[A]], align 4
10759 // CHECK7-NEXT:    store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_2]], align 4
10760 // CHECK7-NEXT:    [[TMP7:%.*]] = load i16, i16* [[AA]], align 2
10761 // CHECK7-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
10762 // CHECK7-NEXT:    store i16 [[TMP7]], i16* [[CONV]], align 2
10763 // CHECK7-NEXT:    [[TMP8:%.*]] = load i32, i32* [[AA_CASTED]], align 4
10764 // CHECK7-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
10765 // CHECK7-NEXT:    store i32 [[TMP9]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
10766 // CHECK7-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
10767 // CHECK7-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
10768 // CHECK7-NEXT:    store i32 [[TMP11]], i32* [[DOTCAPTURE_EXPR__CASTED3]], align 4
10769 // CHECK7-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED3]], align 4
10770 // CHECK7-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
10771 // CHECK7-NEXT:    [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i32*
10772 // CHECK7-NEXT:    store i32 [[TMP8]], i32* [[TMP14]], align 4
10773 // CHECK7-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
10774 // CHECK7-NEXT:    [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i32*
10775 // CHECK7-NEXT:    store i32 [[TMP8]], i32* [[TMP16]], align 4
10776 // CHECK7-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
10777 // CHECK7-NEXT:    store i8* null, i8** [[TMP17]], align 4
10778 // CHECK7-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
10779 // CHECK7-NEXT:    [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32*
10780 // CHECK7-NEXT:    store i32 [[TMP10]], i32* [[TMP19]], align 4
10781 // CHECK7-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
10782 // CHECK7-NEXT:    [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32*
10783 // CHECK7-NEXT:    store i32 [[TMP10]], i32* [[TMP21]], align 4
10784 // CHECK7-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
10785 // CHECK7-NEXT:    store i8* null, i8** [[TMP22]], align 4
10786 // CHECK7-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
10787 // CHECK7-NEXT:    [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i32*
10788 // CHECK7-NEXT:    store i32 [[TMP12]], i32* [[TMP24]], align 4
10789 // CHECK7-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
10790 // CHECK7-NEXT:    [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i32*
10791 // CHECK7-NEXT:    store i32 [[TMP12]], i32* [[TMP26]], align 4
10792 // CHECK7-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
10793 // CHECK7-NEXT:    store i8* null, i8** [[TMP27]], align 4
10794 // CHECK7-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
10795 // CHECK7-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
10796 // CHECK7-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 0
10797 // CHECK7-NEXT:    [[TMP31:%.*]] = load i16, i16* [[AA]], align 2
10798 // CHECK7-NEXT:    store i16 [[TMP31]], i16* [[TMP30]], align 4
10799 // CHECK7-NEXT:    [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 1
10800 // CHECK7-NEXT:    [[TMP33:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
10801 // CHECK7-NEXT:    store i32 [[TMP33]], i32* [[TMP32]], align 4
10802 // CHECK7-NEXT:    [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 2
10803 // CHECK7-NEXT:    [[TMP35:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
10804 // CHECK7-NEXT:    store i32 [[TMP35]], i32* [[TMP34]], align 4
10805 // CHECK7-NEXT:    [[TMP36:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 1, i32 72, i32 12, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1)
10806 // CHECK7-NEXT:    [[TMP37:%.*]] = bitcast i8* [[TMP36]] to %struct.kmp_task_t_with_privates*
10807 // CHECK7-NEXT:    [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP37]], i32 0, i32 0
10808 // CHECK7-NEXT:    [[TMP39:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP38]], i32 0, i32 0
10809 // CHECK7-NEXT:    [[TMP40:%.*]] = load i8*, i8** [[TMP39]], align 4
10810 // CHECK7-NEXT:    [[TMP41:%.*]] = bitcast %struct.anon* [[AGG_CAPTURED]] to i8*
10811 // CHECK7-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP40]], i8* align 4 [[TMP41]], i32 12, i1 false)
10812 // CHECK7-NEXT:    [[TMP42:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP37]], i32 0, i32 1
10813 // CHECK7-NEXT:    [[TMP43:%.*]] = bitcast i8* [[TMP40]] to %struct.anon*
10814 // CHECK7-NEXT:    [[TMP44:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 0
10815 // CHECK7-NEXT:    [[TMP45:%.*]] = bitcast [3 x i64]* [[TMP44]] to i8*
10816 // CHECK7-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP45]], i8* align 4 bitcast ([3 x i64]* @.offload_sizes to i8*), i32 24, i1 false)
10817 // CHECK7-NEXT:    [[TMP46:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 1
10818 // CHECK7-NEXT:    [[TMP47:%.*]] = bitcast [3 x i8*]* [[TMP46]] to i8*
10819 // CHECK7-NEXT:    [[TMP48:%.*]] = bitcast i8** [[TMP28]] to i8*
10820 // CHECK7-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP47]], i8* align 4 [[TMP48]], i32 12, i1 false)
10821 // CHECK7-NEXT:    [[TMP49:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 2
10822 // CHECK7-NEXT:    [[TMP50:%.*]] = bitcast [3 x i8*]* [[TMP49]] to i8*
10823 // CHECK7-NEXT:    [[TMP51:%.*]] = bitcast i8** [[TMP29]] to i8*
10824 // CHECK7-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP50]], i8* align 4 [[TMP51]], i32 12, i1 false)
10825 // CHECK7-NEXT:    [[TMP52:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 3
10826 // CHECK7-NEXT:    [[TMP53:%.*]] = load i16, i16* [[AA]], align 2
10827 // CHECK7-NEXT:    store i16 [[TMP53]], i16* [[TMP52]], align 4
10828 // CHECK7-NEXT:    [[TMP54:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i8* [[TMP36]])
10829 // CHECK7-NEXT:    [[TMP55:%.*]] = load i32, i32* [[A]], align 4
10830 // CHECK7-NEXT:    store i32 [[TMP55]], i32* [[A_CASTED]], align 4
10831 // CHECK7-NEXT:    [[TMP56:%.*]] = load i32, i32* [[A_CASTED]], align 4
10832 // CHECK7-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l102(i32 [[TMP56]]) #[[ATTR4:[0-9]+]]
10833 // CHECK7-NEXT:    [[TMP57:%.*]] = load i16, i16* [[AA]], align 2
10834 // CHECK7-NEXT:    [[CONV5:%.*]] = bitcast i32* [[AA_CASTED4]] to i16*
10835 // CHECK7-NEXT:    store i16 [[TMP57]], i16* [[CONV5]], align 2
10836 // CHECK7-NEXT:    [[TMP58:%.*]] = load i32, i32* [[AA_CASTED4]], align 4
10837 // CHECK7-NEXT:    [[TMP59:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0
10838 // CHECK7-NEXT:    [[TMP60:%.*]] = bitcast i8** [[TMP59]] to i32*
10839 // CHECK7-NEXT:    store i32 [[TMP58]], i32* [[TMP60]], align 4
10840 // CHECK7-NEXT:    [[TMP61:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0
10841 // CHECK7-NEXT:    [[TMP62:%.*]] = bitcast i8** [[TMP61]] to i32*
10842 // CHECK7-NEXT:    store i32 [[TMP58]], i32* [[TMP62]], align 4
10843 // CHECK7-NEXT:    [[TMP63:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS8]], i32 0, i32 0
10844 // CHECK7-NEXT:    store i8* null, i8** [[TMP63]], align 4
10845 // CHECK7-NEXT:    [[TMP64:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0
10846 // CHECK7-NEXT:    [[TMP65:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0
10847 // CHECK7-NEXT:    call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10)
10848 // CHECK7-NEXT:    [[TMP66:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.region_id, i32 1, i8** [[TMP64]], i8** [[TMP65]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.4, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.5, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1)
10849 // CHECK7-NEXT:    [[TMP67:%.*]] = icmp ne i32 [[TMP66]], 0
10850 // CHECK7-NEXT:    br i1 [[TMP67]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
10851 // CHECK7:       omp_offload.failed:
10852 // CHECK7-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111(i32 [[TMP58]]) #[[ATTR4]]
10853 // CHECK7-NEXT:    br label [[OMP_OFFLOAD_CONT]]
10854 // CHECK7:       omp_offload.cont:
10855 // CHECK7-NEXT:    [[TMP68:%.*]] = load i32, i32* [[A]], align 4
10856 // CHECK7-NEXT:    store i32 [[TMP68]], i32* [[A_CASTED9]], align 4
10857 // CHECK7-NEXT:    [[TMP69:%.*]] = load i32, i32* [[A_CASTED9]], align 4
10858 // CHECK7-NEXT:    [[TMP70:%.*]] = load i16, i16* [[AA]], align 2
10859 // CHECK7-NEXT:    [[CONV11:%.*]] = bitcast i32* [[AA_CASTED10]] to i16*
10860 // CHECK7-NEXT:    store i16 [[TMP70]], i16* [[CONV11]], align 2
10861 // CHECK7-NEXT:    [[TMP71:%.*]] = load i32, i32* [[AA_CASTED10]], align 4
10862 // CHECK7-NEXT:    [[TMP72:%.*]] = load i32, i32* [[N_ADDR]], align 4
10863 // CHECK7-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP72]], 10
10864 // CHECK7-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
10865 // CHECK7:       omp_if.then:
10866 // CHECK7-NEXT:    [[TMP73:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS12]], i32 0, i32 0
10867 // CHECK7-NEXT:    [[TMP74:%.*]] = bitcast i8** [[TMP73]] to i32*
10868 // CHECK7-NEXT:    store i32 [[TMP69]], i32* [[TMP74]], align 4
10869 // CHECK7-NEXT:    [[TMP75:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS13]], i32 0, i32 0
10870 // CHECK7-NEXT:    [[TMP76:%.*]] = bitcast i8** [[TMP75]] to i32*
10871 // CHECK7-NEXT:    store i32 [[TMP69]], i32* [[TMP76]], align 4
10872 // CHECK7-NEXT:    [[TMP77:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS14]], i32 0, i32 0
10873 // CHECK7-NEXT:    store i8* null, i8** [[TMP77]], align 4
10874 // CHECK7-NEXT:    [[TMP78:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS12]], i32 0, i32 1
10875 // CHECK7-NEXT:    [[TMP79:%.*]] = bitcast i8** [[TMP78]] to i32*
10876 // CHECK7-NEXT:    store i32 [[TMP71]], i32* [[TMP79]], align 4
10877 // CHECK7-NEXT:    [[TMP80:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS13]], i32 0, i32 1
10878 // CHECK7-NEXT:    [[TMP81:%.*]] = bitcast i8** [[TMP80]] to i32*
10879 // CHECK7-NEXT:    store i32 [[TMP71]], i32* [[TMP81]], align 4
10880 // CHECK7-NEXT:    [[TMP82:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS14]], i32 0, i32 1
10881 // CHECK7-NEXT:    store i8* null, i8** [[TMP82]], align 4
10882 // CHECK7-NEXT:    [[TMP83:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS12]], i32 0, i32 0
10883 // CHECK7-NEXT:    [[TMP84:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS13]], i32 0, i32 0
10884 // CHECK7-NEXT:    call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10)
10885 // CHECK7-NEXT:    [[TMP85:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.region_id, i32 2, i8** [[TMP83]], i8** [[TMP84]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.7, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.8, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1)
10886 // CHECK7-NEXT:    [[TMP86:%.*]] = icmp ne i32 [[TMP85]], 0
10887 // CHECK7-NEXT:    br i1 [[TMP86]], label [[OMP_OFFLOAD_FAILED16:%.*]], label [[OMP_OFFLOAD_CONT17:%.*]]
10888 // CHECK7:       omp_offload.failed16:
10889 // CHECK7-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i32 [[TMP69]], i32 [[TMP71]]) #[[ATTR4]]
10890 // CHECK7-NEXT:    br label [[OMP_OFFLOAD_CONT17]]
10891 // CHECK7:       omp_offload.cont17:
10892 // CHECK7-NEXT:    br label [[OMP_IF_END:%.*]]
10893 // CHECK7:       omp_if.else:
10894 // CHECK7-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i32 [[TMP69]], i32 [[TMP71]]) #[[ATTR4]]
10895 // CHECK7-NEXT:    br label [[OMP_IF_END]]
10896 // CHECK7:       omp_if.end:
10897 // CHECK7-NEXT:    [[TMP87:%.*]] = load i32, i32* [[A]], align 4
10898 // CHECK7-NEXT:    store i32 [[TMP87]], i32* [[A_CASTED18]], align 4
10899 // CHECK7-NEXT:    [[TMP88:%.*]] = load i32, i32* [[A_CASTED18]], align 4
10900 // CHECK7-NEXT:    [[TMP89:%.*]] = load i32, i32* [[N_ADDR]], align 4
10901 // CHECK7-NEXT:    [[CMP19:%.*]] = icmp sgt i32 [[TMP89]], 20
10902 // CHECK7-NEXT:    br i1 [[CMP19]], label [[OMP_IF_THEN20:%.*]], label [[OMP_IF_ELSE27:%.*]]
10903 // CHECK7:       omp_if.then20:
10904 // CHECK7-NEXT:    [[TMP90:%.*]] = mul nuw i32 [[TMP1]], 4
10905 // CHECK7-NEXT:    [[TMP91:%.*]] = sext i32 [[TMP90]] to i64
10906 // CHECK7-NEXT:    [[TMP92:%.*]] = mul nuw i32 5, [[TMP3]]
10907 // CHECK7-NEXT:    [[TMP93:%.*]] = mul nuw i32 [[TMP92]], 8
10908 // CHECK7-NEXT:    [[TMP94:%.*]] = sext i32 [[TMP93]] to i64
10909 // CHECK7-NEXT:    [[TMP95:%.*]] = bitcast [9 x i64]* [[DOTOFFLOAD_SIZES]] to i8*
10910 // CHECK7-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP95]], i8* align 4 bitcast ([9 x i64]* @.offload_sizes.10 to i8*), i32 72, i1 false)
10911 // CHECK7-NEXT:    [[TMP96:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 0
10912 // CHECK7-NEXT:    [[TMP97:%.*]] = bitcast i8** [[TMP96]] to i32*
10913 // CHECK7-NEXT:    store i32 [[TMP88]], i32* [[TMP97]], align 4
10914 // CHECK7-NEXT:    [[TMP98:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 0
10915 // CHECK7-NEXT:    [[TMP99:%.*]] = bitcast i8** [[TMP98]] to i32*
10916 // CHECK7-NEXT:    store i32 [[TMP88]], i32* [[TMP99]], align 4
10917 // CHECK7-NEXT:    [[TMP100:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i32 0, i32 0
10918 // CHECK7-NEXT:    store i8* null, i8** [[TMP100]], align 4
10919 // CHECK7-NEXT:    [[TMP101:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 1
10920 // CHECK7-NEXT:    [[TMP102:%.*]] = bitcast i8** [[TMP101]] to [10 x float]**
10921 // CHECK7-NEXT:    store [10 x float]* [[B]], [10 x float]** [[TMP102]], align 4
10922 // CHECK7-NEXT:    [[TMP103:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 1
10923 // CHECK7-NEXT:    [[TMP104:%.*]] = bitcast i8** [[TMP103]] to [10 x float]**
10924 // CHECK7-NEXT:    store [10 x float]* [[B]], [10 x float]** [[TMP104]], align 4
10925 // CHECK7-NEXT:    [[TMP105:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i32 0, i32 1
10926 // CHECK7-NEXT:    store i8* null, i8** [[TMP105]], align 4
10927 // CHECK7-NEXT:    [[TMP106:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 2
10928 // CHECK7-NEXT:    [[TMP107:%.*]] = bitcast i8** [[TMP106]] to i32*
10929 // CHECK7-NEXT:    store i32 [[TMP1]], i32* [[TMP107]], align 4
10930 // CHECK7-NEXT:    [[TMP108:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 2
10931 // CHECK7-NEXT:    [[TMP109:%.*]] = bitcast i8** [[TMP108]] to i32*
10932 // CHECK7-NEXT:    store i32 [[TMP1]], i32* [[TMP109]], align 4
10933 // CHECK7-NEXT:    [[TMP110:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i32 0, i32 2
10934 // CHECK7-NEXT:    store i8* null, i8** [[TMP110]], align 4
10935 // CHECK7-NEXT:    [[TMP111:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 3
10936 // CHECK7-NEXT:    [[TMP112:%.*]] = bitcast i8** [[TMP111]] to float**
10937 // CHECK7-NEXT:    store float* [[VLA]], float** [[TMP112]], align 4
10938 // CHECK7-NEXT:    [[TMP113:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 3
10939 // CHECK7-NEXT:    [[TMP114:%.*]] = bitcast i8** [[TMP113]] to float**
10940 // CHECK7-NEXT:    store float* [[VLA]], float** [[TMP114]], align 4
10941 // CHECK7-NEXT:    [[TMP115:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3
10942 // CHECK7-NEXT:    store i64 [[TMP91]], i64* [[TMP115]], align 4
10943 // CHECK7-NEXT:    [[TMP116:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i32 0, i32 3
10944 // CHECK7-NEXT:    store i8* null, i8** [[TMP116]], align 4
10945 // CHECK7-NEXT:    [[TMP117:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 4
10946 // CHECK7-NEXT:    [[TMP118:%.*]] = bitcast i8** [[TMP117]] to [5 x [10 x double]]**
10947 // CHECK7-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP118]], align 4
10948 // CHECK7-NEXT:    [[TMP119:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 4
10949 // CHECK7-NEXT:    [[TMP120:%.*]] = bitcast i8** [[TMP119]] to [5 x [10 x double]]**
10950 // CHECK7-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP120]], align 4
10951 // CHECK7-NEXT:    [[TMP121:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i32 0, i32 4
10952 // CHECK7-NEXT:    store i8* null, i8** [[TMP121]], align 4
10953 // CHECK7-NEXT:    [[TMP122:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 5
10954 // CHECK7-NEXT:    [[TMP123:%.*]] = bitcast i8** [[TMP122]] to i32*
10955 // CHECK7-NEXT:    store i32 5, i32* [[TMP123]], align 4
10956 // CHECK7-NEXT:    [[TMP124:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 5
10957 // CHECK7-NEXT:    [[TMP125:%.*]] = bitcast i8** [[TMP124]] to i32*
10958 // CHECK7-NEXT:    store i32 5, i32* [[TMP125]], align 4
10959 // CHECK7-NEXT:    [[TMP126:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i32 0, i32 5
10960 // CHECK7-NEXT:    store i8* null, i8** [[TMP126]], align 4
10961 // CHECK7-NEXT:    [[TMP127:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 6
10962 // CHECK7-NEXT:    [[TMP128:%.*]] = bitcast i8** [[TMP127]] to i32*
10963 // CHECK7-NEXT:    store i32 [[TMP3]], i32* [[TMP128]], align 4
10964 // CHECK7-NEXT:    [[TMP129:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 6
10965 // CHECK7-NEXT:    [[TMP130:%.*]] = bitcast i8** [[TMP129]] to i32*
10966 // CHECK7-NEXT:    store i32 [[TMP3]], i32* [[TMP130]], align 4
10967 // CHECK7-NEXT:    [[TMP131:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i32 0, i32 6
10968 // CHECK7-NEXT:    store i8* null, i8** [[TMP131]], align 4
10969 // CHECK7-NEXT:    [[TMP132:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 7
10970 // CHECK7-NEXT:    [[TMP133:%.*]] = bitcast i8** [[TMP132]] to double**
10971 // CHECK7-NEXT:    store double* [[VLA1]], double** [[TMP133]], align 4
10972 // CHECK7-NEXT:    [[TMP134:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 7
10973 // CHECK7-NEXT:    [[TMP135:%.*]] = bitcast i8** [[TMP134]] to double**
10974 // CHECK7-NEXT:    store double* [[VLA1]], double** [[TMP135]], align 4
10975 // CHECK7-NEXT:    [[TMP136:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7
10976 // CHECK7-NEXT:    store i64 [[TMP94]], i64* [[TMP136]], align 4
10977 // CHECK7-NEXT:    [[TMP137:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i32 0, i32 7
10978 // CHECK7-NEXT:    store i8* null, i8** [[TMP137]], align 4
10979 // CHECK7-NEXT:    [[TMP138:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 8
10980 // CHECK7-NEXT:    [[TMP139:%.*]] = bitcast i8** [[TMP138]] to %struct.TT**
10981 // CHECK7-NEXT:    store %struct.TT* [[D]], %struct.TT** [[TMP139]], align 4
10982 // CHECK7-NEXT:    [[TMP140:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 8
10983 // CHECK7-NEXT:    [[TMP141:%.*]] = bitcast i8** [[TMP140]] to %struct.TT**
10984 // CHECK7-NEXT:    store %struct.TT* [[D]], %struct.TT** [[TMP141]], align 4
10985 // CHECK7-NEXT:    [[TMP142:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i32 0, i32 8
10986 // CHECK7-NEXT:    store i8* null, i8** [[TMP142]], align 4
10987 // CHECK7-NEXT:    [[TMP143:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 0
10988 // CHECK7-NEXT:    [[TMP144:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 0
10989 // CHECK7-NEXT:    [[TMP145:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
10990 // CHECK7-NEXT:    call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10)
10991 // CHECK7-NEXT:    [[TMP146:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142.region_id, i32 9, i8** [[TMP143]], i8** [[TMP144]], i64* [[TMP145]], i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_maptypes.11, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1)
10992 // CHECK7-NEXT:    [[TMP147:%.*]] = icmp ne i32 [[TMP146]], 0
10993 // CHECK7-NEXT:    br i1 [[TMP147]], label [[OMP_OFFLOAD_FAILED25:%.*]], label [[OMP_OFFLOAD_CONT26:%.*]]
10994 // CHECK7:       omp_offload.failed25:
10995 // CHECK7-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i32 [[TMP88]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR4]]
10996 // CHECK7-NEXT:    br label [[OMP_OFFLOAD_CONT26]]
10997 // CHECK7:       omp_offload.cont26:
10998 // CHECK7-NEXT:    br label [[OMP_IF_END28:%.*]]
10999 // CHECK7:       omp_if.else27:
11000 // CHECK7-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i32 [[TMP88]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR4]]
11001 // CHECK7-NEXT:    br label [[OMP_IF_END28]]
11002 // CHECK7:       omp_if.end28:
11003 // CHECK7-NEXT:    [[TMP148:%.*]] = load i32, i32* [[A]], align 4
11004 // CHECK7-NEXT:    [[TMP149:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
11005 // CHECK7-NEXT:    call void @llvm.stackrestore(i8* [[TMP149]])
11006 // CHECK7-NEXT:    ret i32 [[TMP148]]
11007 //
11008 //
11009 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97
11010 // CHECK7-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]], i32 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] {
11011 // CHECK7-NEXT:  entry:
11012 // CHECK7-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
11013 // CHECK7-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
11014 // CHECK7-NEXT:    [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4
11015 // CHECK7-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
11016 // CHECK7-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]])
11017 // CHECK7-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
11018 // CHECK7-NEXT:    store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
11019 // CHECK7-NEXT:    store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4
11020 // CHECK7-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
11021 // CHECK7-NEXT:    [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
11022 // CHECK7-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4
11023 // CHECK7-NEXT:    call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
11024 // CHECK7-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
11025 // CHECK7-NEXT:    [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
11026 // CHECK7-NEXT:    store i16 [[TMP3]], i16* [[CONV3]], align 2
11027 // CHECK7-NEXT:    [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
11028 // CHECK7-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]])
11029 // CHECK7-NEXT:    ret void
11030 //
11031 //
11032 // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined.
11033 // CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR3:[0-9]+]] {
11034 // CHECK7-NEXT:  entry:
11035 // CHECK7-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
11036 // CHECK7-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
11037 // CHECK7-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
11038 // CHECK7-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
11039 // CHECK7-NEXT:    [[TMP:%.*]] = alloca i32, align 4
11040 // CHECK7-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
11041 // CHECK7-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
11042 // CHECK7-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
11043 // CHECK7-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
11044 // CHECK7-NEXT:    [[I:%.*]] = alloca i32, align 4
11045 // CHECK7-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
11046 // CHECK7-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
11047 // CHECK7-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
11048 // CHECK7-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
11049 // CHECK7-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
11050 // CHECK7-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
11051 // CHECK7-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
11052 // CHECK7-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
11053 // CHECK7-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
11054 // CHECK7-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
11055 // CHECK7-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
11056 // CHECK7-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
11057 // CHECK7-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
11058 // CHECK7-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
11059 // CHECK7:       cond.true:
11060 // CHECK7-NEXT:    br label [[COND_END:%.*]]
11061 // CHECK7:       cond.false:
11062 // CHECK7-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
11063 // CHECK7-NEXT:    br label [[COND_END]]
11064 // CHECK7:       cond.end:
11065 // CHECK7-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
11066 // CHECK7-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
11067 // CHECK7-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
11068 // CHECK7-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
11069 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
11070 // CHECK7:       omp.inner.for.cond:
11071 // CHECK7-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
11072 // CHECK7-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !11
11073 // CHECK7-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
11074 // CHECK7-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
11075 // CHECK7:       omp.inner.for.body:
11076 // CHECK7-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
11077 // CHECK7-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
11078 // CHECK7-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
11079 // CHECK7-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11
11080 // CHECK7-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
11081 // CHECK7:       omp.body.continue:
11082 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
11083 // CHECK7:       omp.inner.for.inc:
11084 // CHECK7-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
11085 // CHECK7-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
11086 // CHECK7-NEXT:    store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
11087 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]
11088 // CHECK7:       omp.inner.for.end:
11089 // CHECK7-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
11090 // CHECK7:       omp.loop.exit:
11091 // CHECK7-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
11092 // CHECK7-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
11093 // CHECK7-NEXT:    [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0
11094 // CHECK7-NEXT:    br i1 [[TMP10]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
11095 // CHECK7:       .omp.final.then:
11096 // CHECK7-NEXT:    store i32 10, i32* [[I]], align 4
11097 // CHECK7-NEXT:    br label [[DOTOMP_FINAL_DONE]]
11098 // CHECK7:       .omp.final.done:
11099 // CHECK7-NEXT:    ret void
11100 //
11101 //
11102 // CHECK7-LABEL: define {{[^@]+}}@.omp_task_privates_map.
11103 // CHECK7-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], i16** noalias noundef [[TMP1:%.*]], [3 x i8*]** noalias noundef [[TMP2:%.*]], [3 x i8*]** noalias noundef [[TMP3:%.*]], [3 x i64]** noalias noundef [[TMP4:%.*]]) #[[ATTR5:[0-9]+]] {
11104 // CHECK7-NEXT:  entry:
11105 // CHECK7-NEXT:    [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 4
11106 // CHECK7-NEXT:    [[DOTADDR1:%.*]] = alloca i16**, align 4
11107 // CHECK7-NEXT:    [[DOTADDR2:%.*]] = alloca [3 x i8*]**, align 4
11108 // CHECK7-NEXT:    [[DOTADDR3:%.*]] = alloca [3 x i8*]**, align 4
11109 // CHECK7-NEXT:    [[DOTADDR4:%.*]] = alloca [3 x i64]**, align 4
11110 // CHECK7-NEXT:    store %struct..kmp_privates.t* [[TMP0]], %struct..kmp_privates.t** [[DOTADDR]], align 4
11111 // CHECK7-NEXT:    store i16** [[TMP1]], i16*** [[DOTADDR1]], align 4
11112 // CHECK7-NEXT:    store [3 x i8*]** [[TMP2]], [3 x i8*]*** [[DOTADDR2]], align 4
11113 // CHECK7-NEXT:    store [3 x i8*]** [[TMP3]], [3 x i8*]*** [[DOTADDR3]], align 4
11114 // CHECK7-NEXT:    store [3 x i64]** [[TMP4]], [3 x i64]*** [[DOTADDR4]], align 4
11115 // CHECK7-NEXT:    [[TMP5:%.*]] = load %struct..kmp_privates.t*, %struct..kmp_privates.t** [[DOTADDR]], align 4
11116 // CHECK7-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 0
11117 // CHECK7-NEXT:    [[TMP7:%.*]] = load [3 x i64]**, [3 x i64]*** [[DOTADDR4]], align 4
11118 // CHECK7-NEXT:    store [3 x i64]* [[TMP6]], [3 x i64]** [[TMP7]], align 4
11119 // CHECK7-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 1
11120 // CHECK7-NEXT:    [[TMP9:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR2]], align 4
11121 // CHECK7-NEXT:    store [3 x i8*]* [[TMP8]], [3 x i8*]** [[TMP9]], align 4
11122 // CHECK7-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 2
11123 // CHECK7-NEXT:    [[TMP11:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR3]], align 4
11124 // CHECK7-NEXT:    store [3 x i8*]* [[TMP10]], [3 x i8*]** [[TMP11]], align 4
11125 // CHECK7-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 3
11126 // CHECK7-NEXT:    [[TMP13:%.*]] = load i16**, i16*** [[DOTADDR1]], align 4
11127 // CHECK7-NEXT:    store i16* [[TMP12]], i16** [[TMP13]], align 4
11128 // CHECK7-NEXT:    ret void
11129 //
11130 //
11131 // CHECK7-LABEL: define {{[^@]+}}@.omp_task_entry.
11132 // CHECK7-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] {
11133 // CHECK7-NEXT:  entry:
11134 // CHECK7-NEXT:    [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
11135 // CHECK7-NEXT:    [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 4
11136 // CHECK7-NEXT:    [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 4
11137 // CHECK7-NEXT:    [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 4
11138 // CHECK7-NEXT:    [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 4
11139 // CHECK7-NEXT:    [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 4
11140 // CHECK7-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca i16*, align 4
11141 // CHECK7-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca [3 x i8*]*, align 4
11142 // CHECK7-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca [3 x i8*]*, align 4
11143 // CHECK7-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca [3 x i64]*, align 4
11144 // CHECK7-NEXT:    [[AA_CASTED_I:%.*]] = alloca i32, align 4
11145 // CHECK7-NEXT:    [[DOTCAPTURE_EXPR__CASTED_I:%.*]] = alloca i32, align 4
11146 // CHECK7-NEXT:    [[DOTCAPTURE_EXPR__CASTED4_I:%.*]] = alloca i32, align 4
11147 // CHECK7-NEXT:    [[DOTADDR:%.*]] = alloca i32, align 4
11148 // CHECK7-NEXT:    [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 4
11149 // CHECK7-NEXT:    store i32 [[TMP0]], i32* [[DOTADDR]], align 4
11150 // CHECK7-NEXT:    store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4
11151 // CHECK7-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4
11152 // CHECK7-NEXT:    [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4
11153 // CHECK7-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
11154 // CHECK7-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
11155 // CHECK7-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0
11156 // CHECK7-NEXT:    [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 4
11157 // CHECK7-NEXT:    [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon*
11158 // CHECK7-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1
11159 // CHECK7-NEXT:    [[TMP10:%.*]] = bitcast %struct..kmp_privates.t* [[TMP9]] to i8*
11160 // CHECK7-NEXT:    [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8*
11161 // CHECK7-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]])
11162 // CHECK7-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META21:![0-9]+]])
11163 // CHECK7-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META23:![0-9]+]])
11164 // CHECK7-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META25:![0-9]+]])
11165 // CHECK7-NEXT:    store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !27
11166 // CHECK7-NEXT:    store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 4, !noalias !27
11167 // CHECK7-NEXT:    store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !27
11168 // CHECK7-NEXT:    store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* @.omp_task_privates_map. to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !27
11169 // CHECK7-NEXT:    store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 4, !noalias !27
11170 // CHECK7-NEXT:    store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !27
11171 // CHECK7-NEXT:    [[TMP12:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !27
11172 // CHECK7-NEXT:    [[TMP13:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !27
11173 // CHECK7-NEXT:    [[TMP14:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !27
11174 // CHECK7-NEXT:    [[TMP15:%.*]] = bitcast void (i8*, ...)* [[TMP13]] to void (i8*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)*
11175 // CHECK7-NEXT:    call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR4]]
11176 // CHECK7-NEXT:    [[TMP16:%.*]] = load i16*, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 4, !noalias !27
11177 // CHECK7-NEXT:    [[TMP17:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 4, !noalias !27
11178 // CHECK7-NEXT:    [[TMP18:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 4, !noalias !27
11179 // CHECK7-NEXT:    [[TMP19:%.*]] = load [3 x i64]*, [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 4, !noalias !27
11180 // CHECK7-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP17]], i32 0, i32 0
11181 // CHECK7-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP18]], i32 0, i32 0
11182 // CHECK7-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[TMP19]], i32 0, i32 0
11183 // CHECK7-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP12]], i32 0, i32 1
11184 // CHECK7-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[TMP12]], i32 0, i32 2
11185 // CHECK7-NEXT:    [[TMP25:%.*]] = load i32, i32* [[TMP23]], align 4
11186 // CHECK7-NEXT:    call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) #[[ATTR4]]
11187 // CHECK7-NEXT:    [[TMP26:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 [[TMP25]], i32 1, i32 0, i8* null, i32 0, i8* null) #[[ATTR4]]
11188 // CHECK7-NEXT:    [[TMP27:%.*]] = icmp ne i32 [[TMP26]], 0
11189 // CHECK7-NEXT:    br i1 [[TMP27]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]]
11190 // CHECK7:       omp_offload.failed.i:
11191 // CHECK7-NEXT:    [[TMP28:%.*]] = load i16, i16* [[TMP16]], align 2
11192 // CHECK7-NEXT:    [[CONV_I:%.*]] = bitcast i32* [[AA_CASTED_I]] to i16*
11193 // CHECK7-NEXT:    store i16 [[TMP28]], i16* [[CONV_I]], align 2, !noalias !27
11194 // CHECK7-NEXT:    [[TMP29:%.*]] = load i32, i32* [[AA_CASTED_I]], align 4, !noalias !27
11195 // CHECK7-NEXT:    [[TMP30:%.*]] = load i32, i32* [[TMP23]], align 4
11196 // CHECK7-NEXT:    store i32 [[TMP30]], i32* [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias !27
11197 // CHECK7-NEXT:    [[TMP31:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias !27
11198 // CHECK7-NEXT:    [[TMP32:%.*]] = load i32, i32* [[TMP24]], align 4
11199 // CHECK7-NEXT:    store i32 [[TMP32]], i32* [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias !27
11200 // CHECK7-NEXT:    [[TMP33:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias !27
11201 // CHECK7-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97(i32 [[TMP29]], i32 [[TMP31]], i32 [[TMP33]]) #[[ATTR4]]
11202 // CHECK7-NEXT:    br label [[DOTOMP_OUTLINED__1_EXIT]]
11203 // CHECK7:       .omp_outlined..1.exit:
11204 // CHECK7-NEXT:    ret i32 0
11205 //
11206 //
11207 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l102
11208 // CHECK7-SAME: (i32 noundef [[A:%.*]]) #[[ATTR3]] {
11209 // CHECK7-NEXT:  entry:
11210 // CHECK7-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
11211 // CHECK7-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
11212 // CHECK7-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
11213 // CHECK7-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
11214 // CHECK7-NEXT:    store i32 [[TMP0]], i32* [[A_CASTED]], align 4
11215 // CHECK7-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
11216 // CHECK7-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]])
11217 // CHECK7-NEXT:    ret void
11218 //
11219 //
11220 // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..2
11221 // CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]]) #[[ATTR3]] {
11222 // CHECK7-NEXT:  entry:
11223 // CHECK7-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
11224 // CHECK7-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
11225 // CHECK7-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
11226 // CHECK7-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
11227 // CHECK7-NEXT:    [[TMP:%.*]] = alloca i32, align 4
11228 // CHECK7-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
11229 // CHECK7-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
11230 // CHECK7-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
11231 // CHECK7-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
11232 // CHECK7-NEXT:    [[A1:%.*]] = alloca i32, align 4
11233 // CHECK7-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
11234 // CHECK7-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
11235 // CHECK7-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
11236 // CHECK7-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
11237 // CHECK7-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
11238 // CHECK7-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
11239 // CHECK7-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
11240 // CHECK7-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
11241 // CHECK7-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
11242 // CHECK7-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
11243 // CHECK7-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
11244 // CHECK7-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
11245 // CHECK7-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
11246 // CHECK7:       cond.true:
11247 // CHECK7-NEXT:    br label [[COND_END:%.*]]
11248 // CHECK7:       cond.false:
11249 // CHECK7-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
11250 // CHECK7-NEXT:    br label [[COND_END]]
11251 // CHECK7:       cond.end:
11252 // CHECK7-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
11253 // CHECK7-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
11254 // CHECK7-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
11255 // CHECK7-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
11256 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
11257 // CHECK7:       omp.inner.for.cond:
11258 // CHECK7-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
11259 // CHECK7-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
11260 // CHECK7-NEXT:    [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
11261 // CHECK7-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
11262 // CHECK7:       omp.inner.for.body:
11263 // CHECK7-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
11264 // CHECK7-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
11265 // CHECK7-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
11266 // CHECK7-NEXT:    store i32 [[ADD]], i32* [[A1]], align 4, !nontemporal !28
11267 // CHECK7-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A1]], align 4, !nontemporal !28
11268 // CHECK7-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
11269 // CHECK7-NEXT:    store i32 [[ADD3]], i32* [[A1]], align 4, !nontemporal !28
11270 // CHECK7-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
11271 // CHECK7:       omp.body.continue:
11272 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
11273 // CHECK7:       omp.inner.for.inc:
11274 // CHECK7-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
11275 // CHECK7-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP9]], 1
11276 // CHECK7-NEXT:    store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4
11277 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP29:![0-9]+]]
11278 // CHECK7:       omp.inner.for.end:
11279 // CHECK7-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
11280 // CHECK7:       omp.loop.exit:
11281 // CHECK7-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
11282 // CHECK7-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
11283 // CHECK7-NEXT:    [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0
11284 // CHECK7-NEXT:    br i1 [[TMP11]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
11285 // CHECK7:       .omp.final.then:
11286 // CHECK7-NEXT:    store i32 10, i32* [[A_ADDR]], align 4
11287 // CHECK7-NEXT:    br label [[DOTOMP_FINAL_DONE]]
11288 // CHECK7:       .omp.final.done:
11289 // CHECK7-NEXT:    ret void
11290 //
11291 //
11292 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111
11293 // CHECK7-SAME: (i32 noundef [[AA:%.*]]) #[[ATTR2]] {
11294 // CHECK7-NEXT:  entry:
11295 // CHECK7-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
11296 // CHECK7-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
11297 // CHECK7-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
11298 // CHECK7-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
11299 // CHECK7-NEXT:    [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
11300 // CHECK7-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
11301 // CHECK7-NEXT:    store i16 [[TMP0]], i16* [[CONV1]], align 2
11302 // CHECK7-NEXT:    [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
11303 // CHECK7-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP1]])
11304 // CHECK7-NEXT:    ret void
11305 //
11306 //
11307 // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..3
11308 // CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR3]] {
11309 // CHECK7-NEXT:  entry:
11310 // CHECK7-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
11311 // CHECK7-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
11312 // CHECK7-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
11313 // CHECK7-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
11314 // CHECK7-NEXT:    [[TMP:%.*]] = alloca i32, align 4
11315 // CHECK7-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
11316 // CHECK7-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
11317 // CHECK7-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
11318 // CHECK7-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
11319 // CHECK7-NEXT:    [[I:%.*]] = alloca i32, align 4
11320 // CHECK7-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
11321 // CHECK7-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
11322 // CHECK7-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
11323 // CHECK7-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
11324 // CHECK7-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
11325 // CHECK7-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
11326 // CHECK7-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
11327 // CHECK7-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
11328 // CHECK7-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
11329 // CHECK7-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
11330 // CHECK7-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
11331 // CHECK7-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
11332 // CHECK7-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
11333 // CHECK7-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
11334 // CHECK7:       cond.true:
11335 // CHECK7-NEXT:    br label [[COND_END:%.*]]
11336 // CHECK7:       cond.false:
11337 // CHECK7-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
11338 // CHECK7-NEXT:    br label [[COND_END]]
11339 // CHECK7:       cond.end:
11340 // CHECK7-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
11341 // CHECK7-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
11342 // CHECK7-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
11343 // CHECK7-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
11344 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
11345 // CHECK7:       omp.inner.for.cond:
11346 // CHECK7-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !31
11347 // CHECK7-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !31
11348 // CHECK7-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
11349 // CHECK7-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
11350 // CHECK7:       omp.inner.for.body:
11351 // CHECK7-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !31
11352 // CHECK7-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
11353 // CHECK7-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
11354 // CHECK7-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !31
11355 // CHECK7-NEXT:    [[TMP8:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !31
11356 // CHECK7-NEXT:    [[CONV2:%.*]] = sext i16 [[TMP8]] to i32
11357 // CHECK7-NEXT:    [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
11358 // CHECK7-NEXT:    [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
11359 // CHECK7-NEXT:    store i16 [[CONV4]], i16* [[CONV]], align 2, !llvm.access.group !31
11360 // CHECK7-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
11361 // CHECK7:       omp.body.continue:
11362 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
11363 // CHECK7:       omp.inner.for.inc:
11364 // CHECK7-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !31
11365 // CHECK7-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP9]], 1
11366 // CHECK7-NEXT:    store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !31
11367 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP32:![0-9]+]]
11368 // CHECK7:       omp.inner.for.end:
11369 // CHECK7-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
11370 // CHECK7:       omp.loop.exit:
11371 // CHECK7-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
11372 // CHECK7-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
11373 // CHECK7-NEXT:    [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0
11374 // CHECK7-NEXT:    br i1 [[TMP11]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
11375 // CHECK7:       .omp.final.then:
11376 // CHECK7-NEXT:    store i32 10, i32* [[I]], align 4
11377 // CHECK7-NEXT:    br label [[DOTOMP_FINAL_DONE]]
11378 // CHECK7:       .omp.final.done:
11379 // CHECK7-NEXT:    ret void
11380 //
11381 //
11382 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118
11383 // CHECK7-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] {
11384 // CHECK7-NEXT:  entry:
11385 // CHECK7-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
11386 // CHECK7-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
11387 // CHECK7-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
11388 // CHECK7-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
11389 // CHECK7-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
11390 // CHECK7-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
11391 // CHECK7-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
11392 // CHECK7-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
11393 // CHECK7-NEXT:    store i32 [[TMP0]], i32* [[A_CASTED]], align 4
11394 // CHECK7-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
11395 // CHECK7-NEXT:    [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
11396 // CHECK7-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
11397 // CHECK7-NEXT:    store i16 [[TMP2]], i16* [[CONV1]], align 2
11398 // CHECK7-NEXT:    [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
11399 // CHECK7-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]])
11400 // CHECK7-NEXT:    ret void
11401 //
11402 //
11403 // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..6
11404 // CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR3]] {
11405 // CHECK7-NEXT:  entry:
11406 // CHECK7-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
11407 // CHECK7-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
11408 // CHECK7-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
11409 // CHECK7-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
11410 // CHECK7-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
11411 // CHECK7-NEXT:    [[TMP:%.*]] = alloca i32, align 4
11412 // CHECK7-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
11413 // CHECK7-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
11414 // CHECK7-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
11415 // CHECK7-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
11416 // CHECK7-NEXT:    [[I:%.*]] = alloca i32, align 4
11417 // CHECK7-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
11418 // CHECK7-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
11419 // CHECK7-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
11420 // CHECK7-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
11421 // CHECK7-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
11422 // CHECK7-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
11423 // CHECK7-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
11424 // CHECK7-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
11425 // CHECK7-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
11426 // CHECK7-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
11427 // CHECK7-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
11428 // CHECK7-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
11429 // CHECK7-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
11430 // CHECK7-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
11431 // CHECK7-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
11432 // CHECK7:       cond.true:
11433 // CHECK7-NEXT:    br label [[COND_END:%.*]]
11434 // CHECK7:       cond.false:
11435 // CHECK7-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
11436 // CHECK7-NEXT:    br label [[COND_END]]
11437 // CHECK7:       cond.end:
11438 // CHECK7-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
11439 // CHECK7-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
11440 // CHECK7-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
11441 // CHECK7-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
11442 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
11443 // CHECK7:       omp.inner.for.cond:
11444 // CHECK7-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !34
11445 // CHECK7-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !34
11446 // CHECK7-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
11447 // CHECK7-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
11448 // CHECK7:       omp.inner.for.body:
11449 // CHECK7-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !34
11450 // CHECK7-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
11451 // CHECK7-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
11452 // CHECK7-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !34
11453 // CHECK7-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !34
11454 // CHECK7-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
11455 // CHECK7-NEXT:    store i32 [[ADD2]], i32* [[A_ADDR]], align 4, !llvm.access.group !34
11456 // CHECK7-NEXT:    [[TMP9:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !34
11457 // CHECK7-NEXT:    [[CONV3:%.*]] = sext i16 [[TMP9]] to i32
11458 // CHECK7-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
11459 // CHECK7-NEXT:    [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
11460 // CHECK7-NEXT:    store i16 [[CONV5]], i16* [[CONV]], align 2, !llvm.access.group !34
11461 // CHECK7-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
11462 // CHECK7:       omp.body.continue:
11463 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
11464 // CHECK7:       omp.inner.for.inc:
11465 // CHECK7-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !34
11466 // CHECK7-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP10]], 1
11467 // CHECK7-NEXT:    store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !34
11468 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP35:![0-9]+]]
11469 // CHECK7:       omp.inner.for.end:
11470 // CHECK7-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
11471 // CHECK7:       omp.loop.exit:
11472 // CHECK7-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
11473 // CHECK7-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
11474 // CHECK7-NEXT:    [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
11475 // CHECK7-NEXT:    br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
11476 // CHECK7:       .omp.final.then:
11477 // CHECK7-NEXT:    store i32 10, i32* [[I]], align 4
11478 // CHECK7-NEXT:    br label [[DOTOMP_FINAL_DONE]]
11479 // CHECK7:       .omp.final.done:
11480 // CHECK7-NEXT:    ret void
11481 //
11482 //
11483 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142
11484 // CHECK7-SAME: (i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] {
11485 // CHECK7-NEXT:  entry:
11486 // CHECK7-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
11487 // CHECK7-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
11488 // CHECK7-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
11489 // CHECK7-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 4
11490 // CHECK7-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
11491 // CHECK7-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
11492 // CHECK7-NEXT:    [[VLA_ADDR4:%.*]] = alloca i32, align 4
11493 // CHECK7-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 4
11494 // CHECK7-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
11495 // CHECK7-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
11496 // CHECK7-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
11497 // CHECK7-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
11498 // CHECK7-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
11499 // CHECK7-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 4
11500 // CHECK7-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
11501 // CHECK7-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
11502 // CHECK7-NEXT:    store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
11503 // CHECK7-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 4
11504 // CHECK7-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
11505 // CHECK7-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
11506 // CHECK7-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
11507 // CHECK7-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
11508 // CHECK7-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
11509 // CHECK7-NEXT:    [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
11510 // CHECK7-NEXT:    [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
11511 // CHECK7-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
11512 // CHECK7-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
11513 // CHECK7-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
11514 // CHECK7-NEXT:    store i32 [[TMP8]], i32* [[A_CASTED]], align 4
11515 // CHECK7-NEXT:    [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4
11516 // CHECK7-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]])
11517 // CHECK7-NEXT:    ret void
11518 //
11519 //
11520 // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..9
11521 // CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR3]] {
11522 // CHECK7-NEXT:  entry:
11523 // CHECK7-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
11524 // CHECK7-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
11525 // CHECK7-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
11526 // CHECK7-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
11527 // CHECK7-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
11528 // CHECK7-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 4
11529 // CHECK7-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
11530 // CHECK7-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
11531 // CHECK7-NEXT:    [[VLA_ADDR4:%.*]] = alloca i32, align 4
11532 // CHECK7-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 4
11533 // CHECK7-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
11534 // CHECK7-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
11535 // CHECK7-NEXT:    [[TMP:%.*]] = alloca i32, align 4
11536 // CHECK7-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
11537 // CHECK7-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
11538 // CHECK7-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
11539 // CHECK7-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
11540 // CHECK7-NEXT:    [[I:%.*]] = alloca i32, align 4
11541 // CHECK7-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
11542 // CHECK7-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
11543 // CHECK7-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
11544 // CHECK7-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
11545 // CHECK7-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
11546 // CHECK7-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 4
11547 // CHECK7-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
11548 // CHECK7-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
11549 // CHECK7-NEXT:    store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
11550 // CHECK7-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 4
11551 // CHECK7-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
11552 // CHECK7-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
11553 // CHECK7-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
11554 // CHECK7-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
11555 // CHECK7-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
11556 // CHECK7-NEXT:    [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
11557 // CHECK7-NEXT:    [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
11558 // CHECK7-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
11559 // CHECK7-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
11560 // CHECK7-NEXT:    [[ARRAYDECAY:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 0
11561 // CHECK7-NEXT:    call void @llvm.assume(i1 true) [ "align"(float* [[ARRAYDECAY]], i32 16) ]
11562 // CHECK7-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
11563 // CHECK7-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
11564 // CHECK7-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
11565 // CHECK7-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
11566 // CHECK7-NEXT:    [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
11567 // CHECK7-NEXT:    [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4
11568 // CHECK7-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
11569 // CHECK7-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
11570 // CHECK7-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP10]], 9
11571 // CHECK7-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
11572 // CHECK7:       cond.true:
11573 // CHECK7-NEXT:    br label [[COND_END:%.*]]
11574 // CHECK7:       cond.false:
11575 // CHECK7-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
11576 // CHECK7-NEXT:    br label [[COND_END]]
11577 // CHECK7:       cond.end:
11578 // CHECK7-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ]
11579 // CHECK7-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
11580 // CHECK7-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
11581 // CHECK7-NEXT:    store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4
11582 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
11583 // CHECK7:       omp.inner.for.cond:
11584 // CHECK7-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !37
11585 // CHECK7-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !37
11586 // CHECK7-NEXT:    [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
11587 // CHECK7-NEXT:    br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
11588 // CHECK7:       omp.inner.for.body:
11589 // CHECK7-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !37
11590 // CHECK7-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1
11591 // CHECK7-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
11592 // CHECK7-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !37
11593 // CHECK7-NEXT:    [[TMP16:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !37
11594 // CHECK7-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP16]], 1
11595 // CHECK7-NEXT:    store i32 [[ADD6]], i32* [[A_ADDR]], align 4, !llvm.access.group !37
11596 // CHECK7-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2
11597 // CHECK7-NEXT:    [[TMP17:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !37
11598 // CHECK7-NEXT:    [[CONV:%.*]] = fpext float [[TMP17]] to double
11599 // CHECK7-NEXT:    [[ADD7:%.*]] = fadd double [[CONV]], 1.000000e+00
11600 // CHECK7-NEXT:    [[CONV8:%.*]] = fptrunc double [[ADD7]] to float
11601 // CHECK7-NEXT:    store float [[CONV8]], float* [[ARRAYIDX]], align 4, !llvm.access.group !37
11602 // CHECK7-NEXT:    [[ARRAYIDX9:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3
11603 // CHECK7-NEXT:    [[TMP18:%.*]] = load float, float* [[ARRAYIDX9]], align 4, !llvm.access.group !37
11604 // CHECK7-NEXT:    [[CONV10:%.*]] = fpext float [[TMP18]] to double
11605 // CHECK7-NEXT:    [[ADD11:%.*]] = fadd double [[CONV10]], 1.000000e+00
11606 // CHECK7-NEXT:    [[CONV12:%.*]] = fptrunc double [[ADD11]] to float
11607 // CHECK7-NEXT:    store float [[CONV12]], float* [[ARRAYIDX9]], align 4, !llvm.access.group !37
11608 // CHECK7-NEXT:    [[ARRAYIDX13:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1
11609 // CHECK7-NEXT:    [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX13]], i32 0, i32 2
11610 // CHECK7-NEXT:    [[TMP19:%.*]] = load double, double* [[ARRAYIDX14]], align 8, !llvm.access.group !37
11611 // CHECK7-NEXT:    [[ADD15:%.*]] = fadd double [[TMP19]], 1.000000e+00
11612 // CHECK7-NEXT:    store double [[ADD15]], double* [[ARRAYIDX14]], align 8, !llvm.access.group !37
11613 // CHECK7-NEXT:    [[TMP20:%.*]] = mul nsw i32 1, [[TMP5]]
11614 // CHECK7-NEXT:    [[ARRAYIDX16:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP20]]
11615 // CHECK7-NEXT:    [[ARRAYIDX17:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX16]], i32 3
11616 // CHECK7-NEXT:    [[TMP21:%.*]] = load double, double* [[ARRAYIDX17]], align 8, !llvm.access.group !37
11617 // CHECK7-NEXT:    [[ADD18:%.*]] = fadd double [[TMP21]], 1.000000e+00
11618 // CHECK7-NEXT:    store double [[ADD18]], double* [[ARRAYIDX17]], align 8, !llvm.access.group !37
11619 // CHECK7-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0
11620 // CHECK7-NEXT:    [[TMP22:%.*]] = load i64, i64* [[X]], align 4, !llvm.access.group !37
11621 // CHECK7-NEXT:    [[ADD19:%.*]] = add nsw i64 [[TMP22]], 1
11622 // CHECK7-NEXT:    store i64 [[ADD19]], i64* [[X]], align 4, !llvm.access.group !37
11623 // CHECK7-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1
11624 // CHECK7-NEXT:    [[TMP23:%.*]] = load i8, i8* [[Y]], align 4, !llvm.access.group !37
11625 // CHECK7-NEXT:    [[CONV20:%.*]] = sext i8 [[TMP23]] to i32
11626 // CHECK7-NEXT:    [[ADD21:%.*]] = add nsw i32 [[CONV20]], 1
11627 // CHECK7-NEXT:    [[CONV22:%.*]] = trunc i32 [[ADD21]] to i8
11628 // CHECK7-NEXT:    store i8 [[CONV22]], i8* [[Y]], align 4, !llvm.access.group !37
11629 // CHECK7-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
11630 // CHECK7:       omp.body.continue:
11631 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
11632 // CHECK7:       omp.inner.for.inc:
11633 // CHECK7-NEXT:    [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !37
11634 // CHECK7-NEXT:    [[ADD23:%.*]] = add nsw i32 [[TMP24]], 1
11635 // CHECK7-NEXT:    store i32 [[ADD23]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !37
11636 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP38:![0-9]+]]
11637 // CHECK7:       omp.inner.for.end:
11638 // CHECK7-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
11639 // CHECK7:       omp.loop.exit:
11640 // CHECK7-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]])
11641 // CHECK7-NEXT:    [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
11642 // CHECK7-NEXT:    [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
11643 // CHECK7-NEXT:    br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
11644 // CHECK7:       .omp.final.then:
11645 // CHECK7-NEXT:    store i32 10, i32* [[I]], align 4
11646 // CHECK7-NEXT:    br label [[DOTOMP_FINAL_DONE]]
11647 // CHECK7:       .omp.final.done:
11648 // CHECK7-NEXT:    ret void
11649 //
11650 //
11651 // CHECK7-LABEL: define {{[^@]+}}@_Z3bari
11652 // CHECK7-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {
11653 // CHECK7-NEXT:  entry:
11654 // CHECK7-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
11655 // CHECK7-NEXT:    [[A:%.*]] = alloca i32, align 4
11656 // CHECK7-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4
11657 // CHECK7-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
11658 // CHECK7-NEXT:    store i32 0, i32* [[A]], align 4
11659 // CHECK7-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
11660 // CHECK7-NEXT:    [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]])
11661 // CHECK7-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
11662 // CHECK7-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
11663 // CHECK7-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
11664 // CHECK7-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
11665 // CHECK7-NEXT:    [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP2]])
11666 // CHECK7-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
11667 // CHECK7-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
11668 // CHECK7-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
11669 // CHECK7-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
11670 // CHECK7-NEXT:    [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]])
11671 // CHECK7-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
11672 // CHECK7-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
11673 // CHECK7-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
11674 // CHECK7-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
11675 // CHECK7-NEXT:    [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]])
11676 // CHECK7-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
11677 // CHECK7-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
11678 // CHECK7-NEXT:    store i32 [[ADD6]], i32* [[A]], align 4
11679 // CHECK7-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
11680 // CHECK7-NEXT:    ret i32 [[TMP8]]
11681 //
11682 //
11683 // CHECK7-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
11684 // CHECK7-SAME: (%struct.S1* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 {
11685 // CHECK7-NEXT:  entry:
11686 // CHECK7-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
11687 // CHECK7-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
11688 // CHECK7-NEXT:    [[B:%.*]] = alloca i32, align 4
11689 // CHECK7-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 4
11690 // CHECK7-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 4
11691 // CHECK7-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
11692 // CHECK7-NEXT:    [[B_CASTED:%.*]] = alloca i32, align 4
11693 // CHECK7-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
11694 // CHECK7-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [6 x i8*], align 4
11695 // CHECK7-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [6 x i8*], align 4
11696 // CHECK7-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [6 x i8*], align 4
11697 // CHECK7-NEXT:    [[DOTOFFLOAD_SIZES:%.*]] = alloca [6 x i64], align 4
11698 // CHECK7-NEXT:    [[TMP:%.*]] = alloca i32, align 4
11699 // CHECK7-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
11700 // CHECK7-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
11701 // CHECK7-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
11702 // CHECK7-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
11703 // CHECK7-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
11704 // CHECK7-NEXT:    store i32 [[ADD]], i32* [[B]], align 4
11705 // CHECK7-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
11706 // CHECK7-NEXT:    [[TMP2:%.*]] = call i8* @llvm.stacksave()
11707 // CHECK7-NEXT:    store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4
11708 // CHECK7-NEXT:    [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]
11709 // CHECK7-NEXT:    [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2
11710 // CHECK7-NEXT:    store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
11711 // CHECK7-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
11712 // CHECK7-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 60
11713 // CHECK7-NEXT:    [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8
11714 // CHECK7-NEXT:    store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
11715 // CHECK7-NEXT:    [[TMP5:%.*]] = load i32, i32* [[B]], align 4
11716 // CHECK7-NEXT:    store i32 [[TMP5]], i32* [[B_CASTED]], align 4
11717 // CHECK7-NEXT:    [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4
11718 // CHECK7-NEXT:    [[TMP7:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
11719 // CHECK7-NEXT:    [[TOBOOL:%.*]] = trunc i8 [[TMP7]] to i1
11720 // CHECK7-NEXT:    [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__CASTED]] to i8*
11721 // CHECK7-NEXT:    [[FROMBOOL2:%.*]] = zext i1 [[TOBOOL]] to i8
11722 // CHECK7-NEXT:    store i8 [[FROMBOOL2]], i8* [[CONV]], align 1
11723 // CHECK7-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
11724 // CHECK7-NEXT:    [[TMP9:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
11725 // CHECK7-NEXT:    [[TOBOOL3:%.*]] = trunc i8 [[TMP9]] to i1
11726 // CHECK7-NEXT:    br i1 [[TOBOOL3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
11727 // CHECK7:       omp_if.then:
11728 // CHECK7-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
11729 // CHECK7-NEXT:    [[TMP10:%.*]] = mul nuw i32 2, [[TMP1]]
11730 // CHECK7-NEXT:    [[TMP11:%.*]] = mul nuw i32 [[TMP10]], 2
11731 // CHECK7-NEXT:    [[TMP12:%.*]] = sext i32 [[TMP11]] to i64
11732 // CHECK7-NEXT:    [[TMP13:%.*]] = bitcast [6 x i64]* [[DOTOFFLOAD_SIZES]] to i8*
11733 // CHECK7-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP13]], i8* align 4 bitcast ([6 x i64]* @.offload_sizes.13 to i8*), i32 48, i1 false)
11734 // CHECK7-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
11735 // CHECK7-NEXT:    [[TMP15:%.*]] = bitcast i8** [[TMP14]] to %struct.S1**
11736 // CHECK7-NEXT:    store %struct.S1* [[THIS1]], %struct.S1** [[TMP15]], align 4
11737 // CHECK7-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
11738 // CHECK7-NEXT:    [[TMP17:%.*]] = bitcast i8** [[TMP16]] to double**
11739 // CHECK7-NEXT:    store double* [[A]], double** [[TMP17]], align 4
11740 // CHECK7-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
11741 // CHECK7-NEXT:    store i8* null, i8** [[TMP18]], align 4
11742 // CHECK7-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
11743 // CHECK7-NEXT:    [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32*
11744 // CHECK7-NEXT:    store i32 [[TMP6]], i32* [[TMP20]], align 4
11745 // CHECK7-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
11746 // CHECK7-NEXT:    [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i32*
11747 // CHECK7-NEXT:    store i32 [[TMP6]], i32* [[TMP22]], align 4
11748 // CHECK7-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
11749 // CHECK7-NEXT:    store i8* null, i8** [[TMP23]], align 4
11750 // CHECK7-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
11751 // CHECK7-NEXT:    [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i32*
11752 // CHECK7-NEXT:    store i32 2, i32* [[TMP25]], align 4
11753 // CHECK7-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
11754 // CHECK7-NEXT:    [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i32*
11755 // CHECK7-NEXT:    store i32 2, i32* [[TMP27]], align 4
11756 // CHECK7-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
11757 // CHECK7-NEXT:    store i8* null, i8** [[TMP28]], align 4
11758 // CHECK7-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
11759 // CHECK7-NEXT:    [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i32*
11760 // CHECK7-NEXT:    store i32 [[TMP1]], i32* [[TMP30]], align 4
11761 // CHECK7-NEXT:    [[TMP31:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
11762 // CHECK7-NEXT:    [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i32*
11763 // CHECK7-NEXT:    store i32 [[TMP1]], i32* [[TMP32]], align 4
11764 // CHECK7-NEXT:    [[TMP33:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
11765 // CHECK7-NEXT:    store i8* null, i8** [[TMP33]], align 4
11766 // CHECK7-NEXT:    [[TMP34:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
11767 // CHECK7-NEXT:    [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i16**
11768 // CHECK7-NEXT:    store i16* [[VLA]], i16** [[TMP35]], align 4
11769 // CHECK7-NEXT:    [[TMP36:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
11770 // CHECK7-NEXT:    [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i16**
11771 // CHECK7-NEXT:    store i16* [[VLA]], i16** [[TMP37]], align 4
11772 // CHECK7-NEXT:    [[TMP38:%.*]] = getelementptr inbounds [6 x i64], [6 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4
11773 // CHECK7-NEXT:    store i64 [[TMP12]], i64* [[TMP38]], align 4
11774 // CHECK7-NEXT:    [[TMP39:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4
11775 // CHECK7-NEXT:    store i8* null, i8** [[TMP39]], align 4
11776 // CHECK7-NEXT:    [[TMP40:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 5
11777 // CHECK7-NEXT:    [[TMP41:%.*]] = bitcast i8** [[TMP40]] to i32*
11778 // CHECK7-NEXT:    store i32 [[TMP8]], i32* [[TMP41]], align 4
11779 // CHECK7-NEXT:    [[TMP42:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 5
11780 // CHECK7-NEXT:    [[TMP43:%.*]] = bitcast i8** [[TMP42]] to i32*
11781 // CHECK7-NEXT:    store i32 [[TMP8]], i32* [[TMP43]], align 4
11782 // CHECK7-NEXT:    [[TMP44:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 5
11783 // CHECK7-NEXT:    store i8* null, i8** [[TMP44]], align 4
11784 // CHECK7-NEXT:    [[TMP45:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
11785 // CHECK7-NEXT:    [[TMP46:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
11786 // CHECK7-NEXT:    [[TMP47:%.*]] = getelementptr inbounds [6 x i64], [6 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
11787 // CHECK7-NEXT:    call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10)
11788 // CHECK7-NEXT:    [[TMP48:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215.region_id, i32 6, i8** [[TMP45]], i8** [[TMP46]], i64* [[TMP47]], i64* getelementptr inbounds ([6 x i64], [6 x i64]* @.offload_maptypes.14, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1)
11789 // CHECK7-NEXT:    [[TMP49:%.*]] = icmp ne i32 [[TMP48]], 0
11790 // CHECK7-NEXT:    br i1 [[TMP49]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
11791 // CHECK7:       omp_offload.failed:
11792 // CHECK7-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215(%struct.S1* [[THIS1]], i32 [[TMP6]], i32 2, i32 [[TMP1]], i16* [[VLA]], i32 [[TMP8]]) #[[ATTR4]]
11793 // CHECK7-NEXT:    br label [[OMP_OFFLOAD_CONT]]
11794 // CHECK7:       omp_offload.cont:
11795 // CHECK7-NEXT:    br label [[OMP_IF_END:%.*]]
11796 // CHECK7:       omp_if.else:
11797 // CHECK7-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215(%struct.S1* [[THIS1]], i32 [[TMP6]], i32 2, i32 [[TMP1]], i16* [[VLA]], i32 [[TMP8]]) #[[ATTR4]]
11798 // CHECK7-NEXT:    br label [[OMP_IF_END]]
11799 // CHECK7:       omp_if.end:
11800 // CHECK7-NEXT:    [[TMP50:%.*]] = mul nsw i32 1, [[TMP1]]
11801 // CHECK7-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP50]]
11802 // CHECK7-NEXT:    [[ARRAYIDX4:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
11803 // CHECK7-NEXT:    [[TMP51:%.*]] = load i16, i16* [[ARRAYIDX4]], align 2
11804 // CHECK7-NEXT:    [[CONV5:%.*]] = sext i16 [[TMP51]] to i32
11805 // CHECK7-NEXT:    [[TMP52:%.*]] = load i32, i32* [[B]], align 4
11806 // CHECK7-NEXT:    [[ADD6:%.*]] = add nsw i32 [[CONV5]], [[TMP52]]
11807 // CHECK7-NEXT:    [[TMP53:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
11808 // CHECK7-NEXT:    call void @llvm.stackrestore(i8* [[TMP53]])
11809 // CHECK7-NEXT:    ret i32 [[ADD6]]
11810 //
11811 //
11812 // CHECK7-LABEL: define {{[^@]+}}@_ZL7fstatici
11813 // CHECK7-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {
11814 // CHECK7-NEXT:  entry:
11815 // CHECK7-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
11816 // CHECK7-NEXT:    [[A:%.*]] = alloca i32, align 4
11817 // CHECK7-NEXT:    [[AA:%.*]] = alloca i16, align 2
11818 // CHECK7-NEXT:    [[AAA:%.*]] = alloca i8, align 1
11819 // CHECK7-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
11820 // CHECK7-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
11821 // CHECK7-NEXT:    [[N_CASTED:%.*]] = alloca i32, align 4
11822 // CHECK7-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
11823 // CHECK7-NEXT:    [[AAA_CASTED:%.*]] = alloca i32, align 4
11824 // CHECK7-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4
11825 // CHECK7-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4
11826 // CHECK7-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4
11827 // CHECK7-NEXT:    [[TMP:%.*]] = alloca i32, align 4
11828 // CHECK7-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
11829 // CHECK7-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
11830 // CHECK7-NEXT:    [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4
11831 // CHECK7-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
11832 // CHECK7-NEXT:    store i32 0, i32* [[A]], align 4
11833 // CHECK7-NEXT:    store i16 0, i16* [[AA]], align 2
11834 // CHECK7-NEXT:    store i8 0, i8* [[AAA]], align 1
11835 // CHECK7-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
11836 // CHECK7-NEXT:    store i32 [[TMP0]], i32* [[A_CASTED]], align 4
11837 // CHECK7-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
11838 // CHECK7-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
11839 // CHECK7-NEXT:    store i32 [[TMP2]], i32* [[N_CASTED]], align 4
11840 // CHECK7-NEXT:    [[TMP3:%.*]] = load i32, i32* [[N_CASTED]], align 4
11841 // CHECK7-NEXT:    [[TMP4:%.*]] = load i16, i16* [[AA]], align 2
11842 // CHECK7-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
11843 // CHECK7-NEXT:    store i16 [[TMP4]], i16* [[CONV]], align 2
11844 // CHECK7-NEXT:    [[TMP5:%.*]] = load i32, i32* [[AA_CASTED]], align 4
11845 // CHECK7-NEXT:    [[TMP6:%.*]] = load i8, i8* [[AAA]], align 1
11846 // CHECK7-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
11847 // CHECK7-NEXT:    store i8 [[TMP6]], i8* [[CONV1]], align 1
11848 // CHECK7-NEXT:    [[TMP7:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
11849 // CHECK7-NEXT:    [[TMP8:%.*]] = load i32, i32* [[N_ADDR]], align 4
11850 // CHECK7-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP8]], 50
11851 // CHECK7-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
11852 // CHECK7:       omp_if.then:
11853 // CHECK7-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
11854 // CHECK7-NEXT:    [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32*
11855 // CHECK7-NEXT:    store i32 [[TMP1]], i32* [[TMP10]], align 4
11856 // CHECK7-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
11857 // CHECK7-NEXT:    [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32*
11858 // CHECK7-NEXT:    store i32 [[TMP1]], i32* [[TMP12]], align 4
11859 // CHECK7-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
11860 // CHECK7-NEXT:    store i8* null, i8** [[TMP13]], align 4
11861 // CHECK7-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
11862 // CHECK7-NEXT:    [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32*
11863 // CHECK7-NEXT:    store i32 [[TMP3]], i32* [[TMP15]], align 4
11864 // CHECK7-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
11865 // CHECK7-NEXT:    [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32*
11866 // CHECK7-NEXT:    store i32 [[TMP3]], i32* [[TMP17]], align 4
11867 // CHECK7-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
11868 // CHECK7-NEXT:    store i8* null, i8** [[TMP18]], align 4
11869 // CHECK7-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
11870 // CHECK7-NEXT:    [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32*
11871 // CHECK7-NEXT:    store i32 [[TMP5]], i32* [[TMP20]], align 4
11872 // CHECK7-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
11873 // CHECK7-NEXT:    [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i32*
11874 // CHECK7-NEXT:    store i32 [[TMP5]], i32* [[TMP22]], align 4
11875 // CHECK7-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
11876 // CHECK7-NEXT:    store i8* null, i8** [[TMP23]], align 4
11877 // CHECK7-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
11878 // CHECK7-NEXT:    [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i32*
11879 // CHECK7-NEXT:    store i32 [[TMP7]], i32* [[TMP25]], align 4
11880 // CHECK7-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
11881 // CHECK7-NEXT:    [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i32*
11882 // CHECK7-NEXT:    store i32 [[TMP7]], i32* [[TMP27]], align 4
11883 // CHECK7-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
11884 // CHECK7-NEXT:    store i8* null, i8** [[TMP28]], align 4
11885 // CHECK7-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
11886 // CHECK7-NEXT:    [[TMP30:%.*]] = bitcast i8** [[TMP29]] to [10 x i32]**
11887 // CHECK7-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP30]], align 4
11888 // CHECK7-NEXT:    [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
11889 // CHECK7-NEXT:    [[TMP32:%.*]] = bitcast i8** [[TMP31]] to [10 x i32]**
11890 // CHECK7-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP32]], align 4
11891 // CHECK7-NEXT:    [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4
11892 // CHECK7-NEXT:    store i8* null, i8** [[TMP33]], align 4
11893 // CHECK7-NEXT:    [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
11894 // CHECK7-NEXT:    [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
11895 // CHECK7-NEXT:    [[TMP36:%.*]] = load i32, i32* [[A]], align 4
11896 // CHECK7-NEXT:    store i32 [[TMP36]], i32* [[DOTCAPTURE_EXPR_]], align 4
11897 // CHECK7-NEXT:    [[TMP37:%.*]] = load i32, i32* [[N_ADDR]], align 4
11898 // CHECK7-NEXT:    store i32 [[TMP37]], i32* [[DOTCAPTURE_EXPR_2]], align 4
11899 // CHECK7-NEXT:    [[TMP38:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
11900 // CHECK7-NEXT:    [[TMP39:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
11901 // CHECK7-NEXT:    [[SUB:%.*]] = sub i32 [[TMP38]], [[TMP39]]
11902 // CHECK7-NEXT:    [[SUB4:%.*]] = sub i32 [[SUB]], 1
11903 // CHECK7-NEXT:    [[ADD:%.*]] = add i32 [[SUB4]], 1
11904 // CHECK7-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], 1
11905 // CHECK7-NEXT:    [[SUB5:%.*]] = sub i32 [[DIV]], 1
11906 // CHECK7-NEXT:    store i32 [[SUB5]], i32* [[DOTCAPTURE_EXPR_3]], align 4
11907 // CHECK7-NEXT:    [[TMP40:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
11908 // CHECK7-NEXT:    [[ADD6:%.*]] = add i32 [[TMP40]], 1
11909 // CHECK7-NEXT:    [[TMP41:%.*]] = zext i32 [[ADD6]] to i64
11910 // CHECK7-NEXT:    call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 [[TMP41]])
11911 // CHECK7-NEXT:    [[TMP42:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197.region_id, i32 5, i8** [[TMP34]], i8** [[TMP35]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes.16, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.17, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1)
11912 // CHECK7-NEXT:    [[TMP43:%.*]] = icmp ne i32 [[TMP42]], 0
11913 // CHECK7-NEXT:    br i1 [[TMP43]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
11914 // CHECK7:       omp_offload.failed:
11915 // CHECK7-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], i32 [[TMP7]], [10 x i32]* [[B]]) #[[ATTR4]]
11916 // CHECK7-NEXT:    br label [[OMP_OFFLOAD_CONT]]
11917 // CHECK7:       omp_offload.cont:
11918 // CHECK7-NEXT:    br label [[OMP_IF_END:%.*]]
11919 // CHECK7:       omp_if.else:
11920 // CHECK7-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], i32 [[TMP7]], [10 x i32]* [[B]]) #[[ATTR4]]
11921 // CHECK7-NEXT:    br label [[OMP_IF_END]]
11922 // CHECK7:       omp_if.end:
11923 // CHECK7-NEXT:    [[TMP44:%.*]] = load i32, i32* [[A]], align 4
11924 // CHECK7-NEXT:    ret i32 [[TMP44]]
11925 //
11926 //
11927 // CHECK7-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
11928 // CHECK7-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat {
11929 // CHECK7-NEXT:  entry:
11930 // CHECK7-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
11931 // CHECK7-NEXT:    [[A:%.*]] = alloca i32, align 4
11932 // CHECK7-NEXT:    [[AA:%.*]] = alloca i16, align 2
11933 // CHECK7-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
11934 // CHECK7-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
11935 // CHECK7-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
11936 // CHECK7-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4
11937 // CHECK7-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4
11938 // CHECK7-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4
11939 // CHECK7-NEXT:    [[TMP:%.*]] = alloca i32, align 4
11940 // CHECK7-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
11941 // CHECK7-NEXT:    store i32 0, i32* [[A]], align 4
11942 // CHECK7-NEXT:    store i16 0, i16* [[AA]], align 2
11943 // CHECK7-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
11944 // CHECK7-NEXT:    store i32 [[TMP0]], i32* [[A_CASTED]], align 4
11945 // CHECK7-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
11946 // CHECK7-NEXT:    [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
11947 // CHECK7-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
11948 // CHECK7-NEXT:    store i16 [[TMP2]], i16* [[CONV]], align 2
11949 // CHECK7-NEXT:    [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
11950 // CHECK7-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
11951 // CHECK7-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40
11952 // CHECK7-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
11953 // CHECK7:       omp_if.then:
11954 // CHECK7-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
11955 // CHECK7-NEXT:    [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i32*
11956 // CHECK7-NEXT:    store i32 [[TMP1]], i32* [[TMP6]], align 4
11957 // CHECK7-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
11958 // CHECK7-NEXT:    [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32*
11959 // CHECK7-NEXT:    store i32 [[TMP1]], i32* [[TMP8]], align 4
11960 // CHECK7-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
11961 // CHECK7-NEXT:    store i8* null, i8** [[TMP9]], align 4
11962 // CHECK7-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
11963 // CHECK7-NEXT:    [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i32*
11964 // CHECK7-NEXT:    store i32 [[TMP3]], i32* [[TMP11]], align 4
11965 // CHECK7-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
11966 // CHECK7-NEXT:    [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32*
11967 // CHECK7-NEXT:    store i32 [[TMP3]], i32* [[TMP13]], align 4
11968 // CHECK7-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
11969 // CHECK7-NEXT:    store i8* null, i8** [[TMP14]], align 4
11970 // CHECK7-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
11971 // CHECK7-NEXT:    [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]**
11972 // CHECK7-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 4
11973 // CHECK7-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
11974 // CHECK7-NEXT:    [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]**
11975 // CHECK7-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 4
11976 // CHECK7-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
11977 // CHECK7-NEXT:    store i8* null, i8** [[TMP19]], align 4
11978 // CHECK7-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
11979 // CHECK7-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
11980 // CHECK7-NEXT:    call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10)
11981 // CHECK7-NEXT:    [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.19, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.20, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1)
11982 // CHECK7-NEXT:    [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0
11983 // CHECK7-NEXT:    br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
11984 // CHECK7:       omp_offload.failed:
11985 // CHECK7-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]]
11986 // CHECK7-NEXT:    br label [[OMP_OFFLOAD_CONT]]
11987 // CHECK7:       omp_offload.cont:
11988 // CHECK7-NEXT:    br label [[OMP_IF_END:%.*]]
11989 // CHECK7:       omp_if.else:
11990 // CHECK7-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]]
11991 // CHECK7-NEXT:    br label [[OMP_IF_END]]
11992 // CHECK7:       omp_if.end:
11993 // CHECK7-NEXT:    [[TMP24:%.*]] = load i32, i32* [[A]], align 4
11994 // CHECK7-NEXT:    ret i32 [[TMP24]]
11995 //
11996 //
11997 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215
11998 // CHECK7-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] {
11999 // CHECK7-NEXT:  entry:
12000 // CHECK7-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
12001 // CHECK7-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
12002 // CHECK7-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
12003 // CHECK7-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
12004 // CHECK7-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 4
12005 // CHECK7-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
12006 // CHECK7-NEXT:    [[B_CASTED:%.*]] = alloca i32, align 4
12007 // CHECK7-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
12008 // CHECK7-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
12009 // CHECK7-NEXT:    store i32 [[B]], i32* [[B_ADDR]], align 4
12010 // CHECK7-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
12011 // CHECK7-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
12012 // CHECK7-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 4
12013 // CHECK7-NEXT:    store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
12014 // CHECK7-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
12015 // CHECK7-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
12016 // CHECK7-NEXT:    [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
12017 // CHECK7-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
12018 // CHECK7-NEXT:    [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8*
12019 // CHECK7-NEXT:    [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4
12020 // CHECK7-NEXT:    store i32 [[TMP4]], i32* [[B_CASTED]], align 4
12021 // CHECK7-NEXT:    [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4
12022 // CHECK7-NEXT:    [[TMP6:%.*]] = load i8, i8* [[CONV]], align 1
12023 // CHECK7-NEXT:    [[TOBOOL:%.*]] = trunc i8 [[TMP6]] to i1
12024 // CHECK7-NEXT:    [[CONV3:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__CASTED]] to i8*
12025 // CHECK7-NEXT:    [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
12026 // CHECK7-NEXT:    store i8 [[FROMBOOL]], i8* [[CONV3]], align 1
12027 // CHECK7-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
12028 // CHECK7-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*, i32)* @.omp_outlined..12 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]], i32 [[TMP7]])
12029 // CHECK7-NEXT:    ret void
12030 //
12031 //
12032 // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..12
12033 // CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] {
12034 // CHECK7-NEXT:  entry:
12035 // CHECK7-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
12036 // CHECK7-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
12037 // CHECK7-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
12038 // CHECK7-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
12039 // CHECK7-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
12040 // CHECK7-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
12041 // CHECK7-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 4
12042 // CHECK7-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
12043 // CHECK7-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
12044 // CHECK7-NEXT:    [[TMP:%.*]] = alloca i32, align 4
12045 // CHECK7-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
12046 // CHECK7-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
12047 // CHECK7-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
12048 // CHECK7-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
12049 // CHECK7-NEXT:    [[I:%.*]] = alloca i32, align 4
12050 // CHECK7-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
12051 // CHECK7-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
12052 // CHECK7-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
12053 // CHECK7-NEXT:    store i32 [[B]], i32* [[B_ADDR]], align 4
12054 // CHECK7-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
12055 // CHECK7-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
12056 // CHECK7-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 4
12057 // CHECK7-NEXT:    store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
12058 // CHECK7-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
12059 // CHECK7-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
12060 // CHECK7-NEXT:    [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
12061 // CHECK7-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
12062 // CHECK7-NEXT:    [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8*
12063 // CHECK7-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
12064 // CHECK7-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
12065 // CHECK7-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
12066 // CHECK7-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
12067 // CHECK7-NEXT:    [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
12068 // CHECK7-NEXT:    [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
12069 // CHECK7-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
12070 // CHECK7-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
12071 // CHECK7-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 9
12072 // CHECK7-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
12073 // CHECK7:       cond.true:
12074 // CHECK7-NEXT:    br label [[COND_END:%.*]]
12075 // CHECK7:       cond.false:
12076 // CHECK7-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
12077 // CHECK7-NEXT:    br label [[COND_END]]
12078 // CHECK7:       cond.end:
12079 // CHECK7-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
12080 // CHECK7-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
12081 // CHECK7-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
12082 // CHECK7-NEXT:    store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
12083 // CHECK7-NEXT:    [[TMP9:%.*]] = load i8, i8* [[CONV]], align 1
12084 // CHECK7-NEXT:    [[TOBOOL:%.*]] = trunc i8 [[TMP9]] to i1
12085 // CHECK7-NEXT:    br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
12086 // CHECK7:       omp_if.then:
12087 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
12088 // CHECK7:       omp.inner.for.cond:
12089 // CHECK7-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !40
12090 // CHECK7-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !40
12091 // CHECK7-NEXT:    [[CMP3:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]
12092 // CHECK7-NEXT:    br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
12093 // CHECK7:       omp.inner.for.body:
12094 // CHECK7-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !40
12095 // CHECK7-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1
12096 // CHECK7-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
12097 // CHECK7-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !40
12098 // CHECK7-NEXT:    [[TMP13:%.*]] = load i32, i32* [[B_ADDR]], align 4, !llvm.access.group !40
12099 // CHECK7-NEXT:    [[CONV4:%.*]] = sitofp i32 [[TMP13]] to double
12100 // CHECK7-NEXT:    [[ADD5:%.*]] = fadd double [[CONV4]], 1.500000e+00
12101 // CHECK7-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
12102 // CHECK7-NEXT:    store double [[ADD5]], double* [[A]], align 4, !llvm.access.group !40
12103 // CHECK7-NEXT:    [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
12104 // CHECK7-NEXT:    [[TMP14:%.*]] = load double, double* [[A6]], align 4, !llvm.access.group !40
12105 // CHECK7-NEXT:    [[INC:%.*]] = fadd double [[TMP14]], 1.000000e+00
12106 // CHECK7-NEXT:    store double [[INC]], double* [[A6]], align 4, !llvm.access.group !40
12107 // CHECK7-NEXT:    [[CONV7:%.*]] = fptosi double [[INC]] to i16
12108 // CHECK7-NEXT:    [[TMP15:%.*]] = mul nsw i32 1, [[TMP2]]
12109 // CHECK7-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP15]]
12110 // CHECK7-NEXT:    [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
12111 // CHECK7-NEXT:    store i16 [[CONV7]], i16* [[ARRAYIDX8]], align 2, !llvm.access.group !40
12112 // CHECK7-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
12113 // CHECK7:       omp.body.continue:
12114 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
12115 // CHECK7:       omp.inner.for.inc:
12116 // CHECK7-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !40
12117 // CHECK7-NEXT:    [[ADD9:%.*]] = add nsw i32 [[TMP16]], 1
12118 // CHECK7-NEXT:    store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !40
12119 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP41:![0-9]+]]
12120 // CHECK7:       omp.inner.for.end:
12121 // CHECK7-NEXT:    br label [[OMP_IF_END:%.*]]
12122 // CHECK7:       omp_if.else:
12123 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_COND10:%.*]]
12124 // CHECK7:       omp.inner.for.cond10:
12125 // CHECK7-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
12126 // CHECK7-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
12127 // CHECK7-NEXT:    [[CMP11:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]]
12128 // CHECK7-NEXT:    br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY12:%.*]], label [[OMP_INNER_FOR_END26:%.*]]
12129 // CHECK7:       omp.inner.for.body12:
12130 // CHECK7-NEXT:    [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
12131 // CHECK7-NEXT:    [[MUL13:%.*]] = mul nsw i32 [[TMP19]], 1
12132 // CHECK7-NEXT:    [[ADD14:%.*]] = add nsw i32 0, [[MUL13]]
12133 // CHECK7-NEXT:    store i32 [[ADD14]], i32* [[I]], align 4
12134 // CHECK7-NEXT:    [[TMP20:%.*]] = load i32, i32* [[B_ADDR]], align 4
12135 // CHECK7-NEXT:    [[CONV15:%.*]] = sitofp i32 [[TMP20]] to double
12136 // CHECK7-NEXT:    [[ADD16:%.*]] = fadd double [[CONV15]], 1.500000e+00
12137 // CHECK7-NEXT:    [[A17:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
12138 // CHECK7-NEXT:    store double [[ADD16]], double* [[A17]], align 4
12139 // CHECK7-NEXT:    [[A18:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
12140 // CHECK7-NEXT:    [[TMP21:%.*]] = load double, double* [[A18]], align 4
12141 // CHECK7-NEXT:    [[INC19:%.*]] = fadd double [[TMP21]], 1.000000e+00
12142 // CHECK7-NEXT:    store double [[INC19]], double* [[A18]], align 4
12143 // CHECK7-NEXT:    [[CONV20:%.*]] = fptosi double [[INC19]] to i16
12144 // CHECK7-NEXT:    [[TMP22:%.*]] = mul nsw i32 1, [[TMP2]]
12145 // CHECK7-NEXT:    [[ARRAYIDX21:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP22]]
12146 // CHECK7-NEXT:    [[ARRAYIDX22:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX21]], i32 1
12147 // CHECK7-NEXT:    store i16 [[CONV20]], i16* [[ARRAYIDX22]], align 2
12148 // CHECK7-NEXT:    br label [[OMP_BODY_CONTINUE23:%.*]]
12149 // CHECK7:       omp.body.continue23:
12150 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_INC24:%.*]]
12151 // CHECK7:       omp.inner.for.inc24:
12152 // CHECK7-NEXT:    [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
12153 // CHECK7-NEXT:    [[ADD25:%.*]] = add nsw i32 [[TMP23]], 1
12154 // CHECK7-NEXT:    store i32 [[ADD25]], i32* [[DOTOMP_IV]], align 4
12155 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_COND10]], !llvm.loop [[LOOP43:![0-9]+]]
12156 // CHECK7:       omp.inner.for.end26:
12157 // CHECK7-NEXT:    br label [[OMP_IF_END]]
12158 // CHECK7:       omp_if.end:
12159 // CHECK7-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
12160 // CHECK7:       omp.loop.exit:
12161 // CHECK7-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
12162 // CHECK7-NEXT:    [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
12163 // CHECK7-NEXT:    [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0
12164 // CHECK7-NEXT:    br i1 [[TMP25]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
12165 // CHECK7:       .omp.final.then:
12166 // CHECK7-NEXT:    store i32 10, i32* [[I]], align 4
12167 // CHECK7-NEXT:    br label [[DOTOMP_FINAL_DONE]]
12168 // CHECK7:       .omp.final.done:
12169 // CHECK7-NEXT:    ret void
12170 //
12171 //
12172 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197
12173 // CHECK7-SAME: (i32 noundef [[A:%.*]], i32 noundef [[N:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
12174 // CHECK7-NEXT:  entry:
12175 // CHECK7-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
12176 // CHECK7-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
12177 // CHECK7-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
12178 // CHECK7-NEXT:    [[AAA_ADDR:%.*]] = alloca i32, align 4
12179 // CHECK7-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
12180 // CHECK7-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
12181 // CHECK7-NEXT:    [[N_CASTED:%.*]] = alloca i32, align 4
12182 // CHECK7-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
12183 // CHECK7-NEXT:    [[AAA_CASTED:%.*]] = alloca i32, align 4
12184 // CHECK7-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
12185 // CHECK7-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
12186 // CHECK7-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
12187 // CHECK7-NEXT:    store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
12188 // CHECK7-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
12189 // CHECK7-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
12190 // CHECK7-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
12191 // CHECK7-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
12192 // CHECK7-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
12193 // CHECK7-NEXT:    store i32 [[TMP1]], i32* [[A_CASTED]], align 4
12194 // CHECK7-NEXT:    [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
12195 // CHECK7-NEXT:    [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
12196 // CHECK7-NEXT:    store i32 [[TMP3]], i32* [[N_CASTED]], align 4
12197 // CHECK7-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_CASTED]], align 4
12198 // CHECK7-NEXT:    [[TMP5:%.*]] = load i16, i16* [[CONV]], align 2
12199 // CHECK7-NEXT:    [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
12200 // CHECK7-NEXT:    store i16 [[TMP5]], i16* [[CONV2]], align 2
12201 // CHECK7-NEXT:    [[TMP6:%.*]] = load i32, i32* [[AA_CASTED]], align 4
12202 // CHECK7-NEXT:    [[TMP7:%.*]] = load i8, i8* [[CONV1]], align 1
12203 // CHECK7-NEXT:    [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
12204 // CHECK7-NEXT:    store i8 [[TMP7]], i8* [[CONV3]], align 1
12205 // CHECK7-NEXT:    [[TMP8:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
12206 // CHECK7-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, [10 x i32]*)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP8]], [10 x i32]* [[TMP0]])
12207 // CHECK7-NEXT:    ret void
12208 //
12209 //
12210 // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..15
12211 // CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[N:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] {
12212 // CHECK7-NEXT:  entry:
12213 // CHECK7-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
12214 // CHECK7-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
12215 // CHECK7-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
12216 // CHECK7-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
12217 // CHECK7-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
12218 // CHECK7-NEXT:    [[AAA_ADDR:%.*]] = alloca i32, align 4
12219 // CHECK7-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
12220 // CHECK7-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
12221 // CHECK7-NEXT:    [[TMP:%.*]] = alloca i32, align 4
12222 // CHECK7-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
12223 // CHECK7-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
12224 // CHECK7-NEXT:    [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4
12225 // CHECK7-NEXT:    [[I:%.*]] = alloca i32, align 4
12226 // CHECK7-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
12227 // CHECK7-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
12228 // CHECK7-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
12229 // CHECK7-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
12230 // CHECK7-NEXT:    [[I6:%.*]] = alloca i32, align 4
12231 // CHECK7-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
12232 // CHECK7-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
12233 // CHECK7-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
12234 // CHECK7-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
12235 // CHECK7-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
12236 // CHECK7-NEXT:    store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
12237 // CHECK7-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
12238 // CHECK7-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
12239 // CHECK7-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
12240 // CHECK7-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
12241 // CHECK7-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
12242 // CHECK7-NEXT:    store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
12243 // CHECK7-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
12244 // CHECK7-NEXT:    store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4
12245 // CHECK7-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
12246 // CHECK7-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
12247 // CHECK7-NEXT:    [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]]
12248 // CHECK7-NEXT:    [[SUB4:%.*]] = sub i32 [[SUB]], 1
12249 // CHECK7-NEXT:    [[ADD:%.*]] = add i32 [[SUB4]], 1
12250 // CHECK7-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], 1
12251 // CHECK7-NEXT:    [[SUB5:%.*]] = sub i32 [[DIV]], 1
12252 // CHECK7-NEXT:    store i32 [[SUB5]], i32* [[DOTCAPTURE_EXPR_3]], align 4
12253 // CHECK7-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
12254 // CHECK7-NEXT:    store i32 [[TMP5]], i32* [[I]], align 4
12255 // CHECK7-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
12256 // CHECK7-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
12257 // CHECK7-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]]
12258 // CHECK7-NEXT:    br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
12259 // CHECK7:       omp.precond.then:
12260 // CHECK7-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
12261 // CHECK7-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
12262 // CHECK7-NEXT:    store i32 [[TMP8]], i32* [[DOTOMP_UB]], align 4
12263 // CHECK7-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
12264 // CHECK7-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
12265 // CHECK7-NEXT:    [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
12266 // CHECK7-NEXT:    [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
12267 // CHECK7-NEXT:    call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
12268 // CHECK7-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
12269 // CHECK7-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
12270 // CHECK7-NEXT:    [[CMP7:%.*]] = icmp ugt i32 [[TMP11]], [[TMP12]]
12271 // CHECK7-NEXT:    br i1 [[CMP7]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
12272 // CHECK7:       cond.true:
12273 // CHECK7-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
12274 // CHECK7-NEXT:    br label [[COND_END:%.*]]
12275 // CHECK7:       cond.false:
12276 // CHECK7-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
12277 // CHECK7-NEXT:    br label [[COND_END]]
12278 // CHECK7:       cond.end:
12279 // CHECK7-NEXT:    [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ]
12280 // CHECK7-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
12281 // CHECK7-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
12282 // CHECK7-NEXT:    store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4
12283 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
12284 // CHECK7:       omp.inner.for.cond:
12285 // CHECK7-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !45
12286 // CHECK7-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !45
12287 // CHECK7-NEXT:    [[ADD8:%.*]] = add i32 [[TMP17]], 1
12288 // CHECK7-NEXT:    [[CMP9:%.*]] = icmp ult i32 [[TMP16]], [[ADD8]]
12289 // CHECK7-NEXT:    br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
12290 // CHECK7:       omp.inner.for.body:
12291 // CHECK7-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group !45
12292 // CHECK7-NEXT:    [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !45
12293 // CHECK7-NEXT:    [[MUL:%.*]] = mul i32 [[TMP19]], 1
12294 // CHECK7-NEXT:    [[ADD10:%.*]] = add i32 [[TMP18]], [[MUL]]
12295 // CHECK7-NEXT:    store i32 [[ADD10]], i32* [[I6]], align 4, !llvm.access.group !45
12296 // CHECK7-NEXT:    [[TMP20:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !45
12297 // CHECK7-NEXT:    [[ADD11:%.*]] = add nsw i32 [[TMP20]], 1
12298 // CHECK7-NEXT:    store i32 [[ADD11]], i32* [[A_ADDR]], align 4, !llvm.access.group !45
12299 // CHECK7-NEXT:    [[TMP21:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !45
12300 // CHECK7-NEXT:    [[CONV12:%.*]] = sext i16 [[TMP21]] to i32
12301 // CHECK7-NEXT:    [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1
12302 // CHECK7-NEXT:    [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16
12303 // CHECK7-NEXT:    store i16 [[CONV14]], i16* [[CONV]], align 2, !llvm.access.group !45
12304 // CHECK7-NEXT:    [[TMP22:%.*]] = load i8, i8* [[CONV1]], align 1, !llvm.access.group !45
12305 // CHECK7-NEXT:    [[CONV15:%.*]] = sext i8 [[TMP22]] to i32
12306 // CHECK7-NEXT:    [[ADD16:%.*]] = add nsw i32 [[CONV15]], 1
12307 // CHECK7-NEXT:    [[CONV17:%.*]] = trunc i32 [[ADD16]] to i8
12308 // CHECK7-NEXT:    store i8 [[CONV17]], i8* [[CONV1]], align 1, !llvm.access.group !45
12309 // CHECK7-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
12310 // CHECK7-NEXT:    [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !45
12311 // CHECK7-NEXT:    [[ADD18:%.*]] = add nsw i32 [[TMP23]], 1
12312 // CHECK7-NEXT:    store i32 [[ADD18]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !45
12313 // CHECK7-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
12314 // CHECK7:       omp.body.continue:
12315 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
12316 // CHECK7:       omp.inner.for.inc:
12317 // CHECK7-NEXT:    [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !45
12318 // CHECK7-NEXT:    [[ADD19:%.*]] = add i32 [[TMP24]], 1
12319 // CHECK7-NEXT:    store i32 [[ADD19]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !45
12320 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP46:![0-9]+]]
12321 // CHECK7:       omp.inner.for.end:
12322 // CHECK7-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
12323 // CHECK7:       omp.loop.exit:
12324 // CHECK7-NEXT:    [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
12325 // CHECK7-NEXT:    [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4
12326 // CHECK7-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]])
12327 // CHECK7-NEXT:    [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
12328 // CHECK7-NEXT:    [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0
12329 // CHECK7-NEXT:    br i1 [[TMP28]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
12330 // CHECK7:       .omp.final.then:
12331 // CHECK7-NEXT:    [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
12332 // CHECK7-NEXT:    [[TMP30:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
12333 // CHECK7-NEXT:    [[TMP31:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
12334 // CHECK7-NEXT:    [[SUB20:%.*]] = sub i32 [[TMP30]], [[TMP31]]
12335 // CHECK7-NEXT:    [[SUB21:%.*]] = sub i32 [[SUB20]], 1
12336 // CHECK7-NEXT:    [[ADD22:%.*]] = add i32 [[SUB21]], 1
12337 // CHECK7-NEXT:    [[DIV23:%.*]] = udiv i32 [[ADD22]], 1
12338 // CHECK7-NEXT:    [[MUL24:%.*]] = mul i32 [[DIV23]], 1
12339 // CHECK7-NEXT:    [[ADD25:%.*]] = add i32 [[TMP29]], [[MUL24]]
12340 // CHECK7-NEXT:    store i32 [[ADD25]], i32* [[I6]], align 4
12341 // CHECK7-NEXT:    br label [[DOTOMP_FINAL_DONE]]
12342 // CHECK7:       .omp.final.done:
12343 // CHECK7-NEXT:    br label [[OMP_PRECOND_END]]
12344 // CHECK7:       omp.precond.end:
12345 // CHECK7-NEXT:    ret void
12346 //
12347 //
12348 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180
12349 // CHECK7-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
12350 // CHECK7-NEXT:  entry:
12351 // CHECK7-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
12352 // CHECK7-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
12353 // CHECK7-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
12354 // CHECK7-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
12355 // CHECK7-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
12356 // CHECK7-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
12357 // CHECK7-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
12358 // CHECK7-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
12359 // CHECK7-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
12360 // CHECK7-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
12361 // CHECK7-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
12362 // CHECK7-NEXT:    store i32 [[TMP1]], i32* [[A_CASTED]], align 4
12363 // CHECK7-NEXT:    [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
12364 // CHECK7-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
12365 // CHECK7-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
12366 // CHECK7-NEXT:    store i16 [[TMP3]], i16* [[CONV1]], align 2
12367 // CHECK7-NEXT:    [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
12368 // CHECK7-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..18 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]])
12369 // CHECK7-NEXT:    ret void
12370 //
12371 //
12372 // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..18
12373 // CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] {
12374 // CHECK7-NEXT:  entry:
12375 // CHECK7-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
12376 // CHECK7-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
12377 // CHECK7-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
12378 // CHECK7-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
12379 // CHECK7-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
12380 // CHECK7-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
12381 // CHECK7-NEXT:    [[TMP:%.*]] = alloca i32, align 4
12382 // CHECK7-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
12383 // CHECK7-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
12384 // CHECK7-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
12385 // CHECK7-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
12386 // CHECK7-NEXT:    [[I:%.*]] = alloca i32, align 4
12387 // CHECK7-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
12388 // CHECK7-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
12389 // CHECK7-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
12390 // CHECK7-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
12391 // CHECK7-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
12392 // CHECK7-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
12393 // CHECK7-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
12394 // CHECK7-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
12395 // CHECK7-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
12396 // CHECK7-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
12397 // CHECK7-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
12398 // CHECK7-NEXT:    [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
12399 // CHECK7-NEXT:    [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
12400 // CHECK7-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
12401 // CHECK7-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
12402 // CHECK7-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9
12403 // CHECK7-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
12404 // CHECK7:       cond.true:
12405 // CHECK7-NEXT:    br label [[COND_END:%.*]]
12406 // CHECK7:       cond.false:
12407 // CHECK7-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
12408 // CHECK7-NEXT:    br label [[COND_END]]
12409 // CHECK7:       cond.end:
12410 // CHECK7-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
12411 // CHECK7-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
12412 // CHECK7-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
12413 // CHECK7-NEXT:    store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
12414 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
12415 // CHECK7:       omp.inner.for.cond:
12416 // CHECK7-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !48
12417 // CHECK7-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !48
12418 // CHECK7-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
12419 // CHECK7-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
12420 // CHECK7:       omp.inner.for.body:
12421 // CHECK7-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !48
12422 // CHECK7-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
12423 // CHECK7-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
12424 // CHECK7-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !48
12425 // CHECK7-NEXT:    [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !48
12426 // CHECK7-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
12427 // CHECK7-NEXT:    store i32 [[ADD2]], i32* [[A_ADDR]], align 4, !llvm.access.group !48
12428 // CHECK7-NEXT:    [[TMP10:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !48
12429 // CHECK7-NEXT:    [[CONV3:%.*]] = sext i16 [[TMP10]] to i32
12430 // CHECK7-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
12431 // CHECK7-NEXT:    [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
12432 // CHECK7-NEXT:    store i16 [[CONV5]], i16* [[CONV]], align 2, !llvm.access.group !48
12433 // CHECK7-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
12434 // CHECK7-NEXT:    [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !48
12435 // CHECK7-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1
12436 // CHECK7-NEXT:    store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !48
12437 // CHECK7-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
12438 // CHECK7:       omp.body.continue:
12439 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
12440 // CHECK7:       omp.inner.for.inc:
12441 // CHECK7-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !48
12442 // CHECK7-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP12]], 1
12443 // CHECK7-NEXT:    store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !48
12444 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP49:![0-9]+]]
12445 // CHECK7:       omp.inner.for.end:
12446 // CHECK7-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
12447 // CHECK7:       omp.loop.exit:
12448 // CHECK7-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
12449 // CHECK7-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
12450 // CHECK7-NEXT:    [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
12451 // CHECK7-NEXT:    br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
12452 // CHECK7:       .omp.final.then:
12453 // CHECK7-NEXT:    store i32 10, i32* [[I]], align 4
12454 // CHECK7-NEXT:    br label [[DOTOMP_FINAL_DONE]]
12455 // CHECK7:       .omp.final.done:
12456 // CHECK7-NEXT:    ret void
12457 //
12458 //
12459 // CHECK7-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
12460 // CHECK7-SAME: () #[[ATTR5]] {
12461 // CHECK7-NEXT:  entry:
12462 // CHECK7-NEXT:    call void @__tgt_register_requires(i64 1)
12463 // CHECK7-NEXT:    ret void
12464 //
12465 //
12466 // CHECK8-LABEL: define {{[^@]+}}@_Z3fooi
12467 // CHECK8-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0:[0-9]+]] {
12468 // CHECK8-NEXT:  entry:
12469 // CHECK8-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
12470 // CHECK8-NEXT:    [[A:%.*]] = alloca i32, align 4
12471 // CHECK8-NEXT:    [[AA:%.*]] = alloca i16, align 2
12472 // CHECK8-NEXT:    [[B:%.*]] = alloca [10 x float], align 4
12473 // CHECK8-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 4
12474 // CHECK8-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 4
12475 // CHECK8-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 8
12476 // CHECK8-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i32, align 4
12477 // CHECK8-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4
12478 // CHECK8-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
12479 // CHECK8-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
12480 // CHECK8-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
12481 // CHECK8-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
12482 // CHECK8-NEXT:    [[DOTCAPTURE_EXPR__CASTED3:%.*]] = alloca i32, align 4
12483 // CHECK8-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4
12484 // CHECK8-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4
12485 // CHECK8-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4
12486 // CHECK8-NEXT:    [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4
12487 // CHECK8-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
12488 // CHECK8-NEXT:    [[AA_CASTED4:%.*]] = alloca i32, align 4
12489 // CHECK8-NEXT:    [[DOTOFFLOAD_BASEPTRS6:%.*]] = alloca [1 x i8*], align 4
12490 // CHECK8-NEXT:    [[DOTOFFLOAD_PTRS7:%.*]] = alloca [1 x i8*], align 4
12491 // CHECK8-NEXT:    [[DOTOFFLOAD_MAPPERS8:%.*]] = alloca [1 x i8*], align 4
12492 // CHECK8-NEXT:    [[TMP:%.*]] = alloca i32, align 4
12493 // CHECK8-NEXT:    [[A_CASTED9:%.*]] = alloca i32, align 4
12494 // CHECK8-NEXT:    [[AA_CASTED10:%.*]] = alloca i32, align 4
12495 // CHECK8-NEXT:    [[DOTOFFLOAD_BASEPTRS12:%.*]] = alloca [2 x i8*], align 4
12496 // CHECK8-NEXT:    [[DOTOFFLOAD_PTRS13:%.*]] = alloca [2 x i8*], align 4
12497 // CHECK8-NEXT:    [[DOTOFFLOAD_MAPPERS14:%.*]] = alloca [2 x i8*], align 4
12498 // CHECK8-NEXT:    [[_TMP15:%.*]] = alloca i32, align 4
12499 // CHECK8-NEXT:    [[A_CASTED18:%.*]] = alloca i32, align 4
12500 // CHECK8-NEXT:    [[DOTOFFLOAD_BASEPTRS21:%.*]] = alloca [9 x i8*], align 4
12501 // CHECK8-NEXT:    [[DOTOFFLOAD_PTRS22:%.*]] = alloca [9 x i8*], align 4
12502 // CHECK8-NEXT:    [[DOTOFFLOAD_MAPPERS23:%.*]] = alloca [9 x i8*], align 4
12503 // CHECK8-NEXT:    [[DOTOFFLOAD_SIZES:%.*]] = alloca [9 x i64], align 4
12504 // CHECK8-NEXT:    [[_TMP24:%.*]] = alloca i32, align 4
12505 // CHECK8-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]])
12506 // CHECK8-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
12507 // CHECK8-NEXT:    store i32 0, i32* [[A]], align 4
12508 // CHECK8-NEXT:    store i16 0, i16* [[AA]], align 2
12509 // CHECK8-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
12510 // CHECK8-NEXT:    [[TMP2:%.*]] = call i8* @llvm.stacksave()
12511 // CHECK8-NEXT:    store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4
12512 // CHECK8-NEXT:    [[VLA:%.*]] = alloca float, i32 [[TMP1]], align 4
12513 // CHECK8-NEXT:    store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
12514 // CHECK8-NEXT:    [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
12515 // CHECK8-NEXT:    [[TMP4:%.*]] = mul nuw i32 5, [[TMP3]]
12516 // CHECK8-NEXT:    [[VLA1:%.*]] = alloca double, i32 [[TMP4]], align 8
12517 // CHECK8-NEXT:    store i32 [[TMP3]], i32* [[__VLA_EXPR1]], align 4
12518 // CHECK8-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
12519 // CHECK8-NEXT:    store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_]], align 4
12520 // CHECK8-NEXT:    [[TMP6:%.*]] = load i32, i32* [[A]], align 4
12521 // CHECK8-NEXT:    store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_2]], align 4
12522 // CHECK8-NEXT:    [[TMP7:%.*]] = load i16, i16* [[AA]], align 2
12523 // CHECK8-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
12524 // CHECK8-NEXT:    store i16 [[TMP7]], i16* [[CONV]], align 2
12525 // CHECK8-NEXT:    [[TMP8:%.*]] = load i32, i32* [[AA_CASTED]], align 4
12526 // CHECK8-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
12527 // CHECK8-NEXT:    store i32 [[TMP9]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
12528 // CHECK8-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
12529 // CHECK8-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
12530 // CHECK8-NEXT:    store i32 [[TMP11]], i32* [[DOTCAPTURE_EXPR__CASTED3]], align 4
12531 // CHECK8-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED3]], align 4
12532 // CHECK8-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
12533 // CHECK8-NEXT:    [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i32*
12534 // CHECK8-NEXT:    store i32 [[TMP8]], i32* [[TMP14]], align 4
12535 // CHECK8-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
12536 // CHECK8-NEXT:    [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i32*
12537 // CHECK8-NEXT:    store i32 [[TMP8]], i32* [[TMP16]], align 4
12538 // CHECK8-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
12539 // CHECK8-NEXT:    store i8* null, i8** [[TMP17]], align 4
12540 // CHECK8-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
12541 // CHECK8-NEXT:    [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32*
12542 // CHECK8-NEXT:    store i32 [[TMP10]], i32* [[TMP19]], align 4
12543 // CHECK8-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
12544 // CHECK8-NEXT:    [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32*
12545 // CHECK8-NEXT:    store i32 [[TMP10]], i32* [[TMP21]], align 4
12546 // CHECK8-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
12547 // CHECK8-NEXT:    store i8* null, i8** [[TMP22]], align 4
12548 // CHECK8-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
12549 // CHECK8-NEXT:    [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i32*
12550 // CHECK8-NEXT:    store i32 [[TMP12]], i32* [[TMP24]], align 4
12551 // CHECK8-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
12552 // CHECK8-NEXT:    [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i32*
12553 // CHECK8-NEXT:    store i32 [[TMP12]], i32* [[TMP26]], align 4
12554 // CHECK8-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
12555 // CHECK8-NEXT:    store i8* null, i8** [[TMP27]], align 4
12556 // CHECK8-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
12557 // CHECK8-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
12558 // CHECK8-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 0
12559 // CHECK8-NEXT:    [[TMP31:%.*]] = load i16, i16* [[AA]], align 2
12560 // CHECK8-NEXT:    store i16 [[TMP31]], i16* [[TMP30]], align 4
12561 // CHECK8-NEXT:    [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 1
12562 // CHECK8-NEXT:    [[TMP33:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
12563 // CHECK8-NEXT:    store i32 [[TMP33]], i32* [[TMP32]], align 4
12564 // CHECK8-NEXT:    [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 2
12565 // CHECK8-NEXT:    [[TMP35:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
12566 // CHECK8-NEXT:    store i32 [[TMP35]], i32* [[TMP34]], align 4
12567 // CHECK8-NEXT:    [[TMP36:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 1, i32 72, i32 12, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1)
12568 // CHECK8-NEXT:    [[TMP37:%.*]] = bitcast i8* [[TMP36]] to %struct.kmp_task_t_with_privates*
12569 // CHECK8-NEXT:    [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP37]], i32 0, i32 0
12570 // CHECK8-NEXT:    [[TMP39:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP38]], i32 0, i32 0
12571 // CHECK8-NEXT:    [[TMP40:%.*]] = load i8*, i8** [[TMP39]], align 4
12572 // CHECK8-NEXT:    [[TMP41:%.*]] = bitcast %struct.anon* [[AGG_CAPTURED]] to i8*
12573 // CHECK8-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP40]], i8* align 4 [[TMP41]], i32 12, i1 false)
12574 // CHECK8-NEXT:    [[TMP42:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP37]], i32 0, i32 1
12575 // CHECK8-NEXT:    [[TMP43:%.*]] = bitcast i8* [[TMP40]] to %struct.anon*
12576 // CHECK8-NEXT:    [[TMP44:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 0
12577 // CHECK8-NEXT:    [[TMP45:%.*]] = bitcast [3 x i64]* [[TMP44]] to i8*
12578 // CHECK8-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP45]], i8* align 4 bitcast ([3 x i64]* @.offload_sizes to i8*), i32 24, i1 false)
12579 // CHECK8-NEXT:    [[TMP46:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 1
12580 // CHECK8-NEXT:    [[TMP47:%.*]] = bitcast [3 x i8*]* [[TMP46]] to i8*
12581 // CHECK8-NEXT:    [[TMP48:%.*]] = bitcast i8** [[TMP28]] to i8*
12582 // CHECK8-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP47]], i8* align 4 [[TMP48]], i32 12, i1 false)
12583 // CHECK8-NEXT:    [[TMP49:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 2
12584 // CHECK8-NEXT:    [[TMP50:%.*]] = bitcast [3 x i8*]* [[TMP49]] to i8*
12585 // CHECK8-NEXT:    [[TMP51:%.*]] = bitcast i8** [[TMP29]] to i8*
12586 // CHECK8-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP50]], i8* align 4 [[TMP51]], i32 12, i1 false)
12587 // CHECK8-NEXT:    [[TMP52:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 3
12588 // CHECK8-NEXT:    [[TMP53:%.*]] = load i16, i16* [[AA]], align 2
12589 // CHECK8-NEXT:    store i16 [[TMP53]], i16* [[TMP52]], align 4
12590 // CHECK8-NEXT:    [[TMP54:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i8* [[TMP36]])
12591 // CHECK8-NEXT:    [[TMP55:%.*]] = load i32, i32* [[A]], align 4
12592 // CHECK8-NEXT:    store i32 [[TMP55]], i32* [[A_CASTED]], align 4
12593 // CHECK8-NEXT:    [[TMP56:%.*]] = load i32, i32* [[A_CASTED]], align 4
12594 // CHECK8-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l102(i32 [[TMP56]]) #[[ATTR4:[0-9]+]]
12595 // CHECK8-NEXT:    [[TMP57:%.*]] = load i16, i16* [[AA]], align 2
12596 // CHECK8-NEXT:    [[CONV5:%.*]] = bitcast i32* [[AA_CASTED4]] to i16*
12597 // CHECK8-NEXT:    store i16 [[TMP57]], i16* [[CONV5]], align 2
12598 // CHECK8-NEXT:    [[TMP58:%.*]] = load i32, i32* [[AA_CASTED4]], align 4
12599 // CHECK8-NEXT:    [[TMP59:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0
12600 // CHECK8-NEXT:    [[TMP60:%.*]] = bitcast i8** [[TMP59]] to i32*
12601 // CHECK8-NEXT:    store i32 [[TMP58]], i32* [[TMP60]], align 4
12602 // CHECK8-NEXT:    [[TMP61:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0
12603 // CHECK8-NEXT:    [[TMP62:%.*]] = bitcast i8** [[TMP61]] to i32*
12604 // CHECK8-NEXT:    store i32 [[TMP58]], i32* [[TMP62]], align 4
12605 // CHECK8-NEXT:    [[TMP63:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS8]], i32 0, i32 0
12606 // CHECK8-NEXT:    store i8* null, i8** [[TMP63]], align 4
12607 // CHECK8-NEXT:    [[TMP64:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0
12608 // CHECK8-NEXT:    [[TMP65:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0
12609 // CHECK8-NEXT:    call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10)
12610 // CHECK8-NEXT:    [[TMP66:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.region_id, i32 1, i8** [[TMP64]], i8** [[TMP65]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.4, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.5, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1)
12611 // CHECK8-NEXT:    [[TMP67:%.*]] = icmp ne i32 [[TMP66]], 0
12612 // CHECK8-NEXT:    br i1 [[TMP67]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
12613 // CHECK8:       omp_offload.failed:
12614 // CHECK8-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111(i32 [[TMP58]]) #[[ATTR4]]
12615 // CHECK8-NEXT:    br label [[OMP_OFFLOAD_CONT]]
12616 // CHECK8:       omp_offload.cont:
12617 // CHECK8-NEXT:    [[TMP68:%.*]] = load i32, i32* [[A]], align 4
12618 // CHECK8-NEXT:    store i32 [[TMP68]], i32* [[A_CASTED9]], align 4
12619 // CHECK8-NEXT:    [[TMP69:%.*]] = load i32, i32* [[A_CASTED9]], align 4
12620 // CHECK8-NEXT:    [[TMP70:%.*]] = load i16, i16* [[AA]], align 2
12621 // CHECK8-NEXT:    [[CONV11:%.*]] = bitcast i32* [[AA_CASTED10]] to i16*
12622 // CHECK8-NEXT:    store i16 [[TMP70]], i16* [[CONV11]], align 2
12623 // CHECK8-NEXT:    [[TMP71:%.*]] = load i32, i32* [[AA_CASTED10]], align 4
12624 // CHECK8-NEXT:    [[TMP72:%.*]] = load i32, i32* [[N_ADDR]], align 4
12625 // CHECK8-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP72]], 10
12626 // CHECK8-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
12627 // CHECK8:       omp_if.then:
12628 // CHECK8-NEXT:    [[TMP73:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS12]], i32 0, i32 0
12629 // CHECK8-NEXT:    [[TMP74:%.*]] = bitcast i8** [[TMP73]] to i32*
12630 // CHECK8-NEXT:    store i32 [[TMP69]], i32* [[TMP74]], align 4
12631 // CHECK8-NEXT:    [[TMP75:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS13]], i32 0, i32 0
12632 // CHECK8-NEXT:    [[TMP76:%.*]] = bitcast i8** [[TMP75]] to i32*
12633 // CHECK8-NEXT:    store i32 [[TMP69]], i32* [[TMP76]], align 4
12634 // CHECK8-NEXT:    [[TMP77:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS14]], i32 0, i32 0
12635 // CHECK8-NEXT:    store i8* null, i8** [[TMP77]], align 4
12636 // CHECK8-NEXT:    [[TMP78:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS12]], i32 0, i32 1
12637 // CHECK8-NEXT:    [[TMP79:%.*]] = bitcast i8** [[TMP78]] to i32*
12638 // CHECK8-NEXT:    store i32 [[TMP71]], i32* [[TMP79]], align 4
12639 // CHECK8-NEXT:    [[TMP80:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS13]], i32 0, i32 1
12640 // CHECK8-NEXT:    [[TMP81:%.*]] = bitcast i8** [[TMP80]] to i32*
12641 // CHECK8-NEXT:    store i32 [[TMP71]], i32* [[TMP81]], align 4
12642 // CHECK8-NEXT:    [[TMP82:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS14]], i32 0, i32 1
12643 // CHECK8-NEXT:    store i8* null, i8** [[TMP82]], align 4
12644 // CHECK8-NEXT:    [[TMP83:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS12]], i32 0, i32 0
12645 // CHECK8-NEXT:    [[TMP84:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS13]], i32 0, i32 0
12646 // CHECK8-NEXT:    call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10)
12647 // CHECK8-NEXT:    [[TMP85:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.region_id, i32 2, i8** [[TMP83]], i8** [[TMP84]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.7, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.8, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1)
12648 // CHECK8-NEXT:    [[TMP86:%.*]] = icmp ne i32 [[TMP85]], 0
12649 // CHECK8-NEXT:    br i1 [[TMP86]], label [[OMP_OFFLOAD_FAILED16:%.*]], label [[OMP_OFFLOAD_CONT17:%.*]]
12650 // CHECK8:       omp_offload.failed16:
12651 // CHECK8-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i32 [[TMP69]], i32 [[TMP71]]) #[[ATTR4]]
12652 // CHECK8-NEXT:    br label [[OMP_OFFLOAD_CONT17]]
12653 // CHECK8:       omp_offload.cont17:
12654 // CHECK8-NEXT:    br label [[OMP_IF_END:%.*]]
12655 // CHECK8:       omp_if.else:
12656 // CHECK8-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i32 [[TMP69]], i32 [[TMP71]]) #[[ATTR4]]
12657 // CHECK8-NEXT:    br label [[OMP_IF_END]]
12658 // CHECK8:       omp_if.end:
12659 // CHECK8-NEXT:    [[TMP87:%.*]] = load i32, i32* [[A]], align 4
12660 // CHECK8-NEXT:    store i32 [[TMP87]], i32* [[A_CASTED18]], align 4
12661 // CHECK8-NEXT:    [[TMP88:%.*]] = load i32, i32* [[A_CASTED18]], align 4
12662 // CHECK8-NEXT:    [[TMP89:%.*]] = load i32, i32* [[N_ADDR]], align 4
12663 // CHECK8-NEXT:    [[CMP19:%.*]] = icmp sgt i32 [[TMP89]], 20
12664 // CHECK8-NEXT:    br i1 [[CMP19]], label [[OMP_IF_THEN20:%.*]], label [[OMP_IF_ELSE27:%.*]]
12665 // CHECK8:       omp_if.then20:
12666 // CHECK8-NEXT:    [[TMP90:%.*]] = mul nuw i32 [[TMP1]], 4
12667 // CHECK8-NEXT:    [[TMP91:%.*]] = sext i32 [[TMP90]] to i64
12668 // CHECK8-NEXT:    [[TMP92:%.*]] = mul nuw i32 5, [[TMP3]]
12669 // CHECK8-NEXT:    [[TMP93:%.*]] = mul nuw i32 [[TMP92]], 8
12670 // CHECK8-NEXT:    [[TMP94:%.*]] = sext i32 [[TMP93]] to i64
12671 // CHECK8-NEXT:    [[TMP95:%.*]] = bitcast [9 x i64]* [[DOTOFFLOAD_SIZES]] to i8*
12672 // CHECK8-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP95]], i8* align 4 bitcast ([9 x i64]* @.offload_sizes.10 to i8*), i32 72, i1 false)
12673 // CHECK8-NEXT:    [[TMP96:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 0
12674 // CHECK8-NEXT:    [[TMP97:%.*]] = bitcast i8** [[TMP96]] to i32*
12675 // CHECK8-NEXT:    store i32 [[TMP88]], i32* [[TMP97]], align 4
12676 // CHECK8-NEXT:    [[TMP98:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 0
12677 // CHECK8-NEXT:    [[TMP99:%.*]] = bitcast i8** [[TMP98]] to i32*
12678 // CHECK8-NEXT:    store i32 [[TMP88]], i32* [[TMP99]], align 4
12679 // CHECK8-NEXT:    [[TMP100:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i32 0, i32 0
12680 // CHECK8-NEXT:    store i8* null, i8** [[TMP100]], align 4
12681 // CHECK8-NEXT:    [[TMP101:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 1
12682 // CHECK8-NEXT:    [[TMP102:%.*]] = bitcast i8** [[TMP101]] to [10 x float]**
12683 // CHECK8-NEXT:    store [10 x float]* [[B]], [10 x float]** [[TMP102]], align 4
12684 // CHECK8-NEXT:    [[TMP103:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 1
12685 // CHECK8-NEXT:    [[TMP104:%.*]] = bitcast i8** [[TMP103]] to [10 x float]**
12686 // CHECK8-NEXT:    store [10 x float]* [[B]], [10 x float]** [[TMP104]], align 4
12687 // CHECK8-NEXT:    [[TMP105:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i32 0, i32 1
12688 // CHECK8-NEXT:    store i8* null, i8** [[TMP105]], align 4
12689 // CHECK8-NEXT:    [[TMP106:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 2
12690 // CHECK8-NEXT:    [[TMP107:%.*]] = bitcast i8** [[TMP106]] to i32*
12691 // CHECK8-NEXT:    store i32 [[TMP1]], i32* [[TMP107]], align 4
12692 // CHECK8-NEXT:    [[TMP108:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 2
12693 // CHECK8-NEXT:    [[TMP109:%.*]] = bitcast i8** [[TMP108]] to i32*
12694 // CHECK8-NEXT:    store i32 [[TMP1]], i32* [[TMP109]], align 4
12695 // CHECK8-NEXT:    [[TMP110:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i32 0, i32 2
12696 // CHECK8-NEXT:    store i8* null, i8** [[TMP110]], align 4
12697 // CHECK8-NEXT:    [[TMP111:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 3
12698 // CHECK8-NEXT:    [[TMP112:%.*]] = bitcast i8** [[TMP111]] to float**
12699 // CHECK8-NEXT:    store float* [[VLA]], float** [[TMP112]], align 4
12700 // CHECK8-NEXT:    [[TMP113:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 3
12701 // CHECK8-NEXT:    [[TMP114:%.*]] = bitcast i8** [[TMP113]] to float**
12702 // CHECK8-NEXT:    store float* [[VLA]], float** [[TMP114]], align 4
12703 // CHECK8-NEXT:    [[TMP115:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3
12704 // CHECK8-NEXT:    store i64 [[TMP91]], i64* [[TMP115]], align 4
12705 // CHECK8-NEXT:    [[TMP116:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i32 0, i32 3
12706 // CHECK8-NEXT:    store i8* null, i8** [[TMP116]], align 4
12707 // CHECK8-NEXT:    [[TMP117:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 4
12708 // CHECK8-NEXT:    [[TMP118:%.*]] = bitcast i8** [[TMP117]] to [5 x [10 x double]]**
12709 // CHECK8-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP118]], align 4
12710 // CHECK8-NEXT:    [[TMP119:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 4
12711 // CHECK8-NEXT:    [[TMP120:%.*]] = bitcast i8** [[TMP119]] to [5 x [10 x double]]**
12712 // CHECK8-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP120]], align 4
12713 // CHECK8-NEXT:    [[TMP121:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i32 0, i32 4
12714 // CHECK8-NEXT:    store i8* null, i8** [[TMP121]], align 4
12715 // CHECK8-NEXT:    [[TMP122:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 5
12716 // CHECK8-NEXT:    [[TMP123:%.*]] = bitcast i8** [[TMP122]] to i32*
12717 // CHECK8-NEXT:    store i32 5, i32* [[TMP123]], align 4
12718 // CHECK8-NEXT:    [[TMP124:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 5
12719 // CHECK8-NEXT:    [[TMP125:%.*]] = bitcast i8** [[TMP124]] to i32*
12720 // CHECK8-NEXT:    store i32 5, i32* [[TMP125]], align 4
12721 // CHECK8-NEXT:    [[TMP126:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i32 0, i32 5
12722 // CHECK8-NEXT:    store i8* null, i8** [[TMP126]], align 4
12723 // CHECK8-NEXT:    [[TMP127:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 6
12724 // CHECK8-NEXT:    [[TMP128:%.*]] = bitcast i8** [[TMP127]] to i32*
12725 // CHECK8-NEXT:    store i32 [[TMP3]], i32* [[TMP128]], align 4
12726 // CHECK8-NEXT:    [[TMP129:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 6
12727 // CHECK8-NEXT:    [[TMP130:%.*]] = bitcast i8** [[TMP129]] to i32*
12728 // CHECK8-NEXT:    store i32 [[TMP3]], i32* [[TMP130]], align 4
12729 // CHECK8-NEXT:    [[TMP131:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i32 0, i32 6
12730 // CHECK8-NEXT:    store i8* null, i8** [[TMP131]], align 4
12731 // CHECK8-NEXT:    [[TMP132:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 7
12732 // CHECK8-NEXT:    [[TMP133:%.*]] = bitcast i8** [[TMP132]] to double**
12733 // CHECK8-NEXT:    store double* [[VLA1]], double** [[TMP133]], align 4
12734 // CHECK8-NEXT:    [[TMP134:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 7
12735 // CHECK8-NEXT:    [[TMP135:%.*]] = bitcast i8** [[TMP134]] to double**
12736 // CHECK8-NEXT:    store double* [[VLA1]], double** [[TMP135]], align 4
12737 // CHECK8-NEXT:    [[TMP136:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7
12738 // CHECK8-NEXT:    store i64 [[TMP94]], i64* [[TMP136]], align 4
12739 // CHECK8-NEXT:    [[TMP137:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i32 0, i32 7
12740 // CHECK8-NEXT:    store i8* null, i8** [[TMP137]], align 4
12741 // CHECK8-NEXT:    [[TMP138:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 8
12742 // CHECK8-NEXT:    [[TMP139:%.*]] = bitcast i8** [[TMP138]] to %struct.TT**
12743 // CHECK8-NEXT:    store %struct.TT* [[D]], %struct.TT** [[TMP139]], align 4
12744 // CHECK8-NEXT:    [[TMP140:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 8
12745 // CHECK8-NEXT:    [[TMP141:%.*]] = bitcast i8** [[TMP140]] to %struct.TT**
12746 // CHECK8-NEXT:    store %struct.TT* [[D]], %struct.TT** [[TMP141]], align 4
12747 // CHECK8-NEXT:    [[TMP142:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i32 0, i32 8
12748 // CHECK8-NEXT:    store i8* null, i8** [[TMP142]], align 4
12749 // CHECK8-NEXT:    [[TMP143:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 0
12750 // CHECK8-NEXT:    [[TMP144:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 0
12751 // CHECK8-NEXT:    [[TMP145:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
12752 // CHECK8-NEXT:    call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10)
12753 // CHECK8-NEXT:    [[TMP146:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142.region_id, i32 9, i8** [[TMP143]], i8** [[TMP144]], i64* [[TMP145]], i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_maptypes.11, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1)
12754 // CHECK8-NEXT:    [[TMP147:%.*]] = icmp ne i32 [[TMP146]], 0
12755 // CHECK8-NEXT:    br i1 [[TMP147]], label [[OMP_OFFLOAD_FAILED25:%.*]], label [[OMP_OFFLOAD_CONT26:%.*]]
12756 // CHECK8:       omp_offload.failed25:
12757 // CHECK8-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i32 [[TMP88]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR4]]
12758 // CHECK8-NEXT:    br label [[OMP_OFFLOAD_CONT26]]
12759 // CHECK8:       omp_offload.cont26:
12760 // CHECK8-NEXT:    br label [[OMP_IF_END28:%.*]]
12761 // CHECK8:       omp_if.else27:
12762 // CHECK8-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i32 [[TMP88]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR4]]
12763 // CHECK8-NEXT:    br label [[OMP_IF_END28]]
12764 // CHECK8:       omp_if.end28:
12765 // CHECK8-NEXT:    [[TMP148:%.*]] = load i32, i32* [[A]], align 4
12766 // CHECK8-NEXT:    [[TMP149:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
12767 // CHECK8-NEXT:    call void @llvm.stackrestore(i8* [[TMP149]])
12768 // CHECK8-NEXT:    ret i32 [[TMP148]]
12769 //
12770 //
12771 // CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97
12772 // CHECK8-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]], i32 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] {
12773 // CHECK8-NEXT:  entry:
12774 // CHECK8-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
12775 // CHECK8-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
12776 // CHECK8-NEXT:    [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4
12777 // CHECK8-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
12778 // CHECK8-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]])
12779 // CHECK8-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
12780 // CHECK8-NEXT:    store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
12781 // CHECK8-NEXT:    store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4
12782 // CHECK8-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
12783 // CHECK8-NEXT:    [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
12784 // CHECK8-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4
12785 // CHECK8-NEXT:    call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
12786 // CHECK8-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
12787 // CHECK8-NEXT:    [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
12788 // CHECK8-NEXT:    store i16 [[TMP3]], i16* [[CONV3]], align 2
12789 // CHECK8-NEXT:    [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
12790 // CHECK8-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]])
12791 // CHECK8-NEXT:    ret void
12792 //
12793 //
12794 // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined.
12795 // CHECK8-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR3:[0-9]+]] {
12796 // CHECK8-NEXT:  entry:
12797 // CHECK8-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
12798 // CHECK8-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
12799 // CHECK8-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
12800 // CHECK8-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
12801 // CHECK8-NEXT:    [[TMP:%.*]] = alloca i32, align 4
12802 // CHECK8-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
12803 // CHECK8-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
12804 // CHECK8-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
12805 // CHECK8-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
12806 // CHECK8-NEXT:    [[I:%.*]] = alloca i32, align 4
12807 // CHECK8-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
12808 // CHECK8-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
12809 // CHECK8-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
12810 // CHECK8-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
12811 // CHECK8-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
12812 // CHECK8-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
12813 // CHECK8-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
12814 // CHECK8-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
12815 // CHECK8-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
12816 // CHECK8-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
12817 // CHECK8-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
12818 // CHECK8-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
12819 // CHECK8-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
12820 // CHECK8-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
12821 // CHECK8:       cond.true:
12822 // CHECK8-NEXT:    br label [[COND_END:%.*]]
12823 // CHECK8:       cond.false:
12824 // CHECK8-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
12825 // CHECK8-NEXT:    br label [[COND_END]]
12826 // CHECK8:       cond.end:
12827 // CHECK8-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
12828 // CHECK8-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
12829 // CHECK8-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
12830 // CHECK8-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
12831 // CHECK8-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
12832 // CHECK8:       omp.inner.for.cond:
12833 // CHECK8-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
12834 // CHECK8-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !11
12835 // CHECK8-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
12836 // CHECK8-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
12837 // CHECK8:       omp.inner.for.body:
12838 // CHECK8-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
12839 // CHECK8-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
12840 // CHECK8-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
12841 // CHECK8-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11
12842 // CHECK8-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
12843 // CHECK8:       omp.body.continue:
12844 // CHECK8-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
12845 // CHECK8:       omp.inner.for.inc:
12846 // CHECK8-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
12847 // CHECK8-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
12848 // CHECK8-NEXT:    store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
12849 // CHECK8-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]
12850 // CHECK8:       omp.inner.for.end:
12851 // CHECK8-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
12852 // CHECK8:       omp.loop.exit:
12853 // CHECK8-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
12854 // CHECK8-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
12855 // CHECK8-NEXT:    [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0
12856 // CHECK8-NEXT:    br i1 [[TMP10]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
12857 // CHECK8:       .omp.final.then:
12858 // CHECK8-NEXT:    store i32 10, i32* [[I]], align 4
12859 // CHECK8-NEXT:    br label [[DOTOMP_FINAL_DONE]]
12860 // CHECK8:       .omp.final.done:
12861 // CHECK8-NEXT:    ret void
12862 //
12863 //
12864 // CHECK8-LABEL: define {{[^@]+}}@.omp_task_privates_map.
12865 // CHECK8-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], i16** noalias noundef [[TMP1:%.*]], [3 x i8*]** noalias noundef [[TMP2:%.*]], [3 x i8*]** noalias noundef [[TMP3:%.*]], [3 x i64]** noalias noundef [[TMP4:%.*]]) #[[ATTR5:[0-9]+]] {
12866 // CHECK8-NEXT:  entry:
12867 // CHECK8-NEXT:    [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 4
12868 // CHECK8-NEXT:    [[DOTADDR1:%.*]] = alloca i16**, align 4
12869 // CHECK8-NEXT:    [[DOTADDR2:%.*]] = alloca [3 x i8*]**, align 4
12870 // CHECK8-NEXT:    [[DOTADDR3:%.*]] = alloca [3 x i8*]**, align 4
12871 // CHECK8-NEXT:    [[DOTADDR4:%.*]] = alloca [3 x i64]**, align 4
12872 // CHECK8-NEXT:    store %struct..kmp_privates.t* [[TMP0]], %struct..kmp_privates.t** [[DOTADDR]], align 4
12873 // CHECK8-NEXT:    store i16** [[TMP1]], i16*** [[DOTADDR1]], align 4
12874 // CHECK8-NEXT:    store [3 x i8*]** [[TMP2]], [3 x i8*]*** [[DOTADDR2]], align 4
12875 // CHECK8-NEXT:    store [3 x i8*]** [[TMP3]], [3 x i8*]*** [[DOTADDR3]], align 4
12876 // CHECK8-NEXT:    store [3 x i64]** [[TMP4]], [3 x i64]*** [[DOTADDR4]], align 4
12877 // CHECK8-NEXT:    [[TMP5:%.*]] = load %struct..kmp_privates.t*, %struct..kmp_privates.t** [[DOTADDR]], align 4
12878 // CHECK8-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 0
12879 // CHECK8-NEXT:    [[TMP7:%.*]] = load [3 x i64]**, [3 x i64]*** [[DOTADDR4]], align 4
12880 // CHECK8-NEXT:    store [3 x i64]* [[TMP6]], [3 x i64]** [[TMP7]], align 4
12881 // CHECK8-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 1
12882 // CHECK8-NEXT:    [[TMP9:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR2]], align 4
12883 // CHECK8-NEXT:    store [3 x i8*]* [[TMP8]], [3 x i8*]** [[TMP9]], align 4
12884 // CHECK8-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 2
12885 // CHECK8-NEXT:    [[TMP11:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR3]], align 4
12886 // CHECK8-NEXT:    store [3 x i8*]* [[TMP10]], [3 x i8*]** [[TMP11]], align 4
12887 // CHECK8-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 3
12888 // CHECK8-NEXT:    [[TMP13:%.*]] = load i16**, i16*** [[DOTADDR1]], align 4
12889 // CHECK8-NEXT:    store i16* [[TMP12]], i16** [[TMP13]], align 4
12890 // CHECK8-NEXT:    ret void
12891 //
12892 //
12893 // CHECK8-LABEL: define {{[^@]+}}@.omp_task_entry.
12894 // CHECK8-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] {
12895 // CHECK8-NEXT:  entry:
12896 // CHECK8-NEXT:    [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
12897 // CHECK8-NEXT:    [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 4
12898 // CHECK8-NEXT:    [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 4
12899 // CHECK8-NEXT:    [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 4
12900 // CHECK8-NEXT:    [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 4
12901 // CHECK8-NEXT:    [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 4
12902 // CHECK8-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca i16*, align 4
12903 // CHECK8-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca [3 x i8*]*, align 4
12904 // CHECK8-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca [3 x i8*]*, align 4
12905 // CHECK8-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca [3 x i64]*, align 4
12906 // CHECK8-NEXT:    [[AA_CASTED_I:%.*]] = alloca i32, align 4
12907 // CHECK8-NEXT:    [[DOTCAPTURE_EXPR__CASTED_I:%.*]] = alloca i32, align 4
12908 // CHECK8-NEXT:    [[DOTCAPTURE_EXPR__CASTED4_I:%.*]] = alloca i32, align 4
12909 // CHECK8-NEXT:    [[DOTADDR:%.*]] = alloca i32, align 4
12910 // CHECK8-NEXT:    [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 4
12911 // CHECK8-NEXT:    store i32 [[TMP0]], i32* [[DOTADDR]], align 4
12912 // CHECK8-NEXT:    store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4
12913 // CHECK8-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4
12914 // CHECK8-NEXT:    [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4
12915 // CHECK8-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
12916 // CHECK8-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
12917 // CHECK8-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0
12918 // CHECK8-NEXT:    [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 4
12919 // CHECK8-NEXT:    [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon*
12920 // CHECK8-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1
12921 // CHECK8-NEXT:    [[TMP10:%.*]] = bitcast %struct..kmp_privates.t* [[TMP9]] to i8*
12922 // CHECK8-NEXT:    [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8*
12923 // CHECK8-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]])
12924 // CHECK8-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META21:![0-9]+]])
12925 // CHECK8-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META23:![0-9]+]])
12926 // CHECK8-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META25:![0-9]+]])
12927 // CHECK8-NEXT:    store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !27
12928 // CHECK8-NEXT:    store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 4, !noalias !27
12929 // CHECK8-NEXT:    store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !27
12930 // CHECK8-NEXT:    store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* @.omp_task_privates_map. to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !27
12931 // CHECK8-NEXT:    store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 4, !noalias !27
12932 // CHECK8-NEXT:    store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !27
12933 // CHECK8-NEXT:    [[TMP12:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !27
12934 // CHECK8-NEXT:    [[TMP13:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !27
12935 // CHECK8-NEXT:    [[TMP14:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !27
12936 // CHECK8-NEXT:    [[TMP15:%.*]] = bitcast void (i8*, ...)* [[TMP13]] to void (i8*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)*
12937 // CHECK8-NEXT:    call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR4]]
12938 // CHECK8-NEXT:    [[TMP16:%.*]] = load i16*, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 4, !noalias !27
12939 // CHECK8-NEXT:    [[TMP17:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 4, !noalias !27
12940 // CHECK8-NEXT:    [[TMP18:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 4, !noalias !27
12941 // CHECK8-NEXT:    [[TMP19:%.*]] = load [3 x i64]*, [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 4, !noalias !27
12942 // CHECK8-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP17]], i32 0, i32 0
12943 // CHECK8-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP18]], i32 0, i32 0
12944 // CHECK8-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[TMP19]], i32 0, i32 0
12945 // CHECK8-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP12]], i32 0, i32 1
12946 // CHECK8-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[TMP12]], i32 0, i32 2
12947 // CHECK8-NEXT:    [[TMP25:%.*]] = load i32, i32* [[TMP23]], align 4
12948 // CHECK8-NEXT:    call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) #[[ATTR4]]
12949 // CHECK8-NEXT:    [[TMP26:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 [[TMP25]], i32 1, i32 0, i8* null, i32 0, i8* null) #[[ATTR4]]
12950 // CHECK8-NEXT:    [[TMP27:%.*]] = icmp ne i32 [[TMP26]], 0
12951 // CHECK8-NEXT:    br i1 [[TMP27]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]]
12952 // CHECK8:       omp_offload.failed.i:
12953 // CHECK8-NEXT:    [[TMP28:%.*]] = load i16, i16* [[TMP16]], align 2
12954 // CHECK8-NEXT:    [[CONV_I:%.*]] = bitcast i32* [[AA_CASTED_I]] to i16*
12955 // CHECK8-NEXT:    store i16 [[TMP28]], i16* [[CONV_I]], align 2, !noalias !27
12956 // CHECK8-NEXT:    [[TMP29:%.*]] = load i32, i32* [[AA_CASTED_I]], align 4, !noalias !27
12957 // CHECK8-NEXT:    [[TMP30:%.*]] = load i32, i32* [[TMP23]], align 4
12958 // CHECK8-NEXT:    store i32 [[TMP30]], i32* [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias !27
12959 // CHECK8-NEXT:    [[TMP31:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias !27
12960 // CHECK8-NEXT:    [[TMP32:%.*]] = load i32, i32* [[TMP24]], align 4
12961 // CHECK8-NEXT:    store i32 [[TMP32]], i32* [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias !27
12962 // CHECK8-NEXT:    [[TMP33:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias !27
12963 // CHECK8-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97(i32 [[TMP29]], i32 [[TMP31]], i32 [[TMP33]]) #[[ATTR4]]
12964 // CHECK8-NEXT:    br label [[DOTOMP_OUTLINED__1_EXIT]]
12965 // CHECK8:       .omp_outlined..1.exit:
12966 // CHECK8-NEXT:    ret i32 0
12967 //
12968 //
12969 // CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l102
12970 // CHECK8-SAME: (i32 noundef [[A:%.*]]) #[[ATTR3]] {
12971 // CHECK8-NEXT:  entry:
12972 // CHECK8-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
12973 // CHECK8-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
12974 // CHECK8-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
12975 // CHECK8-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
12976 // CHECK8-NEXT:    store i32 [[TMP0]], i32* [[A_CASTED]], align 4
12977 // CHECK8-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
12978 // CHECK8-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]])
12979 // CHECK8-NEXT:    ret void
12980 //
12981 //
12982 // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..2
12983 // CHECK8-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]]) #[[ATTR3]] {
12984 // CHECK8-NEXT:  entry:
12985 // CHECK8-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
12986 // CHECK8-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
12987 // CHECK8-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
12988 // CHECK8-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
12989 // CHECK8-NEXT:    [[TMP:%.*]] = alloca i32, align 4
12990 // CHECK8-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
12991 // CHECK8-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
12992 // CHECK8-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
12993 // CHECK8-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
12994 // CHECK8-NEXT:    [[A1:%.*]] = alloca i32, align 4
12995 // CHECK8-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
12996 // CHECK8-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
12997 // CHECK8-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
12998 // CHECK8-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
12999 // CHECK8-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
13000 // CHECK8-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
13001 // CHECK8-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
13002 // CHECK8-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
13003 // CHECK8-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
13004 // CHECK8-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
13005 // CHECK8-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
13006 // CHECK8-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
13007 // CHECK8-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
13008 // CHECK8:       cond.true:
13009 // CHECK8-NEXT:    br label [[COND_END:%.*]]
13010 // CHECK8:       cond.false:
13011 // CHECK8-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
13012 // CHECK8-NEXT:    br label [[COND_END]]
13013 // CHECK8:       cond.end:
13014 // CHECK8-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
13015 // CHECK8-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
13016 // CHECK8-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
13017 // CHECK8-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
13018 // CHECK8-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
13019 // CHECK8:       omp.inner.for.cond:
13020 // CHECK8-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
13021 // CHECK8-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
13022 // CHECK8-NEXT:    [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
13023 // CHECK8-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
13024 // CHECK8:       omp.inner.for.body:
13025 // CHECK8-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
13026 // CHECK8-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
13027 // CHECK8-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
13028 // CHECK8-NEXT:    store i32 [[ADD]], i32* [[A1]], align 4, !nontemporal !28
13029 // CHECK8-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A1]], align 4, !nontemporal !28
13030 // CHECK8-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
13031 // CHECK8-NEXT:    store i32 [[ADD3]], i32* [[A1]], align 4, !nontemporal !28
13032 // CHECK8-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
13033 // CHECK8:       omp.body.continue:
13034 // CHECK8-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
13035 // CHECK8:       omp.inner.for.inc:
13036 // CHECK8-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
13037 // CHECK8-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP9]], 1
13038 // CHECK8-NEXT:    store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4
13039 // CHECK8-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP29:![0-9]+]]
13040 // CHECK8:       omp.inner.for.end:
13041 // CHECK8-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
13042 // CHECK8:       omp.loop.exit:
13043 // CHECK8-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
13044 // CHECK8-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
13045 // CHECK8-NEXT:    [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0
13046 // CHECK8-NEXT:    br i1 [[TMP11]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
13047 // CHECK8:       .omp.final.then:
13048 // CHECK8-NEXT:    store i32 10, i32* [[A_ADDR]], align 4
13049 // CHECK8-NEXT:    br label [[DOTOMP_FINAL_DONE]]
13050 // CHECK8:       .omp.final.done:
13051 // CHECK8-NEXT:    ret void
13052 //
13053 //
13054 // CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111
13055 // CHECK8-SAME: (i32 noundef [[AA:%.*]]) #[[ATTR2]] {
13056 // CHECK8-NEXT:  entry:
13057 // CHECK8-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
13058 // CHECK8-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
13059 // CHECK8-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
13060 // CHECK8-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
13061 // CHECK8-NEXT:    [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
13062 // CHECK8-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
13063 // CHECK8-NEXT:    store i16 [[TMP0]], i16* [[CONV1]], align 2
13064 // CHECK8-NEXT:    [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
13065 // CHECK8-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP1]])
13066 // CHECK8-NEXT:    ret void
13067 //
13068 //
13069 // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..3
13070 // CHECK8-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR3]] {
13071 // CHECK8-NEXT:  entry:
13072 // CHECK8-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
13073 // CHECK8-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
13074 // CHECK8-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
13075 // CHECK8-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
13076 // CHECK8-NEXT:    [[TMP:%.*]] = alloca i32, align 4
13077 // CHECK8-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
13078 // CHECK8-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
13079 // CHECK8-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
13080 // CHECK8-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
13081 // CHECK8-NEXT:    [[I:%.*]] = alloca i32, align 4
13082 // CHECK8-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
13083 // CHECK8-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
13084 // CHECK8-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
13085 // CHECK8-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
13086 // CHECK8-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
13087 // CHECK8-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
13088 // CHECK8-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
13089 // CHECK8-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
13090 // CHECK8-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
13091 // CHECK8-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
13092 // CHECK8-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
13093 // CHECK8-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
13094 // CHECK8-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
13095 // CHECK8-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
13096 // CHECK8:       cond.true:
13097 // CHECK8-NEXT:    br label [[COND_END:%.*]]
13098 // CHECK8:       cond.false:
13099 // CHECK8-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
13100 // CHECK8-NEXT:    br label [[COND_END]]
13101 // CHECK8:       cond.end:
13102 // CHECK8-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
13103 // CHECK8-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
13104 // CHECK8-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
13105 // CHECK8-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
13106 // CHECK8-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
13107 // CHECK8:       omp.inner.for.cond:
13108 // CHECK8-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !31
13109 // CHECK8-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !31
13110 // CHECK8-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
13111 // CHECK8-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
13112 // CHECK8:       omp.inner.for.body:
13113 // CHECK8-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !31
13114 // CHECK8-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
13115 // CHECK8-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
13116 // CHECK8-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !31
13117 // CHECK8-NEXT:    [[TMP8:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !31
13118 // CHECK8-NEXT:    [[CONV2:%.*]] = sext i16 [[TMP8]] to i32
13119 // CHECK8-NEXT:    [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
13120 // CHECK8-NEXT:    [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
13121 // CHECK8-NEXT:    store i16 [[CONV4]], i16* [[CONV]], align 2, !llvm.access.group !31
13122 // CHECK8-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
13123 // CHECK8:       omp.body.continue:
13124 // CHECK8-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
13125 // CHECK8:       omp.inner.for.inc:
13126 // CHECK8-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !31
13127 // CHECK8-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP9]], 1
13128 // CHECK8-NEXT:    store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !31
13129 // CHECK8-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP32:![0-9]+]]
13130 // CHECK8:       omp.inner.for.end:
13131 // CHECK8-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
13132 // CHECK8:       omp.loop.exit:
13133 // CHECK8-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
13134 // CHECK8-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
13135 // CHECK8-NEXT:    [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0
13136 // CHECK8-NEXT:    br i1 [[TMP11]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
13137 // CHECK8:       .omp.final.then:
13138 // CHECK8-NEXT:    store i32 10, i32* [[I]], align 4
13139 // CHECK8-NEXT:    br label [[DOTOMP_FINAL_DONE]]
13140 // CHECK8:       .omp.final.done:
13141 // CHECK8-NEXT:    ret void
13142 //
13143 //
13144 // CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118
13145 // CHECK8-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] {
13146 // CHECK8-NEXT:  entry:
13147 // CHECK8-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
13148 // CHECK8-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
13149 // CHECK8-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
13150 // CHECK8-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
13151 // CHECK8-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
13152 // CHECK8-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
13153 // CHECK8-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
13154 // CHECK8-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
13155 // CHECK8-NEXT:    store i32 [[TMP0]], i32* [[A_CASTED]], align 4
13156 // CHECK8-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
13157 // CHECK8-NEXT:    [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
13158 // CHECK8-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
13159 // CHECK8-NEXT:    store i16 [[TMP2]], i16* [[CONV1]], align 2
13160 // CHECK8-NEXT:    [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
13161 // CHECK8-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]])
13162 // CHECK8-NEXT:    ret void
13163 //
13164 //
13165 // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..6
13166 // CHECK8-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR3]] {
13167 // CHECK8-NEXT:  entry:
13168 // CHECK8-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
13169 // CHECK8-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
13170 // CHECK8-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
13171 // CHECK8-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
13172 // CHECK8-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
13173 // CHECK8-NEXT:    [[TMP:%.*]] = alloca i32, align 4
13174 // CHECK8-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
13175 // CHECK8-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
13176 // CHECK8-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
13177 // CHECK8-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
13178 // CHECK8-NEXT:    [[I:%.*]] = alloca i32, align 4
13179 // CHECK8-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
13180 // CHECK8-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
13181 // CHECK8-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
13182 // CHECK8-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
13183 // CHECK8-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
13184 // CHECK8-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
13185 // CHECK8-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
13186 // CHECK8-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
13187 // CHECK8-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
13188 // CHECK8-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
13189 // CHECK8-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
13190 // CHECK8-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
13191 // CHECK8-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
13192 // CHECK8-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
13193 // CHECK8-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
13194 // CHECK8:       cond.true:
13195 // CHECK8-NEXT:    br label [[COND_END:%.*]]
13196 // CHECK8:       cond.false:
13197 // CHECK8-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
13198 // CHECK8-NEXT:    br label [[COND_END]]
13199 // CHECK8:       cond.end:
13200 // CHECK8-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
13201 // CHECK8-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
13202 // CHECK8-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
13203 // CHECK8-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
13204 // CHECK8-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
13205 // CHECK8:       omp.inner.for.cond:
13206 // CHECK8-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !34
13207 // CHECK8-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !34
13208 // CHECK8-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
13209 // CHECK8-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
13210 // CHECK8:       omp.inner.for.body:
13211 // CHECK8-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !34
13212 // CHECK8-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
13213 // CHECK8-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
13214 // CHECK8-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !34
13215 // CHECK8-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !34
13216 // CHECK8-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
13217 // CHECK8-NEXT:    store i32 [[ADD2]], i32* [[A_ADDR]], align 4, !llvm.access.group !34
13218 // CHECK8-NEXT:    [[TMP9:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !34
13219 // CHECK8-NEXT:    [[CONV3:%.*]] = sext i16 [[TMP9]] to i32
13220 // CHECK8-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
13221 // CHECK8-NEXT:    [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
13222 // CHECK8-NEXT:    store i16 [[CONV5]], i16* [[CONV]], align 2, !llvm.access.group !34
13223 // CHECK8-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
13224 // CHECK8:       omp.body.continue:
13225 // CHECK8-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
13226 // CHECK8:       omp.inner.for.inc:
13227 // CHECK8-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !34
13228 // CHECK8-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP10]], 1
13229 // CHECK8-NEXT:    store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !34
13230 // CHECK8-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP35:![0-9]+]]
13231 // CHECK8:       omp.inner.for.end:
13232 // CHECK8-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
13233 // CHECK8:       omp.loop.exit:
13234 // CHECK8-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
13235 // CHECK8-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
13236 // CHECK8-NEXT:    [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
13237 // CHECK8-NEXT:    br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
13238 // CHECK8:       .omp.final.then:
13239 // CHECK8-NEXT:    store i32 10, i32* [[I]], align 4
13240 // CHECK8-NEXT:    br label [[DOTOMP_FINAL_DONE]]
13241 // CHECK8:       .omp.final.done:
13242 // CHECK8-NEXT:    ret void
13243 //
13244 //
13245 // CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142
13246 // CHECK8-SAME: (i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] {
13247 // CHECK8-NEXT:  entry:
13248 // CHECK8-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
13249 // CHECK8-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
13250 // CHECK8-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
13251 // CHECK8-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 4
13252 // CHECK8-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
13253 // CHECK8-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
13254 // CHECK8-NEXT:    [[VLA_ADDR4:%.*]] = alloca i32, align 4
13255 // CHECK8-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 4
13256 // CHECK8-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
13257 // CHECK8-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
13258 // CHECK8-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
13259 // CHECK8-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
13260 // CHECK8-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
13261 // CHECK8-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 4
13262 // CHECK8-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
13263 // CHECK8-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
13264 // CHECK8-NEXT:    store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
13265 // CHECK8-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 4
13266 // CHECK8-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
13267 // CHECK8-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
13268 // CHECK8-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
13269 // CHECK8-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
13270 // CHECK8-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
13271 // CHECK8-NEXT:    [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
13272 // CHECK8-NEXT:    [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
13273 // CHECK8-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
13274 // CHECK8-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
13275 // CHECK8-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
13276 // CHECK8-NEXT:    store i32 [[TMP8]], i32* [[A_CASTED]], align 4
13277 // CHECK8-NEXT:    [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4
13278 // CHECK8-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]])
13279 // CHECK8-NEXT:    ret void
13280 //
13281 //
13282 // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..9
13283 // CHECK8-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR3]] {
13284 // CHECK8-NEXT:  entry:
13285 // CHECK8-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
13286 // CHECK8-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
13287 // CHECK8-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
13288 // CHECK8-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
13289 // CHECK8-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
13290 // CHECK8-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 4
13291 // CHECK8-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
13292 // CHECK8-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
13293 // CHECK8-NEXT:    [[VLA_ADDR4:%.*]] = alloca i32, align 4
13294 // CHECK8-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 4
13295 // CHECK8-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
13296 // CHECK8-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
13297 // CHECK8-NEXT:    [[TMP:%.*]] = alloca i32, align 4
13298 // CHECK8-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
13299 // CHECK8-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
13300 // CHECK8-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
13301 // CHECK8-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
13302 // CHECK8-NEXT:    [[I:%.*]] = alloca i32, align 4
13303 // CHECK8-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
13304 // CHECK8-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
13305 // CHECK8-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
13306 // CHECK8-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
13307 // CHECK8-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
13308 // CHECK8-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 4
13309 // CHECK8-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
13310 // CHECK8-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
13311 // CHECK8-NEXT:    store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
13312 // CHECK8-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 4
13313 // CHECK8-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
13314 // CHECK8-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
13315 // CHECK8-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
13316 // CHECK8-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
13317 // CHECK8-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
13318 // CHECK8-NEXT:    [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
13319 // CHECK8-NEXT:    [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
13320 // CHECK8-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
13321 // CHECK8-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
13322 // CHECK8-NEXT:    [[ARRAYDECAY:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 0
13323 // CHECK8-NEXT:    call void @llvm.assume(i1 true) [ "align"(float* [[ARRAYDECAY]], i32 16) ]
13324 // CHECK8-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
13325 // CHECK8-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
13326 // CHECK8-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
13327 // CHECK8-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
13328 // CHECK8-NEXT:    [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
13329 // CHECK8-NEXT:    [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4
13330 // CHECK8-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
13331 // CHECK8-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
13332 // CHECK8-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP10]], 9
13333 // CHECK8-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
13334 // CHECK8:       cond.true:
13335 // CHECK8-NEXT:    br label [[COND_END:%.*]]
13336 // CHECK8:       cond.false:
13337 // CHECK8-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
13338 // CHECK8-NEXT:    br label [[COND_END]]
13339 // CHECK8:       cond.end:
13340 // CHECK8-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ]
13341 // CHECK8-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
13342 // CHECK8-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
13343 // CHECK8-NEXT:    store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4
13344 // CHECK8-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
13345 // CHECK8:       omp.inner.for.cond:
13346 // CHECK8-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !37
13347 // CHECK8-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !37
13348 // CHECK8-NEXT:    [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
13349 // CHECK8-NEXT:    br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
13350 // CHECK8:       omp.inner.for.body:
13351 // CHECK8-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !37
13352 // CHECK8-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1
13353 // CHECK8-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
13354 // CHECK8-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !37
13355 // CHECK8-NEXT:    [[TMP16:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !37
13356 // CHECK8-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP16]], 1
13357 // CHECK8-NEXT:    store i32 [[ADD6]], i32* [[A_ADDR]], align 4, !llvm.access.group !37
13358 // CHECK8-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2
13359 // CHECK8-NEXT:    [[TMP17:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !37
13360 // CHECK8-NEXT:    [[CONV:%.*]] = fpext float [[TMP17]] to double
13361 // CHECK8-NEXT:    [[ADD7:%.*]] = fadd double [[CONV]], 1.000000e+00
13362 // CHECK8-NEXT:    [[CONV8:%.*]] = fptrunc double [[ADD7]] to float
13363 // CHECK8-NEXT:    store float [[CONV8]], float* [[ARRAYIDX]], align 4, !llvm.access.group !37
13364 // CHECK8-NEXT:    [[ARRAYIDX9:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3
13365 // CHECK8-NEXT:    [[TMP18:%.*]] = load float, float* [[ARRAYIDX9]], align 4, !llvm.access.group !37
13366 // CHECK8-NEXT:    [[CONV10:%.*]] = fpext float [[TMP18]] to double
13367 // CHECK8-NEXT:    [[ADD11:%.*]] = fadd double [[CONV10]], 1.000000e+00
13368 // CHECK8-NEXT:    [[CONV12:%.*]] = fptrunc double [[ADD11]] to float
13369 // CHECK8-NEXT:    store float [[CONV12]], float* [[ARRAYIDX9]], align 4, !llvm.access.group !37
13370 // CHECK8-NEXT:    [[ARRAYIDX13:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1
13371 // CHECK8-NEXT:    [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX13]], i32 0, i32 2
13372 // CHECK8-NEXT:    [[TMP19:%.*]] = load double, double* [[ARRAYIDX14]], align 8, !llvm.access.group !37
13373 // CHECK8-NEXT:    [[ADD15:%.*]] = fadd double [[TMP19]], 1.000000e+00
13374 // CHECK8-NEXT:    store double [[ADD15]], double* [[ARRAYIDX14]], align 8, !llvm.access.group !37
13375 // CHECK8-NEXT:    [[TMP20:%.*]] = mul nsw i32 1, [[TMP5]]
13376 // CHECK8-NEXT:    [[ARRAYIDX16:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP20]]
13377 // CHECK8-NEXT:    [[ARRAYIDX17:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX16]], i32 3
13378 // CHECK8-NEXT:    [[TMP21:%.*]] = load double, double* [[ARRAYIDX17]], align 8, !llvm.access.group !37
13379 // CHECK8-NEXT:    [[ADD18:%.*]] = fadd double [[TMP21]], 1.000000e+00
13380 // CHECK8-NEXT:    store double [[ADD18]], double* [[ARRAYIDX17]], align 8, !llvm.access.group !37
13381 // CHECK8-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0
13382 // CHECK8-NEXT:    [[TMP22:%.*]] = load i64, i64* [[X]], align 4, !llvm.access.group !37
13383 // CHECK8-NEXT:    [[ADD19:%.*]] = add nsw i64 [[TMP22]], 1
13384 // CHECK8-NEXT:    store i64 [[ADD19]], i64* [[X]], align 4, !llvm.access.group !37
13385 // CHECK8-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1
13386 // CHECK8-NEXT:    [[TMP23:%.*]] = load i8, i8* [[Y]], align 4, !llvm.access.group !37
13387 // CHECK8-NEXT:    [[CONV20:%.*]] = sext i8 [[TMP23]] to i32
13388 // CHECK8-NEXT:    [[ADD21:%.*]] = add nsw i32 [[CONV20]], 1
13389 // CHECK8-NEXT:    [[CONV22:%.*]] = trunc i32 [[ADD21]] to i8
13390 // CHECK8-NEXT:    store i8 [[CONV22]], i8* [[Y]], align 4, !llvm.access.group !37
13391 // CHECK8-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
13392 // CHECK8:       omp.body.continue:
13393 // CHECK8-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
13394 // CHECK8:       omp.inner.for.inc:
13395 // CHECK8-NEXT:    [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !37
13396 // CHECK8-NEXT:    [[ADD23:%.*]] = add nsw i32 [[TMP24]], 1
13397 // CHECK8-NEXT:    store i32 [[ADD23]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !37
13398 // CHECK8-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP38:![0-9]+]]
13399 // CHECK8:       omp.inner.for.end:
13400 // CHECK8-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
13401 // CHECK8:       omp.loop.exit:
13402 // CHECK8-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]])
13403 // CHECK8-NEXT:    [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
13404 // CHECK8-NEXT:    [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
13405 // CHECK8-NEXT:    br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
13406 // CHECK8:       .omp.final.then:
13407 // CHECK8-NEXT:    store i32 10, i32* [[I]], align 4
13408 // CHECK8-NEXT:    br label [[DOTOMP_FINAL_DONE]]
13409 // CHECK8:       .omp.final.done:
13410 // CHECK8-NEXT:    ret void
13411 //
13412 //
13413 // CHECK8-LABEL: define {{[^@]+}}@_Z3bari
13414 // CHECK8-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {
13415 // CHECK8-NEXT:  entry:
13416 // CHECK8-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
13417 // CHECK8-NEXT:    [[A:%.*]] = alloca i32, align 4
13418 // CHECK8-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4
13419 // CHECK8-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
13420 // CHECK8-NEXT:    store i32 0, i32* [[A]], align 4
13421 // CHECK8-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
13422 // CHECK8-NEXT:    [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]])
13423 // CHECK8-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
13424 // CHECK8-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
13425 // CHECK8-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
13426 // CHECK8-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
13427 // CHECK8-NEXT:    [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP2]])
13428 // CHECK8-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
13429 // CHECK8-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
13430 // CHECK8-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
13431 // CHECK8-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
13432 // CHECK8-NEXT:    [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]])
13433 // CHECK8-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
13434 // CHECK8-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
13435 // CHECK8-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
13436 // CHECK8-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
13437 // CHECK8-NEXT:    [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]])
13438 // CHECK8-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
13439 // CHECK8-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
13440 // CHECK8-NEXT:    store i32 [[ADD6]], i32* [[A]], align 4
13441 // CHECK8-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
13442 // CHECK8-NEXT:    ret i32 [[TMP8]]
13443 //
13444 //
13445 // CHECK8-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
13446 // CHECK8-SAME: (%struct.S1* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 {
13447 // CHECK8-NEXT:  entry:
13448 // CHECK8-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
13449 // CHECK8-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
13450 // CHECK8-NEXT:    [[B:%.*]] = alloca i32, align 4
13451 // CHECK8-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 4
13452 // CHECK8-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 4
13453 // CHECK8-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
13454 // CHECK8-NEXT:    [[B_CASTED:%.*]] = alloca i32, align 4
13455 // CHECK8-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
13456 // CHECK8-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [6 x i8*], align 4
13457 // CHECK8-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [6 x i8*], align 4
13458 // CHECK8-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [6 x i8*], align 4
13459 // CHECK8-NEXT:    [[DOTOFFLOAD_SIZES:%.*]] = alloca [6 x i64], align 4
13460 // CHECK8-NEXT:    [[TMP:%.*]] = alloca i32, align 4
13461 // CHECK8-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
13462 // CHECK8-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
13463 // CHECK8-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
13464 // CHECK8-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
13465 // CHECK8-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
13466 // CHECK8-NEXT:    store i32 [[ADD]], i32* [[B]], align 4
13467 // CHECK8-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
13468 // CHECK8-NEXT:    [[TMP2:%.*]] = call i8* @llvm.stacksave()
13469 // CHECK8-NEXT:    store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4
13470 // CHECK8-NEXT:    [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]
13471 // CHECK8-NEXT:    [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2
13472 // CHECK8-NEXT:    store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
13473 // CHECK8-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
13474 // CHECK8-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 60
13475 // CHECK8-NEXT:    [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8
13476 // CHECK8-NEXT:    store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
13477 // CHECK8-NEXT:    [[TMP5:%.*]] = load i32, i32* [[B]], align 4
13478 // CHECK8-NEXT:    store i32 [[TMP5]], i32* [[B_CASTED]], align 4
13479 // CHECK8-NEXT:    [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4
13480 // CHECK8-NEXT:    [[TMP7:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
13481 // CHECK8-NEXT:    [[TOBOOL:%.*]] = trunc i8 [[TMP7]] to i1
13482 // CHECK8-NEXT:    [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__CASTED]] to i8*
13483 // CHECK8-NEXT:    [[FROMBOOL2:%.*]] = zext i1 [[TOBOOL]] to i8
13484 // CHECK8-NEXT:    store i8 [[FROMBOOL2]], i8* [[CONV]], align 1
13485 // CHECK8-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
13486 // CHECK8-NEXT:    [[TMP9:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
13487 // CHECK8-NEXT:    [[TOBOOL3:%.*]] = trunc i8 [[TMP9]] to i1
13488 // CHECK8-NEXT:    br i1 [[TOBOOL3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
13489 // CHECK8:       omp_if.then:
13490 // CHECK8-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
13491 // CHECK8-NEXT:    [[TMP10:%.*]] = mul nuw i32 2, [[TMP1]]
13492 // CHECK8-NEXT:    [[TMP11:%.*]] = mul nuw i32 [[TMP10]], 2
13493 // CHECK8-NEXT:    [[TMP12:%.*]] = sext i32 [[TMP11]] to i64
13494 // CHECK8-NEXT:    [[TMP13:%.*]] = bitcast [6 x i64]* [[DOTOFFLOAD_SIZES]] to i8*
13495 // CHECK8-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP13]], i8* align 4 bitcast ([6 x i64]* @.offload_sizes.13 to i8*), i32 48, i1 false)
13496 // CHECK8-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
13497 // CHECK8-NEXT:    [[TMP15:%.*]] = bitcast i8** [[TMP14]] to %struct.S1**
13498 // CHECK8-NEXT:    store %struct.S1* [[THIS1]], %struct.S1** [[TMP15]], align 4
13499 // CHECK8-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
13500 // CHECK8-NEXT:    [[TMP17:%.*]] = bitcast i8** [[TMP16]] to double**
13501 // CHECK8-NEXT:    store double* [[A]], double** [[TMP17]], align 4
13502 // CHECK8-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
13503 // CHECK8-NEXT:    store i8* null, i8** [[TMP18]], align 4
13504 // CHECK8-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
13505 // CHECK8-NEXT:    [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32*
13506 // CHECK8-NEXT:    store i32 [[TMP6]], i32* [[TMP20]], align 4
13507 // CHECK8-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
13508 // CHECK8-NEXT:    [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i32*
13509 // CHECK8-NEXT:    store i32 [[TMP6]], i32* [[TMP22]], align 4
13510 // CHECK8-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
13511 // CHECK8-NEXT:    store i8* null, i8** [[TMP23]], align 4
13512 // CHECK8-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
13513 // CHECK8-NEXT:    [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i32*
13514 // CHECK8-NEXT:    store i32 2, i32* [[TMP25]], align 4
13515 // CHECK8-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
13516 // CHECK8-NEXT:    [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i32*
13517 // CHECK8-NEXT:    store i32 2, i32* [[TMP27]], align 4
13518 // CHECK8-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
13519 // CHECK8-NEXT:    store i8* null, i8** [[TMP28]], align 4
13520 // CHECK8-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
13521 // CHECK8-NEXT:    [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i32*
13522 // CHECK8-NEXT:    store i32 [[TMP1]], i32* [[TMP30]], align 4
13523 // CHECK8-NEXT:    [[TMP31:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
13524 // CHECK8-NEXT:    [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i32*
13525 // CHECK8-NEXT:    store i32 [[TMP1]], i32* [[TMP32]], align 4
13526 // CHECK8-NEXT:    [[TMP33:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
13527 // CHECK8-NEXT:    store i8* null, i8** [[TMP33]], align 4
13528 // CHECK8-NEXT:    [[TMP34:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
13529 // CHECK8-NEXT:    [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i16**
13530 // CHECK8-NEXT:    store i16* [[VLA]], i16** [[TMP35]], align 4
13531 // CHECK8-NEXT:    [[TMP36:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
13532 // CHECK8-NEXT:    [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i16**
13533 // CHECK8-NEXT:    store i16* [[VLA]], i16** [[TMP37]], align 4
13534 // CHECK8-NEXT:    [[TMP38:%.*]] = getelementptr inbounds [6 x i64], [6 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4
13535 // CHECK8-NEXT:    store i64 [[TMP12]], i64* [[TMP38]], align 4
13536 // CHECK8-NEXT:    [[TMP39:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4
13537 // CHECK8-NEXT:    store i8* null, i8** [[TMP39]], align 4
13538 // CHECK8-NEXT:    [[TMP40:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 5
13539 // CHECK8-NEXT:    [[TMP41:%.*]] = bitcast i8** [[TMP40]] to i32*
13540 // CHECK8-NEXT:    store i32 [[TMP8]], i32* [[TMP41]], align 4
13541 // CHECK8-NEXT:    [[TMP42:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 5
13542 // CHECK8-NEXT:    [[TMP43:%.*]] = bitcast i8** [[TMP42]] to i32*
13543 // CHECK8-NEXT:    store i32 [[TMP8]], i32* [[TMP43]], align 4
13544 // CHECK8-NEXT:    [[TMP44:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 5
13545 // CHECK8-NEXT:    store i8* null, i8** [[TMP44]], align 4
13546 // CHECK8-NEXT:    [[TMP45:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
13547 // CHECK8-NEXT:    [[TMP46:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
13548 // CHECK8-NEXT:    [[TMP47:%.*]] = getelementptr inbounds [6 x i64], [6 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
13549 // CHECK8-NEXT:    call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10)
13550 // CHECK8-NEXT:    [[TMP48:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215.region_id, i32 6, i8** [[TMP45]], i8** [[TMP46]], i64* [[TMP47]], i64* getelementptr inbounds ([6 x i64], [6 x i64]* @.offload_maptypes.14, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1)
13551 // CHECK8-NEXT:    [[TMP49:%.*]] = icmp ne i32 [[TMP48]], 0
13552 // CHECK8-NEXT:    br i1 [[TMP49]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
13553 // CHECK8:       omp_offload.failed:
13554 // CHECK8-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215(%struct.S1* [[THIS1]], i32 [[TMP6]], i32 2, i32 [[TMP1]], i16* [[VLA]], i32 [[TMP8]]) #[[ATTR4]]
13555 // CHECK8-NEXT:    br label [[OMP_OFFLOAD_CONT]]
13556 // CHECK8:       omp_offload.cont:
13557 // CHECK8-NEXT:    br label [[OMP_IF_END:%.*]]
13558 // CHECK8:       omp_if.else:
13559 // CHECK8-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215(%struct.S1* [[THIS1]], i32 [[TMP6]], i32 2, i32 [[TMP1]], i16* [[VLA]], i32 [[TMP8]]) #[[ATTR4]]
13560 // CHECK8-NEXT:    br label [[OMP_IF_END]]
13561 // CHECK8:       omp_if.end:
13562 // CHECK8-NEXT:    [[TMP50:%.*]] = mul nsw i32 1, [[TMP1]]
13563 // CHECK8-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP50]]
13564 // CHECK8-NEXT:    [[ARRAYIDX4:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
13565 // CHECK8-NEXT:    [[TMP51:%.*]] = load i16, i16* [[ARRAYIDX4]], align 2
13566 // CHECK8-NEXT:    [[CONV5:%.*]] = sext i16 [[TMP51]] to i32
13567 // CHECK8-NEXT:    [[TMP52:%.*]] = load i32, i32* [[B]], align 4
13568 // CHECK8-NEXT:    [[ADD6:%.*]] = add nsw i32 [[CONV5]], [[TMP52]]
13569 // CHECK8-NEXT:    [[TMP53:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
13570 // CHECK8-NEXT:    call void @llvm.stackrestore(i8* [[TMP53]])
13571 // CHECK8-NEXT:    ret i32 [[ADD6]]
13572 //
13573 //
13574 // CHECK8-LABEL: define {{[^@]+}}@_ZL7fstatici
13575 // CHECK8-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {
13576 // CHECK8-NEXT:  entry:
13577 // CHECK8-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
13578 // CHECK8-NEXT:    [[A:%.*]] = alloca i32, align 4
13579 // CHECK8-NEXT:    [[AA:%.*]] = alloca i16, align 2
13580 // CHECK8-NEXT:    [[AAA:%.*]] = alloca i8, align 1
13581 // CHECK8-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
13582 // CHECK8-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
13583 // CHECK8-NEXT:    [[N_CASTED:%.*]] = alloca i32, align 4
13584 // CHECK8-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
13585 // CHECK8-NEXT:    [[AAA_CASTED:%.*]] = alloca i32, align 4
13586 // CHECK8-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4
13587 // CHECK8-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4
13588 // CHECK8-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4
13589 // CHECK8-NEXT:    [[TMP:%.*]] = alloca i32, align 4
13590 // CHECK8-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
13591 // CHECK8-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
13592 // CHECK8-NEXT:    [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4
13593 // CHECK8-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
13594 // CHECK8-NEXT:    store i32 0, i32* [[A]], align 4
13595 // CHECK8-NEXT:    store i16 0, i16* [[AA]], align 2
13596 // CHECK8-NEXT:    store i8 0, i8* [[AAA]], align 1
13597 // CHECK8-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
13598 // CHECK8-NEXT:    store i32 [[TMP0]], i32* [[A_CASTED]], align 4
13599 // CHECK8-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
13600 // CHECK8-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
13601 // CHECK8-NEXT:    store i32 [[TMP2]], i32* [[N_CASTED]], align 4
13602 // CHECK8-NEXT:    [[TMP3:%.*]] = load i32, i32* [[N_CASTED]], align 4
13603 // CHECK8-NEXT:    [[TMP4:%.*]] = load i16, i16* [[AA]], align 2
13604 // CHECK8-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
13605 // CHECK8-NEXT:    store i16 [[TMP4]], i16* [[CONV]], align 2
13606 // CHECK8-NEXT:    [[TMP5:%.*]] = load i32, i32* [[AA_CASTED]], align 4
13607 // CHECK8-NEXT:    [[TMP6:%.*]] = load i8, i8* [[AAA]], align 1
13608 // CHECK8-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
13609 // CHECK8-NEXT:    store i8 [[TMP6]], i8* [[CONV1]], align 1
13610 // CHECK8-NEXT:    [[TMP7:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
13611 // CHECK8-NEXT:    [[TMP8:%.*]] = load i32, i32* [[N_ADDR]], align 4
13612 // CHECK8-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP8]], 50
13613 // CHECK8-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
13614 // CHECK8:       omp_if.then:
13615 // CHECK8-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
13616 // CHECK8-NEXT:    [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32*
13617 // CHECK8-NEXT:    store i32 [[TMP1]], i32* [[TMP10]], align 4
13618 // CHECK8-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
13619 // CHECK8-NEXT:    [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32*
13620 // CHECK8-NEXT:    store i32 [[TMP1]], i32* [[TMP12]], align 4
13621 // CHECK8-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
13622 // CHECK8-NEXT:    store i8* null, i8** [[TMP13]], align 4
13623 // CHECK8-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
13624 // CHECK8-NEXT:    [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32*
13625 // CHECK8-NEXT:    store i32 [[TMP3]], i32* [[TMP15]], align 4
13626 // CHECK8-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
13627 // CHECK8-NEXT:    [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32*
13628 // CHECK8-NEXT:    store i32 [[TMP3]], i32* [[TMP17]], align 4
13629 // CHECK8-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
13630 // CHECK8-NEXT:    store i8* null, i8** [[TMP18]], align 4
13631 // CHECK8-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
13632 // CHECK8-NEXT:    [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32*
13633 // CHECK8-NEXT:    store i32 [[TMP5]], i32* [[TMP20]], align 4
13634 // CHECK8-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
13635 // CHECK8-NEXT:    [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i32*
13636 // CHECK8-NEXT:    store i32 [[TMP5]], i32* [[TMP22]], align 4
13637 // CHECK8-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
13638 // CHECK8-NEXT:    store i8* null, i8** [[TMP23]], align 4
13639 // CHECK8-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
13640 // CHECK8-NEXT:    [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i32*
13641 // CHECK8-NEXT:    store i32 [[TMP7]], i32* [[TMP25]], align 4
13642 // CHECK8-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
13643 // CHECK8-NEXT:    [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i32*
13644 // CHECK8-NEXT:    store i32 [[TMP7]], i32* [[TMP27]], align 4
13645 // CHECK8-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
13646 // CHECK8-NEXT:    store i8* null, i8** [[TMP28]], align 4
13647 // CHECK8-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
13648 // CHECK8-NEXT:    [[TMP30:%.*]] = bitcast i8** [[TMP29]] to [10 x i32]**
13649 // CHECK8-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP30]], align 4
13650 // CHECK8-NEXT:    [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
13651 // CHECK8-NEXT:    [[TMP32:%.*]] = bitcast i8** [[TMP31]] to [10 x i32]**
13652 // CHECK8-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP32]], align 4
13653 // CHECK8-NEXT:    [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4
13654 // CHECK8-NEXT:    store i8* null, i8** [[TMP33]], align 4
13655 // CHECK8-NEXT:    [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
13656 // CHECK8-NEXT:    [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
13657 // CHECK8-NEXT:    [[TMP36:%.*]] = load i32, i32* [[A]], align 4
13658 // CHECK8-NEXT:    store i32 [[TMP36]], i32* [[DOTCAPTURE_EXPR_]], align 4
13659 // CHECK8-NEXT:    [[TMP37:%.*]] = load i32, i32* [[N_ADDR]], align 4
13660 // CHECK8-NEXT:    store i32 [[TMP37]], i32* [[DOTCAPTURE_EXPR_2]], align 4
13661 // CHECK8-NEXT:    [[TMP38:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
13662 // CHECK8-NEXT:    [[TMP39:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
13663 // CHECK8-NEXT:    [[SUB:%.*]] = sub i32 [[TMP38]], [[TMP39]]
13664 // CHECK8-NEXT:    [[SUB4:%.*]] = sub i32 [[SUB]], 1
13665 // CHECK8-NEXT:    [[ADD:%.*]] = add i32 [[SUB4]], 1
13666 // CHECK8-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], 1
13667 // CHECK8-NEXT:    [[SUB5:%.*]] = sub i32 [[DIV]], 1
13668 // CHECK8-NEXT:    store i32 [[SUB5]], i32* [[DOTCAPTURE_EXPR_3]], align 4
13669 // CHECK8-NEXT:    [[TMP40:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
13670 // CHECK8-NEXT:    [[ADD6:%.*]] = add i32 [[TMP40]], 1
13671 // CHECK8-NEXT:    [[TMP41:%.*]] = zext i32 [[ADD6]] to i64
13672 // CHECK8-NEXT:    call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 [[TMP41]])
13673 // CHECK8-NEXT:    [[TMP42:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197.region_id, i32 5, i8** [[TMP34]], i8** [[TMP35]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes.16, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.17, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1)
13674 // CHECK8-NEXT:    [[TMP43:%.*]] = icmp ne i32 [[TMP42]], 0
13675 // CHECK8-NEXT:    br i1 [[TMP43]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
13676 // CHECK8:       omp_offload.failed:
13677 // CHECK8-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], i32 [[TMP7]], [10 x i32]* [[B]]) #[[ATTR4]]
13678 // CHECK8-NEXT:    br label [[OMP_OFFLOAD_CONT]]
13679 // CHECK8:       omp_offload.cont:
13680 // CHECK8-NEXT:    br label [[OMP_IF_END:%.*]]
13681 // CHECK8:       omp_if.else:
13682 // CHECK8-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], i32 [[TMP7]], [10 x i32]* [[B]]) #[[ATTR4]]
13683 // CHECK8-NEXT:    br label [[OMP_IF_END]]
13684 // CHECK8:       omp_if.end:
13685 // CHECK8-NEXT:    [[TMP44:%.*]] = load i32, i32* [[A]], align 4
13686 // CHECK8-NEXT:    ret i32 [[TMP44]]
13687 //
13688 //
13689 // CHECK8-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
13690 // CHECK8-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat {
13691 // CHECK8-NEXT:  entry:
13692 // CHECK8-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
13693 // CHECK8-NEXT:    [[A:%.*]] = alloca i32, align 4
13694 // CHECK8-NEXT:    [[AA:%.*]] = alloca i16, align 2
13695 // CHECK8-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
13696 // CHECK8-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
13697 // CHECK8-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
13698 // CHECK8-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4
13699 // CHECK8-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4
13700 // CHECK8-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4
13701 // CHECK8-NEXT:    [[TMP:%.*]] = alloca i32, align 4
13702 // CHECK8-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
13703 // CHECK8-NEXT:    store i32 0, i32* [[A]], align 4
13704 // CHECK8-NEXT:    store i16 0, i16* [[AA]], align 2
13705 // CHECK8-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
13706 // CHECK8-NEXT:    store i32 [[TMP0]], i32* [[A_CASTED]], align 4
13707 // CHECK8-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
13708 // CHECK8-NEXT:    [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
13709 // CHECK8-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
13710 // CHECK8-NEXT:    store i16 [[TMP2]], i16* [[CONV]], align 2
13711 // CHECK8-NEXT:    [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
13712 // CHECK8-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
13713 // CHECK8-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40
13714 // CHECK8-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
13715 // CHECK8:       omp_if.then:
13716 // CHECK8-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
13717 // CHECK8-NEXT:    [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i32*
13718 // CHECK8-NEXT:    store i32 [[TMP1]], i32* [[TMP6]], align 4
13719 // CHECK8-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
13720 // CHECK8-NEXT:    [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32*
13721 // CHECK8-NEXT:    store i32 [[TMP1]], i32* [[TMP8]], align 4
13722 // CHECK8-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
13723 // CHECK8-NEXT:    store i8* null, i8** [[TMP9]], align 4
13724 // CHECK8-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
13725 // CHECK8-NEXT:    [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i32*
13726 // CHECK8-NEXT:    store i32 [[TMP3]], i32* [[TMP11]], align 4
13727 // CHECK8-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
13728 // CHECK8-NEXT:    [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32*
13729 // CHECK8-NEXT:    store i32 [[TMP3]], i32* [[TMP13]], align 4
13730 // CHECK8-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
13731 // CHECK8-NEXT:    store i8* null, i8** [[TMP14]], align 4
13732 // CHECK8-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
13733 // CHECK8-NEXT:    [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]**
13734 // CHECK8-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 4
13735 // CHECK8-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
13736 // CHECK8-NEXT:    [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]**
13737 // CHECK8-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 4
13738 // CHECK8-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
13739 // CHECK8-NEXT:    store i8* null, i8** [[TMP19]], align 4
13740 // CHECK8-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
13741 // CHECK8-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
13742 // CHECK8-NEXT:    call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10)
13743 // CHECK8-NEXT:    [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.19, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.20, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1)
13744 // CHECK8-NEXT:    [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0
13745 // CHECK8-NEXT:    br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
13746 // CHECK8:       omp_offload.failed:
13747 // CHECK8-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]]
13748 // CHECK8-NEXT:    br label [[OMP_OFFLOAD_CONT]]
13749 // CHECK8:       omp_offload.cont:
13750 // CHECK8-NEXT:    br label [[OMP_IF_END:%.*]]
13751 // CHECK8:       omp_if.else:
13752 // CHECK8-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]]
13753 // CHECK8-NEXT:    br label [[OMP_IF_END]]
13754 // CHECK8:       omp_if.end:
13755 // CHECK8-NEXT:    [[TMP24:%.*]] = load i32, i32* [[A]], align 4
13756 // CHECK8-NEXT:    ret i32 [[TMP24]]
13757 //
13758 //
13759 // CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215
13760 // CHECK8-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] {
13761 // CHECK8-NEXT:  entry:
13762 // CHECK8-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
13763 // CHECK8-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
13764 // CHECK8-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
13765 // CHECK8-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
13766 // CHECK8-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 4
13767 // CHECK8-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
13768 // CHECK8-NEXT:    [[B_CASTED:%.*]] = alloca i32, align 4
13769 // CHECK8-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
13770 // CHECK8-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
13771 // CHECK8-NEXT:    store i32 [[B]], i32* [[B_ADDR]], align 4
13772 // CHECK8-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
13773 // CHECK8-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
13774 // CHECK8-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 4
13775 // CHECK8-NEXT:    store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
13776 // CHECK8-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
13777 // CHECK8-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
13778 // CHECK8-NEXT:    [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
13779 // CHECK8-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
13780 // CHECK8-NEXT:    [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8*
13781 // CHECK8-NEXT:    [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4
13782 // CHECK8-NEXT:    store i32 [[TMP4]], i32* [[B_CASTED]], align 4
13783 // CHECK8-NEXT:    [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4
13784 // CHECK8-NEXT:    [[TMP6:%.*]] = load i8, i8* [[CONV]], align 1
13785 // CHECK8-NEXT:    [[TOBOOL:%.*]] = trunc i8 [[TMP6]] to i1
13786 // CHECK8-NEXT:    [[CONV3:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__CASTED]] to i8*
13787 // CHECK8-NEXT:    [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
13788 // CHECK8-NEXT:    store i8 [[FROMBOOL]], i8* [[CONV3]], align 1
13789 // CHECK8-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
13790 // CHECK8-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*, i32)* @.omp_outlined..12 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]], i32 [[TMP7]])
13791 // CHECK8-NEXT:    ret void
13792 //
13793 //
13794 // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..12
13795 // CHECK8-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] {
13796 // CHECK8-NEXT:  entry:
13797 // CHECK8-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
13798 // CHECK8-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
13799 // CHECK8-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
13800 // CHECK8-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
13801 // CHECK8-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
13802 // CHECK8-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
13803 // CHECK8-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 4
13804 // CHECK8-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
13805 // CHECK8-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
13806 // CHECK8-NEXT:    [[TMP:%.*]] = alloca i32, align 4
13807 // CHECK8-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
13808 // CHECK8-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
13809 // CHECK8-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
13810 // CHECK8-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
13811 // CHECK8-NEXT:    [[I:%.*]] = alloca i32, align 4
13812 // CHECK8-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
13813 // CHECK8-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
13814 // CHECK8-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
13815 // CHECK8-NEXT:    store i32 [[B]], i32* [[B_ADDR]], align 4
13816 // CHECK8-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
13817 // CHECK8-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
13818 // CHECK8-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 4
13819 // CHECK8-NEXT:    store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
13820 // CHECK8-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
13821 // CHECK8-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
13822 // CHECK8-NEXT:    [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
13823 // CHECK8-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
13824 // CHECK8-NEXT:    [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8*
13825 // CHECK8-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
13826 // CHECK8-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
13827 // CHECK8-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
13828 // CHECK8-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
13829 // CHECK8-NEXT:    [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
13830 // CHECK8-NEXT:    [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
13831 // CHECK8-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
13832 // CHECK8-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
13833 // CHECK8-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 9
13834 // CHECK8-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
13835 // CHECK8:       cond.true:
13836 // CHECK8-NEXT:    br label [[COND_END:%.*]]
13837 // CHECK8:       cond.false:
13838 // CHECK8-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
13839 // CHECK8-NEXT:    br label [[COND_END]]
13840 // CHECK8:       cond.end:
13841 // CHECK8-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
13842 // CHECK8-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
13843 // CHECK8-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
13844 // CHECK8-NEXT:    store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
13845 // CHECK8-NEXT:    [[TMP9:%.*]] = load i8, i8* [[CONV]], align 1
13846 // CHECK8-NEXT:    [[TOBOOL:%.*]] = trunc i8 [[TMP9]] to i1
13847 // CHECK8-NEXT:    br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
13848 // CHECK8:       omp_if.then:
13849 // CHECK8-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
13850 // CHECK8:       omp.inner.for.cond:
13851 // CHECK8-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !40
13852 // CHECK8-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !40
13853 // CHECK8-NEXT:    [[CMP3:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]
13854 // CHECK8-NEXT:    br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
13855 // CHECK8:       omp.inner.for.body:
13856 // CHECK8-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !40
13857 // CHECK8-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1
13858 // CHECK8-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
13859 // CHECK8-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !40
13860 // CHECK8-NEXT:    [[TMP13:%.*]] = load i32, i32* [[B_ADDR]], align 4, !llvm.access.group !40
13861 // CHECK8-NEXT:    [[CONV4:%.*]] = sitofp i32 [[TMP13]] to double
13862 // CHECK8-NEXT:    [[ADD5:%.*]] = fadd double [[CONV4]], 1.500000e+00
13863 // CHECK8-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
13864 // CHECK8-NEXT:    store double [[ADD5]], double* [[A]], align 4, !llvm.access.group !40
13865 // CHECK8-NEXT:    [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
13866 // CHECK8-NEXT:    [[TMP14:%.*]] = load double, double* [[A6]], align 4, !llvm.access.group !40
13867 // CHECK8-NEXT:    [[INC:%.*]] = fadd double [[TMP14]], 1.000000e+00
13868 // CHECK8-NEXT:    store double [[INC]], double* [[A6]], align 4, !llvm.access.group !40
13869 // CHECK8-NEXT:    [[CONV7:%.*]] = fptosi double [[INC]] to i16
13870 // CHECK8-NEXT:    [[TMP15:%.*]] = mul nsw i32 1, [[TMP2]]
13871 // CHECK8-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP15]]
13872 // CHECK8-NEXT:    [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
13873 // CHECK8-NEXT:    store i16 [[CONV7]], i16* [[ARRAYIDX8]], align 2, !llvm.access.group !40
13874 // CHECK8-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
13875 // CHECK8:       omp.body.continue:
13876 // CHECK8-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
13877 // CHECK8:       omp.inner.for.inc:
13878 // CHECK8-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !40
13879 // CHECK8-NEXT:    [[ADD9:%.*]] = add nsw i32 [[TMP16]], 1
13880 // CHECK8-NEXT:    store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !40
13881 // CHECK8-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP41:![0-9]+]]
13882 // CHECK8:       omp.inner.for.end:
13883 // CHECK8-NEXT:    br label [[OMP_IF_END:%.*]]
13884 // CHECK8:       omp_if.else:
13885 // CHECK8-NEXT:    br label [[OMP_INNER_FOR_COND10:%.*]]
13886 // CHECK8:       omp.inner.for.cond10:
13887 // CHECK8-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
13888 // CHECK8-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
13889 // CHECK8-NEXT:    [[CMP11:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]]
13890 // CHECK8-NEXT:    br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY12:%.*]], label [[OMP_INNER_FOR_END26:%.*]]
13891 // CHECK8:       omp.inner.for.body12:
13892 // CHECK8-NEXT:    [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
13893 // CHECK8-NEXT:    [[MUL13:%.*]] = mul nsw i32 [[TMP19]], 1
13894 // CHECK8-NEXT:    [[ADD14:%.*]] = add nsw i32 0, [[MUL13]]
13895 // CHECK8-NEXT:    store i32 [[ADD14]], i32* [[I]], align 4
13896 // CHECK8-NEXT:    [[TMP20:%.*]] = load i32, i32* [[B_ADDR]], align 4
13897 // CHECK8-NEXT:    [[CONV15:%.*]] = sitofp i32 [[TMP20]] to double
13898 // CHECK8-NEXT:    [[ADD16:%.*]] = fadd double [[CONV15]], 1.500000e+00
13899 // CHECK8-NEXT:    [[A17:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
13900 // CHECK8-NEXT:    store double [[ADD16]], double* [[A17]], align 4
13901 // CHECK8-NEXT:    [[A18:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
13902 // CHECK8-NEXT:    [[TMP21:%.*]] = load double, double* [[A18]], align 4
13903 // CHECK8-NEXT:    [[INC19:%.*]] = fadd double [[TMP21]], 1.000000e+00
13904 // CHECK8-NEXT:    store double [[INC19]], double* [[A18]], align 4
13905 // CHECK8-NEXT:    [[CONV20:%.*]] = fptosi double [[INC19]] to i16
13906 // CHECK8-NEXT:    [[TMP22:%.*]] = mul nsw i32 1, [[TMP2]]
13907 // CHECK8-NEXT:    [[ARRAYIDX21:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP22]]
13908 // CHECK8-NEXT:    [[ARRAYIDX22:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX21]], i32 1
13909 // CHECK8-NEXT:    store i16 [[CONV20]], i16* [[ARRAYIDX22]], align 2
13910 // CHECK8-NEXT:    br label [[OMP_BODY_CONTINUE23:%.*]]
13911 // CHECK8:       omp.body.continue23:
13912 // CHECK8-NEXT:    br label [[OMP_INNER_FOR_INC24:%.*]]
13913 // CHECK8:       omp.inner.for.inc24:
13914 // CHECK8-NEXT:    [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
13915 // CHECK8-NEXT:    [[ADD25:%.*]] = add nsw i32 [[TMP23]], 1
13916 // CHECK8-NEXT:    store i32 [[ADD25]], i32* [[DOTOMP_IV]], align 4
13917 // CHECK8-NEXT:    br label [[OMP_INNER_FOR_COND10]], !llvm.loop [[LOOP43:![0-9]+]]
13918 // CHECK8:       omp.inner.for.end26:
13919 // CHECK8-NEXT:    br label [[OMP_IF_END]]
13920 // CHECK8:       omp_if.end:
13921 // CHECK8-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
13922 // CHECK8:       omp.loop.exit:
13923 // CHECK8-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
13924 // CHECK8-NEXT:    [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
13925 // CHECK8-NEXT:    [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0
13926 // CHECK8-NEXT:    br i1 [[TMP25]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
13927 // CHECK8:       .omp.final.then:
13928 // CHECK8-NEXT:    store i32 10, i32* [[I]], align 4
13929 // CHECK8-NEXT:    br label [[DOTOMP_FINAL_DONE]]
13930 // CHECK8:       .omp.final.done:
13931 // CHECK8-NEXT:    ret void
13932 //
13933 //
13934 // CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197
13935 // CHECK8-SAME: (i32 noundef [[A:%.*]], i32 noundef [[N:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
13936 // CHECK8-NEXT:  entry:
13937 // CHECK8-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
13938 // CHECK8-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
13939 // CHECK8-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
13940 // CHECK8-NEXT:    [[AAA_ADDR:%.*]] = alloca i32, align 4
13941 // CHECK8-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
13942 // CHECK8-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
13943 // CHECK8-NEXT:    [[N_CASTED:%.*]] = alloca i32, align 4
13944 // CHECK8-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
13945 // CHECK8-NEXT:    [[AAA_CASTED:%.*]] = alloca i32, align 4
13946 // CHECK8-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
13947 // CHECK8-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
13948 // CHECK8-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
13949 // CHECK8-NEXT:    store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
13950 // CHECK8-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
13951 // CHECK8-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
13952 // CHECK8-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
13953 // CHECK8-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
13954 // CHECK8-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
13955 // CHECK8-NEXT:    store i32 [[TMP1]], i32* [[A_CASTED]], align 4
13956 // CHECK8-NEXT:    [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
13957 // CHECK8-NEXT:    [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
13958 // CHECK8-NEXT:    store i32 [[TMP3]], i32* [[N_CASTED]], align 4
13959 // CHECK8-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_CASTED]], align 4
13960 // CHECK8-NEXT:    [[TMP5:%.*]] = load i16, i16* [[CONV]], align 2
13961 // CHECK8-NEXT:    [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
13962 // CHECK8-NEXT:    store i16 [[TMP5]], i16* [[CONV2]], align 2
13963 // CHECK8-NEXT:    [[TMP6:%.*]] = load i32, i32* [[AA_CASTED]], align 4
13964 // CHECK8-NEXT:    [[TMP7:%.*]] = load i8, i8* [[CONV1]], align 1
13965 // CHECK8-NEXT:    [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
13966 // CHECK8-NEXT:    store i8 [[TMP7]], i8* [[CONV3]], align 1
13967 // CHECK8-NEXT:    [[TMP8:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
13968 // CHECK8-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, [10 x i32]*)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP8]], [10 x i32]* [[TMP0]])
13969 // CHECK8-NEXT:    ret void
13970 //
13971 //
13972 // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..15
13973 // CHECK8-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[N:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] {
13974 // CHECK8-NEXT:  entry:
13975 // CHECK8-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
13976 // CHECK8-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
13977 // CHECK8-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
13978 // CHECK8-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
13979 // CHECK8-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
13980 // CHECK8-NEXT:    [[AAA_ADDR:%.*]] = alloca i32, align 4
13981 // CHECK8-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
13982 // CHECK8-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
13983 // CHECK8-NEXT:    [[TMP:%.*]] = alloca i32, align 4
13984 // CHECK8-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
13985 // CHECK8-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
13986 // CHECK8-NEXT:    [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4
13987 // CHECK8-NEXT:    [[I:%.*]] = alloca i32, align 4
13988 // CHECK8-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
13989 // CHECK8-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
13990 // CHECK8-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
13991 // CHECK8-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
13992 // CHECK8-NEXT:    [[I6:%.*]] = alloca i32, align 4
13993 // CHECK8-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
13994 // CHECK8-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
13995 // CHECK8-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
13996 // CHECK8-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
13997 // CHECK8-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
13998 // CHECK8-NEXT:    store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
13999 // CHECK8-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
14000 // CHECK8-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
14001 // CHECK8-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
14002 // CHECK8-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
14003 // CHECK8-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
14004 // CHECK8-NEXT:    store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
14005 // CHECK8-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
14006 // CHECK8-NEXT:    store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4
14007 // CHECK8-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
14008 // CHECK8-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
14009 // CHECK8-NEXT:    [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]]
14010 // CHECK8-NEXT:    [[SUB4:%.*]] = sub i32 [[SUB]], 1
14011 // CHECK8-NEXT:    [[ADD:%.*]] = add i32 [[SUB4]], 1
14012 // CHECK8-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], 1
14013 // CHECK8-NEXT:    [[SUB5:%.*]] = sub i32 [[DIV]], 1
14014 // CHECK8-NEXT:    store i32 [[SUB5]], i32* [[DOTCAPTURE_EXPR_3]], align 4
14015 // CHECK8-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
14016 // CHECK8-NEXT:    store i32 [[TMP5]], i32* [[I]], align 4
14017 // CHECK8-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
14018 // CHECK8-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
14019 // CHECK8-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]]
14020 // CHECK8-NEXT:    br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
14021 // CHECK8:       omp.precond.then:
14022 // CHECK8-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
14023 // CHECK8-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
14024 // CHECK8-NEXT:    store i32 [[TMP8]], i32* [[DOTOMP_UB]], align 4
14025 // CHECK8-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
14026 // CHECK8-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
14027 // CHECK8-NEXT:    [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
14028 // CHECK8-NEXT:    [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
14029 // CHECK8-NEXT:    call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
14030 // CHECK8-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
14031 // CHECK8-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
14032 // CHECK8-NEXT:    [[CMP7:%.*]] = icmp ugt i32 [[TMP11]], [[TMP12]]
14033 // CHECK8-NEXT:    br i1 [[CMP7]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
14034 // CHECK8:       cond.true:
14035 // CHECK8-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
14036 // CHECK8-NEXT:    br label [[COND_END:%.*]]
14037 // CHECK8:       cond.false:
14038 // CHECK8-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
14039 // CHECK8-NEXT:    br label [[COND_END]]
14040 // CHECK8:       cond.end:
14041 // CHECK8-NEXT:    [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ]
14042 // CHECK8-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
14043 // CHECK8-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
14044 // CHECK8-NEXT:    store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4
14045 // CHECK8-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
14046 // CHECK8:       omp.inner.for.cond:
14047 // CHECK8-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !45
14048 // CHECK8-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !45
14049 // CHECK8-NEXT:    [[ADD8:%.*]] = add i32 [[TMP17]], 1
14050 // CHECK8-NEXT:    [[CMP9:%.*]] = icmp ult i32 [[TMP16]], [[ADD8]]
14051 // CHECK8-NEXT:    br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
14052 // CHECK8:       omp.inner.for.body:
14053 // CHECK8-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group !45
14054 // CHECK8-NEXT:    [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !45
14055 // CHECK8-NEXT:    [[MUL:%.*]] = mul i32 [[TMP19]], 1
14056 // CHECK8-NEXT:    [[ADD10:%.*]] = add i32 [[TMP18]], [[MUL]]
14057 // CHECK8-NEXT:    store i32 [[ADD10]], i32* [[I6]], align 4, !llvm.access.group !45
14058 // CHECK8-NEXT:    [[TMP20:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !45
14059 // CHECK8-NEXT:    [[ADD11:%.*]] = add nsw i32 [[TMP20]], 1
14060 // CHECK8-NEXT:    store i32 [[ADD11]], i32* [[A_ADDR]], align 4, !llvm.access.group !45
14061 // CHECK8-NEXT:    [[TMP21:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !45
14062 // CHECK8-NEXT:    [[CONV12:%.*]] = sext i16 [[TMP21]] to i32
14063 // CHECK8-NEXT:    [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1
14064 // CHECK8-NEXT:    [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16
14065 // CHECK8-NEXT:    store i16 [[CONV14]], i16* [[CONV]], align 2, !llvm.access.group !45
14066 // CHECK8-NEXT:    [[TMP22:%.*]] = load i8, i8* [[CONV1]], align 1, !llvm.access.group !45
14067 // CHECK8-NEXT:    [[CONV15:%.*]] = sext i8 [[TMP22]] to i32
14068 // CHECK8-NEXT:    [[ADD16:%.*]] = add nsw i32 [[CONV15]], 1
14069 // CHECK8-NEXT:    [[CONV17:%.*]] = trunc i32 [[ADD16]] to i8
14070 // CHECK8-NEXT:    store i8 [[CONV17]], i8* [[CONV1]], align 1, !llvm.access.group !45
14071 // CHECK8-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
14072 // CHECK8-NEXT:    [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !45
14073 // CHECK8-NEXT:    [[ADD18:%.*]] = add nsw i32 [[TMP23]], 1
14074 // CHECK8-NEXT:    store i32 [[ADD18]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !45
14075 // CHECK8-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
14076 // CHECK8:       omp.body.continue:
14077 // CHECK8-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
14078 // CHECK8:       omp.inner.for.inc:
14079 // CHECK8-NEXT:    [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !45
14080 // CHECK8-NEXT:    [[ADD19:%.*]] = add i32 [[TMP24]], 1
14081 // CHECK8-NEXT:    store i32 [[ADD19]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !45
14082 // CHECK8-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP46:![0-9]+]]
14083 // CHECK8:       omp.inner.for.end:
14084 // CHECK8-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
14085 // CHECK8:       omp.loop.exit:
14086 // CHECK8-NEXT:    [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
14087 // CHECK8-NEXT:    [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4
14088 // CHECK8-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]])
14089 // CHECK8-NEXT:    [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
14090 // CHECK8-NEXT:    [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0
14091 // CHECK8-NEXT:    br i1 [[TMP28]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
14092 // CHECK8:       .omp.final.then:
14093 // CHECK8-NEXT:    [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
14094 // CHECK8-NEXT:    [[TMP30:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
14095 // CHECK8-NEXT:    [[TMP31:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
14096 // CHECK8-NEXT:    [[SUB20:%.*]] = sub i32 [[TMP30]], [[TMP31]]
14097 // CHECK8-NEXT:    [[SUB21:%.*]] = sub i32 [[SUB20]], 1
14098 // CHECK8-NEXT:    [[ADD22:%.*]] = add i32 [[SUB21]], 1
14099 // CHECK8-NEXT:    [[DIV23:%.*]] = udiv i32 [[ADD22]], 1
14100 // CHECK8-NEXT:    [[MUL24:%.*]] = mul i32 [[DIV23]], 1
14101 // CHECK8-NEXT:    [[ADD25:%.*]] = add i32 [[TMP29]], [[MUL24]]
14102 // CHECK8-NEXT:    store i32 [[ADD25]], i32* [[I6]], align 4
14103 // CHECK8-NEXT:    br label [[DOTOMP_FINAL_DONE]]
14104 // CHECK8:       .omp.final.done:
14105 // CHECK8-NEXT:    br label [[OMP_PRECOND_END]]
14106 // CHECK8:       omp.precond.end:
14107 // CHECK8-NEXT:    ret void
14108 //
14109 //
14110 // CHECK8-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180
14111 // CHECK8-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
14112 // CHECK8-NEXT:  entry:
14113 // CHECK8-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
14114 // CHECK8-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
14115 // CHECK8-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
14116 // CHECK8-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
14117 // CHECK8-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
14118 // CHECK8-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
14119 // CHECK8-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
14120 // CHECK8-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
14121 // CHECK8-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
14122 // CHECK8-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
14123 // CHECK8-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
14124 // CHECK8-NEXT:    store i32 [[TMP1]], i32* [[A_CASTED]], align 4
14125 // CHECK8-NEXT:    [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
14126 // CHECK8-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
14127 // CHECK8-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
14128 // CHECK8-NEXT:    store i16 [[TMP3]], i16* [[CONV1]], align 2
14129 // CHECK8-NEXT:    [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
14130 // CHECK8-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..18 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]])
14131 // CHECK8-NEXT:    ret void
14132 //
14133 //
14134 // CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..18
14135 // CHECK8-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] {
14136 // CHECK8-NEXT:  entry:
14137 // CHECK8-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
14138 // CHECK8-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
14139 // CHECK8-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
14140 // CHECK8-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
14141 // CHECK8-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
14142 // CHECK8-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
14143 // CHECK8-NEXT:    [[TMP:%.*]] = alloca i32, align 4
14144 // CHECK8-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
14145 // CHECK8-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
14146 // CHECK8-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
14147 // CHECK8-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
14148 // CHECK8-NEXT:    [[I:%.*]] = alloca i32, align 4
14149 // CHECK8-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
14150 // CHECK8-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
14151 // CHECK8-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
14152 // CHECK8-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
14153 // CHECK8-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
14154 // CHECK8-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
14155 // CHECK8-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
14156 // CHECK8-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
14157 // CHECK8-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
14158 // CHECK8-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
14159 // CHECK8-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
14160 // CHECK8-NEXT:    [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
14161 // CHECK8-NEXT:    [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
14162 // CHECK8-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
14163 // CHECK8-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
14164 // CHECK8-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9
14165 // CHECK8-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
14166 // CHECK8:       cond.true:
14167 // CHECK8-NEXT:    br label [[COND_END:%.*]]
14168 // CHECK8:       cond.false:
14169 // CHECK8-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
14170 // CHECK8-NEXT:    br label [[COND_END]]
14171 // CHECK8:       cond.end:
14172 // CHECK8-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
14173 // CHECK8-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
14174 // CHECK8-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
14175 // CHECK8-NEXT:    store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
14176 // CHECK8-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
14177 // CHECK8:       omp.inner.for.cond:
14178 // CHECK8-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !48
14179 // CHECK8-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !48
14180 // CHECK8-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
14181 // CHECK8-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
14182 // CHECK8:       omp.inner.for.body:
14183 // CHECK8-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !48
14184 // CHECK8-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
14185 // CHECK8-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
14186 // CHECK8-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !48
14187 // CHECK8-NEXT:    [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !48
14188 // CHECK8-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
14189 // CHECK8-NEXT:    store i32 [[ADD2]], i32* [[A_ADDR]], align 4, !llvm.access.group !48
14190 // CHECK8-NEXT:    [[TMP10:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !48
14191 // CHECK8-NEXT:    [[CONV3:%.*]] = sext i16 [[TMP10]] to i32
14192 // CHECK8-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
14193 // CHECK8-NEXT:    [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
14194 // CHECK8-NEXT:    store i16 [[CONV5]], i16* [[CONV]], align 2, !llvm.access.group !48
14195 // CHECK8-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
14196 // CHECK8-NEXT:    [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !48
14197 // CHECK8-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1
14198 // CHECK8-NEXT:    store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !48
14199 // CHECK8-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
14200 // CHECK8:       omp.body.continue:
14201 // CHECK8-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
14202 // CHECK8:       omp.inner.for.inc:
14203 // CHECK8-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !48
14204 // CHECK8-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP12]], 1
14205 // CHECK8-NEXT:    store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !48
14206 // CHECK8-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP49:![0-9]+]]
14207 // CHECK8:       omp.inner.for.end:
14208 // CHECK8-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
14209 // CHECK8:       omp.loop.exit:
14210 // CHECK8-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
14211 // CHECK8-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
14212 // CHECK8-NEXT:    [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
14213 // CHECK8-NEXT:    br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
14214 // CHECK8:       .omp.final.then:
14215 // CHECK8-NEXT:    store i32 10, i32* [[I]], align 4
14216 // CHECK8-NEXT:    br label [[DOTOMP_FINAL_DONE]]
14217 // CHECK8:       .omp.final.done:
14218 // CHECK8-NEXT:    ret void
14219 //
14220 //
14221 // CHECK8-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
14222 // CHECK8-SAME: () #[[ATTR5]] {
14223 // CHECK8-NEXT:  entry:
14224 // CHECK8-NEXT:    call void @__tgt_register_requires(i64 1)
14225 // CHECK8-NEXT:    ret void
14226 //
14227 //
14228 // CHECK9-LABEL: define {{[^@]+}}@_Z3fooi
14229 // CHECK9-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0:[0-9]+]] {
14230 // CHECK9-NEXT:  entry:
14231 // CHECK9-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
14232 // CHECK9-NEXT:    [[A:%.*]] = alloca i32, align 4
14233 // CHECK9-NEXT:    [[AA:%.*]] = alloca i16, align 2
14234 // CHECK9-NEXT:    [[B:%.*]] = alloca [10 x float], align 4
14235 // CHECK9-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 8
14236 // CHECK9-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
14237 // CHECK9-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 8
14238 // CHECK9-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i64, align 8
14239 // CHECK9-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8
14240 // CHECK9-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
14241 // CHECK9-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
14242 // CHECK9-NEXT:    [[TMP:%.*]] = alloca i32, align 4
14243 // CHECK9-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
14244 // CHECK9-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
14245 // CHECK9-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
14246 // CHECK9-NEXT:    [[I:%.*]] = alloca i32, align 4
14247 // CHECK9-NEXT:    [[_TMP4:%.*]] = alloca i32, align 4
14248 // CHECK9-NEXT:    [[DOTOMP_LB5:%.*]] = alloca i32, align 4
14249 // CHECK9-NEXT:    [[DOTOMP_UB6:%.*]] = alloca i32, align 4
14250 // CHECK9-NEXT:    [[DOTOMP_IV7:%.*]] = alloca i32, align 4
14251 // CHECK9-NEXT:    [[DOTLINEAR_START:%.*]] = alloca i32, align 4
14252 // CHECK9-NEXT:    [[A8:%.*]] = alloca i32, align 4
14253 // CHECK9-NEXT:    [[A9:%.*]] = alloca i32, align 4
14254 // CHECK9-NEXT:    [[_TMP20:%.*]] = alloca i32, align 4
14255 // CHECK9-NEXT:    [[DOTOMP_LB21:%.*]] = alloca i32, align 4
14256 // CHECK9-NEXT:    [[DOTOMP_UB22:%.*]] = alloca i32, align 4
14257 // CHECK9-NEXT:    [[DOTOMP_IV23:%.*]] = alloca i32, align 4
14258 // CHECK9-NEXT:    [[I24:%.*]] = alloca i32, align 4
14259 // CHECK9-NEXT:    [[_TMP36:%.*]] = alloca i32, align 4
14260 // CHECK9-NEXT:    [[DOTOMP_LB37:%.*]] = alloca i32, align 4
14261 // CHECK9-NEXT:    [[DOTOMP_UB38:%.*]] = alloca i32, align 4
14262 // CHECK9-NEXT:    [[DOTOMP_IV39:%.*]] = alloca i32, align 4
14263 // CHECK9-NEXT:    [[I40:%.*]] = alloca i32, align 4
14264 // CHECK9-NEXT:    [[_TMP54:%.*]] = alloca i32, align 4
14265 // CHECK9-NEXT:    [[DOTOMP_LB55:%.*]] = alloca i32, align 4
14266 // CHECK9-NEXT:    [[DOTOMP_UB56:%.*]] = alloca i32, align 4
14267 // CHECK9-NEXT:    [[DOTOMP_IV57:%.*]] = alloca i32, align 4
14268 // CHECK9-NEXT:    [[I58:%.*]] = alloca i32, align 4
14269 // CHECK9-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
14270 // CHECK9-NEXT:    store i32 0, i32* [[A]], align 4
14271 // CHECK9-NEXT:    store i16 0, i16* [[AA]], align 2
14272 // CHECK9-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
14273 // CHECK9-NEXT:    [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
14274 // CHECK9-NEXT:    [[TMP2:%.*]] = call i8* @llvm.stacksave()
14275 // CHECK9-NEXT:    store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8
14276 // CHECK9-NEXT:    [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4
14277 // CHECK9-NEXT:    store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8
14278 // CHECK9-NEXT:    [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
14279 // CHECK9-NEXT:    [[TMP4:%.*]] = zext i32 [[TMP3]] to i64
14280 // CHECK9-NEXT:    [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]]
14281 // CHECK9-NEXT:    [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8
14282 // CHECK9-NEXT:    store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8
14283 // CHECK9-NEXT:    [[TMP6:%.*]] = load i32, i32* [[A]], align 4
14284 // CHECK9-NEXT:    store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_]], align 4
14285 // CHECK9-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
14286 // CHECK9-NEXT:    store i32 [[TMP7]], i32* [[DOTCAPTURE_EXPR_2]], align 4
14287 // CHECK9-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
14288 // CHECK9-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
14289 // CHECK9-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
14290 // CHECK9-NEXT:    store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
14291 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
14292 // CHECK9:       omp.inner.for.cond:
14293 // CHECK9-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
14294 // CHECK9-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !2
14295 // CHECK9-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
14296 // CHECK9-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
14297 // CHECK9:       omp.inner.for.body:
14298 // CHECK9-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
14299 // CHECK9-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
14300 // CHECK9-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
14301 // CHECK9-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !2
14302 // CHECK9-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
14303 // CHECK9:       omp.body.continue:
14304 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
14305 // CHECK9:       omp.inner.for.inc:
14306 // CHECK9-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
14307 // CHECK9-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1
14308 // CHECK9-NEXT:    store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
14309 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]
14310 // CHECK9:       omp.inner.for.end:
14311 // CHECK9-NEXT:    store i32 10, i32* [[I]], align 4
14312 // CHECK9-NEXT:    store i32 0, i32* [[DOTOMP_LB5]], align 4
14313 // CHECK9-NEXT:    store i32 9, i32* [[DOTOMP_UB6]], align 4
14314 // CHECK9-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB5]], align 4
14315 // CHECK9-NEXT:    store i32 [[TMP13]], i32* [[DOTOMP_IV7]], align 4
14316 // CHECK9-NEXT:    [[TMP14:%.*]] = load i32, i32* [[A]], align 4
14317 // CHECK9-NEXT:    store i32 [[TMP14]], i32* [[DOTLINEAR_START]], align 4
14318 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND10:%.*]]
14319 // CHECK9:       omp.inner.for.cond10:
14320 // CHECK9-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV7]], align 4
14321 // CHECK9-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB6]], align 4
14322 // CHECK9-NEXT:    [[CMP11:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]]
14323 // CHECK9-NEXT:    br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY12:%.*]], label [[OMP_INNER_FOR_END19:%.*]]
14324 // CHECK9:       omp.inner.for.body12:
14325 // CHECK9-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV7]], align 4
14326 // CHECK9-NEXT:    [[MUL13:%.*]] = mul nsw i32 [[TMP17]], 1
14327 // CHECK9-NEXT:    [[ADD14:%.*]] = add nsw i32 0, [[MUL13]]
14328 // CHECK9-NEXT:    store i32 [[ADD14]], i32* [[A8]], align 4
14329 // CHECK9-NEXT:    [[TMP18:%.*]] = load i32, i32* [[A8]], align 4
14330 // CHECK9-NEXT:    [[ADD15:%.*]] = add nsw i32 [[TMP18]], 1
14331 // CHECK9-NEXT:    store i32 [[ADD15]], i32* [[A8]], align 4
14332 // CHECK9-NEXT:    br label [[OMP_BODY_CONTINUE16:%.*]]
14333 // CHECK9:       omp.body.continue16:
14334 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_INC17:%.*]]
14335 // CHECK9:       omp.inner.for.inc17:
14336 // CHECK9-NEXT:    [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV7]], align 4
14337 // CHECK9-NEXT:    [[ADD18:%.*]] = add nsw i32 [[TMP19]], 1
14338 // CHECK9-NEXT:    store i32 [[ADD18]], i32* [[DOTOMP_IV7]], align 4
14339 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND10]], !llvm.loop [[LOOP7:![0-9]+]]
14340 // CHECK9:       omp.inner.for.end19:
14341 // CHECK9-NEXT:    store i32 10, i32* [[A]], align 4
14342 // CHECK9-NEXT:    store i32 0, i32* [[DOTOMP_LB21]], align 4
14343 // CHECK9-NEXT:    store i32 9, i32* [[DOTOMP_UB22]], align 4
14344 // CHECK9-NEXT:    [[TMP20:%.*]] = load i32, i32* [[DOTOMP_LB21]], align 4
14345 // CHECK9-NEXT:    store i32 [[TMP20]], i32* [[DOTOMP_IV23]], align 4
14346 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND25:%.*]]
14347 // CHECK9:       omp.inner.for.cond25:
14348 // CHECK9-NEXT:    [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV23]], align 4, !llvm.access.group !9
14349 // CHECK9-NEXT:    [[TMP22:%.*]] = load i32, i32* [[DOTOMP_UB22]], align 4, !llvm.access.group !9
14350 // CHECK9-NEXT:    [[CMP26:%.*]] = icmp sle i32 [[TMP21]], [[TMP22]]
14351 // CHECK9-NEXT:    br i1 [[CMP26]], label [[OMP_INNER_FOR_BODY27:%.*]], label [[OMP_INNER_FOR_END35:%.*]]
14352 // CHECK9:       omp.inner.for.body27:
14353 // CHECK9-NEXT:    [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV23]], align 4, !llvm.access.group !9
14354 // CHECK9-NEXT:    [[MUL28:%.*]] = mul nsw i32 [[TMP23]], 1
14355 // CHECK9-NEXT:    [[ADD29:%.*]] = add nsw i32 0, [[MUL28]]
14356 // CHECK9-NEXT:    store i32 [[ADD29]], i32* [[I24]], align 4, !llvm.access.group !9
14357 // CHECK9-NEXT:    [[TMP24:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !9
14358 // CHECK9-NEXT:    [[CONV:%.*]] = sext i16 [[TMP24]] to i32
14359 // CHECK9-NEXT:    [[ADD30:%.*]] = add nsw i32 [[CONV]], 1
14360 // CHECK9-NEXT:    [[CONV31:%.*]] = trunc i32 [[ADD30]] to i16
14361 // CHECK9-NEXT:    store i16 [[CONV31]], i16* [[AA]], align 2, !llvm.access.group !9
14362 // CHECK9-NEXT:    br label [[OMP_BODY_CONTINUE32:%.*]]
14363 // CHECK9:       omp.body.continue32:
14364 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_INC33:%.*]]
14365 // CHECK9:       omp.inner.for.inc33:
14366 // CHECK9-NEXT:    [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IV23]], align 4, !llvm.access.group !9
14367 // CHECK9-NEXT:    [[ADD34:%.*]] = add nsw i32 [[TMP25]], 1
14368 // CHECK9-NEXT:    store i32 [[ADD34]], i32* [[DOTOMP_IV23]], align 4, !llvm.access.group !9
14369 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND25]], !llvm.loop [[LOOP10:![0-9]+]]
14370 // CHECK9:       omp.inner.for.end35:
14371 // CHECK9-NEXT:    store i32 10, i32* [[I24]], align 4
14372 // CHECK9-NEXT:    store i32 0, i32* [[DOTOMP_LB37]], align 4
14373 // CHECK9-NEXT:    store i32 9, i32* [[DOTOMP_UB38]], align 4
14374 // CHECK9-NEXT:    [[TMP26:%.*]] = load i32, i32* [[DOTOMP_LB37]], align 4
14375 // CHECK9-NEXT:    store i32 [[TMP26]], i32* [[DOTOMP_IV39]], align 4
14376 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND41:%.*]]
14377 // CHECK9:       omp.inner.for.cond41:
14378 // CHECK9-NEXT:    [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV39]], align 4, !llvm.access.group !12
14379 // CHECK9-NEXT:    [[TMP28:%.*]] = load i32, i32* [[DOTOMP_UB38]], align 4, !llvm.access.group !12
14380 // CHECK9-NEXT:    [[CMP42:%.*]] = icmp sle i32 [[TMP27]], [[TMP28]]
14381 // CHECK9-NEXT:    br i1 [[CMP42]], label [[OMP_INNER_FOR_BODY43:%.*]], label [[OMP_INNER_FOR_END53:%.*]]
14382 // CHECK9:       omp.inner.for.body43:
14383 // CHECK9-NEXT:    [[TMP29:%.*]] = load i32, i32* [[DOTOMP_IV39]], align 4, !llvm.access.group !12
14384 // CHECK9-NEXT:    [[MUL44:%.*]] = mul nsw i32 [[TMP29]], 1
14385 // CHECK9-NEXT:    [[ADD45:%.*]] = add nsw i32 0, [[MUL44]]
14386 // CHECK9-NEXT:    store i32 [[ADD45]], i32* [[I40]], align 4, !llvm.access.group !12
14387 // CHECK9-NEXT:    [[TMP30:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !12
14388 // CHECK9-NEXT:    [[ADD46:%.*]] = add nsw i32 [[TMP30]], 1
14389 // CHECK9-NEXT:    store i32 [[ADD46]], i32* [[A]], align 4, !llvm.access.group !12
14390 // CHECK9-NEXT:    [[TMP31:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !12
14391 // CHECK9-NEXT:    [[CONV47:%.*]] = sext i16 [[TMP31]] to i32
14392 // CHECK9-NEXT:    [[ADD48:%.*]] = add nsw i32 [[CONV47]], 1
14393 // CHECK9-NEXT:    [[CONV49:%.*]] = trunc i32 [[ADD48]] to i16
14394 // CHECK9-NEXT:    store i16 [[CONV49]], i16* [[AA]], align 2, !llvm.access.group !12
14395 // CHECK9-NEXT:    br label [[OMP_BODY_CONTINUE50:%.*]]
14396 // CHECK9:       omp.body.continue50:
14397 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_INC51:%.*]]
14398 // CHECK9:       omp.inner.for.inc51:
14399 // CHECK9-NEXT:    [[TMP32:%.*]] = load i32, i32* [[DOTOMP_IV39]], align 4, !llvm.access.group !12
14400 // CHECK9-NEXT:    [[ADD52:%.*]] = add nsw i32 [[TMP32]], 1
14401 // CHECK9-NEXT:    store i32 [[ADD52]], i32* [[DOTOMP_IV39]], align 4, !llvm.access.group !12
14402 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND41]], !llvm.loop [[LOOP13:![0-9]+]]
14403 // CHECK9:       omp.inner.for.end53:
14404 // CHECK9-NEXT:    store i32 10, i32* [[I40]], align 4
14405 // CHECK9-NEXT:    store i32 0, i32* [[DOTOMP_LB55]], align 4
14406 // CHECK9-NEXT:    store i32 9, i32* [[DOTOMP_UB56]], align 4
14407 // CHECK9-NEXT:    [[TMP33:%.*]] = load i32, i32* [[DOTOMP_LB55]], align 4
14408 // CHECK9-NEXT:    store i32 [[TMP33]], i32* [[DOTOMP_IV57]], align 4
14409 // CHECK9-NEXT:    [[ARRAYDECAY:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 0
14410 // CHECK9-NEXT:    call void @llvm.assume(i1 true) [ "align"(float* [[ARRAYDECAY]], i64 16) ]
14411 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND59:%.*]]
14412 // CHECK9:       omp.inner.for.cond59:
14413 // CHECK9-NEXT:    [[TMP34:%.*]] = load i32, i32* [[DOTOMP_IV57]], align 4, !llvm.access.group !15
14414 // CHECK9-NEXT:    [[TMP35:%.*]] = load i32, i32* [[DOTOMP_UB56]], align 4, !llvm.access.group !15
14415 // CHECK9-NEXT:    [[CMP60:%.*]] = icmp sle i32 [[TMP34]], [[TMP35]]
14416 // CHECK9-NEXT:    br i1 [[CMP60]], label [[OMP_INNER_FOR_BODY61:%.*]], label [[OMP_INNER_FOR_END85:%.*]]
14417 // CHECK9:       omp.inner.for.body61:
14418 // CHECK9-NEXT:    [[TMP36:%.*]] = load i32, i32* [[DOTOMP_IV57]], align 4, !llvm.access.group !15
14419 // CHECK9-NEXT:    [[MUL62:%.*]] = mul nsw i32 [[TMP36]], 1
14420 // CHECK9-NEXT:    [[ADD63:%.*]] = add nsw i32 0, [[MUL62]]
14421 // CHECK9-NEXT:    store i32 [[ADD63]], i32* [[I58]], align 4, !llvm.access.group !15
14422 // CHECK9-NEXT:    [[TMP37:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !15
14423 // CHECK9-NEXT:    [[ADD64:%.*]] = add nsw i32 [[TMP37]], 1
14424 // CHECK9-NEXT:    store i32 [[ADD64]], i32* [[A]], align 4, !llvm.access.group !15
14425 // CHECK9-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2
14426 // CHECK9-NEXT:    [[TMP38:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !15
14427 // CHECK9-NEXT:    [[CONV65:%.*]] = fpext float [[TMP38]] to double
14428 // CHECK9-NEXT:    [[ADD66:%.*]] = fadd double [[CONV65]], 1.000000e+00
14429 // CHECK9-NEXT:    [[CONV67:%.*]] = fptrunc double [[ADD66]] to float
14430 // CHECK9-NEXT:    store float [[CONV67]], float* [[ARRAYIDX]], align 4, !llvm.access.group !15
14431 // CHECK9-NEXT:    [[ARRAYIDX68:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3
14432 // CHECK9-NEXT:    [[TMP39:%.*]] = load float, float* [[ARRAYIDX68]], align 4, !llvm.access.group !15
14433 // CHECK9-NEXT:    [[CONV69:%.*]] = fpext float [[TMP39]] to double
14434 // CHECK9-NEXT:    [[ADD70:%.*]] = fadd double [[CONV69]], 1.000000e+00
14435 // CHECK9-NEXT:    [[CONV71:%.*]] = fptrunc double [[ADD70]] to float
14436 // CHECK9-NEXT:    store float [[CONV71]], float* [[ARRAYIDX68]], align 4, !llvm.access.group !15
14437 // CHECK9-NEXT:    [[ARRAYIDX72:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1
14438 // CHECK9-NEXT:    [[ARRAYIDX73:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX72]], i64 0, i64 2
14439 // CHECK9-NEXT:    [[TMP40:%.*]] = load double, double* [[ARRAYIDX73]], align 8, !llvm.access.group !15
14440 // CHECK9-NEXT:    [[ADD74:%.*]] = fadd double [[TMP40]], 1.000000e+00
14441 // CHECK9-NEXT:    store double [[ADD74]], double* [[ARRAYIDX73]], align 8, !llvm.access.group !15
14442 // CHECK9-NEXT:    [[TMP41:%.*]] = mul nsw i64 1, [[TMP4]]
14443 // CHECK9-NEXT:    [[ARRAYIDX75:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP41]]
14444 // CHECK9-NEXT:    [[ARRAYIDX76:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX75]], i64 3
14445 // CHECK9-NEXT:    [[TMP42:%.*]] = load double, double* [[ARRAYIDX76]], align 8, !llvm.access.group !15
14446 // CHECK9-NEXT:    [[ADD77:%.*]] = fadd double [[TMP42]], 1.000000e+00
14447 // CHECK9-NEXT:    store double [[ADD77]], double* [[ARRAYIDX76]], align 8, !llvm.access.group !15
14448 // CHECK9-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0
14449 // CHECK9-NEXT:    [[TMP43:%.*]] = load i64, i64* [[X]], align 8, !llvm.access.group !15
14450 // CHECK9-NEXT:    [[ADD78:%.*]] = add nsw i64 [[TMP43]], 1
14451 // CHECK9-NEXT:    store i64 [[ADD78]], i64* [[X]], align 8, !llvm.access.group !15
14452 // CHECK9-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1
14453 // CHECK9-NEXT:    [[TMP44:%.*]] = load i8, i8* [[Y]], align 8, !llvm.access.group !15
14454 // CHECK9-NEXT:    [[CONV79:%.*]] = sext i8 [[TMP44]] to i32
14455 // CHECK9-NEXT:    [[ADD80:%.*]] = add nsw i32 [[CONV79]], 1
14456 // CHECK9-NEXT:    [[CONV81:%.*]] = trunc i32 [[ADD80]] to i8
14457 // CHECK9-NEXT:    store i8 [[CONV81]], i8* [[Y]], align 8, !llvm.access.group !15
14458 // CHECK9-NEXT:    br label [[OMP_BODY_CONTINUE82:%.*]]
14459 // CHECK9:       omp.body.continue82:
14460 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_INC83:%.*]]
14461 // CHECK9:       omp.inner.for.inc83:
14462 // CHECK9-NEXT:    [[TMP45:%.*]] = load i32, i32* [[DOTOMP_IV57]], align 4, !llvm.access.group !15
14463 // CHECK9-NEXT:    [[ADD84:%.*]] = add nsw i32 [[TMP45]], 1
14464 // CHECK9-NEXT:    store i32 [[ADD84]], i32* [[DOTOMP_IV57]], align 4, !llvm.access.group !15
14465 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND59]], !llvm.loop [[LOOP16:![0-9]+]]
14466 // CHECK9:       omp.inner.for.end85:
14467 // CHECK9-NEXT:    store i32 10, i32* [[I58]], align 4
14468 // CHECK9-NEXT:    [[TMP46:%.*]] = load i32, i32* [[A]], align 4
14469 // CHECK9-NEXT:    [[TMP47:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
14470 // CHECK9-NEXT:    call void @llvm.stackrestore(i8* [[TMP47]])
14471 // CHECK9-NEXT:    ret i32 [[TMP46]]
14472 //
14473 //
14474 // CHECK9-LABEL: define {{[^@]+}}@_Z3bari
14475 // CHECK9-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {
14476 // CHECK9-NEXT:  entry:
14477 // CHECK9-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
14478 // CHECK9-NEXT:    [[A:%.*]] = alloca i32, align 4
14479 // CHECK9-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8
14480 // CHECK9-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
14481 // CHECK9-NEXT:    store i32 0, i32* [[A]], align 4
14482 // CHECK9-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
14483 // CHECK9-NEXT:    [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]])
14484 // CHECK9-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
14485 // CHECK9-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
14486 // CHECK9-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
14487 // CHECK9-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
14488 // CHECK9-NEXT:    [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP2]])
14489 // CHECK9-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
14490 // CHECK9-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
14491 // CHECK9-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
14492 // CHECK9-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
14493 // CHECK9-NEXT:    [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]])
14494 // CHECK9-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
14495 // CHECK9-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
14496 // CHECK9-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
14497 // CHECK9-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
14498 // CHECK9-NEXT:    [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]])
14499 // CHECK9-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
14500 // CHECK9-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
14501 // CHECK9-NEXT:    store i32 [[ADD6]], i32* [[A]], align 4
14502 // CHECK9-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
14503 // CHECK9-NEXT:    ret i32 [[TMP8]]
14504 //
14505 //
14506 // CHECK9-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
14507 // CHECK9-SAME: (%struct.S1* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 {
14508 // CHECK9-NEXT:  entry:
14509 // CHECK9-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
14510 // CHECK9-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
14511 // CHECK9-NEXT:    [[B:%.*]] = alloca i32, align 4
14512 // CHECK9-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 8
14513 // CHECK9-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
14514 // CHECK9-NEXT:    [[TMP:%.*]] = alloca i32, align 4
14515 // CHECK9-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
14516 // CHECK9-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
14517 // CHECK9-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
14518 // CHECK9-NEXT:    [[I:%.*]] = alloca i32, align 4
14519 // CHECK9-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
14520 // CHECK9-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
14521 // CHECK9-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
14522 // CHECK9-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
14523 // CHECK9-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
14524 // CHECK9-NEXT:    store i32 [[ADD]], i32* [[B]], align 4
14525 // CHECK9-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
14526 // CHECK9-NEXT:    [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
14527 // CHECK9-NEXT:    [[TMP3:%.*]] = call i8* @llvm.stacksave()
14528 // CHECK9-NEXT:    store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8
14529 // CHECK9-NEXT:    [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]
14530 // CHECK9-NEXT:    [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2
14531 // CHECK9-NEXT:    store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8
14532 // CHECK9-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
14533 // CHECK9-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
14534 // CHECK9-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
14535 // CHECK9-NEXT:    store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
14536 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
14537 // CHECK9:       omp.inner.for.cond:
14538 // CHECK9-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
14539 // CHECK9-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !18
14540 // CHECK9-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
14541 // CHECK9-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
14542 // CHECK9:       omp.inner.for.body:
14543 // CHECK9-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
14544 // CHECK9-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
14545 // CHECK9-NEXT:    [[ADD2:%.*]] = add nsw i32 0, [[MUL]]
14546 // CHECK9-NEXT:    store i32 [[ADD2]], i32* [[I]], align 4, !llvm.access.group !18
14547 // CHECK9-NEXT:    [[TMP9:%.*]] = load i32, i32* [[B]], align 4, !llvm.access.group !18
14548 // CHECK9-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP9]] to double
14549 // CHECK9-NEXT:    [[ADD3:%.*]] = fadd double [[CONV]], 1.500000e+00
14550 // CHECK9-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
14551 // CHECK9-NEXT:    store double [[ADD3]], double* [[A]], align 8, !llvm.access.group !18
14552 // CHECK9-NEXT:    [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
14553 // CHECK9-NEXT:    [[TMP10:%.*]] = load double, double* [[A4]], align 8, !llvm.access.group !18
14554 // CHECK9-NEXT:    [[INC:%.*]] = fadd double [[TMP10]], 1.000000e+00
14555 // CHECK9-NEXT:    store double [[INC]], double* [[A4]], align 8, !llvm.access.group !18
14556 // CHECK9-NEXT:    [[CONV5:%.*]] = fptosi double [[INC]] to i16
14557 // CHECK9-NEXT:    [[TMP11:%.*]] = mul nsw i64 1, [[TMP2]]
14558 // CHECK9-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP11]]
14559 // CHECK9-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
14560 // CHECK9-NEXT:    store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2, !llvm.access.group !18
14561 // CHECK9-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
14562 // CHECK9:       omp.body.continue:
14563 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
14564 // CHECK9:       omp.inner.for.inc:
14565 // CHECK9-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
14566 // CHECK9-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP12]], 1
14567 // CHECK9-NEXT:    store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
14568 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]
14569 // CHECK9:       omp.inner.for.end:
14570 // CHECK9-NEXT:    store i32 10, i32* [[I]], align 4
14571 // CHECK9-NEXT:    [[TMP13:%.*]] = mul nsw i64 1, [[TMP2]]
14572 // CHECK9-NEXT:    [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP13]]
14573 // CHECK9-NEXT:    [[ARRAYIDX9:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX8]], i64 1
14574 // CHECK9-NEXT:    [[TMP14:%.*]] = load i16, i16* [[ARRAYIDX9]], align 2
14575 // CHECK9-NEXT:    [[CONV10:%.*]] = sext i16 [[TMP14]] to i32
14576 // CHECK9-NEXT:    [[TMP15:%.*]] = load i32, i32* [[B]], align 4
14577 // CHECK9-NEXT:    [[ADD11:%.*]] = add nsw i32 [[CONV10]], [[TMP15]]
14578 // CHECK9-NEXT:    [[TMP16:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
14579 // CHECK9-NEXT:    call void @llvm.stackrestore(i8* [[TMP16]])
14580 // CHECK9-NEXT:    ret i32 [[ADD11]]
14581 //
14582 //
14583 // CHECK9-LABEL: define {{[^@]+}}@_ZL7fstatici
14584 // CHECK9-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {
14585 // CHECK9-NEXT:  entry:
14586 // CHECK9-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
14587 // CHECK9-NEXT:    [[A:%.*]] = alloca i32, align 4
14588 // CHECK9-NEXT:    [[AA:%.*]] = alloca i16, align 2
14589 // CHECK9-NEXT:    [[AAA:%.*]] = alloca i8, align 1
14590 // CHECK9-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
14591 // CHECK9-NEXT:    [[TMP:%.*]] = alloca i32, align 4
14592 // CHECK9-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
14593 // CHECK9-NEXT:    [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
14594 // CHECK9-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
14595 // CHECK9-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
14596 // CHECK9-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
14597 // CHECK9-NEXT:    [[I:%.*]] = alloca i32, align 4
14598 // CHECK9-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
14599 // CHECK9-NEXT:    [[I5:%.*]] = alloca i32, align 4
14600 // CHECK9-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
14601 // CHECK9-NEXT:    store i32 0, i32* [[A]], align 4
14602 // CHECK9-NEXT:    store i16 0, i16* [[AA]], align 2
14603 // CHECK9-NEXT:    store i8 0, i8* [[AAA]], align 1
14604 // CHECK9-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
14605 // CHECK9-NEXT:    store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4
14606 // CHECK9-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
14607 // CHECK9-NEXT:    store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_1]], align 4
14608 // CHECK9-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
14609 // CHECK9-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
14610 // CHECK9-NEXT:    [[SUB:%.*]] = sub i32 [[TMP2]], [[TMP3]]
14611 // CHECK9-NEXT:    [[SUB3:%.*]] = sub i32 [[SUB]], 1
14612 // CHECK9-NEXT:    [[ADD:%.*]] = add i32 [[SUB3]], 1
14613 // CHECK9-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], 1
14614 // CHECK9-NEXT:    [[SUB4:%.*]] = sub i32 [[DIV]], 1
14615 // CHECK9-NEXT:    store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_2]], align 4
14616 // CHECK9-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
14617 // CHECK9-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
14618 // CHECK9-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_UB]], align 4
14619 // CHECK9-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
14620 // CHECK9-NEXT:    store i32 [[TMP5]], i32* [[I]], align 4
14621 // CHECK9-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
14622 // CHECK9-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
14623 // CHECK9-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]]
14624 // CHECK9-NEXT:    br i1 [[CMP]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END:%.*]]
14625 // CHECK9:       simd.if.then:
14626 // CHECK9-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
14627 // CHECK9-NEXT:    store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
14628 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
14629 // CHECK9:       omp.inner.for.cond:
14630 // CHECK9-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
14631 // CHECK9-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !21
14632 // CHECK9-NEXT:    [[ADD6:%.*]] = add i32 [[TMP10]], 1
14633 // CHECK9-NEXT:    [[CMP7:%.*]] = icmp ult i32 [[TMP9]], [[ADD6]]
14634 // CHECK9-NEXT:    br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
14635 // CHECK9:       omp.inner.for.body:
14636 // CHECK9-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group !21
14637 // CHECK9-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
14638 // CHECK9-NEXT:    [[MUL:%.*]] = mul i32 [[TMP12]], 1
14639 // CHECK9-NEXT:    [[ADD8:%.*]] = add i32 [[TMP11]], [[MUL]]
14640 // CHECK9-NEXT:    store i32 [[ADD8]], i32* [[I5]], align 4, !llvm.access.group !21
14641 // CHECK9-NEXT:    [[TMP13:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !21
14642 // CHECK9-NEXT:    [[ADD9:%.*]] = add nsw i32 [[TMP13]], 1
14643 // CHECK9-NEXT:    store i32 [[ADD9]], i32* [[A]], align 4, !llvm.access.group !21
14644 // CHECK9-NEXT:    [[TMP14:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !21
14645 // CHECK9-NEXT:    [[CONV:%.*]] = sext i16 [[TMP14]] to i32
14646 // CHECK9-NEXT:    [[ADD10:%.*]] = add nsw i32 [[CONV]], 1
14647 // CHECK9-NEXT:    [[CONV11:%.*]] = trunc i32 [[ADD10]] to i16
14648 // CHECK9-NEXT:    store i16 [[CONV11]], i16* [[AA]], align 2, !llvm.access.group !21
14649 // CHECK9-NEXT:    [[TMP15:%.*]] = load i8, i8* [[AAA]], align 1, !llvm.access.group !21
14650 // CHECK9-NEXT:    [[CONV12:%.*]] = sext i8 [[TMP15]] to i32
14651 // CHECK9-NEXT:    [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1
14652 // CHECK9-NEXT:    [[CONV14:%.*]] = trunc i32 [[ADD13]] to i8
14653 // CHECK9-NEXT:    store i8 [[CONV14]], i8* [[AAA]], align 1, !llvm.access.group !21
14654 // CHECK9-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2
14655 // CHECK9-NEXT:    [[TMP16:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !21
14656 // CHECK9-NEXT:    [[ADD15:%.*]] = add nsw i32 [[TMP16]], 1
14657 // CHECK9-NEXT:    store i32 [[ADD15]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !21
14658 // CHECK9-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
14659 // CHECK9:       omp.body.continue:
14660 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
14661 // CHECK9:       omp.inner.for.inc:
14662 // CHECK9-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
14663 // CHECK9-NEXT:    [[ADD16:%.*]] = add i32 [[TMP17]], 1
14664 // CHECK9-NEXT:    store i32 [[ADD16]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
14665 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]]
14666 // CHECK9:       omp.inner.for.end:
14667 // CHECK9-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
14668 // CHECK9-NEXT:    [[TMP19:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
14669 // CHECK9-NEXT:    [[TMP20:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
14670 // CHECK9-NEXT:    [[SUB17:%.*]] = sub i32 [[TMP19]], [[TMP20]]
14671 // CHECK9-NEXT:    [[SUB18:%.*]] = sub i32 [[SUB17]], 1
14672 // CHECK9-NEXT:    [[ADD19:%.*]] = add i32 [[SUB18]], 1
14673 // CHECK9-NEXT:    [[DIV20:%.*]] = udiv i32 [[ADD19]], 1
14674 // CHECK9-NEXT:    [[MUL21:%.*]] = mul i32 [[DIV20]], 1
14675 // CHECK9-NEXT:    [[ADD22:%.*]] = add i32 [[TMP18]], [[MUL21]]
14676 // CHECK9-NEXT:    store i32 [[ADD22]], i32* [[I5]], align 4
14677 // CHECK9-NEXT:    br label [[SIMD_IF_END]]
14678 // CHECK9:       simd.if.end:
14679 // CHECK9-NEXT:    [[TMP21:%.*]] = load i32, i32* [[A]], align 4
14680 // CHECK9-NEXT:    ret i32 [[TMP21]]
14681 //
14682 //
14683 // CHECK9-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
14684 // CHECK9-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat {
14685 // CHECK9-NEXT:  entry:
14686 // CHECK9-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
14687 // CHECK9-NEXT:    [[A:%.*]] = alloca i32, align 4
14688 // CHECK9-NEXT:    [[AA:%.*]] = alloca i16, align 2
14689 // CHECK9-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
14690 // CHECK9-NEXT:    [[TMP:%.*]] = alloca i32, align 4
14691 // CHECK9-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
14692 // CHECK9-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
14693 // CHECK9-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
14694 // CHECK9-NEXT:    [[I:%.*]] = alloca i32, align 4
14695 // CHECK9-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
14696 // CHECK9-NEXT:    store i32 0, i32* [[A]], align 4
14697 // CHECK9-NEXT:    store i16 0, i16* [[AA]], align 2
14698 // CHECK9-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
14699 // CHECK9-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
14700 // CHECK9-NEXT:    [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
14701 // CHECK9-NEXT:    store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4
14702 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
14703 // CHECK9:       omp.inner.for.cond:
14704 // CHECK9-NEXT:    [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
14705 // CHECK9-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !24
14706 // CHECK9-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
14707 // CHECK9-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
14708 // CHECK9:       omp.inner.for.body:
14709 // CHECK9-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
14710 // CHECK9-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1
14711 // CHECK9-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
14712 // CHECK9-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !24
14713 // CHECK9-NEXT:    [[TMP4:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !24
14714 // CHECK9-NEXT:    [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1
14715 // CHECK9-NEXT:    store i32 [[ADD1]], i32* [[A]], align 4, !llvm.access.group !24
14716 // CHECK9-NEXT:    [[TMP5:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !24
14717 // CHECK9-NEXT:    [[CONV:%.*]] = sext i16 [[TMP5]] to i32
14718 // CHECK9-NEXT:    [[ADD2:%.*]] = add nsw i32 [[CONV]], 1
14719 // CHECK9-NEXT:    [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
14720 // CHECK9-NEXT:    store i16 [[CONV3]], i16* [[AA]], align 2, !llvm.access.group !24
14721 // CHECK9-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2
14722 // CHECK9-NEXT:    [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !24
14723 // CHECK9-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP6]], 1
14724 // CHECK9-NEXT:    store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !24
14725 // CHECK9-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
14726 // CHECK9:       omp.body.continue:
14727 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
14728 // CHECK9:       omp.inner.for.inc:
14729 // CHECK9-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
14730 // CHECK9-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP7]], 1
14731 // CHECK9-NEXT:    store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
14732 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]]
14733 // CHECK9:       omp.inner.for.end:
14734 // CHECK9-NEXT:    store i32 10, i32* [[I]], align 4
14735 // CHECK9-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
14736 // CHECK9-NEXT:    ret i32 [[TMP8]]
14737 //
14738 //
14739 // CHECK10-LABEL: define {{[^@]+}}@_Z3fooi
14740 // CHECK10-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0:[0-9]+]] {
14741 // CHECK10-NEXT:  entry:
14742 // CHECK10-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
14743 // CHECK10-NEXT:    [[A:%.*]] = alloca i32, align 4
14744 // CHECK10-NEXT:    [[AA:%.*]] = alloca i16, align 2
14745 // CHECK10-NEXT:    [[B:%.*]] = alloca [10 x float], align 4
14746 // CHECK10-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 8
14747 // CHECK10-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
14748 // CHECK10-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 8
14749 // CHECK10-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i64, align 8
14750 // CHECK10-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8
14751 // CHECK10-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
14752 // CHECK10-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
14753 // CHECK10-NEXT:    [[TMP:%.*]] = alloca i32, align 4
14754 // CHECK10-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
14755 // CHECK10-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
14756 // CHECK10-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
14757 // CHECK10-NEXT:    [[I:%.*]] = alloca i32, align 4
14758 // CHECK10-NEXT:    [[_TMP4:%.*]] = alloca i32, align 4
14759 // CHECK10-NEXT:    [[DOTOMP_LB5:%.*]] = alloca i32, align 4
14760 // CHECK10-NEXT:    [[DOTOMP_UB6:%.*]] = alloca i32, align 4
14761 // CHECK10-NEXT:    [[DOTOMP_IV7:%.*]] = alloca i32, align 4
14762 // CHECK10-NEXT:    [[DOTLINEAR_START:%.*]] = alloca i32, align 4
14763 // CHECK10-NEXT:    [[A8:%.*]] = alloca i32, align 4
14764 // CHECK10-NEXT:    [[A9:%.*]] = alloca i32, align 4
14765 // CHECK10-NEXT:    [[_TMP20:%.*]] = alloca i32, align 4
14766 // CHECK10-NEXT:    [[DOTOMP_LB21:%.*]] = alloca i32, align 4
14767 // CHECK10-NEXT:    [[DOTOMP_UB22:%.*]] = alloca i32, align 4
14768 // CHECK10-NEXT:    [[DOTOMP_IV23:%.*]] = alloca i32, align 4
14769 // CHECK10-NEXT:    [[I24:%.*]] = alloca i32, align 4
14770 // CHECK10-NEXT:    [[_TMP36:%.*]] = alloca i32, align 4
14771 // CHECK10-NEXT:    [[DOTOMP_LB37:%.*]] = alloca i32, align 4
14772 // CHECK10-NEXT:    [[DOTOMP_UB38:%.*]] = alloca i32, align 4
14773 // CHECK10-NEXT:    [[DOTOMP_IV39:%.*]] = alloca i32, align 4
14774 // CHECK10-NEXT:    [[I40:%.*]] = alloca i32, align 4
14775 // CHECK10-NEXT:    [[_TMP54:%.*]] = alloca i32, align 4
14776 // CHECK10-NEXT:    [[DOTOMP_LB55:%.*]] = alloca i32, align 4
14777 // CHECK10-NEXT:    [[DOTOMP_UB56:%.*]] = alloca i32, align 4
14778 // CHECK10-NEXT:    [[DOTOMP_IV57:%.*]] = alloca i32, align 4
14779 // CHECK10-NEXT:    [[I58:%.*]] = alloca i32, align 4
14780 // CHECK10-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
14781 // CHECK10-NEXT:    store i32 0, i32* [[A]], align 4
14782 // CHECK10-NEXT:    store i16 0, i16* [[AA]], align 2
14783 // CHECK10-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
14784 // CHECK10-NEXT:    [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
14785 // CHECK10-NEXT:    [[TMP2:%.*]] = call i8* @llvm.stacksave()
14786 // CHECK10-NEXT:    store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8
14787 // CHECK10-NEXT:    [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4
14788 // CHECK10-NEXT:    store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8
14789 // CHECK10-NEXT:    [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
14790 // CHECK10-NEXT:    [[TMP4:%.*]] = zext i32 [[TMP3]] to i64
14791 // CHECK10-NEXT:    [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]]
14792 // CHECK10-NEXT:    [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8
14793 // CHECK10-NEXT:    store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8
14794 // CHECK10-NEXT:    [[TMP6:%.*]] = load i32, i32* [[A]], align 4
14795 // CHECK10-NEXT:    store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_]], align 4
14796 // CHECK10-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
14797 // CHECK10-NEXT:    store i32 [[TMP7]], i32* [[DOTCAPTURE_EXPR_2]], align 4
14798 // CHECK10-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
14799 // CHECK10-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
14800 // CHECK10-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
14801 // CHECK10-NEXT:    store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
14802 // CHECK10-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
14803 // CHECK10:       omp.inner.for.cond:
14804 // CHECK10-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
14805 // CHECK10-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !2
14806 // CHECK10-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
14807 // CHECK10-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
14808 // CHECK10:       omp.inner.for.body:
14809 // CHECK10-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
14810 // CHECK10-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
14811 // CHECK10-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
14812 // CHECK10-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !2
14813 // CHECK10-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
14814 // CHECK10:       omp.body.continue:
14815 // CHECK10-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
14816 // CHECK10:       omp.inner.for.inc:
14817 // CHECK10-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
14818 // CHECK10-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1
14819 // CHECK10-NEXT:    store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
14820 // CHECK10-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]
14821 // CHECK10:       omp.inner.for.end:
14822 // CHECK10-NEXT:    store i32 10, i32* [[I]], align 4
14823 // CHECK10-NEXT:    store i32 0, i32* [[DOTOMP_LB5]], align 4
14824 // CHECK10-NEXT:    store i32 9, i32* [[DOTOMP_UB6]], align 4
14825 // CHECK10-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB5]], align 4
14826 // CHECK10-NEXT:    store i32 [[TMP13]], i32* [[DOTOMP_IV7]], align 4
14827 // CHECK10-NEXT:    [[TMP14:%.*]] = load i32, i32* [[A]], align 4
14828 // CHECK10-NEXT:    store i32 [[TMP14]], i32* [[DOTLINEAR_START]], align 4
14829 // CHECK10-NEXT:    br label [[OMP_INNER_FOR_COND10:%.*]]
14830 // CHECK10:       omp.inner.for.cond10:
14831 // CHECK10-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV7]], align 4
14832 // CHECK10-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB6]], align 4
14833 // CHECK10-NEXT:    [[CMP11:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]]
14834 // CHECK10-NEXT:    br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY12:%.*]], label [[OMP_INNER_FOR_END19:%.*]]
14835 // CHECK10:       omp.inner.for.body12:
14836 // CHECK10-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV7]], align 4
14837 // CHECK10-NEXT:    [[MUL13:%.*]] = mul nsw i32 [[TMP17]], 1
14838 // CHECK10-NEXT:    [[ADD14:%.*]] = add nsw i32 0, [[MUL13]]
14839 // CHECK10-NEXT:    store i32 [[ADD14]], i32* [[A8]], align 4
14840 // CHECK10-NEXT:    [[TMP18:%.*]] = load i32, i32* [[A8]], align 4
14841 // CHECK10-NEXT:    [[ADD15:%.*]] = add nsw i32 [[TMP18]], 1
14842 // CHECK10-NEXT:    store i32 [[ADD15]], i32* [[A8]], align 4
14843 // CHECK10-NEXT:    br label [[OMP_BODY_CONTINUE16:%.*]]
14844 // CHECK10:       omp.body.continue16:
14845 // CHECK10-NEXT:    br label [[OMP_INNER_FOR_INC17:%.*]]
14846 // CHECK10:       omp.inner.for.inc17:
14847 // CHECK10-NEXT:    [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV7]], align 4
14848 // CHECK10-NEXT:    [[ADD18:%.*]] = add nsw i32 [[TMP19]], 1
14849 // CHECK10-NEXT:    store i32 [[ADD18]], i32* [[DOTOMP_IV7]], align 4
14850 // CHECK10-NEXT:    br label [[OMP_INNER_FOR_COND10]], !llvm.loop [[LOOP7:![0-9]+]]
14851 // CHECK10:       omp.inner.for.end19:
14852 // CHECK10-NEXT:    store i32 10, i32* [[A]], align 4
14853 // CHECK10-NEXT:    store i32 0, i32* [[DOTOMP_LB21]], align 4
14854 // CHECK10-NEXT:    store i32 9, i32* [[DOTOMP_UB22]], align 4
14855 // CHECK10-NEXT:    [[TMP20:%.*]] = load i32, i32* [[DOTOMP_LB21]], align 4
14856 // CHECK10-NEXT:    store i32 [[TMP20]], i32* [[DOTOMP_IV23]], align 4
14857 // CHECK10-NEXT:    br label [[OMP_INNER_FOR_COND25:%.*]]
14858 // CHECK10:       omp.inner.for.cond25:
14859 // CHECK10-NEXT:    [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV23]], align 4, !llvm.access.group !9
14860 // CHECK10-NEXT:    [[TMP22:%.*]] = load i32, i32* [[DOTOMP_UB22]], align 4, !llvm.access.group !9
14861 // CHECK10-NEXT:    [[CMP26:%.*]] = icmp sle i32 [[TMP21]], [[TMP22]]
14862 // CHECK10-NEXT:    br i1 [[CMP26]], label [[OMP_INNER_FOR_BODY27:%.*]], label [[OMP_INNER_FOR_END35:%.*]]
14863 // CHECK10:       omp.inner.for.body27:
14864 // CHECK10-NEXT:    [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV23]], align 4, !llvm.access.group !9
14865 // CHECK10-NEXT:    [[MUL28:%.*]] = mul nsw i32 [[TMP23]], 1
14866 // CHECK10-NEXT:    [[ADD29:%.*]] = add nsw i32 0, [[MUL28]]
14867 // CHECK10-NEXT:    store i32 [[ADD29]], i32* [[I24]], align 4, !llvm.access.group !9
14868 // CHECK10-NEXT:    [[TMP24:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !9
14869 // CHECK10-NEXT:    [[CONV:%.*]] = sext i16 [[TMP24]] to i32
14870 // CHECK10-NEXT:    [[ADD30:%.*]] = add nsw i32 [[CONV]], 1
14871 // CHECK10-NEXT:    [[CONV31:%.*]] = trunc i32 [[ADD30]] to i16
14872 // CHECK10-NEXT:    store i16 [[CONV31]], i16* [[AA]], align 2, !llvm.access.group !9
14873 // CHECK10-NEXT:    br label [[OMP_BODY_CONTINUE32:%.*]]
14874 // CHECK10:       omp.body.continue32:
14875 // CHECK10-NEXT:    br label [[OMP_INNER_FOR_INC33:%.*]]
14876 // CHECK10:       omp.inner.for.inc33:
14877 // CHECK10-NEXT:    [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IV23]], align 4, !llvm.access.group !9
14878 // CHECK10-NEXT:    [[ADD34:%.*]] = add nsw i32 [[TMP25]], 1
14879 // CHECK10-NEXT:    store i32 [[ADD34]], i32* [[DOTOMP_IV23]], align 4, !llvm.access.group !9
14880 // CHECK10-NEXT:    br label [[OMP_INNER_FOR_COND25]], !llvm.loop [[LOOP10:![0-9]+]]
14881 // CHECK10:       omp.inner.for.end35:
14882 // CHECK10-NEXT:    store i32 10, i32* [[I24]], align 4
14883 // CHECK10-NEXT:    store i32 0, i32* [[DOTOMP_LB37]], align 4
14884 // CHECK10-NEXT:    store i32 9, i32* [[DOTOMP_UB38]], align 4
14885 // CHECK10-NEXT:    [[TMP26:%.*]] = load i32, i32* [[DOTOMP_LB37]], align 4
14886 // CHECK10-NEXT:    store i32 [[TMP26]], i32* [[DOTOMP_IV39]], align 4
14887 // CHECK10-NEXT:    br label [[OMP_INNER_FOR_COND41:%.*]]
14888 // CHECK10:       omp.inner.for.cond41:
14889 // CHECK10-NEXT:    [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV39]], align 4, !llvm.access.group !12
14890 // CHECK10-NEXT:    [[TMP28:%.*]] = load i32, i32* [[DOTOMP_UB38]], align 4, !llvm.access.group !12
14891 // CHECK10-NEXT:    [[CMP42:%.*]] = icmp sle i32 [[TMP27]], [[TMP28]]
14892 // CHECK10-NEXT:    br i1 [[CMP42]], label [[OMP_INNER_FOR_BODY43:%.*]], label [[OMP_INNER_FOR_END53:%.*]]
14893 // CHECK10:       omp.inner.for.body43:
14894 // CHECK10-NEXT:    [[TMP29:%.*]] = load i32, i32* [[DOTOMP_IV39]], align 4, !llvm.access.group !12
14895 // CHECK10-NEXT:    [[MUL44:%.*]] = mul nsw i32 [[TMP29]], 1
14896 // CHECK10-NEXT:    [[ADD45:%.*]] = add nsw i32 0, [[MUL44]]
14897 // CHECK10-NEXT:    store i32 [[ADD45]], i32* [[I40]], align 4, !llvm.access.group !12
14898 // CHECK10-NEXT:    [[TMP30:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !12
14899 // CHECK10-NEXT:    [[ADD46:%.*]] = add nsw i32 [[TMP30]], 1
14900 // CHECK10-NEXT:    store i32 [[ADD46]], i32* [[A]], align 4, !llvm.access.group !12
14901 // CHECK10-NEXT:    [[TMP31:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !12
14902 // CHECK10-NEXT:    [[CONV47:%.*]] = sext i16 [[TMP31]] to i32
14903 // CHECK10-NEXT:    [[ADD48:%.*]] = add nsw i32 [[CONV47]], 1
14904 // CHECK10-NEXT:    [[CONV49:%.*]] = trunc i32 [[ADD48]] to i16
14905 // CHECK10-NEXT:    store i16 [[CONV49]], i16* [[AA]], align 2, !llvm.access.group !12
14906 // CHECK10-NEXT:    br label [[OMP_BODY_CONTINUE50:%.*]]
14907 // CHECK10:       omp.body.continue50:
14908 // CHECK10-NEXT:    br label [[OMP_INNER_FOR_INC51:%.*]]
14909 // CHECK10:       omp.inner.for.inc51:
14910 // CHECK10-NEXT:    [[TMP32:%.*]] = load i32, i32* [[DOTOMP_IV39]], align 4, !llvm.access.group !12
14911 // CHECK10-NEXT:    [[ADD52:%.*]] = add nsw i32 [[TMP32]], 1
14912 // CHECK10-NEXT:    store i32 [[ADD52]], i32* [[DOTOMP_IV39]], align 4, !llvm.access.group !12
14913 // CHECK10-NEXT:    br label [[OMP_INNER_FOR_COND41]], !llvm.loop [[LOOP13:![0-9]+]]
14914 // CHECK10:       omp.inner.for.end53:
14915 // CHECK10-NEXT:    store i32 10, i32* [[I40]], align 4
14916 // CHECK10-NEXT:    store i32 0, i32* [[DOTOMP_LB55]], align 4
14917 // CHECK10-NEXT:    store i32 9, i32* [[DOTOMP_UB56]], align 4
14918 // CHECK10-NEXT:    [[TMP33:%.*]] = load i32, i32* [[DOTOMP_LB55]], align 4
14919 // CHECK10-NEXT:    store i32 [[TMP33]], i32* [[DOTOMP_IV57]], align 4
14920 // CHECK10-NEXT:    [[ARRAYDECAY:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 0
14921 // CHECK10-NEXT:    call void @llvm.assume(i1 true) [ "align"(float* [[ARRAYDECAY]], i64 16) ]
14922 // CHECK10-NEXT:    br label [[OMP_INNER_FOR_COND59:%.*]]
14923 // CHECK10:       omp.inner.for.cond59:
14924 // CHECK10-NEXT:    [[TMP34:%.*]] = load i32, i32* [[DOTOMP_IV57]], align 4, !llvm.access.group !15
14925 // CHECK10-NEXT:    [[TMP35:%.*]] = load i32, i32* [[DOTOMP_UB56]], align 4, !llvm.access.group !15
14926 // CHECK10-NEXT:    [[CMP60:%.*]] = icmp sle i32 [[TMP34]], [[TMP35]]
14927 // CHECK10-NEXT:    br i1 [[CMP60]], label [[OMP_INNER_FOR_BODY61:%.*]], label [[OMP_INNER_FOR_END85:%.*]]
14928 // CHECK10:       omp.inner.for.body61:
14929 // CHECK10-NEXT:    [[TMP36:%.*]] = load i32, i32* [[DOTOMP_IV57]], align 4, !llvm.access.group !15
14930 // CHECK10-NEXT:    [[MUL62:%.*]] = mul nsw i32 [[TMP36]], 1
14931 // CHECK10-NEXT:    [[ADD63:%.*]] = add nsw i32 0, [[MUL62]]
14932 // CHECK10-NEXT:    store i32 [[ADD63]], i32* [[I58]], align 4, !llvm.access.group !15
14933 // CHECK10-NEXT:    [[TMP37:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !15
14934 // CHECK10-NEXT:    [[ADD64:%.*]] = add nsw i32 [[TMP37]], 1
14935 // CHECK10-NEXT:    store i32 [[ADD64]], i32* [[A]], align 4, !llvm.access.group !15
14936 // CHECK10-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2
14937 // CHECK10-NEXT:    [[TMP38:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !15
14938 // CHECK10-NEXT:    [[CONV65:%.*]] = fpext float [[TMP38]] to double
14939 // CHECK10-NEXT:    [[ADD66:%.*]] = fadd double [[CONV65]], 1.000000e+00
14940 // CHECK10-NEXT:    [[CONV67:%.*]] = fptrunc double [[ADD66]] to float
14941 // CHECK10-NEXT:    store float [[CONV67]], float* [[ARRAYIDX]], align 4, !llvm.access.group !15
14942 // CHECK10-NEXT:    [[ARRAYIDX68:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3
14943 // CHECK10-NEXT:    [[TMP39:%.*]] = load float, float* [[ARRAYIDX68]], align 4, !llvm.access.group !15
14944 // CHECK10-NEXT:    [[CONV69:%.*]] = fpext float [[TMP39]] to double
14945 // CHECK10-NEXT:    [[ADD70:%.*]] = fadd double [[CONV69]], 1.000000e+00
14946 // CHECK10-NEXT:    [[CONV71:%.*]] = fptrunc double [[ADD70]] to float
14947 // CHECK10-NEXT:    store float [[CONV71]], float* [[ARRAYIDX68]], align 4, !llvm.access.group !15
14948 // CHECK10-NEXT:    [[ARRAYIDX72:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1
14949 // CHECK10-NEXT:    [[ARRAYIDX73:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX72]], i64 0, i64 2
14950 // CHECK10-NEXT:    [[TMP40:%.*]] = load double, double* [[ARRAYIDX73]], align 8, !llvm.access.group !15
14951 // CHECK10-NEXT:    [[ADD74:%.*]] = fadd double [[TMP40]], 1.000000e+00
14952 // CHECK10-NEXT:    store double [[ADD74]], double* [[ARRAYIDX73]], align 8, !llvm.access.group !15
14953 // CHECK10-NEXT:    [[TMP41:%.*]] = mul nsw i64 1, [[TMP4]]
14954 // CHECK10-NEXT:    [[ARRAYIDX75:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP41]]
14955 // CHECK10-NEXT:    [[ARRAYIDX76:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX75]], i64 3
14956 // CHECK10-NEXT:    [[TMP42:%.*]] = load double, double* [[ARRAYIDX76]], align 8, !llvm.access.group !15
14957 // CHECK10-NEXT:    [[ADD77:%.*]] = fadd double [[TMP42]], 1.000000e+00
14958 // CHECK10-NEXT:    store double [[ADD77]], double* [[ARRAYIDX76]], align 8, !llvm.access.group !15
14959 // CHECK10-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0
14960 // CHECK10-NEXT:    [[TMP43:%.*]] = load i64, i64* [[X]], align 8, !llvm.access.group !15
14961 // CHECK10-NEXT:    [[ADD78:%.*]] = add nsw i64 [[TMP43]], 1
14962 // CHECK10-NEXT:    store i64 [[ADD78]], i64* [[X]], align 8, !llvm.access.group !15
14963 // CHECK10-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1
14964 // CHECK10-NEXT:    [[TMP44:%.*]] = load i8, i8* [[Y]], align 8, !llvm.access.group !15
14965 // CHECK10-NEXT:    [[CONV79:%.*]] = sext i8 [[TMP44]] to i32
14966 // CHECK10-NEXT:    [[ADD80:%.*]] = add nsw i32 [[CONV79]], 1
14967 // CHECK10-NEXT:    [[CONV81:%.*]] = trunc i32 [[ADD80]] to i8
14968 // CHECK10-NEXT:    store i8 [[CONV81]], i8* [[Y]], align 8, !llvm.access.group !15
14969 // CHECK10-NEXT:    br label [[OMP_BODY_CONTINUE82:%.*]]
14970 // CHECK10:       omp.body.continue82:
14971 // CHECK10-NEXT:    br label [[OMP_INNER_FOR_INC83:%.*]]
14972 // CHECK10:       omp.inner.for.inc83:
14973 // CHECK10-NEXT:    [[TMP45:%.*]] = load i32, i32* [[DOTOMP_IV57]], align 4, !llvm.access.group !15
14974 // CHECK10-NEXT:    [[ADD84:%.*]] = add nsw i32 [[TMP45]], 1
14975 // CHECK10-NEXT:    store i32 [[ADD84]], i32* [[DOTOMP_IV57]], align 4, !llvm.access.group !15
14976 // CHECK10-NEXT:    br label [[OMP_INNER_FOR_COND59]], !llvm.loop [[LOOP16:![0-9]+]]
14977 // CHECK10:       omp.inner.for.end85:
14978 // CHECK10-NEXT:    store i32 10, i32* [[I58]], align 4
14979 // CHECK10-NEXT:    [[TMP46:%.*]] = load i32, i32* [[A]], align 4
14980 // CHECK10-NEXT:    [[TMP47:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
14981 // CHECK10-NEXT:    call void @llvm.stackrestore(i8* [[TMP47]])
14982 // CHECK10-NEXT:    ret i32 [[TMP46]]
14983 //
14984 //
14985 // CHECK10-LABEL: define {{[^@]+}}@_Z3bari
14986 // CHECK10-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {
14987 // CHECK10-NEXT:  entry:
14988 // CHECK10-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
14989 // CHECK10-NEXT:    [[A:%.*]] = alloca i32, align 4
14990 // CHECK10-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8
14991 // CHECK10-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
14992 // CHECK10-NEXT:    store i32 0, i32* [[A]], align 4
14993 // CHECK10-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
14994 // CHECK10-NEXT:    [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]])
14995 // CHECK10-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
14996 // CHECK10-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
14997 // CHECK10-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
14998 // CHECK10-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
14999 // CHECK10-NEXT:    [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP2]])
15000 // CHECK10-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
15001 // CHECK10-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
15002 // CHECK10-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
15003 // CHECK10-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
15004 // CHECK10-NEXT:    [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]])
15005 // CHECK10-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
15006 // CHECK10-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
15007 // CHECK10-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
15008 // CHECK10-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
15009 // CHECK10-NEXT:    [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]])
15010 // CHECK10-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
15011 // CHECK10-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
15012 // CHECK10-NEXT:    store i32 [[ADD6]], i32* [[A]], align 4
15013 // CHECK10-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
15014 // CHECK10-NEXT:    ret i32 [[TMP8]]
15015 //
15016 //
15017 // CHECK10-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
15018 // CHECK10-SAME: (%struct.S1* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 {
15019 // CHECK10-NEXT:  entry:
15020 // CHECK10-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
15021 // CHECK10-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
15022 // CHECK10-NEXT:    [[B:%.*]] = alloca i32, align 4
15023 // CHECK10-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 8
15024 // CHECK10-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
15025 // CHECK10-NEXT:    [[TMP:%.*]] = alloca i32, align 4
15026 // CHECK10-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
15027 // CHECK10-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
15028 // CHECK10-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
15029 // CHECK10-NEXT:    [[I:%.*]] = alloca i32, align 4
15030 // CHECK10-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
15031 // CHECK10-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
15032 // CHECK10-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
15033 // CHECK10-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
15034 // CHECK10-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
15035 // CHECK10-NEXT:    store i32 [[ADD]], i32* [[B]], align 4
15036 // CHECK10-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
15037 // CHECK10-NEXT:    [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
15038 // CHECK10-NEXT:    [[TMP3:%.*]] = call i8* @llvm.stacksave()
15039 // CHECK10-NEXT:    store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8
15040 // CHECK10-NEXT:    [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]
15041 // CHECK10-NEXT:    [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2
15042 // CHECK10-NEXT:    store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8
15043 // CHECK10-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
15044 // CHECK10-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
15045 // CHECK10-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
15046 // CHECK10-NEXT:    store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
15047 // CHECK10-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
15048 // CHECK10:       omp.inner.for.cond:
15049 // CHECK10-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
15050 // CHECK10-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !18
15051 // CHECK10-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
15052 // CHECK10-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
15053 // CHECK10:       omp.inner.for.body:
15054 // CHECK10-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
15055 // CHECK10-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
15056 // CHECK10-NEXT:    [[ADD2:%.*]] = add nsw i32 0, [[MUL]]
15057 // CHECK10-NEXT:    store i32 [[ADD2]], i32* [[I]], align 4, !llvm.access.group !18
15058 // CHECK10-NEXT:    [[TMP9:%.*]] = load i32, i32* [[B]], align 4, !llvm.access.group !18
15059 // CHECK10-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP9]] to double
15060 // CHECK10-NEXT:    [[ADD3:%.*]] = fadd double [[CONV]], 1.500000e+00
15061 // CHECK10-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
15062 // CHECK10-NEXT:    store double [[ADD3]], double* [[A]], align 8, !llvm.access.group !18
15063 // CHECK10-NEXT:    [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
15064 // CHECK10-NEXT:    [[TMP10:%.*]] = load double, double* [[A4]], align 8, !llvm.access.group !18
15065 // CHECK10-NEXT:    [[INC:%.*]] = fadd double [[TMP10]], 1.000000e+00
15066 // CHECK10-NEXT:    store double [[INC]], double* [[A4]], align 8, !llvm.access.group !18
15067 // CHECK10-NEXT:    [[CONV5:%.*]] = fptosi double [[INC]] to i16
15068 // CHECK10-NEXT:    [[TMP11:%.*]] = mul nsw i64 1, [[TMP2]]
15069 // CHECK10-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP11]]
15070 // CHECK10-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
15071 // CHECK10-NEXT:    store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2, !llvm.access.group !18
15072 // CHECK10-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
15073 // CHECK10:       omp.body.continue:
15074 // CHECK10-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
15075 // CHECK10:       omp.inner.for.inc:
15076 // CHECK10-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
15077 // CHECK10-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP12]], 1
15078 // CHECK10-NEXT:    store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
15079 // CHECK10-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]
15080 // CHECK10:       omp.inner.for.end:
15081 // CHECK10-NEXT:    store i32 10, i32* [[I]], align 4
15082 // CHECK10-NEXT:    [[TMP13:%.*]] = mul nsw i64 1, [[TMP2]]
15083 // CHECK10-NEXT:    [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP13]]
15084 // CHECK10-NEXT:    [[ARRAYIDX9:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX8]], i64 1
15085 // CHECK10-NEXT:    [[TMP14:%.*]] = load i16, i16* [[ARRAYIDX9]], align 2
15086 // CHECK10-NEXT:    [[CONV10:%.*]] = sext i16 [[TMP14]] to i32
15087 // CHECK10-NEXT:    [[TMP15:%.*]] = load i32, i32* [[B]], align 4
15088 // CHECK10-NEXT:    [[ADD11:%.*]] = add nsw i32 [[CONV10]], [[TMP15]]
15089 // CHECK10-NEXT:    [[TMP16:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
15090 // CHECK10-NEXT:    call void @llvm.stackrestore(i8* [[TMP16]])
15091 // CHECK10-NEXT:    ret i32 [[ADD11]]
15092 //
15093 //
15094 // CHECK10-LABEL: define {{[^@]+}}@_ZL7fstatici
15095 // CHECK10-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {
15096 // CHECK10-NEXT:  entry:
15097 // CHECK10-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
15098 // CHECK10-NEXT:    [[A:%.*]] = alloca i32, align 4
15099 // CHECK10-NEXT:    [[AA:%.*]] = alloca i16, align 2
15100 // CHECK10-NEXT:    [[AAA:%.*]] = alloca i8, align 1
15101 // CHECK10-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
15102 // CHECK10-NEXT:    [[TMP:%.*]] = alloca i32, align 4
15103 // CHECK10-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
15104 // CHECK10-NEXT:    [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
15105 // CHECK10-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
15106 // CHECK10-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
15107 // CHECK10-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
15108 // CHECK10-NEXT:    [[I:%.*]] = alloca i32, align 4
15109 // CHECK10-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
15110 // CHECK10-NEXT:    [[I5:%.*]] = alloca i32, align 4
15111 // CHECK10-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
15112 // CHECK10-NEXT:    store i32 0, i32* [[A]], align 4
15113 // CHECK10-NEXT:    store i16 0, i16* [[AA]], align 2
15114 // CHECK10-NEXT:    store i8 0, i8* [[AAA]], align 1
15115 // CHECK10-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
15116 // CHECK10-NEXT:    store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4
15117 // CHECK10-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
15118 // CHECK10-NEXT:    store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_1]], align 4
15119 // CHECK10-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
15120 // CHECK10-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
15121 // CHECK10-NEXT:    [[SUB:%.*]] = sub i32 [[TMP2]], [[TMP3]]
15122 // CHECK10-NEXT:    [[SUB3:%.*]] = sub i32 [[SUB]], 1
15123 // CHECK10-NEXT:    [[ADD:%.*]] = add i32 [[SUB3]], 1
15124 // CHECK10-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], 1
15125 // CHECK10-NEXT:    [[SUB4:%.*]] = sub i32 [[DIV]], 1
15126 // CHECK10-NEXT:    store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_2]], align 4
15127 // CHECK10-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
15128 // CHECK10-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
15129 // CHECK10-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_UB]], align 4
15130 // CHECK10-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
15131 // CHECK10-NEXT:    store i32 [[TMP5]], i32* [[I]], align 4
15132 // CHECK10-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
15133 // CHECK10-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
15134 // CHECK10-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]]
15135 // CHECK10-NEXT:    br i1 [[CMP]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END:%.*]]
15136 // CHECK10:       simd.if.then:
15137 // CHECK10-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
15138 // CHECK10-NEXT:    store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
15139 // CHECK10-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
15140 // CHECK10:       omp.inner.for.cond:
15141 // CHECK10-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
15142 // CHECK10-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !21
15143 // CHECK10-NEXT:    [[ADD6:%.*]] = add i32 [[TMP10]], 1
15144 // CHECK10-NEXT:    [[CMP7:%.*]] = icmp ult i32 [[TMP9]], [[ADD6]]
15145 // CHECK10-NEXT:    br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
15146 // CHECK10:       omp.inner.for.body:
15147 // CHECK10-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group !21
15148 // CHECK10-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
15149 // CHECK10-NEXT:    [[MUL:%.*]] = mul i32 [[TMP12]], 1
15150 // CHECK10-NEXT:    [[ADD8:%.*]] = add i32 [[TMP11]], [[MUL]]
15151 // CHECK10-NEXT:    store i32 [[ADD8]], i32* [[I5]], align 4, !llvm.access.group !21
15152 // CHECK10-NEXT:    [[TMP13:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !21
15153 // CHECK10-NEXT:    [[ADD9:%.*]] = add nsw i32 [[TMP13]], 1
15154 // CHECK10-NEXT:    store i32 [[ADD9]], i32* [[A]], align 4, !llvm.access.group !21
15155 // CHECK10-NEXT:    [[TMP14:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !21
15156 // CHECK10-NEXT:    [[CONV:%.*]] = sext i16 [[TMP14]] to i32
15157 // CHECK10-NEXT:    [[ADD10:%.*]] = add nsw i32 [[CONV]], 1
15158 // CHECK10-NEXT:    [[CONV11:%.*]] = trunc i32 [[ADD10]] to i16
15159 // CHECK10-NEXT:    store i16 [[CONV11]], i16* [[AA]], align 2, !llvm.access.group !21
15160 // CHECK10-NEXT:    [[TMP15:%.*]] = load i8, i8* [[AAA]], align 1, !llvm.access.group !21
15161 // CHECK10-NEXT:    [[CONV12:%.*]] = sext i8 [[TMP15]] to i32
15162 // CHECK10-NEXT:    [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1
15163 // CHECK10-NEXT:    [[CONV14:%.*]] = trunc i32 [[ADD13]] to i8
15164 // CHECK10-NEXT:    store i8 [[CONV14]], i8* [[AAA]], align 1, !llvm.access.group !21
15165 // CHECK10-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2
15166 // CHECK10-NEXT:    [[TMP16:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !21
15167 // CHECK10-NEXT:    [[ADD15:%.*]] = add nsw i32 [[TMP16]], 1
15168 // CHECK10-NEXT:    store i32 [[ADD15]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !21
15169 // CHECK10-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
15170 // CHECK10:       omp.body.continue:
15171 // CHECK10-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
15172 // CHECK10:       omp.inner.for.inc:
15173 // CHECK10-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
15174 // CHECK10-NEXT:    [[ADD16:%.*]] = add i32 [[TMP17]], 1
15175 // CHECK10-NEXT:    store i32 [[ADD16]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
15176 // CHECK10-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]]
15177 // CHECK10:       omp.inner.for.end:
15178 // CHECK10-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
15179 // CHECK10-NEXT:    [[TMP19:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
15180 // CHECK10-NEXT:    [[TMP20:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
15181 // CHECK10-NEXT:    [[SUB17:%.*]] = sub i32 [[TMP19]], [[TMP20]]
15182 // CHECK10-NEXT:    [[SUB18:%.*]] = sub i32 [[SUB17]], 1
15183 // CHECK10-NEXT:    [[ADD19:%.*]] = add i32 [[SUB18]], 1
15184 // CHECK10-NEXT:    [[DIV20:%.*]] = udiv i32 [[ADD19]], 1
15185 // CHECK10-NEXT:    [[MUL21:%.*]] = mul i32 [[DIV20]], 1
15186 // CHECK10-NEXT:    [[ADD22:%.*]] = add i32 [[TMP18]], [[MUL21]]
15187 // CHECK10-NEXT:    store i32 [[ADD22]], i32* [[I5]], align 4
15188 // CHECK10-NEXT:    br label [[SIMD_IF_END]]
15189 // CHECK10:       simd.if.end:
15190 // CHECK10-NEXT:    [[TMP21:%.*]] = load i32, i32* [[A]], align 4
15191 // CHECK10-NEXT:    ret i32 [[TMP21]]
15192 //
15193 //
15194 // CHECK10-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
15195 // CHECK10-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat {
15196 // CHECK10-NEXT:  entry:
15197 // CHECK10-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
15198 // CHECK10-NEXT:    [[A:%.*]] = alloca i32, align 4
15199 // CHECK10-NEXT:    [[AA:%.*]] = alloca i16, align 2
15200 // CHECK10-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
15201 // CHECK10-NEXT:    [[TMP:%.*]] = alloca i32, align 4
15202 // CHECK10-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
15203 // CHECK10-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
15204 // CHECK10-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
15205 // CHECK10-NEXT:    [[I:%.*]] = alloca i32, align 4
15206 // CHECK10-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
15207 // CHECK10-NEXT:    store i32 0, i32* [[A]], align 4
15208 // CHECK10-NEXT:    store i16 0, i16* [[AA]], align 2
15209 // CHECK10-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
15210 // CHECK10-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
15211 // CHECK10-NEXT:    [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
15212 // CHECK10-NEXT:    store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4
15213 // CHECK10-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
15214 // CHECK10:       omp.inner.for.cond:
15215 // CHECK10-NEXT:    [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
15216 // CHECK10-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !24
15217 // CHECK10-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
15218 // CHECK10-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
15219 // CHECK10:       omp.inner.for.body:
15220 // CHECK10-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
15221 // CHECK10-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1
15222 // CHECK10-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
15223 // CHECK10-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !24
15224 // CHECK10-NEXT:    [[TMP4:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !24
15225 // CHECK10-NEXT:    [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1
15226 // CHECK10-NEXT:    store i32 [[ADD1]], i32* [[A]], align 4, !llvm.access.group !24
15227 // CHECK10-NEXT:    [[TMP5:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !24
15228 // CHECK10-NEXT:    [[CONV:%.*]] = sext i16 [[TMP5]] to i32
15229 // CHECK10-NEXT:    [[ADD2:%.*]] = add nsw i32 [[CONV]], 1
15230 // CHECK10-NEXT:    [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
15231 // CHECK10-NEXT:    store i16 [[CONV3]], i16* [[AA]], align 2, !llvm.access.group !24
15232 // CHECK10-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2
15233 // CHECK10-NEXT:    [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !24
15234 // CHECK10-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP6]], 1
15235 // CHECK10-NEXT:    store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !24
15236 // CHECK10-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
15237 // CHECK10:       omp.body.continue:
15238 // CHECK10-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
15239 // CHECK10:       omp.inner.for.inc:
15240 // CHECK10-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
15241 // CHECK10-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP7]], 1
15242 // CHECK10-NEXT:    store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
15243 // CHECK10-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]]
15244 // CHECK10:       omp.inner.for.end:
15245 // CHECK10-NEXT:    store i32 10, i32* [[I]], align 4
15246 // CHECK10-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
15247 // CHECK10-NEXT:    ret i32 [[TMP8]]
15248 //
15249 //
15250 // CHECK11-LABEL: define {{[^@]+}}@_Z3fooi
15251 // CHECK11-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0:[0-9]+]] {
15252 // CHECK11-NEXT:  entry:
15253 // CHECK11-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
15254 // CHECK11-NEXT:    [[A:%.*]] = alloca i32, align 4
15255 // CHECK11-NEXT:    [[AA:%.*]] = alloca i16, align 2
15256 // CHECK11-NEXT:    [[B:%.*]] = alloca [10 x float], align 4
15257 // CHECK11-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 4
15258 // CHECK11-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 4
15259 // CHECK11-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 8
15260 // CHECK11-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i32, align 4
15261 // CHECK11-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4
15262 // CHECK11-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
15263 // CHECK11-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
15264 // CHECK11-NEXT:    [[TMP:%.*]] = alloca i32, align 4
15265 // CHECK11-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
15266 // CHECK11-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
15267 // CHECK11-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
15268 // CHECK11-NEXT:    [[I:%.*]] = alloca i32, align 4
15269 // CHECK11-NEXT:    [[_TMP4:%.*]] = alloca i32, align 4
15270 // CHECK11-NEXT:    [[DOTOMP_LB5:%.*]] = alloca i32, align 4
15271 // CHECK11-NEXT:    [[DOTOMP_UB6:%.*]] = alloca i32, align 4
15272 // CHECK11-NEXT:    [[DOTOMP_IV7:%.*]] = alloca i32, align 4
15273 // CHECK11-NEXT:    [[DOTLINEAR_START:%.*]] = alloca i32, align 4
15274 // CHECK11-NEXT:    [[A8:%.*]] = alloca i32, align 4
15275 // CHECK11-NEXT:    [[A9:%.*]] = alloca i32, align 4
15276 // CHECK11-NEXT:    [[_TMP20:%.*]] = alloca i32, align 4
15277 // CHECK11-NEXT:    [[DOTOMP_LB21:%.*]] = alloca i32, align 4
15278 // CHECK11-NEXT:    [[DOTOMP_UB22:%.*]] = alloca i32, align 4
15279 // CHECK11-NEXT:    [[DOTOMP_IV23:%.*]] = alloca i32, align 4
15280 // CHECK11-NEXT:    [[I24:%.*]] = alloca i32, align 4
15281 // CHECK11-NEXT:    [[_TMP36:%.*]] = alloca i32, align 4
15282 // CHECK11-NEXT:    [[DOTOMP_LB37:%.*]] = alloca i32, align 4
15283 // CHECK11-NEXT:    [[DOTOMP_UB38:%.*]] = alloca i32, align 4
15284 // CHECK11-NEXT:    [[DOTOMP_IV39:%.*]] = alloca i32, align 4
15285 // CHECK11-NEXT:    [[I40:%.*]] = alloca i32, align 4
15286 // CHECK11-NEXT:    [[_TMP54:%.*]] = alloca i32, align 4
15287 // CHECK11-NEXT:    [[DOTOMP_LB55:%.*]] = alloca i32, align 4
15288 // CHECK11-NEXT:    [[DOTOMP_UB56:%.*]] = alloca i32, align 4
15289 // CHECK11-NEXT:    [[DOTOMP_IV57:%.*]] = alloca i32, align 4
15290 // CHECK11-NEXT:    [[I58:%.*]] = alloca i32, align 4
15291 // CHECK11-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
15292 // CHECK11-NEXT:    store i32 0, i32* [[A]], align 4
15293 // CHECK11-NEXT:    store i16 0, i16* [[AA]], align 2
15294 // CHECK11-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
15295 // CHECK11-NEXT:    [[TMP1:%.*]] = call i8* @llvm.stacksave()
15296 // CHECK11-NEXT:    store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4
15297 // CHECK11-NEXT:    [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4
15298 // CHECK11-NEXT:    store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4
15299 // CHECK11-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
15300 // CHECK11-NEXT:    [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]]
15301 // CHECK11-NEXT:    [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8
15302 // CHECK11-NEXT:    store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4
15303 // CHECK11-NEXT:    [[TMP4:%.*]] = load i32, i32* [[A]], align 4
15304 // CHECK11-NEXT:    store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4
15305 // CHECK11-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
15306 // CHECK11-NEXT:    store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_2]], align 4
15307 // CHECK11-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
15308 // CHECK11-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
15309 // CHECK11-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
15310 // CHECK11-NEXT:    store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
15311 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
15312 // CHECK11:       omp.inner.for.cond:
15313 // CHECK11-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
15314 // CHECK11-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !3
15315 // CHECK11-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
15316 // CHECK11-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
15317 // CHECK11:       omp.inner.for.body:
15318 // CHECK11-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
15319 // CHECK11-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
15320 // CHECK11-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
15321 // CHECK11-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !3
15322 // CHECK11-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
15323 // CHECK11:       omp.body.continue:
15324 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
15325 // CHECK11:       omp.inner.for.inc:
15326 // CHECK11-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
15327 // CHECK11-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
15328 // CHECK11-NEXT:    store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
15329 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]
15330 // CHECK11:       omp.inner.for.end:
15331 // CHECK11-NEXT:    store i32 10, i32* [[I]], align 4
15332 // CHECK11-NEXT:    store i32 0, i32* [[DOTOMP_LB5]], align 4
15333 // CHECK11-NEXT:    store i32 9, i32* [[DOTOMP_UB6]], align 4
15334 // CHECK11-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_LB5]], align 4
15335 // CHECK11-NEXT:    store i32 [[TMP11]], i32* [[DOTOMP_IV7]], align 4
15336 // CHECK11-NEXT:    [[TMP12:%.*]] = load i32, i32* [[A]], align 4
15337 // CHECK11-NEXT:    store i32 [[TMP12]], i32* [[DOTLINEAR_START]], align 4
15338 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_COND10:%.*]]
15339 // CHECK11:       omp.inner.for.cond10:
15340 // CHECK11-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV7]], align 4
15341 // CHECK11-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB6]], align 4
15342 // CHECK11-NEXT:    [[CMP11:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
15343 // CHECK11-NEXT:    br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY12:%.*]], label [[OMP_INNER_FOR_END19:%.*]]
15344 // CHECK11:       omp.inner.for.body12:
15345 // CHECK11-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV7]], align 4
15346 // CHECK11-NEXT:    [[MUL13:%.*]] = mul nsw i32 [[TMP15]], 1
15347 // CHECK11-NEXT:    [[ADD14:%.*]] = add nsw i32 0, [[MUL13]]
15348 // CHECK11-NEXT:    store i32 [[ADD14]], i32* [[A8]], align 4
15349 // CHECK11-NEXT:    [[TMP16:%.*]] = load i32, i32* [[A8]], align 4
15350 // CHECK11-NEXT:    [[ADD15:%.*]] = add nsw i32 [[TMP16]], 1
15351 // CHECK11-NEXT:    store i32 [[ADD15]], i32* [[A8]], align 4
15352 // CHECK11-NEXT:    br label [[OMP_BODY_CONTINUE16:%.*]]
15353 // CHECK11:       omp.body.continue16:
15354 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_INC17:%.*]]
15355 // CHECK11:       omp.inner.for.inc17:
15356 // CHECK11-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV7]], align 4
15357 // CHECK11-NEXT:    [[ADD18:%.*]] = add nsw i32 [[TMP17]], 1
15358 // CHECK11-NEXT:    store i32 [[ADD18]], i32* [[DOTOMP_IV7]], align 4
15359 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_COND10]], !llvm.loop [[LOOP8:![0-9]+]]
15360 // CHECK11:       omp.inner.for.end19:
15361 // CHECK11-NEXT:    store i32 10, i32* [[A]], align 4
15362 // CHECK11-NEXT:    store i32 0, i32* [[DOTOMP_LB21]], align 4
15363 // CHECK11-NEXT:    store i32 9, i32* [[DOTOMP_UB22]], align 4
15364 // CHECK11-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTOMP_LB21]], align 4
15365 // CHECK11-NEXT:    store i32 [[TMP18]], i32* [[DOTOMP_IV23]], align 4
15366 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_COND25:%.*]]
15367 // CHECK11:       omp.inner.for.cond25:
15368 // CHECK11-NEXT:    [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV23]], align 4, !llvm.access.group !10
15369 // CHECK11-NEXT:    [[TMP20:%.*]] = load i32, i32* [[DOTOMP_UB22]], align 4, !llvm.access.group !10
15370 // CHECK11-NEXT:    [[CMP26:%.*]] = icmp sle i32 [[TMP19]], [[TMP20]]
15371 // CHECK11-NEXT:    br i1 [[CMP26]], label [[OMP_INNER_FOR_BODY27:%.*]], label [[OMP_INNER_FOR_END35:%.*]]
15372 // CHECK11:       omp.inner.for.body27:
15373 // CHECK11-NEXT:    [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV23]], align 4, !llvm.access.group !10
15374 // CHECK11-NEXT:    [[MUL28:%.*]] = mul nsw i32 [[TMP21]], 1
15375 // CHECK11-NEXT:    [[ADD29:%.*]] = add nsw i32 0, [[MUL28]]
15376 // CHECK11-NEXT:    store i32 [[ADD29]], i32* [[I24]], align 4, !llvm.access.group !10
15377 // CHECK11-NEXT:    [[TMP22:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !10
15378 // CHECK11-NEXT:    [[CONV:%.*]] = sext i16 [[TMP22]] to i32
15379 // CHECK11-NEXT:    [[ADD30:%.*]] = add nsw i32 [[CONV]], 1
15380 // CHECK11-NEXT:    [[CONV31:%.*]] = trunc i32 [[ADD30]] to i16
15381 // CHECK11-NEXT:    store i16 [[CONV31]], i16* [[AA]], align 2, !llvm.access.group !10
15382 // CHECK11-NEXT:    br label [[OMP_BODY_CONTINUE32:%.*]]
15383 // CHECK11:       omp.body.continue32:
15384 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_INC33:%.*]]
15385 // CHECK11:       omp.inner.for.inc33:
15386 // CHECK11-NEXT:    [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV23]], align 4, !llvm.access.group !10
15387 // CHECK11-NEXT:    [[ADD34:%.*]] = add nsw i32 [[TMP23]], 1
15388 // CHECK11-NEXT:    store i32 [[ADD34]], i32* [[DOTOMP_IV23]], align 4, !llvm.access.group !10
15389 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_COND25]], !llvm.loop [[LOOP11:![0-9]+]]
15390 // CHECK11:       omp.inner.for.end35:
15391 // CHECK11-NEXT:    store i32 10, i32* [[I24]], align 4
15392 // CHECK11-NEXT:    store i32 0, i32* [[DOTOMP_LB37]], align 4
15393 // CHECK11-NEXT:    store i32 9, i32* [[DOTOMP_UB38]], align 4
15394 // CHECK11-NEXT:    [[TMP24:%.*]] = load i32, i32* [[DOTOMP_LB37]], align 4
15395 // CHECK11-NEXT:    store i32 [[TMP24]], i32* [[DOTOMP_IV39]], align 4
15396 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_COND41:%.*]]
15397 // CHECK11:       omp.inner.for.cond41:
15398 // CHECK11-NEXT:    [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IV39]], align 4, !llvm.access.group !13
15399 // CHECK11-NEXT:    [[TMP26:%.*]] = load i32, i32* [[DOTOMP_UB38]], align 4, !llvm.access.group !13
15400 // CHECK11-NEXT:    [[CMP42:%.*]] = icmp sle i32 [[TMP25]], [[TMP26]]
15401 // CHECK11-NEXT:    br i1 [[CMP42]], label [[OMP_INNER_FOR_BODY43:%.*]], label [[OMP_INNER_FOR_END53:%.*]]
15402 // CHECK11:       omp.inner.for.body43:
15403 // CHECK11-NEXT:    [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV39]], align 4, !llvm.access.group !13
15404 // CHECK11-NEXT:    [[MUL44:%.*]] = mul nsw i32 [[TMP27]], 1
15405 // CHECK11-NEXT:    [[ADD45:%.*]] = add nsw i32 0, [[MUL44]]
15406 // CHECK11-NEXT:    store i32 [[ADD45]], i32* [[I40]], align 4, !llvm.access.group !13
15407 // CHECK11-NEXT:    [[TMP28:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !13
15408 // CHECK11-NEXT:    [[ADD46:%.*]] = add nsw i32 [[TMP28]], 1
15409 // CHECK11-NEXT:    store i32 [[ADD46]], i32* [[A]], align 4, !llvm.access.group !13
15410 // CHECK11-NEXT:    [[TMP29:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !13
15411 // CHECK11-NEXT:    [[CONV47:%.*]] = sext i16 [[TMP29]] to i32
15412 // CHECK11-NEXT:    [[ADD48:%.*]] = add nsw i32 [[CONV47]], 1
15413 // CHECK11-NEXT:    [[CONV49:%.*]] = trunc i32 [[ADD48]] to i16
15414 // CHECK11-NEXT:    store i16 [[CONV49]], i16* [[AA]], align 2, !llvm.access.group !13
15415 // CHECK11-NEXT:    br label [[OMP_BODY_CONTINUE50:%.*]]
15416 // CHECK11:       omp.body.continue50:
15417 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_INC51:%.*]]
15418 // CHECK11:       omp.inner.for.inc51:
15419 // CHECK11-NEXT:    [[TMP30:%.*]] = load i32, i32* [[DOTOMP_IV39]], align 4, !llvm.access.group !13
15420 // CHECK11-NEXT:    [[ADD52:%.*]] = add nsw i32 [[TMP30]], 1
15421 // CHECK11-NEXT:    store i32 [[ADD52]], i32* [[DOTOMP_IV39]], align 4, !llvm.access.group !13
15422 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_COND41]], !llvm.loop [[LOOP14:![0-9]+]]
15423 // CHECK11:       omp.inner.for.end53:
15424 // CHECK11-NEXT:    store i32 10, i32* [[I40]], align 4
15425 // CHECK11-NEXT:    store i32 0, i32* [[DOTOMP_LB55]], align 4
15426 // CHECK11-NEXT:    store i32 9, i32* [[DOTOMP_UB56]], align 4
15427 // CHECK11-NEXT:    [[TMP31:%.*]] = load i32, i32* [[DOTOMP_LB55]], align 4
15428 // CHECK11-NEXT:    store i32 [[TMP31]], i32* [[DOTOMP_IV57]], align 4
15429 // CHECK11-NEXT:    [[ARRAYDECAY:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 0
15430 // CHECK11-NEXT:    call void @llvm.assume(i1 true) [ "align"(float* [[ARRAYDECAY]], i32 16) ]
15431 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_COND59:%.*]]
15432 // CHECK11:       omp.inner.for.cond59:
15433 // CHECK11-NEXT:    [[TMP32:%.*]] = load i32, i32* [[DOTOMP_IV57]], align 4, !llvm.access.group !16
15434 // CHECK11-NEXT:    [[TMP33:%.*]] = load i32, i32* [[DOTOMP_UB56]], align 4, !llvm.access.group !16
15435 // CHECK11-NEXT:    [[CMP60:%.*]] = icmp sle i32 [[TMP32]], [[TMP33]]
15436 // CHECK11-NEXT:    br i1 [[CMP60]], label [[OMP_INNER_FOR_BODY61:%.*]], label [[OMP_INNER_FOR_END85:%.*]]
15437 // CHECK11:       omp.inner.for.body61:
15438 // CHECK11-NEXT:    [[TMP34:%.*]] = load i32, i32* [[DOTOMP_IV57]], align 4, !llvm.access.group !16
15439 // CHECK11-NEXT:    [[MUL62:%.*]] = mul nsw i32 [[TMP34]], 1
15440 // CHECK11-NEXT:    [[ADD63:%.*]] = add nsw i32 0, [[MUL62]]
15441 // CHECK11-NEXT:    store i32 [[ADD63]], i32* [[I58]], align 4, !llvm.access.group !16
15442 // CHECK11-NEXT:    [[TMP35:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !16
15443 // CHECK11-NEXT:    [[ADD64:%.*]] = add nsw i32 [[TMP35]], 1
15444 // CHECK11-NEXT:    store i32 [[ADD64]], i32* [[A]], align 4, !llvm.access.group !16
15445 // CHECK11-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2
15446 // CHECK11-NEXT:    [[TMP36:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !16
15447 // CHECK11-NEXT:    [[CONV65:%.*]] = fpext float [[TMP36]] to double
15448 // CHECK11-NEXT:    [[ADD66:%.*]] = fadd double [[CONV65]], 1.000000e+00
15449 // CHECK11-NEXT:    [[CONV67:%.*]] = fptrunc double [[ADD66]] to float
15450 // CHECK11-NEXT:    store float [[CONV67]], float* [[ARRAYIDX]], align 4, !llvm.access.group !16
15451 // CHECK11-NEXT:    [[ARRAYIDX68:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3
15452 // CHECK11-NEXT:    [[TMP37:%.*]] = load float, float* [[ARRAYIDX68]], align 4, !llvm.access.group !16
15453 // CHECK11-NEXT:    [[CONV69:%.*]] = fpext float [[TMP37]] to double
15454 // CHECK11-NEXT:    [[ADD70:%.*]] = fadd double [[CONV69]], 1.000000e+00
15455 // CHECK11-NEXT:    [[CONV71:%.*]] = fptrunc double [[ADD70]] to float
15456 // CHECK11-NEXT:    store float [[CONV71]], float* [[ARRAYIDX68]], align 4, !llvm.access.group !16
15457 // CHECK11-NEXT:    [[ARRAYIDX72:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1
15458 // CHECK11-NEXT:    [[ARRAYIDX73:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX72]], i32 0, i32 2
15459 // CHECK11-NEXT:    [[TMP38:%.*]] = load double, double* [[ARRAYIDX73]], align 8, !llvm.access.group !16
15460 // CHECK11-NEXT:    [[ADD74:%.*]] = fadd double [[TMP38]], 1.000000e+00
15461 // CHECK11-NEXT:    store double [[ADD74]], double* [[ARRAYIDX73]], align 8, !llvm.access.group !16
15462 // CHECK11-NEXT:    [[TMP39:%.*]] = mul nsw i32 1, [[TMP2]]
15463 // CHECK11-NEXT:    [[ARRAYIDX75:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP39]]
15464 // CHECK11-NEXT:    [[ARRAYIDX76:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX75]], i32 3
15465 // CHECK11-NEXT:    [[TMP40:%.*]] = load double, double* [[ARRAYIDX76]], align 8, !llvm.access.group !16
15466 // CHECK11-NEXT:    [[ADD77:%.*]] = fadd double [[TMP40]], 1.000000e+00
15467 // CHECK11-NEXT:    store double [[ADD77]], double* [[ARRAYIDX76]], align 8, !llvm.access.group !16
15468 // CHECK11-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0
15469 // CHECK11-NEXT:    [[TMP41:%.*]] = load i64, i64* [[X]], align 4, !llvm.access.group !16
15470 // CHECK11-NEXT:    [[ADD78:%.*]] = add nsw i64 [[TMP41]], 1
15471 // CHECK11-NEXT:    store i64 [[ADD78]], i64* [[X]], align 4, !llvm.access.group !16
15472 // CHECK11-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1
15473 // CHECK11-NEXT:    [[TMP42:%.*]] = load i8, i8* [[Y]], align 4, !llvm.access.group !16
15474 // CHECK11-NEXT:    [[CONV79:%.*]] = sext i8 [[TMP42]] to i32
15475 // CHECK11-NEXT:    [[ADD80:%.*]] = add nsw i32 [[CONV79]], 1
15476 // CHECK11-NEXT:    [[CONV81:%.*]] = trunc i32 [[ADD80]] to i8
15477 // CHECK11-NEXT:    store i8 [[CONV81]], i8* [[Y]], align 4, !llvm.access.group !16
15478 // CHECK11-NEXT:    br label [[OMP_BODY_CONTINUE82:%.*]]
15479 // CHECK11:       omp.body.continue82:
15480 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_INC83:%.*]]
15481 // CHECK11:       omp.inner.for.inc83:
15482 // CHECK11-NEXT:    [[TMP43:%.*]] = load i32, i32* [[DOTOMP_IV57]], align 4, !llvm.access.group !16
15483 // CHECK11-NEXT:    [[ADD84:%.*]] = add nsw i32 [[TMP43]], 1
15484 // CHECK11-NEXT:    store i32 [[ADD84]], i32* [[DOTOMP_IV57]], align 4, !llvm.access.group !16
15485 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_COND59]], !llvm.loop [[LOOP17:![0-9]+]]
15486 // CHECK11:       omp.inner.for.end85:
15487 // CHECK11-NEXT:    store i32 10, i32* [[I58]], align 4
15488 // CHECK11-NEXT:    [[TMP44:%.*]] = load i32, i32* [[A]], align 4
15489 // CHECK11-NEXT:    [[TMP45:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
15490 // CHECK11-NEXT:    call void @llvm.stackrestore(i8* [[TMP45]])
15491 // CHECK11-NEXT:    ret i32 [[TMP44]]
15492 //
15493 //
15494 // CHECK11-LABEL: define {{[^@]+}}@_Z3bari
15495 // CHECK11-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {
15496 // CHECK11-NEXT:  entry:
15497 // CHECK11-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
15498 // CHECK11-NEXT:    [[A:%.*]] = alloca i32, align 4
15499 // CHECK11-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4
15500 // CHECK11-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
15501 // CHECK11-NEXT:    store i32 0, i32* [[A]], align 4
15502 // CHECK11-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
15503 // CHECK11-NEXT:    [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]])
15504 // CHECK11-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
15505 // CHECK11-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
15506 // CHECK11-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
15507 // CHECK11-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
15508 // CHECK11-NEXT:    [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP2]])
15509 // CHECK11-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
15510 // CHECK11-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
15511 // CHECK11-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
15512 // CHECK11-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
15513 // CHECK11-NEXT:    [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]])
15514 // CHECK11-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
15515 // CHECK11-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
15516 // CHECK11-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
15517 // CHECK11-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
15518 // CHECK11-NEXT:    [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]])
15519 // CHECK11-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
15520 // CHECK11-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
15521 // CHECK11-NEXT:    store i32 [[ADD6]], i32* [[A]], align 4
15522 // CHECK11-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
15523 // CHECK11-NEXT:    ret i32 [[TMP8]]
15524 //
15525 //
15526 // CHECK11-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
15527 // CHECK11-SAME: (%struct.S1* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 {
15528 // CHECK11-NEXT:  entry:
15529 // CHECK11-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
15530 // CHECK11-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
15531 // CHECK11-NEXT:    [[B:%.*]] = alloca i32, align 4
15532 // CHECK11-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 4
15533 // CHECK11-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 4
15534 // CHECK11-NEXT:    [[TMP:%.*]] = alloca i32, align 4
15535 // CHECK11-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
15536 // CHECK11-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
15537 // CHECK11-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
15538 // CHECK11-NEXT:    [[I:%.*]] = alloca i32, align 4
15539 // CHECK11-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
15540 // CHECK11-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
15541 // CHECK11-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
15542 // CHECK11-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
15543 // CHECK11-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
15544 // CHECK11-NEXT:    store i32 [[ADD]], i32* [[B]], align 4
15545 // CHECK11-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
15546 // CHECK11-NEXT:    [[TMP2:%.*]] = call i8* @llvm.stacksave()
15547 // CHECK11-NEXT:    store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4
15548 // CHECK11-NEXT:    [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]
15549 // CHECK11-NEXT:    [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2
15550 // CHECK11-NEXT:    store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
15551 // CHECK11-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
15552 // CHECK11-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
15553 // CHECK11-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
15554 // CHECK11-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
15555 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
15556 // CHECK11:       omp.inner.for.cond:
15557 // CHECK11-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
15558 // CHECK11-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !19
15559 // CHECK11-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
15560 // CHECK11-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
15561 // CHECK11:       omp.inner.for.body:
15562 // CHECK11-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
15563 // CHECK11-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
15564 // CHECK11-NEXT:    [[ADD2:%.*]] = add nsw i32 0, [[MUL]]
15565 // CHECK11-NEXT:    store i32 [[ADD2]], i32* [[I]], align 4, !llvm.access.group !19
15566 // CHECK11-NEXT:    [[TMP8:%.*]] = load i32, i32* [[B]], align 4, !llvm.access.group !19
15567 // CHECK11-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP8]] to double
15568 // CHECK11-NEXT:    [[ADD3:%.*]] = fadd double [[CONV]], 1.500000e+00
15569 // CHECK11-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
15570 // CHECK11-NEXT:    store double [[ADD3]], double* [[A]], align 4, !llvm.access.group !19
15571 // CHECK11-NEXT:    [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
15572 // CHECK11-NEXT:    [[TMP9:%.*]] = load double, double* [[A4]], align 4, !llvm.access.group !19
15573 // CHECK11-NEXT:    [[INC:%.*]] = fadd double [[TMP9]], 1.000000e+00
15574 // CHECK11-NEXT:    store double [[INC]], double* [[A4]], align 4, !llvm.access.group !19
15575 // CHECK11-NEXT:    [[CONV5:%.*]] = fptosi double [[INC]] to i16
15576 // CHECK11-NEXT:    [[TMP10:%.*]] = mul nsw i32 1, [[TMP1]]
15577 // CHECK11-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP10]]
15578 // CHECK11-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
15579 // CHECK11-NEXT:    store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2, !llvm.access.group !19
15580 // CHECK11-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
15581 // CHECK11:       omp.body.continue:
15582 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
15583 // CHECK11:       omp.inner.for.inc:
15584 // CHECK11-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
15585 // CHECK11-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1
15586 // CHECK11-NEXT:    store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
15587 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]]
15588 // CHECK11:       omp.inner.for.end:
15589 // CHECK11-NEXT:    store i32 10, i32* [[I]], align 4
15590 // CHECK11-NEXT:    [[TMP12:%.*]] = mul nsw i32 1, [[TMP1]]
15591 // CHECK11-NEXT:    [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP12]]
15592 // CHECK11-NEXT:    [[ARRAYIDX9:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX8]], i32 1
15593 // CHECK11-NEXT:    [[TMP13:%.*]] = load i16, i16* [[ARRAYIDX9]], align 2
15594 // CHECK11-NEXT:    [[CONV10:%.*]] = sext i16 [[TMP13]] to i32
15595 // CHECK11-NEXT:    [[TMP14:%.*]] = load i32, i32* [[B]], align 4
15596 // CHECK11-NEXT:    [[ADD11:%.*]] = add nsw i32 [[CONV10]], [[TMP14]]
15597 // CHECK11-NEXT:    [[TMP15:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
15598 // CHECK11-NEXT:    call void @llvm.stackrestore(i8* [[TMP15]])
15599 // CHECK11-NEXT:    ret i32 [[ADD11]]
15600 //
15601 //
15602 // CHECK11-LABEL: define {{[^@]+}}@_ZL7fstatici
15603 // CHECK11-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {
15604 // CHECK11-NEXT:  entry:
15605 // CHECK11-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
15606 // CHECK11-NEXT:    [[A:%.*]] = alloca i32, align 4
15607 // CHECK11-NEXT:    [[AA:%.*]] = alloca i16, align 2
15608 // CHECK11-NEXT:    [[AAA:%.*]] = alloca i8, align 1
15609 // CHECK11-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
15610 // CHECK11-NEXT:    [[TMP:%.*]] = alloca i32, align 4
15611 // CHECK11-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
15612 // CHECK11-NEXT:    [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
15613 // CHECK11-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
15614 // CHECK11-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
15615 // CHECK11-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
15616 // CHECK11-NEXT:    [[I:%.*]] = alloca i32, align 4
15617 // CHECK11-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
15618 // CHECK11-NEXT:    [[I5:%.*]] = alloca i32, align 4
15619 // CHECK11-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
15620 // CHECK11-NEXT:    store i32 0, i32* [[A]], align 4
15621 // CHECK11-NEXT:    store i16 0, i16* [[AA]], align 2
15622 // CHECK11-NEXT:    store i8 0, i8* [[AAA]], align 1
15623 // CHECK11-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
15624 // CHECK11-NEXT:    store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4
15625 // CHECK11-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
15626 // CHECK11-NEXT:    store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_1]], align 4
15627 // CHECK11-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
15628 // CHECK11-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
15629 // CHECK11-NEXT:    [[SUB:%.*]] = sub i32 [[TMP2]], [[TMP3]]
15630 // CHECK11-NEXT:    [[SUB3:%.*]] = sub i32 [[SUB]], 1
15631 // CHECK11-NEXT:    [[ADD:%.*]] = add i32 [[SUB3]], 1
15632 // CHECK11-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], 1
15633 // CHECK11-NEXT:    [[SUB4:%.*]] = sub i32 [[DIV]], 1
15634 // CHECK11-NEXT:    store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_2]], align 4
15635 // CHECK11-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
15636 // CHECK11-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
15637 // CHECK11-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_UB]], align 4
15638 // CHECK11-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
15639 // CHECK11-NEXT:    store i32 [[TMP5]], i32* [[I]], align 4
15640 // CHECK11-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
15641 // CHECK11-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
15642 // CHECK11-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]]
15643 // CHECK11-NEXT:    br i1 [[CMP]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END:%.*]]
15644 // CHECK11:       simd.if.then:
15645 // CHECK11-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
15646 // CHECK11-NEXT:    store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
15647 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
15648 // CHECK11:       omp.inner.for.cond:
15649 // CHECK11-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
15650 // CHECK11-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !22
15651 // CHECK11-NEXT:    [[ADD6:%.*]] = add i32 [[TMP10]], 1
15652 // CHECK11-NEXT:    [[CMP7:%.*]] = icmp ult i32 [[TMP9]], [[ADD6]]
15653 // CHECK11-NEXT:    br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
15654 // CHECK11:       omp.inner.for.body:
15655 // CHECK11-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group !22
15656 // CHECK11-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
15657 // CHECK11-NEXT:    [[MUL:%.*]] = mul i32 [[TMP12]], 1
15658 // CHECK11-NEXT:    [[ADD8:%.*]] = add i32 [[TMP11]], [[MUL]]
15659 // CHECK11-NEXT:    store i32 [[ADD8]], i32* [[I5]], align 4, !llvm.access.group !22
15660 // CHECK11-NEXT:    [[TMP13:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !22
15661 // CHECK11-NEXT:    [[ADD9:%.*]] = add nsw i32 [[TMP13]], 1
15662 // CHECK11-NEXT:    store i32 [[ADD9]], i32* [[A]], align 4, !llvm.access.group !22
15663 // CHECK11-NEXT:    [[TMP14:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !22
15664 // CHECK11-NEXT:    [[CONV:%.*]] = sext i16 [[TMP14]] to i32
15665 // CHECK11-NEXT:    [[ADD10:%.*]] = add nsw i32 [[CONV]], 1
15666 // CHECK11-NEXT:    [[CONV11:%.*]] = trunc i32 [[ADD10]] to i16
15667 // CHECK11-NEXT:    store i16 [[CONV11]], i16* [[AA]], align 2, !llvm.access.group !22
15668 // CHECK11-NEXT:    [[TMP15:%.*]] = load i8, i8* [[AAA]], align 1, !llvm.access.group !22
15669 // CHECK11-NEXT:    [[CONV12:%.*]] = sext i8 [[TMP15]] to i32
15670 // CHECK11-NEXT:    [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1
15671 // CHECK11-NEXT:    [[CONV14:%.*]] = trunc i32 [[ADD13]] to i8
15672 // CHECK11-NEXT:    store i8 [[CONV14]], i8* [[AAA]], align 1, !llvm.access.group !22
15673 // CHECK11-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2
15674 // CHECK11-NEXT:    [[TMP16:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !22
15675 // CHECK11-NEXT:    [[ADD15:%.*]] = add nsw i32 [[TMP16]], 1
15676 // CHECK11-NEXT:    store i32 [[ADD15]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !22
15677 // CHECK11-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
15678 // CHECK11:       omp.body.continue:
15679 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
15680 // CHECK11:       omp.inner.for.inc:
15681 // CHECK11-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
15682 // CHECK11-NEXT:    [[ADD16:%.*]] = add i32 [[TMP17]], 1
15683 // CHECK11-NEXT:    store i32 [[ADD16]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
15684 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]]
15685 // CHECK11:       omp.inner.for.end:
15686 // CHECK11-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
15687 // CHECK11-NEXT:    [[TMP19:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
15688 // CHECK11-NEXT:    [[TMP20:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
15689 // CHECK11-NEXT:    [[SUB17:%.*]] = sub i32 [[TMP19]], [[TMP20]]
15690 // CHECK11-NEXT:    [[SUB18:%.*]] = sub i32 [[SUB17]], 1
15691 // CHECK11-NEXT:    [[ADD19:%.*]] = add i32 [[SUB18]], 1
15692 // CHECK11-NEXT:    [[DIV20:%.*]] = udiv i32 [[ADD19]], 1
15693 // CHECK11-NEXT:    [[MUL21:%.*]] = mul i32 [[DIV20]], 1
15694 // CHECK11-NEXT:    [[ADD22:%.*]] = add i32 [[TMP18]], [[MUL21]]
15695 // CHECK11-NEXT:    store i32 [[ADD22]], i32* [[I5]], align 4
15696 // CHECK11-NEXT:    br label [[SIMD_IF_END]]
15697 // CHECK11:       simd.if.end:
15698 // CHECK11-NEXT:    [[TMP21:%.*]] = load i32, i32* [[A]], align 4
15699 // CHECK11-NEXT:    ret i32 [[TMP21]]
15700 //
15701 //
15702 // CHECK11-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
15703 // CHECK11-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat {
15704 // CHECK11-NEXT:  entry:
15705 // CHECK11-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
15706 // CHECK11-NEXT:    [[A:%.*]] = alloca i32, align 4
15707 // CHECK11-NEXT:    [[AA:%.*]] = alloca i16, align 2
15708 // CHECK11-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
15709 // CHECK11-NEXT:    [[TMP:%.*]] = alloca i32, align 4
15710 // CHECK11-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
15711 // CHECK11-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
15712 // CHECK11-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
15713 // CHECK11-NEXT:    [[I:%.*]] = alloca i32, align 4
15714 // CHECK11-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
15715 // CHECK11-NEXT:    store i32 0, i32* [[A]], align 4
15716 // CHECK11-NEXT:    store i16 0, i16* [[AA]], align 2
15717 // CHECK11-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
15718 // CHECK11-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
15719 // CHECK11-NEXT:    [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
15720 // CHECK11-NEXT:    store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4
15721 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
15722 // CHECK11:       omp.inner.for.cond:
15723 // CHECK11-NEXT:    [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25
15724 // CHECK11-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !25
15725 // CHECK11-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
15726 // CHECK11-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
15727 // CHECK11:       omp.inner.for.body:
15728 // CHECK11-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25
15729 // CHECK11-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1
15730 // CHECK11-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
15731 // CHECK11-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !25
15732 // CHECK11-NEXT:    [[TMP4:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !25
15733 // CHECK11-NEXT:    [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1
15734 // CHECK11-NEXT:    store i32 [[ADD1]], i32* [[A]], align 4, !llvm.access.group !25
15735 // CHECK11-NEXT:    [[TMP5:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !25
15736 // CHECK11-NEXT:    [[CONV:%.*]] = sext i16 [[TMP5]] to i32
15737 // CHECK11-NEXT:    [[ADD2:%.*]] = add nsw i32 [[CONV]], 1
15738 // CHECK11-NEXT:    [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
15739 // CHECK11-NEXT:    store i16 [[CONV3]], i16* [[AA]], align 2, !llvm.access.group !25
15740 // CHECK11-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2
15741 // CHECK11-NEXT:    [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !25
15742 // CHECK11-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP6]], 1
15743 // CHECK11-NEXT:    store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !25
15744 // CHECK11-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
15745 // CHECK11:       omp.body.continue:
15746 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
15747 // CHECK11:       omp.inner.for.inc:
15748 // CHECK11-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25
15749 // CHECK11-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP7]], 1
15750 // CHECK11-NEXT:    store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25
15751 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP26:![0-9]+]]
15752 // CHECK11:       omp.inner.for.end:
15753 // CHECK11-NEXT:    store i32 10, i32* [[I]], align 4
15754 // CHECK11-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
15755 // CHECK11-NEXT:    ret i32 [[TMP8]]
15756 //
15757 //
15758 // CHECK12-LABEL: define {{[^@]+}}@_Z3fooi
15759 // CHECK12-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0:[0-9]+]] {
15760 // CHECK12-NEXT:  entry:
15761 // CHECK12-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
15762 // CHECK12-NEXT:    [[A:%.*]] = alloca i32, align 4
15763 // CHECK12-NEXT:    [[AA:%.*]] = alloca i16, align 2
15764 // CHECK12-NEXT:    [[B:%.*]] = alloca [10 x float], align 4
15765 // CHECK12-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 4
15766 // CHECK12-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 4
15767 // CHECK12-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 8
15768 // CHECK12-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i32, align 4
15769 // CHECK12-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4
15770 // CHECK12-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
15771 // CHECK12-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
15772 // CHECK12-NEXT:    [[TMP:%.*]] = alloca i32, align 4
15773 // CHECK12-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
15774 // CHECK12-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
15775 // CHECK12-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
15776 // CHECK12-NEXT:    [[I:%.*]] = alloca i32, align 4
15777 // CHECK12-NEXT:    [[_TMP4:%.*]] = alloca i32, align 4
15778 // CHECK12-NEXT:    [[DOTOMP_LB5:%.*]] = alloca i32, align 4
15779 // CHECK12-NEXT:    [[DOTOMP_UB6:%.*]] = alloca i32, align 4
15780 // CHECK12-NEXT:    [[DOTOMP_IV7:%.*]] = alloca i32, align 4
15781 // CHECK12-NEXT:    [[DOTLINEAR_START:%.*]] = alloca i32, align 4
15782 // CHECK12-NEXT:    [[A8:%.*]] = alloca i32, align 4
15783 // CHECK12-NEXT:    [[A9:%.*]] = alloca i32, align 4
15784 // CHECK12-NEXT:    [[_TMP20:%.*]] = alloca i32, align 4
15785 // CHECK12-NEXT:    [[DOTOMP_LB21:%.*]] = alloca i32, align 4
15786 // CHECK12-NEXT:    [[DOTOMP_UB22:%.*]] = alloca i32, align 4
15787 // CHECK12-NEXT:    [[DOTOMP_IV23:%.*]] = alloca i32, align 4
15788 // CHECK12-NEXT:    [[I24:%.*]] = alloca i32, align 4
15789 // CHECK12-NEXT:    [[_TMP36:%.*]] = alloca i32, align 4
15790 // CHECK12-NEXT:    [[DOTOMP_LB37:%.*]] = alloca i32, align 4
15791 // CHECK12-NEXT:    [[DOTOMP_UB38:%.*]] = alloca i32, align 4
15792 // CHECK12-NEXT:    [[DOTOMP_IV39:%.*]] = alloca i32, align 4
15793 // CHECK12-NEXT:    [[I40:%.*]] = alloca i32, align 4
15794 // CHECK12-NEXT:    [[_TMP54:%.*]] = alloca i32, align 4
15795 // CHECK12-NEXT:    [[DOTOMP_LB55:%.*]] = alloca i32, align 4
15796 // CHECK12-NEXT:    [[DOTOMP_UB56:%.*]] = alloca i32, align 4
15797 // CHECK12-NEXT:    [[DOTOMP_IV57:%.*]] = alloca i32, align 4
15798 // CHECK12-NEXT:    [[I58:%.*]] = alloca i32, align 4
15799 // CHECK12-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
15800 // CHECK12-NEXT:    store i32 0, i32* [[A]], align 4
15801 // CHECK12-NEXT:    store i16 0, i16* [[AA]], align 2
15802 // CHECK12-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
15803 // CHECK12-NEXT:    [[TMP1:%.*]] = call i8* @llvm.stacksave()
15804 // CHECK12-NEXT:    store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4
15805 // CHECK12-NEXT:    [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4
15806 // CHECK12-NEXT:    store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4
15807 // CHECK12-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
15808 // CHECK12-NEXT:    [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]]
15809 // CHECK12-NEXT:    [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8
15810 // CHECK12-NEXT:    store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4
15811 // CHECK12-NEXT:    [[TMP4:%.*]] = load i32, i32* [[A]], align 4
15812 // CHECK12-NEXT:    store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4
15813 // CHECK12-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
15814 // CHECK12-NEXT:    store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_2]], align 4
15815 // CHECK12-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
15816 // CHECK12-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
15817 // CHECK12-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
15818 // CHECK12-NEXT:    store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
15819 // CHECK12-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
15820 // CHECK12:       omp.inner.for.cond:
15821 // CHECK12-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
15822 // CHECK12-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !3
15823 // CHECK12-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
15824 // CHECK12-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
15825 // CHECK12:       omp.inner.for.body:
15826 // CHECK12-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
15827 // CHECK12-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
15828 // CHECK12-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
15829 // CHECK12-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !3
15830 // CHECK12-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
15831 // CHECK12:       omp.body.continue:
15832 // CHECK12-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
15833 // CHECK12:       omp.inner.for.inc:
15834 // CHECK12-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
15835 // CHECK12-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
15836 // CHECK12-NEXT:    store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
15837 // CHECK12-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]
15838 // CHECK12:       omp.inner.for.end:
15839 // CHECK12-NEXT:    store i32 10, i32* [[I]], align 4
15840 // CHECK12-NEXT:    store i32 0, i32* [[DOTOMP_LB5]], align 4
15841 // CHECK12-NEXT:    store i32 9, i32* [[DOTOMP_UB6]], align 4
15842 // CHECK12-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_LB5]], align 4
15843 // CHECK12-NEXT:    store i32 [[TMP11]], i32* [[DOTOMP_IV7]], align 4
15844 // CHECK12-NEXT:    [[TMP12:%.*]] = load i32, i32* [[A]], align 4
15845 // CHECK12-NEXT:    store i32 [[TMP12]], i32* [[DOTLINEAR_START]], align 4
15846 // CHECK12-NEXT:    br label [[OMP_INNER_FOR_COND10:%.*]]
15847 // CHECK12:       omp.inner.for.cond10:
15848 // CHECK12-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV7]], align 4
15849 // CHECK12-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB6]], align 4
15850 // CHECK12-NEXT:    [[CMP11:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
15851 // CHECK12-NEXT:    br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY12:%.*]], label [[OMP_INNER_FOR_END19:%.*]]
15852 // CHECK12:       omp.inner.for.body12:
15853 // CHECK12-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV7]], align 4
15854 // CHECK12-NEXT:    [[MUL13:%.*]] = mul nsw i32 [[TMP15]], 1
15855 // CHECK12-NEXT:    [[ADD14:%.*]] = add nsw i32 0, [[MUL13]]
15856 // CHECK12-NEXT:    store i32 [[ADD14]], i32* [[A8]], align 4
15857 // CHECK12-NEXT:    [[TMP16:%.*]] = load i32, i32* [[A8]], align 4
15858 // CHECK12-NEXT:    [[ADD15:%.*]] = add nsw i32 [[TMP16]], 1
15859 // CHECK12-NEXT:    store i32 [[ADD15]], i32* [[A8]], align 4
15860 // CHECK12-NEXT:    br label [[OMP_BODY_CONTINUE16:%.*]]
15861 // CHECK12:       omp.body.continue16:
15862 // CHECK12-NEXT:    br label [[OMP_INNER_FOR_INC17:%.*]]
15863 // CHECK12:       omp.inner.for.inc17:
15864 // CHECK12-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV7]], align 4
15865 // CHECK12-NEXT:    [[ADD18:%.*]] = add nsw i32 [[TMP17]], 1
15866 // CHECK12-NEXT:    store i32 [[ADD18]], i32* [[DOTOMP_IV7]], align 4
15867 // CHECK12-NEXT:    br label [[OMP_INNER_FOR_COND10]], !llvm.loop [[LOOP8:![0-9]+]]
15868 // CHECK12:       omp.inner.for.end19:
15869 // CHECK12-NEXT:    store i32 10, i32* [[A]], align 4
15870 // CHECK12-NEXT:    store i32 0, i32* [[DOTOMP_LB21]], align 4
15871 // CHECK12-NEXT:    store i32 9, i32* [[DOTOMP_UB22]], align 4
15872 // CHECK12-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTOMP_LB21]], align 4
15873 // CHECK12-NEXT:    store i32 [[TMP18]], i32* [[DOTOMP_IV23]], align 4
15874 // CHECK12-NEXT:    br label [[OMP_INNER_FOR_COND25:%.*]]
15875 // CHECK12:       omp.inner.for.cond25:
15876 // CHECK12-NEXT:    [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV23]], align 4, !llvm.access.group !10
15877 // CHECK12-NEXT:    [[TMP20:%.*]] = load i32, i32* [[DOTOMP_UB22]], align 4, !llvm.access.group !10
15878 // CHECK12-NEXT:    [[CMP26:%.*]] = icmp sle i32 [[TMP19]], [[TMP20]]
15879 // CHECK12-NEXT:    br i1 [[CMP26]], label [[OMP_INNER_FOR_BODY27:%.*]], label [[OMP_INNER_FOR_END35:%.*]]
15880 // CHECK12:       omp.inner.for.body27:
15881 // CHECK12-NEXT:    [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV23]], align 4, !llvm.access.group !10
15882 // CHECK12-NEXT:    [[MUL28:%.*]] = mul nsw i32 [[TMP21]], 1
15883 // CHECK12-NEXT:    [[ADD29:%.*]] = add nsw i32 0, [[MUL28]]
15884 // CHECK12-NEXT:    store i32 [[ADD29]], i32* [[I24]], align 4, !llvm.access.group !10
15885 // CHECK12-NEXT:    [[TMP22:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !10
15886 // CHECK12-NEXT:    [[CONV:%.*]] = sext i16 [[TMP22]] to i32
15887 // CHECK12-NEXT:    [[ADD30:%.*]] = add nsw i32 [[CONV]], 1
15888 // CHECK12-NEXT:    [[CONV31:%.*]] = trunc i32 [[ADD30]] to i16
15889 // CHECK12-NEXT:    store i16 [[CONV31]], i16* [[AA]], align 2, !llvm.access.group !10
15890 // CHECK12-NEXT:    br label [[OMP_BODY_CONTINUE32:%.*]]
15891 // CHECK12:       omp.body.continue32:
15892 // CHECK12-NEXT:    br label [[OMP_INNER_FOR_INC33:%.*]]
15893 // CHECK12:       omp.inner.for.inc33:
15894 // CHECK12-NEXT:    [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV23]], align 4, !llvm.access.group !10
15895 // CHECK12-NEXT:    [[ADD34:%.*]] = add nsw i32 [[TMP23]], 1
15896 // CHECK12-NEXT:    store i32 [[ADD34]], i32* [[DOTOMP_IV23]], align 4, !llvm.access.group !10
15897 // CHECK12-NEXT:    br label [[OMP_INNER_FOR_COND25]], !llvm.loop [[LOOP11:![0-9]+]]
15898 // CHECK12:       omp.inner.for.end35:
15899 // CHECK12-NEXT:    store i32 10, i32* [[I24]], align 4
15900 // CHECK12-NEXT:    store i32 0, i32* [[DOTOMP_LB37]], align 4
15901 // CHECK12-NEXT:    store i32 9, i32* [[DOTOMP_UB38]], align 4
15902 // CHECK12-NEXT:    [[TMP24:%.*]] = load i32, i32* [[DOTOMP_LB37]], align 4
15903 // CHECK12-NEXT:    store i32 [[TMP24]], i32* [[DOTOMP_IV39]], align 4
15904 // CHECK12-NEXT:    br label [[OMP_INNER_FOR_COND41:%.*]]
15905 // CHECK12:       omp.inner.for.cond41:
15906 // CHECK12-NEXT:    [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IV39]], align 4, !llvm.access.group !13
15907 // CHECK12-NEXT:    [[TMP26:%.*]] = load i32, i32* [[DOTOMP_UB38]], align 4, !llvm.access.group !13
15908 // CHECK12-NEXT:    [[CMP42:%.*]] = icmp sle i32 [[TMP25]], [[TMP26]]
15909 // CHECK12-NEXT:    br i1 [[CMP42]], label [[OMP_INNER_FOR_BODY43:%.*]], label [[OMP_INNER_FOR_END53:%.*]]
15910 // CHECK12:       omp.inner.for.body43:
15911 // CHECK12-NEXT:    [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV39]], align 4, !llvm.access.group !13
15912 // CHECK12-NEXT:    [[MUL44:%.*]] = mul nsw i32 [[TMP27]], 1
15913 // CHECK12-NEXT:    [[ADD45:%.*]] = add nsw i32 0, [[MUL44]]
15914 // CHECK12-NEXT:    store i32 [[ADD45]], i32* [[I40]], align 4, !llvm.access.group !13
15915 // CHECK12-NEXT:    [[TMP28:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !13
15916 // CHECK12-NEXT:    [[ADD46:%.*]] = add nsw i32 [[TMP28]], 1
15917 // CHECK12-NEXT:    store i32 [[ADD46]], i32* [[A]], align 4, !llvm.access.group !13
15918 // CHECK12-NEXT:    [[TMP29:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !13
15919 // CHECK12-NEXT:    [[CONV47:%.*]] = sext i16 [[TMP29]] to i32
15920 // CHECK12-NEXT:    [[ADD48:%.*]] = add nsw i32 [[CONV47]], 1
15921 // CHECK12-NEXT:    [[CONV49:%.*]] = trunc i32 [[ADD48]] to i16
15922 // CHECK12-NEXT:    store i16 [[CONV49]], i16* [[AA]], align 2, !llvm.access.group !13
15923 // CHECK12-NEXT:    br label [[OMP_BODY_CONTINUE50:%.*]]
15924 // CHECK12:       omp.body.continue50:
15925 // CHECK12-NEXT:    br label [[OMP_INNER_FOR_INC51:%.*]]
15926 // CHECK12:       omp.inner.for.inc51:
15927 // CHECK12-NEXT:    [[TMP30:%.*]] = load i32, i32* [[DOTOMP_IV39]], align 4, !llvm.access.group !13
15928 // CHECK12-NEXT:    [[ADD52:%.*]] = add nsw i32 [[TMP30]], 1
15929 // CHECK12-NEXT:    store i32 [[ADD52]], i32* [[DOTOMP_IV39]], align 4, !llvm.access.group !13
15930 // CHECK12-NEXT:    br label [[OMP_INNER_FOR_COND41]], !llvm.loop [[LOOP14:![0-9]+]]
15931 // CHECK12:       omp.inner.for.end53:
15932 // CHECK12-NEXT:    store i32 10, i32* [[I40]], align 4
15933 // CHECK12-NEXT:    store i32 0, i32* [[DOTOMP_LB55]], align 4
15934 // CHECK12-NEXT:    store i32 9, i32* [[DOTOMP_UB56]], align 4
15935 // CHECK12-NEXT:    [[TMP31:%.*]] = load i32, i32* [[DOTOMP_LB55]], align 4
15936 // CHECK12-NEXT:    store i32 [[TMP31]], i32* [[DOTOMP_IV57]], align 4
15937 // CHECK12-NEXT:    [[ARRAYDECAY:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 0
15938 // CHECK12-NEXT:    call void @llvm.assume(i1 true) [ "align"(float* [[ARRAYDECAY]], i32 16) ]
15939 // CHECK12-NEXT:    br label [[OMP_INNER_FOR_COND59:%.*]]
15940 // CHECK12:       omp.inner.for.cond59:
15941 // CHECK12-NEXT:    [[TMP32:%.*]] = load i32, i32* [[DOTOMP_IV57]], align 4, !llvm.access.group !16
15942 // CHECK12-NEXT:    [[TMP33:%.*]] = load i32, i32* [[DOTOMP_UB56]], align 4, !llvm.access.group !16
15943 // CHECK12-NEXT:    [[CMP60:%.*]] = icmp sle i32 [[TMP32]], [[TMP33]]
15944 // CHECK12-NEXT:    br i1 [[CMP60]], label [[OMP_INNER_FOR_BODY61:%.*]], label [[OMP_INNER_FOR_END85:%.*]]
15945 // CHECK12:       omp.inner.for.body61:
15946 // CHECK12-NEXT:    [[TMP34:%.*]] = load i32, i32* [[DOTOMP_IV57]], align 4, !llvm.access.group !16
15947 // CHECK12-NEXT:    [[MUL62:%.*]] = mul nsw i32 [[TMP34]], 1
15948 // CHECK12-NEXT:    [[ADD63:%.*]] = add nsw i32 0, [[MUL62]]
15949 // CHECK12-NEXT:    store i32 [[ADD63]], i32* [[I58]], align 4, !llvm.access.group !16
15950 // CHECK12-NEXT:    [[TMP35:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !16
15951 // CHECK12-NEXT:    [[ADD64:%.*]] = add nsw i32 [[TMP35]], 1
15952 // CHECK12-NEXT:    store i32 [[ADD64]], i32* [[A]], align 4, !llvm.access.group !16
15953 // CHECK12-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2
15954 // CHECK12-NEXT:    [[TMP36:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !16
15955 // CHECK12-NEXT:    [[CONV65:%.*]] = fpext float [[TMP36]] to double
15956 // CHECK12-NEXT:    [[ADD66:%.*]] = fadd double [[CONV65]], 1.000000e+00
15957 // CHECK12-NEXT:    [[CONV67:%.*]] = fptrunc double [[ADD66]] to float
15958 // CHECK12-NEXT:    store float [[CONV67]], float* [[ARRAYIDX]], align 4, !llvm.access.group !16
15959 // CHECK12-NEXT:    [[ARRAYIDX68:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3
15960 // CHECK12-NEXT:    [[TMP37:%.*]] = load float, float* [[ARRAYIDX68]], align 4, !llvm.access.group !16
15961 // CHECK12-NEXT:    [[CONV69:%.*]] = fpext float [[TMP37]] to double
15962 // CHECK12-NEXT:    [[ADD70:%.*]] = fadd double [[CONV69]], 1.000000e+00
15963 // CHECK12-NEXT:    [[CONV71:%.*]] = fptrunc double [[ADD70]] to float
15964 // CHECK12-NEXT:    store float [[CONV71]], float* [[ARRAYIDX68]], align 4, !llvm.access.group !16
15965 // CHECK12-NEXT:    [[ARRAYIDX72:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1
15966 // CHECK12-NEXT:    [[ARRAYIDX73:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX72]], i32 0, i32 2
15967 // CHECK12-NEXT:    [[TMP38:%.*]] = load double, double* [[ARRAYIDX73]], align 8, !llvm.access.group !16
15968 // CHECK12-NEXT:    [[ADD74:%.*]] = fadd double [[TMP38]], 1.000000e+00
15969 // CHECK12-NEXT:    store double [[ADD74]], double* [[ARRAYIDX73]], align 8, !llvm.access.group !16
15970 // CHECK12-NEXT:    [[TMP39:%.*]] = mul nsw i32 1, [[TMP2]]
15971 // CHECK12-NEXT:    [[ARRAYIDX75:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP39]]
15972 // CHECK12-NEXT:    [[ARRAYIDX76:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX75]], i32 3
15973 // CHECK12-NEXT:    [[TMP40:%.*]] = load double, double* [[ARRAYIDX76]], align 8, !llvm.access.group !16
15974 // CHECK12-NEXT:    [[ADD77:%.*]] = fadd double [[TMP40]], 1.000000e+00
15975 // CHECK12-NEXT:    store double [[ADD77]], double* [[ARRAYIDX76]], align 8, !llvm.access.group !16
15976 // CHECK12-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0
15977 // CHECK12-NEXT:    [[TMP41:%.*]] = load i64, i64* [[X]], align 4, !llvm.access.group !16
15978 // CHECK12-NEXT:    [[ADD78:%.*]] = add nsw i64 [[TMP41]], 1
15979 // CHECK12-NEXT:    store i64 [[ADD78]], i64* [[X]], align 4, !llvm.access.group !16
15980 // CHECK12-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1
15981 // CHECK12-NEXT:    [[TMP42:%.*]] = load i8, i8* [[Y]], align 4, !llvm.access.group !16
15982 // CHECK12-NEXT:    [[CONV79:%.*]] = sext i8 [[TMP42]] to i32
15983 // CHECK12-NEXT:    [[ADD80:%.*]] = add nsw i32 [[CONV79]], 1
15984 // CHECK12-NEXT:    [[CONV81:%.*]] = trunc i32 [[ADD80]] to i8
15985 // CHECK12-NEXT:    store i8 [[CONV81]], i8* [[Y]], align 4, !llvm.access.group !16
15986 // CHECK12-NEXT:    br label [[OMP_BODY_CONTINUE82:%.*]]
15987 // CHECK12:       omp.body.continue82:
15988 // CHECK12-NEXT:    br label [[OMP_INNER_FOR_INC83:%.*]]
15989 // CHECK12:       omp.inner.for.inc83:
15990 // CHECK12-NEXT:    [[TMP43:%.*]] = load i32, i32* [[DOTOMP_IV57]], align 4, !llvm.access.group !16
15991 // CHECK12-NEXT:    [[ADD84:%.*]] = add nsw i32 [[TMP43]], 1
15992 // CHECK12-NEXT:    store i32 [[ADD84]], i32* [[DOTOMP_IV57]], align 4, !llvm.access.group !16
15993 // CHECK12-NEXT:    br label [[OMP_INNER_FOR_COND59]], !llvm.loop [[LOOP17:![0-9]+]]
15994 // CHECK12:       omp.inner.for.end85:
15995 // CHECK12-NEXT:    store i32 10, i32* [[I58]], align 4
15996 // CHECK12-NEXT:    [[TMP44:%.*]] = load i32, i32* [[A]], align 4
15997 // CHECK12-NEXT:    [[TMP45:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
15998 // CHECK12-NEXT:    call void @llvm.stackrestore(i8* [[TMP45]])
15999 // CHECK12-NEXT:    ret i32 [[TMP44]]
16000 //
16001 //
16002 // CHECK12-LABEL: define {{[^@]+}}@_Z3bari
16003 // CHECK12-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {
16004 // CHECK12-NEXT:  entry:
16005 // CHECK12-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
16006 // CHECK12-NEXT:    [[A:%.*]] = alloca i32, align 4
16007 // CHECK12-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4
16008 // CHECK12-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
16009 // CHECK12-NEXT:    store i32 0, i32* [[A]], align 4
16010 // CHECK12-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
16011 // CHECK12-NEXT:    [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]])
16012 // CHECK12-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
16013 // CHECK12-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
16014 // CHECK12-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
16015 // CHECK12-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
16016 // CHECK12-NEXT:    [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP2]])
16017 // CHECK12-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
16018 // CHECK12-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
16019 // CHECK12-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
16020 // CHECK12-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
16021 // CHECK12-NEXT:    [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]])
16022 // CHECK12-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
16023 // CHECK12-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
16024 // CHECK12-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
16025 // CHECK12-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
16026 // CHECK12-NEXT:    [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]])
16027 // CHECK12-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
16028 // CHECK12-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
16029 // CHECK12-NEXT:    store i32 [[ADD6]], i32* [[A]], align 4
16030 // CHECK12-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
16031 // CHECK12-NEXT:    ret i32 [[TMP8]]
16032 //
16033 //
16034 // CHECK12-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
16035 // CHECK12-SAME: (%struct.S1* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 {
16036 // CHECK12-NEXT:  entry:
16037 // CHECK12-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
16038 // CHECK12-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
16039 // CHECK12-NEXT:    [[B:%.*]] = alloca i32, align 4
16040 // CHECK12-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 4
16041 // CHECK12-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 4
16042 // CHECK12-NEXT:    [[TMP:%.*]] = alloca i32, align 4
16043 // CHECK12-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
16044 // CHECK12-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
16045 // CHECK12-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
16046 // CHECK12-NEXT:    [[I:%.*]] = alloca i32, align 4
16047 // CHECK12-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
16048 // CHECK12-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
16049 // CHECK12-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
16050 // CHECK12-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
16051 // CHECK12-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
16052 // CHECK12-NEXT:    store i32 [[ADD]], i32* [[B]], align 4
16053 // CHECK12-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
16054 // CHECK12-NEXT:    [[TMP2:%.*]] = call i8* @llvm.stacksave()
16055 // CHECK12-NEXT:    store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4
16056 // CHECK12-NEXT:    [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]
16057 // CHECK12-NEXT:    [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2
16058 // CHECK12-NEXT:    store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
16059 // CHECK12-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
16060 // CHECK12-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
16061 // CHECK12-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
16062 // CHECK12-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
16063 // CHECK12-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
16064 // CHECK12:       omp.inner.for.cond:
16065 // CHECK12-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
16066 // CHECK12-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !19
16067 // CHECK12-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
16068 // CHECK12-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
16069 // CHECK12:       omp.inner.for.body:
16070 // CHECK12-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
16071 // CHECK12-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
16072 // CHECK12-NEXT:    [[ADD2:%.*]] = add nsw i32 0, [[MUL]]
16073 // CHECK12-NEXT:    store i32 [[ADD2]], i32* [[I]], align 4, !llvm.access.group !19
16074 // CHECK12-NEXT:    [[TMP8:%.*]] = load i32, i32* [[B]], align 4, !llvm.access.group !19
16075 // CHECK12-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP8]] to double
16076 // CHECK12-NEXT:    [[ADD3:%.*]] = fadd double [[CONV]], 1.500000e+00
16077 // CHECK12-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
16078 // CHECK12-NEXT:    store double [[ADD3]], double* [[A]], align 4, !llvm.access.group !19
16079 // CHECK12-NEXT:    [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
16080 // CHECK12-NEXT:    [[TMP9:%.*]] = load double, double* [[A4]], align 4, !llvm.access.group !19
16081 // CHECK12-NEXT:    [[INC:%.*]] = fadd double [[TMP9]], 1.000000e+00
16082 // CHECK12-NEXT:    store double [[INC]], double* [[A4]], align 4, !llvm.access.group !19
16083 // CHECK12-NEXT:    [[CONV5:%.*]] = fptosi double [[INC]] to i16
16084 // CHECK12-NEXT:    [[TMP10:%.*]] = mul nsw i32 1, [[TMP1]]
16085 // CHECK12-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP10]]
16086 // CHECK12-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
16087 // CHECK12-NEXT:    store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2, !llvm.access.group !19
16088 // CHECK12-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
16089 // CHECK12:       omp.body.continue:
16090 // CHECK12-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
16091 // CHECK12:       omp.inner.for.inc:
16092 // CHECK12-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
16093 // CHECK12-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1
16094 // CHECK12-NEXT:    store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
16095 // CHECK12-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]]
16096 // CHECK12:       omp.inner.for.end:
16097 // CHECK12-NEXT:    store i32 10, i32* [[I]], align 4
16098 // CHECK12-NEXT:    [[TMP12:%.*]] = mul nsw i32 1, [[TMP1]]
16099 // CHECK12-NEXT:    [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP12]]
16100 // CHECK12-NEXT:    [[ARRAYIDX9:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX8]], i32 1
16101 // CHECK12-NEXT:    [[TMP13:%.*]] = load i16, i16* [[ARRAYIDX9]], align 2
16102 // CHECK12-NEXT:    [[CONV10:%.*]] = sext i16 [[TMP13]] to i32
16103 // CHECK12-NEXT:    [[TMP14:%.*]] = load i32, i32* [[B]], align 4
16104 // CHECK12-NEXT:    [[ADD11:%.*]] = add nsw i32 [[CONV10]], [[TMP14]]
16105 // CHECK12-NEXT:    [[TMP15:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
16106 // CHECK12-NEXT:    call void @llvm.stackrestore(i8* [[TMP15]])
16107 // CHECK12-NEXT:    ret i32 [[ADD11]]
16108 //
16109 //
16110 // CHECK12-LABEL: define {{[^@]+}}@_ZL7fstatici
16111 // CHECK12-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {
16112 // CHECK12-NEXT:  entry:
16113 // CHECK12-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
16114 // CHECK12-NEXT:    [[A:%.*]] = alloca i32, align 4
16115 // CHECK12-NEXT:    [[AA:%.*]] = alloca i16, align 2
16116 // CHECK12-NEXT:    [[AAA:%.*]] = alloca i8, align 1
16117 // CHECK12-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
16118 // CHECK12-NEXT:    [[TMP:%.*]] = alloca i32, align 4
16119 // CHECK12-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
16120 // CHECK12-NEXT:    [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
16121 // CHECK12-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
16122 // CHECK12-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
16123 // CHECK12-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
16124 // CHECK12-NEXT:    [[I:%.*]] = alloca i32, align 4
16125 // CHECK12-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
16126 // CHECK12-NEXT:    [[I5:%.*]] = alloca i32, align 4
16127 // CHECK12-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
16128 // CHECK12-NEXT:    store i32 0, i32* [[A]], align 4
16129 // CHECK12-NEXT:    store i16 0, i16* [[AA]], align 2
16130 // CHECK12-NEXT:    store i8 0, i8* [[AAA]], align 1
16131 // CHECK12-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
16132 // CHECK12-NEXT:    store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4
16133 // CHECK12-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
16134 // CHECK12-NEXT:    store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_1]], align 4
16135 // CHECK12-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
16136 // CHECK12-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
16137 // CHECK12-NEXT:    [[SUB:%.*]] = sub i32 [[TMP2]], [[TMP3]]
16138 // CHECK12-NEXT:    [[SUB3:%.*]] = sub i32 [[SUB]], 1
16139 // CHECK12-NEXT:    [[ADD:%.*]] = add i32 [[SUB3]], 1
16140 // CHECK12-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], 1
16141 // CHECK12-NEXT:    [[SUB4:%.*]] = sub i32 [[DIV]], 1
16142 // CHECK12-NEXT:    store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_2]], align 4
16143 // CHECK12-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
16144 // CHECK12-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
16145 // CHECK12-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_UB]], align 4
16146 // CHECK12-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
16147 // CHECK12-NEXT:    store i32 [[TMP5]], i32* [[I]], align 4
16148 // CHECK12-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
16149 // CHECK12-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
16150 // CHECK12-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]]
16151 // CHECK12-NEXT:    br i1 [[CMP]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END:%.*]]
16152 // CHECK12:       simd.if.then:
16153 // CHECK12-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
16154 // CHECK12-NEXT:    store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
16155 // CHECK12-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
16156 // CHECK12:       omp.inner.for.cond:
16157 // CHECK12-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
16158 // CHECK12-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !22
16159 // CHECK12-NEXT:    [[ADD6:%.*]] = add i32 [[TMP10]], 1
16160 // CHECK12-NEXT:    [[CMP7:%.*]] = icmp ult i32 [[TMP9]], [[ADD6]]
16161 // CHECK12-NEXT:    br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
16162 // CHECK12:       omp.inner.for.body:
16163 // CHECK12-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group !22
16164 // CHECK12-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
16165 // CHECK12-NEXT:    [[MUL:%.*]] = mul i32 [[TMP12]], 1
16166 // CHECK12-NEXT:    [[ADD8:%.*]] = add i32 [[TMP11]], [[MUL]]
16167 // CHECK12-NEXT:    store i32 [[ADD8]], i32* [[I5]], align 4, !llvm.access.group !22
16168 // CHECK12-NEXT:    [[TMP13:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !22
16169 // CHECK12-NEXT:    [[ADD9:%.*]] = add nsw i32 [[TMP13]], 1
16170 // CHECK12-NEXT:    store i32 [[ADD9]], i32* [[A]], align 4, !llvm.access.group !22
16171 // CHECK12-NEXT:    [[TMP14:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !22
16172 // CHECK12-NEXT:    [[CONV:%.*]] = sext i16 [[TMP14]] to i32
16173 // CHECK12-NEXT:    [[ADD10:%.*]] = add nsw i32 [[CONV]], 1
16174 // CHECK12-NEXT:    [[CONV11:%.*]] = trunc i32 [[ADD10]] to i16
16175 // CHECK12-NEXT:    store i16 [[CONV11]], i16* [[AA]], align 2, !llvm.access.group !22
16176 // CHECK12-NEXT:    [[TMP15:%.*]] = load i8, i8* [[AAA]], align 1, !llvm.access.group !22
16177 // CHECK12-NEXT:    [[CONV12:%.*]] = sext i8 [[TMP15]] to i32
16178 // CHECK12-NEXT:    [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1
16179 // CHECK12-NEXT:    [[CONV14:%.*]] = trunc i32 [[ADD13]] to i8
16180 // CHECK12-NEXT:    store i8 [[CONV14]], i8* [[AAA]], align 1, !llvm.access.group !22
16181 // CHECK12-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2
16182 // CHECK12-NEXT:    [[TMP16:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !22
16183 // CHECK12-NEXT:    [[ADD15:%.*]] = add nsw i32 [[TMP16]], 1
16184 // CHECK12-NEXT:    store i32 [[ADD15]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !22
16185 // CHECK12-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
16186 // CHECK12:       omp.body.continue:
16187 // CHECK12-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
16188 // CHECK12:       omp.inner.for.inc:
16189 // CHECK12-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
16190 // CHECK12-NEXT:    [[ADD16:%.*]] = add i32 [[TMP17]], 1
16191 // CHECK12-NEXT:    store i32 [[ADD16]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
16192 // CHECK12-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]]
16193 // CHECK12:       omp.inner.for.end:
16194 // CHECK12-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
16195 // CHECK12-NEXT:    [[TMP19:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
16196 // CHECK12-NEXT:    [[TMP20:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
16197 // CHECK12-NEXT:    [[SUB17:%.*]] = sub i32 [[TMP19]], [[TMP20]]
16198 // CHECK12-NEXT:    [[SUB18:%.*]] = sub i32 [[SUB17]], 1
16199 // CHECK12-NEXT:    [[ADD19:%.*]] = add i32 [[SUB18]], 1
16200 // CHECK12-NEXT:    [[DIV20:%.*]] = udiv i32 [[ADD19]], 1
16201 // CHECK12-NEXT:    [[MUL21:%.*]] = mul i32 [[DIV20]], 1
16202 // CHECK12-NEXT:    [[ADD22:%.*]] = add i32 [[TMP18]], [[MUL21]]
16203 // CHECK12-NEXT:    store i32 [[ADD22]], i32* [[I5]], align 4
16204 // CHECK12-NEXT:    br label [[SIMD_IF_END]]
16205 // CHECK12:       simd.if.end:
16206 // CHECK12-NEXT:    [[TMP21:%.*]] = load i32, i32* [[A]], align 4
16207 // CHECK12-NEXT:    ret i32 [[TMP21]]
16208 //
16209 //
16210 // CHECK12-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
16211 // CHECK12-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat {
16212 // CHECK12-NEXT:  entry:
16213 // CHECK12-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
16214 // CHECK12-NEXT:    [[A:%.*]] = alloca i32, align 4
16215 // CHECK12-NEXT:    [[AA:%.*]] = alloca i16, align 2
16216 // CHECK12-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
16217 // CHECK12-NEXT:    [[TMP:%.*]] = alloca i32, align 4
16218 // CHECK12-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
16219 // CHECK12-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
16220 // CHECK12-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
16221 // CHECK12-NEXT:    [[I:%.*]] = alloca i32, align 4
16222 // CHECK12-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
16223 // CHECK12-NEXT:    store i32 0, i32* [[A]], align 4
16224 // CHECK12-NEXT:    store i16 0, i16* [[AA]], align 2
16225 // CHECK12-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
16226 // CHECK12-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
16227 // CHECK12-NEXT:    [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
16228 // CHECK12-NEXT:    store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4
16229 // CHECK12-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
16230 // CHECK12:       omp.inner.for.cond:
16231 // CHECK12-NEXT:    [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25
16232 // CHECK12-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !25
16233 // CHECK12-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
16234 // CHECK12-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
16235 // CHECK12:       omp.inner.for.body:
16236 // CHECK12-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25
16237 // CHECK12-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1
16238 // CHECK12-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
16239 // CHECK12-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !25
16240 // CHECK12-NEXT:    [[TMP4:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !25
16241 // CHECK12-NEXT:    [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1
16242 // CHECK12-NEXT:    store i32 [[ADD1]], i32* [[A]], align 4, !llvm.access.group !25
16243 // CHECK12-NEXT:    [[TMP5:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !25
16244 // CHECK12-NEXT:    [[CONV:%.*]] = sext i16 [[TMP5]] to i32
16245 // CHECK12-NEXT:    [[ADD2:%.*]] = add nsw i32 [[CONV]], 1
16246 // CHECK12-NEXT:    [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
16247 // CHECK12-NEXT:    store i16 [[CONV3]], i16* [[AA]], align 2, !llvm.access.group !25
16248 // CHECK12-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2
16249 // CHECK12-NEXT:    [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !25
16250 // CHECK12-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP6]], 1
16251 // CHECK12-NEXT:    store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !25
16252 // CHECK12-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
16253 // CHECK12:       omp.body.continue:
16254 // CHECK12-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
16255 // CHECK12:       omp.inner.for.inc:
16256 // CHECK12-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25
16257 // CHECK12-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP7]], 1
16258 // CHECK12-NEXT:    store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25
16259 // CHECK12-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP26:![0-9]+]]
16260 // CHECK12:       omp.inner.for.end:
16261 // CHECK12-NEXT:    store i32 10, i32* [[I]], align 4
16262 // CHECK12-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
16263 // CHECK12-NEXT:    ret i32 [[TMP8]]
16264 //
16265 //
16266 // CHECK13-LABEL: define {{[^@]+}}@_Z3fooi
16267 // CHECK13-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0:[0-9]+]] {
16268 // CHECK13-NEXT:  entry:
16269 // CHECK13-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
16270 // CHECK13-NEXT:    [[A:%.*]] = alloca i32, align 4
16271 // CHECK13-NEXT:    [[AA:%.*]] = alloca i16, align 2
16272 // CHECK13-NEXT:    [[B:%.*]] = alloca [10 x float], align 4
16273 // CHECK13-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 8
16274 // CHECK13-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
16275 // CHECK13-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 8
16276 // CHECK13-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i64, align 8
16277 // CHECK13-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8
16278 // CHECK13-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
16279 // CHECK13-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
16280 // CHECK13-NEXT:    [[TMP:%.*]] = alloca i32, align 4
16281 // CHECK13-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
16282 // CHECK13-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
16283 // CHECK13-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
16284 // CHECK13-NEXT:    [[I:%.*]] = alloca i32, align 4
16285 // CHECK13-NEXT:    [[_TMP4:%.*]] = alloca i32, align 4
16286 // CHECK13-NEXT:    [[DOTOMP_LB5:%.*]] = alloca i32, align 4
16287 // CHECK13-NEXT:    [[DOTOMP_UB6:%.*]] = alloca i32, align 4
16288 // CHECK13-NEXT:    [[DOTOMP_IV7:%.*]] = alloca i32, align 4
16289 // CHECK13-NEXT:    [[DOTLINEAR_START:%.*]] = alloca i32, align 4
16290 // CHECK13-NEXT:    [[A8:%.*]] = alloca i32, align 4
16291 // CHECK13-NEXT:    [[A9:%.*]] = alloca i32, align 4
16292 // CHECK13-NEXT:    [[_TMP20:%.*]] = alloca i32, align 4
16293 // CHECK13-NEXT:    [[DOTOMP_LB21:%.*]] = alloca i32, align 4
16294 // CHECK13-NEXT:    [[DOTOMP_UB22:%.*]] = alloca i32, align 4
16295 // CHECK13-NEXT:    [[DOTOMP_IV23:%.*]] = alloca i32, align 4
16296 // CHECK13-NEXT:    [[I24:%.*]] = alloca i32, align 4
16297 // CHECK13-NEXT:    [[_TMP36:%.*]] = alloca i32, align 4
16298 // CHECK13-NEXT:    [[DOTOMP_LB37:%.*]] = alloca i32, align 4
16299 // CHECK13-NEXT:    [[DOTOMP_UB38:%.*]] = alloca i32, align 4
16300 // CHECK13-NEXT:    [[DOTOMP_IV39:%.*]] = alloca i32, align 4
16301 // CHECK13-NEXT:    [[I40:%.*]] = alloca i32, align 4
16302 // CHECK13-NEXT:    [[_TMP54:%.*]] = alloca i32, align 4
16303 // CHECK13-NEXT:    [[DOTOMP_LB55:%.*]] = alloca i32, align 4
16304 // CHECK13-NEXT:    [[DOTOMP_UB56:%.*]] = alloca i32, align 4
16305 // CHECK13-NEXT:    [[DOTOMP_IV57:%.*]] = alloca i32, align 4
16306 // CHECK13-NEXT:    [[I58:%.*]] = alloca i32, align 4
16307 // CHECK13-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
16308 // CHECK13-NEXT:    store i32 0, i32* [[A]], align 4
16309 // CHECK13-NEXT:    store i16 0, i16* [[AA]], align 2
16310 // CHECK13-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
16311 // CHECK13-NEXT:    [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
16312 // CHECK13-NEXT:    [[TMP2:%.*]] = call i8* @llvm.stacksave()
16313 // CHECK13-NEXT:    store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8
16314 // CHECK13-NEXT:    [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4
16315 // CHECK13-NEXT:    store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8
16316 // CHECK13-NEXT:    [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
16317 // CHECK13-NEXT:    [[TMP4:%.*]] = zext i32 [[TMP3]] to i64
16318 // CHECK13-NEXT:    [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]]
16319 // CHECK13-NEXT:    [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8
16320 // CHECK13-NEXT:    store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8
16321 // CHECK13-NEXT:    [[TMP6:%.*]] = load i32, i32* [[A]], align 4
16322 // CHECK13-NEXT:    store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_]], align 4
16323 // CHECK13-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
16324 // CHECK13-NEXT:    store i32 [[TMP7]], i32* [[DOTCAPTURE_EXPR_2]], align 4
16325 // CHECK13-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
16326 // CHECK13-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
16327 // CHECK13-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
16328 // CHECK13-NEXT:    store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
16329 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
16330 // CHECK13:       omp.inner.for.cond:
16331 // CHECK13-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
16332 // CHECK13-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !2
16333 // CHECK13-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
16334 // CHECK13-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
16335 // CHECK13:       omp.inner.for.body:
16336 // CHECK13-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
16337 // CHECK13-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
16338 // CHECK13-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
16339 // CHECK13-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !2
16340 // CHECK13-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
16341 // CHECK13:       omp.body.continue:
16342 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
16343 // CHECK13:       omp.inner.for.inc:
16344 // CHECK13-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
16345 // CHECK13-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1
16346 // CHECK13-NEXT:    store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
16347 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]
16348 // CHECK13:       omp.inner.for.end:
16349 // CHECK13-NEXT:    store i32 10, i32* [[I]], align 4
16350 // CHECK13-NEXT:    store i32 0, i32* [[DOTOMP_LB5]], align 4
16351 // CHECK13-NEXT:    store i32 9, i32* [[DOTOMP_UB6]], align 4
16352 // CHECK13-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB5]], align 4
16353 // CHECK13-NEXT:    store i32 [[TMP13]], i32* [[DOTOMP_IV7]], align 4
16354 // CHECK13-NEXT:    [[TMP14:%.*]] = load i32, i32* [[A]], align 4
16355 // CHECK13-NEXT:    store i32 [[TMP14]], i32* [[DOTLINEAR_START]], align 4
16356 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_COND10:%.*]]
16357 // CHECK13:       omp.inner.for.cond10:
16358 // CHECK13-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV7]], align 4
16359 // CHECK13-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB6]], align 4
16360 // CHECK13-NEXT:    [[CMP11:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]]
16361 // CHECK13-NEXT:    br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY12:%.*]], label [[OMP_INNER_FOR_END19:%.*]]
16362 // CHECK13:       omp.inner.for.body12:
16363 // CHECK13-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV7]], align 4
16364 // CHECK13-NEXT:    [[MUL13:%.*]] = mul nsw i32 [[TMP17]], 1
16365 // CHECK13-NEXT:    [[ADD14:%.*]] = add nsw i32 0, [[MUL13]]
16366 // CHECK13-NEXT:    store i32 [[ADD14]], i32* [[A8]], align 4, !nontemporal !7
16367 // CHECK13-NEXT:    [[TMP18:%.*]] = load i32, i32* [[A8]], align 4, !nontemporal !7
16368 // CHECK13-NEXT:    [[ADD15:%.*]] = add nsw i32 [[TMP18]], 1
16369 // CHECK13-NEXT:    store i32 [[ADD15]], i32* [[A8]], align 4, !nontemporal !7
16370 // CHECK13-NEXT:    br label [[OMP_BODY_CONTINUE16:%.*]]
16371 // CHECK13:       omp.body.continue16:
16372 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_INC17:%.*]]
16373 // CHECK13:       omp.inner.for.inc17:
16374 // CHECK13-NEXT:    [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV7]], align 4
16375 // CHECK13-NEXT:    [[ADD18:%.*]] = add nsw i32 [[TMP19]], 1
16376 // CHECK13-NEXT:    store i32 [[ADD18]], i32* [[DOTOMP_IV7]], align 4
16377 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_COND10]], !llvm.loop [[LOOP8:![0-9]+]]
16378 // CHECK13:       omp.inner.for.end19:
16379 // CHECK13-NEXT:    store i32 10, i32* [[A]], align 4
16380 // CHECK13-NEXT:    store i32 0, i32* [[DOTOMP_LB21]], align 4
16381 // CHECK13-NEXT:    store i32 9, i32* [[DOTOMP_UB22]], align 4
16382 // CHECK13-NEXT:    [[TMP20:%.*]] = load i32, i32* [[DOTOMP_LB21]], align 4
16383 // CHECK13-NEXT:    store i32 [[TMP20]], i32* [[DOTOMP_IV23]], align 4
16384 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_COND25:%.*]]
16385 // CHECK13:       omp.inner.for.cond25:
16386 // CHECK13-NEXT:    [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV23]], align 4, !llvm.access.group !10
16387 // CHECK13-NEXT:    [[TMP22:%.*]] = load i32, i32* [[DOTOMP_UB22]], align 4, !llvm.access.group !10
16388 // CHECK13-NEXT:    [[CMP26:%.*]] = icmp sle i32 [[TMP21]], [[TMP22]]
16389 // CHECK13-NEXT:    br i1 [[CMP26]], label [[OMP_INNER_FOR_BODY27:%.*]], label [[OMP_INNER_FOR_END35:%.*]]
16390 // CHECK13:       omp.inner.for.body27:
16391 // CHECK13-NEXT:    [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV23]], align 4, !llvm.access.group !10
16392 // CHECK13-NEXT:    [[MUL28:%.*]] = mul nsw i32 [[TMP23]], 1
16393 // CHECK13-NEXT:    [[ADD29:%.*]] = add nsw i32 0, [[MUL28]]
16394 // CHECK13-NEXT:    store i32 [[ADD29]], i32* [[I24]], align 4, !llvm.access.group !10
16395 // CHECK13-NEXT:    [[TMP24:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !10
16396 // CHECK13-NEXT:    [[CONV:%.*]] = sext i16 [[TMP24]] to i32
16397 // CHECK13-NEXT:    [[ADD30:%.*]] = add nsw i32 [[CONV]], 1
16398 // CHECK13-NEXT:    [[CONV31:%.*]] = trunc i32 [[ADD30]] to i16
16399 // CHECK13-NEXT:    store i16 [[CONV31]], i16* [[AA]], align 2, !llvm.access.group !10
16400 // CHECK13-NEXT:    br label [[OMP_BODY_CONTINUE32:%.*]]
16401 // CHECK13:       omp.body.continue32:
16402 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_INC33:%.*]]
16403 // CHECK13:       omp.inner.for.inc33:
16404 // CHECK13-NEXT:    [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IV23]], align 4, !llvm.access.group !10
16405 // CHECK13-NEXT:    [[ADD34:%.*]] = add nsw i32 [[TMP25]], 1
16406 // CHECK13-NEXT:    store i32 [[ADD34]], i32* [[DOTOMP_IV23]], align 4, !llvm.access.group !10
16407 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_COND25]], !llvm.loop [[LOOP11:![0-9]+]]
16408 // CHECK13:       omp.inner.for.end35:
16409 // CHECK13-NEXT:    store i32 10, i32* [[I24]], align 4
16410 // CHECK13-NEXT:    store i32 0, i32* [[DOTOMP_LB37]], align 4
16411 // CHECK13-NEXT:    store i32 9, i32* [[DOTOMP_UB38]], align 4
16412 // CHECK13-NEXT:    [[TMP26:%.*]] = load i32, i32* [[DOTOMP_LB37]], align 4
16413 // CHECK13-NEXT:    store i32 [[TMP26]], i32* [[DOTOMP_IV39]], align 4
16414 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_COND41:%.*]]
16415 // CHECK13:       omp.inner.for.cond41:
16416 // CHECK13-NEXT:    [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV39]], align 4, !llvm.access.group !13
16417 // CHECK13-NEXT:    [[TMP28:%.*]] = load i32, i32* [[DOTOMP_UB38]], align 4, !llvm.access.group !13
16418 // CHECK13-NEXT:    [[CMP42:%.*]] = icmp sle i32 [[TMP27]], [[TMP28]]
16419 // CHECK13-NEXT:    br i1 [[CMP42]], label [[OMP_INNER_FOR_BODY43:%.*]], label [[OMP_INNER_FOR_END53:%.*]]
16420 // CHECK13:       omp.inner.for.body43:
16421 // CHECK13-NEXT:    [[TMP29:%.*]] = load i32, i32* [[DOTOMP_IV39]], align 4, !llvm.access.group !13
16422 // CHECK13-NEXT:    [[MUL44:%.*]] = mul nsw i32 [[TMP29]], 1
16423 // CHECK13-NEXT:    [[ADD45:%.*]] = add nsw i32 0, [[MUL44]]
16424 // CHECK13-NEXT:    store i32 [[ADD45]], i32* [[I40]], align 4, !llvm.access.group !13
16425 // CHECK13-NEXT:    [[TMP30:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !13
16426 // CHECK13-NEXT:    [[ADD46:%.*]] = add nsw i32 [[TMP30]], 1
16427 // CHECK13-NEXT:    store i32 [[ADD46]], i32* [[A]], align 4, !llvm.access.group !13
16428 // CHECK13-NEXT:    [[TMP31:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !13
16429 // CHECK13-NEXT:    [[CONV47:%.*]] = sext i16 [[TMP31]] to i32
16430 // CHECK13-NEXT:    [[ADD48:%.*]] = add nsw i32 [[CONV47]], 1
16431 // CHECK13-NEXT:    [[CONV49:%.*]] = trunc i32 [[ADD48]] to i16
16432 // CHECK13-NEXT:    store i16 [[CONV49]], i16* [[AA]], align 2, !llvm.access.group !13
16433 // CHECK13-NEXT:    br label [[OMP_BODY_CONTINUE50:%.*]]
16434 // CHECK13:       omp.body.continue50:
16435 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_INC51:%.*]]
16436 // CHECK13:       omp.inner.for.inc51:
16437 // CHECK13-NEXT:    [[TMP32:%.*]] = load i32, i32* [[DOTOMP_IV39]], align 4, !llvm.access.group !13
16438 // CHECK13-NEXT:    [[ADD52:%.*]] = add nsw i32 [[TMP32]], 1
16439 // CHECK13-NEXT:    store i32 [[ADD52]], i32* [[DOTOMP_IV39]], align 4, !llvm.access.group !13
16440 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_COND41]], !llvm.loop [[LOOP14:![0-9]+]]
16441 // CHECK13:       omp.inner.for.end53:
16442 // CHECK13-NEXT:    store i32 10, i32* [[I40]], align 4
16443 // CHECK13-NEXT:    store i32 0, i32* [[DOTOMP_LB55]], align 4
16444 // CHECK13-NEXT:    store i32 9, i32* [[DOTOMP_UB56]], align 4
16445 // CHECK13-NEXT:    [[TMP33:%.*]] = load i32, i32* [[DOTOMP_LB55]], align 4
16446 // CHECK13-NEXT:    store i32 [[TMP33]], i32* [[DOTOMP_IV57]], align 4
16447 // CHECK13-NEXT:    [[ARRAYDECAY:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 0
16448 // CHECK13-NEXT:    call void @llvm.assume(i1 true) [ "align"(float* [[ARRAYDECAY]], i64 16) ]
16449 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_COND59:%.*]]
16450 // CHECK13:       omp.inner.for.cond59:
16451 // CHECK13-NEXT:    [[TMP34:%.*]] = load i32, i32* [[DOTOMP_IV57]], align 4, !llvm.access.group !16
16452 // CHECK13-NEXT:    [[TMP35:%.*]] = load i32, i32* [[DOTOMP_UB56]], align 4, !llvm.access.group !16
16453 // CHECK13-NEXT:    [[CMP60:%.*]] = icmp sle i32 [[TMP34]], [[TMP35]]
16454 // CHECK13-NEXT:    br i1 [[CMP60]], label [[OMP_INNER_FOR_BODY61:%.*]], label [[OMP_INNER_FOR_END85:%.*]]
16455 // CHECK13:       omp.inner.for.body61:
16456 // CHECK13-NEXT:    [[TMP36:%.*]] = load i32, i32* [[DOTOMP_IV57]], align 4, !llvm.access.group !16
16457 // CHECK13-NEXT:    [[MUL62:%.*]] = mul nsw i32 [[TMP36]], 1
16458 // CHECK13-NEXT:    [[ADD63:%.*]] = add nsw i32 0, [[MUL62]]
16459 // CHECK13-NEXT:    store i32 [[ADD63]], i32* [[I58]], align 4, !llvm.access.group !16
16460 // CHECK13-NEXT:    [[TMP37:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !16
16461 // CHECK13-NEXT:    [[ADD64:%.*]] = add nsw i32 [[TMP37]], 1
16462 // CHECK13-NEXT:    store i32 [[ADD64]], i32* [[A]], align 4, !llvm.access.group !16
16463 // CHECK13-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2
16464 // CHECK13-NEXT:    [[TMP38:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !16
16465 // CHECK13-NEXT:    [[CONV65:%.*]] = fpext float [[TMP38]] to double
16466 // CHECK13-NEXT:    [[ADD66:%.*]] = fadd double [[CONV65]], 1.000000e+00
16467 // CHECK13-NEXT:    [[CONV67:%.*]] = fptrunc double [[ADD66]] to float
16468 // CHECK13-NEXT:    store float [[CONV67]], float* [[ARRAYIDX]], align 4, !llvm.access.group !16
16469 // CHECK13-NEXT:    [[ARRAYIDX68:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3
16470 // CHECK13-NEXT:    [[TMP39:%.*]] = load float, float* [[ARRAYIDX68]], align 4, !llvm.access.group !16
16471 // CHECK13-NEXT:    [[CONV69:%.*]] = fpext float [[TMP39]] to double
16472 // CHECK13-NEXT:    [[ADD70:%.*]] = fadd double [[CONV69]], 1.000000e+00
16473 // CHECK13-NEXT:    [[CONV71:%.*]] = fptrunc double [[ADD70]] to float
16474 // CHECK13-NEXT:    store float [[CONV71]], float* [[ARRAYIDX68]], align 4, !llvm.access.group !16
16475 // CHECK13-NEXT:    [[ARRAYIDX72:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1
16476 // CHECK13-NEXT:    [[ARRAYIDX73:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX72]], i64 0, i64 2
16477 // CHECK13-NEXT:    [[TMP40:%.*]] = load double, double* [[ARRAYIDX73]], align 8, !llvm.access.group !16
16478 // CHECK13-NEXT:    [[ADD74:%.*]] = fadd double [[TMP40]], 1.000000e+00
16479 // CHECK13-NEXT:    store double [[ADD74]], double* [[ARRAYIDX73]], align 8, !llvm.access.group !16
16480 // CHECK13-NEXT:    [[TMP41:%.*]] = mul nsw i64 1, [[TMP4]]
16481 // CHECK13-NEXT:    [[ARRAYIDX75:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP41]]
16482 // CHECK13-NEXT:    [[ARRAYIDX76:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX75]], i64 3
16483 // CHECK13-NEXT:    [[TMP42:%.*]] = load double, double* [[ARRAYIDX76]], align 8, !llvm.access.group !16
16484 // CHECK13-NEXT:    [[ADD77:%.*]] = fadd double [[TMP42]], 1.000000e+00
16485 // CHECK13-NEXT:    store double [[ADD77]], double* [[ARRAYIDX76]], align 8, !llvm.access.group !16
16486 // CHECK13-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0
16487 // CHECK13-NEXT:    [[TMP43:%.*]] = load i64, i64* [[X]], align 8, !llvm.access.group !16
16488 // CHECK13-NEXT:    [[ADD78:%.*]] = add nsw i64 [[TMP43]], 1
16489 // CHECK13-NEXT:    store i64 [[ADD78]], i64* [[X]], align 8, !llvm.access.group !16
16490 // CHECK13-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1
16491 // CHECK13-NEXT:    [[TMP44:%.*]] = load i8, i8* [[Y]], align 8, !llvm.access.group !16
16492 // CHECK13-NEXT:    [[CONV79:%.*]] = sext i8 [[TMP44]] to i32
16493 // CHECK13-NEXT:    [[ADD80:%.*]] = add nsw i32 [[CONV79]], 1
16494 // CHECK13-NEXT:    [[CONV81:%.*]] = trunc i32 [[ADD80]] to i8
16495 // CHECK13-NEXT:    store i8 [[CONV81]], i8* [[Y]], align 8, !llvm.access.group !16
16496 // CHECK13-NEXT:    br label [[OMP_BODY_CONTINUE82:%.*]]
16497 // CHECK13:       omp.body.continue82:
16498 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_INC83:%.*]]
16499 // CHECK13:       omp.inner.for.inc83:
16500 // CHECK13-NEXT:    [[TMP45:%.*]] = load i32, i32* [[DOTOMP_IV57]], align 4, !llvm.access.group !16
16501 // CHECK13-NEXT:    [[ADD84:%.*]] = add nsw i32 [[TMP45]], 1
16502 // CHECK13-NEXT:    store i32 [[ADD84]], i32* [[DOTOMP_IV57]], align 4, !llvm.access.group !16
16503 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_COND59]], !llvm.loop [[LOOP17:![0-9]+]]
16504 // CHECK13:       omp.inner.for.end85:
16505 // CHECK13-NEXT:    store i32 10, i32* [[I58]], align 4
16506 // CHECK13-NEXT:    [[TMP46:%.*]] = load i32, i32* [[A]], align 4
16507 // CHECK13-NEXT:    [[TMP47:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
16508 // CHECK13-NEXT:    call void @llvm.stackrestore(i8* [[TMP47]])
16509 // CHECK13-NEXT:    ret i32 [[TMP46]]
16510 //
16511 //
16512 // CHECK13-LABEL: define {{[^@]+}}@_Z3bari
16513 // CHECK13-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {
16514 // CHECK13-NEXT:  entry:
16515 // CHECK13-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
16516 // CHECK13-NEXT:    [[A:%.*]] = alloca i32, align 4
16517 // CHECK13-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8
16518 // CHECK13-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
16519 // CHECK13-NEXT:    store i32 0, i32* [[A]], align 4
16520 // CHECK13-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
16521 // CHECK13-NEXT:    [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]])
16522 // CHECK13-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
16523 // CHECK13-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
16524 // CHECK13-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
16525 // CHECK13-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
16526 // CHECK13-NEXT:    [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP2]])
16527 // CHECK13-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
16528 // CHECK13-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
16529 // CHECK13-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
16530 // CHECK13-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
16531 // CHECK13-NEXT:    [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]])
16532 // CHECK13-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
16533 // CHECK13-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
16534 // CHECK13-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
16535 // CHECK13-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
16536 // CHECK13-NEXT:    [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]])
16537 // CHECK13-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
16538 // CHECK13-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
16539 // CHECK13-NEXT:    store i32 [[ADD6]], i32* [[A]], align 4
16540 // CHECK13-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
16541 // CHECK13-NEXT:    ret i32 [[TMP8]]
16542 //
16543 //
16544 // CHECK13-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
16545 // CHECK13-SAME: (%struct.S1* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 {
16546 // CHECK13-NEXT:  entry:
16547 // CHECK13-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
16548 // CHECK13-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
16549 // CHECK13-NEXT:    [[B:%.*]] = alloca i32, align 4
16550 // CHECK13-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 8
16551 // CHECK13-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
16552 // CHECK13-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
16553 // CHECK13-NEXT:    [[TMP:%.*]] = alloca i32, align 4
16554 // CHECK13-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
16555 // CHECK13-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
16556 // CHECK13-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
16557 // CHECK13-NEXT:    [[I:%.*]] = alloca i32, align 4
16558 // CHECK13-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
16559 // CHECK13-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
16560 // CHECK13-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
16561 // CHECK13-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
16562 // CHECK13-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
16563 // CHECK13-NEXT:    store i32 [[ADD]], i32* [[B]], align 4
16564 // CHECK13-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
16565 // CHECK13-NEXT:    [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
16566 // CHECK13-NEXT:    [[TMP3:%.*]] = call i8* @llvm.stacksave()
16567 // CHECK13-NEXT:    store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8
16568 // CHECK13-NEXT:    [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]
16569 // CHECK13-NEXT:    [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2
16570 // CHECK13-NEXT:    store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8
16571 // CHECK13-NEXT:    [[TMP5:%.*]] = load i32, i32* [[N_ADDR]], align 4
16572 // CHECK13-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 60
16573 // CHECK13-NEXT:    [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8
16574 // CHECK13-NEXT:    store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
16575 // CHECK13-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
16576 // CHECK13-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
16577 // CHECK13-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
16578 // CHECK13-NEXT:    store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
16579 // CHECK13-NEXT:    [[TMP7:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
16580 // CHECK13-NEXT:    [[TOBOOL:%.*]] = trunc i8 [[TMP7]] to i1
16581 // CHECK13-NEXT:    br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
16582 // CHECK13:       omp_if.then:
16583 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
16584 // CHECK13:       omp.inner.for.cond:
16585 // CHECK13-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
16586 // CHECK13-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !19
16587 // CHECK13-NEXT:    [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
16588 // CHECK13-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
16589 // CHECK13:       omp.inner.for.body:
16590 // CHECK13-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
16591 // CHECK13-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
16592 // CHECK13-NEXT:    [[ADD3:%.*]] = add nsw i32 0, [[MUL]]
16593 // CHECK13-NEXT:    store i32 [[ADD3]], i32* [[I]], align 4, !llvm.access.group !19
16594 // CHECK13-NEXT:    [[TMP11:%.*]] = load i32, i32* [[B]], align 4, !llvm.access.group !19
16595 // CHECK13-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP11]] to double
16596 // CHECK13-NEXT:    [[ADD4:%.*]] = fadd double [[CONV]], 1.500000e+00
16597 // CHECK13-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
16598 // CHECK13-NEXT:    store double [[ADD4]], double* [[A]], align 8, !llvm.access.group !19
16599 // CHECK13-NEXT:    [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
16600 // CHECK13-NEXT:    [[TMP12:%.*]] = load double, double* [[A5]], align 8, !llvm.access.group !19
16601 // CHECK13-NEXT:    [[INC:%.*]] = fadd double [[TMP12]], 1.000000e+00
16602 // CHECK13-NEXT:    store double [[INC]], double* [[A5]], align 8, !llvm.access.group !19
16603 // CHECK13-NEXT:    [[CONV6:%.*]] = fptosi double [[INC]] to i16
16604 // CHECK13-NEXT:    [[TMP13:%.*]] = mul nsw i64 1, [[TMP2]]
16605 // CHECK13-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP13]]
16606 // CHECK13-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
16607 // CHECK13-NEXT:    store i16 [[CONV6]], i16* [[ARRAYIDX7]], align 2, !llvm.access.group !19
16608 // CHECK13-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
16609 // CHECK13:       omp.body.continue:
16610 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
16611 // CHECK13:       omp.inner.for.inc:
16612 // CHECK13-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
16613 // CHECK13-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP14]], 1
16614 // CHECK13-NEXT:    store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
16615 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]]
16616 // CHECK13:       omp.inner.for.end:
16617 // CHECK13-NEXT:    br label [[OMP_IF_END:%.*]]
16618 // CHECK13:       omp_if.else:
16619 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_COND9:%.*]]
16620 // CHECK13:       omp.inner.for.cond9:
16621 // CHECK13-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
16622 // CHECK13-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
16623 // CHECK13-NEXT:    [[CMP10:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]]
16624 // CHECK13-NEXT:    br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY11:%.*]], label [[OMP_INNER_FOR_END25:%.*]]
16625 // CHECK13:       omp.inner.for.body11:
16626 // CHECK13-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
16627 // CHECK13-NEXT:    [[MUL12:%.*]] = mul nsw i32 [[TMP17]], 1
16628 // CHECK13-NEXT:    [[ADD13:%.*]] = add nsw i32 0, [[MUL12]]
16629 // CHECK13-NEXT:    store i32 [[ADD13]], i32* [[I]], align 4
16630 // CHECK13-NEXT:    [[TMP18:%.*]] = load i32, i32* [[B]], align 4
16631 // CHECK13-NEXT:    [[CONV14:%.*]] = sitofp i32 [[TMP18]] to double
16632 // CHECK13-NEXT:    [[ADD15:%.*]] = fadd double [[CONV14]], 1.500000e+00
16633 // CHECK13-NEXT:    [[A16:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
16634 // CHECK13-NEXT:    store double [[ADD15]], double* [[A16]], align 8
16635 // CHECK13-NEXT:    [[A17:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
16636 // CHECK13-NEXT:    [[TMP19:%.*]] = load double, double* [[A17]], align 8
16637 // CHECK13-NEXT:    [[INC18:%.*]] = fadd double [[TMP19]], 1.000000e+00
16638 // CHECK13-NEXT:    store double [[INC18]], double* [[A17]], align 8
16639 // CHECK13-NEXT:    [[CONV19:%.*]] = fptosi double [[INC18]] to i16
16640 // CHECK13-NEXT:    [[TMP20:%.*]] = mul nsw i64 1, [[TMP2]]
16641 // CHECK13-NEXT:    [[ARRAYIDX20:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP20]]
16642 // CHECK13-NEXT:    [[ARRAYIDX21:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX20]], i64 1
16643 // CHECK13-NEXT:    store i16 [[CONV19]], i16* [[ARRAYIDX21]], align 2
16644 // CHECK13-NEXT:    br label [[OMP_BODY_CONTINUE22:%.*]]
16645 // CHECK13:       omp.body.continue22:
16646 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_INC23:%.*]]
16647 // CHECK13:       omp.inner.for.inc23:
16648 // CHECK13-NEXT:    [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
16649 // CHECK13-NEXT:    [[ADD24:%.*]] = add nsw i32 [[TMP21]], 1
16650 // CHECK13-NEXT:    store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4
16651 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_COND9]], !llvm.loop [[LOOP22:![0-9]+]]
16652 // CHECK13:       omp.inner.for.end25:
16653 // CHECK13-NEXT:    br label [[OMP_IF_END]]
16654 // CHECK13:       omp_if.end:
16655 // CHECK13-NEXT:    store i32 10, i32* [[I]], align 4
16656 // CHECK13-NEXT:    [[TMP22:%.*]] = mul nsw i64 1, [[TMP2]]
16657 // CHECK13-NEXT:    [[ARRAYIDX26:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP22]]
16658 // CHECK13-NEXT:    [[ARRAYIDX27:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX26]], i64 1
16659 // CHECK13-NEXT:    [[TMP23:%.*]] = load i16, i16* [[ARRAYIDX27]], align 2
16660 // CHECK13-NEXT:    [[CONV28:%.*]] = sext i16 [[TMP23]] to i32
16661 // CHECK13-NEXT:    [[TMP24:%.*]] = load i32, i32* [[B]], align 4
16662 // CHECK13-NEXT:    [[ADD29:%.*]] = add nsw i32 [[CONV28]], [[TMP24]]
16663 // CHECK13-NEXT:    [[TMP25:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
16664 // CHECK13-NEXT:    call void @llvm.stackrestore(i8* [[TMP25]])
16665 // CHECK13-NEXT:    ret i32 [[ADD29]]
16666 //
16667 //
16668 // CHECK13-LABEL: define {{[^@]+}}@_ZL7fstatici
16669 // CHECK13-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {
16670 // CHECK13-NEXT:  entry:
16671 // CHECK13-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
16672 // CHECK13-NEXT:    [[A:%.*]] = alloca i32, align 4
16673 // CHECK13-NEXT:    [[AA:%.*]] = alloca i16, align 2
16674 // CHECK13-NEXT:    [[AAA:%.*]] = alloca i8, align 1
16675 // CHECK13-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
16676 // CHECK13-NEXT:    [[TMP:%.*]] = alloca i32, align 4
16677 // CHECK13-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
16678 // CHECK13-NEXT:    [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
16679 // CHECK13-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
16680 // CHECK13-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
16681 // CHECK13-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
16682 // CHECK13-NEXT:    [[I:%.*]] = alloca i32, align 4
16683 // CHECK13-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
16684 // CHECK13-NEXT:    [[I5:%.*]] = alloca i32, align 4
16685 // CHECK13-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
16686 // CHECK13-NEXT:    store i32 0, i32* [[A]], align 4
16687 // CHECK13-NEXT:    store i16 0, i16* [[AA]], align 2
16688 // CHECK13-NEXT:    store i8 0, i8* [[AAA]], align 1
16689 // CHECK13-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
16690 // CHECK13-NEXT:    store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4
16691 // CHECK13-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
16692 // CHECK13-NEXT:    store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_1]], align 4
16693 // CHECK13-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
16694 // CHECK13-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
16695 // CHECK13-NEXT:    [[SUB:%.*]] = sub i32 [[TMP2]], [[TMP3]]
16696 // CHECK13-NEXT:    [[SUB3:%.*]] = sub i32 [[SUB]], 1
16697 // CHECK13-NEXT:    [[ADD:%.*]] = add i32 [[SUB3]], 1
16698 // CHECK13-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], 1
16699 // CHECK13-NEXT:    [[SUB4:%.*]] = sub i32 [[DIV]], 1
16700 // CHECK13-NEXT:    store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_2]], align 4
16701 // CHECK13-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
16702 // CHECK13-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
16703 // CHECK13-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_UB]], align 4
16704 // CHECK13-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
16705 // CHECK13-NEXT:    store i32 [[TMP5]], i32* [[I]], align 4
16706 // CHECK13-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
16707 // CHECK13-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
16708 // CHECK13-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]]
16709 // CHECK13-NEXT:    br i1 [[CMP]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END:%.*]]
16710 // CHECK13:       simd.if.then:
16711 // CHECK13-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
16712 // CHECK13-NEXT:    store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
16713 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
16714 // CHECK13:       omp.inner.for.cond:
16715 // CHECK13-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
16716 // CHECK13-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !24
16717 // CHECK13-NEXT:    [[ADD6:%.*]] = add i32 [[TMP10]], 1
16718 // CHECK13-NEXT:    [[CMP7:%.*]] = icmp ult i32 [[TMP9]], [[ADD6]]
16719 // CHECK13-NEXT:    br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
16720 // CHECK13:       omp.inner.for.body:
16721 // CHECK13-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group !24
16722 // CHECK13-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
16723 // CHECK13-NEXT:    [[MUL:%.*]] = mul i32 [[TMP12]], 1
16724 // CHECK13-NEXT:    [[ADD8:%.*]] = add i32 [[TMP11]], [[MUL]]
16725 // CHECK13-NEXT:    store i32 [[ADD8]], i32* [[I5]], align 4, !llvm.access.group !24
16726 // CHECK13-NEXT:    [[TMP13:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !24
16727 // CHECK13-NEXT:    [[ADD9:%.*]] = add nsw i32 [[TMP13]], 1
16728 // CHECK13-NEXT:    store i32 [[ADD9]], i32* [[A]], align 4, !llvm.access.group !24
16729 // CHECK13-NEXT:    [[TMP14:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !24
16730 // CHECK13-NEXT:    [[CONV:%.*]] = sext i16 [[TMP14]] to i32
16731 // CHECK13-NEXT:    [[ADD10:%.*]] = add nsw i32 [[CONV]], 1
16732 // CHECK13-NEXT:    [[CONV11:%.*]] = trunc i32 [[ADD10]] to i16
16733 // CHECK13-NEXT:    store i16 [[CONV11]], i16* [[AA]], align 2, !llvm.access.group !24
16734 // CHECK13-NEXT:    [[TMP15:%.*]] = load i8, i8* [[AAA]], align 1, !llvm.access.group !24
16735 // CHECK13-NEXT:    [[CONV12:%.*]] = sext i8 [[TMP15]] to i32
16736 // CHECK13-NEXT:    [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1
16737 // CHECK13-NEXT:    [[CONV14:%.*]] = trunc i32 [[ADD13]] to i8
16738 // CHECK13-NEXT:    store i8 [[CONV14]], i8* [[AAA]], align 1, !llvm.access.group !24
16739 // CHECK13-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2
16740 // CHECK13-NEXT:    [[TMP16:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !24
16741 // CHECK13-NEXT:    [[ADD15:%.*]] = add nsw i32 [[TMP16]], 1
16742 // CHECK13-NEXT:    store i32 [[ADD15]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !24
16743 // CHECK13-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
16744 // CHECK13:       omp.body.continue:
16745 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
16746 // CHECK13:       omp.inner.for.inc:
16747 // CHECK13-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
16748 // CHECK13-NEXT:    [[ADD16:%.*]] = add i32 [[TMP17]], 1
16749 // CHECK13-NEXT:    store i32 [[ADD16]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
16750 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]]
16751 // CHECK13:       omp.inner.for.end:
16752 // CHECK13-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
16753 // CHECK13-NEXT:    [[TMP19:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
16754 // CHECK13-NEXT:    [[TMP20:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
16755 // CHECK13-NEXT:    [[SUB17:%.*]] = sub i32 [[TMP19]], [[TMP20]]
16756 // CHECK13-NEXT:    [[SUB18:%.*]] = sub i32 [[SUB17]], 1
16757 // CHECK13-NEXT:    [[ADD19:%.*]] = add i32 [[SUB18]], 1
16758 // CHECK13-NEXT:    [[DIV20:%.*]] = udiv i32 [[ADD19]], 1
16759 // CHECK13-NEXT:    [[MUL21:%.*]] = mul i32 [[DIV20]], 1
16760 // CHECK13-NEXT:    [[ADD22:%.*]] = add i32 [[TMP18]], [[MUL21]]
16761 // CHECK13-NEXT:    store i32 [[ADD22]], i32* [[I5]], align 4
16762 // CHECK13-NEXT:    br label [[SIMD_IF_END]]
16763 // CHECK13:       simd.if.end:
16764 // CHECK13-NEXT:    [[TMP21:%.*]] = load i32, i32* [[A]], align 4
16765 // CHECK13-NEXT:    ret i32 [[TMP21]]
16766 //
16767 //
16768 // CHECK13-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
16769 // CHECK13-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat {
16770 // CHECK13-NEXT:  entry:
16771 // CHECK13-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
16772 // CHECK13-NEXT:    [[A:%.*]] = alloca i32, align 4
16773 // CHECK13-NEXT:    [[AA:%.*]] = alloca i16, align 2
16774 // CHECK13-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
16775 // CHECK13-NEXT:    [[TMP:%.*]] = alloca i32, align 4
16776 // CHECK13-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
16777 // CHECK13-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
16778 // CHECK13-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
16779 // CHECK13-NEXT:    [[I:%.*]] = alloca i32, align 4
16780 // CHECK13-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
16781 // CHECK13-NEXT:    store i32 0, i32* [[A]], align 4
16782 // CHECK13-NEXT:    store i16 0, i16* [[AA]], align 2
16783 // CHECK13-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
16784 // CHECK13-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
16785 // CHECK13-NEXT:    [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
16786 // CHECK13-NEXT:    store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4
16787 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
16788 // CHECK13:       omp.inner.for.cond:
16789 // CHECK13-NEXT:    [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27
16790 // CHECK13-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !27
16791 // CHECK13-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
16792 // CHECK13-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
16793 // CHECK13:       omp.inner.for.body:
16794 // CHECK13-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27
16795 // CHECK13-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1
16796 // CHECK13-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
16797 // CHECK13-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !27
16798 // CHECK13-NEXT:    [[TMP4:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !27
16799 // CHECK13-NEXT:    [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1
16800 // CHECK13-NEXT:    store i32 [[ADD1]], i32* [[A]], align 4, !llvm.access.group !27
16801 // CHECK13-NEXT:    [[TMP5:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !27
16802 // CHECK13-NEXT:    [[CONV:%.*]] = sext i16 [[TMP5]] to i32
16803 // CHECK13-NEXT:    [[ADD2:%.*]] = add nsw i32 [[CONV]], 1
16804 // CHECK13-NEXT:    [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
16805 // CHECK13-NEXT:    store i16 [[CONV3]], i16* [[AA]], align 2, !llvm.access.group !27
16806 // CHECK13-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2
16807 // CHECK13-NEXT:    [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !27
16808 // CHECK13-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP6]], 1
16809 // CHECK13-NEXT:    store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !27
16810 // CHECK13-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
16811 // CHECK13:       omp.body.continue:
16812 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
16813 // CHECK13:       omp.inner.for.inc:
16814 // CHECK13-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27
16815 // CHECK13-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP7]], 1
16816 // CHECK13-NEXT:    store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27
16817 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]]
16818 // CHECK13:       omp.inner.for.end:
16819 // CHECK13-NEXT:    store i32 10, i32* [[I]], align 4
16820 // CHECK13-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
16821 // CHECK13-NEXT:    ret i32 [[TMP8]]
16822 //
16823 //
16824 // CHECK14-LABEL: define {{[^@]+}}@_Z3fooi
16825 // CHECK14-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0:[0-9]+]] {
16826 // CHECK14-NEXT:  entry:
16827 // CHECK14-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
16828 // CHECK14-NEXT:    [[A:%.*]] = alloca i32, align 4
16829 // CHECK14-NEXT:    [[AA:%.*]] = alloca i16, align 2
16830 // CHECK14-NEXT:    [[B:%.*]] = alloca [10 x float], align 4
16831 // CHECK14-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 8
16832 // CHECK14-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
16833 // CHECK14-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 8
16834 // CHECK14-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i64, align 8
16835 // CHECK14-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8
16836 // CHECK14-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
16837 // CHECK14-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
16838 // CHECK14-NEXT:    [[TMP:%.*]] = alloca i32, align 4
16839 // CHECK14-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
16840 // CHECK14-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
16841 // CHECK14-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
16842 // CHECK14-NEXT:    [[I:%.*]] = alloca i32, align 4
16843 // CHECK14-NEXT:    [[_TMP4:%.*]] = alloca i32, align 4
16844 // CHECK14-NEXT:    [[DOTOMP_LB5:%.*]] = alloca i32, align 4
16845 // CHECK14-NEXT:    [[DOTOMP_UB6:%.*]] = alloca i32, align 4
16846 // CHECK14-NEXT:    [[DOTOMP_IV7:%.*]] = alloca i32, align 4
16847 // CHECK14-NEXT:    [[DOTLINEAR_START:%.*]] = alloca i32, align 4
16848 // CHECK14-NEXT:    [[A8:%.*]] = alloca i32, align 4
16849 // CHECK14-NEXT:    [[A9:%.*]] = alloca i32, align 4
16850 // CHECK14-NEXT:    [[_TMP20:%.*]] = alloca i32, align 4
16851 // CHECK14-NEXT:    [[DOTOMP_LB21:%.*]] = alloca i32, align 4
16852 // CHECK14-NEXT:    [[DOTOMP_UB22:%.*]] = alloca i32, align 4
16853 // CHECK14-NEXT:    [[DOTOMP_IV23:%.*]] = alloca i32, align 4
16854 // CHECK14-NEXT:    [[I24:%.*]] = alloca i32, align 4
16855 // CHECK14-NEXT:    [[_TMP36:%.*]] = alloca i32, align 4
16856 // CHECK14-NEXT:    [[DOTOMP_LB37:%.*]] = alloca i32, align 4
16857 // CHECK14-NEXT:    [[DOTOMP_UB38:%.*]] = alloca i32, align 4
16858 // CHECK14-NEXT:    [[DOTOMP_IV39:%.*]] = alloca i32, align 4
16859 // CHECK14-NEXT:    [[I40:%.*]] = alloca i32, align 4
16860 // CHECK14-NEXT:    [[_TMP54:%.*]] = alloca i32, align 4
16861 // CHECK14-NEXT:    [[DOTOMP_LB55:%.*]] = alloca i32, align 4
16862 // CHECK14-NEXT:    [[DOTOMP_UB56:%.*]] = alloca i32, align 4
16863 // CHECK14-NEXT:    [[DOTOMP_IV57:%.*]] = alloca i32, align 4
16864 // CHECK14-NEXT:    [[I58:%.*]] = alloca i32, align 4
16865 // CHECK14-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
16866 // CHECK14-NEXT:    store i32 0, i32* [[A]], align 4
16867 // CHECK14-NEXT:    store i16 0, i16* [[AA]], align 2
16868 // CHECK14-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
16869 // CHECK14-NEXT:    [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
16870 // CHECK14-NEXT:    [[TMP2:%.*]] = call i8* @llvm.stacksave()
16871 // CHECK14-NEXT:    store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8
16872 // CHECK14-NEXT:    [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4
16873 // CHECK14-NEXT:    store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8
16874 // CHECK14-NEXT:    [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
16875 // CHECK14-NEXT:    [[TMP4:%.*]] = zext i32 [[TMP3]] to i64
16876 // CHECK14-NEXT:    [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]]
16877 // CHECK14-NEXT:    [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8
16878 // CHECK14-NEXT:    store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8
16879 // CHECK14-NEXT:    [[TMP6:%.*]] = load i32, i32* [[A]], align 4
16880 // CHECK14-NEXT:    store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_]], align 4
16881 // CHECK14-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
16882 // CHECK14-NEXT:    store i32 [[TMP7]], i32* [[DOTCAPTURE_EXPR_2]], align 4
16883 // CHECK14-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
16884 // CHECK14-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
16885 // CHECK14-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
16886 // CHECK14-NEXT:    store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
16887 // CHECK14-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
16888 // CHECK14:       omp.inner.for.cond:
16889 // CHECK14-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
16890 // CHECK14-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !2
16891 // CHECK14-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
16892 // CHECK14-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
16893 // CHECK14:       omp.inner.for.body:
16894 // CHECK14-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
16895 // CHECK14-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
16896 // CHECK14-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
16897 // CHECK14-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !2
16898 // CHECK14-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
16899 // CHECK14:       omp.body.continue:
16900 // CHECK14-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
16901 // CHECK14:       omp.inner.for.inc:
16902 // CHECK14-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
16903 // CHECK14-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1
16904 // CHECK14-NEXT:    store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
16905 // CHECK14-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]
16906 // CHECK14:       omp.inner.for.end:
16907 // CHECK14-NEXT:    store i32 10, i32* [[I]], align 4
16908 // CHECK14-NEXT:    store i32 0, i32* [[DOTOMP_LB5]], align 4
16909 // CHECK14-NEXT:    store i32 9, i32* [[DOTOMP_UB6]], align 4
16910 // CHECK14-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB5]], align 4
16911 // CHECK14-NEXT:    store i32 [[TMP13]], i32* [[DOTOMP_IV7]], align 4
16912 // CHECK14-NEXT:    [[TMP14:%.*]] = load i32, i32* [[A]], align 4
16913 // CHECK14-NEXT:    store i32 [[TMP14]], i32* [[DOTLINEAR_START]], align 4
16914 // CHECK14-NEXT:    br label [[OMP_INNER_FOR_COND10:%.*]]
16915 // CHECK14:       omp.inner.for.cond10:
16916 // CHECK14-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV7]], align 4
16917 // CHECK14-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB6]], align 4
16918 // CHECK14-NEXT:    [[CMP11:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]]
16919 // CHECK14-NEXT:    br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY12:%.*]], label [[OMP_INNER_FOR_END19:%.*]]
16920 // CHECK14:       omp.inner.for.body12:
16921 // CHECK14-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV7]], align 4
16922 // CHECK14-NEXT:    [[MUL13:%.*]] = mul nsw i32 [[TMP17]], 1
16923 // CHECK14-NEXT:    [[ADD14:%.*]] = add nsw i32 0, [[MUL13]]
16924 // CHECK14-NEXT:    store i32 [[ADD14]], i32* [[A8]], align 4, !nontemporal !7
16925 // CHECK14-NEXT:    [[TMP18:%.*]] = load i32, i32* [[A8]], align 4, !nontemporal !7
16926 // CHECK14-NEXT:    [[ADD15:%.*]] = add nsw i32 [[TMP18]], 1
16927 // CHECK14-NEXT:    store i32 [[ADD15]], i32* [[A8]], align 4, !nontemporal !7
16928 // CHECK14-NEXT:    br label [[OMP_BODY_CONTINUE16:%.*]]
16929 // CHECK14:       omp.body.continue16:
16930 // CHECK14-NEXT:    br label [[OMP_INNER_FOR_INC17:%.*]]
16931 // CHECK14:       omp.inner.for.inc17:
16932 // CHECK14-NEXT:    [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV7]], align 4
16933 // CHECK14-NEXT:    [[ADD18:%.*]] = add nsw i32 [[TMP19]], 1
16934 // CHECK14-NEXT:    store i32 [[ADD18]], i32* [[DOTOMP_IV7]], align 4
16935 // CHECK14-NEXT:    br label [[OMP_INNER_FOR_COND10]], !llvm.loop [[LOOP8:![0-9]+]]
16936 // CHECK14:       omp.inner.for.end19:
16937 // CHECK14-NEXT:    store i32 10, i32* [[A]], align 4
16938 // CHECK14-NEXT:    store i32 0, i32* [[DOTOMP_LB21]], align 4
16939 // CHECK14-NEXT:    store i32 9, i32* [[DOTOMP_UB22]], align 4
16940 // CHECK14-NEXT:    [[TMP20:%.*]] = load i32, i32* [[DOTOMP_LB21]], align 4
16941 // CHECK14-NEXT:    store i32 [[TMP20]], i32* [[DOTOMP_IV23]], align 4
16942 // CHECK14-NEXT:    br label [[OMP_INNER_FOR_COND25:%.*]]
16943 // CHECK14:       omp.inner.for.cond25:
16944 // CHECK14-NEXT:    [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV23]], align 4, !llvm.access.group !10
16945 // CHECK14-NEXT:    [[TMP22:%.*]] = load i32, i32* [[DOTOMP_UB22]], align 4, !llvm.access.group !10
16946 // CHECK14-NEXT:    [[CMP26:%.*]] = icmp sle i32 [[TMP21]], [[TMP22]]
16947 // CHECK14-NEXT:    br i1 [[CMP26]], label [[OMP_INNER_FOR_BODY27:%.*]], label [[OMP_INNER_FOR_END35:%.*]]
16948 // CHECK14:       omp.inner.for.body27:
16949 // CHECK14-NEXT:    [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV23]], align 4, !llvm.access.group !10
16950 // CHECK14-NEXT:    [[MUL28:%.*]] = mul nsw i32 [[TMP23]], 1
16951 // CHECK14-NEXT:    [[ADD29:%.*]] = add nsw i32 0, [[MUL28]]
16952 // CHECK14-NEXT:    store i32 [[ADD29]], i32* [[I24]], align 4, !llvm.access.group !10
16953 // CHECK14-NEXT:    [[TMP24:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !10
16954 // CHECK14-NEXT:    [[CONV:%.*]] = sext i16 [[TMP24]] to i32
16955 // CHECK14-NEXT:    [[ADD30:%.*]] = add nsw i32 [[CONV]], 1
16956 // CHECK14-NEXT:    [[CONV31:%.*]] = trunc i32 [[ADD30]] to i16
16957 // CHECK14-NEXT:    store i16 [[CONV31]], i16* [[AA]], align 2, !llvm.access.group !10
16958 // CHECK14-NEXT:    br label [[OMP_BODY_CONTINUE32:%.*]]
16959 // CHECK14:       omp.body.continue32:
16960 // CHECK14-NEXT:    br label [[OMP_INNER_FOR_INC33:%.*]]
16961 // CHECK14:       omp.inner.for.inc33:
16962 // CHECK14-NEXT:    [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IV23]], align 4, !llvm.access.group !10
16963 // CHECK14-NEXT:    [[ADD34:%.*]] = add nsw i32 [[TMP25]], 1
16964 // CHECK14-NEXT:    store i32 [[ADD34]], i32* [[DOTOMP_IV23]], align 4, !llvm.access.group !10
16965 // CHECK14-NEXT:    br label [[OMP_INNER_FOR_COND25]], !llvm.loop [[LOOP11:![0-9]+]]
16966 // CHECK14:       omp.inner.for.end35:
16967 // CHECK14-NEXT:    store i32 10, i32* [[I24]], align 4
16968 // CHECK14-NEXT:    store i32 0, i32* [[DOTOMP_LB37]], align 4
16969 // CHECK14-NEXT:    store i32 9, i32* [[DOTOMP_UB38]], align 4
16970 // CHECK14-NEXT:    [[TMP26:%.*]] = load i32, i32* [[DOTOMP_LB37]], align 4
16971 // CHECK14-NEXT:    store i32 [[TMP26]], i32* [[DOTOMP_IV39]], align 4
16972 // CHECK14-NEXT:    br label [[OMP_INNER_FOR_COND41:%.*]]
16973 // CHECK14:       omp.inner.for.cond41:
16974 // CHECK14-NEXT:    [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV39]], align 4, !llvm.access.group !13
16975 // CHECK14-NEXT:    [[TMP28:%.*]] = load i32, i32* [[DOTOMP_UB38]], align 4, !llvm.access.group !13
16976 // CHECK14-NEXT:    [[CMP42:%.*]] = icmp sle i32 [[TMP27]], [[TMP28]]
16977 // CHECK14-NEXT:    br i1 [[CMP42]], label [[OMP_INNER_FOR_BODY43:%.*]], label [[OMP_INNER_FOR_END53:%.*]]
16978 // CHECK14:       omp.inner.for.body43:
16979 // CHECK14-NEXT:    [[TMP29:%.*]] = load i32, i32* [[DOTOMP_IV39]], align 4, !llvm.access.group !13
16980 // CHECK14-NEXT:    [[MUL44:%.*]] = mul nsw i32 [[TMP29]], 1
16981 // CHECK14-NEXT:    [[ADD45:%.*]] = add nsw i32 0, [[MUL44]]
16982 // CHECK14-NEXT:    store i32 [[ADD45]], i32* [[I40]], align 4, !llvm.access.group !13
16983 // CHECK14-NEXT:    [[TMP30:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !13
16984 // CHECK14-NEXT:    [[ADD46:%.*]] = add nsw i32 [[TMP30]], 1
16985 // CHECK14-NEXT:    store i32 [[ADD46]], i32* [[A]], align 4, !llvm.access.group !13
16986 // CHECK14-NEXT:    [[TMP31:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !13
16987 // CHECK14-NEXT:    [[CONV47:%.*]] = sext i16 [[TMP31]] to i32
16988 // CHECK14-NEXT:    [[ADD48:%.*]] = add nsw i32 [[CONV47]], 1
16989 // CHECK14-NEXT:    [[CONV49:%.*]] = trunc i32 [[ADD48]] to i16
16990 // CHECK14-NEXT:    store i16 [[CONV49]], i16* [[AA]], align 2, !llvm.access.group !13
16991 // CHECK14-NEXT:    br label [[OMP_BODY_CONTINUE50:%.*]]
16992 // CHECK14:       omp.body.continue50:
16993 // CHECK14-NEXT:    br label [[OMP_INNER_FOR_INC51:%.*]]
16994 // CHECK14:       omp.inner.for.inc51:
16995 // CHECK14-NEXT:    [[TMP32:%.*]] = load i32, i32* [[DOTOMP_IV39]], align 4, !llvm.access.group !13
16996 // CHECK14-NEXT:    [[ADD52:%.*]] = add nsw i32 [[TMP32]], 1
16997 // CHECK14-NEXT:    store i32 [[ADD52]], i32* [[DOTOMP_IV39]], align 4, !llvm.access.group !13
16998 // CHECK14-NEXT:    br label [[OMP_INNER_FOR_COND41]], !llvm.loop [[LOOP14:![0-9]+]]
16999 // CHECK14:       omp.inner.for.end53:
17000 // CHECK14-NEXT:    store i32 10, i32* [[I40]], align 4
17001 // CHECK14-NEXT:    store i32 0, i32* [[DOTOMP_LB55]], align 4
17002 // CHECK14-NEXT:    store i32 9, i32* [[DOTOMP_UB56]], align 4
17003 // CHECK14-NEXT:    [[TMP33:%.*]] = load i32, i32* [[DOTOMP_LB55]], align 4
17004 // CHECK14-NEXT:    store i32 [[TMP33]], i32* [[DOTOMP_IV57]], align 4
17005 // CHECK14-NEXT:    [[ARRAYDECAY:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 0
17006 // CHECK14-NEXT:    call void @llvm.assume(i1 true) [ "align"(float* [[ARRAYDECAY]], i64 16) ]
17007 // CHECK14-NEXT:    br label [[OMP_INNER_FOR_COND59:%.*]]
17008 // CHECK14:       omp.inner.for.cond59:
17009 // CHECK14-NEXT:    [[TMP34:%.*]] = load i32, i32* [[DOTOMP_IV57]], align 4, !llvm.access.group !16
17010 // CHECK14-NEXT:    [[TMP35:%.*]] = load i32, i32* [[DOTOMP_UB56]], align 4, !llvm.access.group !16
17011 // CHECK14-NEXT:    [[CMP60:%.*]] = icmp sle i32 [[TMP34]], [[TMP35]]
17012 // CHECK14-NEXT:    br i1 [[CMP60]], label [[OMP_INNER_FOR_BODY61:%.*]], label [[OMP_INNER_FOR_END85:%.*]]
17013 // CHECK14:       omp.inner.for.body61:
17014 // CHECK14-NEXT:    [[TMP36:%.*]] = load i32, i32* [[DOTOMP_IV57]], align 4, !llvm.access.group !16
17015 // CHECK14-NEXT:    [[MUL62:%.*]] = mul nsw i32 [[TMP36]], 1
17016 // CHECK14-NEXT:    [[ADD63:%.*]] = add nsw i32 0, [[MUL62]]
17017 // CHECK14-NEXT:    store i32 [[ADD63]], i32* [[I58]], align 4, !llvm.access.group !16
17018 // CHECK14-NEXT:    [[TMP37:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !16
17019 // CHECK14-NEXT:    [[ADD64:%.*]] = add nsw i32 [[TMP37]], 1
17020 // CHECK14-NEXT:    store i32 [[ADD64]], i32* [[A]], align 4, !llvm.access.group !16
17021 // CHECK14-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2
17022 // CHECK14-NEXT:    [[TMP38:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !16
17023 // CHECK14-NEXT:    [[CONV65:%.*]] = fpext float [[TMP38]] to double
17024 // CHECK14-NEXT:    [[ADD66:%.*]] = fadd double [[CONV65]], 1.000000e+00
17025 // CHECK14-NEXT:    [[CONV67:%.*]] = fptrunc double [[ADD66]] to float
17026 // CHECK14-NEXT:    store float [[CONV67]], float* [[ARRAYIDX]], align 4, !llvm.access.group !16
17027 // CHECK14-NEXT:    [[ARRAYIDX68:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3
17028 // CHECK14-NEXT:    [[TMP39:%.*]] = load float, float* [[ARRAYIDX68]], align 4, !llvm.access.group !16
17029 // CHECK14-NEXT:    [[CONV69:%.*]] = fpext float [[TMP39]] to double
17030 // CHECK14-NEXT:    [[ADD70:%.*]] = fadd double [[CONV69]], 1.000000e+00
17031 // CHECK14-NEXT:    [[CONV71:%.*]] = fptrunc double [[ADD70]] to float
17032 // CHECK14-NEXT:    store float [[CONV71]], float* [[ARRAYIDX68]], align 4, !llvm.access.group !16
17033 // CHECK14-NEXT:    [[ARRAYIDX72:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1
17034 // CHECK14-NEXT:    [[ARRAYIDX73:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX72]], i64 0, i64 2
17035 // CHECK14-NEXT:    [[TMP40:%.*]] = load double, double* [[ARRAYIDX73]], align 8, !llvm.access.group !16
17036 // CHECK14-NEXT:    [[ADD74:%.*]] = fadd double [[TMP40]], 1.000000e+00
17037 // CHECK14-NEXT:    store double [[ADD74]], double* [[ARRAYIDX73]], align 8, !llvm.access.group !16
17038 // CHECK14-NEXT:    [[TMP41:%.*]] = mul nsw i64 1, [[TMP4]]
17039 // CHECK14-NEXT:    [[ARRAYIDX75:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP41]]
17040 // CHECK14-NEXT:    [[ARRAYIDX76:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX75]], i64 3
17041 // CHECK14-NEXT:    [[TMP42:%.*]] = load double, double* [[ARRAYIDX76]], align 8, !llvm.access.group !16
17042 // CHECK14-NEXT:    [[ADD77:%.*]] = fadd double [[TMP42]], 1.000000e+00
17043 // CHECK14-NEXT:    store double [[ADD77]], double* [[ARRAYIDX76]], align 8, !llvm.access.group !16
17044 // CHECK14-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0
17045 // CHECK14-NEXT:    [[TMP43:%.*]] = load i64, i64* [[X]], align 8, !llvm.access.group !16
17046 // CHECK14-NEXT:    [[ADD78:%.*]] = add nsw i64 [[TMP43]], 1
17047 // CHECK14-NEXT:    store i64 [[ADD78]], i64* [[X]], align 8, !llvm.access.group !16
17048 // CHECK14-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1
17049 // CHECK14-NEXT:    [[TMP44:%.*]] = load i8, i8* [[Y]], align 8, !llvm.access.group !16
17050 // CHECK14-NEXT:    [[CONV79:%.*]] = sext i8 [[TMP44]] to i32
17051 // CHECK14-NEXT:    [[ADD80:%.*]] = add nsw i32 [[CONV79]], 1
17052 // CHECK14-NEXT:    [[CONV81:%.*]] = trunc i32 [[ADD80]] to i8
17053 // CHECK14-NEXT:    store i8 [[CONV81]], i8* [[Y]], align 8, !llvm.access.group !16
17054 // CHECK14-NEXT:    br label [[OMP_BODY_CONTINUE82:%.*]]
17055 // CHECK14:       omp.body.continue82:
17056 // CHECK14-NEXT:    br label [[OMP_INNER_FOR_INC83:%.*]]
17057 // CHECK14:       omp.inner.for.inc83:
17058 // CHECK14-NEXT:    [[TMP45:%.*]] = load i32, i32* [[DOTOMP_IV57]], align 4, !llvm.access.group !16
17059 // CHECK14-NEXT:    [[ADD84:%.*]] = add nsw i32 [[TMP45]], 1
17060 // CHECK14-NEXT:    store i32 [[ADD84]], i32* [[DOTOMP_IV57]], align 4, !llvm.access.group !16
17061 // CHECK14-NEXT:    br label [[OMP_INNER_FOR_COND59]], !llvm.loop [[LOOP17:![0-9]+]]
17062 // CHECK14:       omp.inner.for.end85:
17063 // CHECK14-NEXT:    store i32 10, i32* [[I58]], align 4
17064 // CHECK14-NEXT:    [[TMP46:%.*]] = load i32, i32* [[A]], align 4
17065 // CHECK14-NEXT:    [[TMP47:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
17066 // CHECK14-NEXT:    call void @llvm.stackrestore(i8* [[TMP47]])
17067 // CHECK14-NEXT:    ret i32 [[TMP46]]
17068 //
17069 //
17070 // CHECK14-LABEL: define {{[^@]+}}@_Z3bari
17071 // CHECK14-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {
17072 // CHECK14-NEXT:  entry:
17073 // CHECK14-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
17074 // CHECK14-NEXT:    [[A:%.*]] = alloca i32, align 4
17075 // CHECK14-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8
17076 // CHECK14-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
17077 // CHECK14-NEXT:    store i32 0, i32* [[A]], align 4
17078 // CHECK14-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
17079 // CHECK14-NEXT:    [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]])
17080 // CHECK14-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
17081 // CHECK14-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
17082 // CHECK14-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
17083 // CHECK14-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
17084 // CHECK14-NEXT:    [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP2]])
17085 // CHECK14-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
17086 // CHECK14-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
17087 // CHECK14-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
17088 // CHECK14-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
17089 // CHECK14-NEXT:    [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]])
17090 // CHECK14-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
17091 // CHECK14-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
17092 // CHECK14-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
17093 // CHECK14-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
17094 // CHECK14-NEXT:    [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]])
17095 // CHECK14-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
17096 // CHECK14-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
17097 // CHECK14-NEXT:    store i32 [[ADD6]], i32* [[A]], align 4
17098 // CHECK14-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
17099 // CHECK14-NEXT:    ret i32 [[TMP8]]
17100 //
17101 //
17102 // CHECK14-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
17103 // CHECK14-SAME: (%struct.S1* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 {
17104 // CHECK14-NEXT:  entry:
17105 // CHECK14-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
17106 // CHECK14-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
17107 // CHECK14-NEXT:    [[B:%.*]] = alloca i32, align 4
17108 // CHECK14-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 8
17109 // CHECK14-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
17110 // CHECK14-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
17111 // CHECK14-NEXT:    [[TMP:%.*]] = alloca i32, align 4
17112 // CHECK14-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
17113 // CHECK14-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
17114 // CHECK14-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
17115 // CHECK14-NEXT:    [[I:%.*]] = alloca i32, align 4
17116 // CHECK14-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
17117 // CHECK14-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
17118 // CHECK14-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
17119 // CHECK14-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
17120 // CHECK14-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
17121 // CHECK14-NEXT:    store i32 [[ADD]], i32* [[B]], align 4
17122 // CHECK14-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
17123 // CHECK14-NEXT:    [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
17124 // CHECK14-NEXT:    [[TMP3:%.*]] = call i8* @llvm.stacksave()
17125 // CHECK14-NEXT:    store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8
17126 // CHECK14-NEXT:    [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]
17127 // CHECK14-NEXT:    [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2
17128 // CHECK14-NEXT:    store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8
17129 // CHECK14-NEXT:    [[TMP5:%.*]] = load i32, i32* [[N_ADDR]], align 4
17130 // CHECK14-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 60
17131 // CHECK14-NEXT:    [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8
17132 // CHECK14-NEXT:    store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
17133 // CHECK14-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
17134 // CHECK14-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
17135 // CHECK14-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
17136 // CHECK14-NEXT:    store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
17137 // CHECK14-NEXT:    [[TMP7:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
17138 // CHECK14-NEXT:    [[TOBOOL:%.*]] = trunc i8 [[TMP7]] to i1
17139 // CHECK14-NEXT:    br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
17140 // CHECK14:       omp_if.then:
17141 // CHECK14-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
17142 // CHECK14:       omp.inner.for.cond:
17143 // CHECK14-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
17144 // CHECK14-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !19
17145 // CHECK14-NEXT:    [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
17146 // CHECK14-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
17147 // CHECK14:       omp.inner.for.body:
17148 // CHECK14-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
17149 // CHECK14-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
17150 // CHECK14-NEXT:    [[ADD3:%.*]] = add nsw i32 0, [[MUL]]
17151 // CHECK14-NEXT:    store i32 [[ADD3]], i32* [[I]], align 4, !llvm.access.group !19
17152 // CHECK14-NEXT:    [[TMP11:%.*]] = load i32, i32* [[B]], align 4, !llvm.access.group !19
17153 // CHECK14-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP11]] to double
17154 // CHECK14-NEXT:    [[ADD4:%.*]] = fadd double [[CONV]], 1.500000e+00
17155 // CHECK14-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
17156 // CHECK14-NEXT:    store double [[ADD4]], double* [[A]], align 8, !llvm.access.group !19
17157 // CHECK14-NEXT:    [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
17158 // CHECK14-NEXT:    [[TMP12:%.*]] = load double, double* [[A5]], align 8, !llvm.access.group !19
17159 // CHECK14-NEXT:    [[INC:%.*]] = fadd double [[TMP12]], 1.000000e+00
17160 // CHECK14-NEXT:    store double [[INC]], double* [[A5]], align 8, !llvm.access.group !19
17161 // CHECK14-NEXT:    [[CONV6:%.*]] = fptosi double [[INC]] to i16
17162 // CHECK14-NEXT:    [[TMP13:%.*]] = mul nsw i64 1, [[TMP2]]
17163 // CHECK14-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP13]]
17164 // CHECK14-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
17165 // CHECK14-NEXT:    store i16 [[CONV6]], i16* [[ARRAYIDX7]], align 2, !llvm.access.group !19
17166 // CHECK14-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
17167 // CHECK14:       omp.body.continue:
17168 // CHECK14-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
17169 // CHECK14:       omp.inner.for.inc:
17170 // CHECK14-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
17171 // CHECK14-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP14]], 1
17172 // CHECK14-NEXT:    store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
17173 // CHECK14-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]]
17174 // CHECK14:       omp.inner.for.end:
17175 // CHECK14-NEXT:    br label [[OMP_IF_END:%.*]]
17176 // CHECK14:       omp_if.else:
17177 // CHECK14-NEXT:    br label [[OMP_INNER_FOR_COND9:%.*]]
17178 // CHECK14:       omp.inner.for.cond9:
17179 // CHECK14-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
17180 // CHECK14-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
17181 // CHECK14-NEXT:    [[CMP10:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]]
17182 // CHECK14-NEXT:    br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY11:%.*]], label [[OMP_INNER_FOR_END25:%.*]]
17183 // CHECK14:       omp.inner.for.body11:
17184 // CHECK14-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
17185 // CHECK14-NEXT:    [[MUL12:%.*]] = mul nsw i32 [[TMP17]], 1
17186 // CHECK14-NEXT:    [[ADD13:%.*]] = add nsw i32 0, [[MUL12]]
17187 // CHECK14-NEXT:    store i32 [[ADD13]], i32* [[I]], align 4
17188 // CHECK14-NEXT:    [[TMP18:%.*]] = load i32, i32* [[B]], align 4
17189 // CHECK14-NEXT:    [[CONV14:%.*]] = sitofp i32 [[TMP18]] to double
17190 // CHECK14-NEXT:    [[ADD15:%.*]] = fadd double [[CONV14]], 1.500000e+00
17191 // CHECK14-NEXT:    [[A16:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
17192 // CHECK14-NEXT:    store double [[ADD15]], double* [[A16]], align 8
17193 // CHECK14-NEXT:    [[A17:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
17194 // CHECK14-NEXT:    [[TMP19:%.*]] = load double, double* [[A17]], align 8
17195 // CHECK14-NEXT:    [[INC18:%.*]] = fadd double [[TMP19]], 1.000000e+00
17196 // CHECK14-NEXT:    store double [[INC18]], double* [[A17]], align 8
17197 // CHECK14-NEXT:    [[CONV19:%.*]] = fptosi double [[INC18]] to i16
17198 // CHECK14-NEXT:    [[TMP20:%.*]] = mul nsw i64 1, [[TMP2]]
17199 // CHECK14-NEXT:    [[ARRAYIDX20:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP20]]
17200 // CHECK14-NEXT:    [[ARRAYIDX21:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX20]], i64 1
17201 // CHECK14-NEXT:    store i16 [[CONV19]], i16* [[ARRAYIDX21]], align 2
17202 // CHECK14-NEXT:    br label [[OMP_BODY_CONTINUE22:%.*]]
17203 // CHECK14:       omp.body.continue22:
17204 // CHECK14-NEXT:    br label [[OMP_INNER_FOR_INC23:%.*]]
17205 // CHECK14:       omp.inner.for.inc23:
17206 // CHECK14-NEXT:    [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
17207 // CHECK14-NEXT:    [[ADD24:%.*]] = add nsw i32 [[TMP21]], 1
17208 // CHECK14-NEXT:    store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4
17209 // CHECK14-NEXT:    br label [[OMP_INNER_FOR_COND9]], !llvm.loop [[LOOP22:![0-9]+]]
17210 // CHECK14:       omp.inner.for.end25:
17211 // CHECK14-NEXT:    br label [[OMP_IF_END]]
17212 // CHECK14:       omp_if.end:
17213 // CHECK14-NEXT:    store i32 10, i32* [[I]], align 4
17214 // CHECK14-NEXT:    [[TMP22:%.*]] = mul nsw i64 1, [[TMP2]]
17215 // CHECK14-NEXT:    [[ARRAYIDX26:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP22]]
17216 // CHECK14-NEXT:    [[ARRAYIDX27:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX26]], i64 1
17217 // CHECK14-NEXT:    [[TMP23:%.*]] = load i16, i16* [[ARRAYIDX27]], align 2
17218 // CHECK14-NEXT:    [[CONV28:%.*]] = sext i16 [[TMP23]] to i32
17219 // CHECK14-NEXT:    [[TMP24:%.*]] = load i32, i32* [[B]], align 4
17220 // CHECK14-NEXT:    [[ADD29:%.*]] = add nsw i32 [[CONV28]], [[TMP24]]
17221 // CHECK14-NEXT:    [[TMP25:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
17222 // CHECK14-NEXT:    call void @llvm.stackrestore(i8* [[TMP25]])
17223 // CHECK14-NEXT:    ret i32 [[ADD29]]
17224 //
17225 //
17226 // CHECK14-LABEL: define {{[^@]+}}@_ZL7fstatici
17227 // CHECK14-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {
17228 // CHECK14-NEXT:  entry:
17229 // CHECK14-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
17230 // CHECK14-NEXT:    [[A:%.*]] = alloca i32, align 4
17231 // CHECK14-NEXT:    [[AA:%.*]] = alloca i16, align 2
17232 // CHECK14-NEXT:    [[AAA:%.*]] = alloca i8, align 1
17233 // CHECK14-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
17234 // CHECK14-NEXT:    [[TMP:%.*]] = alloca i32, align 4
17235 // CHECK14-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
17236 // CHECK14-NEXT:    [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
17237 // CHECK14-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
17238 // CHECK14-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
17239 // CHECK14-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
17240 // CHECK14-NEXT:    [[I:%.*]] = alloca i32, align 4
17241 // CHECK14-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
17242 // CHECK14-NEXT:    [[I5:%.*]] = alloca i32, align 4
17243 // CHECK14-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
17244 // CHECK14-NEXT:    store i32 0, i32* [[A]], align 4
17245 // CHECK14-NEXT:    store i16 0, i16* [[AA]], align 2
17246 // CHECK14-NEXT:    store i8 0, i8* [[AAA]], align 1
17247 // CHECK14-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
17248 // CHECK14-NEXT:    store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4
17249 // CHECK14-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
17250 // CHECK14-NEXT:    store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_1]], align 4
17251 // CHECK14-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
17252 // CHECK14-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
17253 // CHECK14-NEXT:    [[SUB:%.*]] = sub i32 [[TMP2]], [[TMP3]]
17254 // CHECK14-NEXT:    [[SUB3:%.*]] = sub i32 [[SUB]], 1
17255 // CHECK14-NEXT:    [[ADD:%.*]] = add i32 [[SUB3]], 1
17256 // CHECK14-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], 1
17257 // CHECK14-NEXT:    [[SUB4:%.*]] = sub i32 [[DIV]], 1
17258 // CHECK14-NEXT:    store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_2]], align 4
17259 // CHECK14-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
17260 // CHECK14-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
17261 // CHECK14-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_UB]], align 4
17262 // CHECK14-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
17263 // CHECK14-NEXT:    store i32 [[TMP5]], i32* [[I]], align 4
17264 // CHECK14-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
17265 // CHECK14-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
17266 // CHECK14-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]]
17267 // CHECK14-NEXT:    br i1 [[CMP]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END:%.*]]
17268 // CHECK14:       simd.if.then:
17269 // CHECK14-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
17270 // CHECK14-NEXT:    store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
17271 // CHECK14-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
17272 // CHECK14:       omp.inner.for.cond:
17273 // CHECK14-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
17274 // CHECK14-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !24
17275 // CHECK14-NEXT:    [[ADD6:%.*]] = add i32 [[TMP10]], 1
17276 // CHECK14-NEXT:    [[CMP7:%.*]] = icmp ult i32 [[TMP9]], [[ADD6]]
17277 // CHECK14-NEXT:    br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
17278 // CHECK14:       omp.inner.for.body:
17279 // CHECK14-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group !24
17280 // CHECK14-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
17281 // CHECK14-NEXT:    [[MUL:%.*]] = mul i32 [[TMP12]], 1
17282 // CHECK14-NEXT:    [[ADD8:%.*]] = add i32 [[TMP11]], [[MUL]]
17283 // CHECK14-NEXT:    store i32 [[ADD8]], i32* [[I5]], align 4, !llvm.access.group !24
17284 // CHECK14-NEXT:    [[TMP13:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !24
17285 // CHECK14-NEXT:    [[ADD9:%.*]] = add nsw i32 [[TMP13]], 1
17286 // CHECK14-NEXT:    store i32 [[ADD9]], i32* [[A]], align 4, !llvm.access.group !24
17287 // CHECK14-NEXT:    [[TMP14:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !24
17288 // CHECK14-NEXT:    [[CONV:%.*]] = sext i16 [[TMP14]] to i32
17289 // CHECK14-NEXT:    [[ADD10:%.*]] = add nsw i32 [[CONV]], 1
17290 // CHECK14-NEXT:    [[CONV11:%.*]] = trunc i32 [[ADD10]] to i16
17291 // CHECK14-NEXT:    store i16 [[CONV11]], i16* [[AA]], align 2, !llvm.access.group !24
17292 // CHECK14-NEXT:    [[TMP15:%.*]] = load i8, i8* [[AAA]], align 1, !llvm.access.group !24
17293 // CHECK14-NEXT:    [[CONV12:%.*]] = sext i8 [[TMP15]] to i32
17294 // CHECK14-NEXT:    [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1
17295 // CHECK14-NEXT:    [[CONV14:%.*]] = trunc i32 [[ADD13]] to i8
17296 // CHECK14-NEXT:    store i8 [[CONV14]], i8* [[AAA]], align 1, !llvm.access.group !24
17297 // CHECK14-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2
17298 // CHECK14-NEXT:    [[TMP16:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !24
17299 // CHECK14-NEXT:    [[ADD15:%.*]] = add nsw i32 [[TMP16]], 1
17300 // CHECK14-NEXT:    store i32 [[ADD15]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !24
17301 // CHECK14-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
17302 // CHECK14:       omp.body.continue:
17303 // CHECK14-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
17304 // CHECK14:       omp.inner.for.inc:
17305 // CHECK14-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
17306 // CHECK14-NEXT:    [[ADD16:%.*]] = add i32 [[TMP17]], 1
17307 // CHECK14-NEXT:    store i32 [[ADD16]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
17308 // CHECK14-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]]
17309 // CHECK14:       omp.inner.for.end:
17310 // CHECK14-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
17311 // CHECK14-NEXT:    [[TMP19:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
17312 // CHECK14-NEXT:    [[TMP20:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
17313 // CHECK14-NEXT:    [[SUB17:%.*]] = sub i32 [[TMP19]], [[TMP20]]
17314 // CHECK14-NEXT:    [[SUB18:%.*]] = sub i32 [[SUB17]], 1
17315 // CHECK14-NEXT:    [[ADD19:%.*]] = add i32 [[SUB18]], 1
17316 // CHECK14-NEXT:    [[DIV20:%.*]] = udiv i32 [[ADD19]], 1
17317 // CHECK14-NEXT:    [[MUL21:%.*]] = mul i32 [[DIV20]], 1
17318 // CHECK14-NEXT:    [[ADD22:%.*]] = add i32 [[TMP18]], [[MUL21]]
17319 // CHECK14-NEXT:    store i32 [[ADD22]], i32* [[I5]], align 4
17320 // CHECK14-NEXT:    br label [[SIMD_IF_END]]
17321 // CHECK14:       simd.if.end:
17322 // CHECK14-NEXT:    [[TMP21:%.*]] = load i32, i32* [[A]], align 4
17323 // CHECK14-NEXT:    ret i32 [[TMP21]]
17324 //
17325 //
17326 // CHECK14-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
17327 // CHECK14-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat {
17328 // CHECK14-NEXT:  entry:
17329 // CHECK14-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
17330 // CHECK14-NEXT:    [[A:%.*]] = alloca i32, align 4
17331 // CHECK14-NEXT:    [[AA:%.*]] = alloca i16, align 2
17332 // CHECK14-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
17333 // CHECK14-NEXT:    [[TMP:%.*]] = alloca i32, align 4
17334 // CHECK14-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
17335 // CHECK14-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
17336 // CHECK14-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
17337 // CHECK14-NEXT:    [[I:%.*]] = alloca i32, align 4
17338 // CHECK14-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
17339 // CHECK14-NEXT:    store i32 0, i32* [[A]], align 4
17340 // CHECK14-NEXT:    store i16 0, i16* [[AA]], align 2
17341 // CHECK14-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
17342 // CHECK14-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
17343 // CHECK14-NEXT:    [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
17344 // CHECK14-NEXT:    store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4
17345 // CHECK14-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
17346 // CHECK14:       omp.inner.for.cond:
17347 // CHECK14-NEXT:    [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27
17348 // CHECK14-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !27
17349 // CHECK14-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
17350 // CHECK14-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
17351 // CHECK14:       omp.inner.for.body:
17352 // CHECK14-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27
17353 // CHECK14-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1
17354 // CHECK14-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
17355 // CHECK14-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !27
17356 // CHECK14-NEXT:    [[TMP4:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !27
17357 // CHECK14-NEXT:    [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1
17358 // CHECK14-NEXT:    store i32 [[ADD1]], i32* [[A]], align 4, !llvm.access.group !27
17359 // CHECK14-NEXT:    [[TMP5:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !27
17360 // CHECK14-NEXT:    [[CONV:%.*]] = sext i16 [[TMP5]] to i32
17361 // CHECK14-NEXT:    [[ADD2:%.*]] = add nsw i32 [[CONV]], 1
17362 // CHECK14-NEXT:    [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
17363 // CHECK14-NEXT:    store i16 [[CONV3]], i16* [[AA]], align 2, !llvm.access.group !27
17364 // CHECK14-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2
17365 // CHECK14-NEXT:    [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !27
17366 // CHECK14-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP6]], 1
17367 // CHECK14-NEXT:    store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !27
17368 // CHECK14-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
17369 // CHECK14:       omp.body.continue:
17370 // CHECK14-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
17371 // CHECK14:       omp.inner.for.inc:
17372 // CHECK14-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27
17373 // CHECK14-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP7]], 1
17374 // CHECK14-NEXT:    store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27
17375 // CHECK14-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]]
17376 // CHECK14:       omp.inner.for.end:
17377 // CHECK14-NEXT:    store i32 10, i32* [[I]], align 4
17378 // CHECK14-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
17379 // CHECK14-NEXT:    ret i32 [[TMP8]]
17380 //
17381 //
17382 // CHECK15-LABEL: define {{[^@]+}}@_Z3fooi
17383 // CHECK15-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0:[0-9]+]] {
17384 // CHECK15-NEXT:  entry:
17385 // CHECK15-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
17386 // CHECK15-NEXT:    [[A:%.*]] = alloca i32, align 4
17387 // CHECK15-NEXT:    [[AA:%.*]] = alloca i16, align 2
17388 // CHECK15-NEXT:    [[B:%.*]] = alloca [10 x float], align 4
17389 // CHECK15-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 4
17390 // CHECK15-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 4
17391 // CHECK15-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 8
17392 // CHECK15-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i32, align 4
17393 // CHECK15-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4
17394 // CHECK15-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
17395 // CHECK15-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
17396 // CHECK15-NEXT:    [[TMP:%.*]] = alloca i32, align 4
17397 // CHECK15-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
17398 // CHECK15-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
17399 // CHECK15-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
17400 // CHECK15-NEXT:    [[I:%.*]] = alloca i32, align 4
17401 // CHECK15-NEXT:    [[_TMP4:%.*]] = alloca i32, align 4
17402 // CHECK15-NEXT:    [[DOTOMP_LB5:%.*]] = alloca i32, align 4
17403 // CHECK15-NEXT:    [[DOTOMP_UB6:%.*]] = alloca i32, align 4
17404 // CHECK15-NEXT:    [[DOTOMP_IV7:%.*]] = alloca i32, align 4
17405 // CHECK15-NEXT:    [[DOTLINEAR_START:%.*]] = alloca i32, align 4
17406 // CHECK15-NEXT:    [[A8:%.*]] = alloca i32, align 4
17407 // CHECK15-NEXT:    [[A9:%.*]] = alloca i32, align 4
17408 // CHECK15-NEXT:    [[_TMP20:%.*]] = alloca i32, align 4
17409 // CHECK15-NEXT:    [[DOTOMP_LB21:%.*]] = alloca i32, align 4
17410 // CHECK15-NEXT:    [[DOTOMP_UB22:%.*]] = alloca i32, align 4
17411 // CHECK15-NEXT:    [[DOTOMP_IV23:%.*]] = alloca i32, align 4
17412 // CHECK15-NEXT:    [[I24:%.*]] = alloca i32, align 4
17413 // CHECK15-NEXT:    [[_TMP36:%.*]] = alloca i32, align 4
17414 // CHECK15-NEXT:    [[DOTOMP_LB37:%.*]] = alloca i32, align 4
17415 // CHECK15-NEXT:    [[DOTOMP_UB38:%.*]] = alloca i32, align 4
17416 // CHECK15-NEXT:    [[DOTOMP_IV39:%.*]] = alloca i32, align 4
17417 // CHECK15-NEXT:    [[I40:%.*]] = alloca i32, align 4
17418 // CHECK15-NEXT:    [[_TMP54:%.*]] = alloca i32, align 4
17419 // CHECK15-NEXT:    [[DOTOMP_LB55:%.*]] = alloca i32, align 4
17420 // CHECK15-NEXT:    [[DOTOMP_UB56:%.*]] = alloca i32, align 4
17421 // CHECK15-NEXT:    [[DOTOMP_IV57:%.*]] = alloca i32, align 4
17422 // CHECK15-NEXT:    [[I58:%.*]] = alloca i32, align 4
17423 // CHECK15-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
17424 // CHECK15-NEXT:    store i32 0, i32* [[A]], align 4
17425 // CHECK15-NEXT:    store i16 0, i16* [[AA]], align 2
17426 // CHECK15-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
17427 // CHECK15-NEXT:    [[TMP1:%.*]] = call i8* @llvm.stacksave()
17428 // CHECK15-NEXT:    store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4
17429 // CHECK15-NEXT:    [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4
17430 // CHECK15-NEXT:    store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4
17431 // CHECK15-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
17432 // CHECK15-NEXT:    [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]]
17433 // CHECK15-NEXT:    [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8
17434 // CHECK15-NEXT:    store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4
17435 // CHECK15-NEXT:    [[TMP4:%.*]] = load i32, i32* [[A]], align 4
17436 // CHECK15-NEXT:    store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4
17437 // CHECK15-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
17438 // CHECK15-NEXT:    store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_2]], align 4
17439 // CHECK15-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
17440 // CHECK15-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
17441 // CHECK15-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
17442 // CHECK15-NEXT:    store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
17443 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
17444 // CHECK15:       omp.inner.for.cond:
17445 // CHECK15-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
17446 // CHECK15-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !3
17447 // CHECK15-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
17448 // CHECK15-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
17449 // CHECK15:       omp.inner.for.body:
17450 // CHECK15-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
17451 // CHECK15-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
17452 // CHECK15-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
17453 // CHECK15-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !3
17454 // CHECK15-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
17455 // CHECK15:       omp.body.continue:
17456 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
17457 // CHECK15:       omp.inner.for.inc:
17458 // CHECK15-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
17459 // CHECK15-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
17460 // CHECK15-NEXT:    store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
17461 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]
17462 // CHECK15:       omp.inner.for.end:
17463 // CHECK15-NEXT:    store i32 10, i32* [[I]], align 4
17464 // CHECK15-NEXT:    store i32 0, i32* [[DOTOMP_LB5]], align 4
17465 // CHECK15-NEXT:    store i32 9, i32* [[DOTOMP_UB6]], align 4
17466 // CHECK15-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_LB5]], align 4
17467 // CHECK15-NEXT:    store i32 [[TMP11]], i32* [[DOTOMP_IV7]], align 4
17468 // CHECK15-NEXT:    [[TMP12:%.*]] = load i32, i32* [[A]], align 4
17469 // CHECK15-NEXT:    store i32 [[TMP12]], i32* [[DOTLINEAR_START]], align 4
17470 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_COND10:%.*]]
17471 // CHECK15:       omp.inner.for.cond10:
17472 // CHECK15-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV7]], align 4
17473 // CHECK15-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB6]], align 4
17474 // CHECK15-NEXT:    [[CMP11:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
17475 // CHECK15-NEXT:    br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY12:%.*]], label [[OMP_INNER_FOR_END19:%.*]]
17476 // CHECK15:       omp.inner.for.body12:
17477 // CHECK15-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV7]], align 4
17478 // CHECK15-NEXT:    [[MUL13:%.*]] = mul nsw i32 [[TMP15]], 1
17479 // CHECK15-NEXT:    [[ADD14:%.*]] = add nsw i32 0, [[MUL13]]
17480 // CHECK15-NEXT:    store i32 [[ADD14]], i32* [[A8]], align 4, !nontemporal !8
17481 // CHECK15-NEXT:    [[TMP16:%.*]] = load i32, i32* [[A8]], align 4, !nontemporal !8
17482 // CHECK15-NEXT:    [[ADD15:%.*]] = add nsw i32 [[TMP16]], 1
17483 // CHECK15-NEXT:    store i32 [[ADD15]], i32* [[A8]], align 4, !nontemporal !8
17484 // CHECK15-NEXT:    br label [[OMP_BODY_CONTINUE16:%.*]]
17485 // CHECK15:       omp.body.continue16:
17486 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_INC17:%.*]]
17487 // CHECK15:       omp.inner.for.inc17:
17488 // CHECK15-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV7]], align 4
17489 // CHECK15-NEXT:    [[ADD18:%.*]] = add nsw i32 [[TMP17]], 1
17490 // CHECK15-NEXT:    store i32 [[ADD18]], i32* [[DOTOMP_IV7]], align 4
17491 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_COND10]], !llvm.loop [[LOOP9:![0-9]+]]
17492 // CHECK15:       omp.inner.for.end19:
17493 // CHECK15-NEXT:    store i32 10, i32* [[A]], align 4
17494 // CHECK15-NEXT:    store i32 0, i32* [[DOTOMP_LB21]], align 4
17495 // CHECK15-NEXT:    store i32 9, i32* [[DOTOMP_UB22]], align 4
17496 // CHECK15-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTOMP_LB21]], align 4
17497 // CHECK15-NEXT:    store i32 [[TMP18]], i32* [[DOTOMP_IV23]], align 4
17498 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_COND25:%.*]]
17499 // CHECK15:       omp.inner.for.cond25:
17500 // CHECK15-NEXT:    [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV23]], align 4, !llvm.access.group !11
17501 // CHECK15-NEXT:    [[TMP20:%.*]] = load i32, i32* [[DOTOMP_UB22]], align 4, !llvm.access.group !11
17502 // CHECK15-NEXT:    [[CMP26:%.*]] = icmp sle i32 [[TMP19]], [[TMP20]]
17503 // CHECK15-NEXT:    br i1 [[CMP26]], label [[OMP_INNER_FOR_BODY27:%.*]], label [[OMP_INNER_FOR_END35:%.*]]
17504 // CHECK15:       omp.inner.for.body27:
17505 // CHECK15-NEXT:    [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV23]], align 4, !llvm.access.group !11
17506 // CHECK15-NEXT:    [[MUL28:%.*]] = mul nsw i32 [[TMP21]], 1
17507 // CHECK15-NEXT:    [[ADD29:%.*]] = add nsw i32 0, [[MUL28]]
17508 // CHECK15-NEXT:    store i32 [[ADD29]], i32* [[I24]], align 4, !llvm.access.group !11
17509 // CHECK15-NEXT:    [[TMP22:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !11
17510 // CHECK15-NEXT:    [[CONV:%.*]] = sext i16 [[TMP22]] to i32
17511 // CHECK15-NEXT:    [[ADD30:%.*]] = add nsw i32 [[CONV]], 1
17512 // CHECK15-NEXT:    [[CONV31:%.*]] = trunc i32 [[ADD30]] to i16
17513 // CHECK15-NEXT:    store i16 [[CONV31]], i16* [[AA]], align 2, !llvm.access.group !11
17514 // CHECK15-NEXT:    br label [[OMP_BODY_CONTINUE32:%.*]]
17515 // CHECK15:       omp.body.continue32:
17516 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_INC33:%.*]]
17517 // CHECK15:       omp.inner.for.inc33:
17518 // CHECK15-NEXT:    [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV23]], align 4, !llvm.access.group !11
17519 // CHECK15-NEXT:    [[ADD34:%.*]] = add nsw i32 [[TMP23]], 1
17520 // CHECK15-NEXT:    store i32 [[ADD34]], i32* [[DOTOMP_IV23]], align 4, !llvm.access.group !11
17521 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_COND25]], !llvm.loop [[LOOP12:![0-9]+]]
17522 // CHECK15:       omp.inner.for.end35:
17523 // CHECK15-NEXT:    store i32 10, i32* [[I24]], align 4
17524 // CHECK15-NEXT:    store i32 0, i32* [[DOTOMP_LB37]], align 4
17525 // CHECK15-NEXT:    store i32 9, i32* [[DOTOMP_UB38]], align 4
17526 // CHECK15-NEXT:    [[TMP24:%.*]] = load i32, i32* [[DOTOMP_LB37]], align 4
17527 // CHECK15-NEXT:    store i32 [[TMP24]], i32* [[DOTOMP_IV39]], align 4
17528 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_COND41:%.*]]
17529 // CHECK15:       omp.inner.for.cond41:
17530 // CHECK15-NEXT:    [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IV39]], align 4, !llvm.access.group !14
17531 // CHECK15-NEXT:    [[TMP26:%.*]] = load i32, i32* [[DOTOMP_UB38]], align 4, !llvm.access.group !14
17532 // CHECK15-NEXT:    [[CMP42:%.*]] = icmp sle i32 [[TMP25]], [[TMP26]]
17533 // CHECK15-NEXT:    br i1 [[CMP42]], label [[OMP_INNER_FOR_BODY43:%.*]], label [[OMP_INNER_FOR_END53:%.*]]
17534 // CHECK15:       omp.inner.for.body43:
17535 // CHECK15-NEXT:    [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV39]], align 4, !llvm.access.group !14
17536 // CHECK15-NEXT:    [[MUL44:%.*]] = mul nsw i32 [[TMP27]], 1
17537 // CHECK15-NEXT:    [[ADD45:%.*]] = add nsw i32 0, [[MUL44]]
17538 // CHECK15-NEXT:    store i32 [[ADD45]], i32* [[I40]], align 4, !llvm.access.group !14
17539 // CHECK15-NEXT:    [[TMP28:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !14
17540 // CHECK15-NEXT:    [[ADD46:%.*]] = add nsw i32 [[TMP28]], 1
17541 // CHECK15-NEXT:    store i32 [[ADD46]], i32* [[A]], align 4, !llvm.access.group !14
17542 // CHECK15-NEXT:    [[TMP29:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !14
17543 // CHECK15-NEXT:    [[CONV47:%.*]] = sext i16 [[TMP29]] to i32
17544 // CHECK15-NEXT:    [[ADD48:%.*]] = add nsw i32 [[CONV47]], 1
17545 // CHECK15-NEXT:    [[CONV49:%.*]] = trunc i32 [[ADD48]] to i16
17546 // CHECK15-NEXT:    store i16 [[CONV49]], i16* [[AA]], align 2, !llvm.access.group !14
17547 // CHECK15-NEXT:    br label [[OMP_BODY_CONTINUE50:%.*]]
17548 // CHECK15:       omp.body.continue50:
17549 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_INC51:%.*]]
17550 // CHECK15:       omp.inner.for.inc51:
17551 // CHECK15-NEXT:    [[TMP30:%.*]] = load i32, i32* [[DOTOMP_IV39]], align 4, !llvm.access.group !14
17552 // CHECK15-NEXT:    [[ADD52:%.*]] = add nsw i32 [[TMP30]], 1
17553 // CHECK15-NEXT:    store i32 [[ADD52]], i32* [[DOTOMP_IV39]], align 4, !llvm.access.group !14
17554 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_COND41]], !llvm.loop [[LOOP15:![0-9]+]]
17555 // CHECK15:       omp.inner.for.end53:
17556 // CHECK15-NEXT:    store i32 10, i32* [[I40]], align 4
17557 // CHECK15-NEXT:    store i32 0, i32* [[DOTOMP_LB55]], align 4
17558 // CHECK15-NEXT:    store i32 9, i32* [[DOTOMP_UB56]], align 4
17559 // CHECK15-NEXT:    [[TMP31:%.*]] = load i32, i32* [[DOTOMP_LB55]], align 4
17560 // CHECK15-NEXT:    store i32 [[TMP31]], i32* [[DOTOMP_IV57]], align 4
17561 // CHECK15-NEXT:    [[ARRAYDECAY:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 0
17562 // CHECK15-NEXT:    call void @llvm.assume(i1 true) [ "align"(float* [[ARRAYDECAY]], i32 16) ]
17563 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_COND59:%.*]]
17564 // CHECK15:       omp.inner.for.cond59:
17565 // CHECK15-NEXT:    [[TMP32:%.*]] = load i32, i32* [[DOTOMP_IV57]], align 4, !llvm.access.group !17
17566 // CHECK15-NEXT:    [[TMP33:%.*]] = load i32, i32* [[DOTOMP_UB56]], align 4, !llvm.access.group !17
17567 // CHECK15-NEXT:    [[CMP60:%.*]] = icmp sle i32 [[TMP32]], [[TMP33]]
17568 // CHECK15-NEXT:    br i1 [[CMP60]], label [[OMP_INNER_FOR_BODY61:%.*]], label [[OMP_INNER_FOR_END85:%.*]]
17569 // CHECK15:       omp.inner.for.body61:
17570 // CHECK15-NEXT:    [[TMP34:%.*]] = load i32, i32* [[DOTOMP_IV57]], align 4, !llvm.access.group !17
17571 // CHECK15-NEXT:    [[MUL62:%.*]] = mul nsw i32 [[TMP34]], 1
17572 // CHECK15-NEXT:    [[ADD63:%.*]] = add nsw i32 0, [[MUL62]]
17573 // CHECK15-NEXT:    store i32 [[ADD63]], i32* [[I58]], align 4, !llvm.access.group !17
17574 // CHECK15-NEXT:    [[TMP35:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !17
17575 // CHECK15-NEXT:    [[ADD64:%.*]] = add nsw i32 [[TMP35]], 1
17576 // CHECK15-NEXT:    store i32 [[ADD64]], i32* [[A]], align 4, !llvm.access.group !17
17577 // CHECK15-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2
17578 // CHECK15-NEXT:    [[TMP36:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !17
17579 // CHECK15-NEXT:    [[CONV65:%.*]] = fpext float [[TMP36]] to double
17580 // CHECK15-NEXT:    [[ADD66:%.*]] = fadd double [[CONV65]], 1.000000e+00
17581 // CHECK15-NEXT:    [[CONV67:%.*]] = fptrunc double [[ADD66]] to float
17582 // CHECK15-NEXT:    store float [[CONV67]], float* [[ARRAYIDX]], align 4, !llvm.access.group !17
17583 // CHECK15-NEXT:    [[ARRAYIDX68:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3
17584 // CHECK15-NEXT:    [[TMP37:%.*]] = load float, float* [[ARRAYIDX68]], align 4, !llvm.access.group !17
17585 // CHECK15-NEXT:    [[CONV69:%.*]] = fpext float [[TMP37]] to double
17586 // CHECK15-NEXT:    [[ADD70:%.*]] = fadd double [[CONV69]], 1.000000e+00
17587 // CHECK15-NEXT:    [[CONV71:%.*]] = fptrunc double [[ADD70]] to float
17588 // CHECK15-NEXT:    store float [[CONV71]], float* [[ARRAYIDX68]], align 4, !llvm.access.group !17
17589 // CHECK15-NEXT:    [[ARRAYIDX72:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1
17590 // CHECK15-NEXT:    [[ARRAYIDX73:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX72]], i32 0, i32 2
17591 // CHECK15-NEXT:    [[TMP38:%.*]] = load double, double* [[ARRAYIDX73]], align 8, !llvm.access.group !17
17592 // CHECK15-NEXT:    [[ADD74:%.*]] = fadd double [[TMP38]], 1.000000e+00
17593 // CHECK15-NEXT:    store double [[ADD74]], double* [[ARRAYIDX73]], align 8, !llvm.access.group !17
17594 // CHECK15-NEXT:    [[TMP39:%.*]] = mul nsw i32 1, [[TMP2]]
17595 // CHECK15-NEXT:    [[ARRAYIDX75:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP39]]
17596 // CHECK15-NEXT:    [[ARRAYIDX76:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX75]], i32 3
17597 // CHECK15-NEXT:    [[TMP40:%.*]] = load double, double* [[ARRAYIDX76]], align 8, !llvm.access.group !17
17598 // CHECK15-NEXT:    [[ADD77:%.*]] = fadd double [[TMP40]], 1.000000e+00
17599 // CHECK15-NEXT:    store double [[ADD77]], double* [[ARRAYIDX76]], align 8, !llvm.access.group !17
17600 // CHECK15-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0
17601 // CHECK15-NEXT:    [[TMP41:%.*]] = load i64, i64* [[X]], align 4, !llvm.access.group !17
17602 // CHECK15-NEXT:    [[ADD78:%.*]] = add nsw i64 [[TMP41]], 1
17603 // CHECK15-NEXT:    store i64 [[ADD78]], i64* [[X]], align 4, !llvm.access.group !17
17604 // CHECK15-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1
17605 // CHECK15-NEXT:    [[TMP42:%.*]] = load i8, i8* [[Y]], align 4, !llvm.access.group !17
17606 // CHECK15-NEXT:    [[CONV79:%.*]] = sext i8 [[TMP42]] to i32
17607 // CHECK15-NEXT:    [[ADD80:%.*]] = add nsw i32 [[CONV79]], 1
17608 // CHECK15-NEXT:    [[CONV81:%.*]] = trunc i32 [[ADD80]] to i8
17609 // CHECK15-NEXT:    store i8 [[CONV81]], i8* [[Y]], align 4, !llvm.access.group !17
17610 // CHECK15-NEXT:    br label [[OMP_BODY_CONTINUE82:%.*]]
17611 // CHECK15:       omp.body.continue82:
17612 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_INC83:%.*]]
17613 // CHECK15:       omp.inner.for.inc83:
17614 // CHECK15-NEXT:    [[TMP43:%.*]] = load i32, i32* [[DOTOMP_IV57]], align 4, !llvm.access.group !17
17615 // CHECK15-NEXT:    [[ADD84:%.*]] = add nsw i32 [[TMP43]], 1
17616 // CHECK15-NEXT:    store i32 [[ADD84]], i32* [[DOTOMP_IV57]], align 4, !llvm.access.group !17
17617 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_COND59]], !llvm.loop [[LOOP18:![0-9]+]]
17618 // CHECK15:       omp.inner.for.end85:
17619 // CHECK15-NEXT:    store i32 10, i32* [[I58]], align 4
17620 // CHECK15-NEXT:    [[TMP44:%.*]] = load i32, i32* [[A]], align 4
17621 // CHECK15-NEXT:    [[TMP45:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
17622 // CHECK15-NEXT:    call void @llvm.stackrestore(i8* [[TMP45]])
17623 // CHECK15-NEXT:    ret i32 [[TMP44]]
17624 //
17625 //
17626 // CHECK15-LABEL: define {{[^@]+}}@_Z3bari
17627 // CHECK15-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {
17628 // CHECK15-NEXT:  entry:
17629 // CHECK15-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
17630 // CHECK15-NEXT:    [[A:%.*]] = alloca i32, align 4
17631 // CHECK15-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4
17632 // CHECK15-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
17633 // CHECK15-NEXT:    store i32 0, i32* [[A]], align 4
17634 // CHECK15-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
17635 // CHECK15-NEXT:    [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]])
17636 // CHECK15-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
17637 // CHECK15-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
17638 // CHECK15-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
17639 // CHECK15-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
17640 // CHECK15-NEXT:    [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP2]])
17641 // CHECK15-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
17642 // CHECK15-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
17643 // CHECK15-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
17644 // CHECK15-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
17645 // CHECK15-NEXT:    [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]])
17646 // CHECK15-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
17647 // CHECK15-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
17648 // CHECK15-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
17649 // CHECK15-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
17650 // CHECK15-NEXT:    [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]])
17651 // CHECK15-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
17652 // CHECK15-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
17653 // CHECK15-NEXT:    store i32 [[ADD6]], i32* [[A]], align 4
17654 // CHECK15-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
17655 // CHECK15-NEXT:    ret i32 [[TMP8]]
17656 //
17657 //
17658 // CHECK15-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
17659 // CHECK15-SAME: (%struct.S1* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 {
17660 // CHECK15-NEXT:  entry:
17661 // CHECK15-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
17662 // CHECK15-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
17663 // CHECK15-NEXT:    [[B:%.*]] = alloca i32, align 4
17664 // CHECK15-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 4
17665 // CHECK15-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 4
17666 // CHECK15-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
17667 // CHECK15-NEXT:    [[TMP:%.*]] = alloca i32, align 4
17668 // CHECK15-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
17669 // CHECK15-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
17670 // CHECK15-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
17671 // CHECK15-NEXT:    [[I:%.*]] = alloca i32, align 4
17672 // CHECK15-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
17673 // CHECK15-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
17674 // CHECK15-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
17675 // CHECK15-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
17676 // CHECK15-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
17677 // CHECK15-NEXT:    store i32 [[ADD]], i32* [[B]], align 4
17678 // CHECK15-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
17679 // CHECK15-NEXT:    [[TMP2:%.*]] = call i8* @llvm.stacksave()
17680 // CHECK15-NEXT:    store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4
17681 // CHECK15-NEXT:    [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]
17682 // CHECK15-NEXT:    [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2
17683 // CHECK15-NEXT:    store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
17684 // CHECK15-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
17685 // CHECK15-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 60
17686 // CHECK15-NEXT:    [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8
17687 // CHECK15-NEXT:    store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
17688 // CHECK15-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
17689 // CHECK15-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
17690 // CHECK15-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
17691 // CHECK15-NEXT:    store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
17692 // CHECK15-NEXT:    [[TMP6:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
17693 // CHECK15-NEXT:    [[TOBOOL:%.*]] = trunc i8 [[TMP6]] to i1
17694 // CHECK15-NEXT:    br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
17695 // CHECK15:       omp_if.then:
17696 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
17697 // CHECK15:       omp.inner.for.cond:
17698 // CHECK15-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20
17699 // CHECK15-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !20
17700 // CHECK15-NEXT:    [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
17701 // CHECK15-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
17702 // CHECK15:       omp.inner.for.body:
17703 // CHECK15-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20
17704 // CHECK15-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
17705 // CHECK15-NEXT:    [[ADD3:%.*]] = add nsw i32 0, [[MUL]]
17706 // CHECK15-NEXT:    store i32 [[ADD3]], i32* [[I]], align 4, !llvm.access.group !20
17707 // CHECK15-NEXT:    [[TMP10:%.*]] = load i32, i32* [[B]], align 4, !llvm.access.group !20
17708 // CHECK15-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP10]] to double
17709 // CHECK15-NEXT:    [[ADD4:%.*]] = fadd double [[CONV]], 1.500000e+00
17710 // CHECK15-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
17711 // CHECK15-NEXT:    store double [[ADD4]], double* [[A]], align 4, !llvm.access.group !20
17712 // CHECK15-NEXT:    [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
17713 // CHECK15-NEXT:    [[TMP11:%.*]] = load double, double* [[A5]], align 4, !llvm.access.group !20
17714 // CHECK15-NEXT:    [[INC:%.*]] = fadd double [[TMP11]], 1.000000e+00
17715 // CHECK15-NEXT:    store double [[INC]], double* [[A5]], align 4, !llvm.access.group !20
17716 // CHECK15-NEXT:    [[CONV6:%.*]] = fptosi double [[INC]] to i16
17717 // CHECK15-NEXT:    [[TMP12:%.*]] = mul nsw i32 1, [[TMP1]]
17718 // CHECK15-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP12]]
17719 // CHECK15-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
17720 // CHECK15-NEXT:    store i16 [[CONV6]], i16* [[ARRAYIDX7]], align 2, !llvm.access.group !20
17721 // CHECK15-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
17722 // CHECK15:       omp.body.continue:
17723 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
17724 // CHECK15:       omp.inner.for.inc:
17725 // CHECK15-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20
17726 // CHECK15-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP13]], 1
17727 // CHECK15-NEXT:    store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20
17728 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]]
17729 // CHECK15:       omp.inner.for.end:
17730 // CHECK15-NEXT:    br label [[OMP_IF_END:%.*]]
17731 // CHECK15:       omp_if.else:
17732 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_COND9:%.*]]
17733 // CHECK15:       omp.inner.for.cond9:
17734 // CHECK15-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
17735 // CHECK15-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
17736 // CHECK15-NEXT:    [[CMP10:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
17737 // CHECK15-NEXT:    br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY11:%.*]], label [[OMP_INNER_FOR_END25:%.*]]
17738 // CHECK15:       omp.inner.for.body11:
17739 // CHECK15-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
17740 // CHECK15-NEXT:    [[MUL12:%.*]] = mul nsw i32 [[TMP16]], 1
17741 // CHECK15-NEXT:    [[ADD13:%.*]] = add nsw i32 0, [[MUL12]]
17742 // CHECK15-NEXT:    store i32 [[ADD13]], i32* [[I]], align 4
17743 // CHECK15-NEXT:    [[TMP17:%.*]] = load i32, i32* [[B]], align 4
17744 // CHECK15-NEXT:    [[CONV14:%.*]] = sitofp i32 [[TMP17]] to double
17745 // CHECK15-NEXT:    [[ADD15:%.*]] = fadd double [[CONV14]], 1.500000e+00
17746 // CHECK15-NEXT:    [[A16:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
17747 // CHECK15-NEXT:    store double [[ADD15]], double* [[A16]], align 4
17748 // CHECK15-NEXT:    [[A17:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
17749 // CHECK15-NEXT:    [[TMP18:%.*]] = load double, double* [[A17]], align 4
17750 // CHECK15-NEXT:    [[INC18:%.*]] = fadd double [[TMP18]], 1.000000e+00
17751 // CHECK15-NEXT:    store double [[INC18]], double* [[A17]], align 4
17752 // CHECK15-NEXT:    [[CONV19:%.*]] = fptosi double [[INC18]] to i16
17753 // CHECK15-NEXT:    [[TMP19:%.*]] = mul nsw i32 1, [[TMP1]]
17754 // CHECK15-NEXT:    [[ARRAYIDX20:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP19]]
17755 // CHECK15-NEXT:    [[ARRAYIDX21:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX20]], i32 1
17756 // CHECK15-NEXT:    store i16 [[CONV19]], i16* [[ARRAYIDX21]], align 2
17757 // CHECK15-NEXT:    br label [[OMP_BODY_CONTINUE22:%.*]]
17758 // CHECK15:       omp.body.continue22:
17759 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_INC23:%.*]]
17760 // CHECK15:       omp.inner.for.inc23:
17761 // CHECK15-NEXT:    [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
17762 // CHECK15-NEXT:    [[ADD24:%.*]] = add nsw i32 [[TMP20]], 1
17763 // CHECK15-NEXT:    store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4
17764 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_COND9]], !llvm.loop [[LOOP23:![0-9]+]]
17765 // CHECK15:       omp.inner.for.end25:
17766 // CHECK15-NEXT:    br label [[OMP_IF_END]]
17767 // CHECK15:       omp_if.end:
17768 // CHECK15-NEXT:    store i32 10, i32* [[I]], align 4
17769 // CHECK15-NEXT:    [[TMP21:%.*]] = mul nsw i32 1, [[TMP1]]
17770 // CHECK15-NEXT:    [[ARRAYIDX26:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP21]]
17771 // CHECK15-NEXT:    [[ARRAYIDX27:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX26]], i32 1
17772 // CHECK15-NEXT:    [[TMP22:%.*]] = load i16, i16* [[ARRAYIDX27]], align 2
17773 // CHECK15-NEXT:    [[CONV28:%.*]] = sext i16 [[TMP22]] to i32
17774 // CHECK15-NEXT:    [[TMP23:%.*]] = load i32, i32* [[B]], align 4
17775 // CHECK15-NEXT:    [[ADD29:%.*]] = add nsw i32 [[CONV28]], [[TMP23]]
17776 // CHECK15-NEXT:    [[TMP24:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
17777 // CHECK15-NEXT:    call void @llvm.stackrestore(i8* [[TMP24]])
17778 // CHECK15-NEXT:    ret i32 [[ADD29]]
17779 //
17780 //
17781 // CHECK15-LABEL: define {{[^@]+}}@_ZL7fstatici
17782 // CHECK15-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {
17783 // CHECK15-NEXT:  entry:
17784 // CHECK15-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
17785 // CHECK15-NEXT:    [[A:%.*]] = alloca i32, align 4
17786 // CHECK15-NEXT:    [[AA:%.*]] = alloca i16, align 2
17787 // CHECK15-NEXT:    [[AAA:%.*]] = alloca i8, align 1
17788 // CHECK15-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
17789 // CHECK15-NEXT:    [[TMP:%.*]] = alloca i32, align 4
17790 // CHECK15-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
17791 // CHECK15-NEXT:    [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
17792 // CHECK15-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
17793 // CHECK15-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
17794 // CHECK15-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
17795 // CHECK15-NEXT:    [[I:%.*]] = alloca i32, align 4
17796 // CHECK15-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
17797 // CHECK15-NEXT:    [[I5:%.*]] = alloca i32, align 4
17798 // CHECK15-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
17799 // CHECK15-NEXT:    store i32 0, i32* [[A]], align 4
17800 // CHECK15-NEXT:    store i16 0, i16* [[AA]], align 2
17801 // CHECK15-NEXT:    store i8 0, i8* [[AAA]], align 1
17802 // CHECK15-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
17803 // CHECK15-NEXT:    store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4
17804 // CHECK15-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
17805 // CHECK15-NEXT:    store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_1]], align 4
17806 // CHECK15-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
17807 // CHECK15-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
17808 // CHECK15-NEXT:    [[SUB:%.*]] = sub i32 [[TMP2]], [[TMP3]]
17809 // CHECK15-NEXT:    [[SUB3:%.*]] = sub i32 [[SUB]], 1
17810 // CHECK15-NEXT:    [[ADD:%.*]] = add i32 [[SUB3]], 1
17811 // CHECK15-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], 1
17812 // CHECK15-NEXT:    [[SUB4:%.*]] = sub i32 [[DIV]], 1
17813 // CHECK15-NEXT:    store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_2]], align 4
17814 // CHECK15-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
17815 // CHECK15-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
17816 // CHECK15-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_UB]], align 4
17817 // CHECK15-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
17818 // CHECK15-NEXT:    store i32 [[TMP5]], i32* [[I]], align 4
17819 // CHECK15-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
17820 // CHECK15-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
17821 // CHECK15-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]]
17822 // CHECK15-NEXT:    br i1 [[CMP]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END:%.*]]
17823 // CHECK15:       simd.if.then:
17824 // CHECK15-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
17825 // CHECK15-NEXT:    store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
17826 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
17827 // CHECK15:       omp.inner.for.cond:
17828 // CHECK15-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25
17829 // CHECK15-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !25
17830 // CHECK15-NEXT:    [[ADD6:%.*]] = add i32 [[TMP10]], 1
17831 // CHECK15-NEXT:    [[CMP7:%.*]] = icmp ult i32 [[TMP9]], [[ADD6]]
17832 // CHECK15-NEXT:    br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
17833 // CHECK15:       omp.inner.for.body:
17834 // CHECK15-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group !25
17835 // CHECK15-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25
17836 // CHECK15-NEXT:    [[MUL:%.*]] = mul i32 [[TMP12]], 1
17837 // CHECK15-NEXT:    [[ADD8:%.*]] = add i32 [[TMP11]], [[MUL]]
17838 // CHECK15-NEXT:    store i32 [[ADD8]], i32* [[I5]], align 4, !llvm.access.group !25
17839 // CHECK15-NEXT:    [[TMP13:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !25
17840 // CHECK15-NEXT:    [[ADD9:%.*]] = add nsw i32 [[TMP13]], 1
17841 // CHECK15-NEXT:    store i32 [[ADD9]], i32* [[A]], align 4, !llvm.access.group !25
17842 // CHECK15-NEXT:    [[TMP14:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !25
17843 // CHECK15-NEXT:    [[CONV:%.*]] = sext i16 [[TMP14]] to i32
17844 // CHECK15-NEXT:    [[ADD10:%.*]] = add nsw i32 [[CONV]], 1
17845 // CHECK15-NEXT:    [[CONV11:%.*]] = trunc i32 [[ADD10]] to i16
17846 // CHECK15-NEXT:    store i16 [[CONV11]], i16* [[AA]], align 2, !llvm.access.group !25
17847 // CHECK15-NEXT:    [[TMP15:%.*]] = load i8, i8* [[AAA]], align 1, !llvm.access.group !25
17848 // CHECK15-NEXT:    [[CONV12:%.*]] = sext i8 [[TMP15]] to i32
17849 // CHECK15-NEXT:    [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1
17850 // CHECK15-NEXT:    [[CONV14:%.*]] = trunc i32 [[ADD13]] to i8
17851 // CHECK15-NEXT:    store i8 [[CONV14]], i8* [[AAA]], align 1, !llvm.access.group !25
17852 // CHECK15-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2
17853 // CHECK15-NEXT:    [[TMP16:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !25
17854 // CHECK15-NEXT:    [[ADD15:%.*]] = add nsw i32 [[TMP16]], 1
17855 // CHECK15-NEXT:    store i32 [[ADD15]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !25
17856 // CHECK15-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
17857 // CHECK15:       omp.body.continue:
17858 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
17859 // CHECK15:       omp.inner.for.inc:
17860 // CHECK15-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25
17861 // CHECK15-NEXT:    [[ADD16:%.*]] = add i32 [[TMP17]], 1
17862 // CHECK15-NEXT:    store i32 [[ADD16]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25
17863 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP26:![0-9]+]]
17864 // CHECK15:       omp.inner.for.end:
17865 // CHECK15-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
17866 // CHECK15-NEXT:    [[TMP19:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
17867 // CHECK15-NEXT:    [[TMP20:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
17868 // CHECK15-NEXT:    [[SUB17:%.*]] = sub i32 [[TMP19]], [[TMP20]]
17869 // CHECK15-NEXT:    [[SUB18:%.*]] = sub i32 [[SUB17]], 1
17870 // CHECK15-NEXT:    [[ADD19:%.*]] = add i32 [[SUB18]], 1
17871 // CHECK15-NEXT:    [[DIV20:%.*]] = udiv i32 [[ADD19]], 1
17872 // CHECK15-NEXT:    [[MUL21:%.*]] = mul i32 [[DIV20]], 1
17873 // CHECK15-NEXT:    [[ADD22:%.*]] = add i32 [[TMP18]], [[MUL21]]
17874 // CHECK15-NEXT:    store i32 [[ADD22]], i32* [[I5]], align 4
17875 // CHECK15-NEXT:    br label [[SIMD_IF_END]]
17876 // CHECK15:       simd.if.end:
17877 // CHECK15-NEXT:    [[TMP21:%.*]] = load i32, i32* [[A]], align 4
17878 // CHECK15-NEXT:    ret i32 [[TMP21]]
17879 //
17880 //
17881 // CHECK15-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
17882 // CHECK15-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat {
17883 // CHECK15-NEXT:  entry:
17884 // CHECK15-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
17885 // CHECK15-NEXT:    [[A:%.*]] = alloca i32, align 4
17886 // CHECK15-NEXT:    [[AA:%.*]] = alloca i16, align 2
17887 // CHECK15-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
17888 // CHECK15-NEXT:    [[TMP:%.*]] = alloca i32, align 4
17889 // CHECK15-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
17890 // CHECK15-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
17891 // CHECK15-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
17892 // CHECK15-NEXT:    [[I:%.*]] = alloca i32, align 4
17893 // CHECK15-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
17894 // CHECK15-NEXT:    store i32 0, i32* [[A]], align 4
17895 // CHECK15-NEXT:    store i16 0, i16* [[AA]], align 2
17896 // CHECK15-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
17897 // CHECK15-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
17898 // CHECK15-NEXT:    [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
17899 // CHECK15-NEXT:    store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4
17900 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
17901 // CHECK15:       omp.inner.for.cond:
17902 // CHECK15-NEXT:    [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28
17903 // CHECK15-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !28
17904 // CHECK15-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
17905 // CHECK15-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
17906 // CHECK15:       omp.inner.for.body:
17907 // CHECK15-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28
17908 // CHECK15-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1
17909 // CHECK15-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
17910 // CHECK15-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !28
17911 // CHECK15-NEXT:    [[TMP4:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !28
17912 // CHECK15-NEXT:    [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1
17913 // CHECK15-NEXT:    store i32 [[ADD1]], i32* [[A]], align 4, !llvm.access.group !28
17914 // CHECK15-NEXT:    [[TMP5:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !28
17915 // CHECK15-NEXT:    [[CONV:%.*]] = sext i16 [[TMP5]] to i32
17916 // CHECK15-NEXT:    [[ADD2:%.*]] = add nsw i32 [[CONV]], 1
17917 // CHECK15-NEXT:    [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
17918 // CHECK15-NEXT:    store i16 [[CONV3]], i16* [[AA]], align 2, !llvm.access.group !28
17919 // CHECK15-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2
17920 // CHECK15-NEXT:    [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !28
17921 // CHECK15-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP6]], 1
17922 // CHECK15-NEXT:    store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !28
17923 // CHECK15-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
17924 // CHECK15:       omp.body.continue:
17925 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
17926 // CHECK15:       omp.inner.for.inc:
17927 // CHECK15-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28
17928 // CHECK15-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP7]], 1
17929 // CHECK15-NEXT:    store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28
17930 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP29:![0-9]+]]
17931 // CHECK15:       omp.inner.for.end:
17932 // CHECK15-NEXT:    store i32 10, i32* [[I]], align 4
17933 // CHECK15-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
17934 // CHECK15-NEXT:    ret i32 [[TMP8]]
17935 //
17936 //
17937 // CHECK16-LABEL: define {{[^@]+}}@_Z3fooi
17938 // CHECK16-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0:[0-9]+]] {
17939 // CHECK16-NEXT:  entry:
17940 // CHECK16-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
17941 // CHECK16-NEXT:    [[A:%.*]] = alloca i32, align 4
17942 // CHECK16-NEXT:    [[AA:%.*]] = alloca i16, align 2
17943 // CHECK16-NEXT:    [[B:%.*]] = alloca [10 x float], align 4
17944 // CHECK16-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 4
17945 // CHECK16-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 4
17946 // CHECK16-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 8
17947 // CHECK16-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i32, align 4
17948 // CHECK16-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4
17949 // CHECK16-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
17950 // CHECK16-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
17951 // CHECK16-NEXT:    [[TMP:%.*]] = alloca i32, align 4
17952 // CHECK16-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
17953 // CHECK16-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
17954 // CHECK16-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
17955 // CHECK16-NEXT:    [[I:%.*]] = alloca i32, align 4
17956 // CHECK16-NEXT:    [[_TMP4:%.*]] = alloca i32, align 4
17957 // CHECK16-NEXT:    [[DOTOMP_LB5:%.*]] = alloca i32, align 4
17958 // CHECK16-NEXT:    [[DOTOMP_UB6:%.*]] = alloca i32, align 4
17959 // CHECK16-NEXT:    [[DOTOMP_IV7:%.*]] = alloca i32, align 4
17960 // CHECK16-NEXT:    [[DOTLINEAR_START:%.*]] = alloca i32, align 4
17961 // CHECK16-NEXT:    [[A8:%.*]] = alloca i32, align 4
17962 // CHECK16-NEXT:    [[A9:%.*]] = alloca i32, align 4
17963 // CHECK16-NEXT:    [[_TMP20:%.*]] = alloca i32, align 4
17964 // CHECK16-NEXT:    [[DOTOMP_LB21:%.*]] = alloca i32, align 4
17965 // CHECK16-NEXT:    [[DOTOMP_UB22:%.*]] = alloca i32, align 4
17966 // CHECK16-NEXT:    [[DOTOMP_IV23:%.*]] = alloca i32, align 4
17967 // CHECK16-NEXT:    [[I24:%.*]] = alloca i32, align 4
17968 // CHECK16-NEXT:    [[_TMP36:%.*]] = alloca i32, align 4
17969 // CHECK16-NEXT:    [[DOTOMP_LB37:%.*]] = alloca i32, align 4
17970 // CHECK16-NEXT:    [[DOTOMP_UB38:%.*]] = alloca i32, align 4
17971 // CHECK16-NEXT:    [[DOTOMP_IV39:%.*]] = alloca i32, align 4
17972 // CHECK16-NEXT:    [[I40:%.*]] = alloca i32, align 4
17973 // CHECK16-NEXT:    [[_TMP54:%.*]] = alloca i32, align 4
17974 // CHECK16-NEXT:    [[DOTOMP_LB55:%.*]] = alloca i32, align 4
17975 // CHECK16-NEXT:    [[DOTOMP_UB56:%.*]] = alloca i32, align 4
17976 // CHECK16-NEXT:    [[DOTOMP_IV57:%.*]] = alloca i32, align 4
17977 // CHECK16-NEXT:    [[I58:%.*]] = alloca i32, align 4
17978 // CHECK16-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
17979 // CHECK16-NEXT:    store i32 0, i32* [[A]], align 4
17980 // CHECK16-NEXT:    store i16 0, i16* [[AA]], align 2
17981 // CHECK16-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
17982 // CHECK16-NEXT:    [[TMP1:%.*]] = call i8* @llvm.stacksave()
17983 // CHECK16-NEXT:    store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4
17984 // CHECK16-NEXT:    [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4
17985 // CHECK16-NEXT:    store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4
17986 // CHECK16-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
17987 // CHECK16-NEXT:    [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]]
17988 // CHECK16-NEXT:    [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8
17989 // CHECK16-NEXT:    store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4
17990 // CHECK16-NEXT:    [[TMP4:%.*]] = load i32, i32* [[A]], align 4
17991 // CHECK16-NEXT:    store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4
17992 // CHECK16-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
17993 // CHECK16-NEXT:    store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_2]], align 4
17994 // CHECK16-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
17995 // CHECK16-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
17996 // CHECK16-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
17997 // CHECK16-NEXT:    store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
17998 // CHECK16-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
17999 // CHECK16:       omp.inner.for.cond:
18000 // CHECK16-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
18001 // CHECK16-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !3
18002 // CHECK16-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
18003 // CHECK16-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
18004 // CHECK16:       omp.inner.for.body:
18005 // CHECK16-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
18006 // CHECK16-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
18007 // CHECK16-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
18008 // CHECK16-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !3
18009 // CHECK16-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
18010 // CHECK16:       omp.body.continue:
18011 // CHECK16-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
18012 // CHECK16:       omp.inner.for.inc:
18013 // CHECK16-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
18014 // CHECK16-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
18015 // CHECK16-NEXT:    store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
18016 // CHECK16-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]
18017 // CHECK16:       omp.inner.for.end:
18018 // CHECK16-NEXT:    store i32 10, i32* [[I]], align 4
18019 // CHECK16-NEXT:    store i32 0, i32* [[DOTOMP_LB5]], align 4
18020 // CHECK16-NEXT:    store i32 9, i32* [[DOTOMP_UB6]], align 4
18021 // CHECK16-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_LB5]], align 4
18022 // CHECK16-NEXT:    store i32 [[TMP11]], i32* [[DOTOMP_IV7]], align 4
18023 // CHECK16-NEXT:    [[TMP12:%.*]] = load i32, i32* [[A]], align 4
18024 // CHECK16-NEXT:    store i32 [[TMP12]], i32* [[DOTLINEAR_START]], align 4
18025 // CHECK16-NEXT:    br label [[OMP_INNER_FOR_COND10:%.*]]
18026 // CHECK16:       omp.inner.for.cond10:
18027 // CHECK16-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV7]], align 4
18028 // CHECK16-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB6]], align 4
18029 // CHECK16-NEXT:    [[CMP11:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
18030 // CHECK16-NEXT:    br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY12:%.*]], label [[OMP_INNER_FOR_END19:%.*]]
18031 // CHECK16:       omp.inner.for.body12:
18032 // CHECK16-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV7]], align 4
18033 // CHECK16-NEXT:    [[MUL13:%.*]] = mul nsw i32 [[TMP15]], 1
18034 // CHECK16-NEXT:    [[ADD14:%.*]] = add nsw i32 0, [[MUL13]]
18035 // CHECK16-NEXT:    store i32 [[ADD14]], i32* [[A8]], align 4, !nontemporal !8
18036 // CHECK16-NEXT:    [[TMP16:%.*]] = load i32, i32* [[A8]], align 4, !nontemporal !8
18037 // CHECK16-NEXT:    [[ADD15:%.*]] = add nsw i32 [[TMP16]], 1
18038 // CHECK16-NEXT:    store i32 [[ADD15]], i32* [[A8]], align 4, !nontemporal !8
18039 // CHECK16-NEXT:    br label [[OMP_BODY_CONTINUE16:%.*]]
18040 // CHECK16:       omp.body.continue16:
18041 // CHECK16-NEXT:    br label [[OMP_INNER_FOR_INC17:%.*]]
18042 // CHECK16:       omp.inner.for.inc17:
18043 // CHECK16-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV7]], align 4
18044 // CHECK16-NEXT:    [[ADD18:%.*]] = add nsw i32 [[TMP17]], 1
18045 // CHECK16-NEXT:    store i32 [[ADD18]], i32* [[DOTOMP_IV7]], align 4
18046 // CHECK16-NEXT:    br label [[OMP_INNER_FOR_COND10]], !llvm.loop [[LOOP9:![0-9]+]]
18047 // CHECK16:       omp.inner.for.end19:
18048 // CHECK16-NEXT:    store i32 10, i32* [[A]], align 4
18049 // CHECK16-NEXT:    store i32 0, i32* [[DOTOMP_LB21]], align 4
18050 // CHECK16-NEXT:    store i32 9, i32* [[DOTOMP_UB22]], align 4
18051 // CHECK16-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTOMP_LB21]], align 4
18052 // CHECK16-NEXT:    store i32 [[TMP18]], i32* [[DOTOMP_IV23]], align 4
18053 // CHECK16-NEXT:    br label [[OMP_INNER_FOR_COND25:%.*]]
18054 // CHECK16:       omp.inner.for.cond25:
18055 // CHECK16-NEXT:    [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV23]], align 4, !llvm.access.group !11
18056 // CHECK16-NEXT:    [[TMP20:%.*]] = load i32, i32* [[DOTOMP_UB22]], align 4, !llvm.access.group !11
18057 // CHECK16-NEXT:    [[CMP26:%.*]] = icmp sle i32 [[TMP19]], [[TMP20]]
18058 // CHECK16-NEXT:    br i1 [[CMP26]], label [[OMP_INNER_FOR_BODY27:%.*]], label [[OMP_INNER_FOR_END35:%.*]]
18059 // CHECK16:       omp.inner.for.body27:
18060 // CHECK16-NEXT:    [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV23]], align 4, !llvm.access.group !11
18061 // CHECK16-NEXT:    [[MUL28:%.*]] = mul nsw i32 [[TMP21]], 1
18062 // CHECK16-NEXT:    [[ADD29:%.*]] = add nsw i32 0, [[MUL28]]
18063 // CHECK16-NEXT:    store i32 [[ADD29]], i32* [[I24]], align 4, !llvm.access.group !11
18064 // CHECK16-NEXT:    [[TMP22:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !11
18065 // CHECK16-NEXT:    [[CONV:%.*]] = sext i16 [[TMP22]] to i32
18066 // CHECK16-NEXT:    [[ADD30:%.*]] = add nsw i32 [[CONV]], 1
18067 // CHECK16-NEXT:    [[CONV31:%.*]] = trunc i32 [[ADD30]] to i16
18068 // CHECK16-NEXT:    store i16 [[CONV31]], i16* [[AA]], align 2, !llvm.access.group !11
18069 // CHECK16-NEXT:    br label [[OMP_BODY_CONTINUE32:%.*]]
18070 // CHECK16:       omp.body.continue32:
18071 // CHECK16-NEXT:    br label [[OMP_INNER_FOR_INC33:%.*]]
18072 // CHECK16:       omp.inner.for.inc33:
18073 // CHECK16-NEXT:    [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV23]], align 4, !llvm.access.group !11
18074 // CHECK16-NEXT:    [[ADD34:%.*]] = add nsw i32 [[TMP23]], 1
18075 // CHECK16-NEXT:    store i32 [[ADD34]], i32* [[DOTOMP_IV23]], align 4, !llvm.access.group !11
18076 // CHECK16-NEXT:    br label [[OMP_INNER_FOR_COND25]], !llvm.loop [[LOOP12:![0-9]+]]
18077 // CHECK16:       omp.inner.for.end35:
18078 // CHECK16-NEXT:    store i32 10, i32* [[I24]], align 4
18079 // CHECK16-NEXT:    store i32 0, i32* [[DOTOMP_LB37]], align 4
18080 // CHECK16-NEXT:    store i32 9, i32* [[DOTOMP_UB38]], align 4
18081 // CHECK16-NEXT:    [[TMP24:%.*]] = load i32, i32* [[DOTOMP_LB37]], align 4
18082 // CHECK16-NEXT:    store i32 [[TMP24]], i32* [[DOTOMP_IV39]], align 4
18083 // CHECK16-NEXT:    br label [[OMP_INNER_FOR_COND41:%.*]]
18084 // CHECK16:       omp.inner.for.cond41:
18085 // CHECK16-NEXT:    [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IV39]], align 4, !llvm.access.group !14
18086 // CHECK16-NEXT:    [[TMP26:%.*]] = load i32, i32* [[DOTOMP_UB38]], align 4, !llvm.access.group !14
18087 // CHECK16-NEXT:    [[CMP42:%.*]] = icmp sle i32 [[TMP25]], [[TMP26]]
18088 // CHECK16-NEXT:    br i1 [[CMP42]], label [[OMP_INNER_FOR_BODY43:%.*]], label [[OMP_INNER_FOR_END53:%.*]]
18089 // CHECK16:       omp.inner.for.body43:
18090 // CHECK16-NEXT:    [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV39]], align 4, !llvm.access.group !14
18091 // CHECK16-NEXT:    [[MUL44:%.*]] = mul nsw i32 [[TMP27]], 1
18092 // CHECK16-NEXT:    [[ADD45:%.*]] = add nsw i32 0, [[MUL44]]
18093 // CHECK16-NEXT:    store i32 [[ADD45]], i32* [[I40]], align 4, !llvm.access.group !14
18094 // CHECK16-NEXT:    [[TMP28:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !14
18095 // CHECK16-NEXT:    [[ADD46:%.*]] = add nsw i32 [[TMP28]], 1
18096 // CHECK16-NEXT:    store i32 [[ADD46]], i32* [[A]], align 4, !llvm.access.group !14
18097 // CHECK16-NEXT:    [[TMP29:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !14
18098 // CHECK16-NEXT:    [[CONV47:%.*]] = sext i16 [[TMP29]] to i32
18099 // CHECK16-NEXT:    [[ADD48:%.*]] = add nsw i32 [[CONV47]], 1
18100 // CHECK16-NEXT:    [[CONV49:%.*]] = trunc i32 [[ADD48]] to i16
18101 // CHECK16-NEXT:    store i16 [[CONV49]], i16* [[AA]], align 2, !llvm.access.group !14
18102 // CHECK16-NEXT:    br label [[OMP_BODY_CONTINUE50:%.*]]
18103 // CHECK16:       omp.body.continue50:
18104 // CHECK16-NEXT:    br label [[OMP_INNER_FOR_INC51:%.*]]
18105 // CHECK16:       omp.inner.for.inc51:
18106 // CHECK16-NEXT:    [[TMP30:%.*]] = load i32, i32* [[DOTOMP_IV39]], align 4, !llvm.access.group !14
18107 // CHECK16-NEXT:    [[ADD52:%.*]] = add nsw i32 [[TMP30]], 1
18108 // CHECK16-NEXT:    store i32 [[ADD52]], i32* [[DOTOMP_IV39]], align 4, !llvm.access.group !14
18109 // CHECK16-NEXT:    br label [[OMP_INNER_FOR_COND41]], !llvm.loop [[LOOP15:![0-9]+]]
18110 // CHECK16:       omp.inner.for.end53:
18111 // CHECK16-NEXT:    store i32 10, i32* [[I40]], align 4
18112 // CHECK16-NEXT:    store i32 0, i32* [[DOTOMP_LB55]], align 4
18113 // CHECK16-NEXT:    store i32 9, i32* [[DOTOMP_UB56]], align 4
18114 // CHECK16-NEXT:    [[TMP31:%.*]] = load i32, i32* [[DOTOMP_LB55]], align 4
18115 // CHECK16-NEXT:    store i32 [[TMP31]], i32* [[DOTOMP_IV57]], align 4
18116 // CHECK16-NEXT:    [[ARRAYDECAY:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 0
18117 // CHECK16-NEXT:    call void @llvm.assume(i1 true) [ "align"(float* [[ARRAYDECAY]], i32 16) ]
18118 // CHECK16-NEXT:    br label [[OMP_INNER_FOR_COND59:%.*]]
18119 // CHECK16:       omp.inner.for.cond59:
18120 // CHECK16-NEXT:    [[TMP32:%.*]] = load i32, i32* [[DOTOMP_IV57]], align 4, !llvm.access.group !17
18121 // CHECK16-NEXT:    [[TMP33:%.*]] = load i32, i32* [[DOTOMP_UB56]], align 4, !llvm.access.group !17
18122 // CHECK16-NEXT:    [[CMP60:%.*]] = icmp sle i32 [[TMP32]], [[TMP33]]
18123 // CHECK16-NEXT:    br i1 [[CMP60]], label [[OMP_INNER_FOR_BODY61:%.*]], label [[OMP_INNER_FOR_END85:%.*]]
18124 // CHECK16:       omp.inner.for.body61:
18125 // CHECK16-NEXT:    [[TMP34:%.*]] = load i32, i32* [[DOTOMP_IV57]], align 4, !llvm.access.group !17
18126 // CHECK16-NEXT:    [[MUL62:%.*]] = mul nsw i32 [[TMP34]], 1
18127 // CHECK16-NEXT:    [[ADD63:%.*]] = add nsw i32 0, [[MUL62]]
18128 // CHECK16-NEXT:    store i32 [[ADD63]], i32* [[I58]], align 4, !llvm.access.group !17
18129 // CHECK16-NEXT:    [[TMP35:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !17
18130 // CHECK16-NEXT:    [[ADD64:%.*]] = add nsw i32 [[TMP35]], 1
18131 // CHECK16-NEXT:    store i32 [[ADD64]], i32* [[A]], align 4, !llvm.access.group !17
18132 // CHECK16-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2
18133 // CHECK16-NEXT:    [[TMP36:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !17
18134 // CHECK16-NEXT:    [[CONV65:%.*]] = fpext float [[TMP36]] to double
18135 // CHECK16-NEXT:    [[ADD66:%.*]] = fadd double [[CONV65]], 1.000000e+00
18136 // CHECK16-NEXT:    [[CONV67:%.*]] = fptrunc double [[ADD66]] to float
18137 // CHECK16-NEXT:    store float [[CONV67]], float* [[ARRAYIDX]], align 4, !llvm.access.group !17
18138 // CHECK16-NEXT:    [[ARRAYIDX68:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3
18139 // CHECK16-NEXT:    [[TMP37:%.*]] = load float, float* [[ARRAYIDX68]], align 4, !llvm.access.group !17
18140 // CHECK16-NEXT:    [[CONV69:%.*]] = fpext float [[TMP37]] to double
18141 // CHECK16-NEXT:    [[ADD70:%.*]] = fadd double [[CONV69]], 1.000000e+00
18142 // CHECK16-NEXT:    [[CONV71:%.*]] = fptrunc double [[ADD70]] to float
18143 // CHECK16-NEXT:    store float [[CONV71]], float* [[ARRAYIDX68]], align 4, !llvm.access.group !17
18144 // CHECK16-NEXT:    [[ARRAYIDX72:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1
18145 // CHECK16-NEXT:    [[ARRAYIDX73:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX72]], i32 0, i32 2
18146 // CHECK16-NEXT:    [[TMP38:%.*]] = load double, double* [[ARRAYIDX73]], align 8, !llvm.access.group !17
18147 // CHECK16-NEXT:    [[ADD74:%.*]] = fadd double [[TMP38]], 1.000000e+00
18148 // CHECK16-NEXT:    store double [[ADD74]], double* [[ARRAYIDX73]], align 8, !llvm.access.group !17
18149 // CHECK16-NEXT:    [[TMP39:%.*]] = mul nsw i32 1, [[TMP2]]
18150 // CHECK16-NEXT:    [[ARRAYIDX75:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP39]]
18151 // CHECK16-NEXT:    [[ARRAYIDX76:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX75]], i32 3
18152 // CHECK16-NEXT:    [[TMP40:%.*]] = load double, double* [[ARRAYIDX76]], align 8, !llvm.access.group !17
18153 // CHECK16-NEXT:    [[ADD77:%.*]] = fadd double [[TMP40]], 1.000000e+00
18154 // CHECK16-NEXT:    store double [[ADD77]], double* [[ARRAYIDX76]], align 8, !llvm.access.group !17
18155 // CHECK16-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0
18156 // CHECK16-NEXT:    [[TMP41:%.*]] = load i64, i64* [[X]], align 4, !llvm.access.group !17
18157 // CHECK16-NEXT:    [[ADD78:%.*]] = add nsw i64 [[TMP41]], 1
18158 // CHECK16-NEXT:    store i64 [[ADD78]], i64* [[X]], align 4, !llvm.access.group !17
18159 // CHECK16-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1
18160 // CHECK16-NEXT:    [[TMP42:%.*]] = load i8, i8* [[Y]], align 4, !llvm.access.group !17
18161 // CHECK16-NEXT:    [[CONV79:%.*]] = sext i8 [[TMP42]] to i32
18162 // CHECK16-NEXT:    [[ADD80:%.*]] = add nsw i32 [[CONV79]], 1
18163 // CHECK16-NEXT:    [[CONV81:%.*]] = trunc i32 [[ADD80]] to i8
18164 // CHECK16-NEXT:    store i8 [[CONV81]], i8* [[Y]], align 4, !llvm.access.group !17
18165 // CHECK16-NEXT:    br label [[OMP_BODY_CONTINUE82:%.*]]
18166 // CHECK16:       omp.body.continue82:
18167 // CHECK16-NEXT:    br label [[OMP_INNER_FOR_INC83:%.*]]
18168 // CHECK16:       omp.inner.for.inc83:
18169 // CHECK16-NEXT:    [[TMP43:%.*]] = load i32, i32* [[DOTOMP_IV57]], align 4, !llvm.access.group !17
18170 // CHECK16-NEXT:    [[ADD84:%.*]] = add nsw i32 [[TMP43]], 1
18171 // CHECK16-NEXT:    store i32 [[ADD84]], i32* [[DOTOMP_IV57]], align 4, !llvm.access.group !17
18172 // CHECK16-NEXT:    br label [[OMP_INNER_FOR_COND59]], !llvm.loop [[LOOP18:![0-9]+]]
18173 // CHECK16:       omp.inner.for.end85:
18174 // CHECK16-NEXT:    store i32 10, i32* [[I58]], align 4
18175 // CHECK16-NEXT:    [[TMP44:%.*]] = load i32, i32* [[A]], align 4
18176 // CHECK16-NEXT:    [[TMP45:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
18177 // CHECK16-NEXT:    call void @llvm.stackrestore(i8* [[TMP45]])
18178 // CHECK16-NEXT:    ret i32 [[TMP44]]
18179 //
18180 //
18181 // CHECK16-LABEL: define {{[^@]+}}@_Z3bari
18182 // CHECK16-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {
18183 // CHECK16-NEXT:  entry:
18184 // CHECK16-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
18185 // CHECK16-NEXT:    [[A:%.*]] = alloca i32, align 4
18186 // CHECK16-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4
18187 // CHECK16-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
18188 // CHECK16-NEXT:    store i32 0, i32* [[A]], align 4
18189 // CHECK16-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
18190 // CHECK16-NEXT:    [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]])
18191 // CHECK16-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
18192 // CHECK16-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
18193 // CHECK16-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
18194 // CHECK16-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
18195 // CHECK16-NEXT:    [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP2]])
18196 // CHECK16-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
18197 // CHECK16-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
18198 // CHECK16-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
18199 // CHECK16-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
18200 // CHECK16-NEXT:    [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]])
18201 // CHECK16-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
18202 // CHECK16-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
18203 // CHECK16-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
18204 // CHECK16-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
18205 // CHECK16-NEXT:    [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]])
18206 // CHECK16-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
18207 // CHECK16-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
18208 // CHECK16-NEXT:    store i32 [[ADD6]], i32* [[A]], align 4
18209 // CHECK16-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
18210 // CHECK16-NEXT:    ret i32 [[TMP8]]
18211 //
18212 //
18213 // CHECK16-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
18214 // CHECK16-SAME: (%struct.S1* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 {
18215 // CHECK16-NEXT:  entry:
18216 // CHECK16-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
18217 // CHECK16-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
18218 // CHECK16-NEXT:    [[B:%.*]] = alloca i32, align 4
18219 // CHECK16-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 4
18220 // CHECK16-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 4
18221 // CHECK16-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
18222 // CHECK16-NEXT:    [[TMP:%.*]] = alloca i32, align 4
18223 // CHECK16-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
18224 // CHECK16-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
18225 // CHECK16-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
18226 // CHECK16-NEXT:    [[I:%.*]] = alloca i32, align 4
18227 // CHECK16-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
18228 // CHECK16-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
18229 // CHECK16-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
18230 // CHECK16-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
18231 // CHECK16-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
18232 // CHECK16-NEXT:    store i32 [[ADD]], i32* [[B]], align 4
18233 // CHECK16-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
18234 // CHECK16-NEXT:    [[TMP2:%.*]] = call i8* @llvm.stacksave()
18235 // CHECK16-NEXT:    store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4
18236 // CHECK16-NEXT:    [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]
18237 // CHECK16-NEXT:    [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2
18238 // CHECK16-NEXT:    store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
18239 // CHECK16-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
18240 // CHECK16-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 60
18241 // CHECK16-NEXT:    [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8
18242 // CHECK16-NEXT:    store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
18243 // CHECK16-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
18244 // CHECK16-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
18245 // CHECK16-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
18246 // CHECK16-NEXT:    store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
18247 // CHECK16-NEXT:    [[TMP6:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
18248 // CHECK16-NEXT:    [[TOBOOL:%.*]] = trunc i8 [[TMP6]] to i1
18249 // CHECK16-NEXT:    br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
18250 // CHECK16:       omp_if.then:
18251 // CHECK16-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
18252 // CHECK16:       omp.inner.for.cond:
18253 // CHECK16-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20
18254 // CHECK16-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !20
18255 // CHECK16-NEXT:    [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
18256 // CHECK16-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
18257 // CHECK16:       omp.inner.for.body:
18258 // CHECK16-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20
18259 // CHECK16-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
18260 // CHECK16-NEXT:    [[ADD3:%.*]] = add nsw i32 0, [[MUL]]
18261 // CHECK16-NEXT:    store i32 [[ADD3]], i32* [[I]], align 4, !llvm.access.group !20
18262 // CHECK16-NEXT:    [[TMP10:%.*]] = load i32, i32* [[B]], align 4, !llvm.access.group !20
18263 // CHECK16-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP10]] to double
18264 // CHECK16-NEXT:    [[ADD4:%.*]] = fadd double [[CONV]], 1.500000e+00
18265 // CHECK16-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
18266 // CHECK16-NEXT:    store double [[ADD4]], double* [[A]], align 4, !llvm.access.group !20
18267 // CHECK16-NEXT:    [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
18268 // CHECK16-NEXT:    [[TMP11:%.*]] = load double, double* [[A5]], align 4, !llvm.access.group !20
18269 // CHECK16-NEXT:    [[INC:%.*]] = fadd double [[TMP11]], 1.000000e+00
18270 // CHECK16-NEXT:    store double [[INC]], double* [[A5]], align 4, !llvm.access.group !20
18271 // CHECK16-NEXT:    [[CONV6:%.*]] = fptosi double [[INC]] to i16
18272 // CHECK16-NEXT:    [[TMP12:%.*]] = mul nsw i32 1, [[TMP1]]
18273 // CHECK16-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP12]]
18274 // CHECK16-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
18275 // CHECK16-NEXT:    store i16 [[CONV6]], i16* [[ARRAYIDX7]], align 2, !llvm.access.group !20
18276 // CHECK16-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
18277 // CHECK16:       omp.body.continue:
18278 // CHECK16-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
18279 // CHECK16:       omp.inner.for.inc:
18280 // CHECK16-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20
18281 // CHECK16-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP13]], 1
18282 // CHECK16-NEXT:    store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20
18283 // CHECK16-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]]
18284 // CHECK16:       omp.inner.for.end:
18285 // CHECK16-NEXT:    br label [[OMP_IF_END:%.*]]
18286 // CHECK16:       omp_if.else:
18287 // CHECK16-NEXT:    br label [[OMP_INNER_FOR_COND9:%.*]]
18288 // CHECK16:       omp.inner.for.cond9:
18289 // CHECK16-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
18290 // CHECK16-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
18291 // CHECK16-NEXT:    [[CMP10:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
18292 // CHECK16-NEXT:    br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY11:%.*]], label [[OMP_INNER_FOR_END25:%.*]]
18293 // CHECK16:       omp.inner.for.body11:
18294 // CHECK16-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
18295 // CHECK16-NEXT:    [[MUL12:%.*]] = mul nsw i32 [[TMP16]], 1
18296 // CHECK16-NEXT:    [[ADD13:%.*]] = add nsw i32 0, [[MUL12]]
18297 // CHECK16-NEXT:    store i32 [[ADD13]], i32* [[I]], align 4
18298 // CHECK16-NEXT:    [[TMP17:%.*]] = load i32, i32* [[B]], align 4
18299 // CHECK16-NEXT:    [[CONV14:%.*]] = sitofp i32 [[TMP17]] to double
18300 // CHECK16-NEXT:    [[ADD15:%.*]] = fadd double [[CONV14]], 1.500000e+00
18301 // CHECK16-NEXT:    [[A16:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
18302 // CHECK16-NEXT:    store double [[ADD15]], double* [[A16]], align 4
18303 // CHECK16-NEXT:    [[A17:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
18304 // CHECK16-NEXT:    [[TMP18:%.*]] = load double, double* [[A17]], align 4
18305 // CHECK16-NEXT:    [[INC18:%.*]] = fadd double [[TMP18]], 1.000000e+00
18306 // CHECK16-NEXT:    store double [[INC18]], double* [[A17]], align 4
18307 // CHECK16-NEXT:    [[CONV19:%.*]] = fptosi double [[INC18]] to i16
18308 // CHECK16-NEXT:    [[TMP19:%.*]] = mul nsw i32 1, [[TMP1]]
18309 // CHECK16-NEXT:    [[ARRAYIDX20:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP19]]
18310 // CHECK16-NEXT:    [[ARRAYIDX21:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX20]], i32 1
18311 // CHECK16-NEXT:    store i16 [[CONV19]], i16* [[ARRAYIDX21]], align 2
18312 // CHECK16-NEXT:    br label [[OMP_BODY_CONTINUE22:%.*]]
18313 // CHECK16:       omp.body.continue22:
18314 // CHECK16-NEXT:    br label [[OMP_INNER_FOR_INC23:%.*]]
18315 // CHECK16:       omp.inner.for.inc23:
18316 // CHECK16-NEXT:    [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
18317 // CHECK16-NEXT:    [[ADD24:%.*]] = add nsw i32 [[TMP20]], 1
18318 // CHECK16-NEXT:    store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4
18319 // CHECK16-NEXT:    br label [[OMP_INNER_FOR_COND9]], !llvm.loop [[LOOP23:![0-9]+]]
18320 // CHECK16:       omp.inner.for.end25:
18321 // CHECK16-NEXT:    br label [[OMP_IF_END]]
18322 // CHECK16:       omp_if.end:
18323 // CHECK16-NEXT:    store i32 10, i32* [[I]], align 4
18324 // CHECK16-NEXT:    [[TMP21:%.*]] = mul nsw i32 1, [[TMP1]]
18325 // CHECK16-NEXT:    [[ARRAYIDX26:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP21]]
18326 // CHECK16-NEXT:    [[ARRAYIDX27:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX26]], i32 1
18327 // CHECK16-NEXT:    [[TMP22:%.*]] = load i16, i16* [[ARRAYIDX27]], align 2
18328 // CHECK16-NEXT:    [[CONV28:%.*]] = sext i16 [[TMP22]] to i32
18329 // CHECK16-NEXT:    [[TMP23:%.*]] = load i32, i32* [[B]], align 4
18330 // CHECK16-NEXT:    [[ADD29:%.*]] = add nsw i32 [[CONV28]], [[TMP23]]
18331 // CHECK16-NEXT:    [[TMP24:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
18332 // CHECK16-NEXT:    call void @llvm.stackrestore(i8* [[TMP24]])
18333 // CHECK16-NEXT:    ret i32 [[ADD29]]
18334 //
18335 //
18336 // CHECK16-LABEL: define {{[^@]+}}@_ZL7fstatici
18337 // CHECK16-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {
18338 // CHECK16-NEXT:  entry:
18339 // CHECK16-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
18340 // CHECK16-NEXT:    [[A:%.*]] = alloca i32, align 4
18341 // CHECK16-NEXT:    [[AA:%.*]] = alloca i16, align 2
18342 // CHECK16-NEXT:    [[AAA:%.*]] = alloca i8, align 1
18343 // CHECK16-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
18344 // CHECK16-NEXT:    [[TMP:%.*]] = alloca i32, align 4
18345 // CHECK16-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
18346 // CHECK16-NEXT:    [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
18347 // CHECK16-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
18348 // CHECK16-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
18349 // CHECK16-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
18350 // CHECK16-NEXT:    [[I:%.*]] = alloca i32, align 4
18351 // CHECK16-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
18352 // CHECK16-NEXT:    [[I5:%.*]] = alloca i32, align 4
18353 // CHECK16-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
18354 // CHECK16-NEXT:    store i32 0, i32* [[A]], align 4
18355 // CHECK16-NEXT:    store i16 0, i16* [[AA]], align 2
18356 // CHECK16-NEXT:    store i8 0, i8* [[AAA]], align 1
18357 // CHECK16-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
18358 // CHECK16-NEXT:    store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4
18359 // CHECK16-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
18360 // CHECK16-NEXT:    store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_1]], align 4
18361 // CHECK16-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
18362 // CHECK16-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
18363 // CHECK16-NEXT:    [[SUB:%.*]] = sub i32 [[TMP2]], [[TMP3]]
18364 // CHECK16-NEXT:    [[SUB3:%.*]] = sub i32 [[SUB]], 1
18365 // CHECK16-NEXT:    [[ADD:%.*]] = add i32 [[SUB3]], 1
18366 // CHECK16-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], 1
18367 // CHECK16-NEXT:    [[SUB4:%.*]] = sub i32 [[DIV]], 1
18368 // CHECK16-NEXT:    store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_2]], align 4
18369 // CHECK16-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
18370 // CHECK16-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
18371 // CHECK16-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_UB]], align 4
18372 // CHECK16-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
18373 // CHECK16-NEXT:    store i32 [[TMP5]], i32* [[I]], align 4
18374 // CHECK16-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
18375 // CHECK16-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
18376 // CHECK16-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]]
18377 // CHECK16-NEXT:    br i1 [[CMP]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END:%.*]]
18378 // CHECK16:       simd.if.then:
18379 // CHECK16-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
18380 // CHECK16-NEXT:    store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
18381 // CHECK16-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
18382 // CHECK16:       omp.inner.for.cond:
18383 // CHECK16-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25
18384 // CHECK16-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !25
18385 // CHECK16-NEXT:    [[ADD6:%.*]] = add i32 [[TMP10]], 1
18386 // CHECK16-NEXT:    [[CMP7:%.*]] = icmp ult i32 [[TMP9]], [[ADD6]]
18387 // CHECK16-NEXT:    br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
18388 // CHECK16:       omp.inner.for.body:
18389 // CHECK16-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group !25
18390 // CHECK16-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25
18391 // CHECK16-NEXT:    [[MUL:%.*]] = mul i32 [[TMP12]], 1
18392 // CHECK16-NEXT:    [[ADD8:%.*]] = add i32 [[TMP11]], [[MUL]]
18393 // CHECK16-NEXT:    store i32 [[ADD8]], i32* [[I5]], align 4, !llvm.access.group !25
18394 // CHECK16-NEXT:    [[TMP13:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !25
18395 // CHECK16-NEXT:    [[ADD9:%.*]] = add nsw i32 [[TMP13]], 1
18396 // CHECK16-NEXT:    store i32 [[ADD9]], i32* [[A]], align 4, !llvm.access.group !25
18397 // CHECK16-NEXT:    [[TMP14:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !25
18398 // CHECK16-NEXT:    [[CONV:%.*]] = sext i16 [[TMP14]] to i32
18399 // CHECK16-NEXT:    [[ADD10:%.*]] = add nsw i32 [[CONV]], 1
18400 // CHECK16-NEXT:    [[CONV11:%.*]] = trunc i32 [[ADD10]] to i16
18401 // CHECK16-NEXT:    store i16 [[CONV11]], i16* [[AA]], align 2, !llvm.access.group !25
18402 // CHECK16-NEXT:    [[TMP15:%.*]] = load i8, i8* [[AAA]], align 1, !llvm.access.group !25
18403 // CHECK16-NEXT:    [[CONV12:%.*]] = sext i8 [[TMP15]] to i32
18404 // CHECK16-NEXT:    [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1
18405 // CHECK16-NEXT:    [[CONV14:%.*]] = trunc i32 [[ADD13]] to i8
18406 // CHECK16-NEXT:    store i8 [[CONV14]], i8* [[AAA]], align 1, !llvm.access.group !25
18407 // CHECK16-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2
18408 // CHECK16-NEXT:    [[TMP16:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !25
18409 // CHECK16-NEXT:    [[ADD15:%.*]] = add nsw i32 [[TMP16]], 1
18410 // CHECK16-NEXT:    store i32 [[ADD15]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !25
18411 // CHECK16-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
18412 // CHECK16:       omp.body.continue:
18413 // CHECK16-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
18414 // CHECK16:       omp.inner.for.inc:
18415 // CHECK16-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25
18416 // CHECK16-NEXT:    [[ADD16:%.*]] = add i32 [[TMP17]], 1
18417 // CHECK16-NEXT:    store i32 [[ADD16]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25
18418 // CHECK16-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP26:![0-9]+]]
18419 // CHECK16:       omp.inner.for.end:
18420 // CHECK16-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
18421 // CHECK16-NEXT:    [[TMP19:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
18422 // CHECK16-NEXT:    [[TMP20:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
18423 // CHECK16-NEXT:    [[SUB17:%.*]] = sub i32 [[TMP19]], [[TMP20]]
18424 // CHECK16-NEXT:    [[SUB18:%.*]] = sub i32 [[SUB17]], 1
18425 // CHECK16-NEXT:    [[ADD19:%.*]] = add i32 [[SUB18]], 1
18426 // CHECK16-NEXT:    [[DIV20:%.*]] = udiv i32 [[ADD19]], 1
18427 // CHECK16-NEXT:    [[MUL21:%.*]] = mul i32 [[DIV20]], 1
18428 // CHECK16-NEXT:    [[ADD22:%.*]] = add i32 [[TMP18]], [[MUL21]]
18429 // CHECK16-NEXT:    store i32 [[ADD22]], i32* [[I5]], align 4
18430 // CHECK16-NEXT:    br label [[SIMD_IF_END]]
18431 // CHECK16:       simd.if.end:
18432 // CHECK16-NEXT:    [[TMP21:%.*]] = load i32, i32* [[A]], align 4
18433 // CHECK16-NEXT:    ret i32 [[TMP21]]
18434 //
18435 //
18436 // CHECK16-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
18437 // CHECK16-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat {
18438 // CHECK16-NEXT:  entry:
18439 // CHECK16-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
18440 // CHECK16-NEXT:    [[A:%.*]] = alloca i32, align 4
18441 // CHECK16-NEXT:    [[AA:%.*]] = alloca i16, align 2
18442 // CHECK16-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
18443 // CHECK16-NEXT:    [[TMP:%.*]] = alloca i32, align 4
18444 // CHECK16-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
18445 // CHECK16-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
18446 // CHECK16-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
18447 // CHECK16-NEXT:    [[I:%.*]] = alloca i32, align 4
18448 // CHECK16-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
18449 // CHECK16-NEXT:    store i32 0, i32* [[A]], align 4
18450 // CHECK16-NEXT:    store i16 0, i16* [[AA]], align 2
18451 // CHECK16-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
18452 // CHECK16-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
18453 // CHECK16-NEXT:    [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
18454 // CHECK16-NEXT:    store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4
18455 // CHECK16-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
18456 // CHECK16:       omp.inner.for.cond:
18457 // CHECK16-NEXT:    [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28
18458 // CHECK16-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !28
18459 // CHECK16-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
18460 // CHECK16-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
18461 // CHECK16:       omp.inner.for.body:
18462 // CHECK16-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28
18463 // CHECK16-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1
18464 // CHECK16-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
18465 // CHECK16-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !28
18466 // CHECK16-NEXT:    [[TMP4:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !28
18467 // CHECK16-NEXT:    [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1
18468 // CHECK16-NEXT:    store i32 [[ADD1]], i32* [[A]], align 4, !llvm.access.group !28
18469 // CHECK16-NEXT:    [[TMP5:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !28
18470 // CHECK16-NEXT:    [[CONV:%.*]] = sext i16 [[TMP5]] to i32
18471 // CHECK16-NEXT:    [[ADD2:%.*]] = add nsw i32 [[CONV]], 1
18472 // CHECK16-NEXT:    [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
18473 // CHECK16-NEXT:    store i16 [[CONV3]], i16* [[AA]], align 2, !llvm.access.group !28
18474 // CHECK16-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2
18475 // CHECK16-NEXT:    [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !28
18476 // CHECK16-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP6]], 1
18477 // CHECK16-NEXT:    store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !28
18478 // CHECK16-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
18479 // CHECK16:       omp.body.continue:
18480 // CHECK16-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
18481 // CHECK16:       omp.inner.for.inc:
18482 // CHECK16-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28
18483 // CHECK16-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP7]], 1
18484 // CHECK16-NEXT:    store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28
18485 // CHECK16-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP29:![0-9]+]]
18486 // CHECK16:       omp.inner.for.end:
18487 // CHECK16-NEXT:    store i32 10, i32* [[I]], align 4
18488 // CHECK16-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
18489 // CHECK16-NEXT:    ret i32 [[TMP8]]
18490 //
18491 //
18492 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97
18493 // CHECK17-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] {
18494 // CHECK17-NEXT:  entry:
18495 // CHECK17-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
18496 // CHECK17-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
18497 // CHECK17-NEXT:    [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8
18498 // CHECK17-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
18499 // CHECK17-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]])
18500 // CHECK17-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
18501 // CHECK17-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
18502 // CHECK17-NEXT:    store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8
18503 // CHECK17-NEXT:    [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
18504 // CHECK17-NEXT:    [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
18505 // CHECK17-NEXT:    [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32*
18506 // CHECK17-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 4
18507 // CHECK17-NEXT:    [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 4
18508 // CHECK17-NEXT:    call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
18509 // CHECK17-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
18510 // CHECK17-NEXT:    [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
18511 // CHECK17-NEXT:    store i16 [[TMP3]], i16* [[CONV5]], align 2
18512 // CHECK17-NEXT:    [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
18513 // CHECK17-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]])
18514 // CHECK17-NEXT:    ret void
18515 //
18516 //
18517 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined.
18518 // CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR1:[0-9]+]] {
18519 // CHECK17-NEXT:  entry:
18520 // CHECK17-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
18521 // CHECK17-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
18522 // CHECK17-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
18523 // CHECK17-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
18524 // CHECK17-NEXT:    [[TMP:%.*]] = alloca i32, align 4
18525 // CHECK17-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
18526 // CHECK17-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
18527 // CHECK17-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
18528 // CHECK17-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
18529 // CHECK17-NEXT:    [[I:%.*]] = alloca i32, align 4
18530 // CHECK17-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
18531 // CHECK17-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
18532 // CHECK17-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
18533 // CHECK17-NEXT:    [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
18534 // CHECK17-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
18535 // CHECK17-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
18536 // CHECK17-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
18537 // CHECK17-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
18538 // CHECK17-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
18539 // CHECK17-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
18540 // CHECK17-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
18541 // CHECK17-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
18542 // CHECK17-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
18543 // CHECK17-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
18544 // CHECK17:       cond.true:
18545 // CHECK17-NEXT:    br label [[COND_END:%.*]]
18546 // CHECK17:       cond.false:
18547 // CHECK17-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
18548 // CHECK17-NEXT:    br label [[COND_END]]
18549 // CHECK17:       cond.end:
18550 // CHECK17-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
18551 // CHECK17-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
18552 // CHECK17-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
18553 // CHECK17-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
18554 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
18555 // CHECK17:       omp.inner.for.cond:
18556 // CHECK17-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
18557 // CHECK17-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !11
18558 // CHECK17-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
18559 // CHECK17-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
18560 // CHECK17:       omp.inner.for.body:
18561 // CHECK17-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
18562 // CHECK17-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
18563 // CHECK17-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
18564 // CHECK17-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11
18565 // CHECK17-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
18566 // CHECK17:       omp.body.continue:
18567 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
18568 // CHECK17:       omp.inner.for.inc:
18569 // CHECK17-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
18570 // CHECK17-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
18571 // CHECK17-NEXT:    store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
18572 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]
18573 // CHECK17:       omp.inner.for.end:
18574 // CHECK17-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
18575 // CHECK17:       omp.loop.exit:
18576 // CHECK17-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
18577 // CHECK17-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
18578 // CHECK17-NEXT:    [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0
18579 // CHECK17-NEXT:    br i1 [[TMP10]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
18580 // CHECK17:       .omp.final.then:
18581 // CHECK17-NEXT:    store i32 10, i32* [[I]], align 4
18582 // CHECK17-NEXT:    br label [[DOTOMP_FINAL_DONE]]
18583 // CHECK17:       .omp.final.done:
18584 // CHECK17-NEXT:    ret void
18585 //
18586 //
18587 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111
18588 // CHECK17-SAME: (i64 noundef [[AA:%.*]]) #[[ATTR0]] {
18589 // CHECK17-NEXT:  entry:
18590 // CHECK17-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
18591 // CHECK17-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
18592 // CHECK17-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
18593 // CHECK17-NEXT:    [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
18594 // CHECK17-NEXT:    [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
18595 // CHECK17-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
18596 // CHECK17-NEXT:    store i16 [[TMP0]], i16* [[CONV1]], align 2
18597 // CHECK17-NEXT:    [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
18598 // CHECK17-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]])
18599 // CHECK17-NEXT:    ret void
18600 //
18601 //
18602 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..1
18603 // CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR1]] {
18604 // CHECK17-NEXT:  entry:
18605 // CHECK17-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
18606 // CHECK17-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
18607 // CHECK17-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
18608 // CHECK17-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
18609 // CHECK17-NEXT:    [[TMP:%.*]] = alloca i32, align 4
18610 // CHECK17-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
18611 // CHECK17-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
18612 // CHECK17-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
18613 // CHECK17-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
18614 // CHECK17-NEXT:    [[I:%.*]] = alloca i32, align 4
18615 // CHECK17-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
18616 // CHECK17-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
18617 // CHECK17-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
18618 // CHECK17-NEXT:    [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
18619 // CHECK17-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
18620 // CHECK17-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
18621 // CHECK17-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
18622 // CHECK17-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
18623 // CHECK17-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
18624 // CHECK17-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
18625 // CHECK17-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
18626 // CHECK17-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
18627 // CHECK17-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
18628 // CHECK17-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
18629 // CHECK17:       cond.true:
18630 // CHECK17-NEXT:    br label [[COND_END:%.*]]
18631 // CHECK17:       cond.false:
18632 // CHECK17-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
18633 // CHECK17-NEXT:    br label [[COND_END]]
18634 // CHECK17:       cond.end:
18635 // CHECK17-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
18636 // CHECK17-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
18637 // CHECK17-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
18638 // CHECK17-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
18639 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
18640 // CHECK17:       omp.inner.for.cond:
18641 // CHECK17-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
18642 // CHECK17-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !18
18643 // CHECK17-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
18644 // CHECK17-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
18645 // CHECK17:       omp.inner.for.body:
18646 // CHECK17-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
18647 // CHECK17-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
18648 // CHECK17-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
18649 // CHECK17-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18
18650 // CHECK17-NEXT:    [[TMP8:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !18
18651 // CHECK17-NEXT:    [[CONV2:%.*]] = sext i16 [[TMP8]] to i32
18652 // CHECK17-NEXT:    [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
18653 // CHECK17-NEXT:    [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
18654 // CHECK17-NEXT:    store i16 [[CONV4]], i16* [[CONV]], align 2, !llvm.access.group !18
18655 // CHECK17-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
18656 // CHECK17:       omp.body.continue:
18657 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
18658 // CHECK17:       omp.inner.for.inc:
18659 // CHECK17-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
18660 // CHECK17-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP9]], 1
18661 // CHECK17-NEXT:    store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
18662 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]
18663 // CHECK17:       omp.inner.for.end:
18664 // CHECK17-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
18665 // CHECK17:       omp.loop.exit:
18666 // CHECK17-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
18667 // CHECK17-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
18668 // CHECK17-NEXT:    [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0
18669 // CHECK17-NEXT:    br i1 [[TMP11]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
18670 // CHECK17:       .omp.final.then:
18671 // CHECK17-NEXT:    store i32 10, i32* [[I]], align 4
18672 // CHECK17-NEXT:    br label [[DOTOMP_FINAL_DONE]]
18673 // CHECK17:       .omp.final.done:
18674 // CHECK17-NEXT:    ret void
18675 //
18676 //
18677 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118
18678 // CHECK17-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] {
18679 // CHECK17-NEXT:  entry:
18680 // CHECK17-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
18681 // CHECK17-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
18682 // CHECK17-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
18683 // CHECK17-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
18684 // CHECK17-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
18685 // CHECK17-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
18686 // CHECK17-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
18687 // CHECK17-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
18688 // CHECK17-NEXT:    [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
18689 // CHECK17-NEXT:    [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
18690 // CHECK17-NEXT:    store i32 [[TMP0]], i32* [[CONV2]], align 4
18691 // CHECK17-NEXT:    [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
18692 // CHECK17-NEXT:    [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
18693 // CHECK17-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
18694 // CHECK17-NEXT:    store i16 [[TMP2]], i16* [[CONV3]], align 2
18695 // CHECK17-NEXT:    [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
18696 // CHECK17-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
18697 // CHECK17-NEXT:    ret void
18698 //
18699 //
18700 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..2
18701 // CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR1]] {
18702 // CHECK17-NEXT:  entry:
18703 // CHECK17-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
18704 // CHECK17-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
18705 // CHECK17-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
18706 // CHECK17-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
18707 // CHECK17-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
18708 // CHECK17-NEXT:    [[TMP:%.*]] = alloca i32, align 4
18709 // CHECK17-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
18710 // CHECK17-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
18711 // CHECK17-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
18712 // CHECK17-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
18713 // CHECK17-NEXT:    [[I:%.*]] = alloca i32, align 4
18714 // CHECK17-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
18715 // CHECK17-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
18716 // CHECK17-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
18717 // CHECK17-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
18718 // CHECK17-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
18719 // CHECK17-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
18720 // CHECK17-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
18721 // CHECK17-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
18722 // CHECK17-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
18723 // CHECK17-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
18724 // CHECK17-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
18725 // CHECK17-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
18726 // CHECK17-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
18727 // CHECK17-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
18728 // CHECK17-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
18729 // CHECK17-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
18730 // CHECK17:       cond.true:
18731 // CHECK17-NEXT:    br label [[COND_END:%.*]]
18732 // CHECK17:       cond.false:
18733 // CHECK17-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
18734 // CHECK17-NEXT:    br label [[COND_END]]
18735 // CHECK17:       cond.end:
18736 // CHECK17-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
18737 // CHECK17-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
18738 // CHECK17-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
18739 // CHECK17-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
18740 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
18741 // CHECK17:       omp.inner.for.cond:
18742 // CHECK17-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
18743 // CHECK17-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !21
18744 // CHECK17-NEXT:    [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
18745 // CHECK17-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
18746 // CHECK17:       omp.inner.for.body:
18747 // CHECK17-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
18748 // CHECK17-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
18749 // CHECK17-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
18750 // CHECK17-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !21
18751 // CHECK17-NEXT:    [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !21
18752 // CHECK17-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
18753 // CHECK17-NEXT:    store i32 [[ADD3]], i32* [[CONV]], align 4, !llvm.access.group !21
18754 // CHECK17-NEXT:    [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 2, !llvm.access.group !21
18755 // CHECK17-NEXT:    [[CONV4:%.*]] = sext i16 [[TMP9]] to i32
18756 // CHECK17-NEXT:    [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
18757 // CHECK17-NEXT:    [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
18758 // CHECK17-NEXT:    store i16 [[CONV6]], i16* [[CONV1]], align 2, !llvm.access.group !21
18759 // CHECK17-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
18760 // CHECK17:       omp.body.continue:
18761 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
18762 // CHECK17:       omp.inner.for.inc:
18763 // CHECK17-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
18764 // CHECK17-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1
18765 // CHECK17-NEXT:    store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
18766 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]]
18767 // CHECK17:       omp.inner.for.end:
18768 // CHECK17-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
18769 // CHECK17:       omp.loop.exit:
18770 // CHECK17-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
18771 // CHECK17-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
18772 // CHECK17-NEXT:    [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
18773 // CHECK17-NEXT:    br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
18774 // CHECK17:       .omp.final.then:
18775 // CHECK17-NEXT:    store i32 10, i32* [[I]], align 4
18776 // CHECK17-NEXT:    br label [[DOTOMP_FINAL_DONE]]
18777 // CHECK17:       .omp.final.done:
18778 // CHECK17-NEXT:    ret void
18779 //
18780 //
18781 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142
18782 // CHECK17-SAME: (i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] {
18783 // CHECK17-NEXT:  entry:
18784 // CHECK17-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
18785 // CHECK17-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
18786 // CHECK17-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
18787 // CHECK17-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 8
18788 // CHECK17-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
18789 // CHECK17-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
18790 // CHECK17-NEXT:    [[VLA_ADDR4:%.*]] = alloca i64, align 8
18791 // CHECK17-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 8
18792 // CHECK17-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
18793 // CHECK17-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
18794 // CHECK17-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
18795 // CHECK17-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
18796 // CHECK17-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
18797 // CHECK17-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 8
18798 // CHECK17-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
18799 // CHECK17-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
18800 // CHECK17-NEXT:    store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
18801 // CHECK17-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 8
18802 // CHECK17-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
18803 // CHECK17-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
18804 // CHECK17-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
18805 // CHECK17-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
18806 // CHECK17-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
18807 // CHECK17-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
18808 // CHECK17-NEXT:    [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
18809 // CHECK17-NEXT:    [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
18810 // CHECK17-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
18811 // CHECK17-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
18812 // CHECK17-NEXT:    [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
18813 // CHECK17-NEXT:    [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
18814 // CHECK17-NEXT:    store i32 [[TMP8]], i32* [[CONV5]], align 4
18815 // CHECK17-NEXT:    [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
18816 // CHECK17-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]])
18817 // CHECK17-NEXT:    ret void
18818 //
18819 //
18820 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..3
18821 // CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR1]] {
18822 // CHECK17-NEXT:  entry:
18823 // CHECK17-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
18824 // CHECK17-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
18825 // CHECK17-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
18826 // CHECK17-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
18827 // CHECK17-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
18828 // CHECK17-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 8
18829 // CHECK17-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
18830 // CHECK17-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
18831 // CHECK17-NEXT:    [[VLA_ADDR4:%.*]] = alloca i64, align 8
18832 // CHECK17-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 8
18833 // CHECK17-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
18834 // CHECK17-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
18835 // CHECK17-NEXT:    [[TMP:%.*]] = alloca i32, align 4
18836 // CHECK17-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
18837 // CHECK17-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
18838 // CHECK17-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
18839 // CHECK17-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
18840 // CHECK17-NEXT:    [[I:%.*]] = alloca i32, align 4
18841 // CHECK17-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
18842 // CHECK17-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
18843 // CHECK17-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
18844 // CHECK17-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
18845 // CHECK17-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
18846 // CHECK17-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 8
18847 // CHECK17-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
18848 // CHECK17-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
18849 // CHECK17-NEXT:    store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
18850 // CHECK17-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 8
18851 // CHECK17-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
18852 // CHECK17-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
18853 // CHECK17-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
18854 // CHECK17-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
18855 // CHECK17-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
18856 // CHECK17-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
18857 // CHECK17-NEXT:    [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
18858 // CHECK17-NEXT:    [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
18859 // CHECK17-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
18860 // CHECK17-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
18861 // CHECK17-NEXT:    [[ARRAYDECAY:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 0
18862 // CHECK17-NEXT:    call void @llvm.assume(i1 true) [ "align"(float* [[ARRAYDECAY]], i64 16) ]
18863 // CHECK17-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
18864 // CHECK17-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
18865 // CHECK17-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
18866 // CHECK17-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
18867 // CHECK17-NEXT:    [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
18868 // CHECK17-NEXT:    [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4
18869 // CHECK17-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
18870 // CHECK17-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
18871 // CHECK17-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP10]], 9
18872 // CHECK17-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
18873 // CHECK17:       cond.true:
18874 // CHECK17-NEXT:    br label [[COND_END:%.*]]
18875 // CHECK17:       cond.false:
18876 // CHECK17-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
18877 // CHECK17-NEXT:    br label [[COND_END]]
18878 // CHECK17:       cond.end:
18879 // CHECK17-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ]
18880 // CHECK17-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
18881 // CHECK17-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
18882 // CHECK17-NEXT:    store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4
18883 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
18884 // CHECK17:       omp.inner.for.cond:
18885 // CHECK17-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
18886 // CHECK17-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !24
18887 // CHECK17-NEXT:    [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
18888 // CHECK17-NEXT:    br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
18889 // CHECK17:       omp.inner.for.body:
18890 // CHECK17-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
18891 // CHECK17-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1
18892 // CHECK17-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
18893 // CHECK17-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !24
18894 // CHECK17-NEXT:    [[TMP16:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !24
18895 // CHECK17-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP16]], 1
18896 // CHECK17-NEXT:    store i32 [[ADD6]], i32* [[CONV]], align 4, !llvm.access.group !24
18897 // CHECK17-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
18898 // CHECK17-NEXT:    [[TMP17:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !24
18899 // CHECK17-NEXT:    [[CONV7:%.*]] = fpext float [[TMP17]] to double
18900 // CHECK17-NEXT:    [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00
18901 // CHECK17-NEXT:    [[CONV9:%.*]] = fptrunc double [[ADD8]] to float
18902 // CHECK17-NEXT:    store float [[CONV9]], float* [[ARRAYIDX]], align 4, !llvm.access.group !24
18903 // CHECK17-NEXT:    [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3
18904 // CHECK17-NEXT:    [[TMP18:%.*]] = load float, float* [[ARRAYIDX10]], align 4, !llvm.access.group !24
18905 // CHECK17-NEXT:    [[CONV11:%.*]] = fpext float [[TMP18]] to double
18906 // CHECK17-NEXT:    [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00
18907 // CHECK17-NEXT:    [[CONV13:%.*]] = fptrunc double [[ADD12]] to float
18908 // CHECK17-NEXT:    store float [[CONV13]], float* [[ARRAYIDX10]], align 4, !llvm.access.group !24
18909 // CHECK17-NEXT:    [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1
18910 // CHECK17-NEXT:    [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX14]], i64 0, i64 2
18911 // CHECK17-NEXT:    [[TMP19:%.*]] = load double, double* [[ARRAYIDX15]], align 8, !llvm.access.group !24
18912 // CHECK17-NEXT:    [[ADD16:%.*]] = fadd double [[TMP19]], 1.000000e+00
18913 // CHECK17-NEXT:    store double [[ADD16]], double* [[ARRAYIDX15]], align 8, !llvm.access.group !24
18914 // CHECK17-NEXT:    [[TMP20:%.*]] = mul nsw i64 1, [[TMP5]]
18915 // CHECK17-NEXT:    [[ARRAYIDX17:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP20]]
18916 // CHECK17-NEXT:    [[ARRAYIDX18:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX17]], i64 3
18917 // CHECK17-NEXT:    [[TMP21:%.*]] = load double, double* [[ARRAYIDX18]], align 8, !llvm.access.group !24
18918 // CHECK17-NEXT:    [[ADD19:%.*]] = fadd double [[TMP21]], 1.000000e+00
18919 // CHECK17-NEXT:    store double [[ADD19]], double* [[ARRAYIDX18]], align 8, !llvm.access.group !24
18920 // CHECK17-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0
18921 // CHECK17-NEXT:    [[TMP22:%.*]] = load i64, i64* [[X]], align 8, !llvm.access.group !24
18922 // CHECK17-NEXT:    [[ADD20:%.*]] = add nsw i64 [[TMP22]], 1
18923 // CHECK17-NEXT:    store i64 [[ADD20]], i64* [[X]], align 8, !llvm.access.group !24
18924 // CHECK17-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1
18925 // CHECK17-NEXT:    [[TMP23:%.*]] = load i8, i8* [[Y]], align 8, !llvm.access.group !24
18926 // CHECK17-NEXT:    [[CONV21:%.*]] = sext i8 [[TMP23]] to i32
18927 // CHECK17-NEXT:    [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1
18928 // CHECK17-NEXT:    [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8
18929 // CHECK17-NEXT:    store i8 [[CONV23]], i8* [[Y]], align 8, !llvm.access.group !24
18930 // CHECK17-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
18931 // CHECK17:       omp.body.continue:
18932 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
18933 // CHECK17:       omp.inner.for.inc:
18934 // CHECK17-NEXT:    [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
18935 // CHECK17-NEXT:    [[ADD24:%.*]] = add nsw i32 [[TMP24]], 1
18936 // CHECK17-NEXT:    store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
18937 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]]
18938 // CHECK17:       omp.inner.for.end:
18939 // CHECK17-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
18940 // CHECK17:       omp.loop.exit:
18941 // CHECK17-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]])
18942 // CHECK17-NEXT:    [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
18943 // CHECK17-NEXT:    [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
18944 // CHECK17-NEXT:    br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
18945 // CHECK17:       .omp.final.then:
18946 // CHECK17-NEXT:    store i32 10, i32* [[I]], align 4
18947 // CHECK17-NEXT:    br label [[DOTOMP_FINAL_DONE]]
18948 // CHECK17:       .omp.final.done:
18949 // CHECK17-NEXT:    ret void
18950 //
18951 //
18952 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197
18953 // CHECK17-SAME: (i64 noundef [[A:%.*]], i64 noundef [[N:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
18954 // CHECK17-NEXT:  entry:
18955 // CHECK17-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
18956 // CHECK17-NEXT:    [[N_ADDR:%.*]] = alloca i64, align 8
18957 // CHECK17-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
18958 // CHECK17-NEXT:    [[AAA_ADDR:%.*]] = alloca i64, align 8
18959 // CHECK17-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
18960 // CHECK17-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
18961 // CHECK17-NEXT:    [[N_CASTED:%.*]] = alloca i64, align 8
18962 // CHECK17-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
18963 // CHECK17-NEXT:    [[AAA_CASTED:%.*]] = alloca i64, align 8
18964 // CHECK17-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
18965 // CHECK17-NEXT:    store i64 [[N]], i64* [[N_ADDR]], align 8
18966 // CHECK17-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
18967 // CHECK17-NEXT:    store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
18968 // CHECK17-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
18969 // CHECK17-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
18970 // CHECK17-NEXT:    [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32*
18971 // CHECK17-NEXT:    [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
18972 // CHECK17-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
18973 // CHECK17-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
18974 // CHECK17-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
18975 // CHECK17-NEXT:    [[CONV4:%.*]] = bitcast i64* [[A_CASTED]] to i32*
18976 // CHECK17-NEXT:    store i32 [[TMP1]], i32* [[CONV4]], align 4
18977 // CHECK17-NEXT:    [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
18978 // CHECK17-NEXT:    [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 4
18979 // CHECK17-NEXT:    [[CONV5:%.*]] = bitcast i64* [[N_CASTED]] to i32*
18980 // CHECK17-NEXT:    store i32 [[TMP3]], i32* [[CONV5]], align 4
18981 // CHECK17-NEXT:    [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8
18982 // CHECK17-NEXT:    [[TMP5:%.*]] = load i16, i16* [[CONV2]], align 2
18983 // CHECK17-NEXT:    [[CONV6:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
18984 // CHECK17-NEXT:    store i16 [[TMP5]], i16* [[CONV6]], align 2
18985 // CHECK17-NEXT:    [[TMP6:%.*]] = load i64, i64* [[AA_CASTED]], align 8
18986 // CHECK17-NEXT:    [[TMP7:%.*]] = load i8, i8* [[CONV3]], align 1
18987 // CHECK17-NEXT:    [[CONV7:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
18988 // CHECK17-NEXT:    store i8 [[TMP7]], i8* [[CONV7]], align 1
18989 // CHECK17-NEXT:    [[TMP8:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
18990 // CHECK17-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]], [10 x i32]* [[TMP0]])
18991 // CHECK17-NEXT:    ret void
18992 //
18993 //
18994 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..4
18995 // CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[N:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {
18996 // CHECK17-NEXT:  entry:
18997 // CHECK17-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
18998 // CHECK17-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
18999 // CHECK17-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
19000 // CHECK17-NEXT:    [[N_ADDR:%.*]] = alloca i64, align 8
19001 // CHECK17-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
19002 // CHECK17-NEXT:    [[AAA_ADDR:%.*]] = alloca i64, align 8
19003 // CHECK17-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
19004 // CHECK17-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
19005 // CHECK17-NEXT:    [[TMP:%.*]] = alloca i32, align 4
19006 // CHECK17-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
19007 // CHECK17-NEXT:    [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4
19008 // CHECK17-NEXT:    [[DOTCAPTURE_EXPR_5:%.*]] = alloca i32, align 4
19009 // CHECK17-NEXT:    [[I:%.*]] = alloca i32, align 4
19010 // CHECK17-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
19011 // CHECK17-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
19012 // CHECK17-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
19013 // CHECK17-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
19014 // CHECK17-NEXT:    [[I8:%.*]] = alloca i32, align 4
19015 // CHECK17-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
19016 // CHECK17-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
19017 // CHECK17-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
19018 // CHECK17-NEXT:    store i64 [[N]], i64* [[N_ADDR]], align 8
19019 // CHECK17-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
19020 // CHECK17-NEXT:    store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
19021 // CHECK17-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
19022 // CHECK17-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
19023 // CHECK17-NEXT:    [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32*
19024 // CHECK17-NEXT:    [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
19025 // CHECK17-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
19026 // CHECK17-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
19027 // CHECK17-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
19028 // CHECK17-NEXT:    store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
19029 // CHECK17-NEXT:    [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4
19030 // CHECK17-NEXT:    store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_4]], align 4
19031 // CHECK17-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4
19032 // CHECK17-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
19033 // CHECK17-NEXT:    [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]]
19034 // CHECK17-NEXT:    [[SUB6:%.*]] = sub i32 [[SUB]], 1
19035 // CHECK17-NEXT:    [[ADD:%.*]] = add i32 [[SUB6]], 1
19036 // CHECK17-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], 1
19037 // CHECK17-NEXT:    [[SUB7:%.*]] = sub i32 [[DIV]], 1
19038 // CHECK17-NEXT:    store i32 [[SUB7]], i32* [[DOTCAPTURE_EXPR_5]], align 4
19039 // CHECK17-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
19040 // CHECK17-NEXT:    store i32 [[TMP5]], i32* [[I]], align 4
19041 // CHECK17-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
19042 // CHECK17-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4
19043 // CHECK17-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]]
19044 // CHECK17-NEXT:    br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
19045 // CHECK17:       omp.precond.then:
19046 // CHECK17-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
19047 // CHECK17-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4
19048 // CHECK17-NEXT:    store i32 [[TMP8]], i32* [[DOTOMP_UB]], align 4
19049 // CHECK17-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
19050 // CHECK17-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
19051 // CHECK17-NEXT:    [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
19052 // CHECK17-NEXT:    [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
19053 // CHECK17-NEXT:    call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
19054 // CHECK17-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
19055 // CHECK17-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4
19056 // CHECK17-NEXT:    [[CMP9:%.*]] = icmp ugt i32 [[TMP11]], [[TMP12]]
19057 // CHECK17-NEXT:    br i1 [[CMP9]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
19058 // CHECK17:       cond.true:
19059 // CHECK17-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4
19060 // CHECK17-NEXT:    br label [[COND_END:%.*]]
19061 // CHECK17:       cond.false:
19062 // CHECK17-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
19063 // CHECK17-NEXT:    br label [[COND_END]]
19064 // CHECK17:       cond.end:
19065 // CHECK17-NEXT:    [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ]
19066 // CHECK17-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
19067 // CHECK17-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
19068 // CHECK17-NEXT:    store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4
19069 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
19070 // CHECK17:       omp.inner.for.cond:
19071 // CHECK17-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27
19072 // CHECK17-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !27
19073 // CHECK17-NEXT:    [[ADD10:%.*]] = add i32 [[TMP17]], 1
19074 // CHECK17-NEXT:    [[CMP11:%.*]] = icmp ult i32 [[TMP16]], [[ADD10]]
19075 // CHECK17-NEXT:    br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
19076 // CHECK17:       omp.inner.for.body:
19077 // CHECK17-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group !27
19078 // CHECK17-NEXT:    [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27
19079 // CHECK17-NEXT:    [[MUL:%.*]] = mul i32 [[TMP19]], 1
19080 // CHECK17-NEXT:    [[ADD12:%.*]] = add i32 [[TMP18]], [[MUL]]
19081 // CHECK17-NEXT:    store i32 [[ADD12]], i32* [[I8]], align 4, !llvm.access.group !27
19082 // CHECK17-NEXT:    [[TMP20:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !27
19083 // CHECK17-NEXT:    [[ADD13:%.*]] = add nsw i32 [[TMP20]], 1
19084 // CHECK17-NEXT:    store i32 [[ADD13]], i32* [[CONV]], align 4, !llvm.access.group !27
19085 // CHECK17-NEXT:    [[TMP21:%.*]] = load i16, i16* [[CONV2]], align 2, !llvm.access.group !27
19086 // CHECK17-NEXT:    [[CONV14:%.*]] = sext i16 [[TMP21]] to i32
19087 // CHECK17-NEXT:    [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1
19088 // CHECK17-NEXT:    [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16
19089 // CHECK17-NEXT:    store i16 [[CONV16]], i16* [[CONV2]], align 2, !llvm.access.group !27
19090 // CHECK17-NEXT:    [[TMP22:%.*]] = load i8, i8* [[CONV3]], align 1, !llvm.access.group !27
19091 // CHECK17-NEXT:    [[CONV17:%.*]] = sext i8 [[TMP22]] to i32
19092 // CHECK17-NEXT:    [[ADD18:%.*]] = add nsw i32 [[CONV17]], 1
19093 // CHECK17-NEXT:    [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8
19094 // CHECK17-NEXT:    store i8 [[CONV19]], i8* [[CONV3]], align 1, !llvm.access.group !27
19095 // CHECK17-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
19096 // CHECK17-NEXT:    [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !27
19097 // CHECK17-NEXT:    [[ADD20:%.*]] = add nsw i32 [[TMP23]], 1
19098 // CHECK17-NEXT:    store i32 [[ADD20]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !27
19099 // CHECK17-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
19100 // CHECK17:       omp.body.continue:
19101 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
19102 // CHECK17:       omp.inner.for.inc:
19103 // CHECK17-NEXT:    [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27
19104 // CHECK17-NEXT:    [[ADD21:%.*]] = add i32 [[TMP24]], 1
19105 // CHECK17-NEXT:    store i32 [[ADD21]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27
19106 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]]
19107 // CHECK17:       omp.inner.for.end:
19108 // CHECK17-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
19109 // CHECK17:       omp.loop.exit:
19110 // CHECK17-NEXT:    [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
19111 // CHECK17-NEXT:    [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4
19112 // CHECK17-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]])
19113 // CHECK17-NEXT:    [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
19114 // CHECK17-NEXT:    [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0
19115 // CHECK17-NEXT:    br i1 [[TMP28]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
19116 // CHECK17:       .omp.final.then:
19117 // CHECK17-NEXT:    [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
19118 // CHECK17-NEXT:    [[TMP30:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4
19119 // CHECK17-NEXT:    [[TMP31:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
19120 // CHECK17-NEXT:    [[SUB22:%.*]] = sub i32 [[TMP30]], [[TMP31]]
19121 // CHECK17-NEXT:    [[SUB23:%.*]] = sub i32 [[SUB22]], 1
19122 // CHECK17-NEXT:    [[ADD24:%.*]] = add i32 [[SUB23]], 1
19123 // CHECK17-NEXT:    [[DIV25:%.*]] = udiv i32 [[ADD24]], 1
19124 // CHECK17-NEXT:    [[MUL26:%.*]] = mul i32 [[DIV25]], 1
19125 // CHECK17-NEXT:    [[ADD27:%.*]] = add i32 [[TMP29]], [[MUL26]]
19126 // CHECK17-NEXT:    store i32 [[ADD27]], i32* [[I8]], align 4
19127 // CHECK17-NEXT:    br label [[DOTOMP_FINAL_DONE]]
19128 // CHECK17:       .omp.final.done:
19129 // CHECK17-NEXT:    br label [[OMP_PRECOND_END]]
19130 // CHECK17:       omp.precond.end:
19131 // CHECK17-NEXT:    ret void
19132 //
19133 //
19134 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215
19135 // CHECK17-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {
19136 // CHECK17-NEXT:  entry:
19137 // CHECK17-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
19138 // CHECK17-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
19139 // CHECK17-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
19140 // CHECK17-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
19141 // CHECK17-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 8
19142 // CHECK17-NEXT:    [[B_CASTED:%.*]] = alloca i64, align 8
19143 // CHECK17-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
19144 // CHECK17-NEXT:    store i64 [[B]], i64* [[B_ADDR]], align 8
19145 // CHECK17-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
19146 // CHECK17-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
19147 // CHECK17-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 8
19148 // CHECK17-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
19149 // CHECK17-NEXT:    [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
19150 // CHECK17-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
19151 // CHECK17-NEXT:    [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
19152 // CHECK17-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
19153 // CHECK17-NEXT:    [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
19154 // CHECK17-NEXT:    [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32*
19155 // CHECK17-NEXT:    store i32 [[TMP4]], i32* [[CONV3]], align 4
19156 // CHECK17-NEXT:    [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
19157 // CHECK17-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]])
19158 // CHECK17-NEXT:    ret void
19159 //
19160 //
19161 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..5
19162 // CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] {
19163 // CHECK17-NEXT:  entry:
19164 // CHECK17-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
19165 // CHECK17-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
19166 // CHECK17-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
19167 // CHECK17-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
19168 // CHECK17-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
19169 // CHECK17-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
19170 // CHECK17-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 8
19171 // CHECK17-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
19172 // CHECK17-NEXT:    [[TMP:%.*]] = alloca i32, align 4
19173 // CHECK17-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
19174 // CHECK17-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
19175 // CHECK17-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
19176 // CHECK17-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
19177 // CHECK17-NEXT:    [[I:%.*]] = alloca i32, align 4
19178 // CHECK17-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
19179 // CHECK17-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
19180 // CHECK17-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
19181 // CHECK17-NEXT:    store i64 [[B]], i64* [[B_ADDR]], align 8
19182 // CHECK17-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
19183 // CHECK17-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
19184 // CHECK17-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 8
19185 // CHECK17-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
19186 // CHECK17-NEXT:    [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
19187 // CHECK17-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
19188 // CHECK17-NEXT:    [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
19189 // CHECK17-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
19190 // CHECK17-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
19191 // CHECK17-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
19192 // CHECK17-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
19193 // CHECK17-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
19194 // CHECK17-NEXT:    [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
19195 // CHECK17-NEXT:    [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
19196 // CHECK17-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
19197 // CHECK17-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
19198 // CHECK17-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 9
19199 // CHECK17-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
19200 // CHECK17:       cond.true:
19201 // CHECK17-NEXT:    br label [[COND_END:%.*]]
19202 // CHECK17:       cond.false:
19203 // CHECK17-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
19204 // CHECK17-NEXT:    br label [[COND_END]]
19205 // CHECK17:       cond.end:
19206 // CHECK17-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
19207 // CHECK17-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
19208 // CHECK17-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
19209 // CHECK17-NEXT:    store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
19210 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
19211 // CHECK17:       omp.inner.for.cond:
19212 // CHECK17-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30
19213 // CHECK17-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !30
19214 // CHECK17-NEXT:    [[CMP3:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
19215 // CHECK17-NEXT:    br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
19216 // CHECK17:       omp.inner.for.body:
19217 // CHECK17-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30
19218 // CHECK17-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
19219 // CHECK17-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
19220 // CHECK17-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !30
19221 // CHECK17-NEXT:    [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !30
19222 // CHECK17-NEXT:    [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double
19223 // CHECK17-NEXT:    [[ADD5:%.*]] = fadd double [[CONV4]], 1.500000e+00
19224 // CHECK17-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
19225 // CHECK17-NEXT:    store double [[ADD5]], double* [[A]], align 8, !llvm.access.group !30
19226 // CHECK17-NEXT:    [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
19227 // CHECK17-NEXT:    [[TMP13:%.*]] = load double, double* [[A6]], align 8, !llvm.access.group !30
19228 // CHECK17-NEXT:    [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00
19229 // CHECK17-NEXT:    store double [[INC]], double* [[A6]], align 8, !llvm.access.group !30
19230 // CHECK17-NEXT:    [[CONV7:%.*]] = fptosi double [[INC]] to i16
19231 // CHECK17-NEXT:    [[TMP14:%.*]] = mul nsw i64 1, [[TMP2]]
19232 // CHECK17-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP14]]
19233 // CHECK17-NEXT:    [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
19234 // CHECK17-NEXT:    store i16 [[CONV7]], i16* [[ARRAYIDX8]], align 2, !llvm.access.group !30
19235 // CHECK17-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
19236 // CHECK17:       omp.body.continue:
19237 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
19238 // CHECK17:       omp.inner.for.inc:
19239 // CHECK17-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30
19240 // CHECK17-NEXT:    [[ADD9:%.*]] = add nsw i32 [[TMP15]], 1
19241 // CHECK17-NEXT:    store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30
19242 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP31:![0-9]+]]
19243 // CHECK17:       omp.inner.for.end:
19244 // CHECK17-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
19245 // CHECK17:       omp.loop.exit:
19246 // CHECK17-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
19247 // CHECK17-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
19248 // CHECK17-NEXT:    [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0
19249 // CHECK17-NEXT:    br i1 [[TMP17]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
19250 // CHECK17:       .omp.final.then:
19251 // CHECK17-NEXT:    store i32 10, i32* [[I]], align 4
19252 // CHECK17-NEXT:    br label [[DOTOMP_FINAL_DONE]]
19253 // CHECK17:       .omp.final.done:
19254 // CHECK17-NEXT:    ret void
19255 //
19256 //
19257 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180
19258 // CHECK17-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
19259 // CHECK17-NEXT:  entry:
19260 // CHECK17-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
19261 // CHECK17-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
19262 // CHECK17-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
19263 // CHECK17-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
19264 // CHECK17-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
19265 // CHECK17-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
19266 // CHECK17-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
19267 // CHECK17-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
19268 // CHECK17-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
19269 // CHECK17-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
19270 // CHECK17-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
19271 // CHECK17-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
19272 // CHECK17-NEXT:    [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
19273 // CHECK17-NEXT:    store i32 [[TMP1]], i32* [[CONV2]], align 4
19274 // CHECK17-NEXT:    [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
19275 // CHECK17-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
19276 // CHECK17-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
19277 // CHECK17-NEXT:    store i16 [[TMP3]], i16* [[CONV3]], align 2
19278 // CHECK17-NEXT:    [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
19279 // CHECK17-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]])
19280 // CHECK17-NEXT:    ret void
19281 //
19282 //
19283 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..6
19284 // CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {
19285 // CHECK17-NEXT:  entry:
19286 // CHECK17-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
19287 // CHECK17-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
19288 // CHECK17-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
19289 // CHECK17-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
19290 // CHECK17-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
19291 // CHECK17-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
19292 // CHECK17-NEXT:    [[TMP:%.*]] = alloca i32, align 4
19293 // CHECK17-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
19294 // CHECK17-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
19295 // CHECK17-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
19296 // CHECK17-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
19297 // CHECK17-NEXT:    [[I:%.*]] = alloca i32, align 4
19298 // CHECK17-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
19299 // CHECK17-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
19300 // CHECK17-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
19301 // CHECK17-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
19302 // CHECK17-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
19303 // CHECK17-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
19304 // CHECK17-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
19305 // CHECK17-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
19306 // CHECK17-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
19307 // CHECK17-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
19308 // CHECK17-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
19309 // CHECK17-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
19310 // CHECK17-NEXT:    [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
19311 // CHECK17-NEXT:    [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
19312 // CHECK17-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
19313 // CHECK17-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
19314 // CHECK17-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9
19315 // CHECK17-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
19316 // CHECK17:       cond.true:
19317 // CHECK17-NEXT:    br label [[COND_END:%.*]]
19318 // CHECK17:       cond.false:
19319 // CHECK17-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
19320 // CHECK17-NEXT:    br label [[COND_END]]
19321 // CHECK17:       cond.end:
19322 // CHECK17-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
19323 // CHECK17-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
19324 // CHECK17-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
19325 // CHECK17-NEXT:    store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
19326 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
19327 // CHECK17:       omp.inner.for.cond:
19328 // CHECK17-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33
19329 // CHECK17-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !33
19330 // CHECK17-NEXT:    [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
19331 // CHECK17-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
19332 // CHECK17:       omp.inner.for.body:
19333 // CHECK17-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33
19334 // CHECK17-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
19335 // CHECK17-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
19336 // CHECK17-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !33
19337 // CHECK17-NEXT:    [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !33
19338 // CHECK17-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1
19339 // CHECK17-NEXT:    store i32 [[ADD3]], i32* [[CONV]], align 4, !llvm.access.group !33
19340 // CHECK17-NEXT:    [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 2, !llvm.access.group !33
19341 // CHECK17-NEXT:    [[CONV4:%.*]] = sext i16 [[TMP10]] to i32
19342 // CHECK17-NEXT:    [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
19343 // CHECK17-NEXT:    [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
19344 // CHECK17-NEXT:    store i16 [[CONV6]], i16* [[CONV1]], align 2, !llvm.access.group !33
19345 // CHECK17-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
19346 // CHECK17-NEXT:    [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !33
19347 // CHECK17-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1
19348 // CHECK17-NEXT:    store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !33
19349 // CHECK17-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
19350 // CHECK17:       omp.body.continue:
19351 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
19352 // CHECK17:       omp.inner.for.inc:
19353 // CHECK17-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33
19354 // CHECK17-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP12]], 1
19355 // CHECK17-NEXT:    store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33
19356 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP34:![0-9]+]]
19357 // CHECK17:       omp.inner.for.end:
19358 // CHECK17-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
19359 // CHECK17:       omp.loop.exit:
19360 // CHECK17-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
19361 // CHECK17-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
19362 // CHECK17-NEXT:    [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
19363 // CHECK17-NEXT:    br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
19364 // CHECK17:       .omp.final.then:
19365 // CHECK17-NEXT:    store i32 10, i32* [[I]], align 4
19366 // CHECK17-NEXT:    br label [[DOTOMP_FINAL_DONE]]
19367 // CHECK17:       .omp.final.done:
19368 // CHECK17-NEXT:    ret void
19369 //
19370 //
19371 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97
19372 // CHECK18-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] {
19373 // CHECK18-NEXT:  entry:
19374 // CHECK18-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
19375 // CHECK18-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
19376 // CHECK18-NEXT:    [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8
19377 // CHECK18-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
19378 // CHECK18-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]])
19379 // CHECK18-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
19380 // CHECK18-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
19381 // CHECK18-NEXT:    store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8
19382 // CHECK18-NEXT:    [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
19383 // CHECK18-NEXT:    [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
19384 // CHECK18-NEXT:    [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32*
19385 // CHECK18-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 4
19386 // CHECK18-NEXT:    [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 4
19387 // CHECK18-NEXT:    call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
19388 // CHECK18-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
19389 // CHECK18-NEXT:    [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
19390 // CHECK18-NEXT:    store i16 [[TMP3]], i16* [[CONV5]], align 2
19391 // CHECK18-NEXT:    [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
19392 // CHECK18-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]])
19393 // CHECK18-NEXT:    ret void
19394 //
19395 //
19396 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined.
19397 // CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR1:[0-9]+]] {
19398 // CHECK18-NEXT:  entry:
19399 // CHECK18-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
19400 // CHECK18-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
19401 // CHECK18-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
19402 // CHECK18-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
19403 // CHECK18-NEXT:    [[TMP:%.*]] = alloca i32, align 4
19404 // CHECK18-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
19405 // CHECK18-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
19406 // CHECK18-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
19407 // CHECK18-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
19408 // CHECK18-NEXT:    [[I:%.*]] = alloca i32, align 4
19409 // CHECK18-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
19410 // CHECK18-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
19411 // CHECK18-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
19412 // CHECK18-NEXT:    [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
19413 // CHECK18-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
19414 // CHECK18-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
19415 // CHECK18-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
19416 // CHECK18-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
19417 // CHECK18-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
19418 // CHECK18-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
19419 // CHECK18-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
19420 // CHECK18-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
19421 // CHECK18-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
19422 // CHECK18-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
19423 // CHECK18:       cond.true:
19424 // CHECK18-NEXT:    br label [[COND_END:%.*]]
19425 // CHECK18:       cond.false:
19426 // CHECK18-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
19427 // CHECK18-NEXT:    br label [[COND_END]]
19428 // CHECK18:       cond.end:
19429 // CHECK18-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
19430 // CHECK18-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
19431 // CHECK18-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
19432 // CHECK18-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
19433 // CHECK18-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
19434 // CHECK18:       omp.inner.for.cond:
19435 // CHECK18-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
19436 // CHECK18-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !11
19437 // CHECK18-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
19438 // CHECK18-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
19439 // CHECK18:       omp.inner.for.body:
19440 // CHECK18-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
19441 // CHECK18-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
19442 // CHECK18-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
19443 // CHECK18-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11
19444 // CHECK18-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
19445 // CHECK18:       omp.body.continue:
19446 // CHECK18-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
19447 // CHECK18:       omp.inner.for.inc:
19448 // CHECK18-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
19449 // CHECK18-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
19450 // CHECK18-NEXT:    store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
19451 // CHECK18-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]
19452 // CHECK18:       omp.inner.for.end:
19453 // CHECK18-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
19454 // CHECK18:       omp.loop.exit:
19455 // CHECK18-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
19456 // CHECK18-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
19457 // CHECK18-NEXT:    [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0
19458 // CHECK18-NEXT:    br i1 [[TMP10]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
19459 // CHECK18:       .omp.final.then:
19460 // CHECK18-NEXT:    store i32 10, i32* [[I]], align 4
19461 // CHECK18-NEXT:    br label [[DOTOMP_FINAL_DONE]]
19462 // CHECK18:       .omp.final.done:
19463 // CHECK18-NEXT:    ret void
19464 //
19465 //
19466 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111
19467 // CHECK18-SAME: (i64 noundef [[AA:%.*]]) #[[ATTR0]] {
19468 // CHECK18-NEXT:  entry:
19469 // CHECK18-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
19470 // CHECK18-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
19471 // CHECK18-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
19472 // CHECK18-NEXT:    [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
19473 // CHECK18-NEXT:    [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
19474 // CHECK18-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
19475 // CHECK18-NEXT:    store i16 [[TMP0]], i16* [[CONV1]], align 2
19476 // CHECK18-NEXT:    [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
19477 // CHECK18-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]])
19478 // CHECK18-NEXT:    ret void
19479 //
19480 //
19481 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..1
19482 // CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR1]] {
19483 // CHECK18-NEXT:  entry:
19484 // CHECK18-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
19485 // CHECK18-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
19486 // CHECK18-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
19487 // CHECK18-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
19488 // CHECK18-NEXT:    [[TMP:%.*]] = alloca i32, align 4
19489 // CHECK18-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
19490 // CHECK18-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
19491 // CHECK18-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
19492 // CHECK18-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
19493 // CHECK18-NEXT:    [[I:%.*]] = alloca i32, align 4
19494 // CHECK18-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
19495 // CHECK18-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
19496 // CHECK18-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
19497 // CHECK18-NEXT:    [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
19498 // CHECK18-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
19499 // CHECK18-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
19500 // CHECK18-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
19501 // CHECK18-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
19502 // CHECK18-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
19503 // CHECK18-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
19504 // CHECK18-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
19505 // CHECK18-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
19506 // CHECK18-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
19507 // CHECK18-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
19508 // CHECK18:       cond.true:
19509 // CHECK18-NEXT:    br label [[COND_END:%.*]]
19510 // CHECK18:       cond.false:
19511 // CHECK18-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
19512 // CHECK18-NEXT:    br label [[COND_END]]
19513 // CHECK18:       cond.end:
19514 // CHECK18-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
19515 // CHECK18-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
19516 // CHECK18-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
19517 // CHECK18-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
19518 // CHECK18-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
19519 // CHECK18:       omp.inner.for.cond:
19520 // CHECK18-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
19521 // CHECK18-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !18
19522 // CHECK18-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
19523 // CHECK18-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
19524 // CHECK18:       omp.inner.for.body:
19525 // CHECK18-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
19526 // CHECK18-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
19527 // CHECK18-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
19528 // CHECK18-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18
19529 // CHECK18-NEXT:    [[TMP8:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !18
19530 // CHECK18-NEXT:    [[CONV2:%.*]] = sext i16 [[TMP8]] to i32
19531 // CHECK18-NEXT:    [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
19532 // CHECK18-NEXT:    [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
19533 // CHECK18-NEXT:    store i16 [[CONV4]], i16* [[CONV]], align 2, !llvm.access.group !18
19534 // CHECK18-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
19535 // CHECK18:       omp.body.continue:
19536 // CHECK18-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
19537 // CHECK18:       omp.inner.for.inc:
19538 // CHECK18-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
19539 // CHECK18-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP9]], 1
19540 // CHECK18-NEXT:    store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
19541 // CHECK18-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]
19542 // CHECK18:       omp.inner.for.end:
19543 // CHECK18-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
19544 // CHECK18:       omp.loop.exit:
19545 // CHECK18-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
19546 // CHECK18-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
19547 // CHECK18-NEXT:    [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0
19548 // CHECK18-NEXT:    br i1 [[TMP11]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
19549 // CHECK18:       .omp.final.then:
19550 // CHECK18-NEXT:    store i32 10, i32* [[I]], align 4
19551 // CHECK18-NEXT:    br label [[DOTOMP_FINAL_DONE]]
19552 // CHECK18:       .omp.final.done:
19553 // CHECK18-NEXT:    ret void
19554 //
19555 //
19556 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118
19557 // CHECK18-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] {
19558 // CHECK18-NEXT:  entry:
19559 // CHECK18-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
19560 // CHECK18-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
19561 // CHECK18-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
19562 // CHECK18-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
19563 // CHECK18-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
19564 // CHECK18-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
19565 // CHECK18-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
19566 // CHECK18-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
19567 // CHECK18-NEXT:    [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
19568 // CHECK18-NEXT:    [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
19569 // CHECK18-NEXT:    store i32 [[TMP0]], i32* [[CONV2]], align 4
19570 // CHECK18-NEXT:    [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
19571 // CHECK18-NEXT:    [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
19572 // CHECK18-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
19573 // CHECK18-NEXT:    store i16 [[TMP2]], i16* [[CONV3]], align 2
19574 // CHECK18-NEXT:    [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
19575 // CHECK18-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
19576 // CHECK18-NEXT:    ret void
19577 //
19578 //
19579 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..2
19580 // CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR1]] {
19581 // CHECK18-NEXT:  entry:
19582 // CHECK18-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
19583 // CHECK18-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
19584 // CHECK18-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
19585 // CHECK18-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
19586 // CHECK18-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
19587 // CHECK18-NEXT:    [[TMP:%.*]] = alloca i32, align 4
19588 // CHECK18-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
19589 // CHECK18-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
19590 // CHECK18-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
19591 // CHECK18-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
19592 // CHECK18-NEXT:    [[I:%.*]] = alloca i32, align 4
19593 // CHECK18-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
19594 // CHECK18-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
19595 // CHECK18-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
19596 // CHECK18-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
19597 // CHECK18-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
19598 // CHECK18-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
19599 // CHECK18-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
19600 // CHECK18-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
19601 // CHECK18-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
19602 // CHECK18-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
19603 // CHECK18-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
19604 // CHECK18-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
19605 // CHECK18-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
19606 // CHECK18-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
19607 // CHECK18-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
19608 // CHECK18-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
19609 // CHECK18:       cond.true:
19610 // CHECK18-NEXT:    br label [[COND_END:%.*]]
19611 // CHECK18:       cond.false:
19612 // CHECK18-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
19613 // CHECK18-NEXT:    br label [[COND_END]]
19614 // CHECK18:       cond.end:
19615 // CHECK18-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
19616 // CHECK18-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
19617 // CHECK18-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
19618 // CHECK18-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
19619 // CHECK18-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
19620 // CHECK18:       omp.inner.for.cond:
19621 // CHECK18-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
19622 // CHECK18-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !21
19623 // CHECK18-NEXT:    [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
19624 // CHECK18-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
19625 // CHECK18:       omp.inner.for.body:
19626 // CHECK18-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
19627 // CHECK18-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
19628 // CHECK18-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
19629 // CHECK18-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !21
19630 // CHECK18-NEXT:    [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !21
19631 // CHECK18-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
19632 // CHECK18-NEXT:    store i32 [[ADD3]], i32* [[CONV]], align 4, !llvm.access.group !21
19633 // CHECK18-NEXT:    [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 2, !llvm.access.group !21
19634 // CHECK18-NEXT:    [[CONV4:%.*]] = sext i16 [[TMP9]] to i32
19635 // CHECK18-NEXT:    [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
19636 // CHECK18-NEXT:    [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
19637 // CHECK18-NEXT:    store i16 [[CONV6]], i16* [[CONV1]], align 2, !llvm.access.group !21
19638 // CHECK18-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
19639 // CHECK18:       omp.body.continue:
19640 // CHECK18-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
19641 // CHECK18:       omp.inner.for.inc:
19642 // CHECK18-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
19643 // CHECK18-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1
19644 // CHECK18-NEXT:    store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
19645 // CHECK18-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]]
19646 // CHECK18:       omp.inner.for.end:
19647 // CHECK18-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
19648 // CHECK18:       omp.loop.exit:
19649 // CHECK18-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
19650 // CHECK18-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
19651 // CHECK18-NEXT:    [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
19652 // CHECK18-NEXT:    br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
19653 // CHECK18:       .omp.final.then:
19654 // CHECK18-NEXT:    store i32 10, i32* [[I]], align 4
19655 // CHECK18-NEXT:    br label [[DOTOMP_FINAL_DONE]]
19656 // CHECK18:       .omp.final.done:
19657 // CHECK18-NEXT:    ret void
19658 //
19659 //
19660 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142
19661 // CHECK18-SAME: (i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] {
19662 // CHECK18-NEXT:  entry:
19663 // CHECK18-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
19664 // CHECK18-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
19665 // CHECK18-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
19666 // CHECK18-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 8
19667 // CHECK18-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
19668 // CHECK18-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
19669 // CHECK18-NEXT:    [[VLA_ADDR4:%.*]] = alloca i64, align 8
19670 // CHECK18-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 8
19671 // CHECK18-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
19672 // CHECK18-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
19673 // CHECK18-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
19674 // CHECK18-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
19675 // CHECK18-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
19676 // CHECK18-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 8
19677 // CHECK18-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
19678 // CHECK18-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
19679 // CHECK18-NEXT:    store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
19680 // CHECK18-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 8
19681 // CHECK18-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
19682 // CHECK18-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
19683 // CHECK18-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
19684 // CHECK18-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
19685 // CHECK18-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
19686 // CHECK18-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
19687 // CHECK18-NEXT:    [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
19688 // CHECK18-NEXT:    [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
19689 // CHECK18-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
19690 // CHECK18-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
19691 // CHECK18-NEXT:    [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
19692 // CHECK18-NEXT:    [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
19693 // CHECK18-NEXT:    store i32 [[TMP8]], i32* [[CONV5]], align 4
19694 // CHECK18-NEXT:    [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
19695 // CHECK18-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]])
19696 // CHECK18-NEXT:    ret void
19697 //
19698 //
19699 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..3
19700 // CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR1]] {
19701 // CHECK18-NEXT:  entry:
19702 // CHECK18-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
19703 // CHECK18-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
19704 // CHECK18-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
19705 // CHECK18-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
19706 // CHECK18-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
19707 // CHECK18-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 8
19708 // CHECK18-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
19709 // CHECK18-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
19710 // CHECK18-NEXT:    [[VLA_ADDR4:%.*]] = alloca i64, align 8
19711 // CHECK18-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 8
19712 // CHECK18-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
19713 // CHECK18-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
19714 // CHECK18-NEXT:    [[TMP:%.*]] = alloca i32, align 4
19715 // CHECK18-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
19716 // CHECK18-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
19717 // CHECK18-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
19718 // CHECK18-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
19719 // CHECK18-NEXT:    [[I:%.*]] = alloca i32, align 4
19720 // CHECK18-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
19721 // CHECK18-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
19722 // CHECK18-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
19723 // CHECK18-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
19724 // CHECK18-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
19725 // CHECK18-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 8
19726 // CHECK18-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
19727 // CHECK18-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
19728 // CHECK18-NEXT:    store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
19729 // CHECK18-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 8
19730 // CHECK18-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
19731 // CHECK18-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
19732 // CHECK18-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
19733 // CHECK18-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
19734 // CHECK18-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
19735 // CHECK18-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
19736 // CHECK18-NEXT:    [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
19737 // CHECK18-NEXT:    [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
19738 // CHECK18-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
19739 // CHECK18-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
19740 // CHECK18-NEXT:    [[ARRAYDECAY:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 0
19741 // CHECK18-NEXT:    call void @llvm.assume(i1 true) [ "align"(float* [[ARRAYDECAY]], i64 16) ]
19742 // CHECK18-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
19743 // CHECK18-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
19744 // CHECK18-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
19745 // CHECK18-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
19746 // CHECK18-NEXT:    [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
19747 // CHECK18-NEXT:    [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4
19748 // CHECK18-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
19749 // CHECK18-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
19750 // CHECK18-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP10]], 9
19751 // CHECK18-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
19752 // CHECK18:       cond.true:
19753 // CHECK18-NEXT:    br label [[COND_END:%.*]]
19754 // CHECK18:       cond.false:
19755 // CHECK18-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
19756 // CHECK18-NEXT:    br label [[COND_END]]
19757 // CHECK18:       cond.end:
19758 // CHECK18-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ]
19759 // CHECK18-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
19760 // CHECK18-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
19761 // CHECK18-NEXT:    store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4
19762 // CHECK18-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
19763 // CHECK18:       omp.inner.for.cond:
19764 // CHECK18-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
19765 // CHECK18-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !24
19766 // CHECK18-NEXT:    [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
19767 // CHECK18-NEXT:    br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
19768 // CHECK18:       omp.inner.for.body:
19769 // CHECK18-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
19770 // CHECK18-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1
19771 // CHECK18-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
19772 // CHECK18-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !24
19773 // CHECK18-NEXT:    [[TMP16:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !24
19774 // CHECK18-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP16]], 1
19775 // CHECK18-NEXT:    store i32 [[ADD6]], i32* [[CONV]], align 4, !llvm.access.group !24
19776 // CHECK18-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
19777 // CHECK18-NEXT:    [[TMP17:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !24
19778 // CHECK18-NEXT:    [[CONV7:%.*]] = fpext float [[TMP17]] to double
19779 // CHECK18-NEXT:    [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00
19780 // CHECK18-NEXT:    [[CONV9:%.*]] = fptrunc double [[ADD8]] to float
19781 // CHECK18-NEXT:    store float [[CONV9]], float* [[ARRAYIDX]], align 4, !llvm.access.group !24
19782 // CHECK18-NEXT:    [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3
19783 // CHECK18-NEXT:    [[TMP18:%.*]] = load float, float* [[ARRAYIDX10]], align 4, !llvm.access.group !24
19784 // CHECK18-NEXT:    [[CONV11:%.*]] = fpext float [[TMP18]] to double
19785 // CHECK18-NEXT:    [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00
19786 // CHECK18-NEXT:    [[CONV13:%.*]] = fptrunc double [[ADD12]] to float
19787 // CHECK18-NEXT:    store float [[CONV13]], float* [[ARRAYIDX10]], align 4, !llvm.access.group !24
19788 // CHECK18-NEXT:    [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1
19789 // CHECK18-NEXT:    [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX14]], i64 0, i64 2
19790 // CHECK18-NEXT:    [[TMP19:%.*]] = load double, double* [[ARRAYIDX15]], align 8, !llvm.access.group !24
19791 // CHECK18-NEXT:    [[ADD16:%.*]] = fadd double [[TMP19]], 1.000000e+00
19792 // CHECK18-NEXT:    store double [[ADD16]], double* [[ARRAYIDX15]], align 8, !llvm.access.group !24
19793 // CHECK18-NEXT:    [[TMP20:%.*]] = mul nsw i64 1, [[TMP5]]
19794 // CHECK18-NEXT:    [[ARRAYIDX17:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP20]]
19795 // CHECK18-NEXT:    [[ARRAYIDX18:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX17]], i64 3
19796 // CHECK18-NEXT:    [[TMP21:%.*]] = load double, double* [[ARRAYIDX18]], align 8, !llvm.access.group !24
19797 // CHECK18-NEXT:    [[ADD19:%.*]] = fadd double [[TMP21]], 1.000000e+00
19798 // CHECK18-NEXT:    store double [[ADD19]], double* [[ARRAYIDX18]], align 8, !llvm.access.group !24
19799 // CHECK18-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0
19800 // CHECK18-NEXT:    [[TMP22:%.*]] = load i64, i64* [[X]], align 8, !llvm.access.group !24
19801 // CHECK18-NEXT:    [[ADD20:%.*]] = add nsw i64 [[TMP22]], 1
19802 // CHECK18-NEXT:    store i64 [[ADD20]], i64* [[X]], align 8, !llvm.access.group !24
19803 // CHECK18-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1
19804 // CHECK18-NEXT:    [[TMP23:%.*]] = load i8, i8* [[Y]], align 8, !llvm.access.group !24
19805 // CHECK18-NEXT:    [[CONV21:%.*]] = sext i8 [[TMP23]] to i32
19806 // CHECK18-NEXT:    [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1
19807 // CHECK18-NEXT:    [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8
19808 // CHECK18-NEXT:    store i8 [[CONV23]], i8* [[Y]], align 8, !llvm.access.group !24
19809 // CHECK18-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
19810 // CHECK18:       omp.body.continue:
19811 // CHECK18-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
19812 // CHECK18:       omp.inner.for.inc:
19813 // CHECK18-NEXT:    [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
19814 // CHECK18-NEXT:    [[ADD24:%.*]] = add nsw i32 [[TMP24]], 1
19815 // CHECK18-NEXT:    store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
19816 // CHECK18-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]]
19817 // CHECK18:       omp.inner.for.end:
19818 // CHECK18-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
19819 // CHECK18:       omp.loop.exit:
19820 // CHECK18-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]])
19821 // CHECK18-NEXT:    [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
19822 // CHECK18-NEXT:    [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
19823 // CHECK18-NEXT:    br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
19824 // CHECK18:       .omp.final.then:
19825 // CHECK18-NEXT:    store i32 10, i32* [[I]], align 4
19826 // CHECK18-NEXT:    br label [[DOTOMP_FINAL_DONE]]
19827 // CHECK18:       .omp.final.done:
19828 // CHECK18-NEXT:    ret void
19829 //
19830 //
19831 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197
19832 // CHECK18-SAME: (i64 noundef [[A:%.*]], i64 noundef [[N:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
19833 // CHECK18-NEXT:  entry:
19834 // CHECK18-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
19835 // CHECK18-NEXT:    [[N_ADDR:%.*]] = alloca i64, align 8
19836 // CHECK18-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
19837 // CHECK18-NEXT:    [[AAA_ADDR:%.*]] = alloca i64, align 8
19838 // CHECK18-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
19839 // CHECK18-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
19840 // CHECK18-NEXT:    [[N_CASTED:%.*]] = alloca i64, align 8
19841 // CHECK18-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
19842 // CHECK18-NEXT:    [[AAA_CASTED:%.*]] = alloca i64, align 8
19843 // CHECK18-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
19844 // CHECK18-NEXT:    store i64 [[N]], i64* [[N_ADDR]], align 8
19845 // CHECK18-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
19846 // CHECK18-NEXT:    store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
19847 // CHECK18-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
19848 // CHECK18-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
19849 // CHECK18-NEXT:    [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32*
19850 // CHECK18-NEXT:    [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
19851 // CHECK18-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
19852 // CHECK18-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
19853 // CHECK18-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
19854 // CHECK18-NEXT:    [[CONV4:%.*]] = bitcast i64* [[A_CASTED]] to i32*
19855 // CHECK18-NEXT:    store i32 [[TMP1]], i32* [[CONV4]], align 4
19856 // CHECK18-NEXT:    [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
19857 // CHECK18-NEXT:    [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 4
19858 // CHECK18-NEXT:    [[CONV5:%.*]] = bitcast i64* [[N_CASTED]] to i32*
19859 // CHECK18-NEXT:    store i32 [[TMP3]], i32* [[CONV5]], align 4
19860 // CHECK18-NEXT:    [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8
19861 // CHECK18-NEXT:    [[TMP5:%.*]] = load i16, i16* [[CONV2]], align 2
19862 // CHECK18-NEXT:    [[CONV6:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
19863 // CHECK18-NEXT:    store i16 [[TMP5]], i16* [[CONV6]], align 2
19864 // CHECK18-NEXT:    [[TMP6:%.*]] = load i64, i64* [[AA_CASTED]], align 8
19865 // CHECK18-NEXT:    [[TMP7:%.*]] = load i8, i8* [[CONV3]], align 1
19866 // CHECK18-NEXT:    [[CONV7:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
19867 // CHECK18-NEXT:    store i8 [[TMP7]], i8* [[CONV7]], align 1
19868 // CHECK18-NEXT:    [[TMP8:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
19869 // CHECK18-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]], [10 x i32]* [[TMP0]])
19870 // CHECK18-NEXT:    ret void
19871 //
19872 //
19873 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..4
19874 // CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[N:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {
19875 // CHECK18-NEXT:  entry:
19876 // CHECK18-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
19877 // CHECK18-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
19878 // CHECK18-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
19879 // CHECK18-NEXT:    [[N_ADDR:%.*]] = alloca i64, align 8
19880 // CHECK18-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
19881 // CHECK18-NEXT:    [[AAA_ADDR:%.*]] = alloca i64, align 8
19882 // CHECK18-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
19883 // CHECK18-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
19884 // CHECK18-NEXT:    [[TMP:%.*]] = alloca i32, align 4
19885 // CHECK18-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
19886 // CHECK18-NEXT:    [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4
19887 // CHECK18-NEXT:    [[DOTCAPTURE_EXPR_5:%.*]] = alloca i32, align 4
19888 // CHECK18-NEXT:    [[I:%.*]] = alloca i32, align 4
19889 // CHECK18-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
19890 // CHECK18-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
19891 // CHECK18-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
19892 // CHECK18-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
19893 // CHECK18-NEXT:    [[I8:%.*]] = alloca i32, align 4
19894 // CHECK18-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
19895 // CHECK18-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
19896 // CHECK18-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
19897 // CHECK18-NEXT:    store i64 [[N]], i64* [[N_ADDR]], align 8
19898 // CHECK18-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
19899 // CHECK18-NEXT:    store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
19900 // CHECK18-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
19901 // CHECK18-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
19902 // CHECK18-NEXT:    [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32*
19903 // CHECK18-NEXT:    [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
19904 // CHECK18-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
19905 // CHECK18-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
19906 // CHECK18-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
19907 // CHECK18-NEXT:    store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
19908 // CHECK18-NEXT:    [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4
19909 // CHECK18-NEXT:    store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_4]], align 4
19910 // CHECK18-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4
19911 // CHECK18-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
19912 // CHECK18-NEXT:    [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]]
19913 // CHECK18-NEXT:    [[SUB6:%.*]] = sub i32 [[SUB]], 1
19914 // CHECK18-NEXT:    [[ADD:%.*]] = add i32 [[SUB6]], 1
19915 // CHECK18-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], 1
19916 // CHECK18-NEXT:    [[SUB7:%.*]] = sub i32 [[DIV]], 1
19917 // CHECK18-NEXT:    store i32 [[SUB7]], i32* [[DOTCAPTURE_EXPR_5]], align 4
19918 // CHECK18-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
19919 // CHECK18-NEXT:    store i32 [[TMP5]], i32* [[I]], align 4
19920 // CHECK18-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
19921 // CHECK18-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4
19922 // CHECK18-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]]
19923 // CHECK18-NEXT:    br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
19924 // CHECK18:       omp.precond.then:
19925 // CHECK18-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
19926 // CHECK18-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4
19927 // CHECK18-NEXT:    store i32 [[TMP8]], i32* [[DOTOMP_UB]], align 4
19928 // CHECK18-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
19929 // CHECK18-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
19930 // CHECK18-NEXT:    [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
19931 // CHECK18-NEXT:    [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
19932 // CHECK18-NEXT:    call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
19933 // CHECK18-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
19934 // CHECK18-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4
19935 // CHECK18-NEXT:    [[CMP9:%.*]] = icmp ugt i32 [[TMP11]], [[TMP12]]
19936 // CHECK18-NEXT:    br i1 [[CMP9]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
19937 // CHECK18:       cond.true:
19938 // CHECK18-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4
19939 // CHECK18-NEXT:    br label [[COND_END:%.*]]
19940 // CHECK18:       cond.false:
19941 // CHECK18-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
19942 // CHECK18-NEXT:    br label [[COND_END]]
19943 // CHECK18:       cond.end:
19944 // CHECK18-NEXT:    [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ]
19945 // CHECK18-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
19946 // CHECK18-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
19947 // CHECK18-NEXT:    store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4
19948 // CHECK18-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
19949 // CHECK18:       omp.inner.for.cond:
19950 // CHECK18-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27
19951 // CHECK18-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !27
19952 // CHECK18-NEXT:    [[ADD10:%.*]] = add i32 [[TMP17]], 1
19953 // CHECK18-NEXT:    [[CMP11:%.*]] = icmp ult i32 [[TMP16]], [[ADD10]]
19954 // CHECK18-NEXT:    br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
19955 // CHECK18:       omp.inner.for.body:
19956 // CHECK18-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group !27
19957 // CHECK18-NEXT:    [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27
19958 // CHECK18-NEXT:    [[MUL:%.*]] = mul i32 [[TMP19]], 1
19959 // CHECK18-NEXT:    [[ADD12:%.*]] = add i32 [[TMP18]], [[MUL]]
19960 // CHECK18-NEXT:    store i32 [[ADD12]], i32* [[I8]], align 4, !llvm.access.group !27
19961 // CHECK18-NEXT:    [[TMP20:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !27
19962 // CHECK18-NEXT:    [[ADD13:%.*]] = add nsw i32 [[TMP20]], 1
19963 // CHECK18-NEXT:    store i32 [[ADD13]], i32* [[CONV]], align 4, !llvm.access.group !27
19964 // CHECK18-NEXT:    [[TMP21:%.*]] = load i16, i16* [[CONV2]], align 2, !llvm.access.group !27
19965 // CHECK18-NEXT:    [[CONV14:%.*]] = sext i16 [[TMP21]] to i32
19966 // CHECK18-NEXT:    [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1
19967 // CHECK18-NEXT:    [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16
19968 // CHECK18-NEXT:    store i16 [[CONV16]], i16* [[CONV2]], align 2, !llvm.access.group !27
19969 // CHECK18-NEXT:    [[TMP22:%.*]] = load i8, i8* [[CONV3]], align 1, !llvm.access.group !27
19970 // CHECK18-NEXT:    [[CONV17:%.*]] = sext i8 [[TMP22]] to i32
19971 // CHECK18-NEXT:    [[ADD18:%.*]] = add nsw i32 [[CONV17]], 1
19972 // CHECK18-NEXT:    [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8
19973 // CHECK18-NEXT:    store i8 [[CONV19]], i8* [[CONV3]], align 1, !llvm.access.group !27
19974 // CHECK18-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
19975 // CHECK18-NEXT:    [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !27
19976 // CHECK18-NEXT:    [[ADD20:%.*]] = add nsw i32 [[TMP23]], 1
19977 // CHECK18-NEXT:    store i32 [[ADD20]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !27
19978 // CHECK18-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
19979 // CHECK18:       omp.body.continue:
19980 // CHECK18-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
19981 // CHECK18:       omp.inner.for.inc:
19982 // CHECK18-NEXT:    [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27
19983 // CHECK18-NEXT:    [[ADD21:%.*]] = add i32 [[TMP24]], 1
19984 // CHECK18-NEXT:    store i32 [[ADD21]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27
19985 // CHECK18-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]]
19986 // CHECK18:       omp.inner.for.end:
19987 // CHECK18-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
19988 // CHECK18:       omp.loop.exit:
19989 // CHECK18-NEXT:    [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
19990 // CHECK18-NEXT:    [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4
19991 // CHECK18-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]])
19992 // CHECK18-NEXT:    [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
19993 // CHECK18-NEXT:    [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0
19994 // CHECK18-NEXT:    br i1 [[TMP28]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
19995 // CHECK18:       .omp.final.then:
19996 // CHECK18-NEXT:    [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
19997 // CHECK18-NEXT:    [[TMP30:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4
19998 // CHECK18-NEXT:    [[TMP31:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
19999 // CHECK18-NEXT:    [[SUB22:%.*]] = sub i32 [[TMP30]], [[TMP31]]
20000 // CHECK18-NEXT:    [[SUB23:%.*]] = sub i32 [[SUB22]], 1
20001 // CHECK18-NEXT:    [[ADD24:%.*]] = add i32 [[SUB23]], 1
20002 // CHECK18-NEXT:    [[DIV25:%.*]] = udiv i32 [[ADD24]], 1
20003 // CHECK18-NEXT:    [[MUL26:%.*]] = mul i32 [[DIV25]], 1
20004 // CHECK18-NEXT:    [[ADD27:%.*]] = add i32 [[TMP29]], [[MUL26]]
20005 // CHECK18-NEXT:    store i32 [[ADD27]], i32* [[I8]], align 4
20006 // CHECK18-NEXT:    br label [[DOTOMP_FINAL_DONE]]
20007 // CHECK18:       .omp.final.done:
20008 // CHECK18-NEXT:    br label [[OMP_PRECOND_END]]
20009 // CHECK18:       omp.precond.end:
20010 // CHECK18-NEXT:    ret void
20011 //
20012 //
20013 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215
20014 // CHECK18-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {
20015 // CHECK18-NEXT:  entry:
20016 // CHECK18-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
20017 // CHECK18-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
20018 // CHECK18-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
20019 // CHECK18-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
20020 // CHECK18-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 8
20021 // CHECK18-NEXT:    [[B_CASTED:%.*]] = alloca i64, align 8
20022 // CHECK18-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
20023 // CHECK18-NEXT:    store i64 [[B]], i64* [[B_ADDR]], align 8
20024 // CHECK18-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
20025 // CHECK18-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
20026 // CHECK18-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 8
20027 // CHECK18-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
20028 // CHECK18-NEXT:    [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
20029 // CHECK18-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
20030 // CHECK18-NEXT:    [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
20031 // CHECK18-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
20032 // CHECK18-NEXT:    [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
20033 // CHECK18-NEXT:    [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32*
20034 // CHECK18-NEXT:    store i32 [[TMP4]], i32* [[CONV3]], align 4
20035 // CHECK18-NEXT:    [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
20036 // CHECK18-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]])
20037 // CHECK18-NEXT:    ret void
20038 //
20039 //
20040 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..5
20041 // CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] {
20042 // CHECK18-NEXT:  entry:
20043 // CHECK18-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
20044 // CHECK18-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
20045 // CHECK18-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
20046 // CHECK18-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
20047 // CHECK18-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
20048 // CHECK18-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
20049 // CHECK18-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 8
20050 // CHECK18-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
20051 // CHECK18-NEXT:    [[TMP:%.*]] = alloca i32, align 4
20052 // CHECK18-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
20053 // CHECK18-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
20054 // CHECK18-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
20055 // CHECK18-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
20056 // CHECK18-NEXT:    [[I:%.*]] = alloca i32, align 4
20057 // CHECK18-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
20058 // CHECK18-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
20059 // CHECK18-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
20060 // CHECK18-NEXT:    store i64 [[B]], i64* [[B_ADDR]], align 8
20061 // CHECK18-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
20062 // CHECK18-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
20063 // CHECK18-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 8
20064 // CHECK18-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
20065 // CHECK18-NEXT:    [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
20066 // CHECK18-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
20067 // CHECK18-NEXT:    [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
20068 // CHECK18-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
20069 // CHECK18-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
20070 // CHECK18-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
20071 // CHECK18-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
20072 // CHECK18-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
20073 // CHECK18-NEXT:    [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
20074 // CHECK18-NEXT:    [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
20075 // CHECK18-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
20076 // CHECK18-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
20077 // CHECK18-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 9
20078 // CHECK18-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
20079 // CHECK18:       cond.true:
20080 // CHECK18-NEXT:    br label [[COND_END:%.*]]
20081 // CHECK18:       cond.false:
20082 // CHECK18-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
20083 // CHECK18-NEXT:    br label [[COND_END]]
20084 // CHECK18:       cond.end:
20085 // CHECK18-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
20086 // CHECK18-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
20087 // CHECK18-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
20088 // CHECK18-NEXT:    store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
20089 // CHECK18-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
20090 // CHECK18:       omp.inner.for.cond:
20091 // CHECK18-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30
20092 // CHECK18-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !30
20093 // CHECK18-NEXT:    [[CMP3:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
20094 // CHECK18-NEXT:    br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
20095 // CHECK18:       omp.inner.for.body:
20096 // CHECK18-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30
20097 // CHECK18-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
20098 // CHECK18-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
20099 // CHECK18-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !30
20100 // CHECK18-NEXT:    [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !30
20101 // CHECK18-NEXT:    [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double
20102 // CHECK18-NEXT:    [[ADD5:%.*]] = fadd double [[CONV4]], 1.500000e+00
20103 // CHECK18-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
20104 // CHECK18-NEXT:    store double [[ADD5]], double* [[A]], align 8, !llvm.access.group !30
20105 // CHECK18-NEXT:    [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
20106 // CHECK18-NEXT:    [[TMP13:%.*]] = load double, double* [[A6]], align 8, !llvm.access.group !30
20107 // CHECK18-NEXT:    [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00
20108 // CHECK18-NEXT:    store double [[INC]], double* [[A6]], align 8, !llvm.access.group !30
20109 // CHECK18-NEXT:    [[CONV7:%.*]] = fptosi double [[INC]] to i16
20110 // CHECK18-NEXT:    [[TMP14:%.*]] = mul nsw i64 1, [[TMP2]]
20111 // CHECK18-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP14]]
20112 // CHECK18-NEXT:    [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
20113 // CHECK18-NEXT:    store i16 [[CONV7]], i16* [[ARRAYIDX8]], align 2, !llvm.access.group !30
20114 // CHECK18-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
20115 // CHECK18:       omp.body.continue:
20116 // CHECK18-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
20117 // CHECK18:       omp.inner.for.inc:
20118 // CHECK18-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30
20119 // CHECK18-NEXT:    [[ADD9:%.*]] = add nsw i32 [[TMP15]], 1
20120 // CHECK18-NEXT:    store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30
20121 // CHECK18-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP31:![0-9]+]]
20122 // CHECK18:       omp.inner.for.end:
20123 // CHECK18-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
20124 // CHECK18:       omp.loop.exit:
20125 // CHECK18-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
20126 // CHECK18-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
20127 // CHECK18-NEXT:    [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0
20128 // CHECK18-NEXT:    br i1 [[TMP17]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
20129 // CHECK18:       .omp.final.then:
20130 // CHECK18-NEXT:    store i32 10, i32* [[I]], align 4
20131 // CHECK18-NEXT:    br label [[DOTOMP_FINAL_DONE]]
20132 // CHECK18:       .omp.final.done:
20133 // CHECK18-NEXT:    ret void
20134 //
20135 //
20136 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180
20137 // CHECK18-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
20138 // CHECK18-NEXT:  entry:
20139 // CHECK18-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
20140 // CHECK18-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
20141 // CHECK18-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
20142 // CHECK18-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
20143 // CHECK18-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
20144 // CHECK18-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
20145 // CHECK18-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
20146 // CHECK18-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
20147 // CHECK18-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
20148 // CHECK18-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
20149 // CHECK18-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
20150 // CHECK18-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
20151 // CHECK18-NEXT:    [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
20152 // CHECK18-NEXT:    store i32 [[TMP1]], i32* [[CONV2]], align 4
20153 // CHECK18-NEXT:    [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
20154 // CHECK18-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
20155 // CHECK18-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
20156 // CHECK18-NEXT:    store i16 [[TMP3]], i16* [[CONV3]], align 2
20157 // CHECK18-NEXT:    [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
20158 // CHECK18-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]])
20159 // CHECK18-NEXT:    ret void
20160 //
20161 //
20162 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..6
20163 // CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {
20164 // CHECK18-NEXT:  entry:
20165 // CHECK18-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
20166 // CHECK18-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
20167 // CHECK18-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
20168 // CHECK18-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
20169 // CHECK18-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
20170 // CHECK18-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
20171 // CHECK18-NEXT:    [[TMP:%.*]] = alloca i32, align 4
20172 // CHECK18-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
20173 // CHECK18-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
20174 // CHECK18-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
20175 // CHECK18-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
20176 // CHECK18-NEXT:    [[I:%.*]] = alloca i32, align 4
20177 // CHECK18-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
20178 // CHECK18-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
20179 // CHECK18-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
20180 // CHECK18-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
20181 // CHECK18-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
20182 // CHECK18-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
20183 // CHECK18-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
20184 // CHECK18-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
20185 // CHECK18-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
20186 // CHECK18-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
20187 // CHECK18-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
20188 // CHECK18-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
20189 // CHECK18-NEXT:    [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
20190 // CHECK18-NEXT:    [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
20191 // CHECK18-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
20192 // CHECK18-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
20193 // CHECK18-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9
20194 // CHECK18-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
20195 // CHECK18:       cond.true:
20196 // CHECK18-NEXT:    br label [[COND_END:%.*]]
20197 // CHECK18:       cond.false:
20198 // CHECK18-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
20199 // CHECK18-NEXT:    br label [[COND_END]]
20200 // CHECK18:       cond.end:
20201 // CHECK18-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
20202 // CHECK18-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
20203 // CHECK18-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
20204 // CHECK18-NEXT:    store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
20205 // CHECK18-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
20206 // CHECK18:       omp.inner.for.cond:
20207 // CHECK18-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33
20208 // CHECK18-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !33
20209 // CHECK18-NEXT:    [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
20210 // CHECK18-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
20211 // CHECK18:       omp.inner.for.body:
20212 // CHECK18-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33
20213 // CHECK18-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
20214 // CHECK18-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
20215 // CHECK18-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !33
20216 // CHECK18-NEXT:    [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !33
20217 // CHECK18-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1
20218 // CHECK18-NEXT:    store i32 [[ADD3]], i32* [[CONV]], align 4, !llvm.access.group !33
20219 // CHECK18-NEXT:    [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 2, !llvm.access.group !33
20220 // CHECK18-NEXT:    [[CONV4:%.*]] = sext i16 [[TMP10]] to i32
20221 // CHECK18-NEXT:    [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
20222 // CHECK18-NEXT:    [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
20223 // CHECK18-NEXT:    store i16 [[CONV6]], i16* [[CONV1]], align 2, !llvm.access.group !33
20224 // CHECK18-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
20225 // CHECK18-NEXT:    [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !33
20226 // CHECK18-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1
20227 // CHECK18-NEXT:    store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !33
20228 // CHECK18-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
20229 // CHECK18:       omp.body.continue:
20230 // CHECK18-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
20231 // CHECK18:       omp.inner.for.inc:
20232 // CHECK18-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33
20233 // CHECK18-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP12]], 1
20234 // CHECK18-NEXT:    store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33
20235 // CHECK18-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP34:![0-9]+]]
20236 // CHECK18:       omp.inner.for.end:
20237 // CHECK18-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
20238 // CHECK18:       omp.loop.exit:
20239 // CHECK18-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
20240 // CHECK18-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
20241 // CHECK18-NEXT:    [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
20242 // CHECK18-NEXT:    br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
20243 // CHECK18:       .omp.final.then:
20244 // CHECK18-NEXT:    store i32 10, i32* [[I]], align 4
20245 // CHECK18-NEXT:    br label [[DOTOMP_FINAL_DONE]]
20246 // CHECK18:       .omp.final.done:
20247 // CHECK18-NEXT:    ret void
20248 //
20249 //
20250 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97
20251 // CHECK19-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]], i32 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] {
20252 // CHECK19-NEXT:  entry:
20253 // CHECK19-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
20254 // CHECK19-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
20255 // CHECK19-NEXT:    [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4
20256 // CHECK19-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
20257 // CHECK19-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]])
20258 // CHECK19-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
20259 // CHECK19-NEXT:    store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
20260 // CHECK19-NEXT:    store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4
20261 // CHECK19-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
20262 // CHECK19-NEXT:    [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
20263 // CHECK19-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4
20264 // CHECK19-NEXT:    call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
20265 // CHECK19-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
20266 // CHECK19-NEXT:    [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
20267 // CHECK19-NEXT:    store i16 [[TMP3]], i16* [[CONV3]], align 2
20268 // CHECK19-NEXT:    [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
20269 // CHECK19-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]])
20270 // CHECK19-NEXT:    ret void
20271 //
20272 //
20273 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined.
20274 // CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR1:[0-9]+]] {
20275 // CHECK19-NEXT:  entry:
20276 // CHECK19-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
20277 // CHECK19-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
20278 // CHECK19-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
20279 // CHECK19-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
20280 // CHECK19-NEXT:    [[TMP:%.*]] = alloca i32, align 4
20281 // CHECK19-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
20282 // CHECK19-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
20283 // CHECK19-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
20284 // CHECK19-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
20285 // CHECK19-NEXT:    [[I:%.*]] = alloca i32, align 4
20286 // CHECK19-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
20287 // CHECK19-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
20288 // CHECK19-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
20289 // CHECK19-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
20290 // CHECK19-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
20291 // CHECK19-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
20292 // CHECK19-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
20293 // CHECK19-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
20294 // CHECK19-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
20295 // CHECK19-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
20296 // CHECK19-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
20297 // CHECK19-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
20298 // CHECK19-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
20299 // CHECK19-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
20300 // CHECK19:       cond.true:
20301 // CHECK19-NEXT:    br label [[COND_END:%.*]]
20302 // CHECK19:       cond.false:
20303 // CHECK19-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
20304 // CHECK19-NEXT:    br label [[COND_END]]
20305 // CHECK19:       cond.end:
20306 // CHECK19-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
20307 // CHECK19-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
20308 // CHECK19-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
20309 // CHECK19-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
20310 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
20311 // CHECK19:       omp.inner.for.cond:
20312 // CHECK19-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
20313 // CHECK19-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !12
20314 // CHECK19-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
20315 // CHECK19-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
20316 // CHECK19:       omp.inner.for.body:
20317 // CHECK19-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
20318 // CHECK19-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
20319 // CHECK19-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
20320 // CHECK19-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !12
20321 // CHECK19-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
20322 // CHECK19:       omp.body.continue:
20323 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
20324 // CHECK19:       omp.inner.for.inc:
20325 // CHECK19-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
20326 // CHECK19-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
20327 // CHECK19-NEXT:    store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
20328 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]
20329 // CHECK19:       omp.inner.for.end:
20330 // CHECK19-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
20331 // CHECK19:       omp.loop.exit:
20332 // CHECK19-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
20333 // CHECK19-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
20334 // CHECK19-NEXT:    [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0
20335 // CHECK19-NEXT:    br i1 [[TMP10]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
20336 // CHECK19:       .omp.final.then:
20337 // CHECK19-NEXT:    store i32 10, i32* [[I]], align 4
20338 // CHECK19-NEXT:    br label [[DOTOMP_FINAL_DONE]]
20339 // CHECK19:       .omp.final.done:
20340 // CHECK19-NEXT:    ret void
20341 //
20342 //
20343 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111
20344 // CHECK19-SAME: (i32 noundef [[AA:%.*]]) #[[ATTR0]] {
20345 // CHECK19-NEXT:  entry:
20346 // CHECK19-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
20347 // CHECK19-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
20348 // CHECK19-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
20349 // CHECK19-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
20350 // CHECK19-NEXT:    [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
20351 // CHECK19-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
20352 // CHECK19-NEXT:    store i16 [[TMP0]], i16* [[CONV1]], align 2
20353 // CHECK19-NEXT:    [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
20354 // CHECK19-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]])
20355 // CHECK19-NEXT:    ret void
20356 //
20357 //
20358 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..1
20359 // CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR1]] {
20360 // CHECK19-NEXT:  entry:
20361 // CHECK19-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
20362 // CHECK19-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
20363 // CHECK19-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
20364 // CHECK19-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
20365 // CHECK19-NEXT:    [[TMP:%.*]] = alloca i32, align 4
20366 // CHECK19-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
20367 // CHECK19-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
20368 // CHECK19-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
20369 // CHECK19-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
20370 // CHECK19-NEXT:    [[I:%.*]] = alloca i32, align 4
20371 // CHECK19-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
20372 // CHECK19-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
20373 // CHECK19-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
20374 // CHECK19-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
20375 // CHECK19-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
20376 // CHECK19-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
20377 // CHECK19-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
20378 // CHECK19-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
20379 // CHECK19-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
20380 // CHECK19-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
20381 // CHECK19-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
20382 // CHECK19-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
20383 // CHECK19-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
20384 // CHECK19-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
20385 // CHECK19:       cond.true:
20386 // CHECK19-NEXT:    br label [[COND_END:%.*]]
20387 // CHECK19:       cond.false:
20388 // CHECK19-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
20389 // CHECK19-NEXT:    br label [[COND_END]]
20390 // CHECK19:       cond.end:
20391 // CHECK19-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
20392 // CHECK19-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
20393 // CHECK19-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
20394 // CHECK19-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
20395 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
20396 // CHECK19:       omp.inner.for.cond:
20397 // CHECK19-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
20398 // CHECK19-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !19
20399 // CHECK19-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
20400 // CHECK19-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
20401 // CHECK19:       omp.inner.for.body:
20402 // CHECK19-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
20403 // CHECK19-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
20404 // CHECK19-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
20405 // CHECK19-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !19
20406 // CHECK19-NEXT:    [[TMP8:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !19
20407 // CHECK19-NEXT:    [[CONV2:%.*]] = sext i16 [[TMP8]] to i32
20408 // CHECK19-NEXT:    [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
20409 // CHECK19-NEXT:    [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
20410 // CHECK19-NEXT:    store i16 [[CONV4]], i16* [[CONV]], align 2, !llvm.access.group !19
20411 // CHECK19-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
20412 // CHECK19:       omp.body.continue:
20413 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
20414 // CHECK19:       omp.inner.for.inc:
20415 // CHECK19-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
20416 // CHECK19-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP9]], 1
20417 // CHECK19-NEXT:    store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
20418 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]]
20419 // CHECK19:       omp.inner.for.end:
20420 // CHECK19-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
20421 // CHECK19:       omp.loop.exit:
20422 // CHECK19-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
20423 // CHECK19-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
20424 // CHECK19-NEXT:    [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0
20425 // CHECK19-NEXT:    br i1 [[TMP11]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
20426 // CHECK19:       .omp.final.then:
20427 // CHECK19-NEXT:    store i32 10, i32* [[I]], align 4
20428 // CHECK19-NEXT:    br label [[DOTOMP_FINAL_DONE]]
20429 // CHECK19:       .omp.final.done:
20430 // CHECK19-NEXT:    ret void
20431 //
20432 //
20433 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118
20434 // CHECK19-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] {
20435 // CHECK19-NEXT:  entry:
20436 // CHECK19-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
20437 // CHECK19-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
20438 // CHECK19-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
20439 // CHECK19-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
20440 // CHECK19-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
20441 // CHECK19-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
20442 // CHECK19-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
20443 // CHECK19-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
20444 // CHECK19-NEXT:    store i32 [[TMP0]], i32* [[A_CASTED]], align 4
20445 // CHECK19-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
20446 // CHECK19-NEXT:    [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
20447 // CHECK19-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
20448 // CHECK19-NEXT:    store i16 [[TMP2]], i16* [[CONV1]], align 2
20449 // CHECK19-NEXT:    [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
20450 // CHECK19-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]])
20451 // CHECK19-NEXT:    ret void
20452 //
20453 //
20454 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..2
20455 // CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR1]] {
20456 // CHECK19-NEXT:  entry:
20457 // CHECK19-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
20458 // CHECK19-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
20459 // CHECK19-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
20460 // CHECK19-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
20461 // CHECK19-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
20462 // CHECK19-NEXT:    [[TMP:%.*]] = alloca i32, align 4
20463 // CHECK19-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
20464 // CHECK19-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
20465 // CHECK19-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
20466 // CHECK19-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
20467 // CHECK19-NEXT:    [[I:%.*]] = alloca i32, align 4
20468 // CHECK19-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
20469 // CHECK19-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
20470 // CHECK19-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
20471 // CHECK19-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
20472 // CHECK19-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
20473 // CHECK19-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
20474 // CHECK19-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
20475 // CHECK19-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
20476 // CHECK19-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
20477 // CHECK19-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
20478 // CHECK19-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
20479 // CHECK19-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
20480 // CHECK19-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
20481 // CHECK19-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
20482 // CHECK19-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
20483 // CHECK19:       cond.true:
20484 // CHECK19-NEXT:    br label [[COND_END:%.*]]
20485 // CHECK19:       cond.false:
20486 // CHECK19-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
20487 // CHECK19-NEXT:    br label [[COND_END]]
20488 // CHECK19:       cond.end:
20489 // CHECK19-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
20490 // CHECK19-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
20491 // CHECK19-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
20492 // CHECK19-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
20493 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
20494 // CHECK19:       omp.inner.for.cond:
20495 // CHECK19-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
20496 // CHECK19-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !22
20497 // CHECK19-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
20498 // CHECK19-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
20499 // CHECK19:       omp.inner.for.body:
20500 // CHECK19-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
20501 // CHECK19-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
20502 // CHECK19-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
20503 // CHECK19-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !22
20504 // CHECK19-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !22
20505 // CHECK19-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
20506 // CHECK19-NEXT:    store i32 [[ADD2]], i32* [[A_ADDR]], align 4, !llvm.access.group !22
20507 // CHECK19-NEXT:    [[TMP9:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !22
20508 // CHECK19-NEXT:    [[CONV3:%.*]] = sext i16 [[TMP9]] to i32
20509 // CHECK19-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
20510 // CHECK19-NEXT:    [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
20511 // CHECK19-NEXT:    store i16 [[CONV5]], i16* [[CONV]], align 2, !llvm.access.group !22
20512 // CHECK19-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
20513 // CHECK19:       omp.body.continue:
20514 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
20515 // CHECK19:       omp.inner.for.inc:
20516 // CHECK19-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
20517 // CHECK19-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP10]], 1
20518 // CHECK19-NEXT:    store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
20519 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]]
20520 // CHECK19:       omp.inner.for.end:
20521 // CHECK19-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
20522 // CHECK19:       omp.loop.exit:
20523 // CHECK19-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
20524 // CHECK19-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
20525 // CHECK19-NEXT:    [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
20526 // CHECK19-NEXT:    br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
20527 // CHECK19:       .omp.final.then:
20528 // CHECK19-NEXT:    store i32 10, i32* [[I]], align 4
20529 // CHECK19-NEXT:    br label [[DOTOMP_FINAL_DONE]]
20530 // CHECK19:       .omp.final.done:
20531 // CHECK19-NEXT:    ret void
20532 //
20533 //
20534 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142
20535 // CHECK19-SAME: (i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] {
20536 // CHECK19-NEXT:  entry:
20537 // CHECK19-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
20538 // CHECK19-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
20539 // CHECK19-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
20540 // CHECK19-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 4
20541 // CHECK19-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
20542 // CHECK19-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
20543 // CHECK19-NEXT:    [[VLA_ADDR4:%.*]] = alloca i32, align 4
20544 // CHECK19-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 4
20545 // CHECK19-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
20546 // CHECK19-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
20547 // CHECK19-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
20548 // CHECK19-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
20549 // CHECK19-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
20550 // CHECK19-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 4
20551 // CHECK19-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
20552 // CHECK19-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
20553 // CHECK19-NEXT:    store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
20554 // CHECK19-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 4
20555 // CHECK19-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
20556 // CHECK19-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
20557 // CHECK19-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
20558 // CHECK19-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
20559 // CHECK19-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
20560 // CHECK19-NEXT:    [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
20561 // CHECK19-NEXT:    [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
20562 // CHECK19-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
20563 // CHECK19-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
20564 // CHECK19-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
20565 // CHECK19-NEXT:    store i32 [[TMP8]], i32* [[A_CASTED]], align 4
20566 // CHECK19-NEXT:    [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4
20567 // CHECK19-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]])
20568 // CHECK19-NEXT:    ret void
20569 //
20570 //
20571 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..3
20572 // CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR1]] {
20573 // CHECK19-NEXT:  entry:
20574 // CHECK19-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
20575 // CHECK19-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
20576 // CHECK19-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
20577 // CHECK19-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
20578 // CHECK19-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
20579 // CHECK19-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 4
20580 // CHECK19-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
20581 // CHECK19-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
20582 // CHECK19-NEXT:    [[VLA_ADDR4:%.*]] = alloca i32, align 4
20583 // CHECK19-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 4
20584 // CHECK19-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
20585 // CHECK19-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
20586 // CHECK19-NEXT:    [[TMP:%.*]] = alloca i32, align 4
20587 // CHECK19-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
20588 // CHECK19-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
20589 // CHECK19-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
20590 // CHECK19-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
20591 // CHECK19-NEXT:    [[I:%.*]] = alloca i32, align 4
20592 // CHECK19-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
20593 // CHECK19-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
20594 // CHECK19-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
20595 // CHECK19-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
20596 // CHECK19-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
20597 // CHECK19-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 4
20598 // CHECK19-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
20599 // CHECK19-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
20600 // CHECK19-NEXT:    store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
20601 // CHECK19-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 4
20602 // CHECK19-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
20603 // CHECK19-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
20604 // CHECK19-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
20605 // CHECK19-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
20606 // CHECK19-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
20607 // CHECK19-NEXT:    [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
20608 // CHECK19-NEXT:    [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
20609 // CHECK19-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
20610 // CHECK19-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
20611 // CHECK19-NEXT:    [[ARRAYDECAY:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 0
20612 // CHECK19-NEXT:    call void @llvm.assume(i1 true) [ "align"(float* [[ARRAYDECAY]], i32 16) ]
20613 // CHECK19-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
20614 // CHECK19-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
20615 // CHECK19-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
20616 // CHECK19-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
20617 // CHECK19-NEXT:    [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
20618 // CHECK19-NEXT:    [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4
20619 // CHECK19-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
20620 // CHECK19-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
20621 // CHECK19-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP10]], 9
20622 // CHECK19-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
20623 // CHECK19:       cond.true:
20624 // CHECK19-NEXT:    br label [[COND_END:%.*]]
20625 // CHECK19:       cond.false:
20626 // CHECK19-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
20627 // CHECK19-NEXT:    br label [[COND_END]]
20628 // CHECK19:       cond.end:
20629 // CHECK19-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ]
20630 // CHECK19-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
20631 // CHECK19-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
20632 // CHECK19-NEXT:    store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4
20633 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
20634 // CHECK19:       omp.inner.for.cond:
20635 // CHECK19-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25
20636 // CHECK19-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !25
20637 // CHECK19-NEXT:    [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
20638 // CHECK19-NEXT:    br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
20639 // CHECK19:       omp.inner.for.body:
20640 // CHECK19-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25
20641 // CHECK19-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1
20642 // CHECK19-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
20643 // CHECK19-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !25
20644 // CHECK19-NEXT:    [[TMP16:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !25
20645 // CHECK19-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP16]], 1
20646 // CHECK19-NEXT:    store i32 [[ADD6]], i32* [[A_ADDR]], align 4, !llvm.access.group !25
20647 // CHECK19-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2
20648 // CHECK19-NEXT:    [[TMP17:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !25
20649 // CHECK19-NEXT:    [[CONV:%.*]] = fpext float [[TMP17]] to double
20650 // CHECK19-NEXT:    [[ADD7:%.*]] = fadd double [[CONV]], 1.000000e+00
20651 // CHECK19-NEXT:    [[CONV8:%.*]] = fptrunc double [[ADD7]] to float
20652 // CHECK19-NEXT:    store float [[CONV8]], float* [[ARRAYIDX]], align 4, !llvm.access.group !25
20653 // CHECK19-NEXT:    [[ARRAYIDX9:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3
20654 // CHECK19-NEXT:    [[TMP18:%.*]] = load float, float* [[ARRAYIDX9]], align 4, !llvm.access.group !25
20655 // CHECK19-NEXT:    [[CONV10:%.*]] = fpext float [[TMP18]] to double
20656 // CHECK19-NEXT:    [[ADD11:%.*]] = fadd double [[CONV10]], 1.000000e+00
20657 // CHECK19-NEXT:    [[CONV12:%.*]] = fptrunc double [[ADD11]] to float
20658 // CHECK19-NEXT:    store float [[CONV12]], float* [[ARRAYIDX9]], align 4, !llvm.access.group !25
20659 // CHECK19-NEXT:    [[ARRAYIDX13:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1
20660 // CHECK19-NEXT:    [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX13]], i32 0, i32 2
20661 // CHECK19-NEXT:    [[TMP19:%.*]] = load double, double* [[ARRAYIDX14]], align 8, !llvm.access.group !25
20662 // CHECK19-NEXT:    [[ADD15:%.*]] = fadd double [[TMP19]], 1.000000e+00
20663 // CHECK19-NEXT:    store double [[ADD15]], double* [[ARRAYIDX14]], align 8, !llvm.access.group !25
20664 // CHECK19-NEXT:    [[TMP20:%.*]] = mul nsw i32 1, [[TMP5]]
20665 // CHECK19-NEXT:    [[ARRAYIDX16:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP20]]
20666 // CHECK19-NEXT:    [[ARRAYIDX17:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX16]], i32 3
20667 // CHECK19-NEXT:    [[TMP21:%.*]] = load double, double* [[ARRAYIDX17]], align 8, !llvm.access.group !25
20668 // CHECK19-NEXT:    [[ADD18:%.*]] = fadd double [[TMP21]], 1.000000e+00
20669 // CHECK19-NEXT:    store double [[ADD18]], double* [[ARRAYIDX17]], align 8, !llvm.access.group !25
20670 // CHECK19-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0
20671 // CHECK19-NEXT:    [[TMP22:%.*]] = load i64, i64* [[X]], align 4, !llvm.access.group !25
20672 // CHECK19-NEXT:    [[ADD19:%.*]] = add nsw i64 [[TMP22]], 1
20673 // CHECK19-NEXT:    store i64 [[ADD19]], i64* [[X]], align 4, !llvm.access.group !25
20674 // CHECK19-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1
20675 // CHECK19-NEXT:    [[TMP23:%.*]] = load i8, i8* [[Y]], align 4, !llvm.access.group !25
20676 // CHECK19-NEXT:    [[CONV20:%.*]] = sext i8 [[TMP23]] to i32
20677 // CHECK19-NEXT:    [[ADD21:%.*]] = add nsw i32 [[CONV20]], 1
20678 // CHECK19-NEXT:    [[CONV22:%.*]] = trunc i32 [[ADD21]] to i8
20679 // CHECK19-NEXT:    store i8 [[CONV22]], i8* [[Y]], align 4, !llvm.access.group !25
20680 // CHECK19-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
20681 // CHECK19:       omp.body.continue:
20682 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
20683 // CHECK19:       omp.inner.for.inc:
20684 // CHECK19-NEXT:    [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25
20685 // CHECK19-NEXT:    [[ADD23:%.*]] = add nsw i32 [[TMP24]], 1
20686 // CHECK19-NEXT:    store i32 [[ADD23]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25
20687 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP26:![0-9]+]]
20688 // CHECK19:       omp.inner.for.end:
20689 // CHECK19-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
20690 // CHECK19:       omp.loop.exit:
20691 // CHECK19-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]])
20692 // CHECK19-NEXT:    [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
20693 // CHECK19-NEXT:    [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
20694 // CHECK19-NEXT:    br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
20695 // CHECK19:       .omp.final.then:
20696 // CHECK19-NEXT:    store i32 10, i32* [[I]], align 4
20697 // CHECK19-NEXT:    br label [[DOTOMP_FINAL_DONE]]
20698 // CHECK19:       .omp.final.done:
20699 // CHECK19-NEXT:    ret void
20700 //
20701 //
20702 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197
20703 // CHECK19-SAME: (i32 noundef [[A:%.*]], i32 noundef [[N:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
20704 // CHECK19-NEXT:  entry:
20705 // CHECK19-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
20706 // CHECK19-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
20707 // CHECK19-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
20708 // CHECK19-NEXT:    [[AAA_ADDR:%.*]] = alloca i32, align 4
20709 // CHECK19-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
20710 // CHECK19-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
20711 // CHECK19-NEXT:    [[N_CASTED:%.*]] = alloca i32, align 4
20712 // CHECK19-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
20713 // CHECK19-NEXT:    [[AAA_CASTED:%.*]] = alloca i32, align 4
20714 // CHECK19-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
20715 // CHECK19-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
20716 // CHECK19-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
20717 // CHECK19-NEXT:    store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
20718 // CHECK19-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
20719 // CHECK19-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
20720 // CHECK19-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
20721 // CHECK19-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
20722 // CHECK19-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
20723 // CHECK19-NEXT:    store i32 [[TMP1]], i32* [[A_CASTED]], align 4
20724 // CHECK19-NEXT:    [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
20725 // CHECK19-NEXT:    [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
20726 // CHECK19-NEXT:    store i32 [[TMP3]], i32* [[N_CASTED]], align 4
20727 // CHECK19-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_CASTED]], align 4
20728 // CHECK19-NEXT:    [[TMP5:%.*]] = load i16, i16* [[CONV]], align 2
20729 // CHECK19-NEXT:    [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
20730 // CHECK19-NEXT:    store i16 [[TMP5]], i16* [[CONV2]], align 2
20731 // CHECK19-NEXT:    [[TMP6:%.*]] = load i32, i32* [[AA_CASTED]], align 4
20732 // CHECK19-NEXT:    [[TMP7:%.*]] = load i8, i8* [[CONV1]], align 1
20733 // CHECK19-NEXT:    [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
20734 // CHECK19-NEXT:    store i8 [[TMP7]], i8* [[CONV3]], align 1
20735 // CHECK19-NEXT:    [[TMP8:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
20736 // CHECK19-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP8]], [10 x i32]* [[TMP0]])
20737 // CHECK19-NEXT:    ret void
20738 //
20739 //
20740 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..4
20741 // CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[N:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {
20742 // CHECK19-NEXT:  entry:
20743 // CHECK19-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
20744 // CHECK19-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
20745 // CHECK19-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
20746 // CHECK19-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
20747 // CHECK19-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
20748 // CHECK19-NEXT:    [[AAA_ADDR:%.*]] = alloca i32, align 4
20749 // CHECK19-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
20750 // CHECK19-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
20751 // CHECK19-NEXT:    [[TMP:%.*]] = alloca i32, align 4
20752 // CHECK19-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
20753 // CHECK19-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
20754 // CHECK19-NEXT:    [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4
20755 // CHECK19-NEXT:    [[I:%.*]] = alloca i32, align 4
20756 // CHECK19-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
20757 // CHECK19-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
20758 // CHECK19-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
20759 // CHECK19-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
20760 // CHECK19-NEXT:    [[I6:%.*]] = alloca i32, align 4
20761 // CHECK19-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
20762 // CHECK19-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
20763 // CHECK19-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
20764 // CHECK19-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
20765 // CHECK19-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
20766 // CHECK19-NEXT:    store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
20767 // CHECK19-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
20768 // CHECK19-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
20769 // CHECK19-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
20770 // CHECK19-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
20771 // CHECK19-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
20772 // CHECK19-NEXT:    store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
20773 // CHECK19-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
20774 // CHECK19-NEXT:    store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4
20775 // CHECK19-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
20776 // CHECK19-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
20777 // CHECK19-NEXT:    [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]]
20778 // CHECK19-NEXT:    [[SUB4:%.*]] = sub i32 [[SUB]], 1
20779 // CHECK19-NEXT:    [[ADD:%.*]] = add i32 [[SUB4]], 1
20780 // CHECK19-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], 1
20781 // CHECK19-NEXT:    [[SUB5:%.*]] = sub i32 [[DIV]], 1
20782 // CHECK19-NEXT:    store i32 [[SUB5]], i32* [[DOTCAPTURE_EXPR_3]], align 4
20783 // CHECK19-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
20784 // CHECK19-NEXT:    store i32 [[TMP5]], i32* [[I]], align 4
20785 // CHECK19-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
20786 // CHECK19-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
20787 // CHECK19-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]]
20788 // CHECK19-NEXT:    br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
20789 // CHECK19:       omp.precond.then:
20790 // CHECK19-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
20791 // CHECK19-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
20792 // CHECK19-NEXT:    store i32 [[TMP8]], i32* [[DOTOMP_UB]], align 4
20793 // CHECK19-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
20794 // CHECK19-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
20795 // CHECK19-NEXT:    [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
20796 // CHECK19-NEXT:    [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
20797 // CHECK19-NEXT:    call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
20798 // CHECK19-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
20799 // CHECK19-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
20800 // CHECK19-NEXT:    [[CMP7:%.*]] = icmp ugt i32 [[TMP11]], [[TMP12]]
20801 // CHECK19-NEXT:    br i1 [[CMP7]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
20802 // CHECK19:       cond.true:
20803 // CHECK19-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
20804 // CHECK19-NEXT:    br label [[COND_END:%.*]]
20805 // CHECK19:       cond.false:
20806 // CHECK19-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
20807 // CHECK19-NEXT:    br label [[COND_END]]
20808 // CHECK19:       cond.end:
20809 // CHECK19-NEXT:    [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ]
20810 // CHECK19-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
20811 // CHECK19-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
20812 // CHECK19-NEXT:    store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4
20813 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
20814 // CHECK19:       omp.inner.for.cond:
20815 // CHECK19-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28
20816 // CHECK19-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !28
20817 // CHECK19-NEXT:    [[ADD8:%.*]] = add i32 [[TMP17]], 1
20818 // CHECK19-NEXT:    [[CMP9:%.*]] = icmp ult i32 [[TMP16]], [[ADD8]]
20819 // CHECK19-NEXT:    br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
20820 // CHECK19:       omp.inner.for.body:
20821 // CHECK19-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group !28
20822 // CHECK19-NEXT:    [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28
20823 // CHECK19-NEXT:    [[MUL:%.*]] = mul i32 [[TMP19]], 1
20824 // CHECK19-NEXT:    [[ADD10:%.*]] = add i32 [[TMP18]], [[MUL]]
20825 // CHECK19-NEXT:    store i32 [[ADD10]], i32* [[I6]], align 4, !llvm.access.group !28
20826 // CHECK19-NEXT:    [[TMP20:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !28
20827 // CHECK19-NEXT:    [[ADD11:%.*]] = add nsw i32 [[TMP20]], 1
20828 // CHECK19-NEXT:    store i32 [[ADD11]], i32* [[A_ADDR]], align 4, !llvm.access.group !28
20829 // CHECK19-NEXT:    [[TMP21:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !28
20830 // CHECK19-NEXT:    [[CONV12:%.*]] = sext i16 [[TMP21]] to i32
20831 // CHECK19-NEXT:    [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1
20832 // CHECK19-NEXT:    [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16
20833 // CHECK19-NEXT:    store i16 [[CONV14]], i16* [[CONV]], align 2, !llvm.access.group !28
20834 // CHECK19-NEXT:    [[TMP22:%.*]] = load i8, i8* [[CONV1]], align 1, !llvm.access.group !28
20835 // CHECK19-NEXT:    [[CONV15:%.*]] = sext i8 [[TMP22]] to i32
20836 // CHECK19-NEXT:    [[ADD16:%.*]] = add nsw i32 [[CONV15]], 1
20837 // CHECK19-NEXT:    [[CONV17:%.*]] = trunc i32 [[ADD16]] to i8
20838 // CHECK19-NEXT:    store i8 [[CONV17]], i8* [[CONV1]], align 1, !llvm.access.group !28
20839 // CHECK19-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
20840 // CHECK19-NEXT:    [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !28
20841 // CHECK19-NEXT:    [[ADD18:%.*]] = add nsw i32 [[TMP23]], 1
20842 // CHECK19-NEXT:    store i32 [[ADD18]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !28
20843 // CHECK19-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
20844 // CHECK19:       omp.body.continue:
20845 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
20846 // CHECK19:       omp.inner.for.inc:
20847 // CHECK19-NEXT:    [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28
20848 // CHECK19-NEXT:    [[ADD19:%.*]] = add i32 [[TMP24]], 1
20849 // CHECK19-NEXT:    store i32 [[ADD19]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28
20850 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP29:![0-9]+]]
20851 // CHECK19:       omp.inner.for.end:
20852 // CHECK19-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
20853 // CHECK19:       omp.loop.exit:
20854 // CHECK19-NEXT:    [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
20855 // CHECK19-NEXT:    [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4
20856 // CHECK19-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]])
20857 // CHECK19-NEXT:    [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
20858 // CHECK19-NEXT:    [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0
20859 // CHECK19-NEXT:    br i1 [[TMP28]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
20860 // CHECK19:       .omp.final.then:
20861 // CHECK19-NEXT:    [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
20862 // CHECK19-NEXT:    [[TMP30:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
20863 // CHECK19-NEXT:    [[TMP31:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
20864 // CHECK19-NEXT:    [[SUB20:%.*]] = sub i32 [[TMP30]], [[TMP31]]
20865 // CHECK19-NEXT:    [[SUB21:%.*]] = sub i32 [[SUB20]], 1
20866 // CHECK19-NEXT:    [[ADD22:%.*]] = add i32 [[SUB21]], 1
20867 // CHECK19-NEXT:    [[DIV23:%.*]] = udiv i32 [[ADD22]], 1
20868 // CHECK19-NEXT:    [[MUL24:%.*]] = mul i32 [[DIV23]], 1
20869 // CHECK19-NEXT:    [[ADD25:%.*]] = add i32 [[TMP29]], [[MUL24]]
20870 // CHECK19-NEXT:    store i32 [[ADD25]], i32* [[I6]], align 4
20871 // CHECK19-NEXT:    br label [[DOTOMP_FINAL_DONE]]
20872 // CHECK19:       .omp.final.done:
20873 // CHECK19-NEXT:    br label [[OMP_PRECOND_END]]
20874 // CHECK19:       omp.precond.end:
20875 // CHECK19-NEXT:    ret void
20876 //
20877 //
20878 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215
20879 // CHECK19-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {
20880 // CHECK19-NEXT:  entry:
20881 // CHECK19-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
20882 // CHECK19-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
20883 // CHECK19-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
20884 // CHECK19-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
20885 // CHECK19-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 4
20886 // CHECK19-NEXT:    [[B_CASTED:%.*]] = alloca i32, align 4
20887 // CHECK19-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
20888 // CHECK19-NEXT:    store i32 [[B]], i32* [[B_ADDR]], align 4
20889 // CHECK19-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
20890 // CHECK19-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
20891 // CHECK19-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 4
20892 // CHECK19-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
20893 // CHECK19-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
20894 // CHECK19-NEXT:    [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
20895 // CHECK19-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
20896 // CHECK19-NEXT:    [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4
20897 // CHECK19-NEXT:    store i32 [[TMP4]], i32* [[B_CASTED]], align 4
20898 // CHECK19-NEXT:    [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4
20899 // CHECK19-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]])
20900 // CHECK19-NEXT:    ret void
20901 //
20902 //
20903 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..5
20904 // CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] {
20905 // CHECK19-NEXT:  entry:
20906 // CHECK19-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
20907 // CHECK19-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
20908 // CHECK19-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
20909 // CHECK19-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
20910 // CHECK19-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
20911 // CHECK19-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
20912 // CHECK19-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 4
20913 // CHECK19-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
20914 // CHECK19-NEXT:    [[TMP:%.*]] = alloca i32, align 4
20915 // CHECK19-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
20916 // CHECK19-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
20917 // CHECK19-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
20918 // CHECK19-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
20919 // CHECK19-NEXT:    [[I:%.*]] = alloca i32, align 4
20920 // CHECK19-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
20921 // CHECK19-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
20922 // CHECK19-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
20923 // CHECK19-NEXT:    store i32 [[B]], i32* [[B_ADDR]], align 4
20924 // CHECK19-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
20925 // CHECK19-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
20926 // CHECK19-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 4
20927 // CHECK19-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
20928 // CHECK19-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
20929 // CHECK19-NEXT:    [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
20930 // CHECK19-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
20931 // CHECK19-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
20932 // CHECK19-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
20933 // CHECK19-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
20934 // CHECK19-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
20935 // CHECK19-NEXT:    [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
20936 // CHECK19-NEXT:    [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
20937 // CHECK19-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
20938 // CHECK19-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
20939 // CHECK19-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 9
20940 // CHECK19-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
20941 // CHECK19:       cond.true:
20942 // CHECK19-NEXT:    br label [[COND_END:%.*]]
20943 // CHECK19:       cond.false:
20944 // CHECK19-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
20945 // CHECK19-NEXT:    br label [[COND_END]]
20946 // CHECK19:       cond.end:
20947 // CHECK19-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
20948 // CHECK19-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
20949 // CHECK19-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
20950 // CHECK19-NEXT:    store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
20951 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
20952 // CHECK19:       omp.inner.for.cond:
20953 // CHECK19-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !31
20954 // CHECK19-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !31
20955 // CHECK19-NEXT:    [[CMP3:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
20956 // CHECK19-NEXT:    br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
20957 // CHECK19:       omp.inner.for.body:
20958 // CHECK19-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !31
20959 // CHECK19-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
20960 // CHECK19-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
20961 // CHECK19-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !31
20962 // CHECK19-NEXT:    [[TMP12:%.*]] = load i32, i32* [[B_ADDR]], align 4, !llvm.access.group !31
20963 // CHECK19-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP12]] to double
20964 // CHECK19-NEXT:    [[ADD4:%.*]] = fadd double [[CONV]], 1.500000e+00
20965 // CHECK19-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
20966 // CHECK19-NEXT:    store double [[ADD4]], double* [[A]], align 4, !llvm.access.group !31
20967 // CHECK19-NEXT:    [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
20968 // CHECK19-NEXT:    [[TMP13:%.*]] = load double, double* [[A5]], align 4, !llvm.access.group !31
20969 // CHECK19-NEXT:    [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00
20970 // CHECK19-NEXT:    store double [[INC]], double* [[A5]], align 4, !llvm.access.group !31
20971 // CHECK19-NEXT:    [[CONV6:%.*]] = fptosi double [[INC]] to i16
20972 // CHECK19-NEXT:    [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]]
20973 // CHECK19-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP14]]
20974 // CHECK19-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
20975 // CHECK19-NEXT:    store i16 [[CONV6]], i16* [[ARRAYIDX7]], align 2, !llvm.access.group !31
20976 // CHECK19-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
20977 // CHECK19:       omp.body.continue:
20978 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
20979 // CHECK19:       omp.inner.for.inc:
20980 // CHECK19-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !31
20981 // CHECK19-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP15]], 1
20982 // CHECK19-NEXT:    store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !31
20983 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP32:![0-9]+]]
20984 // CHECK19:       omp.inner.for.end:
20985 // CHECK19-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
20986 // CHECK19:       omp.loop.exit:
20987 // CHECK19-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
20988 // CHECK19-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
20989 // CHECK19-NEXT:    [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0
20990 // CHECK19-NEXT:    br i1 [[TMP17]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
20991 // CHECK19:       .omp.final.then:
20992 // CHECK19-NEXT:    store i32 10, i32* [[I]], align 4
20993 // CHECK19-NEXT:    br label [[DOTOMP_FINAL_DONE]]
20994 // CHECK19:       .omp.final.done:
20995 // CHECK19-NEXT:    ret void
20996 //
20997 //
20998 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180
20999 // CHECK19-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
21000 // CHECK19-NEXT:  entry:
21001 // CHECK19-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
21002 // CHECK19-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
21003 // CHECK19-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
21004 // CHECK19-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
21005 // CHECK19-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
21006 // CHECK19-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
21007 // CHECK19-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
21008 // CHECK19-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
21009 // CHECK19-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
21010 // CHECK19-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
21011 // CHECK19-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
21012 // CHECK19-NEXT:    store i32 [[TMP1]], i32* [[A_CASTED]], align 4
21013 // CHECK19-NEXT:    [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
21014 // CHECK19-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
21015 // CHECK19-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
21016 // CHECK19-NEXT:    store i16 [[TMP3]], i16* [[CONV1]], align 2
21017 // CHECK19-NEXT:    [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
21018 // CHECK19-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]])
21019 // CHECK19-NEXT:    ret void
21020 //
21021 //
21022 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..6
21023 // CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {
21024 // CHECK19-NEXT:  entry:
21025 // CHECK19-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
21026 // CHECK19-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
21027 // CHECK19-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
21028 // CHECK19-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
21029 // CHECK19-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
21030 // CHECK19-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
21031 // CHECK19-NEXT:    [[TMP:%.*]] = alloca i32, align 4
21032 // CHECK19-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
21033 // CHECK19-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
21034 // CHECK19-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
21035 // CHECK19-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
21036 // CHECK19-NEXT:    [[I:%.*]] = alloca i32, align 4
21037 // CHECK19-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
21038 // CHECK19-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
21039 // CHECK19-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
21040 // CHECK19-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
21041 // CHECK19-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
21042 // CHECK19-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
21043 // CHECK19-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
21044 // CHECK19-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
21045 // CHECK19-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
21046 // CHECK19-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
21047 // CHECK19-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
21048 // CHECK19-NEXT:    [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
21049 // CHECK19-NEXT:    [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
21050 // CHECK19-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
21051 // CHECK19-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
21052 // CHECK19-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9
21053 // CHECK19-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
21054 // CHECK19:       cond.true:
21055 // CHECK19-NEXT:    br label [[COND_END:%.*]]
21056 // CHECK19:       cond.false:
21057 // CHECK19-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
21058 // CHECK19-NEXT:    br label [[COND_END]]
21059 // CHECK19:       cond.end:
21060 // CHECK19-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
21061 // CHECK19-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
21062 // CHECK19-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
21063 // CHECK19-NEXT:    store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
21064 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
21065 // CHECK19:       omp.inner.for.cond:
21066 // CHECK19-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !34
21067 // CHECK19-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !34
21068 // CHECK19-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
21069 // CHECK19-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
21070 // CHECK19:       omp.inner.for.body:
21071 // CHECK19-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !34
21072 // CHECK19-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
21073 // CHECK19-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
21074 // CHECK19-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !34
21075 // CHECK19-NEXT:    [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !34
21076 // CHECK19-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
21077 // CHECK19-NEXT:    store i32 [[ADD2]], i32* [[A_ADDR]], align 4, !llvm.access.group !34
21078 // CHECK19-NEXT:    [[TMP10:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !34
21079 // CHECK19-NEXT:    [[CONV3:%.*]] = sext i16 [[TMP10]] to i32
21080 // CHECK19-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
21081 // CHECK19-NEXT:    [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
21082 // CHECK19-NEXT:    store i16 [[CONV5]], i16* [[CONV]], align 2, !llvm.access.group !34
21083 // CHECK19-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
21084 // CHECK19-NEXT:    [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !34
21085 // CHECK19-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1
21086 // CHECK19-NEXT:    store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !34
21087 // CHECK19-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
21088 // CHECK19:       omp.body.continue:
21089 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
21090 // CHECK19:       omp.inner.for.inc:
21091 // CHECK19-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !34
21092 // CHECK19-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP12]], 1
21093 // CHECK19-NEXT:    store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !34
21094 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP35:![0-9]+]]
21095 // CHECK19:       omp.inner.for.end:
21096 // CHECK19-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
21097 // CHECK19:       omp.loop.exit:
21098 // CHECK19-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
21099 // CHECK19-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
21100 // CHECK19-NEXT:    [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
21101 // CHECK19-NEXT:    br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
21102 // CHECK19:       .omp.final.then:
21103 // CHECK19-NEXT:    store i32 10, i32* [[I]], align 4
21104 // CHECK19-NEXT:    br label [[DOTOMP_FINAL_DONE]]
21105 // CHECK19:       .omp.final.done:
21106 // CHECK19-NEXT:    ret void
21107 //
21108 //
21109 // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97
21110 // CHECK20-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]], i32 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] {
21111 // CHECK20-NEXT:  entry:
21112 // CHECK20-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
21113 // CHECK20-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
21114 // CHECK20-NEXT:    [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4
21115 // CHECK20-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
21116 // CHECK20-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]])
21117 // CHECK20-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
21118 // CHECK20-NEXT:    store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
21119 // CHECK20-NEXT:    store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4
21120 // CHECK20-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
21121 // CHECK20-NEXT:    [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
21122 // CHECK20-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4
21123 // CHECK20-NEXT:    call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
21124 // CHECK20-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
21125 // CHECK20-NEXT:    [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
21126 // CHECK20-NEXT:    store i16 [[TMP3]], i16* [[CONV3]], align 2
21127 // CHECK20-NEXT:    [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
21128 // CHECK20-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]])
21129 // CHECK20-NEXT:    ret void
21130 //
21131 //
21132 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined.
21133 // CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR1:[0-9]+]] {
21134 // CHECK20-NEXT:  entry:
21135 // CHECK20-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
21136 // CHECK20-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
21137 // CHECK20-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
21138 // CHECK20-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
21139 // CHECK20-NEXT:    [[TMP:%.*]] = alloca i32, align 4
21140 // CHECK20-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
21141 // CHECK20-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
21142 // CHECK20-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
21143 // CHECK20-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
21144 // CHECK20-NEXT:    [[I:%.*]] = alloca i32, align 4
21145 // CHECK20-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
21146 // CHECK20-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
21147 // CHECK20-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
21148 // CHECK20-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
21149 // CHECK20-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
21150 // CHECK20-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
21151 // CHECK20-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
21152 // CHECK20-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
21153 // CHECK20-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
21154 // CHECK20-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
21155 // CHECK20-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
21156 // CHECK20-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
21157 // CHECK20-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
21158 // CHECK20-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
21159 // CHECK20:       cond.true:
21160 // CHECK20-NEXT:    br label [[COND_END:%.*]]
21161 // CHECK20:       cond.false:
21162 // CHECK20-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
21163 // CHECK20-NEXT:    br label [[COND_END]]
21164 // CHECK20:       cond.end:
21165 // CHECK20-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
21166 // CHECK20-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
21167 // CHECK20-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
21168 // CHECK20-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
21169 // CHECK20-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
21170 // CHECK20:       omp.inner.for.cond:
21171 // CHECK20-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
21172 // CHECK20-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !12
21173 // CHECK20-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
21174 // CHECK20-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
21175 // CHECK20:       omp.inner.for.body:
21176 // CHECK20-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
21177 // CHECK20-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
21178 // CHECK20-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
21179 // CHECK20-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !12
21180 // CHECK20-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
21181 // CHECK20:       omp.body.continue:
21182 // CHECK20-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
21183 // CHECK20:       omp.inner.for.inc:
21184 // CHECK20-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
21185 // CHECK20-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
21186 // CHECK20-NEXT:    store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
21187 // CHECK20-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]
21188 // CHECK20:       omp.inner.for.end:
21189 // CHECK20-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
21190 // CHECK20:       omp.loop.exit:
21191 // CHECK20-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
21192 // CHECK20-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
21193 // CHECK20-NEXT:    [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0
21194 // CHECK20-NEXT:    br i1 [[TMP10]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
21195 // CHECK20:       .omp.final.then:
21196 // CHECK20-NEXT:    store i32 10, i32* [[I]], align 4
21197 // CHECK20-NEXT:    br label [[DOTOMP_FINAL_DONE]]
21198 // CHECK20:       .omp.final.done:
21199 // CHECK20-NEXT:    ret void
21200 //
21201 //
21202 // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111
21203 // CHECK20-SAME: (i32 noundef [[AA:%.*]]) #[[ATTR0]] {
21204 // CHECK20-NEXT:  entry:
21205 // CHECK20-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
21206 // CHECK20-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
21207 // CHECK20-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
21208 // CHECK20-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
21209 // CHECK20-NEXT:    [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
21210 // CHECK20-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
21211 // CHECK20-NEXT:    store i16 [[TMP0]], i16* [[CONV1]], align 2
21212 // CHECK20-NEXT:    [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
21213 // CHECK20-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]])
21214 // CHECK20-NEXT:    ret void
21215 //
21216 //
21217 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..1
21218 // CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR1]] {
21219 // CHECK20-NEXT:  entry:
21220 // CHECK20-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
21221 // CHECK20-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
21222 // CHECK20-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
21223 // CHECK20-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
21224 // CHECK20-NEXT:    [[TMP:%.*]] = alloca i32, align 4
21225 // CHECK20-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
21226 // CHECK20-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
21227 // CHECK20-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
21228 // CHECK20-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
21229 // CHECK20-NEXT:    [[I:%.*]] = alloca i32, align 4
21230 // CHECK20-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
21231 // CHECK20-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
21232 // CHECK20-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
21233 // CHECK20-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
21234 // CHECK20-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
21235 // CHECK20-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
21236 // CHECK20-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
21237 // CHECK20-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
21238 // CHECK20-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
21239 // CHECK20-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
21240 // CHECK20-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
21241 // CHECK20-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
21242 // CHECK20-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
21243 // CHECK20-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
21244 // CHECK20:       cond.true:
21245 // CHECK20-NEXT:    br label [[COND_END:%.*]]
21246 // CHECK20:       cond.false:
21247 // CHECK20-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
21248 // CHECK20-NEXT:    br label [[COND_END]]
21249 // CHECK20:       cond.end:
21250 // CHECK20-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
21251 // CHECK20-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
21252 // CHECK20-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
21253 // CHECK20-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
21254 // CHECK20-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
21255 // CHECK20:       omp.inner.for.cond:
21256 // CHECK20-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
21257 // CHECK20-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !19
21258 // CHECK20-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
21259 // CHECK20-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
21260 // CHECK20:       omp.inner.for.body:
21261 // CHECK20-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
21262 // CHECK20-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
21263 // CHECK20-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
21264 // CHECK20-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !19
21265 // CHECK20-NEXT:    [[TMP8:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !19
21266 // CHECK20-NEXT:    [[CONV2:%.*]] = sext i16 [[TMP8]] to i32
21267 // CHECK20-NEXT:    [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
21268 // CHECK20-NEXT:    [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
21269 // CHECK20-NEXT:    store i16 [[CONV4]], i16* [[CONV]], align 2, !llvm.access.group !19
21270 // CHECK20-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
21271 // CHECK20:       omp.body.continue:
21272 // CHECK20-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
21273 // CHECK20:       omp.inner.for.inc:
21274 // CHECK20-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
21275 // CHECK20-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP9]], 1
21276 // CHECK20-NEXT:    store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
21277 // CHECK20-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]]
21278 // CHECK20:       omp.inner.for.end:
21279 // CHECK20-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
21280 // CHECK20:       omp.loop.exit:
21281 // CHECK20-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
21282 // CHECK20-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
21283 // CHECK20-NEXT:    [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0
21284 // CHECK20-NEXT:    br i1 [[TMP11]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
21285 // CHECK20:       .omp.final.then:
21286 // CHECK20-NEXT:    store i32 10, i32* [[I]], align 4
21287 // CHECK20-NEXT:    br label [[DOTOMP_FINAL_DONE]]
21288 // CHECK20:       .omp.final.done:
21289 // CHECK20-NEXT:    ret void
21290 //
21291 //
21292 // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118
21293 // CHECK20-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] {
21294 // CHECK20-NEXT:  entry:
21295 // CHECK20-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
21296 // CHECK20-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
21297 // CHECK20-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
21298 // CHECK20-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
21299 // CHECK20-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
21300 // CHECK20-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
21301 // CHECK20-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
21302 // CHECK20-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
21303 // CHECK20-NEXT:    store i32 [[TMP0]], i32* [[A_CASTED]], align 4
21304 // CHECK20-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
21305 // CHECK20-NEXT:    [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
21306 // CHECK20-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
21307 // CHECK20-NEXT:    store i16 [[TMP2]], i16* [[CONV1]], align 2
21308 // CHECK20-NEXT:    [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
21309 // CHECK20-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]])
21310 // CHECK20-NEXT:    ret void
21311 //
21312 //
21313 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..2
21314 // CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR1]] {
21315 // CHECK20-NEXT:  entry:
21316 // CHECK20-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
21317 // CHECK20-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
21318 // CHECK20-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
21319 // CHECK20-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
21320 // CHECK20-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
21321 // CHECK20-NEXT:    [[TMP:%.*]] = alloca i32, align 4
21322 // CHECK20-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
21323 // CHECK20-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
21324 // CHECK20-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
21325 // CHECK20-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
21326 // CHECK20-NEXT:    [[I:%.*]] = alloca i32, align 4
21327 // CHECK20-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
21328 // CHECK20-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
21329 // CHECK20-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
21330 // CHECK20-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
21331 // CHECK20-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
21332 // CHECK20-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
21333 // CHECK20-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
21334 // CHECK20-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
21335 // CHECK20-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
21336 // CHECK20-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
21337 // CHECK20-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
21338 // CHECK20-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
21339 // CHECK20-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
21340 // CHECK20-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
21341 // CHECK20-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
21342 // CHECK20:       cond.true:
21343 // CHECK20-NEXT:    br label [[COND_END:%.*]]
21344 // CHECK20:       cond.false:
21345 // CHECK20-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
21346 // CHECK20-NEXT:    br label [[COND_END]]
21347 // CHECK20:       cond.end:
21348 // CHECK20-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
21349 // CHECK20-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
21350 // CHECK20-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
21351 // CHECK20-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
21352 // CHECK20-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
21353 // CHECK20:       omp.inner.for.cond:
21354 // CHECK20-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
21355 // CHECK20-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !22
21356 // CHECK20-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
21357 // CHECK20-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
21358 // CHECK20:       omp.inner.for.body:
21359 // CHECK20-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
21360 // CHECK20-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
21361 // CHECK20-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
21362 // CHECK20-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !22
21363 // CHECK20-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !22
21364 // CHECK20-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
21365 // CHECK20-NEXT:    store i32 [[ADD2]], i32* [[A_ADDR]], align 4, !llvm.access.group !22
21366 // CHECK20-NEXT:    [[TMP9:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !22
21367 // CHECK20-NEXT:    [[CONV3:%.*]] = sext i16 [[TMP9]] to i32
21368 // CHECK20-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
21369 // CHECK20-NEXT:    [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
21370 // CHECK20-NEXT:    store i16 [[CONV5]], i16* [[CONV]], align 2, !llvm.access.group !22
21371 // CHECK20-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
21372 // CHECK20:       omp.body.continue:
21373 // CHECK20-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
21374 // CHECK20:       omp.inner.for.inc:
21375 // CHECK20-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
21376 // CHECK20-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP10]], 1
21377 // CHECK20-NEXT:    store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
21378 // CHECK20-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]]
21379 // CHECK20:       omp.inner.for.end:
21380 // CHECK20-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
21381 // CHECK20:       omp.loop.exit:
21382 // CHECK20-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
21383 // CHECK20-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
21384 // CHECK20-NEXT:    [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
21385 // CHECK20-NEXT:    br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
21386 // CHECK20:       .omp.final.then:
21387 // CHECK20-NEXT:    store i32 10, i32* [[I]], align 4
21388 // CHECK20-NEXT:    br label [[DOTOMP_FINAL_DONE]]
21389 // CHECK20:       .omp.final.done:
21390 // CHECK20-NEXT:    ret void
21391 //
21392 //
21393 // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142
21394 // CHECK20-SAME: (i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] {
21395 // CHECK20-NEXT:  entry:
21396 // CHECK20-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
21397 // CHECK20-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
21398 // CHECK20-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
21399 // CHECK20-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 4
21400 // CHECK20-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
21401 // CHECK20-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
21402 // CHECK20-NEXT:    [[VLA_ADDR4:%.*]] = alloca i32, align 4
21403 // CHECK20-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 4
21404 // CHECK20-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
21405 // CHECK20-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
21406 // CHECK20-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
21407 // CHECK20-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
21408 // CHECK20-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
21409 // CHECK20-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 4
21410 // CHECK20-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
21411 // CHECK20-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
21412 // CHECK20-NEXT:    store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
21413 // CHECK20-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 4
21414 // CHECK20-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
21415 // CHECK20-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
21416 // CHECK20-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
21417 // CHECK20-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
21418 // CHECK20-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
21419 // CHECK20-NEXT:    [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
21420 // CHECK20-NEXT:    [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
21421 // CHECK20-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
21422 // CHECK20-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
21423 // CHECK20-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
21424 // CHECK20-NEXT:    store i32 [[TMP8]], i32* [[A_CASTED]], align 4
21425 // CHECK20-NEXT:    [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4
21426 // CHECK20-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]])
21427 // CHECK20-NEXT:    ret void
21428 //
21429 //
21430 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..3
21431 // CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR1]] {
21432 // CHECK20-NEXT:  entry:
21433 // CHECK20-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
21434 // CHECK20-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
21435 // CHECK20-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
21436 // CHECK20-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
21437 // CHECK20-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
21438 // CHECK20-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 4
21439 // CHECK20-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
21440 // CHECK20-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
21441 // CHECK20-NEXT:    [[VLA_ADDR4:%.*]] = alloca i32, align 4
21442 // CHECK20-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 4
21443 // CHECK20-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
21444 // CHECK20-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
21445 // CHECK20-NEXT:    [[TMP:%.*]] = alloca i32, align 4
21446 // CHECK20-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
21447 // CHECK20-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
21448 // CHECK20-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
21449 // CHECK20-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
21450 // CHECK20-NEXT:    [[I:%.*]] = alloca i32, align 4
21451 // CHECK20-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
21452 // CHECK20-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
21453 // CHECK20-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
21454 // CHECK20-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
21455 // CHECK20-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
21456 // CHECK20-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 4
21457 // CHECK20-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
21458 // CHECK20-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
21459 // CHECK20-NEXT:    store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
21460 // CHECK20-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 4
21461 // CHECK20-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
21462 // CHECK20-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
21463 // CHECK20-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
21464 // CHECK20-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
21465 // CHECK20-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
21466 // CHECK20-NEXT:    [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
21467 // CHECK20-NEXT:    [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
21468 // CHECK20-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
21469 // CHECK20-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
21470 // CHECK20-NEXT:    [[ARRAYDECAY:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 0
21471 // CHECK20-NEXT:    call void @llvm.assume(i1 true) [ "align"(float* [[ARRAYDECAY]], i32 16) ]
21472 // CHECK20-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
21473 // CHECK20-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
21474 // CHECK20-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
21475 // CHECK20-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
21476 // CHECK20-NEXT:    [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
21477 // CHECK20-NEXT:    [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4
21478 // CHECK20-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
21479 // CHECK20-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
21480 // CHECK20-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP10]], 9
21481 // CHECK20-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
21482 // CHECK20:       cond.true:
21483 // CHECK20-NEXT:    br label [[COND_END:%.*]]
21484 // CHECK20:       cond.false:
21485 // CHECK20-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
21486 // CHECK20-NEXT:    br label [[COND_END]]
21487 // CHECK20:       cond.end:
21488 // CHECK20-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ]
21489 // CHECK20-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
21490 // CHECK20-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
21491 // CHECK20-NEXT:    store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4
21492 // CHECK20-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
21493 // CHECK20:       omp.inner.for.cond:
21494 // CHECK20-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25
21495 // CHECK20-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !25
21496 // CHECK20-NEXT:    [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
21497 // CHECK20-NEXT:    br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
21498 // CHECK20:       omp.inner.for.body:
21499 // CHECK20-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25
21500 // CHECK20-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1
21501 // CHECK20-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
21502 // CHECK20-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !25
21503 // CHECK20-NEXT:    [[TMP16:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !25
21504 // CHECK20-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP16]], 1
21505 // CHECK20-NEXT:    store i32 [[ADD6]], i32* [[A_ADDR]], align 4, !llvm.access.group !25
21506 // CHECK20-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2
21507 // CHECK20-NEXT:    [[TMP17:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !25
21508 // CHECK20-NEXT:    [[CONV:%.*]] = fpext float [[TMP17]] to double
21509 // CHECK20-NEXT:    [[ADD7:%.*]] = fadd double [[CONV]], 1.000000e+00
21510 // CHECK20-NEXT:    [[CONV8:%.*]] = fptrunc double [[ADD7]] to float
21511 // CHECK20-NEXT:    store float [[CONV8]], float* [[ARRAYIDX]], align 4, !llvm.access.group !25
21512 // CHECK20-NEXT:    [[ARRAYIDX9:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3
21513 // CHECK20-NEXT:    [[TMP18:%.*]] = load float, float* [[ARRAYIDX9]], align 4, !llvm.access.group !25
21514 // CHECK20-NEXT:    [[CONV10:%.*]] = fpext float [[TMP18]] to double
21515 // CHECK20-NEXT:    [[ADD11:%.*]] = fadd double [[CONV10]], 1.000000e+00
21516 // CHECK20-NEXT:    [[CONV12:%.*]] = fptrunc double [[ADD11]] to float
21517 // CHECK20-NEXT:    store float [[CONV12]], float* [[ARRAYIDX9]], align 4, !llvm.access.group !25
21518 // CHECK20-NEXT:    [[ARRAYIDX13:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1
21519 // CHECK20-NEXT:    [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX13]], i32 0, i32 2
21520 // CHECK20-NEXT:    [[TMP19:%.*]] = load double, double* [[ARRAYIDX14]], align 8, !llvm.access.group !25
21521 // CHECK20-NEXT:    [[ADD15:%.*]] = fadd double [[TMP19]], 1.000000e+00
21522 // CHECK20-NEXT:    store double [[ADD15]], double* [[ARRAYIDX14]], align 8, !llvm.access.group !25
21523 // CHECK20-NEXT:    [[TMP20:%.*]] = mul nsw i32 1, [[TMP5]]
21524 // CHECK20-NEXT:    [[ARRAYIDX16:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP20]]
21525 // CHECK20-NEXT:    [[ARRAYIDX17:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX16]], i32 3
21526 // CHECK20-NEXT:    [[TMP21:%.*]] = load double, double* [[ARRAYIDX17]], align 8, !llvm.access.group !25
21527 // CHECK20-NEXT:    [[ADD18:%.*]] = fadd double [[TMP21]], 1.000000e+00
21528 // CHECK20-NEXT:    store double [[ADD18]], double* [[ARRAYIDX17]], align 8, !llvm.access.group !25
21529 // CHECK20-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0
21530 // CHECK20-NEXT:    [[TMP22:%.*]] = load i64, i64* [[X]], align 4, !llvm.access.group !25
21531 // CHECK20-NEXT:    [[ADD19:%.*]] = add nsw i64 [[TMP22]], 1
21532 // CHECK20-NEXT:    store i64 [[ADD19]], i64* [[X]], align 4, !llvm.access.group !25
21533 // CHECK20-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1
21534 // CHECK20-NEXT:    [[TMP23:%.*]] = load i8, i8* [[Y]], align 4, !llvm.access.group !25
21535 // CHECK20-NEXT:    [[CONV20:%.*]] = sext i8 [[TMP23]] to i32
21536 // CHECK20-NEXT:    [[ADD21:%.*]] = add nsw i32 [[CONV20]], 1
21537 // CHECK20-NEXT:    [[CONV22:%.*]] = trunc i32 [[ADD21]] to i8
21538 // CHECK20-NEXT:    store i8 [[CONV22]], i8* [[Y]], align 4, !llvm.access.group !25
21539 // CHECK20-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
21540 // CHECK20:       omp.body.continue:
21541 // CHECK20-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
21542 // CHECK20:       omp.inner.for.inc:
21543 // CHECK20-NEXT:    [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25
21544 // CHECK20-NEXT:    [[ADD23:%.*]] = add nsw i32 [[TMP24]], 1
21545 // CHECK20-NEXT:    store i32 [[ADD23]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25
21546 // CHECK20-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP26:![0-9]+]]
21547 // CHECK20:       omp.inner.for.end:
21548 // CHECK20-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
21549 // CHECK20:       omp.loop.exit:
21550 // CHECK20-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]])
21551 // CHECK20-NEXT:    [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
21552 // CHECK20-NEXT:    [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
21553 // CHECK20-NEXT:    br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
21554 // CHECK20:       .omp.final.then:
21555 // CHECK20-NEXT:    store i32 10, i32* [[I]], align 4
21556 // CHECK20-NEXT:    br label [[DOTOMP_FINAL_DONE]]
21557 // CHECK20:       .omp.final.done:
21558 // CHECK20-NEXT:    ret void
21559 //
21560 //
21561 // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197
21562 // CHECK20-SAME: (i32 noundef [[A:%.*]], i32 noundef [[N:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
21563 // CHECK20-NEXT:  entry:
21564 // CHECK20-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
21565 // CHECK20-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
21566 // CHECK20-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
21567 // CHECK20-NEXT:    [[AAA_ADDR:%.*]] = alloca i32, align 4
21568 // CHECK20-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
21569 // CHECK20-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
21570 // CHECK20-NEXT:    [[N_CASTED:%.*]] = alloca i32, align 4
21571 // CHECK20-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
21572 // CHECK20-NEXT:    [[AAA_CASTED:%.*]] = alloca i32, align 4
21573 // CHECK20-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
21574 // CHECK20-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
21575 // CHECK20-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
21576 // CHECK20-NEXT:    store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
21577 // CHECK20-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
21578 // CHECK20-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
21579 // CHECK20-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
21580 // CHECK20-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
21581 // CHECK20-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
21582 // CHECK20-NEXT:    store i32 [[TMP1]], i32* [[A_CASTED]], align 4
21583 // CHECK20-NEXT:    [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
21584 // CHECK20-NEXT:    [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
21585 // CHECK20-NEXT:    store i32 [[TMP3]], i32* [[N_CASTED]], align 4
21586 // CHECK20-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_CASTED]], align 4
21587 // CHECK20-NEXT:    [[TMP5:%.*]] = load i16, i16* [[CONV]], align 2
21588 // CHECK20-NEXT:    [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
21589 // CHECK20-NEXT:    store i16 [[TMP5]], i16* [[CONV2]], align 2
21590 // CHECK20-NEXT:    [[TMP6:%.*]] = load i32, i32* [[AA_CASTED]], align 4
21591 // CHECK20-NEXT:    [[TMP7:%.*]] = load i8, i8* [[CONV1]], align 1
21592 // CHECK20-NEXT:    [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
21593 // CHECK20-NEXT:    store i8 [[TMP7]], i8* [[CONV3]], align 1
21594 // CHECK20-NEXT:    [[TMP8:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
21595 // CHECK20-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP8]], [10 x i32]* [[TMP0]])
21596 // CHECK20-NEXT:    ret void
21597 //
21598 //
21599 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..4
21600 // CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[N:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {
21601 // CHECK20-NEXT:  entry:
21602 // CHECK20-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
21603 // CHECK20-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
21604 // CHECK20-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
21605 // CHECK20-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
21606 // CHECK20-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
21607 // CHECK20-NEXT:    [[AAA_ADDR:%.*]] = alloca i32, align 4
21608 // CHECK20-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
21609 // CHECK20-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
21610 // CHECK20-NEXT:    [[TMP:%.*]] = alloca i32, align 4
21611 // CHECK20-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
21612 // CHECK20-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
21613 // CHECK20-NEXT:    [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4
21614 // CHECK20-NEXT:    [[I:%.*]] = alloca i32, align 4
21615 // CHECK20-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
21616 // CHECK20-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
21617 // CHECK20-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
21618 // CHECK20-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
21619 // CHECK20-NEXT:    [[I6:%.*]] = alloca i32, align 4
21620 // CHECK20-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
21621 // CHECK20-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
21622 // CHECK20-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
21623 // CHECK20-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
21624 // CHECK20-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
21625 // CHECK20-NEXT:    store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
21626 // CHECK20-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
21627 // CHECK20-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
21628 // CHECK20-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
21629 // CHECK20-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
21630 // CHECK20-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
21631 // CHECK20-NEXT:    store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
21632 // CHECK20-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
21633 // CHECK20-NEXT:    store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4
21634 // CHECK20-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
21635 // CHECK20-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
21636 // CHECK20-NEXT:    [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]]
21637 // CHECK20-NEXT:    [[SUB4:%.*]] = sub i32 [[SUB]], 1
21638 // CHECK20-NEXT:    [[ADD:%.*]] = add i32 [[SUB4]], 1
21639 // CHECK20-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], 1
21640 // CHECK20-NEXT:    [[SUB5:%.*]] = sub i32 [[DIV]], 1
21641 // CHECK20-NEXT:    store i32 [[SUB5]], i32* [[DOTCAPTURE_EXPR_3]], align 4
21642 // CHECK20-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
21643 // CHECK20-NEXT:    store i32 [[TMP5]], i32* [[I]], align 4
21644 // CHECK20-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
21645 // CHECK20-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
21646 // CHECK20-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]]
21647 // CHECK20-NEXT:    br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
21648 // CHECK20:       omp.precond.then:
21649 // CHECK20-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
21650 // CHECK20-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
21651 // CHECK20-NEXT:    store i32 [[TMP8]], i32* [[DOTOMP_UB]], align 4
21652 // CHECK20-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
21653 // CHECK20-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
21654 // CHECK20-NEXT:    [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
21655 // CHECK20-NEXT:    [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
21656 // CHECK20-NEXT:    call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
21657 // CHECK20-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
21658 // CHECK20-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
21659 // CHECK20-NEXT:    [[CMP7:%.*]] = icmp ugt i32 [[TMP11]], [[TMP12]]
21660 // CHECK20-NEXT:    br i1 [[CMP7]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
21661 // CHECK20:       cond.true:
21662 // CHECK20-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
21663 // CHECK20-NEXT:    br label [[COND_END:%.*]]
21664 // CHECK20:       cond.false:
21665 // CHECK20-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
21666 // CHECK20-NEXT:    br label [[COND_END]]
21667 // CHECK20:       cond.end:
21668 // CHECK20-NEXT:    [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ]
21669 // CHECK20-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
21670 // CHECK20-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
21671 // CHECK20-NEXT:    store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4
21672 // CHECK20-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
21673 // CHECK20:       omp.inner.for.cond:
21674 // CHECK20-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28
21675 // CHECK20-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !28
21676 // CHECK20-NEXT:    [[ADD8:%.*]] = add i32 [[TMP17]], 1
21677 // CHECK20-NEXT:    [[CMP9:%.*]] = icmp ult i32 [[TMP16]], [[ADD8]]
21678 // CHECK20-NEXT:    br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
21679 // CHECK20:       omp.inner.for.body:
21680 // CHECK20-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group !28
21681 // CHECK20-NEXT:    [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28
21682 // CHECK20-NEXT:    [[MUL:%.*]] = mul i32 [[TMP19]], 1
21683 // CHECK20-NEXT:    [[ADD10:%.*]] = add i32 [[TMP18]], [[MUL]]
21684 // CHECK20-NEXT:    store i32 [[ADD10]], i32* [[I6]], align 4, !llvm.access.group !28
21685 // CHECK20-NEXT:    [[TMP20:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !28
21686 // CHECK20-NEXT:    [[ADD11:%.*]] = add nsw i32 [[TMP20]], 1
21687 // CHECK20-NEXT:    store i32 [[ADD11]], i32* [[A_ADDR]], align 4, !llvm.access.group !28
21688 // CHECK20-NEXT:    [[TMP21:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !28
21689 // CHECK20-NEXT:    [[CONV12:%.*]] = sext i16 [[TMP21]] to i32
21690 // CHECK20-NEXT:    [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1
21691 // CHECK20-NEXT:    [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16
21692 // CHECK20-NEXT:    store i16 [[CONV14]], i16* [[CONV]], align 2, !llvm.access.group !28
21693 // CHECK20-NEXT:    [[TMP22:%.*]] = load i8, i8* [[CONV1]], align 1, !llvm.access.group !28
21694 // CHECK20-NEXT:    [[CONV15:%.*]] = sext i8 [[TMP22]] to i32
21695 // CHECK20-NEXT:    [[ADD16:%.*]] = add nsw i32 [[CONV15]], 1
21696 // CHECK20-NEXT:    [[CONV17:%.*]] = trunc i32 [[ADD16]] to i8
21697 // CHECK20-NEXT:    store i8 [[CONV17]], i8* [[CONV1]], align 1, !llvm.access.group !28
21698 // CHECK20-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
21699 // CHECK20-NEXT:    [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !28
21700 // CHECK20-NEXT:    [[ADD18:%.*]] = add nsw i32 [[TMP23]], 1
21701 // CHECK20-NEXT:    store i32 [[ADD18]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !28
21702 // CHECK20-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
21703 // CHECK20:       omp.body.continue:
21704 // CHECK20-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
21705 // CHECK20:       omp.inner.for.inc:
21706 // CHECK20-NEXT:    [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28
21707 // CHECK20-NEXT:    [[ADD19:%.*]] = add i32 [[TMP24]], 1
21708 // CHECK20-NEXT:    store i32 [[ADD19]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28
21709 // CHECK20-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP29:![0-9]+]]
21710 // CHECK20:       omp.inner.for.end:
21711 // CHECK20-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
21712 // CHECK20:       omp.loop.exit:
21713 // CHECK20-NEXT:    [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
21714 // CHECK20-NEXT:    [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4
21715 // CHECK20-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]])
21716 // CHECK20-NEXT:    [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
21717 // CHECK20-NEXT:    [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0
21718 // CHECK20-NEXT:    br i1 [[TMP28]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
21719 // CHECK20:       .omp.final.then:
21720 // CHECK20-NEXT:    [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
21721 // CHECK20-NEXT:    [[TMP30:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
21722 // CHECK20-NEXT:    [[TMP31:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
21723 // CHECK20-NEXT:    [[SUB20:%.*]] = sub i32 [[TMP30]], [[TMP31]]
21724 // CHECK20-NEXT:    [[SUB21:%.*]] = sub i32 [[SUB20]], 1
21725 // CHECK20-NEXT:    [[ADD22:%.*]] = add i32 [[SUB21]], 1
21726 // CHECK20-NEXT:    [[DIV23:%.*]] = udiv i32 [[ADD22]], 1
21727 // CHECK20-NEXT:    [[MUL24:%.*]] = mul i32 [[DIV23]], 1
21728 // CHECK20-NEXT:    [[ADD25:%.*]] = add i32 [[TMP29]], [[MUL24]]
21729 // CHECK20-NEXT:    store i32 [[ADD25]], i32* [[I6]], align 4
21730 // CHECK20-NEXT:    br label [[DOTOMP_FINAL_DONE]]
21731 // CHECK20:       .omp.final.done:
21732 // CHECK20-NEXT:    br label [[OMP_PRECOND_END]]
21733 // CHECK20:       omp.precond.end:
21734 // CHECK20-NEXT:    ret void
21735 //
21736 //
21737 // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215
21738 // CHECK20-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {
21739 // CHECK20-NEXT:  entry:
21740 // CHECK20-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
21741 // CHECK20-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
21742 // CHECK20-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
21743 // CHECK20-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
21744 // CHECK20-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 4
21745 // CHECK20-NEXT:    [[B_CASTED:%.*]] = alloca i32, align 4
21746 // CHECK20-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
21747 // CHECK20-NEXT:    store i32 [[B]], i32* [[B_ADDR]], align 4
21748 // CHECK20-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
21749 // CHECK20-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
21750 // CHECK20-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 4
21751 // CHECK20-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
21752 // CHECK20-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
21753 // CHECK20-NEXT:    [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
21754 // CHECK20-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
21755 // CHECK20-NEXT:    [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4
21756 // CHECK20-NEXT:    store i32 [[TMP4]], i32* [[B_CASTED]], align 4
21757 // CHECK20-NEXT:    [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4
21758 // CHECK20-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]])
21759 // CHECK20-NEXT:    ret void
21760 //
21761 //
21762 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..5
21763 // CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] {
21764 // CHECK20-NEXT:  entry:
21765 // CHECK20-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
21766 // CHECK20-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
21767 // CHECK20-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
21768 // CHECK20-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
21769 // CHECK20-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
21770 // CHECK20-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
21771 // CHECK20-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 4
21772 // CHECK20-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
21773 // CHECK20-NEXT:    [[TMP:%.*]] = alloca i32, align 4
21774 // CHECK20-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
21775 // CHECK20-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
21776 // CHECK20-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
21777 // CHECK20-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
21778 // CHECK20-NEXT:    [[I:%.*]] = alloca i32, align 4
21779 // CHECK20-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
21780 // CHECK20-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
21781 // CHECK20-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
21782 // CHECK20-NEXT:    store i32 [[B]], i32* [[B_ADDR]], align 4
21783 // CHECK20-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
21784 // CHECK20-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
21785 // CHECK20-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 4
21786 // CHECK20-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
21787 // CHECK20-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
21788 // CHECK20-NEXT:    [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
21789 // CHECK20-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
21790 // CHECK20-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
21791 // CHECK20-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
21792 // CHECK20-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
21793 // CHECK20-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
21794 // CHECK20-NEXT:    [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
21795 // CHECK20-NEXT:    [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
21796 // CHECK20-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
21797 // CHECK20-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
21798 // CHECK20-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 9
21799 // CHECK20-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
21800 // CHECK20:       cond.true:
21801 // CHECK20-NEXT:    br label [[COND_END:%.*]]
21802 // CHECK20:       cond.false:
21803 // CHECK20-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
21804 // CHECK20-NEXT:    br label [[COND_END]]
21805 // CHECK20:       cond.end:
21806 // CHECK20-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
21807 // CHECK20-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
21808 // CHECK20-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
21809 // CHECK20-NEXT:    store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
21810 // CHECK20-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
21811 // CHECK20:       omp.inner.for.cond:
21812 // CHECK20-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !31
21813 // CHECK20-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !31
21814 // CHECK20-NEXT:    [[CMP3:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
21815 // CHECK20-NEXT:    br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
21816 // CHECK20:       omp.inner.for.body:
21817 // CHECK20-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !31
21818 // CHECK20-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
21819 // CHECK20-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
21820 // CHECK20-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !31
21821 // CHECK20-NEXT:    [[TMP12:%.*]] = load i32, i32* [[B_ADDR]], align 4, !llvm.access.group !31
21822 // CHECK20-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP12]] to double
21823 // CHECK20-NEXT:    [[ADD4:%.*]] = fadd double [[CONV]], 1.500000e+00
21824 // CHECK20-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
21825 // CHECK20-NEXT:    store double [[ADD4]], double* [[A]], align 4, !llvm.access.group !31
21826 // CHECK20-NEXT:    [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
21827 // CHECK20-NEXT:    [[TMP13:%.*]] = load double, double* [[A5]], align 4, !llvm.access.group !31
21828 // CHECK20-NEXT:    [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00
21829 // CHECK20-NEXT:    store double [[INC]], double* [[A5]], align 4, !llvm.access.group !31
21830 // CHECK20-NEXT:    [[CONV6:%.*]] = fptosi double [[INC]] to i16
21831 // CHECK20-NEXT:    [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]]
21832 // CHECK20-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP14]]
21833 // CHECK20-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
21834 // CHECK20-NEXT:    store i16 [[CONV6]], i16* [[ARRAYIDX7]], align 2, !llvm.access.group !31
21835 // CHECK20-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
21836 // CHECK20:       omp.body.continue:
21837 // CHECK20-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
21838 // CHECK20:       omp.inner.for.inc:
21839 // CHECK20-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !31
21840 // CHECK20-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP15]], 1
21841 // CHECK20-NEXT:    store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !31
21842 // CHECK20-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP32:![0-9]+]]
21843 // CHECK20:       omp.inner.for.end:
21844 // CHECK20-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
21845 // CHECK20:       omp.loop.exit:
21846 // CHECK20-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
21847 // CHECK20-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
21848 // CHECK20-NEXT:    [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0
21849 // CHECK20-NEXT:    br i1 [[TMP17]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
21850 // CHECK20:       .omp.final.then:
21851 // CHECK20-NEXT:    store i32 10, i32* [[I]], align 4
21852 // CHECK20-NEXT:    br label [[DOTOMP_FINAL_DONE]]
21853 // CHECK20:       .omp.final.done:
21854 // CHECK20-NEXT:    ret void
21855 //
21856 //
21857 // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180
21858 // CHECK20-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
21859 // CHECK20-NEXT:  entry:
21860 // CHECK20-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
21861 // CHECK20-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
21862 // CHECK20-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
21863 // CHECK20-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
21864 // CHECK20-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
21865 // CHECK20-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
21866 // CHECK20-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
21867 // CHECK20-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
21868 // CHECK20-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
21869 // CHECK20-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
21870 // CHECK20-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
21871 // CHECK20-NEXT:    store i32 [[TMP1]], i32* [[A_CASTED]], align 4
21872 // CHECK20-NEXT:    [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
21873 // CHECK20-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
21874 // CHECK20-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
21875 // CHECK20-NEXT:    store i16 [[TMP3]], i16* [[CONV1]], align 2
21876 // CHECK20-NEXT:    [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
21877 // CHECK20-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]])
21878 // CHECK20-NEXT:    ret void
21879 //
21880 //
21881 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..6
21882 // CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {
21883 // CHECK20-NEXT:  entry:
21884 // CHECK20-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
21885 // CHECK20-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
21886 // CHECK20-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
21887 // CHECK20-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
21888 // CHECK20-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
21889 // CHECK20-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
21890 // CHECK20-NEXT:    [[TMP:%.*]] = alloca i32, align 4
21891 // CHECK20-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
21892 // CHECK20-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
21893 // CHECK20-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
21894 // CHECK20-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
21895 // CHECK20-NEXT:    [[I:%.*]] = alloca i32, align 4
21896 // CHECK20-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
21897 // CHECK20-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
21898 // CHECK20-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
21899 // CHECK20-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
21900 // CHECK20-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
21901 // CHECK20-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
21902 // CHECK20-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
21903 // CHECK20-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
21904 // CHECK20-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
21905 // CHECK20-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
21906 // CHECK20-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
21907 // CHECK20-NEXT:    [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
21908 // CHECK20-NEXT:    [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
21909 // CHECK20-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
21910 // CHECK20-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
21911 // CHECK20-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9
21912 // CHECK20-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
21913 // CHECK20:       cond.true:
21914 // CHECK20-NEXT:    br label [[COND_END:%.*]]
21915 // CHECK20:       cond.false:
21916 // CHECK20-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
21917 // CHECK20-NEXT:    br label [[COND_END]]
21918 // CHECK20:       cond.end:
21919 // CHECK20-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
21920 // CHECK20-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
21921 // CHECK20-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
21922 // CHECK20-NEXT:    store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
21923 // CHECK20-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
21924 // CHECK20:       omp.inner.for.cond:
21925 // CHECK20-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !34
21926 // CHECK20-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !34
21927 // CHECK20-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
21928 // CHECK20-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
21929 // CHECK20:       omp.inner.for.body:
21930 // CHECK20-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !34
21931 // CHECK20-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
21932 // CHECK20-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
21933 // CHECK20-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !34
21934 // CHECK20-NEXT:    [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !34
21935 // CHECK20-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
21936 // CHECK20-NEXT:    store i32 [[ADD2]], i32* [[A_ADDR]], align 4, !llvm.access.group !34
21937 // CHECK20-NEXT:    [[TMP10:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !34
21938 // CHECK20-NEXT:    [[CONV3:%.*]] = sext i16 [[TMP10]] to i32
21939 // CHECK20-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
21940 // CHECK20-NEXT:    [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
21941 // CHECK20-NEXT:    store i16 [[CONV5]], i16* [[CONV]], align 2, !llvm.access.group !34
21942 // CHECK20-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
21943 // CHECK20-NEXT:    [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !34
21944 // CHECK20-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1
21945 // CHECK20-NEXT:    store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !34
21946 // CHECK20-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
21947 // CHECK20:       omp.body.continue:
21948 // CHECK20-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
21949 // CHECK20:       omp.inner.for.inc:
21950 // CHECK20-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !34
21951 // CHECK20-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP12]], 1
21952 // CHECK20-NEXT:    store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !34
21953 // CHECK20-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP35:![0-9]+]]
21954 // CHECK20:       omp.inner.for.end:
21955 // CHECK20-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
21956 // CHECK20:       omp.loop.exit:
21957 // CHECK20-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
21958 // CHECK20-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
21959 // CHECK20-NEXT:    [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
21960 // CHECK20-NEXT:    br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
21961 // CHECK20:       .omp.final.then:
21962 // CHECK20-NEXT:    store i32 10, i32* [[I]], align 4
21963 // CHECK20-NEXT:    br label [[DOTOMP_FINAL_DONE]]
21964 // CHECK20:       .omp.final.done:
21965 // CHECK20-NEXT:    ret void
21966 //
21967 //
21968 // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97
21969 // CHECK21-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] {
21970 // CHECK21-NEXT:  entry:
21971 // CHECK21-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
21972 // CHECK21-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
21973 // CHECK21-NEXT:    [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8
21974 // CHECK21-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
21975 // CHECK21-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]])
21976 // CHECK21-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
21977 // CHECK21-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
21978 // CHECK21-NEXT:    store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8
21979 // CHECK21-NEXT:    [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
21980 // CHECK21-NEXT:    [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
21981 // CHECK21-NEXT:    [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32*
21982 // CHECK21-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 4
21983 // CHECK21-NEXT:    [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 4
21984 // CHECK21-NEXT:    call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
21985 // CHECK21-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
21986 // CHECK21-NEXT:    [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
21987 // CHECK21-NEXT:    store i16 [[TMP3]], i16* [[CONV5]], align 2
21988 // CHECK21-NEXT:    [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
21989 // CHECK21-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]])
21990 // CHECK21-NEXT:    ret void
21991 //
21992 //
21993 // CHECK21-LABEL: define {{[^@]+}}@.omp_outlined.
21994 // CHECK21-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR1:[0-9]+]] {
21995 // CHECK21-NEXT:  entry:
21996 // CHECK21-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
21997 // CHECK21-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
21998 // CHECK21-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
21999 // CHECK21-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
22000 // CHECK21-NEXT:    [[TMP:%.*]] = alloca i32, align 4
22001 // CHECK21-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
22002 // CHECK21-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
22003 // CHECK21-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
22004 // CHECK21-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
22005 // CHECK21-NEXT:    [[I:%.*]] = alloca i32, align 4
22006 // CHECK21-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
22007 // CHECK21-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
22008 // CHECK21-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
22009 // CHECK21-NEXT:    [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
22010 // CHECK21-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
22011 // CHECK21-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
22012 // CHECK21-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
22013 // CHECK21-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
22014 // CHECK21-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
22015 // CHECK21-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
22016 // CHECK21-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
22017 // CHECK21-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
22018 // CHECK21-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
22019 // CHECK21-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
22020 // CHECK21:       cond.true:
22021 // CHECK21-NEXT:    br label [[COND_END:%.*]]
22022 // CHECK21:       cond.false:
22023 // CHECK21-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
22024 // CHECK21-NEXT:    br label [[COND_END]]
22025 // CHECK21:       cond.end:
22026 // CHECK21-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
22027 // CHECK21-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
22028 // CHECK21-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
22029 // CHECK21-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
22030 // CHECK21-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
22031 // CHECK21:       omp.inner.for.cond:
22032 // CHECK21-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
22033 // CHECK21-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !11
22034 // CHECK21-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
22035 // CHECK21-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
22036 // CHECK21:       omp.inner.for.body:
22037 // CHECK21-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
22038 // CHECK21-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
22039 // CHECK21-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
22040 // CHECK21-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11
22041 // CHECK21-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
22042 // CHECK21:       omp.body.continue:
22043 // CHECK21-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
22044 // CHECK21:       omp.inner.for.inc:
22045 // CHECK21-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
22046 // CHECK21-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
22047 // CHECK21-NEXT:    store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
22048 // CHECK21-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]
22049 // CHECK21:       omp.inner.for.end:
22050 // CHECK21-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
22051 // CHECK21:       omp.loop.exit:
22052 // CHECK21-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
22053 // CHECK21-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
22054 // CHECK21-NEXT:    [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0
22055 // CHECK21-NEXT:    br i1 [[TMP10]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
22056 // CHECK21:       .omp.final.then:
22057 // CHECK21-NEXT:    store i32 10, i32* [[I]], align 4
22058 // CHECK21-NEXT:    br label [[DOTOMP_FINAL_DONE]]
22059 // CHECK21:       .omp.final.done:
22060 // CHECK21-NEXT:    ret void
22061 //
22062 //
22063 // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111
22064 // CHECK21-SAME: (i64 noundef [[AA:%.*]]) #[[ATTR0]] {
22065 // CHECK21-NEXT:  entry:
22066 // CHECK21-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
22067 // CHECK21-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
22068 // CHECK21-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
22069 // CHECK21-NEXT:    [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
22070 // CHECK21-NEXT:    [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
22071 // CHECK21-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
22072 // CHECK21-NEXT:    store i16 [[TMP0]], i16* [[CONV1]], align 2
22073 // CHECK21-NEXT:    [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
22074 // CHECK21-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]])
22075 // CHECK21-NEXT:    ret void
22076 //
22077 //
22078 // CHECK21-LABEL: define {{[^@]+}}@.omp_outlined..1
22079 // CHECK21-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR1]] {
22080 // CHECK21-NEXT:  entry:
22081 // CHECK21-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
22082 // CHECK21-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
22083 // CHECK21-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
22084 // CHECK21-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
22085 // CHECK21-NEXT:    [[TMP:%.*]] = alloca i32, align 4
22086 // CHECK21-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
22087 // CHECK21-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
22088 // CHECK21-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
22089 // CHECK21-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
22090 // CHECK21-NEXT:    [[I:%.*]] = alloca i32, align 4
22091 // CHECK21-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
22092 // CHECK21-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
22093 // CHECK21-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
22094 // CHECK21-NEXT:    [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
22095 // CHECK21-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
22096 // CHECK21-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
22097 // CHECK21-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
22098 // CHECK21-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
22099 // CHECK21-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
22100 // CHECK21-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
22101 // CHECK21-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
22102 // CHECK21-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
22103 // CHECK21-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
22104 // CHECK21-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
22105 // CHECK21:       cond.true:
22106 // CHECK21-NEXT:    br label [[COND_END:%.*]]
22107 // CHECK21:       cond.false:
22108 // CHECK21-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
22109 // CHECK21-NEXT:    br label [[COND_END]]
22110 // CHECK21:       cond.end:
22111 // CHECK21-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
22112 // CHECK21-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
22113 // CHECK21-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
22114 // CHECK21-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
22115 // CHECK21-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
22116 // CHECK21:       omp.inner.for.cond:
22117 // CHECK21-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
22118 // CHECK21-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !18
22119 // CHECK21-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
22120 // CHECK21-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
22121 // CHECK21:       omp.inner.for.body:
22122 // CHECK21-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
22123 // CHECK21-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
22124 // CHECK21-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
22125 // CHECK21-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18
22126 // CHECK21-NEXT:    [[TMP8:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !18
22127 // CHECK21-NEXT:    [[CONV2:%.*]] = sext i16 [[TMP8]] to i32
22128 // CHECK21-NEXT:    [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
22129 // CHECK21-NEXT:    [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
22130 // CHECK21-NEXT:    store i16 [[CONV4]], i16* [[CONV]], align 2, !llvm.access.group !18
22131 // CHECK21-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
22132 // CHECK21:       omp.body.continue:
22133 // CHECK21-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
22134 // CHECK21:       omp.inner.for.inc:
22135 // CHECK21-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
22136 // CHECK21-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP9]], 1
22137 // CHECK21-NEXT:    store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
22138 // CHECK21-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]
22139 // CHECK21:       omp.inner.for.end:
22140 // CHECK21-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
22141 // CHECK21:       omp.loop.exit:
22142 // CHECK21-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
22143 // CHECK21-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
22144 // CHECK21-NEXT:    [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0
22145 // CHECK21-NEXT:    br i1 [[TMP11]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
22146 // CHECK21:       .omp.final.then:
22147 // CHECK21-NEXT:    store i32 10, i32* [[I]], align 4
22148 // CHECK21-NEXT:    br label [[DOTOMP_FINAL_DONE]]
22149 // CHECK21:       .omp.final.done:
22150 // CHECK21-NEXT:    ret void
22151 //
22152 //
22153 // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118
22154 // CHECK21-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] {
22155 // CHECK21-NEXT:  entry:
22156 // CHECK21-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
22157 // CHECK21-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
22158 // CHECK21-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
22159 // CHECK21-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
22160 // CHECK21-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
22161 // CHECK21-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
22162 // CHECK21-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
22163 // CHECK21-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
22164 // CHECK21-NEXT:    [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
22165 // CHECK21-NEXT:    [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
22166 // CHECK21-NEXT:    store i32 [[TMP0]], i32* [[CONV2]], align 4
22167 // CHECK21-NEXT:    [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
22168 // CHECK21-NEXT:    [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
22169 // CHECK21-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
22170 // CHECK21-NEXT:    store i16 [[TMP2]], i16* [[CONV3]], align 2
22171 // CHECK21-NEXT:    [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
22172 // CHECK21-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
22173 // CHECK21-NEXT:    ret void
22174 //
22175 //
22176 // CHECK21-LABEL: define {{[^@]+}}@.omp_outlined..2
22177 // CHECK21-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR1]] {
22178 // CHECK21-NEXT:  entry:
22179 // CHECK21-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
22180 // CHECK21-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
22181 // CHECK21-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
22182 // CHECK21-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
22183 // CHECK21-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
22184 // CHECK21-NEXT:    [[TMP:%.*]] = alloca i32, align 4
22185 // CHECK21-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
22186 // CHECK21-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
22187 // CHECK21-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
22188 // CHECK21-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
22189 // CHECK21-NEXT:    [[I:%.*]] = alloca i32, align 4
22190 // CHECK21-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
22191 // CHECK21-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
22192 // CHECK21-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
22193 // CHECK21-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
22194 // CHECK21-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
22195 // CHECK21-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
22196 // CHECK21-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
22197 // CHECK21-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
22198 // CHECK21-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
22199 // CHECK21-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
22200 // CHECK21-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
22201 // CHECK21-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
22202 // CHECK21-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
22203 // CHECK21-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
22204 // CHECK21-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
22205 // CHECK21-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
22206 // CHECK21:       cond.true:
22207 // CHECK21-NEXT:    br label [[COND_END:%.*]]
22208 // CHECK21:       cond.false:
22209 // CHECK21-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
22210 // CHECK21-NEXT:    br label [[COND_END]]
22211 // CHECK21:       cond.end:
22212 // CHECK21-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
22213 // CHECK21-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
22214 // CHECK21-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
22215 // CHECK21-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
22216 // CHECK21-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
22217 // CHECK21:       omp.inner.for.cond:
22218 // CHECK21-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
22219 // CHECK21-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !21
22220 // CHECK21-NEXT:    [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
22221 // CHECK21-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
22222 // CHECK21:       omp.inner.for.body:
22223 // CHECK21-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
22224 // CHECK21-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
22225 // CHECK21-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
22226 // CHECK21-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !21
22227 // CHECK21-NEXT:    [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !21
22228 // CHECK21-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
22229 // CHECK21-NEXT:    store i32 [[ADD3]], i32* [[CONV]], align 4, !llvm.access.group !21
22230 // CHECK21-NEXT:    [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 2, !llvm.access.group !21
22231 // CHECK21-NEXT:    [[CONV4:%.*]] = sext i16 [[TMP9]] to i32
22232 // CHECK21-NEXT:    [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
22233 // CHECK21-NEXT:    [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
22234 // CHECK21-NEXT:    store i16 [[CONV6]], i16* [[CONV1]], align 2, !llvm.access.group !21
22235 // CHECK21-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
22236 // CHECK21:       omp.body.continue:
22237 // CHECK21-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
22238 // CHECK21:       omp.inner.for.inc:
22239 // CHECK21-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
22240 // CHECK21-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1
22241 // CHECK21-NEXT:    store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
22242 // CHECK21-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]]
22243 // CHECK21:       omp.inner.for.end:
22244 // CHECK21-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
22245 // CHECK21:       omp.loop.exit:
22246 // CHECK21-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
22247 // CHECK21-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
22248 // CHECK21-NEXT:    [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
22249 // CHECK21-NEXT:    br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
22250 // CHECK21:       .omp.final.then:
22251 // CHECK21-NEXT:    store i32 10, i32* [[I]], align 4
22252 // CHECK21-NEXT:    br label [[DOTOMP_FINAL_DONE]]
22253 // CHECK21:       .omp.final.done:
22254 // CHECK21-NEXT:    ret void
22255 //
22256 //
22257 // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142
22258 // CHECK21-SAME: (i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] {
22259 // CHECK21-NEXT:  entry:
22260 // CHECK21-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
22261 // CHECK21-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
22262 // CHECK21-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
22263 // CHECK21-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 8
22264 // CHECK21-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
22265 // CHECK21-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
22266 // CHECK21-NEXT:    [[VLA_ADDR4:%.*]] = alloca i64, align 8
22267 // CHECK21-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 8
22268 // CHECK21-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
22269 // CHECK21-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
22270 // CHECK21-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
22271 // CHECK21-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
22272 // CHECK21-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
22273 // CHECK21-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 8
22274 // CHECK21-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
22275 // CHECK21-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
22276 // CHECK21-NEXT:    store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
22277 // CHECK21-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 8
22278 // CHECK21-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
22279 // CHECK21-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
22280 // CHECK21-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
22281 // CHECK21-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
22282 // CHECK21-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
22283 // CHECK21-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
22284 // CHECK21-NEXT:    [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
22285 // CHECK21-NEXT:    [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
22286 // CHECK21-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
22287 // CHECK21-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
22288 // CHECK21-NEXT:    [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
22289 // CHECK21-NEXT:    [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
22290 // CHECK21-NEXT:    store i32 [[TMP8]], i32* [[CONV5]], align 4
22291 // CHECK21-NEXT:    [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
22292 // CHECK21-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]])
22293 // CHECK21-NEXT:    ret void
22294 //
22295 //
22296 // CHECK21-LABEL: define {{[^@]+}}@.omp_outlined..3
22297 // CHECK21-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR1]] {
22298 // CHECK21-NEXT:  entry:
22299 // CHECK21-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
22300 // CHECK21-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
22301 // CHECK21-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
22302 // CHECK21-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
22303 // CHECK21-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
22304 // CHECK21-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 8
22305 // CHECK21-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
22306 // CHECK21-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
22307 // CHECK21-NEXT:    [[VLA_ADDR4:%.*]] = alloca i64, align 8
22308 // CHECK21-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 8
22309 // CHECK21-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
22310 // CHECK21-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
22311 // CHECK21-NEXT:    [[TMP:%.*]] = alloca i32, align 4
22312 // CHECK21-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
22313 // CHECK21-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
22314 // CHECK21-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
22315 // CHECK21-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
22316 // CHECK21-NEXT:    [[I:%.*]] = alloca i32, align 4
22317 // CHECK21-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
22318 // CHECK21-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
22319 // CHECK21-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
22320 // CHECK21-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
22321 // CHECK21-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
22322 // CHECK21-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 8
22323 // CHECK21-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
22324 // CHECK21-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
22325 // CHECK21-NEXT:    store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
22326 // CHECK21-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 8
22327 // CHECK21-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
22328 // CHECK21-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
22329 // CHECK21-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
22330 // CHECK21-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
22331 // CHECK21-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
22332 // CHECK21-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
22333 // CHECK21-NEXT:    [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
22334 // CHECK21-NEXT:    [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
22335 // CHECK21-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
22336 // CHECK21-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
22337 // CHECK21-NEXT:    [[ARRAYDECAY:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 0
22338 // CHECK21-NEXT:    call void @llvm.assume(i1 true) [ "align"(float* [[ARRAYDECAY]], i64 16) ]
22339 // CHECK21-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
22340 // CHECK21-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
22341 // CHECK21-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
22342 // CHECK21-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
22343 // CHECK21-NEXT:    [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
22344 // CHECK21-NEXT:    [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4
22345 // CHECK21-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
22346 // CHECK21-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
22347 // CHECK21-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP10]], 9
22348 // CHECK21-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
22349 // CHECK21:       cond.true:
22350 // CHECK21-NEXT:    br label [[COND_END:%.*]]
22351 // CHECK21:       cond.false:
22352 // CHECK21-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
22353 // CHECK21-NEXT:    br label [[COND_END]]
22354 // CHECK21:       cond.end:
22355 // CHECK21-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ]
22356 // CHECK21-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
22357 // CHECK21-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
22358 // CHECK21-NEXT:    store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4
22359 // CHECK21-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
22360 // CHECK21:       omp.inner.for.cond:
22361 // CHECK21-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
22362 // CHECK21-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !24
22363 // CHECK21-NEXT:    [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
22364 // CHECK21-NEXT:    br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
22365 // CHECK21:       omp.inner.for.body:
22366 // CHECK21-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
22367 // CHECK21-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1
22368 // CHECK21-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
22369 // CHECK21-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !24
22370 // CHECK21-NEXT:    [[TMP16:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !24
22371 // CHECK21-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP16]], 1
22372 // CHECK21-NEXT:    store i32 [[ADD6]], i32* [[CONV]], align 4, !llvm.access.group !24
22373 // CHECK21-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
22374 // CHECK21-NEXT:    [[TMP17:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !24
22375 // CHECK21-NEXT:    [[CONV7:%.*]] = fpext float [[TMP17]] to double
22376 // CHECK21-NEXT:    [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00
22377 // CHECK21-NEXT:    [[CONV9:%.*]] = fptrunc double [[ADD8]] to float
22378 // CHECK21-NEXT:    store float [[CONV9]], float* [[ARRAYIDX]], align 4, !llvm.access.group !24
22379 // CHECK21-NEXT:    [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3
22380 // CHECK21-NEXT:    [[TMP18:%.*]] = load float, float* [[ARRAYIDX10]], align 4, !llvm.access.group !24
22381 // CHECK21-NEXT:    [[CONV11:%.*]] = fpext float [[TMP18]] to double
22382 // CHECK21-NEXT:    [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00
22383 // CHECK21-NEXT:    [[CONV13:%.*]] = fptrunc double [[ADD12]] to float
22384 // CHECK21-NEXT:    store float [[CONV13]], float* [[ARRAYIDX10]], align 4, !llvm.access.group !24
22385 // CHECK21-NEXT:    [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1
22386 // CHECK21-NEXT:    [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX14]], i64 0, i64 2
22387 // CHECK21-NEXT:    [[TMP19:%.*]] = load double, double* [[ARRAYIDX15]], align 8, !llvm.access.group !24
22388 // CHECK21-NEXT:    [[ADD16:%.*]] = fadd double [[TMP19]], 1.000000e+00
22389 // CHECK21-NEXT:    store double [[ADD16]], double* [[ARRAYIDX15]], align 8, !llvm.access.group !24
22390 // CHECK21-NEXT:    [[TMP20:%.*]] = mul nsw i64 1, [[TMP5]]
22391 // CHECK21-NEXT:    [[ARRAYIDX17:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP20]]
22392 // CHECK21-NEXT:    [[ARRAYIDX18:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX17]], i64 3
22393 // CHECK21-NEXT:    [[TMP21:%.*]] = load double, double* [[ARRAYIDX18]], align 8, !llvm.access.group !24
22394 // CHECK21-NEXT:    [[ADD19:%.*]] = fadd double [[TMP21]], 1.000000e+00
22395 // CHECK21-NEXT:    store double [[ADD19]], double* [[ARRAYIDX18]], align 8, !llvm.access.group !24
22396 // CHECK21-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0
22397 // CHECK21-NEXT:    [[TMP22:%.*]] = load i64, i64* [[X]], align 8, !llvm.access.group !24
22398 // CHECK21-NEXT:    [[ADD20:%.*]] = add nsw i64 [[TMP22]], 1
22399 // CHECK21-NEXT:    store i64 [[ADD20]], i64* [[X]], align 8, !llvm.access.group !24
22400 // CHECK21-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1
22401 // CHECK21-NEXT:    [[TMP23:%.*]] = load i8, i8* [[Y]], align 8, !llvm.access.group !24
22402 // CHECK21-NEXT:    [[CONV21:%.*]] = sext i8 [[TMP23]] to i32
22403 // CHECK21-NEXT:    [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1
22404 // CHECK21-NEXT:    [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8
22405 // CHECK21-NEXT:    store i8 [[CONV23]], i8* [[Y]], align 8, !llvm.access.group !24
22406 // CHECK21-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
22407 // CHECK21:       omp.body.continue:
22408 // CHECK21-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
22409 // CHECK21:       omp.inner.for.inc:
22410 // CHECK21-NEXT:    [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
22411 // CHECK21-NEXT:    [[ADD24:%.*]] = add nsw i32 [[TMP24]], 1
22412 // CHECK21-NEXT:    store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
22413 // CHECK21-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]]
22414 // CHECK21:       omp.inner.for.end:
22415 // CHECK21-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
22416 // CHECK21:       omp.loop.exit:
22417 // CHECK21-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]])
22418 // CHECK21-NEXT:    [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
22419 // CHECK21-NEXT:    [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
22420 // CHECK21-NEXT:    br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
22421 // CHECK21:       .omp.final.then:
22422 // CHECK21-NEXT:    store i32 10, i32* [[I]], align 4
22423 // CHECK21-NEXT:    br label [[DOTOMP_FINAL_DONE]]
22424 // CHECK21:       .omp.final.done:
22425 // CHECK21-NEXT:    ret void
22426 //
22427 //
22428 // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197
22429 // CHECK21-SAME: (i64 noundef [[A:%.*]], i64 noundef [[N:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
22430 // CHECK21-NEXT:  entry:
22431 // CHECK21-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
22432 // CHECK21-NEXT:    [[N_ADDR:%.*]] = alloca i64, align 8
22433 // CHECK21-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
22434 // CHECK21-NEXT:    [[AAA_ADDR:%.*]] = alloca i64, align 8
22435 // CHECK21-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
22436 // CHECK21-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
22437 // CHECK21-NEXT:    [[N_CASTED:%.*]] = alloca i64, align 8
22438 // CHECK21-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
22439 // CHECK21-NEXT:    [[AAA_CASTED:%.*]] = alloca i64, align 8
22440 // CHECK21-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
22441 // CHECK21-NEXT:    store i64 [[N]], i64* [[N_ADDR]], align 8
22442 // CHECK21-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
22443 // CHECK21-NEXT:    store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
22444 // CHECK21-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
22445 // CHECK21-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
22446 // CHECK21-NEXT:    [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32*
22447 // CHECK21-NEXT:    [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
22448 // CHECK21-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
22449 // CHECK21-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
22450 // CHECK21-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
22451 // CHECK21-NEXT:    [[CONV4:%.*]] = bitcast i64* [[A_CASTED]] to i32*
22452 // CHECK21-NEXT:    store i32 [[TMP1]], i32* [[CONV4]], align 4
22453 // CHECK21-NEXT:    [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
22454 // CHECK21-NEXT:    [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 4
22455 // CHECK21-NEXT:    [[CONV5:%.*]] = bitcast i64* [[N_CASTED]] to i32*
22456 // CHECK21-NEXT:    store i32 [[TMP3]], i32* [[CONV5]], align 4
22457 // CHECK21-NEXT:    [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8
22458 // CHECK21-NEXT:    [[TMP5:%.*]] = load i16, i16* [[CONV2]], align 2
22459 // CHECK21-NEXT:    [[CONV6:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
22460 // CHECK21-NEXT:    store i16 [[TMP5]], i16* [[CONV6]], align 2
22461 // CHECK21-NEXT:    [[TMP6:%.*]] = load i64, i64* [[AA_CASTED]], align 8
22462 // CHECK21-NEXT:    [[TMP7:%.*]] = load i8, i8* [[CONV3]], align 1
22463 // CHECK21-NEXT:    [[CONV7:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
22464 // CHECK21-NEXT:    store i8 [[TMP7]], i8* [[CONV7]], align 1
22465 // CHECK21-NEXT:    [[TMP8:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
22466 // CHECK21-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]], [10 x i32]* [[TMP0]])
22467 // CHECK21-NEXT:    ret void
22468 //
22469 //
22470 // CHECK21-LABEL: define {{[^@]+}}@.omp_outlined..4
22471 // CHECK21-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[N:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {
22472 // CHECK21-NEXT:  entry:
22473 // CHECK21-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
22474 // CHECK21-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
22475 // CHECK21-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
22476 // CHECK21-NEXT:    [[N_ADDR:%.*]] = alloca i64, align 8
22477 // CHECK21-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
22478 // CHECK21-NEXT:    [[AAA_ADDR:%.*]] = alloca i64, align 8
22479 // CHECK21-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
22480 // CHECK21-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
22481 // CHECK21-NEXT:    [[TMP:%.*]] = alloca i32, align 4
22482 // CHECK21-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
22483 // CHECK21-NEXT:    [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4
22484 // CHECK21-NEXT:    [[DOTCAPTURE_EXPR_5:%.*]] = alloca i32, align 4
22485 // CHECK21-NEXT:    [[I:%.*]] = alloca i32, align 4
22486 // CHECK21-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
22487 // CHECK21-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
22488 // CHECK21-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
22489 // CHECK21-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
22490 // CHECK21-NEXT:    [[I8:%.*]] = alloca i32, align 4
22491 // CHECK21-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
22492 // CHECK21-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
22493 // CHECK21-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
22494 // CHECK21-NEXT:    store i64 [[N]], i64* [[N_ADDR]], align 8
22495 // CHECK21-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
22496 // CHECK21-NEXT:    store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
22497 // CHECK21-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
22498 // CHECK21-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
22499 // CHECK21-NEXT:    [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32*
22500 // CHECK21-NEXT:    [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
22501 // CHECK21-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
22502 // CHECK21-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
22503 // CHECK21-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
22504 // CHECK21-NEXT:    store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
22505 // CHECK21-NEXT:    [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4
22506 // CHECK21-NEXT:    store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_4]], align 4
22507 // CHECK21-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4
22508 // CHECK21-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
22509 // CHECK21-NEXT:    [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]]
22510 // CHECK21-NEXT:    [[SUB6:%.*]] = sub i32 [[SUB]], 1
22511 // CHECK21-NEXT:    [[ADD:%.*]] = add i32 [[SUB6]], 1
22512 // CHECK21-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], 1
22513 // CHECK21-NEXT:    [[SUB7:%.*]] = sub i32 [[DIV]], 1
22514 // CHECK21-NEXT:    store i32 [[SUB7]], i32* [[DOTCAPTURE_EXPR_5]], align 4
22515 // CHECK21-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
22516 // CHECK21-NEXT:    store i32 [[TMP5]], i32* [[I]], align 4
22517 // CHECK21-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
22518 // CHECK21-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4
22519 // CHECK21-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]]
22520 // CHECK21-NEXT:    br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
22521 // CHECK21:       omp.precond.then:
22522 // CHECK21-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
22523 // CHECK21-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4
22524 // CHECK21-NEXT:    store i32 [[TMP8]], i32* [[DOTOMP_UB]], align 4
22525 // CHECK21-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
22526 // CHECK21-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
22527 // CHECK21-NEXT:    [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
22528 // CHECK21-NEXT:    [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
22529 // CHECK21-NEXT:    call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
22530 // CHECK21-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
22531 // CHECK21-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4
22532 // CHECK21-NEXT:    [[CMP9:%.*]] = icmp ugt i32 [[TMP11]], [[TMP12]]
22533 // CHECK21-NEXT:    br i1 [[CMP9]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
22534 // CHECK21:       cond.true:
22535 // CHECK21-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4
22536 // CHECK21-NEXT:    br label [[COND_END:%.*]]
22537 // CHECK21:       cond.false:
22538 // CHECK21-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
22539 // CHECK21-NEXT:    br label [[COND_END]]
22540 // CHECK21:       cond.end:
22541 // CHECK21-NEXT:    [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ]
22542 // CHECK21-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
22543 // CHECK21-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
22544 // CHECK21-NEXT:    store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4
22545 // CHECK21-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
22546 // CHECK21:       omp.inner.for.cond:
22547 // CHECK21-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27
22548 // CHECK21-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !27
22549 // CHECK21-NEXT:    [[ADD10:%.*]] = add i32 [[TMP17]], 1
22550 // CHECK21-NEXT:    [[CMP11:%.*]] = icmp ult i32 [[TMP16]], [[ADD10]]
22551 // CHECK21-NEXT:    br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
22552 // CHECK21:       omp.inner.for.body:
22553 // CHECK21-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group !27
22554 // CHECK21-NEXT:    [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27
22555 // CHECK21-NEXT:    [[MUL:%.*]] = mul i32 [[TMP19]], 1
22556 // CHECK21-NEXT:    [[ADD12:%.*]] = add i32 [[TMP18]], [[MUL]]
22557 // CHECK21-NEXT:    store i32 [[ADD12]], i32* [[I8]], align 4, !llvm.access.group !27
22558 // CHECK21-NEXT:    [[TMP20:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !27
22559 // CHECK21-NEXT:    [[ADD13:%.*]] = add nsw i32 [[TMP20]], 1
22560 // CHECK21-NEXT:    store i32 [[ADD13]], i32* [[CONV]], align 4, !llvm.access.group !27
22561 // CHECK21-NEXT:    [[TMP21:%.*]] = load i16, i16* [[CONV2]], align 2, !llvm.access.group !27
22562 // CHECK21-NEXT:    [[CONV14:%.*]] = sext i16 [[TMP21]] to i32
22563 // CHECK21-NEXT:    [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1
22564 // CHECK21-NEXT:    [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16
22565 // CHECK21-NEXT:    store i16 [[CONV16]], i16* [[CONV2]], align 2, !llvm.access.group !27
22566 // CHECK21-NEXT:    [[TMP22:%.*]] = load i8, i8* [[CONV3]], align 1, !llvm.access.group !27
22567 // CHECK21-NEXT:    [[CONV17:%.*]] = sext i8 [[TMP22]] to i32
22568 // CHECK21-NEXT:    [[ADD18:%.*]] = add nsw i32 [[CONV17]], 1
22569 // CHECK21-NEXT:    [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8
22570 // CHECK21-NEXT:    store i8 [[CONV19]], i8* [[CONV3]], align 1, !llvm.access.group !27
22571 // CHECK21-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
22572 // CHECK21-NEXT:    [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !27
22573 // CHECK21-NEXT:    [[ADD20:%.*]] = add nsw i32 [[TMP23]], 1
22574 // CHECK21-NEXT:    store i32 [[ADD20]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !27
22575 // CHECK21-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
22576 // CHECK21:       omp.body.continue:
22577 // CHECK21-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
22578 // CHECK21:       omp.inner.for.inc:
22579 // CHECK21-NEXT:    [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27
22580 // CHECK21-NEXT:    [[ADD21:%.*]] = add i32 [[TMP24]], 1
22581 // CHECK21-NEXT:    store i32 [[ADD21]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27
22582 // CHECK21-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]]
22583 // CHECK21:       omp.inner.for.end:
22584 // CHECK21-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
22585 // CHECK21:       omp.loop.exit:
22586 // CHECK21-NEXT:    [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
22587 // CHECK21-NEXT:    [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4
22588 // CHECK21-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]])
22589 // CHECK21-NEXT:    [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
22590 // CHECK21-NEXT:    [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0
22591 // CHECK21-NEXT:    br i1 [[TMP28]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
22592 // CHECK21:       .omp.final.then:
22593 // CHECK21-NEXT:    [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
22594 // CHECK21-NEXT:    [[TMP30:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4
22595 // CHECK21-NEXT:    [[TMP31:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
22596 // CHECK21-NEXT:    [[SUB22:%.*]] = sub i32 [[TMP30]], [[TMP31]]
22597 // CHECK21-NEXT:    [[SUB23:%.*]] = sub i32 [[SUB22]], 1
22598 // CHECK21-NEXT:    [[ADD24:%.*]] = add i32 [[SUB23]], 1
22599 // CHECK21-NEXT:    [[DIV25:%.*]] = udiv i32 [[ADD24]], 1
22600 // CHECK21-NEXT:    [[MUL26:%.*]] = mul i32 [[DIV25]], 1
22601 // CHECK21-NEXT:    [[ADD27:%.*]] = add i32 [[TMP29]], [[MUL26]]
22602 // CHECK21-NEXT:    store i32 [[ADD27]], i32* [[I8]], align 4
22603 // CHECK21-NEXT:    br label [[DOTOMP_FINAL_DONE]]
22604 // CHECK21:       .omp.final.done:
22605 // CHECK21-NEXT:    br label [[OMP_PRECOND_END]]
22606 // CHECK21:       omp.precond.end:
22607 // CHECK21-NEXT:    ret void
22608 //
22609 //
22610 // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215
22611 // CHECK21-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
22612 // CHECK21-NEXT:  entry:
22613 // CHECK21-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
22614 // CHECK21-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
22615 // CHECK21-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
22616 // CHECK21-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
22617 // CHECK21-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 8
22618 // CHECK21-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
22619 // CHECK21-NEXT:    [[B_CASTED:%.*]] = alloca i64, align 8
22620 // CHECK21-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
22621 // CHECK21-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
22622 // CHECK21-NEXT:    store i64 [[B]], i64* [[B_ADDR]], align 8
22623 // CHECK21-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
22624 // CHECK21-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
22625 // CHECK21-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 8
22626 // CHECK21-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
22627 // CHECK21-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
22628 // CHECK21-NEXT:    [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
22629 // CHECK21-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
22630 // CHECK21-NEXT:    [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
22631 // CHECK21-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
22632 // CHECK21-NEXT:    [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
22633 // CHECK21-NEXT:    [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
22634 // CHECK21-NEXT:    [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i32*
22635 // CHECK21-NEXT:    store i32 [[TMP4]], i32* [[CONV4]], align 4
22636 // CHECK21-NEXT:    [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
22637 // CHECK21-NEXT:    [[TMP6:%.*]] = load i8, i8* [[CONV3]], align 1
22638 // CHECK21-NEXT:    [[TOBOOL:%.*]] = trunc i8 [[TMP6]] to i1
22639 // CHECK21-NEXT:    [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
22640 // CHECK21-NEXT:    [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
22641 // CHECK21-NEXT:    store i8 [[FROMBOOL]], i8* [[CONV5]], align 1
22642 // CHECK21-NEXT:    [[TMP7:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
22643 // CHECK21-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]], i64 [[TMP7]])
22644 // CHECK21-NEXT:    ret void
22645 //
22646 //
22647 // CHECK21-LABEL: define {{[^@]+}}@.omp_outlined..5
22648 // CHECK21-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
22649 // CHECK21-NEXT:  entry:
22650 // CHECK21-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
22651 // CHECK21-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
22652 // CHECK21-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
22653 // CHECK21-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
22654 // CHECK21-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
22655 // CHECK21-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
22656 // CHECK21-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 8
22657 // CHECK21-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
22658 // CHECK21-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
22659 // CHECK21-NEXT:    [[TMP:%.*]] = alloca i32, align 4
22660 // CHECK21-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
22661 // CHECK21-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
22662 // CHECK21-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
22663 // CHECK21-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
22664 // CHECK21-NEXT:    [[I:%.*]] = alloca i32, align 4
22665 // CHECK21-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
22666 // CHECK21-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
22667 // CHECK21-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
22668 // CHECK21-NEXT:    store i64 [[B]], i64* [[B_ADDR]], align 8
22669 // CHECK21-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
22670 // CHECK21-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
22671 // CHECK21-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 8
22672 // CHECK21-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
22673 // CHECK21-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
22674 // CHECK21-NEXT:    [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
22675 // CHECK21-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
22676 // CHECK21-NEXT:    [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
22677 // CHECK21-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
22678 // CHECK21-NEXT:    [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
22679 // CHECK21-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
22680 // CHECK21-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
22681 // CHECK21-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
22682 // CHECK21-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
22683 // CHECK21-NEXT:    [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
22684 // CHECK21-NEXT:    [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
22685 // CHECK21-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
22686 // CHECK21-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
22687 // CHECK21-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 9
22688 // CHECK21-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
22689 // CHECK21:       cond.true:
22690 // CHECK21-NEXT:    br label [[COND_END:%.*]]
22691 // CHECK21:       cond.false:
22692 // CHECK21-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
22693 // CHECK21-NEXT:    br label [[COND_END]]
22694 // CHECK21:       cond.end:
22695 // CHECK21-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
22696 // CHECK21-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
22697 // CHECK21-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
22698 // CHECK21-NEXT:    store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
22699 // CHECK21-NEXT:    [[TMP9:%.*]] = load i8, i8* [[CONV3]], align 1
22700 // CHECK21-NEXT:    [[TOBOOL:%.*]] = trunc i8 [[TMP9]] to i1
22701 // CHECK21-NEXT:    br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
22702 // CHECK21:       omp_if.then:
22703 // CHECK21-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
22704 // CHECK21:       omp.inner.for.cond:
22705 // CHECK21-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30
22706 // CHECK21-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !30
22707 // CHECK21-NEXT:    [[CMP4:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]
22708 // CHECK21-NEXT:    br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
22709 // CHECK21:       omp.inner.for.body:
22710 // CHECK21-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30
22711 // CHECK21-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1
22712 // CHECK21-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
22713 // CHECK21-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !30
22714 // CHECK21-NEXT:    [[TMP13:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !30
22715 // CHECK21-NEXT:    [[CONV5:%.*]] = sitofp i32 [[TMP13]] to double
22716 // CHECK21-NEXT:    [[ADD6:%.*]] = fadd double [[CONV5]], 1.500000e+00
22717 // CHECK21-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
22718 // CHECK21-NEXT:    store double [[ADD6]], double* [[A]], align 8, !llvm.access.group !30
22719 // CHECK21-NEXT:    [[A7:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
22720 // CHECK21-NEXT:    [[TMP14:%.*]] = load double, double* [[A7]], align 8, !llvm.access.group !30
22721 // CHECK21-NEXT:    [[INC:%.*]] = fadd double [[TMP14]], 1.000000e+00
22722 // CHECK21-NEXT:    store double [[INC]], double* [[A7]], align 8, !llvm.access.group !30
22723 // CHECK21-NEXT:    [[CONV8:%.*]] = fptosi double [[INC]] to i16
22724 // CHECK21-NEXT:    [[TMP15:%.*]] = mul nsw i64 1, [[TMP2]]
22725 // CHECK21-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP15]]
22726 // CHECK21-NEXT:    [[ARRAYIDX9:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
22727 // CHECK21-NEXT:    store i16 [[CONV8]], i16* [[ARRAYIDX9]], align 2, !llvm.access.group !30
22728 // CHECK21-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
22729 // CHECK21:       omp.body.continue:
22730 // CHECK21-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
22731 // CHECK21:       omp.inner.for.inc:
22732 // CHECK21-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30
22733 // CHECK21-NEXT:    [[ADD10:%.*]] = add nsw i32 [[TMP16]], 1
22734 // CHECK21-NEXT:    store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30
22735 // CHECK21-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP31:![0-9]+]]
22736 // CHECK21:       omp.inner.for.end:
22737 // CHECK21-NEXT:    br label [[OMP_IF_END:%.*]]
22738 // CHECK21:       omp_if.else:
22739 // CHECK21-NEXT:    br label [[OMP_INNER_FOR_COND11:%.*]]
22740 // CHECK21:       omp.inner.for.cond11:
22741 // CHECK21-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
22742 // CHECK21-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
22743 // CHECK21-NEXT:    [[CMP12:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]]
22744 // CHECK21-NEXT:    br i1 [[CMP12]], label [[OMP_INNER_FOR_BODY13:%.*]], label [[OMP_INNER_FOR_END27:%.*]]
22745 // CHECK21:       omp.inner.for.body13:
22746 // CHECK21-NEXT:    [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
22747 // CHECK21-NEXT:    [[MUL14:%.*]] = mul nsw i32 [[TMP19]], 1
22748 // CHECK21-NEXT:    [[ADD15:%.*]] = add nsw i32 0, [[MUL14]]
22749 // CHECK21-NEXT:    store i32 [[ADD15]], i32* [[I]], align 4
22750 // CHECK21-NEXT:    [[TMP20:%.*]] = load i32, i32* [[CONV]], align 4
22751 // CHECK21-NEXT:    [[CONV16:%.*]] = sitofp i32 [[TMP20]] to double
22752 // CHECK21-NEXT:    [[ADD17:%.*]] = fadd double [[CONV16]], 1.500000e+00
22753 // CHECK21-NEXT:    [[A18:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
22754 // CHECK21-NEXT:    store double [[ADD17]], double* [[A18]], align 8
22755 // CHECK21-NEXT:    [[A19:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
22756 // CHECK21-NEXT:    [[TMP21:%.*]] = load double, double* [[A19]], align 8
22757 // CHECK21-NEXT:    [[INC20:%.*]] = fadd double [[TMP21]], 1.000000e+00
22758 // CHECK21-NEXT:    store double [[INC20]], double* [[A19]], align 8
22759 // CHECK21-NEXT:    [[CONV21:%.*]] = fptosi double [[INC20]] to i16
22760 // CHECK21-NEXT:    [[TMP22:%.*]] = mul nsw i64 1, [[TMP2]]
22761 // CHECK21-NEXT:    [[ARRAYIDX22:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP22]]
22762 // CHECK21-NEXT:    [[ARRAYIDX23:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX22]], i64 1
22763 // CHECK21-NEXT:    store i16 [[CONV21]], i16* [[ARRAYIDX23]], align 2
22764 // CHECK21-NEXT:    br label [[OMP_BODY_CONTINUE24:%.*]]
22765 // CHECK21:       omp.body.continue24:
22766 // CHECK21-NEXT:    br label [[OMP_INNER_FOR_INC25:%.*]]
22767 // CHECK21:       omp.inner.for.inc25:
22768 // CHECK21-NEXT:    [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
22769 // CHECK21-NEXT:    [[ADD26:%.*]] = add nsw i32 [[TMP23]], 1
22770 // CHECK21-NEXT:    store i32 [[ADD26]], i32* [[DOTOMP_IV]], align 4
22771 // CHECK21-NEXT:    br label [[OMP_INNER_FOR_COND11]], !llvm.loop [[LOOP33:![0-9]+]]
22772 // CHECK21:       omp.inner.for.end27:
22773 // CHECK21-NEXT:    br label [[OMP_IF_END]]
22774 // CHECK21:       omp_if.end:
22775 // CHECK21-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
22776 // CHECK21:       omp.loop.exit:
22777 // CHECK21-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
22778 // CHECK21-NEXT:    [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
22779 // CHECK21-NEXT:    [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0
22780 // CHECK21-NEXT:    br i1 [[TMP25]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
22781 // CHECK21:       .omp.final.then:
22782 // CHECK21-NEXT:    store i32 10, i32* [[I]], align 4
22783 // CHECK21-NEXT:    br label [[DOTOMP_FINAL_DONE]]
22784 // CHECK21:       .omp.final.done:
22785 // CHECK21-NEXT:    ret void
22786 //
22787 //
22788 // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180
22789 // CHECK21-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
22790 // CHECK21-NEXT:  entry:
22791 // CHECK21-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
22792 // CHECK21-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
22793 // CHECK21-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
22794 // CHECK21-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
22795 // CHECK21-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
22796 // CHECK21-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
22797 // CHECK21-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
22798 // CHECK21-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
22799 // CHECK21-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
22800 // CHECK21-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
22801 // CHECK21-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
22802 // CHECK21-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
22803 // CHECK21-NEXT:    [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
22804 // CHECK21-NEXT:    store i32 [[TMP1]], i32* [[CONV2]], align 4
22805 // CHECK21-NEXT:    [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
22806 // CHECK21-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
22807 // CHECK21-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
22808 // CHECK21-NEXT:    store i16 [[TMP3]], i16* [[CONV3]], align 2
22809 // CHECK21-NEXT:    [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
22810 // CHECK21-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]])
22811 // CHECK21-NEXT:    ret void
22812 //
22813 //
22814 // CHECK21-LABEL: define {{[^@]+}}@.omp_outlined..6
22815 // CHECK21-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {
22816 // CHECK21-NEXT:  entry:
22817 // CHECK21-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
22818 // CHECK21-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
22819 // CHECK21-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
22820 // CHECK21-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
22821 // CHECK21-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
22822 // CHECK21-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
22823 // CHECK21-NEXT:    [[TMP:%.*]] = alloca i32, align 4
22824 // CHECK21-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
22825 // CHECK21-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
22826 // CHECK21-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
22827 // CHECK21-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
22828 // CHECK21-NEXT:    [[I:%.*]] = alloca i32, align 4
22829 // CHECK21-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
22830 // CHECK21-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
22831 // CHECK21-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
22832 // CHECK21-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
22833 // CHECK21-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
22834 // CHECK21-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
22835 // CHECK21-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
22836 // CHECK21-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
22837 // CHECK21-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
22838 // CHECK21-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
22839 // CHECK21-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
22840 // CHECK21-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
22841 // CHECK21-NEXT:    [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
22842 // CHECK21-NEXT:    [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
22843 // CHECK21-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
22844 // CHECK21-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
22845 // CHECK21-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9
22846 // CHECK21-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
22847 // CHECK21:       cond.true:
22848 // CHECK21-NEXT:    br label [[COND_END:%.*]]
22849 // CHECK21:       cond.false:
22850 // CHECK21-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
22851 // CHECK21-NEXT:    br label [[COND_END]]
22852 // CHECK21:       cond.end:
22853 // CHECK21-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
22854 // CHECK21-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
22855 // CHECK21-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
22856 // CHECK21-NEXT:    store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
22857 // CHECK21-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
22858 // CHECK21:       omp.inner.for.cond:
22859 // CHECK21-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !35
22860 // CHECK21-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !35
22861 // CHECK21-NEXT:    [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
22862 // CHECK21-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
22863 // CHECK21:       omp.inner.for.body:
22864 // CHECK21-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !35
22865 // CHECK21-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
22866 // CHECK21-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
22867 // CHECK21-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !35
22868 // CHECK21-NEXT:    [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !35
22869 // CHECK21-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1
22870 // CHECK21-NEXT:    store i32 [[ADD3]], i32* [[CONV]], align 4, !llvm.access.group !35
22871 // CHECK21-NEXT:    [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 2, !llvm.access.group !35
22872 // CHECK21-NEXT:    [[CONV4:%.*]] = sext i16 [[TMP10]] to i32
22873 // CHECK21-NEXT:    [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
22874 // CHECK21-NEXT:    [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
22875 // CHECK21-NEXT:    store i16 [[CONV6]], i16* [[CONV1]], align 2, !llvm.access.group !35
22876 // CHECK21-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
22877 // CHECK21-NEXT:    [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !35
22878 // CHECK21-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1
22879 // CHECK21-NEXT:    store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !35
22880 // CHECK21-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
22881 // CHECK21:       omp.body.continue:
22882 // CHECK21-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
22883 // CHECK21:       omp.inner.for.inc:
22884 // CHECK21-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !35
22885 // CHECK21-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP12]], 1
22886 // CHECK21-NEXT:    store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !35
22887 // CHECK21-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP36:![0-9]+]]
22888 // CHECK21:       omp.inner.for.end:
22889 // CHECK21-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
22890 // CHECK21:       omp.loop.exit:
22891 // CHECK21-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
22892 // CHECK21-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
22893 // CHECK21-NEXT:    [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
22894 // CHECK21-NEXT:    br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
22895 // CHECK21:       .omp.final.then:
22896 // CHECK21-NEXT:    store i32 10, i32* [[I]], align 4
22897 // CHECK21-NEXT:    br label [[DOTOMP_FINAL_DONE]]
22898 // CHECK21:       .omp.final.done:
22899 // CHECK21-NEXT:    ret void
22900 //
22901 //
22902 // CHECK22-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97
22903 // CHECK22-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] {
22904 // CHECK22-NEXT:  entry:
22905 // CHECK22-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
22906 // CHECK22-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
22907 // CHECK22-NEXT:    [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8
22908 // CHECK22-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
22909 // CHECK22-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]])
22910 // CHECK22-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
22911 // CHECK22-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
22912 // CHECK22-NEXT:    store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8
22913 // CHECK22-NEXT:    [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
22914 // CHECK22-NEXT:    [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
22915 // CHECK22-NEXT:    [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32*
22916 // CHECK22-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 4
22917 // CHECK22-NEXT:    [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 4
22918 // CHECK22-NEXT:    call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
22919 // CHECK22-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
22920 // CHECK22-NEXT:    [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
22921 // CHECK22-NEXT:    store i16 [[TMP3]], i16* [[CONV5]], align 2
22922 // CHECK22-NEXT:    [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
22923 // CHECK22-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]])
22924 // CHECK22-NEXT:    ret void
22925 //
22926 //
22927 // CHECK22-LABEL: define {{[^@]+}}@.omp_outlined.
22928 // CHECK22-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR1:[0-9]+]] {
22929 // CHECK22-NEXT:  entry:
22930 // CHECK22-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
22931 // CHECK22-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
22932 // CHECK22-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
22933 // CHECK22-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
22934 // CHECK22-NEXT:    [[TMP:%.*]] = alloca i32, align 4
22935 // CHECK22-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
22936 // CHECK22-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
22937 // CHECK22-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
22938 // CHECK22-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
22939 // CHECK22-NEXT:    [[I:%.*]] = alloca i32, align 4
22940 // CHECK22-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
22941 // CHECK22-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
22942 // CHECK22-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
22943 // CHECK22-NEXT:    [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
22944 // CHECK22-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
22945 // CHECK22-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
22946 // CHECK22-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
22947 // CHECK22-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
22948 // CHECK22-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
22949 // CHECK22-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
22950 // CHECK22-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
22951 // CHECK22-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
22952 // CHECK22-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
22953 // CHECK22-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
22954 // CHECK22:       cond.true:
22955 // CHECK22-NEXT:    br label [[COND_END:%.*]]
22956 // CHECK22:       cond.false:
22957 // CHECK22-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
22958 // CHECK22-NEXT:    br label [[COND_END]]
22959 // CHECK22:       cond.end:
22960 // CHECK22-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
22961 // CHECK22-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
22962 // CHECK22-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
22963 // CHECK22-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
22964 // CHECK22-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
22965 // CHECK22:       omp.inner.for.cond:
22966 // CHECK22-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
22967 // CHECK22-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !11
22968 // CHECK22-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
22969 // CHECK22-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
22970 // CHECK22:       omp.inner.for.body:
22971 // CHECK22-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
22972 // CHECK22-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
22973 // CHECK22-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
22974 // CHECK22-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11
22975 // CHECK22-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
22976 // CHECK22:       omp.body.continue:
22977 // CHECK22-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
22978 // CHECK22:       omp.inner.for.inc:
22979 // CHECK22-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
22980 // CHECK22-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
22981 // CHECK22-NEXT:    store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
22982 // CHECK22-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]
22983 // CHECK22:       omp.inner.for.end:
22984 // CHECK22-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
22985 // CHECK22:       omp.loop.exit:
22986 // CHECK22-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
22987 // CHECK22-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
22988 // CHECK22-NEXT:    [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0
22989 // CHECK22-NEXT:    br i1 [[TMP10]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
22990 // CHECK22:       .omp.final.then:
22991 // CHECK22-NEXT:    store i32 10, i32* [[I]], align 4
22992 // CHECK22-NEXT:    br label [[DOTOMP_FINAL_DONE]]
22993 // CHECK22:       .omp.final.done:
22994 // CHECK22-NEXT:    ret void
22995 //
22996 //
22997 // CHECK22-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111
22998 // CHECK22-SAME: (i64 noundef [[AA:%.*]]) #[[ATTR0]] {
22999 // CHECK22-NEXT:  entry:
23000 // CHECK22-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
23001 // CHECK22-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
23002 // CHECK22-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
23003 // CHECK22-NEXT:    [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
23004 // CHECK22-NEXT:    [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
23005 // CHECK22-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
23006 // CHECK22-NEXT:    store i16 [[TMP0]], i16* [[CONV1]], align 2
23007 // CHECK22-NEXT:    [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
23008 // CHECK22-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]])
23009 // CHECK22-NEXT:    ret void
23010 //
23011 //
23012 // CHECK22-LABEL: define {{[^@]+}}@.omp_outlined..1
23013 // CHECK22-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR1]] {
23014 // CHECK22-NEXT:  entry:
23015 // CHECK22-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
23016 // CHECK22-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
23017 // CHECK22-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
23018 // CHECK22-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
23019 // CHECK22-NEXT:    [[TMP:%.*]] = alloca i32, align 4
23020 // CHECK22-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
23021 // CHECK22-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
23022 // CHECK22-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
23023 // CHECK22-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
23024 // CHECK22-NEXT:    [[I:%.*]] = alloca i32, align 4
23025 // CHECK22-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
23026 // CHECK22-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
23027 // CHECK22-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
23028 // CHECK22-NEXT:    [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
23029 // CHECK22-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
23030 // CHECK22-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
23031 // CHECK22-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
23032 // CHECK22-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
23033 // CHECK22-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
23034 // CHECK22-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
23035 // CHECK22-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
23036 // CHECK22-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
23037 // CHECK22-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
23038 // CHECK22-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
23039 // CHECK22:       cond.true:
23040 // CHECK22-NEXT:    br label [[COND_END:%.*]]
23041 // CHECK22:       cond.false:
23042 // CHECK22-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
23043 // CHECK22-NEXT:    br label [[COND_END]]
23044 // CHECK22:       cond.end:
23045 // CHECK22-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
23046 // CHECK22-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
23047 // CHECK22-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
23048 // CHECK22-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
23049 // CHECK22-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
23050 // CHECK22:       omp.inner.for.cond:
23051 // CHECK22-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
23052 // CHECK22-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !18
23053 // CHECK22-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
23054 // CHECK22-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
23055 // CHECK22:       omp.inner.for.body:
23056 // CHECK22-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
23057 // CHECK22-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
23058 // CHECK22-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
23059 // CHECK22-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18
23060 // CHECK22-NEXT:    [[TMP8:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !18
23061 // CHECK22-NEXT:    [[CONV2:%.*]] = sext i16 [[TMP8]] to i32
23062 // CHECK22-NEXT:    [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
23063 // CHECK22-NEXT:    [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
23064 // CHECK22-NEXT:    store i16 [[CONV4]], i16* [[CONV]], align 2, !llvm.access.group !18
23065 // CHECK22-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
23066 // CHECK22:       omp.body.continue:
23067 // CHECK22-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
23068 // CHECK22:       omp.inner.for.inc:
23069 // CHECK22-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
23070 // CHECK22-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP9]], 1
23071 // CHECK22-NEXT:    store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
23072 // CHECK22-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]
23073 // CHECK22:       omp.inner.for.end:
23074 // CHECK22-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
23075 // CHECK22:       omp.loop.exit:
23076 // CHECK22-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
23077 // CHECK22-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
23078 // CHECK22-NEXT:    [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0
23079 // CHECK22-NEXT:    br i1 [[TMP11]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
23080 // CHECK22:       .omp.final.then:
23081 // CHECK22-NEXT:    store i32 10, i32* [[I]], align 4
23082 // CHECK22-NEXT:    br label [[DOTOMP_FINAL_DONE]]
23083 // CHECK22:       .omp.final.done:
23084 // CHECK22-NEXT:    ret void
23085 //
23086 //
23087 // CHECK22-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118
23088 // CHECK22-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] {
23089 // CHECK22-NEXT:  entry:
23090 // CHECK22-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
23091 // CHECK22-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
23092 // CHECK22-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
23093 // CHECK22-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
23094 // CHECK22-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
23095 // CHECK22-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
23096 // CHECK22-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
23097 // CHECK22-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
23098 // CHECK22-NEXT:    [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
23099 // CHECK22-NEXT:    [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
23100 // CHECK22-NEXT:    store i32 [[TMP0]], i32* [[CONV2]], align 4
23101 // CHECK22-NEXT:    [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
23102 // CHECK22-NEXT:    [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
23103 // CHECK22-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
23104 // CHECK22-NEXT:    store i16 [[TMP2]], i16* [[CONV3]], align 2
23105 // CHECK22-NEXT:    [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
23106 // CHECK22-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
23107 // CHECK22-NEXT:    ret void
23108 //
23109 //
23110 // CHECK22-LABEL: define {{[^@]+}}@.omp_outlined..2
23111 // CHECK22-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR1]] {
23112 // CHECK22-NEXT:  entry:
23113 // CHECK22-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
23114 // CHECK22-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
23115 // CHECK22-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
23116 // CHECK22-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
23117 // CHECK22-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
23118 // CHECK22-NEXT:    [[TMP:%.*]] = alloca i32, align 4
23119 // CHECK22-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
23120 // CHECK22-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
23121 // CHECK22-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
23122 // CHECK22-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
23123 // CHECK22-NEXT:    [[I:%.*]] = alloca i32, align 4
23124 // CHECK22-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
23125 // CHECK22-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
23126 // CHECK22-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
23127 // CHECK22-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
23128 // CHECK22-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
23129 // CHECK22-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
23130 // CHECK22-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
23131 // CHECK22-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
23132 // CHECK22-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
23133 // CHECK22-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
23134 // CHECK22-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
23135 // CHECK22-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
23136 // CHECK22-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
23137 // CHECK22-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
23138 // CHECK22-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
23139 // CHECK22-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
23140 // CHECK22:       cond.true:
23141 // CHECK22-NEXT:    br label [[COND_END:%.*]]
23142 // CHECK22:       cond.false:
23143 // CHECK22-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
23144 // CHECK22-NEXT:    br label [[COND_END]]
23145 // CHECK22:       cond.end:
23146 // CHECK22-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
23147 // CHECK22-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
23148 // CHECK22-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
23149 // CHECK22-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
23150 // CHECK22-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
23151 // CHECK22:       omp.inner.for.cond:
23152 // CHECK22-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
23153 // CHECK22-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !21
23154 // CHECK22-NEXT:    [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
23155 // CHECK22-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
23156 // CHECK22:       omp.inner.for.body:
23157 // CHECK22-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
23158 // CHECK22-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
23159 // CHECK22-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
23160 // CHECK22-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !21
23161 // CHECK22-NEXT:    [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !21
23162 // CHECK22-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
23163 // CHECK22-NEXT:    store i32 [[ADD3]], i32* [[CONV]], align 4, !llvm.access.group !21
23164 // CHECK22-NEXT:    [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 2, !llvm.access.group !21
23165 // CHECK22-NEXT:    [[CONV4:%.*]] = sext i16 [[TMP9]] to i32
23166 // CHECK22-NEXT:    [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
23167 // CHECK22-NEXT:    [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
23168 // CHECK22-NEXT:    store i16 [[CONV6]], i16* [[CONV1]], align 2, !llvm.access.group !21
23169 // CHECK22-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
23170 // CHECK22:       omp.body.continue:
23171 // CHECK22-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
23172 // CHECK22:       omp.inner.for.inc:
23173 // CHECK22-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
23174 // CHECK22-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1
23175 // CHECK22-NEXT:    store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
23176 // CHECK22-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]]
23177 // CHECK22:       omp.inner.for.end:
23178 // CHECK22-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
23179 // CHECK22:       omp.loop.exit:
23180 // CHECK22-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
23181 // CHECK22-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
23182 // CHECK22-NEXT:    [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
23183 // CHECK22-NEXT:    br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
23184 // CHECK22:       .omp.final.then:
23185 // CHECK22-NEXT:    store i32 10, i32* [[I]], align 4
23186 // CHECK22-NEXT:    br label [[DOTOMP_FINAL_DONE]]
23187 // CHECK22:       .omp.final.done:
23188 // CHECK22-NEXT:    ret void
23189 //
23190 //
23191 // CHECK22-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142
23192 // CHECK22-SAME: (i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] {
23193 // CHECK22-NEXT:  entry:
23194 // CHECK22-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
23195 // CHECK22-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
23196 // CHECK22-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
23197 // CHECK22-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 8
23198 // CHECK22-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
23199 // CHECK22-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
23200 // CHECK22-NEXT:    [[VLA_ADDR4:%.*]] = alloca i64, align 8
23201 // CHECK22-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 8
23202 // CHECK22-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
23203 // CHECK22-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
23204 // CHECK22-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
23205 // CHECK22-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
23206 // CHECK22-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
23207 // CHECK22-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 8
23208 // CHECK22-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
23209 // CHECK22-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
23210 // CHECK22-NEXT:    store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
23211 // CHECK22-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 8
23212 // CHECK22-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
23213 // CHECK22-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
23214 // CHECK22-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
23215 // CHECK22-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
23216 // CHECK22-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
23217 // CHECK22-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
23218 // CHECK22-NEXT:    [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
23219 // CHECK22-NEXT:    [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
23220 // CHECK22-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
23221 // CHECK22-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
23222 // CHECK22-NEXT:    [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
23223 // CHECK22-NEXT:    [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
23224 // CHECK22-NEXT:    store i32 [[TMP8]], i32* [[CONV5]], align 4
23225 // CHECK22-NEXT:    [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
23226 // CHECK22-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]])
23227 // CHECK22-NEXT:    ret void
23228 //
23229 //
23230 // CHECK22-LABEL: define {{[^@]+}}@.omp_outlined..3
23231 // CHECK22-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR1]] {
23232 // CHECK22-NEXT:  entry:
23233 // CHECK22-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
23234 // CHECK22-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
23235 // CHECK22-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
23236 // CHECK22-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
23237 // CHECK22-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
23238 // CHECK22-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 8
23239 // CHECK22-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
23240 // CHECK22-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
23241 // CHECK22-NEXT:    [[VLA_ADDR4:%.*]] = alloca i64, align 8
23242 // CHECK22-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 8
23243 // CHECK22-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
23244 // CHECK22-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
23245 // CHECK22-NEXT:    [[TMP:%.*]] = alloca i32, align 4
23246 // CHECK22-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
23247 // CHECK22-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
23248 // CHECK22-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
23249 // CHECK22-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
23250 // CHECK22-NEXT:    [[I:%.*]] = alloca i32, align 4
23251 // CHECK22-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
23252 // CHECK22-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
23253 // CHECK22-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
23254 // CHECK22-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
23255 // CHECK22-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
23256 // CHECK22-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 8
23257 // CHECK22-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
23258 // CHECK22-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
23259 // CHECK22-NEXT:    store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
23260 // CHECK22-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 8
23261 // CHECK22-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
23262 // CHECK22-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
23263 // CHECK22-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
23264 // CHECK22-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
23265 // CHECK22-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
23266 // CHECK22-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
23267 // CHECK22-NEXT:    [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
23268 // CHECK22-NEXT:    [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
23269 // CHECK22-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
23270 // CHECK22-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
23271 // CHECK22-NEXT:    [[ARRAYDECAY:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 0
23272 // CHECK22-NEXT:    call void @llvm.assume(i1 true) [ "align"(float* [[ARRAYDECAY]], i64 16) ]
23273 // CHECK22-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
23274 // CHECK22-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
23275 // CHECK22-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
23276 // CHECK22-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
23277 // CHECK22-NEXT:    [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
23278 // CHECK22-NEXT:    [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4
23279 // CHECK22-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
23280 // CHECK22-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
23281 // CHECK22-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP10]], 9
23282 // CHECK22-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
23283 // CHECK22:       cond.true:
23284 // CHECK22-NEXT:    br label [[COND_END:%.*]]
23285 // CHECK22:       cond.false:
23286 // CHECK22-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
23287 // CHECK22-NEXT:    br label [[COND_END]]
23288 // CHECK22:       cond.end:
23289 // CHECK22-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ]
23290 // CHECK22-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
23291 // CHECK22-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
23292 // CHECK22-NEXT:    store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4
23293 // CHECK22-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
23294 // CHECK22:       omp.inner.for.cond:
23295 // CHECK22-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
23296 // CHECK22-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !24
23297 // CHECK22-NEXT:    [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
23298 // CHECK22-NEXT:    br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
23299 // CHECK22:       omp.inner.for.body:
23300 // CHECK22-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
23301 // CHECK22-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1
23302 // CHECK22-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
23303 // CHECK22-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !24
23304 // CHECK22-NEXT:    [[TMP16:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !24
23305 // CHECK22-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP16]], 1
23306 // CHECK22-NEXT:    store i32 [[ADD6]], i32* [[CONV]], align 4, !llvm.access.group !24
23307 // CHECK22-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
23308 // CHECK22-NEXT:    [[TMP17:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !24
23309 // CHECK22-NEXT:    [[CONV7:%.*]] = fpext float [[TMP17]] to double
23310 // CHECK22-NEXT:    [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00
23311 // CHECK22-NEXT:    [[CONV9:%.*]] = fptrunc double [[ADD8]] to float
23312 // CHECK22-NEXT:    store float [[CONV9]], float* [[ARRAYIDX]], align 4, !llvm.access.group !24
23313 // CHECK22-NEXT:    [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3
23314 // CHECK22-NEXT:    [[TMP18:%.*]] = load float, float* [[ARRAYIDX10]], align 4, !llvm.access.group !24
23315 // CHECK22-NEXT:    [[CONV11:%.*]] = fpext float [[TMP18]] to double
23316 // CHECK22-NEXT:    [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00
23317 // CHECK22-NEXT:    [[CONV13:%.*]] = fptrunc double [[ADD12]] to float
23318 // CHECK22-NEXT:    store float [[CONV13]], float* [[ARRAYIDX10]], align 4, !llvm.access.group !24
23319 // CHECK22-NEXT:    [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1
23320 // CHECK22-NEXT:    [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX14]], i64 0, i64 2
23321 // CHECK22-NEXT:    [[TMP19:%.*]] = load double, double* [[ARRAYIDX15]], align 8, !llvm.access.group !24
23322 // CHECK22-NEXT:    [[ADD16:%.*]] = fadd double [[TMP19]], 1.000000e+00
23323 // CHECK22-NEXT:    store double [[ADD16]], double* [[ARRAYIDX15]], align 8, !llvm.access.group !24
23324 // CHECK22-NEXT:    [[TMP20:%.*]] = mul nsw i64 1, [[TMP5]]
23325 // CHECK22-NEXT:    [[ARRAYIDX17:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP20]]
23326 // CHECK22-NEXT:    [[ARRAYIDX18:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX17]], i64 3
23327 // CHECK22-NEXT:    [[TMP21:%.*]] = load double, double* [[ARRAYIDX18]], align 8, !llvm.access.group !24
23328 // CHECK22-NEXT:    [[ADD19:%.*]] = fadd double [[TMP21]], 1.000000e+00
23329 // CHECK22-NEXT:    store double [[ADD19]], double* [[ARRAYIDX18]], align 8, !llvm.access.group !24
23330 // CHECK22-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0
23331 // CHECK22-NEXT:    [[TMP22:%.*]] = load i64, i64* [[X]], align 8, !llvm.access.group !24
23332 // CHECK22-NEXT:    [[ADD20:%.*]] = add nsw i64 [[TMP22]], 1
23333 // CHECK22-NEXT:    store i64 [[ADD20]], i64* [[X]], align 8, !llvm.access.group !24
23334 // CHECK22-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1
23335 // CHECK22-NEXT:    [[TMP23:%.*]] = load i8, i8* [[Y]], align 8, !llvm.access.group !24
23336 // CHECK22-NEXT:    [[CONV21:%.*]] = sext i8 [[TMP23]] to i32
23337 // CHECK22-NEXT:    [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1
23338 // CHECK22-NEXT:    [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8
23339 // CHECK22-NEXT:    store i8 [[CONV23]], i8* [[Y]], align 8, !llvm.access.group !24
23340 // CHECK22-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
23341 // CHECK22:       omp.body.continue:
23342 // CHECK22-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
23343 // CHECK22:       omp.inner.for.inc:
23344 // CHECK22-NEXT:    [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
23345 // CHECK22-NEXT:    [[ADD24:%.*]] = add nsw i32 [[TMP24]], 1
23346 // CHECK22-NEXT:    store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
23347 // CHECK22-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]]
23348 // CHECK22:       omp.inner.for.end:
23349 // CHECK22-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
23350 // CHECK22:       omp.loop.exit:
23351 // CHECK22-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]])
23352 // CHECK22-NEXT:    [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
23353 // CHECK22-NEXT:    [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
23354 // CHECK22-NEXT:    br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
23355 // CHECK22:       .omp.final.then:
23356 // CHECK22-NEXT:    store i32 10, i32* [[I]], align 4
23357 // CHECK22-NEXT:    br label [[DOTOMP_FINAL_DONE]]
23358 // CHECK22:       .omp.final.done:
23359 // CHECK22-NEXT:    ret void
23360 //
23361 //
23362 // CHECK22-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197
23363 // CHECK22-SAME: (i64 noundef [[A:%.*]], i64 noundef [[N:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
23364 // CHECK22-NEXT:  entry:
23365 // CHECK22-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
23366 // CHECK22-NEXT:    [[N_ADDR:%.*]] = alloca i64, align 8
23367 // CHECK22-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
23368 // CHECK22-NEXT:    [[AAA_ADDR:%.*]] = alloca i64, align 8
23369 // CHECK22-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
23370 // CHECK22-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
23371 // CHECK22-NEXT:    [[N_CASTED:%.*]] = alloca i64, align 8
23372 // CHECK22-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
23373 // CHECK22-NEXT:    [[AAA_CASTED:%.*]] = alloca i64, align 8
23374 // CHECK22-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
23375 // CHECK22-NEXT:    store i64 [[N]], i64* [[N_ADDR]], align 8
23376 // CHECK22-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
23377 // CHECK22-NEXT:    store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
23378 // CHECK22-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
23379 // CHECK22-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
23380 // CHECK22-NEXT:    [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32*
23381 // CHECK22-NEXT:    [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
23382 // CHECK22-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
23383 // CHECK22-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
23384 // CHECK22-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
23385 // CHECK22-NEXT:    [[CONV4:%.*]] = bitcast i64* [[A_CASTED]] to i32*
23386 // CHECK22-NEXT:    store i32 [[TMP1]], i32* [[CONV4]], align 4
23387 // CHECK22-NEXT:    [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
23388 // CHECK22-NEXT:    [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 4
23389 // CHECK22-NEXT:    [[CONV5:%.*]] = bitcast i64* [[N_CASTED]] to i32*
23390 // CHECK22-NEXT:    store i32 [[TMP3]], i32* [[CONV5]], align 4
23391 // CHECK22-NEXT:    [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8
23392 // CHECK22-NEXT:    [[TMP5:%.*]] = load i16, i16* [[CONV2]], align 2
23393 // CHECK22-NEXT:    [[CONV6:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
23394 // CHECK22-NEXT:    store i16 [[TMP5]], i16* [[CONV6]], align 2
23395 // CHECK22-NEXT:    [[TMP6:%.*]] = load i64, i64* [[AA_CASTED]], align 8
23396 // CHECK22-NEXT:    [[TMP7:%.*]] = load i8, i8* [[CONV3]], align 1
23397 // CHECK22-NEXT:    [[CONV7:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
23398 // CHECK22-NEXT:    store i8 [[TMP7]], i8* [[CONV7]], align 1
23399 // CHECK22-NEXT:    [[TMP8:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
23400 // CHECK22-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]], [10 x i32]* [[TMP0]])
23401 // CHECK22-NEXT:    ret void
23402 //
23403 //
23404 // CHECK22-LABEL: define {{[^@]+}}@.omp_outlined..4
23405 // CHECK22-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[N:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {
23406 // CHECK22-NEXT:  entry:
23407 // CHECK22-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
23408 // CHECK22-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
23409 // CHECK22-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
23410 // CHECK22-NEXT:    [[N_ADDR:%.*]] = alloca i64, align 8
23411 // CHECK22-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
23412 // CHECK22-NEXT:    [[AAA_ADDR:%.*]] = alloca i64, align 8
23413 // CHECK22-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
23414 // CHECK22-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
23415 // CHECK22-NEXT:    [[TMP:%.*]] = alloca i32, align 4
23416 // CHECK22-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
23417 // CHECK22-NEXT:    [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4
23418 // CHECK22-NEXT:    [[DOTCAPTURE_EXPR_5:%.*]] = alloca i32, align 4
23419 // CHECK22-NEXT:    [[I:%.*]] = alloca i32, align 4
23420 // CHECK22-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
23421 // CHECK22-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
23422 // CHECK22-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
23423 // CHECK22-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
23424 // CHECK22-NEXT:    [[I8:%.*]] = alloca i32, align 4
23425 // CHECK22-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
23426 // CHECK22-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
23427 // CHECK22-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
23428 // CHECK22-NEXT:    store i64 [[N]], i64* [[N_ADDR]], align 8
23429 // CHECK22-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
23430 // CHECK22-NEXT:    store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
23431 // CHECK22-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
23432 // CHECK22-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
23433 // CHECK22-NEXT:    [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32*
23434 // CHECK22-NEXT:    [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
23435 // CHECK22-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
23436 // CHECK22-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
23437 // CHECK22-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
23438 // CHECK22-NEXT:    store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
23439 // CHECK22-NEXT:    [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4
23440 // CHECK22-NEXT:    store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_4]], align 4
23441 // CHECK22-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4
23442 // CHECK22-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
23443 // CHECK22-NEXT:    [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]]
23444 // CHECK22-NEXT:    [[SUB6:%.*]] = sub i32 [[SUB]], 1
23445 // CHECK22-NEXT:    [[ADD:%.*]] = add i32 [[SUB6]], 1
23446 // CHECK22-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], 1
23447 // CHECK22-NEXT:    [[SUB7:%.*]] = sub i32 [[DIV]], 1
23448 // CHECK22-NEXT:    store i32 [[SUB7]], i32* [[DOTCAPTURE_EXPR_5]], align 4
23449 // CHECK22-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
23450 // CHECK22-NEXT:    store i32 [[TMP5]], i32* [[I]], align 4
23451 // CHECK22-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
23452 // CHECK22-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4
23453 // CHECK22-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]]
23454 // CHECK22-NEXT:    br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
23455 // CHECK22:       omp.precond.then:
23456 // CHECK22-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
23457 // CHECK22-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4
23458 // CHECK22-NEXT:    store i32 [[TMP8]], i32* [[DOTOMP_UB]], align 4
23459 // CHECK22-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
23460 // CHECK22-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
23461 // CHECK22-NEXT:    [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
23462 // CHECK22-NEXT:    [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
23463 // CHECK22-NEXT:    call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
23464 // CHECK22-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
23465 // CHECK22-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4
23466 // CHECK22-NEXT:    [[CMP9:%.*]] = icmp ugt i32 [[TMP11]], [[TMP12]]
23467 // CHECK22-NEXT:    br i1 [[CMP9]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
23468 // CHECK22:       cond.true:
23469 // CHECK22-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4
23470 // CHECK22-NEXT:    br label [[COND_END:%.*]]
23471 // CHECK22:       cond.false:
23472 // CHECK22-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
23473 // CHECK22-NEXT:    br label [[COND_END]]
23474 // CHECK22:       cond.end:
23475 // CHECK22-NEXT:    [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ]
23476 // CHECK22-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
23477 // CHECK22-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
23478 // CHECK22-NEXT:    store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4
23479 // CHECK22-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
23480 // CHECK22:       omp.inner.for.cond:
23481 // CHECK22-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27
23482 // CHECK22-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !27
23483 // CHECK22-NEXT:    [[ADD10:%.*]] = add i32 [[TMP17]], 1
23484 // CHECK22-NEXT:    [[CMP11:%.*]] = icmp ult i32 [[TMP16]], [[ADD10]]
23485 // CHECK22-NEXT:    br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
23486 // CHECK22:       omp.inner.for.body:
23487 // CHECK22-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group !27
23488 // CHECK22-NEXT:    [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27
23489 // CHECK22-NEXT:    [[MUL:%.*]] = mul i32 [[TMP19]], 1
23490 // CHECK22-NEXT:    [[ADD12:%.*]] = add i32 [[TMP18]], [[MUL]]
23491 // CHECK22-NEXT:    store i32 [[ADD12]], i32* [[I8]], align 4, !llvm.access.group !27
23492 // CHECK22-NEXT:    [[TMP20:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !27
23493 // CHECK22-NEXT:    [[ADD13:%.*]] = add nsw i32 [[TMP20]], 1
23494 // CHECK22-NEXT:    store i32 [[ADD13]], i32* [[CONV]], align 4, !llvm.access.group !27
23495 // CHECK22-NEXT:    [[TMP21:%.*]] = load i16, i16* [[CONV2]], align 2, !llvm.access.group !27
23496 // CHECK22-NEXT:    [[CONV14:%.*]] = sext i16 [[TMP21]] to i32
23497 // CHECK22-NEXT:    [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1
23498 // CHECK22-NEXT:    [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16
23499 // CHECK22-NEXT:    store i16 [[CONV16]], i16* [[CONV2]], align 2, !llvm.access.group !27
23500 // CHECK22-NEXT:    [[TMP22:%.*]] = load i8, i8* [[CONV3]], align 1, !llvm.access.group !27
23501 // CHECK22-NEXT:    [[CONV17:%.*]] = sext i8 [[TMP22]] to i32
23502 // CHECK22-NEXT:    [[ADD18:%.*]] = add nsw i32 [[CONV17]], 1
23503 // CHECK22-NEXT:    [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8
23504 // CHECK22-NEXT:    store i8 [[CONV19]], i8* [[CONV3]], align 1, !llvm.access.group !27
23505 // CHECK22-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
23506 // CHECK22-NEXT:    [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !27
23507 // CHECK22-NEXT:    [[ADD20:%.*]] = add nsw i32 [[TMP23]], 1
23508 // CHECK22-NEXT:    store i32 [[ADD20]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !27
23509 // CHECK22-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
23510 // CHECK22:       omp.body.continue:
23511 // CHECK22-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
23512 // CHECK22:       omp.inner.for.inc:
23513 // CHECK22-NEXT:    [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27
23514 // CHECK22-NEXT:    [[ADD21:%.*]] = add i32 [[TMP24]], 1
23515 // CHECK22-NEXT:    store i32 [[ADD21]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27
23516 // CHECK22-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]]
23517 // CHECK22:       omp.inner.for.end:
23518 // CHECK22-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
23519 // CHECK22:       omp.loop.exit:
23520 // CHECK22-NEXT:    [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
23521 // CHECK22-NEXT:    [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4
23522 // CHECK22-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]])
23523 // CHECK22-NEXT:    [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
23524 // CHECK22-NEXT:    [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0
23525 // CHECK22-NEXT:    br i1 [[TMP28]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
23526 // CHECK22:       .omp.final.then:
23527 // CHECK22-NEXT:    [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
23528 // CHECK22-NEXT:    [[TMP30:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4
23529 // CHECK22-NEXT:    [[TMP31:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
23530 // CHECK22-NEXT:    [[SUB22:%.*]] = sub i32 [[TMP30]], [[TMP31]]
23531 // CHECK22-NEXT:    [[SUB23:%.*]] = sub i32 [[SUB22]], 1
23532 // CHECK22-NEXT:    [[ADD24:%.*]] = add i32 [[SUB23]], 1
23533 // CHECK22-NEXT:    [[DIV25:%.*]] = udiv i32 [[ADD24]], 1
23534 // CHECK22-NEXT:    [[MUL26:%.*]] = mul i32 [[DIV25]], 1
23535 // CHECK22-NEXT:    [[ADD27:%.*]] = add i32 [[TMP29]], [[MUL26]]
23536 // CHECK22-NEXT:    store i32 [[ADD27]], i32* [[I8]], align 4
23537 // CHECK22-NEXT:    br label [[DOTOMP_FINAL_DONE]]
23538 // CHECK22:       .omp.final.done:
23539 // CHECK22-NEXT:    br label [[OMP_PRECOND_END]]
23540 // CHECK22:       omp.precond.end:
23541 // CHECK22-NEXT:    ret void
23542 //
23543 //
23544 // CHECK22-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215
23545 // CHECK22-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
23546 // CHECK22-NEXT:  entry:
23547 // CHECK22-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
23548 // CHECK22-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
23549 // CHECK22-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
23550 // CHECK22-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
23551 // CHECK22-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 8
23552 // CHECK22-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
23553 // CHECK22-NEXT:    [[B_CASTED:%.*]] = alloca i64, align 8
23554 // CHECK22-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
23555 // CHECK22-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
23556 // CHECK22-NEXT:    store i64 [[B]], i64* [[B_ADDR]], align 8
23557 // CHECK22-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
23558 // CHECK22-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
23559 // CHECK22-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 8
23560 // CHECK22-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
23561 // CHECK22-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
23562 // CHECK22-NEXT:    [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
23563 // CHECK22-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
23564 // CHECK22-NEXT:    [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
23565 // CHECK22-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
23566 // CHECK22-NEXT:    [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
23567 // CHECK22-NEXT:    [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
23568 // CHECK22-NEXT:    [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i32*
23569 // CHECK22-NEXT:    store i32 [[TMP4]], i32* [[CONV4]], align 4
23570 // CHECK22-NEXT:    [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
23571 // CHECK22-NEXT:    [[TMP6:%.*]] = load i8, i8* [[CONV3]], align 1
23572 // CHECK22-NEXT:    [[TOBOOL:%.*]] = trunc i8 [[TMP6]] to i1
23573 // CHECK22-NEXT:    [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
23574 // CHECK22-NEXT:    [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
23575 // CHECK22-NEXT:    store i8 [[FROMBOOL]], i8* [[CONV5]], align 1
23576 // CHECK22-NEXT:    [[TMP7:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
23577 // CHECK22-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]], i64 [[TMP7]])
23578 // CHECK22-NEXT:    ret void
23579 //
23580 //
23581 // CHECK22-LABEL: define {{[^@]+}}@.omp_outlined..5
23582 // CHECK22-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
23583 // CHECK22-NEXT:  entry:
23584 // CHECK22-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
23585 // CHECK22-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
23586 // CHECK22-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
23587 // CHECK22-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
23588 // CHECK22-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
23589 // CHECK22-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
23590 // CHECK22-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 8
23591 // CHECK22-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
23592 // CHECK22-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
23593 // CHECK22-NEXT:    [[TMP:%.*]] = alloca i32, align 4
23594 // CHECK22-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
23595 // CHECK22-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
23596 // CHECK22-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
23597 // CHECK22-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
23598 // CHECK22-NEXT:    [[I:%.*]] = alloca i32, align 4
23599 // CHECK22-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
23600 // CHECK22-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
23601 // CHECK22-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
23602 // CHECK22-NEXT:    store i64 [[B]], i64* [[B_ADDR]], align 8
23603 // CHECK22-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
23604 // CHECK22-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
23605 // CHECK22-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 8
23606 // CHECK22-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
23607 // CHECK22-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
23608 // CHECK22-NEXT:    [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
23609 // CHECK22-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
23610 // CHECK22-NEXT:    [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
23611 // CHECK22-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
23612 // CHECK22-NEXT:    [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
23613 // CHECK22-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
23614 // CHECK22-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
23615 // CHECK22-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
23616 // CHECK22-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
23617 // CHECK22-NEXT:    [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
23618 // CHECK22-NEXT:    [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
23619 // CHECK22-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
23620 // CHECK22-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
23621 // CHECK22-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 9
23622 // CHECK22-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
23623 // CHECK22:       cond.true:
23624 // CHECK22-NEXT:    br label [[COND_END:%.*]]
23625 // CHECK22:       cond.false:
23626 // CHECK22-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
23627 // CHECK22-NEXT:    br label [[COND_END]]
23628 // CHECK22:       cond.end:
23629 // CHECK22-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
23630 // CHECK22-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
23631 // CHECK22-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
23632 // CHECK22-NEXT:    store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
23633 // CHECK22-NEXT:    [[TMP9:%.*]] = load i8, i8* [[CONV3]], align 1
23634 // CHECK22-NEXT:    [[TOBOOL:%.*]] = trunc i8 [[TMP9]] to i1
23635 // CHECK22-NEXT:    br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
23636 // CHECK22:       omp_if.then:
23637 // CHECK22-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
23638 // CHECK22:       omp.inner.for.cond:
23639 // CHECK22-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30
23640 // CHECK22-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !30
23641 // CHECK22-NEXT:    [[CMP4:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]
23642 // CHECK22-NEXT:    br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
23643 // CHECK22:       omp.inner.for.body:
23644 // CHECK22-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30
23645 // CHECK22-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1
23646 // CHECK22-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
23647 // CHECK22-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !30
23648 // CHECK22-NEXT:    [[TMP13:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !30
23649 // CHECK22-NEXT:    [[CONV5:%.*]] = sitofp i32 [[TMP13]] to double
23650 // CHECK22-NEXT:    [[ADD6:%.*]] = fadd double [[CONV5]], 1.500000e+00
23651 // CHECK22-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
23652 // CHECK22-NEXT:    store double [[ADD6]], double* [[A]], align 8, !llvm.access.group !30
23653 // CHECK22-NEXT:    [[A7:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
23654 // CHECK22-NEXT:    [[TMP14:%.*]] = load double, double* [[A7]], align 8, !llvm.access.group !30
23655 // CHECK22-NEXT:    [[INC:%.*]] = fadd double [[TMP14]], 1.000000e+00
23656 // CHECK22-NEXT:    store double [[INC]], double* [[A7]], align 8, !llvm.access.group !30
23657 // CHECK22-NEXT:    [[CONV8:%.*]] = fptosi double [[INC]] to i16
23658 // CHECK22-NEXT:    [[TMP15:%.*]] = mul nsw i64 1, [[TMP2]]
23659 // CHECK22-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP15]]
23660 // CHECK22-NEXT:    [[ARRAYIDX9:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
23661 // CHECK22-NEXT:    store i16 [[CONV8]], i16* [[ARRAYIDX9]], align 2, !llvm.access.group !30
23662 // CHECK22-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
23663 // CHECK22:       omp.body.continue:
23664 // CHECK22-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
23665 // CHECK22:       omp.inner.for.inc:
23666 // CHECK22-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30
23667 // CHECK22-NEXT:    [[ADD10:%.*]] = add nsw i32 [[TMP16]], 1
23668 // CHECK22-NEXT:    store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30
23669 // CHECK22-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP31:![0-9]+]]
23670 // CHECK22:       omp.inner.for.end:
23671 // CHECK22-NEXT:    br label [[OMP_IF_END:%.*]]
23672 // CHECK22:       omp_if.else:
23673 // CHECK22-NEXT:    br label [[OMP_INNER_FOR_COND11:%.*]]
23674 // CHECK22:       omp.inner.for.cond11:
23675 // CHECK22-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
23676 // CHECK22-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
23677 // CHECK22-NEXT:    [[CMP12:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]]
23678 // CHECK22-NEXT:    br i1 [[CMP12]], label [[OMP_INNER_FOR_BODY13:%.*]], label [[OMP_INNER_FOR_END27:%.*]]
23679 // CHECK22:       omp.inner.for.body13:
23680 // CHECK22-NEXT:    [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
23681 // CHECK22-NEXT:    [[MUL14:%.*]] = mul nsw i32 [[TMP19]], 1
23682 // CHECK22-NEXT:    [[ADD15:%.*]] = add nsw i32 0, [[MUL14]]
23683 // CHECK22-NEXT:    store i32 [[ADD15]], i32* [[I]], align 4
23684 // CHECK22-NEXT:    [[TMP20:%.*]] = load i32, i32* [[CONV]], align 4
23685 // CHECK22-NEXT:    [[CONV16:%.*]] = sitofp i32 [[TMP20]] to double
23686 // CHECK22-NEXT:    [[ADD17:%.*]] = fadd double [[CONV16]], 1.500000e+00
23687 // CHECK22-NEXT:    [[A18:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
23688 // CHECK22-NEXT:    store double [[ADD17]], double* [[A18]], align 8
23689 // CHECK22-NEXT:    [[A19:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
23690 // CHECK22-NEXT:    [[TMP21:%.*]] = load double, double* [[A19]], align 8
23691 // CHECK22-NEXT:    [[INC20:%.*]] = fadd double [[TMP21]], 1.000000e+00
23692 // CHECK22-NEXT:    store double [[INC20]], double* [[A19]], align 8
23693 // CHECK22-NEXT:    [[CONV21:%.*]] = fptosi double [[INC20]] to i16
23694 // CHECK22-NEXT:    [[TMP22:%.*]] = mul nsw i64 1, [[TMP2]]
23695 // CHECK22-NEXT:    [[ARRAYIDX22:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP22]]
23696 // CHECK22-NEXT:    [[ARRAYIDX23:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX22]], i64 1
23697 // CHECK22-NEXT:    store i16 [[CONV21]], i16* [[ARRAYIDX23]], align 2
23698 // CHECK22-NEXT:    br label [[OMP_BODY_CONTINUE24:%.*]]
23699 // CHECK22:       omp.body.continue24:
23700 // CHECK22-NEXT:    br label [[OMP_INNER_FOR_INC25:%.*]]
23701 // CHECK22:       omp.inner.for.inc25:
23702 // CHECK22-NEXT:    [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
23703 // CHECK22-NEXT:    [[ADD26:%.*]] = add nsw i32 [[TMP23]], 1
23704 // CHECK22-NEXT:    store i32 [[ADD26]], i32* [[DOTOMP_IV]], align 4
23705 // CHECK22-NEXT:    br label [[OMP_INNER_FOR_COND11]], !llvm.loop [[LOOP33:![0-9]+]]
23706 // CHECK22:       omp.inner.for.end27:
23707 // CHECK22-NEXT:    br label [[OMP_IF_END]]
23708 // CHECK22:       omp_if.end:
23709 // CHECK22-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
23710 // CHECK22:       omp.loop.exit:
23711 // CHECK22-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
23712 // CHECK22-NEXT:    [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
23713 // CHECK22-NEXT:    [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0
23714 // CHECK22-NEXT:    br i1 [[TMP25]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
23715 // CHECK22:       .omp.final.then:
23716 // CHECK22-NEXT:    store i32 10, i32* [[I]], align 4
23717 // CHECK22-NEXT:    br label [[DOTOMP_FINAL_DONE]]
23718 // CHECK22:       .omp.final.done:
23719 // CHECK22-NEXT:    ret void
23720 //
23721 //
23722 // CHECK22-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180
23723 // CHECK22-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
23724 // CHECK22-NEXT:  entry:
23725 // CHECK22-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
23726 // CHECK22-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
23727 // CHECK22-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
23728 // CHECK22-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
23729 // CHECK22-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
23730 // CHECK22-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
23731 // CHECK22-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
23732 // CHECK22-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
23733 // CHECK22-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
23734 // CHECK22-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
23735 // CHECK22-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
23736 // CHECK22-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
23737 // CHECK22-NEXT:    [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
23738 // CHECK22-NEXT:    store i32 [[TMP1]], i32* [[CONV2]], align 4
23739 // CHECK22-NEXT:    [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
23740 // CHECK22-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
23741 // CHECK22-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
23742 // CHECK22-NEXT:    store i16 [[TMP3]], i16* [[CONV3]], align 2
23743 // CHECK22-NEXT:    [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
23744 // CHECK22-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]])
23745 // CHECK22-NEXT:    ret void
23746 //
23747 //
23748 // CHECK22-LABEL: define {{[^@]+}}@.omp_outlined..6
23749 // CHECK22-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {
23750 // CHECK22-NEXT:  entry:
23751 // CHECK22-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
23752 // CHECK22-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
23753 // CHECK22-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
23754 // CHECK22-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
23755 // CHECK22-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
23756 // CHECK22-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
23757 // CHECK22-NEXT:    [[TMP:%.*]] = alloca i32, align 4
23758 // CHECK22-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
23759 // CHECK22-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
23760 // CHECK22-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
23761 // CHECK22-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
23762 // CHECK22-NEXT:    [[I:%.*]] = alloca i32, align 4
23763 // CHECK22-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
23764 // CHECK22-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
23765 // CHECK22-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
23766 // CHECK22-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
23767 // CHECK22-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
23768 // CHECK22-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
23769 // CHECK22-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
23770 // CHECK22-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
23771 // CHECK22-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
23772 // CHECK22-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
23773 // CHECK22-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
23774 // CHECK22-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
23775 // CHECK22-NEXT:    [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
23776 // CHECK22-NEXT:    [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
23777 // CHECK22-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
23778 // CHECK22-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
23779 // CHECK22-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9
23780 // CHECK22-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
23781 // CHECK22:       cond.true:
23782 // CHECK22-NEXT:    br label [[COND_END:%.*]]
23783 // CHECK22:       cond.false:
23784 // CHECK22-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
23785 // CHECK22-NEXT:    br label [[COND_END]]
23786 // CHECK22:       cond.end:
23787 // CHECK22-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
23788 // CHECK22-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
23789 // CHECK22-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
23790 // CHECK22-NEXT:    store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
23791 // CHECK22-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
23792 // CHECK22:       omp.inner.for.cond:
23793 // CHECK22-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !35
23794 // CHECK22-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !35
23795 // CHECK22-NEXT:    [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
23796 // CHECK22-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
23797 // CHECK22:       omp.inner.for.body:
23798 // CHECK22-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !35
23799 // CHECK22-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
23800 // CHECK22-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
23801 // CHECK22-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !35
23802 // CHECK22-NEXT:    [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !35
23803 // CHECK22-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1
23804 // CHECK22-NEXT:    store i32 [[ADD3]], i32* [[CONV]], align 4, !llvm.access.group !35
23805 // CHECK22-NEXT:    [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 2, !llvm.access.group !35
23806 // CHECK22-NEXT:    [[CONV4:%.*]] = sext i16 [[TMP10]] to i32
23807 // CHECK22-NEXT:    [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
23808 // CHECK22-NEXT:    [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
23809 // CHECK22-NEXT:    store i16 [[CONV6]], i16* [[CONV1]], align 2, !llvm.access.group !35
23810 // CHECK22-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
23811 // CHECK22-NEXT:    [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !35
23812 // CHECK22-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1
23813 // CHECK22-NEXT:    store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !35
23814 // CHECK22-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
23815 // CHECK22:       omp.body.continue:
23816 // CHECK22-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
23817 // CHECK22:       omp.inner.for.inc:
23818 // CHECK22-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !35
23819 // CHECK22-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP12]], 1
23820 // CHECK22-NEXT:    store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !35
23821 // CHECK22-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP36:![0-9]+]]
23822 // CHECK22:       omp.inner.for.end:
23823 // CHECK22-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
23824 // CHECK22:       omp.loop.exit:
23825 // CHECK22-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
23826 // CHECK22-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
23827 // CHECK22-NEXT:    [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
23828 // CHECK22-NEXT:    br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
23829 // CHECK22:       .omp.final.then:
23830 // CHECK22-NEXT:    store i32 10, i32* [[I]], align 4
23831 // CHECK22-NEXT:    br label [[DOTOMP_FINAL_DONE]]
23832 // CHECK22:       .omp.final.done:
23833 // CHECK22-NEXT:    ret void
23834 //
23835 //
23836 // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97
23837 // CHECK23-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]], i32 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] {
23838 // CHECK23-NEXT:  entry:
23839 // CHECK23-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
23840 // CHECK23-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
23841 // CHECK23-NEXT:    [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4
23842 // CHECK23-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
23843 // CHECK23-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]])
23844 // CHECK23-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
23845 // CHECK23-NEXT:    store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
23846 // CHECK23-NEXT:    store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4
23847 // CHECK23-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
23848 // CHECK23-NEXT:    [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
23849 // CHECK23-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4
23850 // CHECK23-NEXT:    call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
23851 // CHECK23-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
23852 // CHECK23-NEXT:    [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
23853 // CHECK23-NEXT:    store i16 [[TMP3]], i16* [[CONV3]], align 2
23854 // CHECK23-NEXT:    [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
23855 // CHECK23-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]])
23856 // CHECK23-NEXT:    ret void
23857 //
23858 //
23859 // CHECK23-LABEL: define {{[^@]+}}@.omp_outlined.
23860 // CHECK23-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR1:[0-9]+]] {
23861 // CHECK23-NEXT:  entry:
23862 // CHECK23-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
23863 // CHECK23-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
23864 // CHECK23-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
23865 // CHECK23-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
23866 // CHECK23-NEXT:    [[TMP:%.*]] = alloca i32, align 4
23867 // CHECK23-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
23868 // CHECK23-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
23869 // CHECK23-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
23870 // CHECK23-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
23871 // CHECK23-NEXT:    [[I:%.*]] = alloca i32, align 4
23872 // CHECK23-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
23873 // CHECK23-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
23874 // CHECK23-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
23875 // CHECK23-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
23876 // CHECK23-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
23877 // CHECK23-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
23878 // CHECK23-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
23879 // CHECK23-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
23880 // CHECK23-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
23881 // CHECK23-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
23882 // CHECK23-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
23883 // CHECK23-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
23884 // CHECK23-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
23885 // CHECK23-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
23886 // CHECK23:       cond.true:
23887 // CHECK23-NEXT:    br label [[COND_END:%.*]]
23888 // CHECK23:       cond.false:
23889 // CHECK23-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
23890 // CHECK23-NEXT:    br label [[COND_END]]
23891 // CHECK23:       cond.end:
23892 // CHECK23-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
23893 // CHECK23-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
23894 // CHECK23-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
23895 // CHECK23-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
23896 // CHECK23-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
23897 // CHECK23:       omp.inner.for.cond:
23898 // CHECK23-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
23899 // CHECK23-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !12
23900 // CHECK23-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
23901 // CHECK23-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
23902 // CHECK23:       omp.inner.for.body:
23903 // CHECK23-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
23904 // CHECK23-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
23905 // CHECK23-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
23906 // CHECK23-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !12
23907 // CHECK23-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
23908 // CHECK23:       omp.body.continue:
23909 // CHECK23-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
23910 // CHECK23:       omp.inner.for.inc:
23911 // CHECK23-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
23912 // CHECK23-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
23913 // CHECK23-NEXT:    store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
23914 // CHECK23-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]
23915 // CHECK23:       omp.inner.for.end:
23916 // CHECK23-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
23917 // CHECK23:       omp.loop.exit:
23918 // CHECK23-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
23919 // CHECK23-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
23920 // CHECK23-NEXT:    [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0
23921 // CHECK23-NEXT:    br i1 [[TMP10]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
23922 // CHECK23:       .omp.final.then:
23923 // CHECK23-NEXT:    store i32 10, i32* [[I]], align 4
23924 // CHECK23-NEXT:    br label [[DOTOMP_FINAL_DONE]]
23925 // CHECK23:       .omp.final.done:
23926 // CHECK23-NEXT:    ret void
23927 //
23928 //
23929 // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111
23930 // CHECK23-SAME: (i32 noundef [[AA:%.*]]) #[[ATTR0]] {
23931 // CHECK23-NEXT:  entry:
23932 // CHECK23-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
23933 // CHECK23-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
23934 // CHECK23-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
23935 // CHECK23-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
23936 // CHECK23-NEXT:    [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
23937 // CHECK23-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
23938 // CHECK23-NEXT:    store i16 [[TMP0]], i16* [[CONV1]], align 2
23939 // CHECK23-NEXT:    [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
23940 // CHECK23-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]])
23941 // CHECK23-NEXT:    ret void
23942 //
23943 //
23944 // CHECK23-LABEL: define {{[^@]+}}@.omp_outlined..1
23945 // CHECK23-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR1]] {
23946 // CHECK23-NEXT:  entry:
23947 // CHECK23-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
23948 // CHECK23-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
23949 // CHECK23-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
23950 // CHECK23-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
23951 // CHECK23-NEXT:    [[TMP:%.*]] = alloca i32, align 4
23952 // CHECK23-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
23953 // CHECK23-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
23954 // CHECK23-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
23955 // CHECK23-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
23956 // CHECK23-NEXT:    [[I:%.*]] = alloca i32, align 4
23957 // CHECK23-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
23958 // CHECK23-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
23959 // CHECK23-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
23960 // CHECK23-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
23961 // CHECK23-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
23962 // CHECK23-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
23963 // CHECK23-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
23964 // CHECK23-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
23965 // CHECK23-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
23966 // CHECK23-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
23967 // CHECK23-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
23968 // CHECK23-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
23969 // CHECK23-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
23970 // CHECK23-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
23971 // CHECK23:       cond.true:
23972 // CHECK23-NEXT:    br label [[COND_END:%.*]]
23973 // CHECK23:       cond.false:
23974 // CHECK23-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
23975 // CHECK23-NEXT:    br label [[COND_END]]
23976 // CHECK23:       cond.end:
23977 // CHECK23-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
23978 // CHECK23-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
23979 // CHECK23-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
23980 // CHECK23-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
23981 // CHECK23-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
23982 // CHECK23:       omp.inner.for.cond:
23983 // CHECK23-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
23984 // CHECK23-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !19
23985 // CHECK23-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
23986 // CHECK23-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
23987 // CHECK23:       omp.inner.for.body:
23988 // CHECK23-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
23989 // CHECK23-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
23990 // CHECK23-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
23991 // CHECK23-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !19
23992 // CHECK23-NEXT:    [[TMP8:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !19
23993 // CHECK23-NEXT:    [[CONV2:%.*]] = sext i16 [[TMP8]] to i32
23994 // CHECK23-NEXT:    [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
23995 // CHECK23-NEXT:    [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
23996 // CHECK23-NEXT:    store i16 [[CONV4]], i16* [[CONV]], align 2, !llvm.access.group !19
23997 // CHECK23-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
23998 // CHECK23:       omp.body.continue:
23999 // CHECK23-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
24000 // CHECK23:       omp.inner.for.inc:
24001 // CHECK23-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
24002 // CHECK23-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP9]], 1
24003 // CHECK23-NEXT:    store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
24004 // CHECK23-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]]
24005 // CHECK23:       omp.inner.for.end:
24006 // CHECK23-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
24007 // CHECK23:       omp.loop.exit:
24008 // CHECK23-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
24009 // CHECK23-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
24010 // CHECK23-NEXT:    [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0
24011 // CHECK23-NEXT:    br i1 [[TMP11]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
24012 // CHECK23:       .omp.final.then:
24013 // CHECK23-NEXT:    store i32 10, i32* [[I]], align 4
24014 // CHECK23-NEXT:    br label [[DOTOMP_FINAL_DONE]]
24015 // CHECK23:       .omp.final.done:
24016 // CHECK23-NEXT:    ret void
24017 //
24018 //
24019 // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118
24020 // CHECK23-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] {
24021 // CHECK23-NEXT:  entry:
24022 // CHECK23-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
24023 // CHECK23-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
24024 // CHECK23-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
24025 // CHECK23-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
24026 // CHECK23-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
24027 // CHECK23-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
24028 // CHECK23-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
24029 // CHECK23-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
24030 // CHECK23-NEXT:    store i32 [[TMP0]], i32* [[A_CASTED]], align 4
24031 // CHECK23-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
24032 // CHECK23-NEXT:    [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
24033 // CHECK23-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
24034 // CHECK23-NEXT:    store i16 [[TMP2]], i16* [[CONV1]], align 2
24035 // CHECK23-NEXT:    [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
24036 // CHECK23-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]])
24037 // CHECK23-NEXT:    ret void
24038 //
24039 //
24040 // CHECK23-LABEL: define {{[^@]+}}@.omp_outlined..2
24041 // CHECK23-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR1]] {
24042 // CHECK23-NEXT:  entry:
24043 // CHECK23-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
24044 // CHECK23-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
24045 // CHECK23-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
24046 // CHECK23-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
24047 // CHECK23-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
24048 // CHECK23-NEXT:    [[TMP:%.*]] = alloca i32, align 4
24049 // CHECK23-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
24050 // CHECK23-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
24051 // CHECK23-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
24052 // CHECK23-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
24053 // CHECK23-NEXT:    [[I:%.*]] = alloca i32, align 4
24054 // CHECK23-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
24055 // CHECK23-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
24056 // CHECK23-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
24057 // CHECK23-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
24058 // CHECK23-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
24059 // CHECK23-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
24060 // CHECK23-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
24061 // CHECK23-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
24062 // CHECK23-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
24063 // CHECK23-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
24064 // CHECK23-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
24065 // CHECK23-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
24066 // CHECK23-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
24067 // CHECK23-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
24068 // CHECK23-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
24069 // CHECK23:       cond.true:
24070 // CHECK23-NEXT:    br label [[COND_END:%.*]]
24071 // CHECK23:       cond.false:
24072 // CHECK23-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
24073 // CHECK23-NEXT:    br label [[COND_END]]
24074 // CHECK23:       cond.end:
24075 // CHECK23-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
24076 // CHECK23-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
24077 // CHECK23-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
24078 // CHECK23-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
24079 // CHECK23-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
24080 // CHECK23:       omp.inner.for.cond:
24081 // CHECK23-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
24082 // CHECK23-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !22
24083 // CHECK23-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
24084 // CHECK23-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
24085 // CHECK23:       omp.inner.for.body:
24086 // CHECK23-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
24087 // CHECK23-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
24088 // CHECK23-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
24089 // CHECK23-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !22
24090 // CHECK23-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !22
24091 // CHECK23-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
24092 // CHECK23-NEXT:    store i32 [[ADD2]], i32* [[A_ADDR]], align 4, !llvm.access.group !22
24093 // CHECK23-NEXT:    [[TMP9:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !22
24094 // CHECK23-NEXT:    [[CONV3:%.*]] = sext i16 [[TMP9]] to i32
24095 // CHECK23-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
24096 // CHECK23-NEXT:    [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
24097 // CHECK23-NEXT:    store i16 [[CONV5]], i16* [[CONV]], align 2, !llvm.access.group !22
24098 // CHECK23-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
24099 // CHECK23:       omp.body.continue:
24100 // CHECK23-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
24101 // CHECK23:       omp.inner.for.inc:
24102 // CHECK23-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
24103 // CHECK23-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP10]], 1
24104 // CHECK23-NEXT:    store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
24105 // CHECK23-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]]
24106 // CHECK23:       omp.inner.for.end:
24107 // CHECK23-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
24108 // CHECK23:       omp.loop.exit:
24109 // CHECK23-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
24110 // CHECK23-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
24111 // CHECK23-NEXT:    [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
24112 // CHECK23-NEXT:    br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
24113 // CHECK23:       .omp.final.then:
24114 // CHECK23-NEXT:    store i32 10, i32* [[I]], align 4
24115 // CHECK23-NEXT:    br label [[DOTOMP_FINAL_DONE]]
24116 // CHECK23:       .omp.final.done:
24117 // CHECK23-NEXT:    ret void
24118 //
24119 //
24120 // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142
24121 // CHECK23-SAME: (i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] {
24122 // CHECK23-NEXT:  entry:
24123 // CHECK23-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
24124 // CHECK23-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
24125 // CHECK23-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
24126 // CHECK23-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 4
24127 // CHECK23-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
24128 // CHECK23-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
24129 // CHECK23-NEXT:    [[VLA_ADDR4:%.*]] = alloca i32, align 4
24130 // CHECK23-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 4
24131 // CHECK23-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
24132 // CHECK23-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
24133 // CHECK23-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
24134 // CHECK23-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
24135 // CHECK23-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
24136 // CHECK23-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 4
24137 // CHECK23-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
24138 // CHECK23-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
24139 // CHECK23-NEXT:    store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
24140 // CHECK23-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 4
24141 // CHECK23-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
24142 // CHECK23-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
24143 // CHECK23-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
24144 // CHECK23-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
24145 // CHECK23-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
24146 // CHECK23-NEXT:    [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
24147 // CHECK23-NEXT:    [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
24148 // CHECK23-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
24149 // CHECK23-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
24150 // CHECK23-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
24151 // CHECK23-NEXT:    store i32 [[TMP8]], i32* [[A_CASTED]], align 4
24152 // CHECK23-NEXT:    [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4
24153 // CHECK23-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]])
24154 // CHECK23-NEXT:    ret void
24155 //
24156 //
24157 // CHECK23-LABEL: define {{[^@]+}}@.omp_outlined..3
24158 // CHECK23-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR1]] {
24159 // CHECK23-NEXT:  entry:
24160 // CHECK23-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
24161 // CHECK23-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
24162 // CHECK23-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
24163 // CHECK23-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
24164 // CHECK23-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
24165 // CHECK23-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 4
24166 // CHECK23-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
24167 // CHECK23-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
24168 // CHECK23-NEXT:    [[VLA_ADDR4:%.*]] = alloca i32, align 4
24169 // CHECK23-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 4
24170 // CHECK23-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
24171 // CHECK23-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
24172 // CHECK23-NEXT:    [[TMP:%.*]] = alloca i32, align 4
24173 // CHECK23-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
24174 // CHECK23-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
24175 // CHECK23-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
24176 // CHECK23-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
24177 // CHECK23-NEXT:    [[I:%.*]] = alloca i32, align 4
24178 // CHECK23-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
24179 // CHECK23-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
24180 // CHECK23-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
24181 // CHECK23-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
24182 // CHECK23-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
24183 // CHECK23-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 4
24184 // CHECK23-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
24185 // CHECK23-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
24186 // CHECK23-NEXT:    store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
24187 // CHECK23-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 4
24188 // CHECK23-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
24189 // CHECK23-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
24190 // CHECK23-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
24191 // CHECK23-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
24192 // CHECK23-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
24193 // CHECK23-NEXT:    [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
24194 // CHECK23-NEXT:    [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
24195 // CHECK23-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
24196 // CHECK23-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
24197 // CHECK23-NEXT:    [[ARRAYDECAY:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 0
24198 // CHECK23-NEXT:    call void @llvm.assume(i1 true) [ "align"(float* [[ARRAYDECAY]], i32 16) ]
24199 // CHECK23-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
24200 // CHECK23-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
24201 // CHECK23-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
24202 // CHECK23-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
24203 // CHECK23-NEXT:    [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
24204 // CHECK23-NEXT:    [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4
24205 // CHECK23-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
24206 // CHECK23-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
24207 // CHECK23-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP10]], 9
24208 // CHECK23-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
24209 // CHECK23:       cond.true:
24210 // CHECK23-NEXT:    br label [[COND_END:%.*]]
24211 // CHECK23:       cond.false:
24212 // CHECK23-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
24213 // CHECK23-NEXT:    br label [[COND_END]]
24214 // CHECK23:       cond.end:
24215 // CHECK23-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ]
24216 // CHECK23-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
24217 // CHECK23-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
24218 // CHECK23-NEXT:    store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4
24219 // CHECK23-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
24220 // CHECK23:       omp.inner.for.cond:
24221 // CHECK23-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25
24222 // CHECK23-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !25
24223 // CHECK23-NEXT:    [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
24224 // CHECK23-NEXT:    br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
24225 // CHECK23:       omp.inner.for.body:
24226 // CHECK23-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25
24227 // CHECK23-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1
24228 // CHECK23-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
24229 // CHECK23-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !25
24230 // CHECK23-NEXT:    [[TMP16:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !25
24231 // CHECK23-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP16]], 1
24232 // CHECK23-NEXT:    store i32 [[ADD6]], i32* [[A_ADDR]], align 4, !llvm.access.group !25
24233 // CHECK23-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2
24234 // CHECK23-NEXT:    [[TMP17:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !25
24235 // CHECK23-NEXT:    [[CONV:%.*]] = fpext float [[TMP17]] to double
24236 // CHECK23-NEXT:    [[ADD7:%.*]] = fadd double [[CONV]], 1.000000e+00
24237 // CHECK23-NEXT:    [[CONV8:%.*]] = fptrunc double [[ADD7]] to float
24238 // CHECK23-NEXT:    store float [[CONV8]], float* [[ARRAYIDX]], align 4, !llvm.access.group !25
24239 // CHECK23-NEXT:    [[ARRAYIDX9:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3
24240 // CHECK23-NEXT:    [[TMP18:%.*]] = load float, float* [[ARRAYIDX9]], align 4, !llvm.access.group !25
24241 // CHECK23-NEXT:    [[CONV10:%.*]] = fpext float [[TMP18]] to double
24242 // CHECK23-NEXT:    [[ADD11:%.*]] = fadd double [[CONV10]], 1.000000e+00
24243 // CHECK23-NEXT:    [[CONV12:%.*]] = fptrunc double [[ADD11]] to float
24244 // CHECK23-NEXT:    store float [[CONV12]], float* [[ARRAYIDX9]], align 4, !llvm.access.group !25
24245 // CHECK23-NEXT:    [[ARRAYIDX13:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1
24246 // CHECK23-NEXT:    [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX13]], i32 0, i32 2
24247 // CHECK23-NEXT:    [[TMP19:%.*]] = load double, double* [[ARRAYIDX14]], align 8, !llvm.access.group !25
24248 // CHECK23-NEXT:    [[ADD15:%.*]] = fadd double [[TMP19]], 1.000000e+00
24249 // CHECK23-NEXT:    store double [[ADD15]], double* [[ARRAYIDX14]], align 8, !llvm.access.group !25
24250 // CHECK23-NEXT:    [[TMP20:%.*]] = mul nsw i32 1, [[TMP5]]
24251 // CHECK23-NEXT:    [[ARRAYIDX16:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP20]]
24252 // CHECK23-NEXT:    [[ARRAYIDX17:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX16]], i32 3
24253 // CHECK23-NEXT:    [[TMP21:%.*]] = load double, double* [[ARRAYIDX17]], align 8, !llvm.access.group !25
24254 // CHECK23-NEXT:    [[ADD18:%.*]] = fadd double [[TMP21]], 1.000000e+00
24255 // CHECK23-NEXT:    store double [[ADD18]], double* [[ARRAYIDX17]], align 8, !llvm.access.group !25
24256 // CHECK23-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0
24257 // CHECK23-NEXT:    [[TMP22:%.*]] = load i64, i64* [[X]], align 4, !llvm.access.group !25
24258 // CHECK23-NEXT:    [[ADD19:%.*]] = add nsw i64 [[TMP22]], 1
24259 // CHECK23-NEXT:    store i64 [[ADD19]], i64* [[X]], align 4, !llvm.access.group !25
24260 // CHECK23-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1
24261 // CHECK23-NEXT:    [[TMP23:%.*]] = load i8, i8* [[Y]], align 4, !llvm.access.group !25
24262 // CHECK23-NEXT:    [[CONV20:%.*]] = sext i8 [[TMP23]] to i32
24263 // CHECK23-NEXT:    [[ADD21:%.*]] = add nsw i32 [[CONV20]], 1
24264 // CHECK23-NEXT:    [[CONV22:%.*]] = trunc i32 [[ADD21]] to i8
24265 // CHECK23-NEXT:    store i8 [[CONV22]], i8* [[Y]], align 4, !llvm.access.group !25
24266 // CHECK23-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
24267 // CHECK23:       omp.body.continue:
24268 // CHECK23-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
24269 // CHECK23:       omp.inner.for.inc:
24270 // CHECK23-NEXT:    [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25
24271 // CHECK23-NEXT:    [[ADD23:%.*]] = add nsw i32 [[TMP24]], 1
24272 // CHECK23-NEXT:    store i32 [[ADD23]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25
24273 // CHECK23-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP26:![0-9]+]]
24274 // CHECK23:       omp.inner.for.end:
24275 // CHECK23-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
24276 // CHECK23:       omp.loop.exit:
24277 // CHECK23-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]])
24278 // CHECK23-NEXT:    [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
24279 // CHECK23-NEXT:    [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
24280 // CHECK23-NEXT:    br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
24281 // CHECK23:       .omp.final.then:
24282 // CHECK23-NEXT:    store i32 10, i32* [[I]], align 4
24283 // CHECK23-NEXT:    br label [[DOTOMP_FINAL_DONE]]
24284 // CHECK23:       .omp.final.done:
24285 // CHECK23-NEXT:    ret void
24286 //
24287 //
24288 // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197
24289 // CHECK23-SAME: (i32 noundef [[A:%.*]], i32 noundef [[N:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
24290 // CHECK23-NEXT:  entry:
24291 // CHECK23-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
24292 // CHECK23-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
24293 // CHECK23-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
24294 // CHECK23-NEXT:    [[AAA_ADDR:%.*]] = alloca i32, align 4
24295 // CHECK23-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
24296 // CHECK23-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
24297 // CHECK23-NEXT:    [[N_CASTED:%.*]] = alloca i32, align 4
24298 // CHECK23-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
24299 // CHECK23-NEXT:    [[AAA_CASTED:%.*]] = alloca i32, align 4
24300 // CHECK23-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
24301 // CHECK23-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
24302 // CHECK23-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
24303 // CHECK23-NEXT:    store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
24304 // CHECK23-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
24305 // CHECK23-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
24306 // CHECK23-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
24307 // CHECK23-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
24308 // CHECK23-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
24309 // CHECK23-NEXT:    store i32 [[TMP1]], i32* [[A_CASTED]], align 4
24310 // CHECK23-NEXT:    [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
24311 // CHECK23-NEXT:    [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
24312 // CHECK23-NEXT:    store i32 [[TMP3]], i32* [[N_CASTED]], align 4
24313 // CHECK23-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_CASTED]], align 4
24314 // CHECK23-NEXT:    [[TMP5:%.*]] = load i16, i16* [[CONV]], align 2
24315 // CHECK23-NEXT:    [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
24316 // CHECK23-NEXT:    store i16 [[TMP5]], i16* [[CONV2]], align 2
24317 // CHECK23-NEXT:    [[TMP6:%.*]] = load i32, i32* [[AA_CASTED]], align 4
24318 // CHECK23-NEXT:    [[TMP7:%.*]] = load i8, i8* [[CONV1]], align 1
24319 // CHECK23-NEXT:    [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
24320 // CHECK23-NEXT:    store i8 [[TMP7]], i8* [[CONV3]], align 1
24321 // CHECK23-NEXT:    [[TMP8:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
24322 // CHECK23-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP8]], [10 x i32]* [[TMP0]])
24323 // CHECK23-NEXT:    ret void
24324 //
24325 //
24326 // CHECK23-LABEL: define {{[^@]+}}@.omp_outlined..4
24327 // CHECK23-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[N:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {
24328 // CHECK23-NEXT:  entry:
24329 // CHECK23-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
24330 // CHECK23-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
24331 // CHECK23-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
24332 // CHECK23-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
24333 // CHECK23-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
24334 // CHECK23-NEXT:    [[AAA_ADDR:%.*]] = alloca i32, align 4
24335 // CHECK23-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
24336 // CHECK23-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
24337 // CHECK23-NEXT:    [[TMP:%.*]] = alloca i32, align 4
24338 // CHECK23-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
24339 // CHECK23-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
24340 // CHECK23-NEXT:    [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4
24341 // CHECK23-NEXT:    [[I:%.*]] = alloca i32, align 4
24342 // CHECK23-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
24343 // CHECK23-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
24344 // CHECK23-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
24345 // CHECK23-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
24346 // CHECK23-NEXT:    [[I6:%.*]] = alloca i32, align 4
24347 // CHECK23-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
24348 // CHECK23-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
24349 // CHECK23-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
24350 // CHECK23-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
24351 // CHECK23-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
24352 // CHECK23-NEXT:    store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
24353 // CHECK23-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
24354 // CHECK23-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
24355 // CHECK23-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
24356 // CHECK23-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
24357 // CHECK23-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
24358 // CHECK23-NEXT:    store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
24359 // CHECK23-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
24360 // CHECK23-NEXT:    store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4
24361 // CHECK23-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
24362 // CHECK23-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
24363 // CHECK23-NEXT:    [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]]
24364 // CHECK23-NEXT:    [[SUB4:%.*]] = sub i32 [[SUB]], 1
24365 // CHECK23-NEXT:    [[ADD:%.*]] = add i32 [[SUB4]], 1
24366 // CHECK23-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], 1
24367 // CHECK23-NEXT:    [[SUB5:%.*]] = sub i32 [[DIV]], 1
24368 // CHECK23-NEXT:    store i32 [[SUB5]], i32* [[DOTCAPTURE_EXPR_3]], align 4
24369 // CHECK23-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
24370 // CHECK23-NEXT:    store i32 [[TMP5]], i32* [[I]], align 4
24371 // CHECK23-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
24372 // CHECK23-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
24373 // CHECK23-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]]
24374 // CHECK23-NEXT:    br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
24375 // CHECK23:       omp.precond.then:
24376 // CHECK23-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
24377 // CHECK23-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
24378 // CHECK23-NEXT:    store i32 [[TMP8]], i32* [[DOTOMP_UB]], align 4
24379 // CHECK23-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
24380 // CHECK23-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
24381 // CHECK23-NEXT:    [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
24382 // CHECK23-NEXT:    [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
24383 // CHECK23-NEXT:    call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
24384 // CHECK23-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
24385 // CHECK23-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
24386 // CHECK23-NEXT:    [[CMP7:%.*]] = icmp ugt i32 [[TMP11]], [[TMP12]]
24387 // CHECK23-NEXT:    br i1 [[CMP7]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
24388 // CHECK23:       cond.true:
24389 // CHECK23-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
24390 // CHECK23-NEXT:    br label [[COND_END:%.*]]
24391 // CHECK23:       cond.false:
24392 // CHECK23-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
24393 // CHECK23-NEXT:    br label [[COND_END]]
24394 // CHECK23:       cond.end:
24395 // CHECK23-NEXT:    [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ]
24396 // CHECK23-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
24397 // CHECK23-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
24398 // CHECK23-NEXT:    store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4
24399 // CHECK23-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
24400 // CHECK23:       omp.inner.for.cond:
24401 // CHECK23-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28
24402 // CHECK23-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !28
24403 // CHECK23-NEXT:    [[ADD8:%.*]] = add i32 [[TMP17]], 1
24404 // CHECK23-NEXT:    [[CMP9:%.*]] = icmp ult i32 [[TMP16]], [[ADD8]]
24405 // CHECK23-NEXT:    br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
24406 // CHECK23:       omp.inner.for.body:
24407 // CHECK23-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group !28
24408 // CHECK23-NEXT:    [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28
24409 // CHECK23-NEXT:    [[MUL:%.*]] = mul i32 [[TMP19]], 1
24410 // CHECK23-NEXT:    [[ADD10:%.*]] = add i32 [[TMP18]], [[MUL]]
24411 // CHECK23-NEXT:    store i32 [[ADD10]], i32* [[I6]], align 4, !llvm.access.group !28
24412 // CHECK23-NEXT:    [[TMP20:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !28
24413 // CHECK23-NEXT:    [[ADD11:%.*]] = add nsw i32 [[TMP20]], 1
24414 // CHECK23-NEXT:    store i32 [[ADD11]], i32* [[A_ADDR]], align 4, !llvm.access.group !28
24415 // CHECK23-NEXT:    [[TMP21:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !28
24416 // CHECK23-NEXT:    [[CONV12:%.*]] = sext i16 [[TMP21]] to i32
24417 // CHECK23-NEXT:    [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1
24418 // CHECK23-NEXT:    [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16
24419 // CHECK23-NEXT:    store i16 [[CONV14]], i16* [[CONV]], align 2, !llvm.access.group !28
24420 // CHECK23-NEXT:    [[TMP22:%.*]] = load i8, i8* [[CONV1]], align 1, !llvm.access.group !28
24421 // CHECK23-NEXT:    [[CONV15:%.*]] = sext i8 [[TMP22]] to i32
24422 // CHECK23-NEXT:    [[ADD16:%.*]] = add nsw i32 [[CONV15]], 1
24423 // CHECK23-NEXT:    [[CONV17:%.*]] = trunc i32 [[ADD16]] to i8
24424 // CHECK23-NEXT:    store i8 [[CONV17]], i8* [[CONV1]], align 1, !llvm.access.group !28
24425 // CHECK23-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
24426 // CHECK23-NEXT:    [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !28
24427 // CHECK23-NEXT:    [[ADD18:%.*]] = add nsw i32 [[TMP23]], 1
24428 // CHECK23-NEXT:    store i32 [[ADD18]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !28
24429 // CHECK23-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
24430 // CHECK23:       omp.body.continue:
24431 // CHECK23-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
24432 // CHECK23:       omp.inner.for.inc:
24433 // CHECK23-NEXT:    [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28
24434 // CHECK23-NEXT:    [[ADD19:%.*]] = add i32 [[TMP24]], 1
24435 // CHECK23-NEXT:    store i32 [[ADD19]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28
24436 // CHECK23-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP29:![0-9]+]]
24437 // CHECK23:       omp.inner.for.end:
24438 // CHECK23-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
24439 // CHECK23:       omp.loop.exit:
24440 // CHECK23-NEXT:    [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
24441 // CHECK23-NEXT:    [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4
24442 // CHECK23-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]])
24443 // CHECK23-NEXT:    [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
24444 // CHECK23-NEXT:    [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0
24445 // CHECK23-NEXT:    br i1 [[TMP28]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
24446 // CHECK23:       .omp.final.then:
24447 // CHECK23-NEXT:    [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
24448 // CHECK23-NEXT:    [[TMP30:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
24449 // CHECK23-NEXT:    [[TMP31:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
24450 // CHECK23-NEXT:    [[SUB20:%.*]] = sub i32 [[TMP30]], [[TMP31]]
24451 // CHECK23-NEXT:    [[SUB21:%.*]] = sub i32 [[SUB20]], 1
24452 // CHECK23-NEXT:    [[ADD22:%.*]] = add i32 [[SUB21]], 1
24453 // CHECK23-NEXT:    [[DIV23:%.*]] = udiv i32 [[ADD22]], 1
24454 // CHECK23-NEXT:    [[MUL24:%.*]] = mul i32 [[DIV23]], 1
24455 // CHECK23-NEXT:    [[ADD25:%.*]] = add i32 [[TMP29]], [[MUL24]]
24456 // CHECK23-NEXT:    store i32 [[ADD25]], i32* [[I6]], align 4
24457 // CHECK23-NEXT:    br label [[DOTOMP_FINAL_DONE]]
24458 // CHECK23:       .omp.final.done:
24459 // CHECK23-NEXT:    br label [[OMP_PRECOND_END]]
24460 // CHECK23:       omp.precond.end:
24461 // CHECK23-NEXT:    ret void
24462 //
24463 //
24464 // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215
24465 // CHECK23-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
24466 // CHECK23-NEXT:  entry:
24467 // CHECK23-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
24468 // CHECK23-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
24469 // CHECK23-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
24470 // CHECK23-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
24471 // CHECK23-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 4
24472 // CHECK23-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
24473 // CHECK23-NEXT:    [[B_CASTED:%.*]] = alloca i32, align 4
24474 // CHECK23-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
24475 // CHECK23-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
24476 // CHECK23-NEXT:    store i32 [[B]], i32* [[B_ADDR]], align 4
24477 // CHECK23-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
24478 // CHECK23-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
24479 // CHECK23-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 4
24480 // CHECK23-NEXT:    store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
24481 // CHECK23-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
24482 // CHECK23-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
24483 // CHECK23-NEXT:    [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
24484 // CHECK23-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
24485 // CHECK23-NEXT:    [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8*
24486 // CHECK23-NEXT:    [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4
24487 // CHECK23-NEXT:    store i32 [[TMP4]], i32* [[B_CASTED]], align 4
24488 // CHECK23-NEXT:    [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4
24489 // CHECK23-NEXT:    [[TMP6:%.*]] = load i8, i8* [[CONV]], align 1
24490 // CHECK23-NEXT:    [[TOBOOL:%.*]] = trunc i8 [[TMP6]] to i1
24491 // CHECK23-NEXT:    [[CONV3:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__CASTED]] to i8*
24492 // CHECK23-NEXT:    [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
24493 // CHECK23-NEXT:    store i8 [[FROMBOOL]], i8* [[CONV3]], align 1
24494 // CHECK23-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
24495 // CHECK23-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]], i32 [[TMP7]])
24496 // CHECK23-NEXT:    ret void
24497 //
24498 //
24499 // CHECK23-LABEL: define {{[^@]+}}@.omp_outlined..5
24500 // CHECK23-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
24501 // CHECK23-NEXT:  entry:
24502 // CHECK23-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
24503 // CHECK23-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
24504 // CHECK23-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
24505 // CHECK23-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
24506 // CHECK23-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
24507 // CHECK23-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
24508 // CHECK23-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 4
24509 // CHECK23-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
24510 // CHECK23-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
24511 // CHECK23-NEXT:    [[TMP:%.*]] = alloca i32, align 4
24512 // CHECK23-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
24513 // CHECK23-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
24514 // CHECK23-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
24515 // CHECK23-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
24516 // CHECK23-NEXT:    [[I:%.*]] = alloca i32, align 4
24517 // CHECK23-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
24518 // CHECK23-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
24519 // CHECK23-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
24520 // CHECK23-NEXT:    store i32 [[B]], i32* [[B_ADDR]], align 4
24521 // CHECK23-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
24522 // CHECK23-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
24523 // CHECK23-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 4
24524 // CHECK23-NEXT:    store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
24525 // CHECK23-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
24526 // CHECK23-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
24527 // CHECK23-NEXT:    [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
24528 // CHECK23-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
24529 // CHECK23-NEXT:    [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8*
24530 // CHECK23-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
24531 // CHECK23-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
24532 // CHECK23-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
24533 // CHECK23-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
24534 // CHECK23-NEXT:    [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
24535 // CHECK23-NEXT:    [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
24536 // CHECK23-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
24537 // CHECK23-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
24538 // CHECK23-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 9
24539 // CHECK23-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
24540 // CHECK23:       cond.true:
24541 // CHECK23-NEXT:    br label [[COND_END:%.*]]
24542 // CHECK23:       cond.false:
24543 // CHECK23-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
24544 // CHECK23-NEXT:    br label [[COND_END]]
24545 // CHECK23:       cond.end:
24546 // CHECK23-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
24547 // CHECK23-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
24548 // CHECK23-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
24549 // CHECK23-NEXT:    store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
24550 // CHECK23-NEXT:    [[TMP9:%.*]] = load i8, i8* [[CONV]], align 1
24551 // CHECK23-NEXT:    [[TOBOOL:%.*]] = trunc i8 [[TMP9]] to i1
24552 // CHECK23-NEXT:    br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
24553 // CHECK23:       omp_if.then:
24554 // CHECK23-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
24555 // CHECK23:       omp.inner.for.cond:
24556 // CHECK23-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !31
24557 // CHECK23-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !31
24558 // CHECK23-NEXT:    [[CMP3:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]
24559 // CHECK23-NEXT:    br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
24560 // CHECK23:       omp.inner.for.body:
24561 // CHECK23-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !31
24562 // CHECK23-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1
24563 // CHECK23-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
24564 // CHECK23-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !31
24565 // CHECK23-NEXT:    [[TMP13:%.*]] = load i32, i32* [[B_ADDR]], align 4, !llvm.access.group !31
24566 // CHECK23-NEXT:    [[CONV4:%.*]] = sitofp i32 [[TMP13]] to double
24567 // CHECK23-NEXT:    [[ADD5:%.*]] = fadd double [[CONV4]], 1.500000e+00
24568 // CHECK23-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
24569 // CHECK23-NEXT:    store double [[ADD5]], double* [[A]], align 4, !llvm.access.group !31
24570 // CHECK23-NEXT:    [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
24571 // CHECK23-NEXT:    [[TMP14:%.*]] = load double, double* [[A6]], align 4, !llvm.access.group !31
24572 // CHECK23-NEXT:    [[INC:%.*]] = fadd double [[TMP14]], 1.000000e+00
24573 // CHECK23-NEXT:    store double [[INC]], double* [[A6]], align 4, !llvm.access.group !31
24574 // CHECK23-NEXT:    [[CONV7:%.*]] = fptosi double [[INC]] to i16
24575 // CHECK23-NEXT:    [[TMP15:%.*]] = mul nsw i32 1, [[TMP2]]
24576 // CHECK23-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP15]]
24577 // CHECK23-NEXT:    [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
24578 // CHECK23-NEXT:    store i16 [[CONV7]], i16* [[ARRAYIDX8]], align 2, !llvm.access.group !31
24579 // CHECK23-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
24580 // CHECK23:       omp.body.continue:
24581 // CHECK23-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
24582 // CHECK23:       omp.inner.for.inc:
24583 // CHECK23-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !31
24584 // CHECK23-NEXT:    [[ADD9:%.*]] = add nsw i32 [[TMP16]], 1
24585 // CHECK23-NEXT:    store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !31
24586 // CHECK23-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP32:![0-9]+]]
24587 // CHECK23:       omp.inner.for.end:
24588 // CHECK23-NEXT:    br label [[OMP_IF_END:%.*]]
24589 // CHECK23:       omp_if.else:
24590 // CHECK23-NEXT:    br label [[OMP_INNER_FOR_COND10:%.*]]
24591 // CHECK23:       omp.inner.for.cond10:
24592 // CHECK23-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
24593 // CHECK23-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
24594 // CHECK23-NEXT:    [[CMP11:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]]
24595 // CHECK23-NEXT:    br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY12:%.*]], label [[OMP_INNER_FOR_END26:%.*]]
24596 // CHECK23:       omp.inner.for.body12:
24597 // CHECK23-NEXT:    [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
24598 // CHECK23-NEXT:    [[MUL13:%.*]] = mul nsw i32 [[TMP19]], 1
24599 // CHECK23-NEXT:    [[ADD14:%.*]] = add nsw i32 0, [[MUL13]]
24600 // CHECK23-NEXT:    store i32 [[ADD14]], i32* [[I]], align 4
24601 // CHECK23-NEXT:    [[TMP20:%.*]] = load i32, i32* [[B_ADDR]], align 4
24602 // CHECK23-NEXT:    [[CONV15:%.*]] = sitofp i32 [[TMP20]] to double
24603 // CHECK23-NEXT:    [[ADD16:%.*]] = fadd double [[CONV15]], 1.500000e+00
24604 // CHECK23-NEXT:    [[A17:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
24605 // CHECK23-NEXT:    store double [[ADD16]], double* [[A17]], align 4
24606 // CHECK23-NEXT:    [[A18:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
24607 // CHECK23-NEXT:    [[TMP21:%.*]] = load double, double* [[A18]], align 4
24608 // CHECK23-NEXT:    [[INC19:%.*]] = fadd double [[TMP21]], 1.000000e+00
24609 // CHECK23-NEXT:    store double [[INC19]], double* [[A18]], align 4
24610 // CHECK23-NEXT:    [[CONV20:%.*]] = fptosi double [[INC19]] to i16
24611 // CHECK23-NEXT:    [[TMP22:%.*]] = mul nsw i32 1, [[TMP2]]
24612 // CHECK23-NEXT:    [[ARRAYIDX21:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP22]]
24613 // CHECK23-NEXT:    [[ARRAYIDX22:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX21]], i32 1
24614 // CHECK23-NEXT:    store i16 [[CONV20]], i16* [[ARRAYIDX22]], align 2
24615 // CHECK23-NEXT:    br label [[OMP_BODY_CONTINUE23:%.*]]
24616 // CHECK23:       omp.body.continue23:
24617 // CHECK23-NEXT:    br label [[OMP_INNER_FOR_INC24:%.*]]
24618 // CHECK23:       omp.inner.for.inc24:
24619 // CHECK23-NEXT:    [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
24620 // CHECK23-NEXT:    [[ADD25:%.*]] = add nsw i32 [[TMP23]], 1
24621 // CHECK23-NEXT:    store i32 [[ADD25]], i32* [[DOTOMP_IV]], align 4
24622 // CHECK23-NEXT:    br label [[OMP_INNER_FOR_COND10]], !llvm.loop [[LOOP34:![0-9]+]]
24623 // CHECK23:       omp.inner.for.end26:
24624 // CHECK23-NEXT:    br label [[OMP_IF_END]]
24625 // CHECK23:       omp_if.end:
24626 // CHECK23-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
24627 // CHECK23:       omp.loop.exit:
24628 // CHECK23-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
24629 // CHECK23-NEXT:    [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
24630 // CHECK23-NEXT:    [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0
24631 // CHECK23-NEXT:    br i1 [[TMP25]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
24632 // CHECK23:       .omp.final.then:
24633 // CHECK23-NEXT:    store i32 10, i32* [[I]], align 4
24634 // CHECK23-NEXT:    br label [[DOTOMP_FINAL_DONE]]
24635 // CHECK23:       .omp.final.done:
24636 // CHECK23-NEXT:    ret void
24637 //
24638 //
24639 // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180
24640 // CHECK23-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
24641 // CHECK23-NEXT:  entry:
24642 // CHECK23-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
24643 // CHECK23-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
24644 // CHECK23-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
24645 // CHECK23-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
24646 // CHECK23-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
24647 // CHECK23-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
24648 // CHECK23-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
24649 // CHECK23-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
24650 // CHECK23-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
24651 // CHECK23-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
24652 // CHECK23-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
24653 // CHECK23-NEXT:    store i32 [[TMP1]], i32* [[A_CASTED]], align 4
24654 // CHECK23-NEXT:    [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
24655 // CHECK23-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
24656 // CHECK23-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
24657 // CHECK23-NEXT:    store i16 [[TMP3]], i16* [[CONV1]], align 2
24658 // CHECK23-NEXT:    [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
24659 // CHECK23-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]])
24660 // CHECK23-NEXT:    ret void
24661 //
24662 //
24663 // CHECK23-LABEL: define {{[^@]+}}@.omp_outlined..6
24664 // CHECK23-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {
24665 // CHECK23-NEXT:  entry:
24666 // CHECK23-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
24667 // CHECK23-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
24668 // CHECK23-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
24669 // CHECK23-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
24670 // CHECK23-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
24671 // CHECK23-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
24672 // CHECK23-NEXT:    [[TMP:%.*]] = alloca i32, align 4
24673 // CHECK23-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
24674 // CHECK23-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
24675 // CHECK23-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
24676 // CHECK23-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
24677 // CHECK23-NEXT:    [[I:%.*]] = alloca i32, align 4
24678 // CHECK23-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
24679 // CHECK23-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
24680 // CHECK23-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
24681 // CHECK23-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
24682 // CHECK23-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
24683 // CHECK23-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
24684 // CHECK23-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
24685 // CHECK23-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
24686 // CHECK23-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
24687 // CHECK23-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
24688 // CHECK23-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
24689 // CHECK23-NEXT:    [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
24690 // CHECK23-NEXT:    [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
24691 // CHECK23-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
24692 // CHECK23-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
24693 // CHECK23-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9
24694 // CHECK23-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
24695 // CHECK23:       cond.true:
24696 // CHECK23-NEXT:    br label [[COND_END:%.*]]
24697 // CHECK23:       cond.false:
24698 // CHECK23-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
24699 // CHECK23-NEXT:    br label [[COND_END]]
24700 // CHECK23:       cond.end:
24701 // CHECK23-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
24702 // CHECK23-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
24703 // CHECK23-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
24704 // CHECK23-NEXT:    store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
24705 // CHECK23-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
24706 // CHECK23:       omp.inner.for.cond:
24707 // CHECK23-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36
24708 // CHECK23-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !36
24709 // CHECK23-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
24710 // CHECK23-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
24711 // CHECK23:       omp.inner.for.body:
24712 // CHECK23-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36
24713 // CHECK23-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
24714 // CHECK23-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
24715 // CHECK23-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !36
24716 // CHECK23-NEXT:    [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !36
24717 // CHECK23-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
24718 // CHECK23-NEXT:    store i32 [[ADD2]], i32* [[A_ADDR]], align 4, !llvm.access.group !36
24719 // CHECK23-NEXT:    [[TMP10:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !36
24720 // CHECK23-NEXT:    [[CONV3:%.*]] = sext i16 [[TMP10]] to i32
24721 // CHECK23-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
24722 // CHECK23-NEXT:    [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
24723 // CHECK23-NEXT:    store i16 [[CONV5]], i16* [[CONV]], align 2, !llvm.access.group !36
24724 // CHECK23-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
24725 // CHECK23-NEXT:    [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !36
24726 // CHECK23-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1
24727 // CHECK23-NEXT:    store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !36
24728 // CHECK23-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
24729 // CHECK23:       omp.body.continue:
24730 // CHECK23-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
24731 // CHECK23:       omp.inner.for.inc:
24732 // CHECK23-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36
24733 // CHECK23-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP12]], 1
24734 // CHECK23-NEXT:    store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36
24735 // CHECK23-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP37:![0-9]+]]
24736 // CHECK23:       omp.inner.for.end:
24737 // CHECK23-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
24738 // CHECK23:       omp.loop.exit:
24739 // CHECK23-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
24740 // CHECK23-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
24741 // CHECK23-NEXT:    [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
24742 // CHECK23-NEXT:    br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
24743 // CHECK23:       .omp.final.then:
24744 // CHECK23-NEXT:    store i32 10, i32* [[I]], align 4
24745 // CHECK23-NEXT:    br label [[DOTOMP_FINAL_DONE]]
24746 // CHECK23:       .omp.final.done:
24747 // CHECK23-NEXT:    ret void
24748 //
24749 //
24750 // CHECK24-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97
24751 // CHECK24-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]], i32 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] {
24752 // CHECK24-NEXT:  entry:
24753 // CHECK24-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
24754 // CHECK24-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
24755 // CHECK24-NEXT:    [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4
24756 // CHECK24-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
24757 // CHECK24-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]])
24758 // CHECK24-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
24759 // CHECK24-NEXT:    store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
24760 // CHECK24-NEXT:    store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4
24761 // CHECK24-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
24762 // CHECK24-NEXT:    [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
24763 // CHECK24-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4
24764 // CHECK24-NEXT:    call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
24765 // CHECK24-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
24766 // CHECK24-NEXT:    [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
24767 // CHECK24-NEXT:    store i16 [[TMP3]], i16* [[CONV3]], align 2
24768 // CHECK24-NEXT:    [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
24769 // CHECK24-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]])
24770 // CHECK24-NEXT:    ret void
24771 //
24772 //
24773 // CHECK24-LABEL: define {{[^@]+}}@.omp_outlined.
24774 // CHECK24-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR1:[0-9]+]] {
24775 // CHECK24-NEXT:  entry:
24776 // CHECK24-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
24777 // CHECK24-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
24778 // CHECK24-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
24779 // CHECK24-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
24780 // CHECK24-NEXT:    [[TMP:%.*]] = alloca i32, align 4
24781 // CHECK24-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
24782 // CHECK24-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
24783 // CHECK24-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
24784 // CHECK24-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
24785 // CHECK24-NEXT:    [[I:%.*]] = alloca i32, align 4
24786 // CHECK24-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
24787 // CHECK24-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
24788 // CHECK24-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
24789 // CHECK24-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
24790 // CHECK24-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
24791 // CHECK24-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
24792 // CHECK24-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
24793 // CHECK24-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
24794 // CHECK24-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
24795 // CHECK24-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
24796 // CHECK24-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
24797 // CHECK24-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
24798 // CHECK24-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
24799 // CHECK24-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
24800 // CHECK24:       cond.true:
24801 // CHECK24-NEXT:    br label [[COND_END:%.*]]
24802 // CHECK24:       cond.false:
24803 // CHECK24-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
24804 // CHECK24-NEXT:    br label [[COND_END]]
24805 // CHECK24:       cond.end:
24806 // CHECK24-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
24807 // CHECK24-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
24808 // CHECK24-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
24809 // CHECK24-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
24810 // CHECK24-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
24811 // CHECK24:       omp.inner.for.cond:
24812 // CHECK24-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
24813 // CHECK24-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !12
24814 // CHECK24-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
24815 // CHECK24-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
24816 // CHECK24:       omp.inner.for.body:
24817 // CHECK24-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
24818 // CHECK24-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
24819 // CHECK24-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
24820 // CHECK24-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !12
24821 // CHECK24-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
24822 // CHECK24:       omp.body.continue:
24823 // CHECK24-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
24824 // CHECK24:       omp.inner.for.inc:
24825 // CHECK24-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
24826 // CHECK24-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
24827 // CHECK24-NEXT:    store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
24828 // CHECK24-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]
24829 // CHECK24:       omp.inner.for.end:
24830 // CHECK24-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
24831 // CHECK24:       omp.loop.exit:
24832 // CHECK24-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
24833 // CHECK24-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
24834 // CHECK24-NEXT:    [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0
24835 // CHECK24-NEXT:    br i1 [[TMP10]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
24836 // CHECK24:       .omp.final.then:
24837 // CHECK24-NEXT:    store i32 10, i32* [[I]], align 4
24838 // CHECK24-NEXT:    br label [[DOTOMP_FINAL_DONE]]
24839 // CHECK24:       .omp.final.done:
24840 // CHECK24-NEXT:    ret void
24841 //
24842 //
24843 // CHECK24-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111
24844 // CHECK24-SAME: (i32 noundef [[AA:%.*]]) #[[ATTR0]] {
24845 // CHECK24-NEXT:  entry:
24846 // CHECK24-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
24847 // CHECK24-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
24848 // CHECK24-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
24849 // CHECK24-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
24850 // CHECK24-NEXT:    [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
24851 // CHECK24-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
24852 // CHECK24-NEXT:    store i16 [[TMP0]], i16* [[CONV1]], align 2
24853 // CHECK24-NEXT:    [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
24854 // CHECK24-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]])
24855 // CHECK24-NEXT:    ret void
24856 //
24857 //
24858 // CHECK24-LABEL: define {{[^@]+}}@.omp_outlined..1
24859 // CHECK24-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR1]] {
24860 // CHECK24-NEXT:  entry:
24861 // CHECK24-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
24862 // CHECK24-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
24863 // CHECK24-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
24864 // CHECK24-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
24865 // CHECK24-NEXT:    [[TMP:%.*]] = alloca i32, align 4
24866 // CHECK24-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
24867 // CHECK24-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
24868 // CHECK24-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
24869 // CHECK24-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
24870 // CHECK24-NEXT:    [[I:%.*]] = alloca i32, align 4
24871 // CHECK24-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
24872 // CHECK24-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
24873 // CHECK24-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
24874 // CHECK24-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
24875 // CHECK24-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
24876 // CHECK24-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
24877 // CHECK24-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
24878 // CHECK24-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
24879 // CHECK24-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
24880 // CHECK24-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
24881 // CHECK24-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
24882 // CHECK24-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
24883 // CHECK24-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
24884 // CHECK24-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
24885 // CHECK24:       cond.true:
24886 // CHECK24-NEXT:    br label [[COND_END:%.*]]
24887 // CHECK24:       cond.false:
24888 // CHECK24-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
24889 // CHECK24-NEXT:    br label [[COND_END]]
24890 // CHECK24:       cond.end:
24891 // CHECK24-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
24892 // CHECK24-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
24893 // CHECK24-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
24894 // CHECK24-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
24895 // CHECK24-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
24896 // CHECK24:       omp.inner.for.cond:
24897 // CHECK24-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
24898 // CHECK24-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !19
24899 // CHECK24-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
24900 // CHECK24-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
24901 // CHECK24:       omp.inner.for.body:
24902 // CHECK24-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
24903 // CHECK24-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
24904 // CHECK24-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
24905 // CHECK24-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !19
24906 // CHECK24-NEXT:    [[TMP8:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !19
24907 // CHECK24-NEXT:    [[CONV2:%.*]] = sext i16 [[TMP8]] to i32
24908 // CHECK24-NEXT:    [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
24909 // CHECK24-NEXT:    [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
24910 // CHECK24-NEXT:    store i16 [[CONV4]], i16* [[CONV]], align 2, !llvm.access.group !19
24911 // CHECK24-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
24912 // CHECK24:       omp.body.continue:
24913 // CHECK24-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
24914 // CHECK24:       omp.inner.for.inc:
24915 // CHECK24-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
24916 // CHECK24-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP9]], 1
24917 // CHECK24-NEXT:    store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
24918 // CHECK24-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]]
24919 // CHECK24:       omp.inner.for.end:
24920 // CHECK24-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
24921 // CHECK24:       omp.loop.exit:
24922 // CHECK24-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
24923 // CHECK24-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
24924 // CHECK24-NEXT:    [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0
24925 // CHECK24-NEXT:    br i1 [[TMP11]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
24926 // CHECK24:       .omp.final.then:
24927 // CHECK24-NEXT:    store i32 10, i32* [[I]], align 4
24928 // CHECK24-NEXT:    br label [[DOTOMP_FINAL_DONE]]
24929 // CHECK24:       .omp.final.done:
24930 // CHECK24-NEXT:    ret void
24931 //
24932 //
24933 // CHECK24-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118
24934 // CHECK24-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] {
24935 // CHECK24-NEXT:  entry:
24936 // CHECK24-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
24937 // CHECK24-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
24938 // CHECK24-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
24939 // CHECK24-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
24940 // CHECK24-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
24941 // CHECK24-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
24942 // CHECK24-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
24943 // CHECK24-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
24944 // CHECK24-NEXT:    store i32 [[TMP0]], i32* [[A_CASTED]], align 4
24945 // CHECK24-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
24946 // CHECK24-NEXT:    [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
24947 // CHECK24-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
24948 // CHECK24-NEXT:    store i16 [[TMP2]], i16* [[CONV1]], align 2
24949 // CHECK24-NEXT:    [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
24950 // CHECK24-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]])
24951 // CHECK24-NEXT:    ret void
24952 //
24953 //
24954 // CHECK24-LABEL: define {{[^@]+}}@.omp_outlined..2
24955 // CHECK24-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR1]] {
24956 // CHECK24-NEXT:  entry:
24957 // CHECK24-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
24958 // CHECK24-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
24959 // CHECK24-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
24960 // CHECK24-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
24961 // CHECK24-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
24962 // CHECK24-NEXT:    [[TMP:%.*]] = alloca i32, align 4
24963 // CHECK24-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
24964 // CHECK24-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
24965 // CHECK24-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
24966 // CHECK24-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
24967 // CHECK24-NEXT:    [[I:%.*]] = alloca i32, align 4
24968 // CHECK24-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
24969 // CHECK24-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
24970 // CHECK24-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
24971 // CHECK24-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
24972 // CHECK24-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
24973 // CHECK24-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
24974 // CHECK24-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
24975 // CHECK24-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
24976 // CHECK24-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
24977 // CHECK24-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
24978 // CHECK24-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
24979 // CHECK24-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
24980 // CHECK24-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
24981 // CHECK24-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
24982 // CHECK24-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
24983 // CHECK24:       cond.true:
24984 // CHECK24-NEXT:    br label [[COND_END:%.*]]
24985 // CHECK24:       cond.false:
24986 // CHECK24-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
24987 // CHECK24-NEXT:    br label [[COND_END]]
24988 // CHECK24:       cond.end:
24989 // CHECK24-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
24990 // CHECK24-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
24991 // CHECK24-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
24992 // CHECK24-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
24993 // CHECK24-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
24994 // CHECK24:       omp.inner.for.cond:
24995 // CHECK24-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
24996 // CHECK24-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !22
24997 // CHECK24-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
24998 // CHECK24-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
24999 // CHECK24:       omp.inner.for.body:
25000 // CHECK24-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
25001 // CHECK24-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
25002 // CHECK24-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
25003 // CHECK24-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !22
25004 // CHECK24-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !22
25005 // CHECK24-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
25006 // CHECK24-NEXT:    store i32 [[ADD2]], i32* [[A_ADDR]], align 4, !llvm.access.group !22
25007 // CHECK24-NEXT:    [[TMP9:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !22
25008 // CHECK24-NEXT:    [[CONV3:%.*]] = sext i16 [[TMP9]] to i32
25009 // CHECK24-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
25010 // CHECK24-NEXT:    [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
25011 // CHECK24-NEXT:    store i16 [[CONV5]], i16* [[CONV]], align 2, !llvm.access.group !22
25012 // CHECK24-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
25013 // CHECK24:       omp.body.continue:
25014 // CHECK24-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
25015 // CHECK24:       omp.inner.for.inc:
25016 // CHECK24-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
25017 // CHECK24-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP10]], 1
25018 // CHECK24-NEXT:    store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
25019 // CHECK24-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]]
25020 // CHECK24:       omp.inner.for.end:
25021 // CHECK24-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
25022 // CHECK24:       omp.loop.exit:
25023 // CHECK24-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
25024 // CHECK24-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
25025 // CHECK24-NEXT:    [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
25026 // CHECK24-NEXT:    br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
25027 // CHECK24:       .omp.final.then:
25028 // CHECK24-NEXT:    store i32 10, i32* [[I]], align 4
25029 // CHECK24-NEXT:    br label [[DOTOMP_FINAL_DONE]]
25030 // CHECK24:       .omp.final.done:
25031 // CHECK24-NEXT:    ret void
25032 //
25033 //
25034 // CHECK24-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142
25035 // CHECK24-SAME: (i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] {
25036 // CHECK24-NEXT:  entry:
25037 // CHECK24-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
25038 // CHECK24-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
25039 // CHECK24-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
25040 // CHECK24-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 4
25041 // CHECK24-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
25042 // CHECK24-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
25043 // CHECK24-NEXT:    [[VLA_ADDR4:%.*]] = alloca i32, align 4
25044 // CHECK24-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 4
25045 // CHECK24-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
25046 // CHECK24-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
25047 // CHECK24-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
25048 // CHECK24-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
25049 // CHECK24-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
25050 // CHECK24-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 4
25051 // CHECK24-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
25052 // CHECK24-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
25053 // CHECK24-NEXT:    store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
25054 // CHECK24-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 4
25055 // CHECK24-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
25056 // CHECK24-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
25057 // CHECK24-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
25058 // CHECK24-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
25059 // CHECK24-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
25060 // CHECK24-NEXT:    [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
25061 // CHECK24-NEXT:    [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
25062 // CHECK24-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
25063 // CHECK24-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
25064 // CHECK24-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
25065 // CHECK24-NEXT:    store i32 [[TMP8]], i32* [[A_CASTED]], align 4
25066 // CHECK24-NEXT:    [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4
25067 // CHECK24-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]])
25068 // CHECK24-NEXT:    ret void
25069 //
25070 //
25071 // CHECK24-LABEL: define {{[^@]+}}@.omp_outlined..3
25072 // CHECK24-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR1]] {
25073 // CHECK24-NEXT:  entry:
25074 // CHECK24-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
25075 // CHECK24-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
25076 // CHECK24-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
25077 // CHECK24-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
25078 // CHECK24-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
25079 // CHECK24-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 4
25080 // CHECK24-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
25081 // CHECK24-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
25082 // CHECK24-NEXT:    [[VLA_ADDR4:%.*]] = alloca i32, align 4
25083 // CHECK24-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 4
25084 // CHECK24-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
25085 // CHECK24-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
25086 // CHECK24-NEXT:    [[TMP:%.*]] = alloca i32, align 4
25087 // CHECK24-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
25088 // CHECK24-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
25089 // CHECK24-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
25090 // CHECK24-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
25091 // CHECK24-NEXT:    [[I:%.*]] = alloca i32, align 4
25092 // CHECK24-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
25093 // CHECK24-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
25094 // CHECK24-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
25095 // CHECK24-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
25096 // CHECK24-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
25097 // CHECK24-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 4
25098 // CHECK24-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
25099 // CHECK24-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
25100 // CHECK24-NEXT:    store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
25101 // CHECK24-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 4
25102 // CHECK24-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
25103 // CHECK24-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
25104 // CHECK24-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
25105 // CHECK24-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
25106 // CHECK24-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
25107 // CHECK24-NEXT:    [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
25108 // CHECK24-NEXT:    [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
25109 // CHECK24-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
25110 // CHECK24-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
25111 // CHECK24-NEXT:    [[ARRAYDECAY:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 0
25112 // CHECK24-NEXT:    call void @llvm.assume(i1 true) [ "align"(float* [[ARRAYDECAY]], i32 16) ]
25113 // CHECK24-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
25114 // CHECK24-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
25115 // CHECK24-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
25116 // CHECK24-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
25117 // CHECK24-NEXT:    [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
25118 // CHECK24-NEXT:    [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4
25119 // CHECK24-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
25120 // CHECK24-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
25121 // CHECK24-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP10]], 9
25122 // CHECK24-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
25123 // CHECK24:       cond.true:
25124 // CHECK24-NEXT:    br label [[COND_END:%.*]]
25125 // CHECK24:       cond.false:
25126 // CHECK24-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
25127 // CHECK24-NEXT:    br label [[COND_END]]
25128 // CHECK24:       cond.end:
25129 // CHECK24-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ]
25130 // CHECK24-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
25131 // CHECK24-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
25132 // CHECK24-NEXT:    store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4
25133 // CHECK24-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
25134 // CHECK24:       omp.inner.for.cond:
25135 // CHECK24-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25
25136 // CHECK24-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !25
25137 // CHECK24-NEXT:    [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
25138 // CHECK24-NEXT:    br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
25139 // CHECK24:       omp.inner.for.body:
25140 // CHECK24-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25
25141 // CHECK24-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1
25142 // CHECK24-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
25143 // CHECK24-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !25
25144 // CHECK24-NEXT:    [[TMP16:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !25
25145 // CHECK24-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP16]], 1
25146 // CHECK24-NEXT:    store i32 [[ADD6]], i32* [[A_ADDR]], align 4, !llvm.access.group !25
25147 // CHECK24-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2
25148 // CHECK24-NEXT:    [[TMP17:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !25
25149 // CHECK24-NEXT:    [[CONV:%.*]] = fpext float [[TMP17]] to double
25150 // CHECK24-NEXT:    [[ADD7:%.*]] = fadd double [[CONV]], 1.000000e+00
25151 // CHECK24-NEXT:    [[CONV8:%.*]] = fptrunc double [[ADD7]] to float
25152 // CHECK24-NEXT:    store float [[CONV8]], float* [[ARRAYIDX]], align 4, !llvm.access.group !25
25153 // CHECK24-NEXT:    [[ARRAYIDX9:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3
25154 // CHECK24-NEXT:    [[TMP18:%.*]] = load float, float* [[ARRAYIDX9]], align 4, !llvm.access.group !25
25155 // CHECK24-NEXT:    [[CONV10:%.*]] = fpext float [[TMP18]] to double
25156 // CHECK24-NEXT:    [[ADD11:%.*]] = fadd double [[CONV10]], 1.000000e+00
25157 // CHECK24-NEXT:    [[CONV12:%.*]] = fptrunc double [[ADD11]] to float
25158 // CHECK24-NEXT:    store float [[CONV12]], float* [[ARRAYIDX9]], align 4, !llvm.access.group !25
25159 // CHECK24-NEXT:    [[ARRAYIDX13:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1
25160 // CHECK24-NEXT:    [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX13]], i32 0, i32 2
25161 // CHECK24-NEXT:    [[TMP19:%.*]] = load double, double* [[ARRAYIDX14]], align 8, !llvm.access.group !25
25162 // CHECK24-NEXT:    [[ADD15:%.*]] = fadd double [[TMP19]], 1.000000e+00
25163 // CHECK24-NEXT:    store double [[ADD15]], double* [[ARRAYIDX14]], align 8, !llvm.access.group !25
25164 // CHECK24-NEXT:    [[TMP20:%.*]] = mul nsw i32 1, [[TMP5]]
25165 // CHECK24-NEXT:    [[ARRAYIDX16:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP20]]
25166 // CHECK24-NEXT:    [[ARRAYIDX17:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX16]], i32 3
25167 // CHECK24-NEXT:    [[TMP21:%.*]] = load double, double* [[ARRAYIDX17]], align 8, !llvm.access.group !25
25168 // CHECK24-NEXT:    [[ADD18:%.*]] = fadd double [[TMP21]], 1.000000e+00
25169 // CHECK24-NEXT:    store double [[ADD18]], double* [[ARRAYIDX17]], align 8, !llvm.access.group !25
25170 // CHECK24-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0
25171 // CHECK24-NEXT:    [[TMP22:%.*]] = load i64, i64* [[X]], align 4, !llvm.access.group !25
25172 // CHECK24-NEXT:    [[ADD19:%.*]] = add nsw i64 [[TMP22]], 1
25173 // CHECK24-NEXT:    store i64 [[ADD19]], i64* [[X]], align 4, !llvm.access.group !25
25174 // CHECK24-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1
25175 // CHECK24-NEXT:    [[TMP23:%.*]] = load i8, i8* [[Y]], align 4, !llvm.access.group !25
25176 // CHECK24-NEXT:    [[CONV20:%.*]] = sext i8 [[TMP23]] to i32
25177 // CHECK24-NEXT:    [[ADD21:%.*]] = add nsw i32 [[CONV20]], 1
25178 // CHECK24-NEXT:    [[CONV22:%.*]] = trunc i32 [[ADD21]] to i8
25179 // CHECK24-NEXT:    store i8 [[CONV22]], i8* [[Y]], align 4, !llvm.access.group !25
25180 // CHECK24-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
25181 // CHECK24:       omp.body.continue:
25182 // CHECK24-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
25183 // CHECK24:       omp.inner.for.inc:
25184 // CHECK24-NEXT:    [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25
25185 // CHECK24-NEXT:    [[ADD23:%.*]] = add nsw i32 [[TMP24]], 1
25186 // CHECK24-NEXT:    store i32 [[ADD23]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25
25187 // CHECK24-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP26:![0-9]+]]
25188 // CHECK24:       omp.inner.for.end:
25189 // CHECK24-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
25190 // CHECK24:       omp.loop.exit:
25191 // CHECK24-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]])
25192 // CHECK24-NEXT:    [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
25193 // CHECK24-NEXT:    [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
25194 // CHECK24-NEXT:    br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
25195 // CHECK24:       .omp.final.then:
25196 // CHECK24-NEXT:    store i32 10, i32* [[I]], align 4
25197 // CHECK24-NEXT:    br label [[DOTOMP_FINAL_DONE]]
25198 // CHECK24:       .omp.final.done:
25199 // CHECK24-NEXT:    ret void
25200 //
25201 //
25202 // CHECK24-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197
25203 // CHECK24-SAME: (i32 noundef [[A:%.*]], i32 noundef [[N:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
25204 // CHECK24-NEXT:  entry:
25205 // CHECK24-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
25206 // CHECK24-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
25207 // CHECK24-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
25208 // CHECK24-NEXT:    [[AAA_ADDR:%.*]] = alloca i32, align 4
25209 // CHECK24-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
25210 // CHECK24-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
25211 // CHECK24-NEXT:    [[N_CASTED:%.*]] = alloca i32, align 4
25212 // CHECK24-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
25213 // CHECK24-NEXT:    [[AAA_CASTED:%.*]] = alloca i32, align 4
25214 // CHECK24-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
25215 // CHECK24-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
25216 // CHECK24-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
25217 // CHECK24-NEXT:    store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
25218 // CHECK24-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
25219 // CHECK24-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
25220 // CHECK24-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
25221 // CHECK24-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
25222 // CHECK24-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
25223 // CHECK24-NEXT:    store i32 [[TMP1]], i32* [[A_CASTED]], align 4
25224 // CHECK24-NEXT:    [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
25225 // CHECK24-NEXT:    [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
25226 // CHECK24-NEXT:    store i32 [[TMP3]], i32* [[N_CASTED]], align 4
25227 // CHECK24-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_CASTED]], align 4
25228 // CHECK24-NEXT:    [[TMP5:%.*]] = load i16, i16* [[CONV]], align 2
25229 // CHECK24-NEXT:    [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
25230 // CHECK24-NEXT:    store i16 [[TMP5]], i16* [[CONV2]], align 2
25231 // CHECK24-NEXT:    [[TMP6:%.*]] = load i32, i32* [[AA_CASTED]], align 4
25232 // CHECK24-NEXT:    [[TMP7:%.*]] = load i8, i8* [[CONV1]], align 1
25233 // CHECK24-NEXT:    [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
25234 // CHECK24-NEXT:    store i8 [[TMP7]], i8* [[CONV3]], align 1
25235 // CHECK24-NEXT:    [[TMP8:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
25236 // CHECK24-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP8]], [10 x i32]* [[TMP0]])
25237 // CHECK24-NEXT:    ret void
25238 //
25239 //
25240 // CHECK24-LABEL: define {{[^@]+}}@.omp_outlined..4
25241 // CHECK24-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[N:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {
25242 // CHECK24-NEXT:  entry:
25243 // CHECK24-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
25244 // CHECK24-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
25245 // CHECK24-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
25246 // CHECK24-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
25247 // CHECK24-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
25248 // CHECK24-NEXT:    [[AAA_ADDR:%.*]] = alloca i32, align 4
25249 // CHECK24-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
25250 // CHECK24-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
25251 // CHECK24-NEXT:    [[TMP:%.*]] = alloca i32, align 4
25252 // CHECK24-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
25253 // CHECK24-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
25254 // CHECK24-NEXT:    [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4
25255 // CHECK24-NEXT:    [[I:%.*]] = alloca i32, align 4
25256 // CHECK24-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
25257 // CHECK24-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
25258 // CHECK24-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
25259 // CHECK24-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
25260 // CHECK24-NEXT:    [[I6:%.*]] = alloca i32, align 4
25261 // CHECK24-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
25262 // CHECK24-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
25263 // CHECK24-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
25264 // CHECK24-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
25265 // CHECK24-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
25266 // CHECK24-NEXT:    store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
25267 // CHECK24-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
25268 // CHECK24-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
25269 // CHECK24-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
25270 // CHECK24-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
25271 // CHECK24-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
25272 // CHECK24-NEXT:    store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
25273 // CHECK24-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
25274 // CHECK24-NEXT:    store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4
25275 // CHECK24-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
25276 // CHECK24-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
25277 // CHECK24-NEXT:    [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]]
25278 // CHECK24-NEXT:    [[SUB4:%.*]] = sub i32 [[SUB]], 1
25279 // CHECK24-NEXT:    [[ADD:%.*]] = add i32 [[SUB4]], 1
25280 // CHECK24-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], 1
25281 // CHECK24-NEXT:    [[SUB5:%.*]] = sub i32 [[DIV]], 1
25282 // CHECK24-NEXT:    store i32 [[SUB5]], i32* [[DOTCAPTURE_EXPR_3]], align 4
25283 // CHECK24-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
25284 // CHECK24-NEXT:    store i32 [[TMP5]], i32* [[I]], align 4
25285 // CHECK24-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
25286 // CHECK24-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
25287 // CHECK24-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]]
25288 // CHECK24-NEXT:    br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
25289 // CHECK24:       omp.precond.then:
25290 // CHECK24-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
25291 // CHECK24-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
25292 // CHECK24-NEXT:    store i32 [[TMP8]], i32* [[DOTOMP_UB]], align 4
25293 // CHECK24-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
25294 // CHECK24-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
25295 // CHECK24-NEXT:    [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
25296 // CHECK24-NEXT:    [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
25297 // CHECK24-NEXT:    call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
25298 // CHECK24-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
25299 // CHECK24-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
25300 // CHECK24-NEXT:    [[CMP7:%.*]] = icmp ugt i32 [[TMP11]], [[TMP12]]
25301 // CHECK24-NEXT:    br i1 [[CMP7]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
25302 // CHECK24:       cond.true:
25303 // CHECK24-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
25304 // CHECK24-NEXT:    br label [[COND_END:%.*]]
25305 // CHECK24:       cond.false:
25306 // CHECK24-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
25307 // CHECK24-NEXT:    br label [[COND_END]]
25308 // CHECK24:       cond.end:
25309 // CHECK24-NEXT:    [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ]
25310 // CHECK24-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
25311 // CHECK24-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
25312 // CHECK24-NEXT:    store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4
25313 // CHECK24-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
25314 // CHECK24:       omp.inner.for.cond:
25315 // CHECK24-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28
25316 // CHECK24-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !28
25317 // CHECK24-NEXT:    [[ADD8:%.*]] = add i32 [[TMP17]], 1
25318 // CHECK24-NEXT:    [[CMP9:%.*]] = icmp ult i32 [[TMP16]], [[ADD8]]
25319 // CHECK24-NEXT:    br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
25320 // CHECK24:       omp.inner.for.body:
25321 // CHECK24-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group !28
25322 // CHECK24-NEXT:    [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28
25323 // CHECK24-NEXT:    [[MUL:%.*]] = mul i32 [[TMP19]], 1
25324 // CHECK24-NEXT:    [[ADD10:%.*]] = add i32 [[TMP18]], [[MUL]]
25325 // CHECK24-NEXT:    store i32 [[ADD10]], i32* [[I6]], align 4, !llvm.access.group !28
25326 // CHECK24-NEXT:    [[TMP20:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !28
25327 // CHECK24-NEXT:    [[ADD11:%.*]] = add nsw i32 [[TMP20]], 1
25328 // CHECK24-NEXT:    store i32 [[ADD11]], i32* [[A_ADDR]], align 4, !llvm.access.group !28
25329 // CHECK24-NEXT:    [[TMP21:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !28
25330 // CHECK24-NEXT:    [[CONV12:%.*]] = sext i16 [[TMP21]] to i32
25331 // CHECK24-NEXT:    [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1
25332 // CHECK24-NEXT:    [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16
25333 // CHECK24-NEXT:    store i16 [[CONV14]], i16* [[CONV]], align 2, !llvm.access.group !28
25334 // CHECK24-NEXT:    [[TMP22:%.*]] = load i8, i8* [[CONV1]], align 1, !llvm.access.group !28
25335 // CHECK24-NEXT:    [[CONV15:%.*]] = sext i8 [[TMP22]] to i32
25336 // CHECK24-NEXT:    [[ADD16:%.*]] = add nsw i32 [[CONV15]], 1
25337 // CHECK24-NEXT:    [[CONV17:%.*]] = trunc i32 [[ADD16]] to i8
25338 // CHECK24-NEXT:    store i8 [[CONV17]], i8* [[CONV1]], align 1, !llvm.access.group !28
25339 // CHECK24-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
25340 // CHECK24-NEXT:    [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !28
25341 // CHECK24-NEXT:    [[ADD18:%.*]] = add nsw i32 [[TMP23]], 1
25342 // CHECK24-NEXT:    store i32 [[ADD18]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !28
25343 // CHECK24-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
25344 // CHECK24:       omp.body.continue:
25345 // CHECK24-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
25346 // CHECK24:       omp.inner.for.inc:
25347 // CHECK24-NEXT:    [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28
25348 // CHECK24-NEXT:    [[ADD19:%.*]] = add i32 [[TMP24]], 1
25349 // CHECK24-NEXT:    store i32 [[ADD19]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28
25350 // CHECK24-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP29:![0-9]+]]
25351 // CHECK24:       omp.inner.for.end:
25352 // CHECK24-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
25353 // CHECK24:       omp.loop.exit:
25354 // CHECK24-NEXT:    [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
25355 // CHECK24-NEXT:    [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4
25356 // CHECK24-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]])
25357 // CHECK24-NEXT:    [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
25358 // CHECK24-NEXT:    [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0
25359 // CHECK24-NEXT:    br i1 [[TMP28]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
25360 // CHECK24:       .omp.final.then:
25361 // CHECK24-NEXT:    [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
25362 // CHECK24-NEXT:    [[TMP30:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
25363 // CHECK24-NEXT:    [[TMP31:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
25364 // CHECK24-NEXT:    [[SUB20:%.*]] = sub i32 [[TMP30]], [[TMP31]]
25365 // CHECK24-NEXT:    [[SUB21:%.*]] = sub i32 [[SUB20]], 1
25366 // CHECK24-NEXT:    [[ADD22:%.*]] = add i32 [[SUB21]], 1
25367 // CHECK24-NEXT:    [[DIV23:%.*]] = udiv i32 [[ADD22]], 1
25368 // CHECK24-NEXT:    [[MUL24:%.*]] = mul i32 [[DIV23]], 1
25369 // CHECK24-NEXT:    [[ADD25:%.*]] = add i32 [[TMP29]], [[MUL24]]
25370 // CHECK24-NEXT:    store i32 [[ADD25]], i32* [[I6]], align 4
25371 // CHECK24-NEXT:    br label [[DOTOMP_FINAL_DONE]]
25372 // CHECK24:       .omp.final.done:
25373 // CHECK24-NEXT:    br label [[OMP_PRECOND_END]]
25374 // CHECK24:       omp.precond.end:
25375 // CHECK24-NEXT:    ret void
25376 //
25377 //
25378 // CHECK24-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215
25379 // CHECK24-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
25380 // CHECK24-NEXT:  entry:
25381 // CHECK24-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
25382 // CHECK24-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
25383 // CHECK24-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
25384 // CHECK24-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
25385 // CHECK24-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 4
25386 // CHECK24-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
25387 // CHECK24-NEXT:    [[B_CASTED:%.*]] = alloca i32, align 4
25388 // CHECK24-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
25389 // CHECK24-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
25390 // CHECK24-NEXT:    store i32 [[B]], i32* [[B_ADDR]], align 4
25391 // CHECK24-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
25392 // CHECK24-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
25393 // CHECK24-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 4
25394 // CHECK24-NEXT:    store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
25395 // CHECK24-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
25396 // CHECK24-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
25397 // CHECK24-NEXT:    [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
25398 // CHECK24-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
25399 // CHECK24-NEXT:    [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8*
25400 // CHECK24-NEXT:    [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4
25401 // CHECK24-NEXT:    store i32 [[TMP4]], i32* [[B_CASTED]], align 4
25402 // CHECK24-NEXT:    [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4
25403 // CHECK24-NEXT:    [[TMP6:%.*]] = load i8, i8* [[CONV]], align 1
25404 // CHECK24-NEXT:    [[TOBOOL:%.*]] = trunc i8 [[TMP6]] to i1
25405 // CHECK24-NEXT:    [[CONV3:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__CASTED]] to i8*
25406 // CHECK24-NEXT:    [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
25407 // CHECK24-NEXT:    store i8 [[FROMBOOL]], i8* [[CONV3]], align 1
25408 // CHECK24-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
25409 // CHECK24-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]], i32 [[TMP7]])
25410 // CHECK24-NEXT:    ret void
25411 //
25412 //
25413 // CHECK24-LABEL: define {{[^@]+}}@.omp_outlined..5
25414 // CHECK24-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
25415 // CHECK24-NEXT:  entry:
25416 // CHECK24-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
25417 // CHECK24-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
25418 // CHECK24-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
25419 // CHECK24-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
25420 // CHECK24-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
25421 // CHECK24-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
25422 // CHECK24-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 4
25423 // CHECK24-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
25424 // CHECK24-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
25425 // CHECK24-NEXT:    [[TMP:%.*]] = alloca i32, align 4
25426 // CHECK24-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
25427 // CHECK24-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
25428 // CHECK24-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
25429 // CHECK24-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
25430 // CHECK24-NEXT:    [[I:%.*]] = alloca i32, align 4
25431 // CHECK24-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
25432 // CHECK24-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
25433 // CHECK24-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
25434 // CHECK24-NEXT:    store i32 [[B]], i32* [[B_ADDR]], align 4
25435 // CHECK24-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
25436 // CHECK24-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
25437 // CHECK24-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 4
25438 // CHECK24-NEXT:    store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
25439 // CHECK24-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
25440 // CHECK24-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
25441 // CHECK24-NEXT:    [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
25442 // CHECK24-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
25443 // CHECK24-NEXT:    [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8*
25444 // CHECK24-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
25445 // CHECK24-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
25446 // CHECK24-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
25447 // CHECK24-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
25448 // CHECK24-NEXT:    [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
25449 // CHECK24-NEXT:    [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
25450 // CHECK24-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
25451 // CHECK24-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
25452 // CHECK24-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 9
25453 // CHECK24-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
25454 // CHECK24:       cond.true:
25455 // CHECK24-NEXT:    br label [[COND_END:%.*]]
25456 // CHECK24:       cond.false:
25457 // CHECK24-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
25458 // CHECK24-NEXT:    br label [[COND_END]]
25459 // CHECK24:       cond.end:
25460 // CHECK24-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
25461 // CHECK24-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
25462 // CHECK24-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
25463 // CHECK24-NEXT:    store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
25464 // CHECK24-NEXT:    [[TMP9:%.*]] = load i8, i8* [[CONV]], align 1
25465 // CHECK24-NEXT:    [[TOBOOL:%.*]] = trunc i8 [[TMP9]] to i1
25466 // CHECK24-NEXT:    br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
25467 // CHECK24:       omp_if.then:
25468 // CHECK24-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
25469 // CHECK24:       omp.inner.for.cond:
25470 // CHECK24-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !31
25471 // CHECK24-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !31
25472 // CHECK24-NEXT:    [[CMP3:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]
25473 // CHECK24-NEXT:    br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
25474 // CHECK24:       omp.inner.for.body:
25475 // CHECK24-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !31
25476 // CHECK24-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1
25477 // CHECK24-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
25478 // CHECK24-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !31
25479 // CHECK24-NEXT:    [[TMP13:%.*]] = load i32, i32* [[B_ADDR]], align 4, !llvm.access.group !31
25480 // CHECK24-NEXT:    [[CONV4:%.*]] = sitofp i32 [[TMP13]] to double
25481 // CHECK24-NEXT:    [[ADD5:%.*]] = fadd double [[CONV4]], 1.500000e+00
25482 // CHECK24-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
25483 // CHECK24-NEXT:    store double [[ADD5]], double* [[A]], align 4, !llvm.access.group !31
25484 // CHECK24-NEXT:    [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
25485 // CHECK24-NEXT:    [[TMP14:%.*]] = load double, double* [[A6]], align 4, !llvm.access.group !31
25486 // CHECK24-NEXT:    [[INC:%.*]] = fadd double [[TMP14]], 1.000000e+00
25487 // CHECK24-NEXT:    store double [[INC]], double* [[A6]], align 4, !llvm.access.group !31
25488 // CHECK24-NEXT:    [[CONV7:%.*]] = fptosi double [[INC]] to i16
25489 // CHECK24-NEXT:    [[TMP15:%.*]] = mul nsw i32 1, [[TMP2]]
25490 // CHECK24-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP15]]
25491 // CHECK24-NEXT:    [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
25492 // CHECK24-NEXT:    store i16 [[CONV7]], i16* [[ARRAYIDX8]], align 2, !llvm.access.group !31
25493 // CHECK24-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
25494 // CHECK24:       omp.body.continue:
25495 // CHECK24-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
25496 // CHECK24:       omp.inner.for.inc:
25497 // CHECK24-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !31
25498 // CHECK24-NEXT:    [[ADD9:%.*]] = add nsw i32 [[TMP16]], 1
25499 // CHECK24-NEXT:    store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !31
25500 // CHECK24-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP32:![0-9]+]]
25501 // CHECK24:       omp.inner.for.end:
25502 // CHECK24-NEXT:    br label [[OMP_IF_END:%.*]]
25503 // CHECK24:       omp_if.else:
25504 // CHECK24-NEXT:    br label [[OMP_INNER_FOR_COND10:%.*]]
25505 // CHECK24:       omp.inner.for.cond10:
25506 // CHECK24-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
25507 // CHECK24-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
25508 // CHECK24-NEXT:    [[CMP11:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]]
25509 // CHECK24-NEXT:    br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY12:%.*]], label [[OMP_INNER_FOR_END26:%.*]]
25510 // CHECK24:       omp.inner.for.body12:
25511 // CHECK24-NEXT:    [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
25512 // CHECK24-NEXT:    [[MUL13:%.*]] = mul nsw i32 [[TMP19]], 1
25513 // CHECK24-NEXT:    [[ADD14:%.*]] = add nsw i32 0, [[MUL13]]
25514 // CHECK24-NEXT:    store i32 [[ADD14]], i32* [[I]], align 4
25515 // CHECK24-NEXT:    [[TMP20:%.*]] = load i32, i32* [[B_ADDR]], align 4
25516 // CHECK24-NEXT:    [[CONV15:%.*]] = sitofp i32 [[TMP20]] to double
25517 // CHECK24-NEXT:    [[ADD16:%.*]] = fadd double [[CONV15]], 1.500000e+00
25518 // CHECK24-NEXT:    [[A17:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
25519 // CHECK24-NEXT:    store double [[ADD16]], double* [[A17]], align 4
25520 // CHECK24-NEXT:    [[A18:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
25521 // CHECK24-NEXT:    [[TMP21:%.*]] = load double, double* [[A18]], align 4
25522 // CHECK24-NEXT:    [[INC19:%.*]] = fadd double [[TMP21]], 1.000000e+00
25523 // CHECK24-NEXT:    store double [[INC19]], double* [[A18]], align 4
25524 // CHECK24-NEXT:    [[CONV20:%.*]] = fptosi double [[INC19]] to i16
25525 // CHECK24-NEXT:    [[TMP22:%.*]] = mul nsw i32 1, [[TMP2]]
25526 // CHECK24-NEXT:    [[ARRAYIDX21:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP22]]
25527 // CHECK24-NEXT:    [[ARRAYIDX22:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX21]], i32 1
25528 // CHECK24-NEXT:    store i16 [[CONV20]], i16* [[ARRAYIDX22]], align 2
25529 // CHECK24-NEXT:    br label [[OMP_BODY_CONTINUE23:%.*]]
25530 // CHECK24:       omp.body.continue23:
25531 // CHECK24-NEXT:    br label [[OMP_INNER_FOR_INC24:%.*]]
25532 // CHECK24:       omp.inner.for.inc24:
25533 // CHECK24-NEXT:    [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
25534 // CHECK24-NEXT:    [[ADD25:%.*]] = add nsw i32 [[TMP23]], 1
25535 // CHECK24-NEXT:    store i32 [[ADD25]], i32* [[DOTOMP_IV]], align 4
25536 // CHECK24-NEXT:    br label [[OMP_INNER_FOR_COND10]], !llvm.loop [[LOOP34:![0-9]+]]
25537 // CHECK24:       omp.inner.for.end26:
25538 // CHECK24-NEXT:    br label [[OMP_IF_END]]
25539 // CHECK24:       omp_if.end:
25540 // CHECK24-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
25541 // CHECK24:       omp.loop.exit:
25542 // CHECK24-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
25543 // CHECK24-NEXT:    [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
25544 // CHECK24-NEXT:    [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0
25545 // CHECK24-NEXT:    br i1 [[TMP25]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
25546 // CHECK24:       .omp.final.then:
25547 // CHECK24-NEXT:    store i32 10, i32* [[I]], align 4
25548 // CHECK24-NEXT:    br label [[DOTOMP_FINAL_DONE]]
25549 // CHECK24:       .omp.final.done:
25550 // CHECK24-NEXT:    ret void
25551 //
25552 //
25553 // CHECK24-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180
25554 // CHECK24-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
25555 // CHECK24-NEXT:  entry:
25556 // CHECK24-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
25557 // CHECK24-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
25558 // CHECK24-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
25559 // CHECK24-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
25560 // CHECK24-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
25561 // CHECK24-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
25562 // CHECK24-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
25563 // CHECK24-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
25564 // CHECK24-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
25565 // CHECK24-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
25566 // CHECK24-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
25567 // CHECK24-NEXT:    store i32 [[TMP1]], i32* [[A_CASTED]], align 4
25568 // CHECK24-NEXT:    [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
25569 // CHECK24-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
25570 // CHECK24-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
25571 // CHECK24-NEXT:    store i16 [[TMP3]], i16* [[CONV1]], align 2
25572 // CHECK24-NEXT:    [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
25573 // CHECK24-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]])
25574 // CHECK24-NEXT:    ret void
25575 //
25576 //
25577 // CHECK24-LABEL: define {{[^@]+}}@.omp_outlined..6
25578 // CHECK24-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {
25579 // CHECK24-NEXT:  entry:
25580 // CHECK24-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
25581 // CHECK24-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
25582 // CHECK24-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
25583 // CHECK24-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
25584 // CHECK24-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
25585 // CHECK24-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
25586 // CHECK24-NEXT:    [[TMP:%.*]] = alloca i32, align 4
25587 // CHECK24-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
25588 // CHECK24-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
25589 // CHECK24-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
25590 // CHECK24-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
25591 // CHECK24-NEXT:    [[I:%.*]] = alloca i32, align 4
25592 // CHECK24-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
25593 // CHECK24-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
25594 // CHECK24-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
25595 // CHECK24-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
25596 // CHECK24-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
25597 // CHECK24-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
25598 // CHECK24-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
25599 // CHECK24-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
25600 // CHECK24-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
25601 // CHECK24-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
25602 // CHECK24-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
25603 // CHECK24-NEXT:    [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
25604 // CHECK24-NEXT:    [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
25605 // CHECK24-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
25606 // CHECK24-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
25607 // CHECK24-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9
25608 // CHECK24-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
25609 // CHECK24:       cond.true:
25610 // CHECK24-NEXT:    br label [[COND_END:%.*]]
25611 // CHECK24:       cond.false:
25612 // CHECK24-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
25613 // CHECK24-NEXT:    br label [[COND_END]]
25614 // CHECK24:       cond.end:
25615 // CHECK24-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
25616 // CHECK24-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
25617 // CHECK24-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
25618 // CHECK24-NEXT:    store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
25619 // CHECK24-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
25620 // CHECK24:       omp.inner.for.cond:
25621 // CHECK24-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36
25622 // CHECK24-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !36
25623 // CHECK24-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
25624 // CHECK24-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
25625 // CHECK24:       omp.inner.for.body:
25626 // CHECK24-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36
25627 // CHECK24-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
25628 // CHECK24-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
25629 // CHECK24-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !36
25630 // CHECK24-NEXT:    [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !36
25631 // CHECK24-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
25632 // CHECK24-NEXT:    store i32 [[ADD2]], i32* [[A_ADDR]], align 4, !llvm.access.group !36
25633 // CHECK24-NEXT:    [[TMP10:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !36
25634 // CHECK24-NEXT:    [[CONV3:%.*]] = sext i16 [[TMP10]] to i32
25635 // CHECK24-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
25636 // CHECK24-NEXT:    [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
25637 // CHECK24-NEXT:    store i16 [[CONV5]], i16* [[CONV]], align 2, !llvm.access.group !36
25638 // CHECK24-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
25639 // CHECK24-NEXT:    [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !36
25640 // CHECK24-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1
25641 // CHECK24-NEXT:    store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !36
25642 // CHECK24-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
25643 // CHECK24:       omp.body.continue:
25644 // CHECK24-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
25645 // CHECK24:       omp.inner.for.inc:
25646 // CHECK24-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36
25647 // CHECK24-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP12]], 1
25648 // CHECK24-NEXT:    store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36
25649 // CHECK24-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP37:![0-9]+]]
25650 // CHECK24:       omp.inner.for.end:
25651 // CHECK24-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
25652 // CHECK24:       omp.loop.exit:
25653 // CHECK24-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
25654 // CHECK24-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
25655 // CHECK24-NEXT:    [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
25656 // CHECK24-NEXT:    br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
25657 // CHECK24:       .omp.final.then:
25658 // CHECK24-NEXT:    store i32 10, i32* [[I]], align 4
25659 // CHECK24-NEXT:    br label [[DOTOMP_FINAL_DONE]]
25660 // CHECK24:       .omp.final.done:
25661 // CHECK24-NEXT:    ret void
25662 //
25663 //
25664 // CHECK25-LABEL: define {{[^@]+}}@_Z3fooi
25665 // CHECK25-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0:[0-9]+]] {
25666 // CHECK25-NEXT:  entry:
25667 // CHECK25-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
25668 // CHECK25-NEXT:    [[A:%.*]] = alloca i32, align 4
25669 // CHECK25-NEXT:    [[AA:%.*]] = alloca i16, align 2
25670 // CHECK25-NEXT:    [[B:%.*]] = alloca [10 x float], align 4
25671 // CHECK25-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 8
25672 // CHECK25-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
25673 // CHECK25-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 8
25674 // CHECK25-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i64, align 8
25675 // CHECK25-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8
25676 // CHECK25-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
25677 // CHECK25-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
25678 // CHECK25-NEXT:    [[TMP:%.*]] = alloca i32, align 4
25679 // CHECK25-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
25680 // CHECK25-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
25681 // CHECK25-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
25682 // CHECK25-NEXT:    [[I:%.*]] = alloca i32, align 4
25683 // CHECK25-NEXT:    [[_TMP4:%.*]] = alloca i32, align 4
25684 // CHECK25-NEXT:    [[DOTOMP_LB5:%.*]] = alloca i32, align 4
25685 // CHECK25-NEXT:    [[DOTOMP_UB6:%.*]] = alloca i32, align 4
25686 // CHECK25-NEXT:    [[DOTOMP_IV7:%.*]] = alloca i32, align 4
25687 // CHECK25-NEXT:    [[DOTLINEAR_START:%.*]] = alloca i32, align 4
25688 // CHECK25-NEXT:    [[A8:%.*]] = alloca i32, align 4
25689 // CHECK25-NEXT:    [[A9:%.*]] = alloca i32, align 4
25690 // CHECK25-NEXT:    [[_TMP20:%.*]] = alloca i32, align 4
25691 // CHECK25-NEXT:    [[DOTOMP_LB21:%.*]] = alloca i32, align 4
25692 // CHECK25-NEXT:    [[DOTOMP_UB22:%.*]] = alloca i32, align 4
25693 // CHECK25-NEXT:    [[DOTOMP_IV23:%.*]] = alloca i32, align 4
25694 // CHECK25-NEXT:    [[I24:%.*]] = alloca i32, align 4
25695 // CHECK25-NEXT:    [[_TMP36:%.*]] = alloca i32, align 4
25696 // CHECK25-NEXT:    [[DOTOMP_LB37:%.*]] = alloca i32, align 4
25697 // CHECK25-NEXT:    [[DOTOMP_UB38:%.*]] = alloca i32, align 4
25698 // CHECK25-NEXT:    [[DOTOMP_IV39:%.*]] = alloca i32, align 4
25699 // CHECK25-NEXT:    [[I40:%.*]] = alloca i32, align 4
25700 // CHECK25-NEXT:    [[_TMP54:%.*]] = alloca i32, align 4
25701 // CHECK25-NEXT:    [[DOTOMP_LB55:%.*]] = alloca i32, align 4
25702 // CHECK25-NEXT:    [[DOTOMP_UB56:%.*]] = alloca i32, align 4
25703 // CHECK25-NEXT:    [[DOTOMP_IV57:%.*]] = alloca i32, align 4
25704 // CHECK25-NEXT:    [[I58:%.*]] = alloca i32, align 4
25705 // CHECK25-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
25706 // CHECK25-NEXT:    store i32 0, i32* [[A]], align 4
25707 // CHECK25-NEXT:    store i16 0, i16* [[AA]], align 2
25708 // CHECK25-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
25709 // CHECK25-NEXT:    [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
25710 // CHECK25-NEXT:    [[TMP2:%.*]] = call i8* @llvm.stacksave()
25711 // CHECK25-NEXT:    store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8
25712 // CHECK25-NEXT:    [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4
25713 // CHECK25-NEXT:    store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8
25714 // CHECK25-NEXT:    [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
25715 // CHECK25-NEXT:    [[TMP4:%.*]] = zext i32 [[TMP3]] to i64
25716 // CHECK25-NEXT:    [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]]
25717 // CHECK25-NEXT:    [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8
25718 // CHECK25-NEXT:    store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8
25719 // CHECK25-NEXT:    [[TMP6:%.*]] = load i32, i32* [[A]], align 4
25720 // CHECK25-NEXT:    store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_]], align 4
25721 // CHECK25-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
25722 // CHECK25-NEXT:    store i32 [[TMP7]], i32* [[DOTCAPTURE_EXPR_2]], align 4
25723 // CHECK25-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
25724 // CHECK25-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
25725 // CHECK25-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
25726 // CHECK25-NEXT:    store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
25727 // CHECK25-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
25728 // CHECK25:       omp.inner.for.cond:
25729 // CHECK25-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
25730 // CHECK25-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !2
25731 // CHECK25-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
25732 // CHECK25-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
25733 // CHECK25:       omp.inner.for.body:
25734 // CHECK25-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
25735 // CHECK25-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
25736 // CHECK25-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
25737 // CHECK25-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !2
25738 // CHECK25-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
25739 // CHECK25:       omp.body.continue:
25740 // CHECK25-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
25741 // CHECK25:       omp.inner.for.inc:
25742 // CHECK25-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
25743 // CHECK25-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1
25744 // CHECK25-NEXT:    store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
25745 // CHECK25-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]
25746 // CHECK25:       omp.inner.for.end:
25747 // CHECK25-NEXT:    store i32 10, i32* [[I]], align 4
25748 // CHECK25-NEXT:    store i32 0, i32* [[DOTOMP_LB5]], align 4
25749 // CHECK25-NEXT:    store i32 9, i32* [[DOTOMP_UB6]], align 4
25750 // CHECK25-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB5]], align 4
25751 // CHECK25-NEXT:    store i32 [[TMP13]], i32* [[DOTOMP_IV7]], align 4
25752 // CHECK25-NEXT:    [[TMP14:%.*]] = load i32, i32* [[A]], align 4
25753 // CHECK25-NEXT:    store i32 [[TMP14]], i32* [[DOTLINEAR_START]], align 4
25754 // CHECK25-NEXT:    br label [[OMP_INNER_FOR_COND10:%.*]]
25755 // CHECK25:       omp.inner.for.cond10:
25756 // CHECK25-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV7]], align 4
25757 // CHECK25-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB6]], align 4
25758 // CHECK25-NEXT:    [[CMP11:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]]
25759 // CHECK25-NEXT:    br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY12:%.*]], label [[OMP_INNER_FOR_END19:%.*]]
25760 // CHECK25:       omp.inner.for.body12:
25761 // CHECK25-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV7]], align 4
25762 // CHECK25-NEXT:    [[MUL13:%.*]] = mul nsw i32 [[TMP17]], 1
25763 // CHECK25-NEXT:    [[ADD14:%.*]] = add nsw i32 0, [[MUL13]]
25764 // CHECK25-NEXT:    store i32 [[ADD14]], i32* [[A8]], align 4
25765 // CHECK25-NEXT:    [[TMP18:%.*]] = load i32, i32* [[A8]], align 4
25766 // CHECK25-NEXT:    [[ADD15:%.*]] = add nsw i32 [[TMP18]], 1
25767 // CHECK25-NEXT:    store i32 [[ADD15]], i32* [[A8]], align 4
25768 // CHECK25-NEXT:    br label [[OMP_BODY_CONTINUE16:%.*]]
25769 // CHECK25:       omp.body.continue16:
25770 // CHECK25-NEXT:    br label [[OMP_INNER_FOR_INC17:%.*]]
25771 // CHECK25:       omp.inner.for.inc17:
25772 // CHECK25-NEXT:    [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV7]], align 4
25773 // CHECK25-NEXT:    [[ADD18:%.*]] = add nsw i32 [[TMP19]], 1
25774 // CHECK25-NEXT:    store i32 [[ADD18]], i32* [[DOTOMP_IV7]], align 4
25775 // CHECK25-NEXT:    br label [[OMP_INNER_FOR_COND10]], !llvm.loop [[LOOP7:![0-9]+]]
25776 // CHECK25:       omp.inner.for.end19:
25777 // CHECK25-NEXT:    store i32 10, i32* [[A]], align 4
25778 // CHECK25-NEXT:    store i32 0, i32* [[DOTOMP_LB21]], align 4
25779 // CHECK25-NEXT:    store i32 9, i32* [[DOTOMP_UB22]], align 4
25780 // CHECK25-NEXT:    [[TMP20:%.*]] = load i32, i32* [[DOTOMP_LB21]], align 4
25781 // CHECK25-NEXT:    store i32 [[TMP20]], i32* [[DOTOMP_IV23]], align 4
25782 // CHECK25-NEXT:    br label [[OMP_INNER_FOR_COND25:%.*]]
25783 // CHECK25:       omp.inner.for.cond25:
25784 // CHECK25-NEXT:    [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV23]], align 4, !llvm.access.group !9
25785 // CHECK25-NEXT:    [[TMP22:%.*]] = load i32, i32* [[DOTOMP_UB22]], align 4, !llvm.access.group !9
25786 // CHECK25-NEXT:    [[CMP26:%.*]] = icmp sle i32 [[TMP21]], [[TMP22]]
25787 // CHECK25-NEXT:    br i1 [[CMP26]], label [[OMP_INNER_FOR_BODY27:%.*]], label [[OMP_INNER_FOR_END35:%.*]]
25788 // CHECK25:       omp.inner.for.body27:
25789 // CHECK25-NEXT:    [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV23]], align 4, !llvm.access.group !9
25790 // CHECK25-NEXT:    [[MUL28:%.*]] = mul nsw i32 [[TMP23]], 1
25791 // CHECK25-NEXT:    [[ADD29:%.*]] = add nsw i32 0, [[MUL28]]
25792 // CHECK25-NEXT:    store i32 [[ADD29]], i32* [[I24]], align 4, !llvm.access.group !9
25793 // CHECK25-NEXT:    [[TMP24:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !9
25794 // CHECK25-NEXT:    [[CONV:%.*]] = sext i16 [[TMP24]] to i32
25795 // CHECK25-NEXT:    [[ADD30:%.*]] = add nsw i32 [[CONV]], 1
25796 // CHECK25-NEXT:    [[CONV31:%.*]] = trunc i32 [[ADD30]] to i16
25797 // CHECK25-NEXT:    store i16 [[CONV31]], i16* [[AA]], align 2, !llvm.access.group !9
25798 // CHECK25-NEXT:    br label [[OMP_BODY_CONTINUE32:%.*]]
25799 // CHECK25:       omp.body.continue32:
25800 // CHECK25-NEXT:    br label [[OMP_INNER_FOR_INC33:%.*]]
25801 // CHECK25:       omp.inner.for.inc33:
25802 // CHECK25-NEXT:    [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IV23]], align 4, !llvm.access.group !9
25803 // CHECK25-NEXT:    [[ADD34:%.*]] = add nsw i32 [[TMP25]], 1
25804 // CHECK25-NEXT:    store i32 [[ADD34]], i32* [[DOTOMP_IV23]], align 4, !llvm.access.group !9
25805 // CHECK25-NEXT:    br label [[OMP_INNER_FOR_COND25]], !llvm.loop [[LOOP10:![0-9]+]]
25806 // CHECK25:       omp.inner.for.end35:
25807 // CHECK25-NEXT:    store i32 10, i32* [[I24]], align 4
25808 // CHECK25-NEXT:    store i32 0, i32* [[DOTOMP_LB37]], align 4
25809 // CHECK25-NEXT:    store i32 9, i32* [[DOTOMP_UB38]], align 4
25810 // CHECK25-NEXT:    [[TMP26:%.*]] = load i32, i32* [[DOTOMP_LB37]], align 4
25811 // CHECK25-NEXT:    store i32 [[TMP26]], i32* [[DOTOMP_IV39]], align 4
25812 // CHECK25-NEXT:    br label [[OMP_INNER_FOR_COND41:%.*]]
25813 // CHECK25:       omp.inner.for.cond41:
25814 // CHECK25-NEXT:    [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV39]], align 4, !llvm.access.group !12
25815 // CHECK25-NEXT:    [[TMP28:%.*]] = load i32, i32* [[DOTOMP_UB38]], align 4, !llvm.access.group !12
25816 // CHECK25-NEXT:    [[CMP42:%.*]] = icmp sle i32 [[TMP27]], [[TMP28]]
25817 // CHECK25-NEXT:    br i1 [[CMP42]], label [[OMP_INNER_FOR_BODY43:%.*]], label [[OMP_INNER_FOR_END53:%.*]]
25818 // CHECK25:       omp.inner.for.body43:
25819 // CHECK25-NEXT:    [[TMP29:%.*]] = load i32, i32* [[DOTOMP_IV39]], align 4, !llvm.access.group !12
25820 // CHECK25-NEXT:    [[MUL44:%.*]] = mul nsw i32 [[TMP29]], 1
25821 // CHECK25-NEXT:    [[ADD45:%.*]] = add nsw i32 0, [[MUL44]]
25822 // CHECK25-NEXT:    store i32 [[ADD45]], i32* [[I40]], align 4, !llvm.access.group !12
25823 // CHECK25-NEXT:    [[TMP30:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !12
25824 // CHECK25-NEXT:    [[ADD46:%.*]] = add nsw i32 [[TMP30]], 1
25825 // CHECK25-NEXT:    store i32 [[ADD46]], i32* [[A]], align 4, !llvm.access.group !12
25826 // CHECK25-NEXT:    [[TMP31:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !12
25827 // CHECK25-NEXT:    [[CONV47:%.*]] = sext i16 [[TMP31]] to i32
25828 // CHECK25-NEXT:    [[ADD48:%.*]] = add nsw i32 [[CONV47]], 1
25829 // CHECK25-NEXT:    [[CONV49:%.*]] = trunc i32 [[ADD48]] to i16
25830 // CHECK25-NEXT:    store i16 [[CONV49]], i16* [[AA]], align 2, !llvm.access.group !12
25831 // CHECK25-NEXT:    br label [[OMP_BODY_CONTINUE50:%.*]]
25832 // CHECK25:       omp.body.continue50:
25833 // CHECK25-NEXT:    br label [[OMP_INNER_FOR_INC51:%.*]]
25834 // CHECK25:       omp.inner.for.inc51:
25835 // CHECK25-NEXT:    [[TMP32:%.*]] = load i32, i32* [[DOTOMP_IV39]], align 4, !llvm.access.group !12
25836 // CHECK25-NEXT:    [[ADD52:%.*]] = add nsw i32 [[TMP32]], 1
25837 // CHECK25-NEXT:    store i32 [[ADD52]], i32* [[DOTOMP_IV39]], align 4, !llvm.access.group !12
25838 // CHECK25-NEXT:    br label [[OMP_INNER_FOR_COND41]], !llvm.loop [[LOOP13:![0-9]+]]
25839 // CHECK25:       omp.inner.for.end53:
25840 // CHECK25-NEXT:    store i32 10, i32* [[I40]], align 4
25841 // CHECK25-NEXT:    store i32 0, i32* [[DOTOMP_LB55]], align 4
25842 // CHECK25-NEXT:    store i32 9, i32* [[DOTOMP_UB56]], align 4
25843 // CHECK25-NEXT:    [[TMP33:%.*]] = load i32, i32* [[DOTOMP_LB55]], align 4
25844 // CHECK25-NEXT:    store i32 [[TMP33]], i32* [[DOTOMP_IV57]], align 4
25845 // CHECK25-NEXT:    [[ARRAYDECAY:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 0
25846 // CHECK25-NEXT:    call void @llvm.assume(i1 true) [ "align"(float* [[ARRAYDECAY]], i64 16) ]
25847 // CHECK25-NEXT:    br label [[OMP_INNER_FOR_COND59:%.*]]
25848 // CHECK25:       omp.inner.for.cond59:
25849 // CHECK25-NEXT:    [[TMP34:%.*]] = load i32, i32* [[DOTOMP_IV57]], align 4, !llvm.access.group !15
25850 // CHECK25-NEXT:    [[TMP35:%.*]] = load i32, i32* [[DOTOMP_UB56]], align 4, !llvm.access.group !15
25851 // CHECK25-NEXT:    [[CMP60:%.*]] = icmp sle i32 [[TMP34]], [[TMP35]]
25852 // CHECK25-NEXT:    br i1 [[CMP60]], label [[OMP_INNER_FOR_BODY61:%.*]], label [[OMP_INNER_FOR_END85:%.*]]
25853 // CHECK25:       omp.inner.for.body61:
25854 // CHECK25-NEXT:    [[TMP36:%.*]] = load i32, i32* [[DOTOMP_IV57]], align 4, !llvm.access.group !15
25855 // CHECK25-NEXT:    [[MUL62:%.*]] = mul nsw i32 [[TMP36]], 1
25856 // CHECK25-NEXT:    [[ADD63:%.*]] = add nsw i32 0, [[MUL62]]
25857 // CHECK25-NEXT:    store i32 [[ADD63]], i32* [[I58]], align 4, !llvm.access.group !15
25858 // CHECK25-NEXT:    [[TMP37:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !15
25859 // CHECK25-NEXT:    [[ADD64:%.*]] = add nsw i32 [[TMP37]], 1
25860 // CHECK25-NEXT:    store i32 [[ADD64]], i32* [[A]], align 4, !llvm.access.group !15
25861 // CHECK25-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2
25862 // CHECK25-NEXT:    [[TMP38:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !15
25863 // CHECK25-NEXT:    [[CONV65:%.*]] = fpext float [[TMP38]] to double
25864 // CHECK25-NEXT:    [[ADD66:%.*]] = fadd double [[CONV65]], 1.000000e+00
25865 // CHECK25-NEXT:    [[CONV67:%.*]] = fptrunc double [[ADD66]] to float
25866 // CHECK25-NEXT:    store float [[CONV67]], float* [[ARRAYIDX]], align 4, !llvm.access.group !15
25867 // CHECK25-NEXT:    [[ARRAYIDX68:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3
25868 // CHECK25-NEXT:    [[TMP39:%.*]] = load float, float* [[ARRAYIDX68]], align 4, !llvm.access.group !15
25869 // CHECK25-NEXT:    [[CONV69:%.*]] = fpext float [[TMP39]] to double
25870 // CHECK25-NEXT:    [[ADD70:%.*]] = fadd double [[CONV69]], 1.000000e+00
25871 // CHECK25-NEXT:    [[CONV71:%.*]] = fptrunc double [[ADD70]] to float
25872 // CHECK25-NEXT:    store float [[CONV71]], float* [[ARRAYIDX68]], align 4, !llvm.access.group !15
25873 // CHECK25-NEXT:    [[ARRAYIDX72:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1
25874 // CHECK25-NEXT:    [[ARRAYIDX73:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX72]], i64 0, i64 2
25875 // CHECK25-NEXT:    [[TMP40:%.*]] = load double, double* [[ARRAYIDX73]], align 8, !llvm.access.group !15
25876 // CHECK25-NEXT:    [[ADD74:%.*]] = fadd double [[TMP40]], 1.000000e+00
25877 // CHECK25-NEXT:    store double [[ADD74]], double* [[ARRAYIDX73]], align 8, !llvm.access.group !15
25878 // CHECK25-NEXT:    [[TMP41:%.*]] = mul nsw i64 1, [[TMP4]]
25879 // CHECK25-NEXT:    [[ARRAYIDX75:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP41]]
25880 // CHECK25-NEXT:    [[ARRAYIDX76:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX75]], i64 3
25881 // CHECK25-NEXT:    [[TMP42:%.*]] = load double, double* [[ARRAYIDX76]], align 8, !llvm.access.group !15
25882 // CHECK25-NEXT:    [[ADD77:%.*]] = fadd double [[TMP42]], 1.000000e+00
25883 // CHECK25-NEXT:    store double [[ADD77]], double* [[ARRAYIDX76]], align 8, !llvm.access.group !15
25884 // CHECK25-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0
25885 // CHECK25-NEXT:    [[TMP43:%.*]] = load i64, i64* [[X]], align 8, !llvm.access.group !15
25886 // CHECK25-NEXT:    [[ADD78:%.*]] = add nsw i64 [[TMP43]], 1
25887 // CHECK25-NEXT:    store i64 [[ADD78]], i64* [[X]], align 8, !llvm.access.group !15
25888 // CHECK25-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1
25889 // CHECK25-NEXT:    [[TMP44:%.*]] = load i8, i8* [[Y]], align 8, !llvm.access.group !15
25890 // CHECK25-NEXT:    [[CONV79:%.*]] = sext i8 [[TMP44]] to i32
25891 // CHECK25-NEXT:    [[ADD80:%.*]] = add nsw i32 [[CONV79]], 1
25892 // CHECK25-NEXT:    [[CONV81:%.*]] = trunc i32 [[ADD80]] to i8
25893 // CHECK25-NEXT:    store i8 [[CONV81]], i8* [[Y]], align 8, !llvm.access.group !15
25894 // CHECK25-NEXT:    br label [[OMP_BODY_CONTINUE82:%.*]]
25895 // CHECK25:       omp.body.continue82:
25896 // CHECK25-NEXT:    br label [[OMP_INNER_FOR_INC83:%.*]]
25897 // CHECK25:       omp.inner.for.inc83:
25898 // CHECK25-NEXT:    [[TMP45:%.*]] = load i32, i32* [[DOTOMP_IV57]], align 4, !llvm.access.group !15
25899 // CHECK25-NEXT:    [[ADD84:%.*]] = add nsw i32 [[TMP45]], 1
25900 // CHECK25-NEXT:    store i32 [[ADD84]], i32* [[DOTOMP_IV57]], align 4, !llvm.access.group !15
25901 // CHECK25-NEXT:    br label [[OMP_INNER_FOR_COND59]], !llvm.loop [[LOOP16:![0-9]+]]
25902 // CHECK25:       omp.inner.for.end85:
25903 // CHECK25-NEXT:    store i32 10, i32* [[I58]], align 4
25904 // CHECK25-NEXT:    [[TMP46:%.*]] = load i32, i32* [[A]], align 4
25905 // CHECK25-NEXT:    [[TMP47:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
25906 // CHECK25-NEXT:    call void @llvm.stackrestore(i8* [[TMP47]])
25907 // CHECK25-NEXT:    ret i32 [[TMP46]]
25908 //
25909 //
25910 // CHECK25-LABEL: define {{[^@]+}}@_Z3bari
25911 // CHECK25-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {
25912 // CHECK25-NEXT:  entry:
25913 // CHECK25-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
25914 // CHECK25-NEXT:    [[A:%.*]] = alloca i32, align 4
25915 // CHECK25-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8
25916 // CHECK25-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
25917 // CHECK25-NEXT:    store i32 0, i32* [[A]], align 4
25918 // CHECK25-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
25919 // CHECK25-NEXT:    [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]])
25920 // CHECK25-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
25921 // CHECK25-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
25922 // CHECK25-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
25923 // CHECK25-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
25924 // CHECK25-NEXT:    [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP2]])
25925 // CHECK25-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
25926 // CHECK25-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
25927 // CHECK25-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
25928 // CHECK25-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
25929 // CHECK25-NEXT:    [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]])
25930 // CHECK25-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
25931 // CHECK25-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
25932 // CHECK25-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
25933 // CHECK25-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
25934 // CHECK25-NEXT:    [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]])
25935 // CHECK25-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
25936 // CHECK25-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
25937 // CHECK25-NEXT:    store i32 [[ADD6]], i32* [[A]], align 4
25938 // CHECK25-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
25939 // CHECK25-NEXT:    ret i32 [[TMP8]]
25940 //
25941 //
25942 // CHECK25-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
25943 // CHECK25-SAME: (%struct.S1* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 {
25944 // CHECK25-NEXT:  entry:
25945 // CHECK25-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
25946 // CHECK25-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
25947 // CHECK25-NEXT:    [[B:%.*]] = alloca i32, align 4
25948 // CHECK25-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 8
25949 // CHECK25-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
25950 // CHECK25-NEXT:    [[TMP:%.*]] = alloca i32, align 4
25951 // CHECK25-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
25952 // CHECK25-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
25953 // CHECK25-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
25954 // CHECK25-NEXT:    [[I:%.*]] = alloca i32, align 4
25955 // CHECK25-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
25956 // CHECK25-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
25957 // CHECK25-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
25958 // CHECK25-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
25959 // CHECK25-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
25960 // CHECK25-NEXT:    store i32 [[ADD]], i32* [[B]], align 4
25961 // CHECK25-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
25962 // CHECK25-NEXT:    [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
25963 // CHECK25-NEXT:    [[TMP3:%.*]] = call i8* @llvm.stacksave()
25964 // CHECK25-NEXT:    store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8
25965 // CHECK25-NEXT:    [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]
25966 // CHECK25-NEXT:    [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2
25967 // CHECK25-NEXT:    store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8
25968 // CHECK25-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
25969 // CHECK25-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
25970 // CHECK25-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
25971 // CHECK25-NEXT:    store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
25972 // CHECK25-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
25973 // CHECK25:       omp.inner.for.cond:
25974 // CHECK25-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
25975 // CHECK25-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !18
25976 // CHECK25-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
25977 // CHECK25-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
25978 // CHECK25:       omp.inner.for.body:
25979 // CHECK25-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
25980 // CHECK25-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
25981 // CHECK25-NEXT:    [[ADD2:%.*]] = add nsw i32 0, [[MUL]]
25982 // CHECK25-NEXT:    store i32 [[ADD2]], i32* [[I]], align 4, !llvm.access.group !18
25983 // CHECK25-NEXT:    [[TMP9:%.*]] = load i32, i32* [[B]], align 4, !llvm.access.group !18
25984 // CHECK25-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP9]] to double
25985 // CHECK25-NEXT:    [[ADD3:%.*]] = fadd double [[CONV]], 1.500000e+00
25986 // CHECK25-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
25987 // CHECK25-NEXT:    store double [[ADD3]], double* [[A]], align 8, !llvm.access.group !18
25988 // CHECK25-NEXT:    [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
25989 // CHECK25-NEXT:    [[TMP10:%.*]] = load double, double* [[A4]], align 8, !llvm.access.group !18
25990 // CHECK25-NEXT:    [[INC:%.*]] = fadd double [[TMP10]], 1.000000e+00
25991 // CHECK25-NEXT:    store double [[INC]], double* [[A4]], align 8, !llvm.access.group !18
25992 // CHECK25-NEXT:    [[CONV5:%.*]] = fptosi double [[INC]] to i16
25993 // CHECK25-NEXT:    [[TMP11:%.*]] = mul nsw i64 1, [[TMP2]]
25994 // CHECK25-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP11]]
25995 // CHECK25-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
25996 // CHECK25-NEXT:    store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2, !llvm.access.group !18
25997 // CHECK25-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
25998 // CHECK25:       omp.body.continue:
25999 // CHECK25-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
26000 // CHECK25:       omp.inner.for.inc:
26001 // CHECK25-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
26002 // CHECK25-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP12]], 1
26003 // CHECK25-NEXT:    store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
26004 // CHECK25-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]
26005 // CHECK25:       omp.inner.for.end:
26006 // CHECK25-NEXT:    store i32 10, i32* [[I]], align 4
26007 // CHECK25-NEXT:    [[TMP13:%.*]] = mul nsw i64 1, [[TMP2]]
26008 // CHECK25-NEXT:    [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP13]]
26009 // CHECK25-NEXT:    [[ARRAYIDX9:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX8]], i64 1
26010 // CHECK25-NEXT:    [[TMP14:%.*]] = load i16, i16* [[ARRAYIDX9]], align 2
26011 // CHECK25-NEXT:    [[CONV10:%.*]] = sext i16 [[TMP14]] to i32
26012 // CHECK25-NEXT:    [[TMP15:%.*]] = load i32, i32* [[B]], align 4
26013 // CHECK25-NEXT:    [[ADD11:%.*]] = add nsw i32 [[CONV10]], [[TMP15]]
26014 // CHECK25-NEXT:    [[TMP16:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
26015 // CHECK25-NEXT:    call void @llvm.stackrestore(i8* [[TMP16]])
26016 // CHECK25-NEXT:    ret i32 [[ADD11]]
26017 //
26018 //
26019 // CHECK25-LABEL: define {{[^@]+}}@_ZL7fstatici
26020 // CHECK25-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {
26021 // CHECK25-NEXT:  entry:
26022 // CHECK25-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
26023 // CHECK25-NEXT:    [[A:%.*]] = alloca i32, align 4
26024 // CHECK25-NEXT:    [[AA:%.*]] = alloca i16, align 2
26025 // CHECK25-NEXT:    [[AAA:%.*]] = alloca i8, align 1
26026 // CHECK25-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
26027 // CHECK25-NEXT:    [[TMP:%.*]] = alloca i32, align 4
26028 // CHECK25-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
26029 // CHECK25-NEXT:    [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
26030 // CHECK25-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
26031 // CHECK25-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
26032 // CHECK25-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
26033 // CHECK25-NEXT:    [[I:%.*]] = alloca i32, align 4
26034 // CHECK25-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
26035 // CHECK25-NEXT:    [[I5:%.*]] = alloca i32, align 4
26036 // CHECK25-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
26037 // CHECK25-NEXT:    store i32 0, i32* [[A]], align 4
26038 // CHECK25-NEXT:    store i16 0, i16* [[AA]], align 2
26039 // CHECK25-NEXT:    store i8 0, i8* [[AAA]], align 1
26040 // CHECK25-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
26041 // CHECK25-NEXT:    store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4
26042 // CHECK25-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
26043 // CHECK25-NEXT:    store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_1]], align 4
26044 // CHECK25-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
26045 // CHECK25-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
26046 // CHECK25-NEXT:    [[SUB:%.*]] = sub i32 [[TMP2]], [[TMP3]]
26047 // CHECK25-NEXT:    [[SUB3:%.*]] = sub i32 [[SUB]], 1
26048 // CHECK25-NEXT:    [[ADD:%.*]] = add i32 [[SUB3]], 1
26049 // CHECK25-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], 1
26050 // CHECK25-NEXT:    [[SUB4:%.*]] = sub i32 [[DIV]], 1
26051 // CHECK25-NEXT:    store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_2]], align 4
26052 // CHECK25-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
26053 // CHECK25-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
26054 // CHECK25-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_UB]], align 4
26055 // CHECK25-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
26056 // CHECK25-NEXT:    store i32 [[TMP5]], i32* [[I]], align 4
26057 // CHECK25-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
26058 // CHECK25-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
26059 // CHECK25-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]]
26060 // CHECK25-NEXT:    br i1 [[CMP]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END:%.*]]
26061 // CHECK25:       simd.if.then:
26062 // CHECK25-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
26063 // CHECK25-NEXT:    store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
26064 // CHECK25-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
26065 // CHECK25:       omp.inner.for.cond:
26066 // CHECK25-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
26067 // CHECK25-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !21
26068 // CHECK25-NEXT:    [[ADD6:%.*]] = add i32 [[TMP10]], 1
26069 // CHECK25-NEXT:    [[CMP7:%.*]] = icmp ult i32 [[TMP9]], [[ADD6]]
26070 // CHECK25-NEXT:    br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
26071 // CHECK25:       omp.inner.for.body:
26072 // CHECK25-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group !21
26073 // CHECK25-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
26074 // CHECK25-NEXT:    [[MUL:%.*]] = mul i32 [[TMP12]], 1
26075 // CHECK25-NEXT:    [[ADD8:%.*]] = add i32 [[TMP11]], [[MUL]]
26076 // CHECK25-NEXT:    store i32 [[ADD8]], i32* [[I5]], align 4, !llvm.access.group !21
26077 // CHECK25-NEXT:    [[TMP13:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !21
26078 // CHECK25-NEXT:    [[ADD9:%.*]] = add nsw i32 [[TMP13]], 1
26079 // CHECK25-NEXT:    store i32 [[ADD9]], i32* [[A]], align 4, !llvm.access.group !21
26080 // CHECK25-NEXT:    [[TMP14:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !21
26081 // CHECK25-NEXT:    [[CONV:%.*]] = sext i16 [[TMP14]] to i32
26082 // CHECK25-NEXT:    [[ADD10:%.*]] = add nsw i32 [[CONV]], 1
26083 // CHECK25-NEXT:    [[CONV11:%.*]] = trunc i32 [[ADD10]] to i16
26084 // CHECK25-NEXT:    store i16 [[CONV11]], i16* [[AA]], align 2, !llvm.access.group !21
26085 // CHECK25-NEXT:    [[TMP15:%.*]] = load i8, i8* [[AAA]], align 1, !llvm.access.group !21
26086 // CHECK25-NEXT:    [[CONV12:%.*]] = sext i8 [[TMP15]] to i32
26087 // CHECK25-NEXT:    [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1
26088 // CHECK25-NEXT:    [[CONV14:%.*]] = trunc i32 [[ADD13]] to i8
26089 // CHECK25-NEXT:    store i8 [[CONV14]], i8* [[AAA]], align 1, !llvm.access.group !21
26090 // CHECK25-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2
26091 // CHECK25-NEXT:    [[TMP16:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !21
26092 // CHECK25-NEXT:    [[ADD15:%.*]] = add nsw i32 [[TMP16]], 1
26093 // CHECK25-NEXT:    store i32 [[ADD15]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !21
26094 // CHECK25-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
26095 // CHECK25:       omp.body.continue:
26096 // CHECK25-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
26097 // CHECK25:       omp.inner.for.inc:
26098 // CHECK25-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
26099 // CHECK25-NEXT:    [[ADD16:%.*]] = add i32 [[TMP17]], 1
26100 // CHECK25-NEXT:    store i32 [[ADD16]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
26101 // CHECK25-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]]
26102 // CHECK25:       omp.inner.for.end:
26103 // CHECK25-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
26104 // CHECK25-NEXT:    [[TMP19:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
26105 // CHECK25-NEXT:    [[TMP20:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
26106 // CHECK25-NEXT:    [[SUB17:%.*]] = sub i32 [[TMP19]], [[TMP20]]
26107 // CHECK25-NEXT:    [[SUB18:%.*]] = sub i32 [[SUB17]], 1
26108 // CHECK25-NEXT:    [[ADD19:%.*]] = add i32 [[SUB18]], 1
26109 // CHECK25-NEXT:    [[DIV20:%.*]] = udiv i32 [[ADD19]], 1
26110 // CHECK25-NEXT:    [[MUL21:%.*]] = mul i32 [[DIV20]], 1
26111 // CHECK25-NEXT:    [[ADD22:%.*]] = add i32 [[TMP18]], [[MUL21]]
26112 // CHECK25-NEXT:    store i32 [[ADD22]], i32* [[I5]], align 4
26113 // CHECK25-NEXT:    br label [[SIMD_IF_END]]
26114 // CHECK25:       simd.if.end:
26115 // CHECK25-NEXT:    [[TMP21:%.*]] = load i32, i32* [[A]], align 4
26116 // CHECK25-NEXT:    ret i32 [[TMP21]]
26117 //
26118 //
26119 // CHECK25-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
26120 // CHECK25-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat {
26121 // CHECK25-NEXT:  entry:
26122 // CHECK25-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
26123 // CHECK25-NEXT:    [[A:%.*]] = alloca i32, align 4
26124 // CHECK25-NEXT:    [[AA:%.*]] = alloca i16, align 2
26125 // CHECK25-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
26126 // CHECK25-NEXT:    [[TMP:%.*]] = alloca i32, align 4
26127 // CHECK25-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
26128 // CHECK25-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
26129 // CHECK25-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
26130 // CHECK25-NEXT:    [[I:%.*]] = alloca i32, align 4
26131 // CHECK25-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
26132 // CHECK25-NEXT:    store i32 0, i32* [[A]], align 4
26133 // CHECK25-NEXT:    store i16 0, i16* [[AA]], align 2
26134 // CHECK25-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
26135 // CHECK25-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
26136 // CHECK25-NEXT:    [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
26137 // CHECK25-NEXT:    store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4
26138 // CHECK25-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
26139 // CHECK25:       omp.inner.for.cond:
26140 // CHECK25-NEXT:    [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
26141 // CHECK25-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !24
26142 // CHECK25-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
26143 // CHECK25-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
26144 // CHECK25:       omp.inner.for.body:
26145 // CHECK25-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
26146 // CHECK25-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1
26147 // CHECK25-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
26148 // CHECK25-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !24
26149 // CHECK25-NEXT:    [[TMP4:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !24
26150 // CHECK25-NEXT:    [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1
26151 // CHECK25-NEXT:    store i32 [[ADD1]], i32* [[A]], align 4, !llvm.access.group !24
26152 // CHECK25-NEXT:    [[TMP5:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !24
26153 // CHECK25-NEXT:    [[CONV:%.*]] = sext i16 [[TMP5]] to i32
26154 // CHECK25-NEXT:    [[ADD2:%.*]] = add nsw i32 [[CONV]], 1
26155 // CHECK25-NEXT:    [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
26156 // CHECK25-NEXT:    store i16 [[CONV3]], i16* [[AA]], align 2, !llvm.access.group !24
26157 // CHECK25-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2
26158 // CHECK25-NEXT:    [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !24
26159 // CHECK25-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP6]], 1
26160 // CHECK25-NEXT:    store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !24
26161 // CHECK25-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
26162 // CHECK25:       omp.body.continue:
26163 // CHECK25-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
26164 // CHECK25:       omp.inner.for.inc:
26165 // CHECK25-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
26166 // CHECK25-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP7]], 1
26167 // CHECK25-NEXT:    store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
26168 // CHECK25-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]]
26169 // CHECK25:       omp.inner.for.end:
26170 // CHECK25-NEXT:    store i32 10, i32* [[I]], align 4
26171 // CHECK25-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
26172 // CHECK25-NEXT:    ret i32 [[TMP8]]
26173 //
26174 //
26175 // CHECK26-LABEL: define {{[^@]+}}@_Z3fooi
26176 // CHECK26-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0:[0-9]+]] {
26177 // CHECK26-NEXT:  entry:
26178 // CHECK26-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
26179 // CHECK26-NEXT:    [[A:%.*]] = alloca i32, align 4
26180 // CHECK26-NEXT:    [[AA:%.*]] = alloca i16, align 2
26181 // CHECK26-NEXT:    [[B:%.*]] = alloca [10 x float], align 4
26182 // CHECK26-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 8
26183 // CHECK26-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
26184 // CHECK26-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 8
26185 // CHECK26-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i64, align 8
26186 // CHECK26-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8
26187 // CHECK26-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
26188 // CHECK26-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
26189 // CHECK26-NEXT:    [[TMP:%.*]] = alloca i32, align 4
26190 // CHECK26-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
26191 // CHECK26-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
26192 // CHECK26-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
26193 // CHECK26-NEXT:    [[I:%.*]] = alloca i32, align 4
26194 // CHECK26-NEXT:    [[_TMP4:%.*]] = alloca i32, align 4
26195 // CHECK26-NEXT:    [[DOTOMP_LB5:%.*]] = alloca i32, align 4
26196 // CHECK26-NEXT:    [[DOTOMP_UB6:%.*]] = alloca i32, align 4
26197 // CHECK26-NEXT:    [[DOTOMP_IV7:%.*]] = alloca i32, align 4
26198 // CHECK26-NEXT:    [[DOTLINEAR_START:%.*]] = alloca i32, align 4
26199 // CHECK26-NEXT:    [[A8:%.*]] = alloca i32, align 4
26200 // CHECK26-NEXT:    [[A9:%.*]] = alloca i32, align 4
26201 // CHECK26-NEXT:    [[_TMP20:%.*]] = alloca i32, align 4
26202 // CHECK26-NEXT:    [[DOTOMP_LB21:%.*]] = alloca i32, align 4
26203 // CHECK26-NEXT:    [[DOTOMP_UB22:%.*]] = alloca i32, align 4
26204 // CHECK26-NEXT:    [[DOTOMP_IV23:%.*]] = alloca i32, align 4
26205 // CHECK26-NEXT:    [[I24:%.*]] = alloca i32, align 4
26206 // CHECK26-NEXT:    [[_TMP36:%.*]] = alloca i32, align 4
26207 // CHECK26-NEXT:    [[DOTOMP_LB37:%.*]] = alloca i32, align 4
26208 // CHECK26-NEXT:    [[DOTOMP_UB38:%.*]] = alloca i32, align 4
26209 // CHECK26-NEXT:    [[DOTOMP_IV39:%.*]] = alloca i32, align 4
26210 // CHECK26-NEXT:    [[I40:%.*]] = alloca i32, align 4
26211 // CHECK26-NEXT:    [[_TMP54:%.*]] = alloca i32, align 4
26212 // CHECK26-NEXT:    [[DOTOMP_LB55:%.*]] = alloca i32, align 4
26213 // CHECK26-NEXT:    [[DOTOMP_UB56:%.*]] = alloca i32, align 4
26214 // CHECK26-NEXT:    [[DOTOMP_IV57:%.*]] = alloca i32, align 4
26215 // CHECK26-NEXT:    [[I58:%.*]] = alloca i32, align 4
26216 // CHECK26-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
26217 // CHECK26-NEXT:    store i32 0, i32* [[A]], align 4
26218 // CHECK26-NEXT:    store i16 0, i16* [[AA]], align 2
26219 // CHECK26-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
26220 // CHECK26-NEXT:    [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
26221 // CHECK26-NEXT:    [[TMP2:%.*]] = call i8* @llvm.stacksave()
26222 // CHECK26-NEXT:    store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8
26223 // CHECK26-NEXT:    [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4
26224 // CHECK26-NEXT:    store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8
26225 // CHECK26-NEXT:    [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
26226 // CHECK26-NEXT:    [[TMP4:%.*]] = zext i32 [[TMP3]] to i64
26227 // CHECK26-NEXT:    [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]]
26228 // CHECK26-NEXT:    [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8
26229 // CHECK26-NEXT:    store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8
26230 // CHECK26-NEXT:    [[TMP6:%.*]] = load i32, i32* [[A]], align 4
26231 // CHECK26-NEXT:    store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_]], align 4
26232 // CHECK26-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
26233 // CHECK26-NEXT:    store i32 [[TMP7]], i32* [[DOTCAPTURE_EXPR_2]], align 4
26234 // CHECK26-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
26235 // CHECK26-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
26236 // CHECK26-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
26237 // CHECK26-NEXT:    store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
26238 // CHECK26-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
26239 // CHECK26:       omp.inner.for.cond:
26240 // CHECK26-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
26241 // CHECK26-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !2
26242 // CHECK26-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
26243 // CHECK26-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
26244 // CHECK26:       omp.inner.for.body:
26245 // CHECK26-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
26246 // CHECK26-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
26247 // CHECK26-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
26248 // CHECK26-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !2
26249 // CHECK26-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
26250 // CHECK26:       omp.body.continue:
26251 // CHECK26-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
26252 // CHECK26:       omp.inner.for.inc:
26253 // CHECK26-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
26254 // CHECK26-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1
26255 // CHECK26-NEXT:    store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
26256 // CHECK26-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]
26257 // CHECK26:       omp.inner.for.end:
26258 // CHECK26-NEXT:    store i32 10, i32* [[I]], align 4
26259 // CHECK26-NEXT:    store i32 0, i32* [[DOTOMP_LB5]], align 4
26260 // CHECK26-NEXT:    store i32 9, i32* [[DOTOMP_UB6]], align 4
26261 // CHECK26-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB5]], align 4
26262 // CHECK26-NEXT:    store i32 [[TMP13]], i32* [[DOTOMP_IV7]], align 4
26263 // CHECK26-NEXT:    [[TMP14:%.*]] = load i32, i32* [[A]], align 4
26264 // CHECK26-NEXT:    store i32 [[TMP14]], i32* [[DOTLINEAR_START]], align 4
26265 // CHECK26-NEXT:    br label [[OMP_INNER_FOR_COND10:%.*]]
26266 // CHECK26:       omp.inner.for.cond10:
26267 // CHECK26-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV7]], align 4
26268 // CHECK26-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB6]], align 4
26269 // CHECK26-NEXT:    [[CMP11:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]]
26270 // CHECK26-NEXT:    br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY12:%.*]], label [[OMP_INNER_FOR_END19:%.*]]
26271 // CHECK26:       omp.inner.for.body12:
26272 // CHECK26-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV7]], align 4
26273 // CHECK26-NEXT:    [[MUL13:%.*]] = mul nsw i32 [[TMP17]], 1
26274 // CHECK26-NEXT:    [[ADD14:%.*]] = add nsw i32 0, [[MUL13]]
26275 // CHECK26-NEXT:    store i32 [[ADD14]], i32* [[A8]], align 4
26276 // CHECK26-NEXT:    [[TMP18:%.*]] = load i32, i32* [[A8]], align 4
26277 // CHECK26-NEXT:    [[ADD15:%.*]] = add nsw i32 [[TMP18]], 1
26278 // CHECK26-NEXT:    store i32 [[ADD15]], i32* [[A8]], align 4
26279 // CHECK26-NEXT:    br label [[OMP_BODY_CONTINUE16:%.*]]
26280 // CHECK26:       omp.body.continue16:
26281 // CHECK26-NEXT:    br label [[OMP_INNER_FOR_INC17:%.*]]
26282 // CHECK26:       omp.inner.for.inc17:
26283 // CHECK26-NEXT:    [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV7]], align 4
26284 // CHECK26-NEXT:    [[ADD18:%.*]] = add nsw i32 [[TMP19]], 1
26285 // CHECK26-NEXT:    store i32 [[ADD18]], i32* [[DOTOMP_IV7]], align 4
26286 // CHECK26-NEXT:    br label [[OMP_INNER_FOR_COND10]], !llvm.loop [[LOOP7:![0-9]+]]
26287 // CHECK26:       omp.inner.for.end19:
26288 // CHECK26-NEXT:    store i32 10, i32* [[A]], align 4
26289 // CHECK26-NEXT:    store i32 0, i32* [[DOTOMP_LB21]], align 4
26290 // CHECK26-NEXT:    store i32 9, i32* [[DOTOMP_UB22]], align 4
26291 // CHECK26-NEXT:    [[TMP20:%.*]] = load i32, i32* [[DOTOMP_LB21]], align 4
26292 // CHECK26-NEXT:    store i32 [[TMP20]], i32* [[DOTOMP_IV23]], align 4
26293 // CHECK26-NEXT:    br label [[OMP_INNER_FOR_COND25:%.*]]
26294 // CHECK26:       omp.inner.for.cond25:
26295 // CHECK26-NEXT:    [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV23]], align 4, !llvm.access.group !9
26296 // CHECK26-NEXT:    [[TMP22:%.*]] = load i32, i32* [[DOTOMP_UB22]], align 4, !llvm.access.group !9
26297 // CHECK26-NEXT:    [[CMP26:%.*]] = icmp sle i32 [[TMP21]], [[TMP22]]
26298 // CHECK26-NEXT:    br i1 [[CMP26]], label [[OMP_INNER_FOR_BODY27:%.*]], label [[OMP_INNER_FOR_END35:%.*]]
26299 // CHECK26:       omp.inner.for.body27:
26300 // CHECK26-NEXT:    [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV23]], align 4, !llvm.access.group !9
26301 // CHECK26-NEXT:    [[MUL28:%.*]] = mul nsw i32 [[TMP23]], 1
26302 // CHECK26-NEXT:    [[ADD29:%.*]] = add nsw i32 0, [[MUL28]]
26303 // CHECK26-NEXT:    store i32 [[ADD29]], i32* [[I24]], align 4, !llvm.access.group !9
26304 // CHECK26-NEXT:    [[TMP24:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !9
26305 // CHECK26-NEXT:    [[CONV:%.*]] = sext i16 [[TMP24]] to i32
26306 // CHECK26-NEXT:    [[ADD30:%.*]] = add nsw i32 [[CONV]], 1
26307 // CHECK26-NEXT:    [[CONV31:%.*]] = trunc i32 [[ADD30]] to i16
26308 // CHECK26-NEXT:    store i16 [[CONV31]], i16* [[AA]], align 2, !llvm.access.group !9
26309 // CHECK26-NEXT:    br label [[OMP_BODY_CONTINUE32:%.*]]
26310 // CHECK26:       omp.body.continue32:
26311 // CHECK26-NEXT:    br label [[OMP_INNER_FOR_INC33:%.*]]
26312 // CHECK26:       omp.inner.for.inc33:
26313 // CHECK26-NEXT:    [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IV23]], align 4, !llvm.access.group !9
26314 // CHECK26-NEXT:    [[ADD34:%.*]] = add nsw i32 [[TMP25]], 1
26315 // CHECK26-NEXT:    store i32 [[ADD34]], i32* [[DOTOMP_IV23]], align 4, !llvm.access.group !9
26316 // CHECK26-NEXT:    br label [[OMP_INNER_FOR_COND25]], !llvm.loop [[LOOP10:![0-9]+]]
26317 // CHECK26:       omp.inner.for.end35:
26318 // CHECK26-NEXT:    store i32 10, i32* [[I24]], align 4
26319 // CHECK26-NEXT:    store i32 0, i32* [[DOTOMP_LB37]], align 4
26320 // CHECK26-NEXT:    store i32 9, i32* [[DOTOMP_UB38]], align 4
26321 // CHECK26-NEXT:    [[TMP26:%.*]] = load i32, i32* [[DOTOMP_LB37]], align 4
26322 // CHECK26-NEXT:    store i32 [[TMP26]], i32* [[DOTOMP_IV39]], align 4
26323 // CHECK26-NEXT:    br label [[OMP_INNER_FOR_COND41:%.*]]
26324 // CHECK26:       omp.inner.for.cond41:
26325 // CHECK26-NEXT:    [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV39]], align 4, !llvm.access.group !12
26326 // CHECK26-NEXT:    [[TMP28:%.*]] = load i32, i32* [[DOTOMP_UB38]], align 4, !llvm.access.group !12
26327 // CHECK26-NEXT:    [[CMP42:%.*]] = icmp sle i32 [[TMP27]], [[TMP28]]
26328 // CHECK26-NEXT:    br i1 [[CMP42]], label [[OMP_INNER_FOR_BODY43:%.*]], label [[OMP_INNER_FOR_END53:%.*]]
26329 // CHECK26:       omp.inner.for.body43:
26330 // CHECK26-NEXT:    [[TMP29:%.*]] = load i32, i32* [[DOTOMP_IV39]], align 4, !llvm.access.group !12
26331 // CHECK26-NEXT:    [[MUL44:%.*]] = mul nsw i32 [[TMP29]], 1
26332 // CHECK26-NEXT:    [[ADD45:%.*]] = add nsw i32 0, [[MUL44]]
26333 // CHECK26-NEXT:    store i32 [[ADD45]], i32* [[I40]], align 4, !llvm.access.group !12
26334 // CHECK26-NEXT:    [[TMP30:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !12
26335 // CHECK26-NEXT:    [[ADD46:%.*]] = add nsw i32 [[TMP30]], 1
26336 // CHECK26-NEXT:    store i32 [[ADD46]], i32* [[A]], align 4, !llvm.access.group !12
26337 // CHECK26-NEXT:    [[TMP31:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !12
26338 // CHECK26-NEXT:    [[CONV47:%.*]] = sext i16 [[TMP31]] to i32
26339 // CHECK26-NEXT:    [[ADD48:%.*]] = add nsw i32 [[CONV47]], 1
26340 // CHECK26-NEXT:    [[CONV49:%.*]] = trunc i32 [[ADD48]] to i16
26341 // CHECK26-NEXT:    store i16 [[CONV49]], i16* [[AA]], align 2, !llvm.access.group !12
26342 // CHECK26-NEXT:    br label [[OMP_BODY_CONTINUE50:%.*]]
26343 // CHECK26:       omp.body.continue50:
26344 // CHECK26-NEXT:    br label [[OMP_INNER_FOR_INC51:%.*]]
26345 // CHECK26:       omp.inner.for.inc51:
26346 // CHECK26-NEXT:    [[TMP32:%.*]] = load i32, i32* [[DOTOMP_IV39]], align 4, !llvm.access.group !12
26347 // CHECK26-NEXT:    [[ADD52:%.*]] = add nsw i32 [[TMP32]], 1
26348 // CHECK26-NEXT:    store i32 [[ADD52]], i32* [[DOTOMP_IV39]], align 4, !llvm.access.group !12
26349 // CHECK26-NEXT:    br label [[OMP_INNER_FOR_COND41]], !llvm.loop [[LOOP13:![0-9]+]]
26350 // CHECK26:       omp.inner.for.end53:
26351 // CHECK26-NEXT:    store i32 10, i32* [[I40]], align 4
26352 // CHECK26-NEXT:    store i32 0, i32* [[DOTOMP_LB55]], align 4
26353 // CHECK26-NEXT:    store i32 9, i32* [[DOTOMP_UB56]], align 4
26354 // CHECK26-NEXT:    [[TMP33:%.*]] = load i32, i32* [[DOTOMP_LB55]], align 4
26355 // CHECK26-NEXT:    store i32 [[TMP33]], i32* [[DOTOMP_IV57]], align 4
26356 // CHECK26-NEXT:    [[ARRAYDECAY:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 0
26357 // CHECK26-NEXT:    call void @llvm.assume(i1 true) [ "align"(float* [[ARRAYDECAY]], i64 16) ]
26358 // CHECK26-NEXT:    br label [[OMP_INNER_FOR_COND59:%.*]]
26359 // CHECK26:       omp.inner.for.cond59:
26360 // CHECK26-NEXT:    [[TMP34:%.*]] = load i32, i32* [[DOTOMP_IV57]], align 4, !llvm.access.group !15
26361 // CHECK26-NEXT:    [[TMP35:%.*]] = load i32, i32* [[DOTOMP_UB56]], align 4, !llvm.access.group !15
26362 // CHECK26-NEXT:    [[CMP60:%.*]] = icmp sle i32 [[TMP34]], [[TMP35]]
26363 // CHECK26-NEXT:    br i1 [[CMP60]], label [[OMP_INNER_FOR_BODY61:%.*]], label [[OMP_INNER_FOR_END85:%.*]]
26364 // CHECK26:       omp.inner.for.body61:
26365 // CHECK26-NEXT:    [[TMP36:%.*]] = load i32, i32* [[DOTOMP_IV57]], align 4, !llvm.access.group !15
26366 // CHECK26-NEXT:    [[MUL62:%.*]] = mul nsw i32 [[TMP36]], 1
26367 // CHECK26-NEXT:    [[ADD63:%.*]] = add nsw i32 0, [[MUL62]]
26368 // CHECK26-NEXT:    store i32 [[ADD63]], i32* [[I58]], align 4, !llvm.access.group !15
26369 // CHECK26-NEXT:    [[TMP37:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !15
26370 // CHECK26-NEXT:    [[ADD64:%.*]] = add nsw i32 [[TMP37]], 1
26371 // CHECK26-NEXT:    store i32 [[ADD64]], i32* [[A]], align 4, !llvm.access.group !15
26372 // CHECK26-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2
26373 // CHECK26-NEXT:    [[TMP38:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !15
26374 // CHECK26-NEXT:    [[CONV65:%.*]] = fpext float [[TMP38]] to double
26375 // CHECK26-NEXT:    [[ADD66:%.*]] = fadd double [[CONV65]], 1.000000e+00
26376 // CHECK26-NEXT:    [[CONV67:%.*]] = fptrunc double [[ADD66]] to float
26377 // CHECK26-NEXT:    store float [[CONV67]], float* [[ARRAYIDX]], align 4, !llvm.access.group !15
26378 // CHECK26-NEXT:    [[ARRAYIDX68:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3
26379 // CHECK26-NEXT:    [[TMP39:%.*]] = load float, float* [[ARRAYIDX68]], align 4, !llvm.access.group !15
26380 // CHECK26-NEXT:    [[CONV69:%.*]] = fpext float [[TMP39]] to double
26381 // CHECK26-NEXT:    [[ADD70:%.*]] = fadd double [[CONV69]], 1.000000e+00
26382 // CHECK26-NEXT:    [[CONV71:%.*]] = fptrunc double [[ADD70]] to float
26383 // CHECK26-NEXT:    store float [[CONV71]], float* [[ARRAYIDX68]], align 4, !llvm.access.group !15
26384 // CHECK26-NEXT:    [[ARRAYIDX72:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1
26385 // CHECK26-NEXT:    [[ARRAYIDX73:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX72]], i64 0, i64 2
26386 // CHECK26-NEXT:    [[TMP40:%.*]] = load double, double* [[ARRAYIDX73]], align 8, !llvm.access.group !15
26387 // CHECK26-NEXT:    [[ADD74:%.*]] = fadd double [[TMP40]], 1.000000e+00
26388 // CHECK26-NEXT:    store double [[ADD74]], double* [[ARRAYIDX73]], align 8, !llvm.access.group !15
26389 // CHECK26-NEXT:    [[TMP41:%.*]] = mul nsw i64 1, [[TMP4]]
26390 // CHECK26-NEXT:    [[ARRAYIDX75:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP41]]
26391 // CHECK26-NEXT:    [[ARRAYIDX76:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX75]], i64 3
26392 // CHECK26-NEXT:    [[TMP42:%.*]] = load double, double* [[ARRAYIDX76]], align 8, !llvm.access.group !15
26393 // CHECK26-NEXT:    [[ADD77:%.*]] = fadd double [[TMP42]], 1.000000e+00
26394 // CHECK26-NEXT:    store double [[ADD77]], double* [[ARRAYIDX76]], align 8, !llvm.access.group !15
26395 // CHECK26-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0
26396 // CHECK26-NEXT:    [[TMP43:%.*]] = load i64, i64* [[X]], align 8, !llvm.access.group !15
26397 // CHECK26-NEXT:    [[ADD78:%.*]] = add nsw i64 [[TMP43]], 1
26398 // CHECK26-NEXT:    store i64 [[ADD78]], i64* [[X]], align 8, !llvm.access.group !15
26399 // CHECK26-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1
26400 // CHECK26-NEXT:    [[TMP44:%.*]] = load i8, i8* [[Y]], align 8, !llvm.access.group !15
26401 // CHECK26-NEXT:    [[CONV79:%.*]] = sext i8 [[TMP44]] to i32
26402 // CHECK26-NEXT:    [[ADD80:%.*]] = add nsw i32 [[CONV79]], 1
26403 // CHECK26-NEXT:    [[CONV81:%.*]] = trunc i32 [[ADD80]] to i8
26404 // CHECK26-NEXT:    store i8 [[CONV81]], i8* [[Y]], align 8, !llvm.access.group !15
26405 // CHECK26-NEXT:    br label [[OMP_BODY_CONTINUE82:%.*]]
26406 // CHECK26:       omp.body.continue82:
26407 // CHECK26-NEXT:    br label [[OMP_INNER_FOR_INC83:%.*]]
26408 // CHECK26:       omp.inner.for.inc83:
26409 // CHECK26-NEXT:    [[TMP45:%.*]] = load i32, i32* [[DOTOMP_IV57]], align 4, !llvm.access.group !15
26410 // CHECK26-NEXT:    [[ADD84:%.*]] = add nsw i32 [[TMP45]], 1
26411 // CHECK26-NEXT:    store i32 [[ADD84]], i32* [[DOTOMP_IV57]], align 4, !llvm.access.group !15
26412 // CHECK26-NEXT:    br label [[OMP_INNER_FOR_COND59]], !llvm.loop [[LOOP16:![0-9]+]]
26413 // CHECK26:       omp.inner.for.end85:
26414 // CHECK26-NEXT:    store i32 10, i32* [[I58]], align 4
26415 // CHECK26-NEXT:    [[TMP46:%.*]] = load i32, i32* [[A]], align 4
26416 // CHECK26-NEXT:    [[TMP47:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
26417 // CHECK26-NEXT:    call void @llvm.stackrestore(i8* [[TMP47]])
26418 // CHECK26-NEXT:    ret i32 [[TMP46]]
26419 //
26420 //
26421 // CHECK26-LABEL: define {{[^@]+}}@_Z3bari
26422 // CHECK26-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {
26423 // CHECK26-NEXT:  entry:
26424 // CHECK26-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
26425 // CHECK26-NEXT:    [[A:%.*]] = alloca i32, align 4
26426 // CHECK26-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8
26427 // CHECK26-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
26428 // CHECK26-NEXT:    store i32 0, i32* [[A]], align 4
26429 // CHECK26-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
26430 // CHECK26-NEXT:    [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]])
26431 // CHECK26-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
26432 // CHECK26-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
26433 // CHECK26-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
26434 // CHECK26-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
26435 // CHECK26-NEXT:    [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP2]])
26436 // CHECK26-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
26437 // CHECK26-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
26438 // CHECK26-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
26439 // CHECK26-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
26440 // CHECK26-NEXT:    [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]])
26441 // CHECK26-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
26442 // CHECK26-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
26443 // CHECK26-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
26444 // CHECK26-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
26445 // CHECK26-NEXT:    [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]])
26446 // CHECK26-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
26447 // CHECK26-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
26448 // CHECK26-NEXT:    store i32 [[ADD6]], i32* [[A]], align 4
26449 // CHECK26-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
26450 // CHECK26-NEXT:    ret i32 [[TMP8]]
26451 //
26452 //
26453 // CHECK26-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
26454 // CHECK26-SAME: (%struct.S1* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 {
26455 // CHECK26-NEXT:  entry:
26456 // CHECK26-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
26457 // CHECK26-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
26458 // CHECK26-NEXT:    [[B:%.*]] = alloca i32, align 4
26459 // CHECK26-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 8
26460 // CHECK26-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
26461 // CHECK26-NEXT:    [[TMP:%.*]] = alloca i32, align 4
26462 // CHECK26-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
26463 // CHECK26-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
26464 // CHECK26-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
26465 // CHECK26-NEXT:    [[I:%.*]] = alloca i32, align 4
26466 // CHECK26-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
26467 // CHECK26-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
26468 // CHECK26-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
26469 // CHECK26-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
26470 // CHECK26-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
26471 // CHECK26-NEXT:    store i32 [[ADD]], i32* [[B]], align 4
26472 // CHECK26-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
26473 // CHECK26-NEXT:    [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
26474 // CHECK26-NEXT:    [[TMP3:%.*]] = call i8* @llvm.stacksave()
26475 // CHECK26-NEXT:    store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8
26476 // CHECK26-NEXT:    [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]
26477 // CHECK26-NEXT:    [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2
26478 // CHECK26-NEXT:    store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8
26479 // CHECK26-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
26480 // CHECK26-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
26481 // CHECK26-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
26482 // CHECK26-NEXT:    store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
26483 // CHECK26-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
26484 // CHECK26:       omp.inner.for.cond:
26485 // CHECK26-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
26486 // CHECK26-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !18
26487 // CHECK26-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
26488 // CHECK26-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
26489 // CHECK26:       omp.inner.for.body:
26490 // CHECK26-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
26491 // CHECK26-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
26492 // CHECK26-NEXT:    [[ADD2:%.*]] = add nsw i32 0, [[MUL]]
26493 // CHECK26-NEXT:    store i32 [[ADD2]], i32* [[I]], align 4, !llvm.access.group !18
26494 // CHECK26-NEXT:    [[TMP9:%.*]] = load i32, i32* [[B]], align 4, !llvm.access.group !18
26495 // CHECK26-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP9]] to double
26496 // CHECK26-NEXT:    [[ADD3:%.*]] = fadd double [[CONV]], 1.500000e+00
26497 // CHECK26-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
26498 // CHECK26-NEXT:    store double [[ADD3]], double* [[A]], align 8, !llvm.access.group !18
26499 // CHECK26-NEXT:    [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
26500 // CHECK26-NEXT:    [[TMP10:%.*]] = load double, double* [[A4]], align 8, !llvm.access.group !18
26501 // CHECK26-NEXT:    [[INC:%.*]] = fadd double [[TMP10]], 1.000000e+00
26502 // CHECK26-NEXT:    store double [[INC]], double* [[A4]], align 8, !llvm.access.group !18
26503 // CHECK26-NEXT:    [[CONV5:%.*]] = fptosi double [[INC]] to i16
26504 // CHECK26-NEXT:    [[TMP11:%.*]] = mul nsw i64 1, [[TMP2]]
26505 // CHECK26-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP11]]
26506 // CHECK26-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
26507 // CHECK26-NEXT:    store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2, !llvm.access.group !18
26508 // CHECK26-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
26509 // CHECK26:       omp.body.continue:
26510 // CHECK26-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
26511 // CHECK26:       omp.inner.for.inc:
26512 // CHECK26-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
26513 // CHECK26-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP12]], 1
26514 // CHECK26-NEXT:    store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
26515 // CHECK26-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]
26516 // CHECK26:       omp.inner.for.end:
26517 // CHECK26-NEXT:    store i32 10, i32* [[I]], align 4
26518 // CHECK26-NEXT:    [[TMP13:%.*]] = mul nsw i64 1, [[TMP2]]
26519 // CHECK26-NEXT:    [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP13]]
26520 // CHECK26-NEXT:    [[ARRAYIDX9:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX8]], i64 1
26521 // CHECK26-NEXT:    [[TMP14:%.*]] = load i16, i16* [[ARRAYIDX9]], align 2
26522 // CHECK26-NEXT:    [[CONV10:%.*]] = sext i16 [[TMP14]] to i32
26523 // CHECK26-NEXT:    [[TMP15:%.*]] = load i32, i32* [[B]], align 4
26524 // CHECK26-NEXT:    [[ADD11:%.*]] = add nsw i32 [[CONV10]], [[TMP15]]
26525 // CHECK26-NEXT:    [[TMP16:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
26526 // CHECK26-NEXT:    call void @llvm.stackrestore(i8* [[TMP16]])
26527 // CHECK26-NEXT:    ret i32 [[ADD11]]
26528 //
26529 //
26530 // CHECK26-LABEL: define {{[^@]+}}@_ZL7fstatici
26531 // CHECK26-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {
26532 // CHECK26-NEXT:  entry:
26533 // CHECK26-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
26534 // CHECK26-NEXT:    [[A:%.*]] = alloca i32, align 4
26535 // CHECK26-NEXT:    [[AA:%.*]] = alloca i16, align 2
26536 // CHECK26-NEXT:    [[AAA:%.*]] = alloca i8, align 1
26537 // CHECK26-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
26538 // CHECK26-NEXT:    [[TMP:%.*]] = alloca i32, align 4
26539 // CHECK26-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
26540 // CHECK26-NEXT:    [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
26541 // CHECK26-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
26542 // CHECK26-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
26543 // CHECK26-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
26544 // CHECK26-NEXT:    [[I:%.*]] = alloca i32, align 4
26545 // CHECK26-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
26546 // CHECK26-NEXT:    [[I5:%.*]] = alloca i32, align 4
26547 // CHECK26-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
26548 // CHECK26-NEXT:    store i32 0, i32* [[A]], align 4
26549 // CHECK26-NEXT:    store i16 0, i16* [[AA]], align 2
26550 // CHECK26-NEXT:    store i8 0, i8* [[AAA]], align 1
26551 // CHECK26-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
26552 // CHECK26-NEXT:    store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4
26553 // CHECK26-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
26554 // CHECK26-NEXT:    store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_1]], align 4
26555 // CHECK26-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
26556 // CHECK26-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
26557 // CHECK26-NEXT:    [[SUB:%.*]] = sub i32 [[TMP2]], [[TMP3]]
26558 // CHECK26-NEXT:    [[SUB3:%.*]] = sub i32 [[SUB]], 1
26559 // CHECK26-NEXT:    [[ADD:%.*]] = add i32 [[SUB3]], 1
26560 // CHECK26-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], 1
26561 // CHECK26-NEXT:    [[SUB4:%.*]] = sub i32 [[DIV]], 1
26562 // CHECK26-NEXT:    store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_2]], align 4
26563 // CHECK26-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
26564 // CHECK26-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
26565 // CHECK26-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_UB]], align 4
26566 // CHECK26-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
26567 // CHECK26-NEXT:    store i32 [[TMP5]], i32* [[I]], align 4
26568 // CHECK26-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
26569 // CHECK26-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
26570 // CHECK26-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]]
26571 // CHECK26-NEXT:    br i1 [[CMP]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END:%.*]]
26572 // CHECK26:       simd.if.then:
26573 // CHECK26-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
26574 // CHECK26-NEXT:    store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
26575 // CHECK26-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
26576 // CHECK26:       omp.inner.for.cond:
26577 // CHECK26-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
26578 // CHECK26-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !21
26579 // CHECK26-NEXT:    [[ADD6:%.*]] = add i32 [[TMP10]], 1
26580 // CHECK26-NEXT:    [[CMP7:%.*]] = icmp ult i32 [[TMP9]], [[ADD6]]
26581 // CHECK26-NEXT:    br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
26582 // CHECK26:       omp.inner.for.body:
26583 // CHECK26-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group !21
26584 // CHECK26-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
26585 // CHECK26-NEXT:    [[MUL:%.*]] = mul i32 [[TMP12]], 1
26586 // CHECK26-NEXT:    [[ADD8:%.*]] = add i32 [[TMP11]], [[MUL]]
26587 // CHECK26-NEXT:    store i32 [[ADD8]], i32* [[I5]], align 4, !llvm.access.group !21
26588 // CHECK26-NEXT:    [[TMP13:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !21
26589 // CHECK26-NEXT:    [[ADD9:%.*]] = add nsw i32 [[TMP13]], 1
26590 // CHECK26-NEXT:    store i32 [[ADD9]], i32* [[A]], align 4, !llvm.access.group !21
26591 // CHECK26-NEXT:    [[TMP14:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !21
26592 // CHECK26-NEXT:    [[CONV:%.*]] = sext i16 [[TMP14]] to i32
26593 // CHECK26-NEXT:    [[ADD10:%.*]] = add nsw i32 [[CONV]], 1
26594 // CHECK26-NEXT:    [[CONV11:%.*]] = trunc i32 [[ADD10]] to i16
26595 // CHECK26-NEXT:    store i16 [[CONV11]], i16* [[AA]], align 2, !llvm.access.group !21
26596 // CHECK26-NEXT:    [[TMP15:%.*]] = load i8, i8* [[AAA]], align 1, !llvm.access.group !21
26597 // CHECK26-NEXT:    [[CONV12:%.*]] = sext i8 [[TMP15]] to i32
26598 // CHECK26-NEXT:    [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1
26599 // CHECK26-NEXT:    [[CONV14:%.*]] = trunc i32 [[ADD13]] to i8
26600 // CHECK26-NEXT:    store i8 [[CONV14]], i8* [[AAA]], align 1, !llvm.access.group !21
26601 // CHECK26-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2
26602 // CHECK26-NEXT:    [[TMP16:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !21
26603 // CHECK26-NEXT:    [[ADD15:%.*]] = add nsw i32 [[TMP16]], 1
26604 // CHECK26-NEXT:    store i32 [[ADD15]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !21
26605 // CHECK26-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
26606 // CHECK26:       omp.body.continue:
26607 // CHECK26-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
26608 // CHECK26:       omp.inner.for.inc:
26609 // CHECK26-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
26610 // CHECK26-NEXT:    [[ADD16:%.*]] = add i32 [[TMP17]], 1
26611 // CHECK26-NEXT:    store i32 [[ADD16]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
26612 // CHECK26-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]]
26613 // CHECK26:       omp.inner.for.end:
26614 // CHECK26-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
26615 // CHECK26-NEXT:    [[TMP19:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
26616 // CHECK26-NEXT:    [[TMP20:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
26617 // CHECK26-NEXT:    [[SUB17:%.*]] = sub i32 [[TMP19]], [[TMP20]]
26618 // CHECK26-NEXT:    [[SUB18:%.*]] = sub i32 [[SUB17]], 1
26619 // CHECK26-NEXT:    [[ADD19:%.*]] = add i32 [[SUB18]], 1
26620 // CHECK26-NEXT:    [[DIV20:%.*]] = udiv i32 [[ADD19]], 1
26621 // CHECK26-NEXT:    [[MUL21:%.*]] = mul i32 [[DIV20]], 1
26622 // CHECK26-NEXT:    [[ADD22:%.*]] = add i32 [[TMP18]], [[MUL21]]
26623 // CHECK26-NEXT:    store i32 [[ADD22]], i32* [[I5]], align 4
26624 // CHECK26-NEXT:    br label [[SIMD_IF_END]]
26625 // CHECK26:       simd.if.end:
26626 // CHECK26-NEXT:    [[TMP21:%.*]] = load i32, i32* [[A]], align 4
26627 // CHECK26-NEXT:    ret i32 [[TMP21]]
26628 //
26629 //
26630 // CHECK26-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
26631 // CHECK26-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat {
26632 // CHECK26-NEXT:  entry:
26633 // CHECK26-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
26634 // CHECK26-NEXT:    [[A:%.*]] = alloca i32, align 4
26635 // CHECK26-NEXT:    [[AA:%.*]] = alloca i16, align 2
26636 // CHECK26-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
26637 // CHECK26-NEXT:    [[TMP:%.*]] = alloca i32, align 4
26638 // CHECK26-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
26639 // CHECK26-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
26640 // CHECK26-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
26641 // CHECK26-NEXT:    [[I:%.*]] = alloca i32, align 4
26642 // CHECK26-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
26643 // CHECK26-NEXT:    store i32 0, i32* [[A]], align 4
26644 // CHECK26-NEXT:    store i16 0, i16* [[AA]], align 2
26645 // CHECK26-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
26646 // CHECK26-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
26647 // CHECK26-NEXT:    [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
26648 // CHECK26-NEXT:    store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4
26649 // CHECK26-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
26650 // CHECK26:       omp.inner.for.cond:
26651 // CHECK26-NEXT:    [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
26652 // CHECK26-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !24
26653 // CHECK26-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
26654 // CHECK26-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
26655 // CHECK26:       omp.inner.for.body:
26656 // CHECK26-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
26657 // CHECK26-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1
26658 // CHECK26-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
26659 // CHECK26-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !24
26660 // CHECK26-NEXT:    [[TMP4:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !24
26661 // CHECK26-NEXT:    [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1
26662 // CHECK26-NEXT:    store i32 [[ADD1]], i32* [[A]], align 4, !llvm.access.group !24
26663 // CHECK26-NEXT:    [[TMP5:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !24
26664 // CHECK26-NEXT:    [[CONV:%.*]] = sext i16 [[TMP5]] to i32
26665 // CHECK26-NEXT:    [[ADD2:%.*]] = add nsw i32 [[CONV]], 1
26666 // CHECK26-NEXT:    [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
26667 // CHECK26-NEXT:    store i16 [[CONV3]], i16* [[AA]], align 2, !llvm.access.group !24
26668 // CHECK26-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2
26669 // CHECK26-NEXT:    [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !24
26670 // CHECK26-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP6]], 1
26671 // CHECK26-NEXT:    store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !24
26672 // CHECK26-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
26673 // CHECK26:       omp.body.continue:
26674 // CHECK26-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
26675 // CHECK26:       omp.inner.for.inc:
26676 // CHECK26-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
26677 // CHECK26-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP7]], 1
26678 // CHECK26-NEXT:    store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
26679 // CHECK26-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]]
26680 // CHECK26:       omp.inner.for.end:
26681 // CHECK26-NEXT:    store i32 10, i32* [[I]], align 4
26682 // CHECK26-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
26683 // CHECK26-NEXT:    ret i32 [[TMP8]]
26684 //
26685 //
26686 // CHECK27-LABEL: define {{[^@]+}}@_Z3fooi
26687 // CHECK27-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0:[0-9]+]] {
26688 // CHECK27-NEXT:  entry:
26689 // CHECK27-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
26690 // CHECK27-NEXT:    [[A:%.*]] = alloca i32, align 4
26691 // CHECK27-NEXT:    [[AA:%.*]] = alloca i16, align 2
26692 // CHECK27-NEXT:    [[B:%.*]] = alloca [10 x float], align 4
26693 // CHECK27-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 4
26694 // CHECK27-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 4
26695 // CHECK27-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 8
26696 // CHECK27-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i32, align 4
26697 // CHECK27-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4
26698 // CHECK27-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
26699 // CHECK27-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
26700 // CHECK27-NEXT:    [[TMP:%.*]] = alloca i32, align 4
26701 // CHECK27-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
26702 // CHECK27-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
26703 // CHECK27-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
26704 // CHECK27-NEXT:    [[I:%.*]] = alloca i32, align 4
26705 // CHECK27-NEXT:    [[_TMP4:%.*]] = alloca i32, align 4
26706 // CHECK27-NEXT:    [[DOTOMP_LB5:%.*]] = alloca i32, align 4
26707 // CHECK27-NEXT:    [[DOTOMP_UB6:%.*]] = alloca i32, align 4
26708 // CHECK27-NEXT:    [[DOTOMP_IV7:%.*]] = alloca i32, align 4
26709 // CHECK27-NEXT:    [[DOTLINEAR_START:%.*]] = alloca i32, align 4
26710 // CHECK27-NEXT:    [[A8:%.*]] = alloca i32, align 4
26711 // CHECK27-NEXT:    [[A9:%.*]] = alloca i32, align 4
26712 // CHECK27-NEXT:    [[_TMP20:%.*]] = alloca i32, align 4
26713 // CHECK27-NEXT:    [[DOTOMP_LB21:%.*]] = alloca i32, align 4
26714 // CHECK27-NEXT:    [[DOTOMP_UB22:%.*]] = alloca i32, align 4
26715 // CHECK27-NEXT:    [[DOTOMP_IV23:%.*]] = alloca i32, align 4
26716 // CHECK27-NEXT:    [[I24:%.*]] = alloca i32, align 4
26717 // CHECK27-NEXT:    [[_TMP36:%.*]] = alloca i32, align 4
26718 // CHECK27-NEXT:    [[DOTOMP_LB37:%.*]] = alloca i32, align 4
26719 // CHECK27-NEXT:    [[DOTOMP_UB38:%.*]] = alloca i32, align 4
26720 // CHECK27-NEXT:    [[DOTOMP_IV39:%.*]] = alloca i32, align 4
26721 // CHECK27-NEXT:    [[I40:%.*]] = alloca i32, align 4
26722 // CHECK27-NEXT:    [[_TMP54:%.*]] = alloca i32, align 4
26723 // CHECK27-NEXT:    [[DOTOMP_LB55:%.*]] = alloca i32, align 4
26724 // CHECK27-NEXT:    [[DOTOMP_UB56:%.*]] = alloca i32, align 4
26725 // CHECK27-NEXT:    [[DOTOMP_IV57:%.*]] = alloca i32, align 4
26726 // CHECK27-NEXT:    [[I58:%.*]] = alloca i32, align 4
26727 // CHECK27-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
26728 // CHECK27-NEXT:    store i32 0, i32* [[A]], align 4
26729 // CHECK27-NEXT:    store i16 0, i16* [[AA]], align 2
26730 // CHECK27-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
26731 // CHECK27-NEXT:    [[TMP1:%.*]] = call i8* @llvm.stacksave()
26732 // CHECK27-NEXT:    store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4
26733 // CHECK27-NEXT:    [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4
26734 // CHECK27-NEXT:    store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4
26735 // CHECK27-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
26736 // CHECK27-NEXT:    [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]]
26737 // CHECK27-NEXT:    [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8
26738 // CHECK27-NEXT:    store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4
26739 // CHECK27-NEXT:    [[TMP4:%.*]] = load i32, i32* [[A]], align 4
26740 // CHECK27-NEXT:    store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4
26741 // CHECK27-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
26742 // CHECK27-NEXT:    store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_2]], align 4
26743 // CHECK27-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
26744 // CHECK27-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
26745 // CHECK27-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
26746 // CHECK27-NEXT:    store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
26747 // CHECK27-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
26748 // CHECK27:       omp.inner.for.cond:
26749 // CHECK27-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
26750 // CHECK27-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !3
26751 // CHECK27-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
26752 // CHECK27-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
26753 // CHECK27:       omp.inner.for.body:
26754 // CHECK27-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
26755 // CHECK27-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
26756 // CHECK27-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
26757 // CHECK27-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !3
26758 // CHECK27-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
26759 // CHECK27:       omp.body.continue:
26760 // CHECK27-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
26761 // CHECK27:       omp.inner.for.inc:
26762 // CHECK27-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
26763 // CHECK27-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
26764 // CHECK27-NEXT:    store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
26765 // CHECK27-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]
26766 // CHECK27:       omp.inner.for.end:
26767 // CHECK27-NEXT:    store i32 10, i32* [[I]], align 4
26768 // CHECK27-NEXT:    store i32 0, i32* [[DOTOMP_LB5]], align 4
26769 // CHECK27-NEXT:    store i32 9, i32* [[DOTOMP_UB6]], align 4
26770 // CHECK27-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_LB5]], align 4
26771 // CHECK27-NEXT:    store i32 [[TMP11]], i32* [[DOTOMP_IV7]], align 4
26772 // CHECK27-NEXT:    [[TMP12:%.*]] = load i32, i32* [[A]], align 4
26773 // CHECK27-NEXT:    store i32 [[TMP12]], i32* [[DOTLINEAR_START]], align 4
26774 // CHECK27-NEXT:    br label [[OMP_INNER_FOR_COND10:%.*]]
26775 // CHECK27:       omp.inner.for.cond10:
26776 // CHECK27-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV7]], align 4
26777 // CHECK27-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB6]], align 4
26778 // CHECK27-NEXT:    [[CMP11:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
26779 // CHECK27-NEXT:    br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY12:%.*]], label [[OMP_INNER_FOR_END19:%.*]]
26780 // CHECK27:       omp.inner.for.body12:
26781 // CHECK27-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV7]], align 4
26782 // CHECK27-NEXT:    [[MUL13:%.*]] = mul nsw i32 [[TMP15]], 1
26783 // CHECK27-NEXT:    [[ADD14:%.*]] = add nsw i32 0, [[MUL13]]
26784 // CHECK27-NEXT:    store i32 [[ADD14]], i32* [[A8]], align 4
26785 // CHECK27-NEXT:    [[TMP16:%.*]] = load i32, i32* [[A8]], align 4
26786 // CHECK27-NEXT:    [[ADD15:%.*]] = add nsw i32 [[TMP16]], 1
26787 // CHECK27-NEXT:    store i32 [[ADD15]], i32* [[A8]], align 4
26788 // CHECK27-NEXT:    br label [[OMP_BODY_CONTINUE16:%.*]]
26789 // CHECK27:       omp.body.continue16:
26790 // CHECK27-NEXT:    br label [[OMP_INNER_FOR_INC17:%.*]]
26791 // CHECK27:       omp.inner.for.inc17:
26792 // CHECK27-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV7]], align 4
26793 // CHECK27-NEXT:    [[ADD18:%.*]] = add nsw i32 [[TMP17]], 1
26794 // CHECK27-NEXT:    store i32 [[ADD18]], i32* [[DOTOMP_IV7]], align 4
26795 // CHECK27-NEXT:    br label [[OMP_INNER_FOR_COND10]], !llvm.loop [[LOOP8:![0-9]+]]
26796 // CHECK27:       omp.inner.for.end19:
26797 // CHECK27-NEXT:    store i32 10, i32* [[A]], align 4
26798 // CHECK27-NEXT:    store i32 0, i32* [[DOTOMP_LB21]], align 4
26799 // CHECK27-NEXT:    store i32 9, i32* [[DOTOMP_UB22]], align 4
26800 // CHECK27-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTOMP_LB21]], align 4
26801 // CHECK27-NEXT:    store i32 [[TMP18]], i32* [[DOTOMP_IV23]], align 4
26802 // CHECK27-NEXT:    br label [[OMP_INNER_FOR_COND25:%.*]]
26803 // CHECK27:       omp.inner.for.cond25:
26804 // CHECK27-NEXT:    [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV23]], align 4, !llvm.access.group !10
26805 // CHECK27-NEXT:    [[TMP20:%.*]] = load i32, i32* [[DOTOMP_UB22]], align 4, !llvm.access.group !10
26806 // CHECK27-NEXT:    [[CMP26:%.*]] = icmp sle i32 [[TMP19]], [[TMP20]]
26807 // CHECK27-NEXT:    br i1 [[CMP26]], label [[OMP_INNER_FOR_BODY27:%.*]], label [[OMP_INNER_FOR_END35:%.*]]
26808 // CHECK27:       omp.inner.for.body27:
26809 // CHECK27-NEXT:    [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV23]], align 4, !llvm.access.group !10
26810 // CHECK27-NEXT:    [[MUL28:%.*]] = mul nsw i32 [[TMP21]], 1
26811 // CHECK27-NEXT:    [[ADD29:%.*]] = add nsw i32 0, [[MUL28]]
26812 // CHECK27-NEXT:    store i32 [[ADD29]], i32* [[I24]], align 4, !llvm.access.group !10
26813 // CHECK27-NEXT:    [[TMP22:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !10
26814 // CHECK27-NEXT:    [[CONV:%.*]] = sext i16 [[TMP22]] to i32
26815 // CHECK27-NEXT:    [[ADD30:%.*]] = add nsw i32 [[CONV]], 1
26816 // CHECK27-NEXT:    [[CONV31:%.*]] = trunc i32 [[ADD30]] to i16
26817 // CHECK27-NEXT:    store i16 [[CONV31]], i16* [[AA]], align 2, !llvm.access.group !10
26818 // CHECK27-NEXT:    br label [[OMP_BODY_CONTINUE32:%.*]]
26819 // CHECK27:       omp.body.continue32:
26820 // CHECK27-NEXT:    br label [[OMP_INNER_FOR_INC33:%.*]]
26821 // CHECK27:       omp.inner.for.inc33:
26822 // CHECK27-NEXT:    [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV23]], align 4, !llvm.access.group !10
26823 // CHECK27-NEXT:    [[ADD34:%.*]] = add nsw i32 [[TMP23]], 1
26824 // CHECK27-NEXT:    store i32 [[ADD34]], i32* [[DOTOMP_IV23]], align 4, !llvm.access.group !10
26825 // CHECK27-NEXT:    br label [[OMP_INNER_FOR_COND25]], !llvm.loop [[LOOP11:![0-9]+]]
26826 // CHECK27:       omp.inner.for.end35:
26827 // CHECK27-NEXT:    store i32 10, i32* [[I24]], align 4
26828 // CHECK27-NEXT:    store i32 0, i32* [[DOTOMP_LB37]], align 4
26829 // CHECK27-NEXT:    store i32 9, i32* [[DOTOMP_UB38]], align 4
26830 // CHECK27-NEXT:    [[TMP24:%.*]] = load i32, i32* [[DOTOMP_LB37]], align 4
26831 // CHECK27-NEXT:    store i32 [[TMP24]], i32* [[DOTOMP_IV39]], align 4
26832 // CHECK27-NEXT:    br label [[OMP_INNER_FOR_COND41:%.*]]
26833 // CHECK27:       omp.inner.for.cond41:
26834 // CHECK27-NEXT:    [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IV39]], align 4, !llvm.access.group !13
26835 // CHECK27-NEXT:    [[TMP26:%.*]] = load i32, i32* [[DOTOMP_UB38]], align 4, !llvm.access.group !13
26836 // CHECK27-NEXT:    [[CMP42:%.*]] = icmp sle i32 [[TMP25]], [[TMP26]]
26837 // CHECK27-NEXT:    br i1 [[CMP42]], label [[OMP_INNER_FOR_BODY43:%.*]], label [[OMP_INNER_FOR_END53:%.*]]
26838 // CHECK27:       omp.inner.for.body43:
26839 // CHECK27-NEXT:    [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV39]], align 4, !llvm.access.group !13
26840 // CHECK27-NEXT:    [[MUL44:%.*]] = mul nsw i32 [[TMP27]], 1
26841 // CHECK27-NEXT:    [[ADD45:%.*]] = add nsw i32 0, [[MUL44]]
26842 // CHECK27-NEXT:    store i32 [[ADD45]], i32* [[I40]], align 4, !llvm.access.group !13
26843 // CHECK27-NEXT:    [[TMP28:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !13
26844 // CHECK27-NEXT:    [[ADD46:%.*]] = add nsw i32 [[TMP28]], 1
26845 // CHECK27-NEXT:    store i32 [[ADD46]], i32* [[A]], align 4, !llvm.access.group !13
26846 // CHECK27-NEXT:    [[TMP29:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !13
26847 // CHECK27-NEXT:    [[CONV47:%.*]] = sext i16 [[TMP29]] to i32
26848 // CHECK27-NEXT:    [[ADD48:%.*]] = add nsw i32 [[CONV47]], 1
26849 // CHECK27-NEXT:    [[CONV49:%.*]] = trunc i32 [[ADD48]] to i16
26850 // CHECK27-NEXT:    store i16 [[CONV49]], i16* [[AA]], align 2, !llvm.access.group !13
26851 // CHECK27-NEXT:    br label [[OMP_BODY_CONTINUE50:%.*]]
26852 // CHECK27:       omp.body.continue50:
26853 // CHECK27-NEXT:    br label [[OMP_INNER_FOR_INC51:%.*]]
26854 // CHECK27:       omp.inner.for.inc51:
26855 // CHECK27-NEXT:    [[TMP30:%.*]] = load i32, i32* [[DOTOMP_IV39]], align 4, !llvm.access.group !13
26856 // CHECK27-NEXT:    [[ADD52:%.*]] = add nsw i32 [[TMP30]], 1
26857 // CHECK27-NEXT:    store i32 [[ADD52]], i32* [[DOTOMP_IV39]], align 4, !llvm.access.group !13
26858 // CHECK27-NEXT:    br label [[OMP_INNER_FOR_COND41]], !llvm.loop [[LOOP14:![0-9]+]]
26859 // CHECK27:       omp.inner.for.end53:
26860 // CHECK27-NEXT:    store i32 10, i32* [[I40]], align 4
26861 // CHECK27-NEXT:    store i32 0, i32* [[DOTOMP_LB55]], align 4
26862 // CHECK27-NEXT:    store i32 9, i32* [[DOTOMP_UB56]], align 4
26863 // CHECK27-NEXT:    [[TMP31:%.*]] = load i32, i32* [[DOTOMP_LB55]], align 4
26864 // CHECK27-NEXT:    store i32 [[TMP31]], i32* [[DOTOMP_IV57]], align 4
26865 // CHECK27-NEXT:    [[ARRAYDECAY:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 0
26866 // CHECK27-NEXT:    call void @llvm.assume(i1 true) [ "align"(float* [[ARRAYDECAY]], i32 16) ]
26867 // CHECK27-NEXT:    br label [[OMP_INNER_FOR_COND59:%.*]]
26868 // CHECK27:       omp.inner.for.cond59:
26869 // CHECK27-NEXT:    [[TMP32:%.*]] = load i32, i32* [[DOTOMP_IV57]], align 4, !llvm.access.group !16
26870 // CHECK27-NEXT:    [[TMP33:%.*]] = load i32, i32* [[DOTOMP_UB56]], align 4, !llvm.access.group !16
26871 // CHECK27-NEXT:    [[CMP60:%.*]] = icmp sle i32 [[TMP32]], [[TMP33]]
26872 // CHECK27-NEXT:    br i1 [[CMP60]], label [[OMP_INNER_FOR_BODY61:%.*]], label [[OMP_INNER_FOR_END85:%.*]]
26873 // CHECK27:       omp.inner.for.body61:
26874 // CHECK27-NEXT:    [[TMP34:%.*]] = load i32, i32* [[DOTOMP_IV57]], align 4, !llvm.access.group !16
26875 // CHECK27-NEXT:    [[MUL62:%.*]] = mul nsw i32 [[TMP34]], 1
26876 // CHECK27-NEXT:    [[ADD63:%.*]] = add nsw i32 0, [[MUL62]]
26877 // CHECK27-NEXT:    store i32 [[ADD63]], i32* [[I58]], align 4, !llvm.access.group !16
26878 // CHECK27-NEXT:    [[TMP35:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !16
26879 // CHECK27-NEXT:    [[ADD64:%.*]] = add nsw i32 [[TMP35]], 1
26880 // CHECK27-NEXT:    store i32 [[ADD64]], i32* [[A]], align 4, !llvm.access.group !16
26881 // CHECK27-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2
26882 // CHECK27-NEXT:    [[TMP36:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !16
26883 // CHECK27-NEXT:    [[CONV65:%.*]] = fpext float [[TMP36]] to double
26884 // CHECK27-NEXT:    [[ADD66:%.*]] = fadd double [[CONV65]], 1.000000e+00
26885 // CHECK27-NEXT:    [[CONV67:%.*]] = fptrunc double [[ADD66]] to float
26886 // CHECK27-NEXT:    store float [[CONV67]], float* [[ARRAYIDX]], align 4, !llvm.access.group !16
26887 // CHECK27-NEXT:    [[ARRAYIDX68:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3
26888 // CHECK27-NEXT:    [[TMP37:%.*]] = load float, float* [[ARRAYIDX68]], align 4, !llvm.access.group !16
26889 // CHECK27-NEXT:    [[CONV69:%.*]] = fpext float [[TMP37]] to double
26890 // CHECK27-NEXT:    [[ADD70:%.*]] = fadd double [[CONV69]], 1.000000e+00
26891 // CHECK27-NEXT:    [[CONV71:%.*]] = fptrunc double [[ADD70]] to float
26892 // CHECK27-NEXT:    store float [[CONV71]], float* [[ARRAYIDX68]], align 4, !llvm.access.group !16
26893 // CHECK27-NEXT:    [[ARRAYIDX72:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1
26894 // CHECK27-NEXT:    [[ARRAYIDX73:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX72]], i32 0, i32 2
26895 // CHECK27-NEXT:    [[TMP38:%.*]] = load double, double* [[ARRAYIDX73]], align 8, !llvm.access.group !16
26896 // CHECK27-NEXT:    [[ADD74:%.*]] = fadd double [[TMP38]], 1.000000e+00
26897 // CHECK27-NEXT:    store double [[ADD74]], double* [[ARRAYIDX73]], align 8, !llvm.access.group !16
26898 // CHECK27-NEXT:    [[TMP39:%.*]] = mul nsw i32 1, [[TMP2]]
26899 // CHECK27-NEXT:    [[ARRAYIDX75:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP39]]
26900 // CHECK27-NEXT:    [[ARRAYIDX76:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX75]], i32 3
26901 // CHECK27-NEXT:    [[TMP40:%.*]] = load double, double* [[ARRAYIDX76]], align 8, !llvm.access.group !16
26902 // CHECK27-NEXT:    [[ADD77:%.*]] = fadd double [[TMP40]], 1.000000e+00
26903 // CHECK27-NEXT:    store double [[ADD77]], double* [[ARRAYIDX76]], align 8, !llvm.access.group !16
26904 // CHECK27-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0
26905 // CHECK27-NEXT:    [[TMP41:%.*]] = load i64, i64* [[X]], align 4, !llvm.access.group !16
26906 // CHECK27-NEXT:    [[ADD78:%.*]] = add nsw i64 [[TMP41]], 1
26907 // CHECK27-NEXT:    store i64 [[ADD78]], i64* [[X]], align 4, !llvm.access.group !16
26908 // CHECK27-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1
26909 // CHECK27-NEXT:    [[TMP42:%.*]] = load i8, i8* [[Y]], align 4, !llvm.access.group !16
26910 // CHECK27-NEXT:    [[CONV79:%.*]] = sext i8 [[TMP42]] to i32
26911 // CHECK27-NEXT:    [[ADD80:%.*]] = add nsw i32 [[CONV79]], 1
26912 // CHECK27-NEXT:    [[CONV81:%.*]] = trunc i32 [[ADD80]] to i8
26913 // CHECK27-NEXT:    store i8 [[CONV81]], i8* [[Y]], align 4, !llvm.access.group !16
26914 // CHECK27-NEXT:    br label [[OMP_BODY_CONTINUE82:%.*]]
26915 // CHECK27:       omp.body.continue82:
26916 // CHECK27-NEXT:    br label [[OMP_INNER_FOR_INC83:%.*]]
26917 // CHECK27:       omp.inner.for.inc83:
26918 // CHECK27-NEXT:    [[TMP43:%.*]] = load i32, i32* [[DOTOMP_IV57]], align 4, !llvm.access.group !16
26919 // CHECK27-NEXT:    [[ADD84:%.*]] = add nsw i32 [[TMP43]], 1
26920 // CHECK27-NEXT:    store i32 [[ADD84]], i32* [[DOTOMP_IV57]], align 4, !llvm.access.group !16
26921 // CHECK27-NEXT:    br label [[OMP_INNER_FOR_COND59]], !llvm.loop [[LOOP17:![0-9]+]]
26922 // CHECK27:       omp.inner.for.end85:
26923 // CHECK27-NEXT:    store i32 10, i32* [[I58]], align 4
26924 // CHECK27-NEXT:    [[TMP44:%.*]] = load i32, i32* [[A]], align 4
26925 // CHECK27-NEXT:    [[TMP45:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
26926 // CHECK27-NEXT:    call void @llvm.stackrestore(i8* [[TMP45]])
26927 // CHECK27-NEXT:    ret i32 [[TMP44]]
26928 //
26929 //
26930 // CHECK27-LABEL: define {{[^@]+}}@_Z3bari
26931 // CHECK27-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {
26932 // CHECK27-NEXT:  entry:
26933 // CHECK27-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
26934 // CHECK27-NEXT:    [[A:%.*]] = alloca i32, align 4
26935 // CHECK27-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4
26936 // CHECK27-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
26937 // CHECK27-NEXT:    store i32 0, i32* [[A]], align 4
26938 // CHECK27-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
26939 // CHECK27-NEXT:    [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]])
26940 // CHECK27-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
26941 // CHECK27-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
26942 // CHECK27-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
26943 // CHECK27-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
26944 // CHECK27-NEXT:    [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP2]])
26945 // CHECK27-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
26946 // CHECK27-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
26947 // CHECK27-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
26948 // CHECK27-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
26949 // CHECK27-NEXT:    [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]])
26950 // CHECK27-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
26951 // CHECK27-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
26952 // CHECK27-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
26953 // CHECK27-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
26954 // CHECK27-NEXT:    [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]])
26955 // CHECK27-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
26956 // CHECK27-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
26957 // CHECK27-NEXT:    store i32 [[ADD6]], i32* [[A]], align 4
26958 // CHECK27-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
26959 // CHECK27-NEXT:    ret i32 [[TMP8]]
26960 //
26961 //
26962 // CHECK27-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
26963 // CHECK27-SAME: (%struct.S1* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 {
26964 // CHECK27-NEXT:  entry:
26965 // CHECK27-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
26966 // CHECK27-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
26967 // CHECK27-NEXT:    [[B:%.*]] = alloca i32, align 4
26968 // CHECK27-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 4
26969 // CHECK27-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 4
26970 // CHECK27-NEXT:    [[TMP:%.*]] = alloca i32, align 4
26971 // CHECK27-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
26972 // CHECK27-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
26973 // CHECK27-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
26974 // CHECK27-NEXT:    [[I:%.*]] = alloca i32, align 4
26975 // CHECK27-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
26976 // CHECK27-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
26977 // CHECK27-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
26978 // CHECK27-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
26979 // CHECK27-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
26980 // CHECK27-NEXT:    store i32 [[ADD]], i32* [[B]], align 4
26981 // CHECK27-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
26982 // CHECK27-NEXT:    [[TMP2:%.*]] = call i8* @llvm.stacksave()
26983 // CHECK27-NEXT:    store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4
26984 // CHECK27-NEXT:    [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]
26985 // CHECK27-NEXT:    [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2
26986 // CHECK27-NEXT:    store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
26987 // CHECK27-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
26988 // CHECK27-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
26989 // CHECK27-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
26990 // CHECK27-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
26991 // CHECK27-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
26992 // CHECK27:       omp.inner.for.cond:
26993 // CHECK27-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
26994 // CHECK27-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !19
26995 // CHECK27-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
26996 // CHECK27-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
26997 // CHECK27:       omp.inner.for.body:
26998 // CHECK27-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
26999 // CHECK27-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
27000 // CHECK27-NEXT:    [[ADD2:%.*]] = add nsw i32 0, [[MUL]]
27001 // CHECK27-NEXT:    store i32 [[ADD2]], i32* [[I]], align 4, !llvm.access.group !19
27002 // CHECK27-NEXT:    [[TMP8:%.*]] = load i32, i32* [[B]], align 4, !llvm.access.group !19
27003 // CHECK27-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP8]] to double
27004 // CHECK27-NEXT:    [[ADD3:%.*]] = fadd double [[CONV]], 1.500000e+00
27005 // CHECK27-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
27006 // CHECK27-NEXT:    store double [[ADD3]], double* [[A]], align 4, !llvm.access.group !19
27007 // CHECK27-NEXT:    [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
27008 // CHECK27-NEXT:    [[TMP9:%.*]] = load double, double* [[A4]], align 4, !llvm.access.group !19
27009 // CHECK27-NEXT:    [[INC:%.*]] = fadd double [[TMP9]], 1.000000e+00
27010 // CHECK27-NEXT:    store double [[INC]], double* [[A4]], align 4, !llvm.access.group !19
27011 // CHECK27-NEXT:    [[CONV5:%.*]] = fptosi double [[INC]] to i16
27012 // CHECK27-NEXT:    [[TMP10:%.*]] = mul nsw i32 1, [[TMP1]]
27013 // CHECK27-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP10]]
27014 // CHECK27-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
27015 // CHECK27-NEXT:    store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2, !llvm.access.group !19
27016 // CHECK27-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
27017 // CHECK27:       omp.body.continue:
27018 // CHECK27-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
27019 // CHECK27:       omp.inner.for.inc:
27020 // CHECK27-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
27021 // CHECK27-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1
27022 // CHECK27-NEXT:    store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
27023 // CHECK27-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]]
27024 // CHECK27:       omp.inner.for.end:
27025 // CHECK27-NEXT:    store i32 10, i32* [[I]], align 4
27026 // CHECK27-NEXT:    [[TMP12:%.*]] = mul nsw i32 1, [[TMP1]]
27027 // CHECK27-NEXT:    [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP12]]
27028 // CHECK27-NEXT:    [[ARRAYIDX9:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX8]], i32 1
27029 // CHECK27-NEXT:    [[TMP13:%.*]] = load i16, i16* [[ARRAYIDX9]], align 2
27030 // CHECK27-NEXT:    [[CONV10:%.*]] = sext i16 [[TMP13]] to i32
27031 // CHECK27-NEXT:    [[TMP14:%.*]] = load i32, i32* [[B]], align 4
27032 // CHECK27-NEXT:    [[ADD11:%.*]] = add nsw i32 [[CONV10]], [[TMP14]]
27033 // CHECK27-NEXT:    [[TMP15:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
27034 // CHECK27-NEXT:    call void @llvm.stackrestore(i8* [[TMP15]])
27035 // CHECK27-NEXT:    ret i32 [[ADD11]]
27036 //
27037 //
27038 // CHECK27-LABEL: define {{[^@]+}}@_ZL7fstatici
27039 // CHECK27-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {
27040 // CHECK27-NEXT:  entry:
27041 // CHECK27-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
27042 // CHECK27-NEXT:    [[A:%.*]] = alloca i32, align 4
27043 // CHECK27-NEXT:    [[AA:%.*]] = alloca i16, align 2
27044 // CHECK27-NEXT:    [[AAA:%.*]] = alloca i8, align 1
27045 // CHECK27-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
27046 // CHECK27-NEXT:    [[TMP:%.*]] = alloca i32, align 4
27047 // CHECK27-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
27048 // CHECK27-NEXT:    [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
27049 // CHECK27-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
27050 // CHECK27-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
27051 // CHECK27-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
27052 // CHECK27-NEXT:    [[I:%.*]] = alloca i32, align 4
27053 // CHECK27-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
27054 // CHECK27-NEXT:    [[I5:%.*]] = alloca i32, align 4
27055 // CHECK27-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
27056 // CHECK27-NEXT:    store i32 0, i32* [[A]], align 4
27057 // CHECK27-NEXT:    store i16 0, i16* [[AA]], align 2
27058 // CHECK27-NEXT:    store i8 0, i8* [[AAA]], align 1
27059 // CHECK27-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
27060 // CHECK27-NEXT:    store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4
27061 // CHECK27-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
27062 // CHECK27-NEXT:    store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_1]], align 4
27063 // CHECK27-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
27064 // CHECK27-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
27065 // CHECK27-NEXT:    [[SUB:%.*]] = sub i32 [[TMP2]], [[TMP3]]
27066 // CHECK27-NEXT:    [[SUB3:%.*]] = sub i32 [[SUB]], 1
27067 // CHECK27-NEXT:    [[ADD:%.*]] = add i32 [[SUB3]], 1
27068 // CHECK27-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], 1
27069 // CHECK27-NEXT:    [[SUB4:%.*]] = sub i32 [[DIV]], 1
27070 // CHECK27-NEXT:    store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_2]], align 4
27071 // CHECK27-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
27072 // CHECK27-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
27073 // CHECK27-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_UB]], align 4
27074 // CHECK27-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
27075 // CHECK27-NEXT:    store i32 [[TMP5]], i32* [[I]], align 4
27076 // CHECK27-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
27077 // CHECK27-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
27078 // CHECK27-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]]
27079 // CHECK27-NEXT:    br i1 [[CMP]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END:%.*]]
27080 // CHECK27:       simd.if.then:
27081 // CHECK27-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
27082 // CHECK27-NEXT:    store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
27083 // CHECK27-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
27084 // CHECK27:       omp.inner.for.cond:
27085 // CHECK27-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
27086 // CHECK27-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !22
27087 // CHECK27-NEXT:    [[ADD6:%.*]] = add i32 [[TMP10]], 1
27088 // CHECK27-NEXT:    [[CMP7:%.*]] = icmp ult i32 [[TMP9]], [[ADD6]]
27089 // CHECK27-NEXT:    br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
27090 // CHECK27:       omp.inner.for.body:
27091 // CHECK27-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group !22
27092 // CHECK27-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
27093 // CHECK27-NEXT:    [[MUL:%.*]] = mul i32 [[TMP12]], 1
27094 // CHECK27-NEXT:    [[ADD8:%.*]] = add i32 [[TMP11]], [[MUL]]
27095 // CHECK27-NEXT:    store i32 [[ADD8]], i32* [[I5]], align 4, !llvm.access.group !22
27096 // CHECK27-NEXT:    [[TMP13:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !22
27097 // CHECK27-NEXT:    [[ADD9:%.*]] = add nsw i32 [[TMP13]], 1
27098 // CHECK27-NEXT:    store i32 [[ADD9]], i32* [[A]], align 4, !llvm.access.group !22
27099 // CHECK27-NEXT:    [[TMP14:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !22
27100 // CHECK27-NEXT:    [[CONV:%.*]] = sext i16 [[TMP14]] to i32
27101 // CHECK27-NEXT:    [[ADD10:%.*]] = add nsw i32 [[CONV]], 1
27102 // CHECK27-NEXT:    [[CONV11:%.*]] = trunc i32 [[ADD10]] to i16
27103 // CHECK27-NEXT:    store i16 [[CONV11]], i16* [[AA]], align 2, !llvm.access.group !22
27104 // CHECK27-NEXT:    [[TMP15:%.*]] = load i8, i8* [[AAA]], align 1, !llvm.access.group !22
27105 // CHECK27-NEXT:    [[CONV12:%.*]] = sext i8 [[TMP15]] to i32
27106 // CHECK27-NEXT:    [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1
27107 // CHECK27-NEXT:    [[CONV14:%.*]] = trunc i32 [[ADD13]] to i8
27108 // CHECK27-NEXT:    store i8 [[CONV14]], i8* [[AAA]], align 1, !llvm.access.group !22
27109 // CHECK27-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2
27110 // CHECK27-NEXT:    [[TMP16:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !22
27111 // CHECK27-NEXT:    [[ADD15:%.*]] = add nsw i32 [[TMP16]], 1
27112 // CHECK27-NEXT:    store i32 [[ADD15]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !22
27113 // CHECK27-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
27114 // CHECK27:       omp.body.continue:
27115 // CHECK27-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
27116 // CHECK27:       omp.inner.for.inc:
27117 // CHECK27-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
27118 // CHECK27-NEXT:    [[ADD16:%.*]] = add i32 [[TMP17]], 1
27119 // CHECK27-NEXT:    store i32 [[ADD16]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
27120 // CHECK27-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]]
27121 // CHECK27:       omp.inner.for.end:
27122 // CHECK27-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
27123 // CHECK27-NEXT:    [[TMP19:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
27124 // CHECK27-NEXT:    [[TMP20:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
27125 // CHECK27-NEXT:    [[SUB17:%.*]] = sub i32 [[TMP19]], [[TMP20]]
27126 // CHECK27-NEXT:    [[SUB18:%.*]] = sub i32 [[SUB17]], 1
27127 // CHECK27-NEXT:    [[ADD19:%.*]] = add i32 [[SUB18]], 1
27128 // CHECK27-NEXT:    [[DIV20:%.*]] = udiv i32 [[ADD19]], 1
27129 // CHECK27-NEXT:    [[MUL21:%.*]] = mul i32 [[DIV20]], 1
27130 // CHECK27-NEXT:    [[ADD22:%.*]] = add i32 [[TMP18]], [[MUL21]]
27131 // CHECK27-NEXT:    store i32 [[ADD22]], i32* [[I5]], align 4
27132 // CHECK27-NEXT:    br label [[SIMD_IF_END]]
27133 // CHECK27:       simd.if.end:
27134 // CHECK27-NEXT:    [[TMP21:%.*]] = load i32, i32* [[A]], align 4
27135 // CHECK27-NEXT:    ret i32 [[TMP21]]
27136 //
27137 //
27138 // CHECK27-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
27139 // CHECK27-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat {
27140 // CHECK27-NEXT:  entry:
27141 // CHECK27-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
27142 // CHECK27-NEXT:    [[A:%.*]] = alloca i32, align 4
27143 // CHECK27-NEXT:    [[AA:%.*]] = alloca i16, align 2
27144 // CHECK27-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
27145 // CHECK27-NEXT:    [[TMP:%.*]] = alloca i32, align 4
27146 // CHECK27-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
27147 // CHECK27-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
27148 // CHECK27-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
27149 // CHECK27-NEXT:    [[I:%.*]] = alloca i32, align 4
27150 // CHECK27-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
27151 // CHECK27-NEXT:    store i32 0, i32* [[A]], align 4
27152 // CHECK27-NEXT:    store i16 0, i16* [[AA]], align 2
27153 // CHECK27-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
27154 // CHECK27-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
27155 // CHECK27-NEXT:    [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
27156 // CHECK27-NEXT:    store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4
27157 // CHECK27-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
27158 // CHECK27:       omp.inner.for.cond:
27159 // CHECK27-NEXT:    [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25
27160 // CHECK27-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !25
27161 // CHECK27-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
27162 // CHECK27-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
27163 // CHECK27:       omp.inner.for.body:
27164 // CHECK27-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25
27165 // CHECK27-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1
27166 // CHECK27-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
27167 // CHECK27-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !25
27168 // CHECK27-NEXT:    [[TMP4:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !25
27169 // CHECK27-NEXT:    [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1
27170 // CHECK27-NEXT:    store i32 [[ADD1]], i32* [[A]], align 4, !llvm.access.group !25
27171 // CHECK27-NEXT:    [[TMP5:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !25
27172 // CHECK27-NEXT:    [[CONV:%.*]] = sext i16 [[TMP5]] to i32
27173 // CHECK27-NEXT:    [[ADD2:%.*]] = add nsw i32 [[CONV]], 1
27174 // CHECK27-NEXT:    [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
27175 // CHECK27-NEXT:    store i16 [[CONV3]], i16* [[AA]], align 2, !llvm.access.group !25
27176 // CHECK27-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2
27177 // CHECK27-NEXT:    [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !25
27178 // CHECK27-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP6]], 1
27179 // CHECK27-NEXT:    store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !25
27180 // CHECK27-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
27181 // CHECK27:       omp.body.continue:
27182 // CHECK27-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
27183 // CHECK27:       omp.inner.for.inc:
27184 // CHECK27-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25
27185 // CHECK27-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP7]], 1
27186 // CHECK27-NEXT:    store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25
27187 // CHECK27-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP26:![0-9]+]]
27188 // CHECK27:       omp.inner.for.end:
27189 // CHECK27-NEXT:    store i32 10, i32* [[I]], align 4
27190 // CHECK27-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
27191 // CHECK27-NEXT:    ret i32 [[TMP8]]
27192 //
27193 //
27194 // CHECK28-LABEL: define {{[^@]+}}@_Z3fooi
27195 // CHECK28-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0:[0-9]+]] {
27196 // CHECK28-NEXT:  entry:
27197 // CHECK28-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
27198 // CHECK28-NEXT:    [[A:%.*]] = alloca i32, align 4
27199 // CHECK28-NEXT:    [[AA:%.*]] = alloca i16, align 2
27200 // CHECK28-NEXT:    [[B:%.*]] = alloca [10 x float], align 4
27201 // CHECK28-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 4
27202 // CHECK28-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 4
27203 // CHECK28-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 8
27204 // CHECK28-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i32, align 4
27205 // CHECK28-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4
27206 // CHECK28-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
27207 // CHECK28-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
27208 // CHECK28-NEXT:    [[TMP:%.*]] = alloca i32, align 4
27209 // CHECK28-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
27210 // CHECK28-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
27211 // CHECK28-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
27212 // CHECK28-NEXT:    [[I:%.*]] = alloca i32, align 4
27213 // CHECK28-NEXT:    [[_TMP4:%.*]] = alloca i32, align 4
27214 // CHECK28-NEXT:    [[DOTOMP_LB5:%.*]] = alloca i32, align 4
27215 // CHECK28-NEXT:    [[DOTOMP_UB6:%.*]] = alloca i32, align 4
27216 // CHECK28-NEXT:    [[DOTOMP_IV7:%.*]] = alloca i32, align 4
27217 // CHECK28-NEXT:    [[DOTLINEAR_START:%.*]] = alloca i32, align 4
27218 // CHECK28-NEXT:    [[A8:%.*]] = alloca i32, align 4
27219 // CHECK28-NEXT:    [[A9:%.*]] = alloca i32, align 4
27220 // CHECK28-NEXT:    [[_TMP20:%.*]] = alloca i32, align 4
27221 // CHECK28-NEXT:    [[DOTOMP_LB21:%.*]] = alloca i32, align 4
27222 // CHECK28-NEXT:    [[DOTOMP_UB22:%.*]] = alloca i32, align 4
27223 // CHECK28-NEXT:    [[DOTOMP_IV23:%.*]] = alloca i32, align 4
27224 // CHECK28-NEXT:    [[I24:%.*]] = alloca i32, align 4
27225 // CHECK28-NEXT:    [[_TMP36:%.*]] = alloca i32, align 4
27226 // CHECK28-NEXT:    [[DOTOMP_LB37:%.*]] = alloca i32, align 4
27227 // CHECK28-NEXT:    [[DOTOMP_UB38:%.*]] = alloca i32, align 4
27228 // CHECK28-NEXT:    [[DOTOMP_IV39:%.*]] = alloca i32, align 4
27229 // CHECK28-NEXT:    [[I40:%.*]] = alloca i32, align 4
27230 // CHECK28-NEXT:    [[_TMP54:%.*]] = alloca i32, align 4
27231 // CHECK28-NEXT:    [[DOTOMP_LB55:%.*]] = alloca i32, align 4
27232 // CHECK28-NEXT:    [[DOTOMP_UB56:%.*]] = alloca i32, align 4
27233 // CHECK28-NEXT:    [[DOTOMP_IV57:%.*]] = alloca i32, align 4
27234 // CHECK28-NEXT:    [[I58:%.*]] = alloca i32, align 4
27235 // CHECK28-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
27236 // CHECK28-NEXT:    store i32 0, i32* [[A]], align 4
27237 // CHECK28-NEXT:    store i16 0, i16* [[AA]], align 2
27238 // CHECK28-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
27239 // CHECK28-NEXT:    [[TMP1:%.*]] = call i8* @llvm.stacksave()
27240 // CHECK28-NEXT:    store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4
27241 // CHECK28-NEXT:    [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4
27242 // CHECK28-NEXT:    store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4
27243 // CHECK28-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
27244 // CHECK28-NEXT:    [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]]
27245 // CHECK28-NEXT:    [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8
27246 // CHECK28-NEXT:    store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4
27247 // CHECK28-NEXT:    [[TMP4:%.*]] = load i32, i32* [[A]], align 4
27248 // CHECK28-NEXT:    store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4
27249 // CHECK28-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
27250 // CHECK28-NEXT:    store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_2]], align 4
27251 // CHECK28-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
27252 // CHECK28-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
27253 // CHECK28-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
27254 // CHECK28-NEXT:    store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
27255 // CHECK28-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
27256 // CHECK28:       omp.inner.for.cond:
27257 // CHECK28-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
27258 // CHECK28-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !3
27259 // CHECK28-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
27260 // CHECK28-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
27261 // CHECK28:       omp.inner.for.body:
27262 // CHECK28-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
27263 // CHECK28-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
27264 // CHECK28-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
27265 // CHECK28-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !3
27266 // CHECK28-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
27267 // CHECK28:       omp.body.continue:
27268 // CHECK28-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
27269 // CHECK28:       omp.inner.for.inc:
27270 // CHECK28-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
27271 // CHECK28-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
27272 // CHECK28-NEXT:    store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
27273 // CHECK28-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]
27274 // CHECK28:       omp.inner.for.end:
27275 // CHECK28-NEXT:    store i32 10, i32* [[I]], align 4
27276 // CHECK28-NEXT:    store i32 0, i32* [[DOTOMP_LB5]], align 4
27277 // CHECK28-NEXT:    store i32 9, i32* [[DOTOMP_UB6]], align 4
27278 // CHECK28-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_LB5]], align 4
27279 // CHECK28-NEXT:    store i32 [[TMP11]], i32* [[DOTOMP_IV7]], align 4
27280 // CHECK28-NEXT:    [[TMP12:%.*]] = load i32, i32* [[A]], align 4
27281 // CHECK28-NEXT:    store i32 [[TMP12]], i32* [[DOTLINEAR_START]], align 4
27282 // CHECK28-NEXT:    br label [[OMP_INNER_FOR_COND10:%.*]]
27283 // CHECK28:       omp.inner.for.cond10:
27284 // CHECK28-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV7]], align 4
27285 // CHECK28-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB6]], align 4
27286 // CHECK28-NEXT:    [[CMP11:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
27287 // CHECK28-NEXT:    br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY12:%.*]], label [[OMP_INNER_FOR_END19:%.*]]
27288 // CHECK28:       omp.inner.for.body12:
27289 // CHECK28-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV7]], align 4
27290 // CHECK28-NEXT:    [[MUL13:%.*]] = mul nsw i32 [[TMP15]], 1
27291 // CHECK28-NEXT:    [[ADD14:%.*]] = add nsw i32 0, [[MUL13]]
27292 // CHECK28-NEXT:    store i32 [[ADD14]], i32* [[A8]], align 4
27293 // CHECK28-NEXT:    [[TMP16:%.*]] = load i32, i32* [[A8]], align 4
27294 // CHECK28-NEXT:    [[ADD15:%.*]] = add nsw i32 [[TMP16]], 1
27295 // CHECK28-NEXT:    store i32 [[ADD15]], i32* [[A8]], align 4
27296 // CHECK28-NEXT:    br label [[OMP_BODY_CONTINUE16:%.*]]
27297 // CHECK28:       omp.body.continue16:
27298 // CHECK28-NEXT:    br label [[OMP_INNER_FOR_INC17:%.*]]
27299 // CHECK28:       omp.inner.for.inc17:
27300 // CHECK28-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV7]], align 4
27301 // CHECK28-NEXT:    [[ADD18:%.*]] = add nsw i32 [[TMP17]], 1
27302 // CHECK28-NEXT:    store i32 [[ADD18]], i32* [[DOTOMP_IV7]], align 4
27303 // CHECK28-NEXT:    br label [[OMP_INNER_FOR_COND10]], !llvm.loop [[LOOP8:![0-9]+]]
27304 // CHECK28:       omp.inner.for.end19:
27305 // CHECK28-NEXT:    store i32 10, i32* [[A]], align 4
27306 // CHECK28-NEXT:    store i32 0, i32* [[DOTOMP_LB21]], align 4
27307 // CHECK28-NEXT:    store i32 9, i32* [[DOTOMP_UB22]], align 4
27308 // CHECK28-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTOMP_LB21]], align 4
27309 // CHECK28-NEXT:    store i32 [[TMP18]], i32* [[DOTOMP_IV23]], align 4
27310 // CHECK28-NEXT:    br label [[OMP_INNER_FOR_COND25:%.*]]
27311 // CHECK28:       omp.inner.for.cond25:
27312 // CHECK28-NEXT:    [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV23]], align 4, !llvm.access.group !10
27313 // CHECK28-NEXT:    [[TMP20:%.*]] = load i32, i32* [[DOTOMP_UB22]], align 4, !llvm.access.group !10
27314 // CHECK28-NEXT:    [[CMP26:%.*]] = icmp sle i32 [[TMP19]], [[TMP20]]
27315 // CHECK28-NEXT:    br i1 [[CMP26]], label [[OMP_INNER_FOR_BODY27:%.*]], label [[OMP_INNER_FOR_END35:%.*]]
27316 // CHECK28:       omp.inner.for.body27:
27317 // CHECK28-NEXT:    [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV23]], align 4, !llvm.access.group !10
27318 // CHECK28-NEXT:    [[MUL28:%.*]] = mul nsw i32 [[TMP21]], 1
27319 // CHECK28-NEXT:    [[ADD29:%.*]] = add nsw i32 0, [[MUL28]]
27320 // CHECK28-NEXT:    store i32 [[ADD29]], i32* [[I24]], align 4, !llvm.access.group !10
27321 // CHECK28-NEXT:    [[TMP22:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !10
27322 // CHECK28-NEXT:    [[CONV:%.*]] = sext i16 [[TMP22]] to i32
27323 // CHECK28-NEXT:    [[ADD30:%.*]] = add nsw i32 [[CONV]], 1
27324 // CHECK28-NEXT:    [[CONV31:%.*]] = trunc i32 [[ADD30]] to i16
27325 // CHECK28-NEXT:    store i16 [[CONV31]], i16* [[AA]], align 2, !llvm.access.group !10
27326 // CHECK28-NEXT:    br label [[OMP_BODY_CONTINUE32:%.*]]
27327 // CHECK28:       omp.body.continue32:
27328 // CHECK28-NEXT:    br label [[OMP_INNER_FOR_INC33:%.*]]
27329 // CHECK28:       omp.inner.for.inc33:
27330 // CHECK28-NEXT:    [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV23]], align 4, !llvm.access.group !10
27331 // CHECK28-NEXT:    [[ADD34:%.*]] = add nsw i32 [[TMP23]], 1
27332 // CHECK28-NEXT:    store i32 [[ADD34]], i32* [[DOTOMP_IV23]], align 4, !llvm.access.group !10
27333 // CHECK28-NEXT:    br label [[OMP_INNER_FOR_COND25]], !llvm.loop [[LOOP11:![0-9]+]]
27334 // CHECK28:       omp.inner.for.end35:
27335 // CHECK28-NEXT:    store i32 10, i32* [[I24]], align 4
27336 // CHECK28-NEXT:    store i32 0, i32* [[DOTOMP_LB37]], align 4
27337 // CHECK28-NEXT:    store i32 9, i32* [[DOTOMP_UB38]], align 4
27338 // CHECK28-NEXT:    [[TMP24:%.*]] = load i32, i32* [[DOTOMP_LB37]], align 4
27339 // CHECK28-NEXT:    store i32 [[TMP24]], i32* [[DOTOMP_IV39]], align 4
27340 // CHECK28-NEXT:    br label [[OMP_INNER_FOR_COND41:%.*]]
27341 // CHECK28:       omp.inner.for.cond41:
27342 // CHECK28-NEXT:    [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IV39]], align 4, !llvm.access.group !13
27343 // CHECK28-NEXT:    [[TMP26:%.*]] = load i32, i32* [[DOTOMP_UB38]], align 4, !llvm.access.group !13
27344 // CHECK28-NEXT:    [[CMP42:%.*]] = icmp sle i32 [[TMP25]], [[TMP26]]
27345 // CHECK28-NEXT:    br i1 [[CMP42]], label [[OMP_INNER_FOR_BODY43:%.*]], label [[OMP_INNER_FOR_END53:%.*]]
27346 // CHECK28:       omp.inner.for.body43:
27347 // CHECK28-NEXT:    [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV39]], align 4, !llvm.access.group !13
27348 // CHECK28-NEXT:    [[MUL44:%.*]] = mul nsw i32 [[TMP27]], 1
27349 // CHECK28-NEXT:    [[ADD45:%.*]] = add nsw i32 0, [[MUL44]]
27350 // CHECK28-NEXT:    store i32 [[ADD45]], i32* [[I40]], align 4, !llvm.access.group !13
27351 // CHECK28-NEXT:    [[TMP28:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !13
27352 // CHECK28-NEXT:    [[ADD46:%.*]] = add nsw i32 [[TMP28]], 1
27353 // CHECK28-NEXT:    store i32 [[ADD46]], i32* [[A]], align 4, !llvm.access.group !13
27354 // CHECK28-NEXT:    [[TMP29:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !13
27355 // CHECK28-NEXT:    [[CONV47:%.*]] = sext i16 [[TMP29]] to i32
27356 // CHECK28-NEXT:    [[ADD48:%.*]] = add nsw i32 [[CONV47]], 1
27357 // CHECK28-NEXT:    [[CONV49:%.*]] = trunc i32 [[ADD48]] to i16
27358 // CHECK28-NEXT:    store i16 [[CONV49]], i16* [[AA]], align 2, !llvm.access.group !13
27359 // CHECK28-NEXT:    br label [[OMP_BODY_CONTINUE50:%.*]]
27360 // CHECK28:       omp.body.continue50:
27361 // CHECK28-NEXT:    br label [[OMP_INNER_FOR_INC51:%.*]]
27362 // CHECK28:       omp.inner.for.inc51:
27363 // CHECK28-NEXT:    [[TMP30:%.*]] = load i32, i32* [[DOTOMP_IV39]], align 4, !llvm.access.group !13
27364 // CHECK28-NEXT:    [[ADD52:%.*]] = add nsw i32 [[TMP30]], 1
27365 // CHECK28-NEXT:    store i32 [[ADD52]], i32* [[DOTOMP_IV39]], align 4, !llvm.access.group !13
27366 // CHECK28-NEXT:    br label [[OMP_INNER_FOR_COND41]], !llvm.loop [[LOOP14:![0-9]+]]
27367 // CHECK28:       omp.inner.for.end53:
27368 // CHECK28-NEXT:    store i32 10, i32* [[I40]], align 4
27369 // CHECK28-NEXT:    store i32 0, i32* [[DOTOMP_LB55]], align 4
27370 // CHECK28-NEXT:    store i32 9, i32* [[DOTOMP_UB56]], align 4
27371 // CHECK28-NEXT:    [[TMP31:%.*]] = load i32, i32* [[DOTOMP_LB55]], align 4
27372 // CHECK28-NEXT:    store i32 [[TMP31]], i32* [[DOTOMP_IV57]], align 4
27373 // CHECK28-NEXT:    [[ARRAYDECAY:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 0
27374 // CHECK28-NEXT:    call void @llvm.assume(i1 true) [ "align"(float* [[ARRAYDECAY]], i32 16) ]
27375 // CHECK28-NEXT:    br label [[OMP_INNER_FOR_COND59:%.*]]
27376 // CHECK28:       omp.inner.for.cond59:
27377 // CHECK28-NEXT:    [[TMP32:%.*]] = load i32, i32* [[DOTOMP_IV57]], align 4, !llvm.access.group !16
27378 // CHECK28-NEXT:    [[TMP33:%.*]] = load i32, i32* [[DOTOMP_UB56]], align 4, !llvm.access.group !16
27379 // CHECK28-NEXT:    [[CMP60:%.*]] = icmp sle i32 [[TMP32]], [[TMP33]]
27380 // CHECK28-NEXT:    br i1 [[CMP60]], label [[OMP_INNER_FOR_BODY61:%.*]], label [[OMP_INNER_FOR_END85:%.*]]
27381 // CHECK28:       omp.inner.for.body61:
27382 // CHECK28-NEXT:    [[TMP34:%.*]] = load i32, i32* [[DOTOMP_IV57]], align 4, !llvm.access.group !16
27383 // CHECK28-NEXT:    [[MUL62:%.*]] = mul nsw i32 [[TMP34]], 1
27384 // CHECK28-NEXT:    [[ADD63:%.*]] = add nsw i32 0, [[MUL62]]
27385 // CHECK28-NEXT:    store i32 [[ADD63]], i32* [[I58]], align 4, !llvm.access.group !16
27386 // CHECK28-NEXT:    [[TMP35:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !16
27387 // CHECK28-NEXT:    [[ADD64:%.*]] = add nsw i32 [[TMP35]], 1
27388 // CHECK28-NEXT:    store i32 [[ADD64]], i32* [[A]], align 4, !llvm.access.group !16
27389 // CHECK28-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2
27390 // CHECK28-NEXT:    [[TMP36:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !16
27391 // CHECK28-NEXT:    [[CONV65:%.*]] = fpext float [[TMP36]] to double
27392 // CHECK28-NEXT:    [[ADD66:%.*]] = fadd double [[CONV65]], 1.000000e+00
27393 // CHECK28-NEXT:    [[CONV67:%.*]] = fptrunc double [[ADD66]] to float
27394 // CHECK28-NEXT:    store float [[CONV67]], float* [[ARRAYIDX]], align 4, !llvm.access.group !16
27395 // CHECK28-NEXT:    [[ARRAYIDX68:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3
27396 // CHECK28-NEXT:    [[TMP37:%.*]] = load float, float* [[ARRAYIDX68]], align 4, !llvm.access.group !16
27397 // CHECK28-NEXT:    [[CONV69:%.*]] = fpext float [[TMP37]] to double
27398 // CHECK28-NEXT:    [[ADD70:%.*]] = fadd double [[CONV69]], 1.000000e+00
27399 // CHECK28-NEXT:    [[CONV71:%.*]] = fptrunc double [[ADD70]] to float
27400 // CHECK28-NEXT:    store float [[CONV71]], float* [[ARRAYIDX68]], align 4, !llvm.access.group !16
27401 // CHECK28-NEXT:    [[ARRAYIDX72:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1
27402 // CHECK28-NEXT:    [[ARRAYIDX73:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX72]], i32 0, i32 2
27403 // CHECK28-NEXT:    [[TMP38:%.*]] = load double, double* [[ARRAYIDX73]], align 8, !llvm.access.group !16
27404 // CHECK28-NEXT:    [[ADD74:%.*]] = fadd double [[TMP38]], 1.000000e+00
27405 // CHECK28-NEXT:    store double [[ADD74]], double* [[ARRAYIDX73]], align 8, !llvm.access.group !16
27406 // CHECK28-NEXT:    [[TMP39:%.*]] = mul nsw i32 1, [[TMP2]]
27407 // CHECK28-NEXT:    [[ARRAYIDX75:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP39]]
27408 // CHECK28-NEXT:    [[ARRAYIDX76:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX75]], i32 3
27409 // CHECK28-NEXT:    [[TMP40:%.*]] = load double, double* [[ARRAYIDX76]], align 8, !llvm.access.group !16
27410 // CHECK28-NEXT:    [[ADD77:%.*]] = fadd double [[TMP40]], 1.000000e+00
27411 // CHECK28-NEXT:    store double [[ADD77]], double* [[ARRAYIDX76]], align 8, !llvm.access.group !16
27412 // CHECK28-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0
27413 // CHECK28-NEXT:    [[TMP41:%.*]] = load i64, i64* [[X]], align 4, !llvm.access.group !16
27414 // CHECK28-NEXT:    [[ADD78:%.*]] = add nsw i64 [[TMP41]], 1
27415 // CHECK28-NEXT:    store i64 [[ADD78]], i64* [[X]], align 4, !llvm.access.group !16
27416 // CHECK28-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1
27417 // CHECK28-NEXT:    [[TMP42:%.*]] = load i8, i8* [[Y]], align 4, !llvm.access.group !16
27418 // CHECK28-NEXT:    [[CONV79:%.*]] = sext i8 [[TMP42]] to i32
27419 // CHECK28-NEXT:    [[ADD80:%.*]] = add nsw i32 [[CONV79]], 1
27420 // CHECK28-NEXT:    [[CONV81:%.*]] = trunc i32 [[ADD80]] to i8
27421 // CHECK28-NEXT:    store i8 [[CONV81]], i8* [[Y]], align 4, !llvm.access.group !16
27422 // CHECK28-NEXT:    br label [[OMP_BODY_CONTINUE82:%.*]]
27423 // CHECK28:       omp.body.continue82:
27424 // CHECK28-NEXT:    br label [[OMP_INNER_FOR_INC83:%.*]]
27425 // CHECK28:       omp.inner.for.inc83:
27426 // CHECK28-NEXT:    [[TMP43:%.*]] = load i32, i32* [[DOTOMP_IV57]], align 4, !llvm.access.group !16
27427 // CHECK28-NEXT:    [[ADD84:%.*]] = add nsw i32 [[TMP43]], 1
27428 // CHECK28-NEXT:    store i32 [[ADD84]], i32* [[DOTOMP_IV57]], align 4, !llvm.access.group !16
27429 // CHECK28-NEXT:    br label [[OMP_INNER_FOR_COND59]], !llvm.loop [[LOOP17:![0-9]+]]
27430 // CHECK28:       omp.inner.for.end85:
27431 // CHECK28-NEXT:    store i32 10, i32* [[I58]], align 4
27432 // CHECK28-NEXT:    [[TMP44:%.*]] = load i32, i32* [[A]], align 4
27433 // CHECK28-NEXT:    [[TMP45:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
27434 // CHECK28-NEXT:    call void @llvm.stackrestore(i8* [[TMP45]])
27435 // CHECK28-NEXT:    ret i32 [[TMP44]]
27436 //
27437 //
27438 // CHECK28-LABEL: define {{[^@]+}}@_Z3bari
27439 // CHECK28-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {
27440 // CHECK28-NEXT:  entry:
27441 // CHECK28-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
27442 // CHECK28-NEXT:    [[A:%.*]] = alloca i32, align 4
27443 // CHECK28-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4
27444 // CHECK28-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
27445 // CHECK28-NEXT:    store i32 0, i32* [[A]], align 4
27446 // CHECK28-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
27447 // CHECK28-NEXT:    [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]])
27448 // CHECK28-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
27449 // CHECK28-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
27450 // CHECK28-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
27451 // CHECK28-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
27452 // CHECK28-NEXT:    [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP2]])
27453 // CHECK28-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
27454 // CHECK28-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
27455 // CHECK28-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
27456 // CHECK28-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
27457 // CHECK28-NEXT:    [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]])
27458 // CHECK28-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
27459 // CHECK28-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
27460 // CHECK28-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
27461 // CHECK28-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
27462 // CHECK28-NEXT:    [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]])
27463 // CHECK28-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
27464 // CHECK28-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
27465 // CHECK28-NEXT:    store i32 [[ADD6]], i32* [[A]], align 4
27466 // CHECK28-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
27467 // CHECK28-NEXT:    ret i32 [[TMP8]]
27468 //
27469 //
27470 // CHECK28-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
27471 // CHECK28-SAME: (%struct.S1* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 {
27472 // CHECK28-NEXT:  entry:
27473 // CHECK28-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
27474 // CHECK28-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
27475 // CHECK28-NEXT:    [[B:%.*]] = alloca i32, align 4
27476 // CHECK28-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 4
27477 // CHECK28-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 4
27478 // CHECK28-NEXT:    [[TMP:%.*]] = alloca i32, align 4
27479 // CHECK28-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
27480 // CHECK28-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
27481 // CHECK28-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
27482 // CHECK28-NEXT:    [[I:%.*]] = alloca i32, align 4
27483 // CHECK28-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
27484 // CHECK28-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
27485 // CHECK28-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
27486 // CHECK28-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
27487 // CHECK28-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
27488 // CHECK28-NEXT:    store i32 [[ADD]], i32* [[B]], align 4
27489 // CHECK28-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
27490 // CHECK28-NEXT:    [[TMP2:%.*]] = call i8* @llvm.stacksave()
27491 // CHECK28-NEXT:    store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4
27492 // CHECK28-NEXT:    [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]
27493 // CHECK28-NEXT:    [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2
27494 // CHECK28-NEXT:    store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
27495 // CHECK28-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
27496 // CHECK28-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
27497 // CHECK28-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
27498 // CHECK28-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
27499 // CHECK28-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
27500 // CHECK28:       omp.inner.for.cond:
27501 // CHECK28-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
27502 // CHECK28-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !19
27503 // CHECK28-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
27504 // CHECK28-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
27505 // CHECK28:       omp.inner.for.body:
27506 // CHECK28-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
27507 // CHECK28-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
27508 // CHECK28-NEXT:    [[ADD2:%.*]] = add nsw i32 0, [[MUL]]
27509 // CHECK28-NEXT:    store i32 [[ADD2]], i32* [[I]], align 4, !llvm.access.group !19
27510 // CHECK28-NEXT:    [[TMP8:%.*]] = load i32, i32* [[B]], align 4, !llvm.access.group !19
27511 // CHECK28-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP8]] to double
27512 // CHECK28-NEXT:    [[ADD3:%.*]] = fadd double [[CONV]], 1.500000e+00
27513 // CHECK28-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
27514 // CHECK28-NEXT:    store double [[ADD3]], double* [[A]], align 4, !llvm.access.group !19
27515 // CHECK28-NEXT:    [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
27516 // CHECK28-NEXT:    [[TMP9:%.*]] = load double, double* [[A4]], align 4, !llvm.access.group !19
27517 // CHECK28-NEXT:    [[INC:%.*]] = fadd double [[TMP9]], 1.000000e+00
27518 // CHECK28-NEXT:    store double [[INC]], double* [[A4]], align 4, !llvm.access.group !19
27519 // CHECK28-NEXT:    [[CONV5:%.*]] = fptosi double [[INC]] to i16
27520 // CHECK28-NEXT:    [[TMP10:%.*]] = mul nsw i32 1, [[TMP1]]
27521 // CHECK28-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP10]]
27522 // CHECK28-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
27523 // CHECK28-NEXT:    store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2, !llvm.access.group !19
27524 // CHECK28-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
27525 // CHECK28:       omp.body.continue:
27526 // CHECK28-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
27527 // CHECK28:       omp.inner.for.inc:
27528 // CHECK28-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
27529 // CHECK28-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1
27530 // CHECK28-NEXT:    store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
27531 // CHECK28-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]]
27532 // CHECK28:       omp.inner.for.end:
27533 // CHECK28-NEXT:    store i32 10, i32* [[I]], align 4
27534 // CHECK28-NEXT:    [[TMP12:%.*]] = mul nsw i32 1, [[TMP1]]
27535 // CHECK28-NEXT:    [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP12]]
27536 // CHECK28-NEXT:    [[ARRAYIDX9:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX8]], i32 1
27537 // CHECK28-NEXT:    [[TMP13:%.*]] = load i16, i16* [[ARRAYIDX9]], align 2
27538 // CHECK28-NEXT:    [[CONV10:%.*]] = sext i16 [[TMP13]] to i32
27539 // CHECK28-NEXT:    [[TMP14:%.*]] = load i32, i32* [[B]], align 4
27540 // CHECK28-NEXT:    [[ADD11:%.*]] = add nsw i32 [[CONV10]], [[TMP14]]
27541 // CHECK28-NEXT:    [[TMP15:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
27542 // CHECK28-NEXT:    call void @llvm.stackrestore(i8* [[TMP15]])
27543 // CHECK28-NEXT:    ret i32 [[ADD11]]
27544 //
27545 //
27546 // CHECK28-LABEL: define {{[^@]+}}@_ZL7fstatici
27547 // CHECK28-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {
27548 // CHECK28-NEXT:  entry:
27549 // CHECK28-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
27550 // CHECK28-NEXT:    [[A:%.*]] = alloca i32, align 4
27551 // CHECK28-NEXT:    [[AA:%.*]] = alloca i16, align 2
27552 // CHECK28-NEXT:    [[AAA:%.*]] = alloca i8, align 1
27553 // CHECK28-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
27554 // CHECK28-NEXT:    [[TMP:%.*]] = alloca i32, align 4
27555 // CHECK28-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
27556 // CHECK28-NEXT:    [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
27557 // CHECK28-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
27558 // CHECK28-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
27559 // CHECK28-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
27560 // CHECK28-NEXT:    [[I:%.*]] = alloca i32, align 4
27561 // CHECK28-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
27562 // CHECK28-NEXT:    [[I5:%.*]] = alloca i32, align 4
27563 // CHECK28-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
27564 // CHECK28-NEXT:    store i32 0, i32* [[A]], align 4
27565 // CHECK28-NEXT:    store i16 0, i16* [[AA]], align 2
27566 // CHECK28-NEXT:    store i8 0, i8* [[AAA]], align 1
27567 // CHECK28-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
27568 // CHECK28-NEXT:    store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4
27569 // CHECK28-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
27570 // CHECK28-NEXT:    store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_1]], align 4
27571 // CHECK28-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
27572 // CHECK28-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
27573 // CHECK28-NEXT:    [[SUB:%.*]] = sub i32 [[TMP2]], [[TMP3]]
27574 // CHECK28-NEXT:    [[SUB3:%.*]] = sub i32 [[SUB]], 1
27575 // CHECK28-NEXT:    [[ADD:%.*]] = add i32 [[SUB3]], 1
27576 // CHECK28-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], 1
27577 // CHECK28-NEXT:    [[SUB4:%.*]] = sub i32 [[DIV]], 1
27578 // CHECK28-NEXT:    store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_2]], align 4
27579 // CHECK28-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
27580 // CHECK28-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
27581 // CHECK28-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_UB]], align 4
27582 // CHECK28-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
27583 // CHECK28-NEXT:    store i32 [[TMP5]], i32* [[I]], align 4
27584 // CHECK28-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
27585 // CHECK28-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
27586 // CHECK28-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]]
27587 // CHECK28-NEXT:    br i1 [[CMP]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END:%.*]]
27588 // CHECK28:       simd.if.then:
27589 // CHECK28-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
27590 // CHECK28-NEXT:    store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
27591 // CHECK28-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
27592 // CHECK28:       omp.inner.for.cond:
27593 // CHECK28-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
27594 // CHECK28-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !22
27595 // CHECK28-NEXT:    [[ADD6:%.*]] = add i32 [[TMP10]], 1
27596 // CHECK28-NEXT:    [[CMP7:%.*]] = icmp ult i32 [[TMP9]], [[ADD6]]
27597 // CHECK28-NEXT:    br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
27598 // CHECK28:       omp.inner.for.body:
27599 // CHECK28-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group !22
27600 // CHECK28-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
27601 // CHECK28-NEXT:    [[MUL:%.*]] = mul i32 [[TMP12]], 1
27602 // CHECK28-NEXT:    [[ADD8:%.*]] = add i32 [[TMP11]], [[MUL]]
27603 // CHECK28-NEXT:    store i32 [[ADD8]], i32* [[I5]], align 4, !llvm.access.group !22
27604 // CHECK28-NEXT:    [[TMP13:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !22
27605 // CHECK28-NEXT:    [[ADD9:%.*]] = add nsw i32 [[TMP13]], 1
27606 // CHECK28-NEXT:    store i32 [[ADD9]], i32* [[A]], align 4, !llvm.access.group !22
27607 // CHECK28-NEXT:    [[TMP14:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !22
27608 // CHECK28-NEXT:    [[CONV:%.*]] = sext i16 [[TMP14]] to i32
27609 // CHECK28-NEXT:    [[ADD10:%.*]] = add nsw i32 [[CONV]], 1
27610 // CHECK28-NEXT:    [[CONV11:%.*]] = trunc i32 [[ADD10]] to i16
27611 // CHECK28-NEXT:    store i16 [[CONV11]], i16* [[AA]], align 2, !llvm.access.group !22
27612 // CHECK28-NEXT:    [[TMP15:%.*]] = load i8, i8* [[AAA]], align 1, !llvm.access.group !22
27613 // CHECK28-NEXT:    [[CONV12:%.*]] = sext i8 [[TMP15]] to i32
27614 // CHECK28-NEXT:    [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1
27615 // CHECK28-NEXT:    [[CONV14:%.*]] = trunc i32 [[ADD13]] to i8
27616 // CHECK28-NEXT:    store i8 [[CONV14]], i8* [[AAA]], align 1, !llvm.access.group !22
27617 // CHECK28-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2
27618 // CHECK28-NEXT:    [[TMP16:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !22
27619 // CHECK28-NEXT:    [[ADD15:%.*]] = add nsw i32 [[TMP16]], 1
27620 // CHECK28-NEXT:    store i32 [[ADD15]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !22
27621 // CHECK28-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
27622 // CHECK28:       omp.body.continue:
27623 // CHECK28-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
27624 // CHECK28:       omp.inner.for.inc:
27625 // CHECK28-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
27626 // CHECK28-NEXT:    [[ADD16:%.*]] = add i32 [[TMP17]], 1
27627 // CHECK28-NEXT:    store i32 [[ADD16]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
27628 // CHECK28-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]]
27629 // CHECK28:       omp.inner.for.end:
27630 // CHECK28-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
27631 // CHECK28-NEXT:    [[TMP19:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
27632 // CHECK28-NEXT:    [[TMP20:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
27633 // CHECK28-NEXT:    [[SUB17:%.*]] = sub i32 [[TMP19]], [[TMP20]]
27634 // CHECK28-NEXT:    [[SUB18:%.*]] = sub i32 [[SUB17]], 1
27635 // CHECK28-NEXT:    [[ADD19:%.*]] = add i32 [[SUB18]], 1
27636 // CHECK28-NEXT:    [[DIV20:%.*]] = udiv i32 [[ADD19]], 1
27637 // CHECK28-NEXT:    [[MUL21:%.*]] = mul i32 [[DIV20]], 1
27638 // CHECK28-NEXT:    [[ADD22:%.*]] = add i32 [[TMP18]], [[MUL21]]
27639 // CHECK28-NEXT:    store i32 [[ADD22]], i32* [[I5]], align 4
27640 // CHECK28-NEXT:    br label [[SIMD_IF_END]]
27641 // CHECK28:       simd.if.end:
27642 // CHECK28-NEXT:    [[TMP21:%.*]] = load i32, i32* [[A]], align 4
27643 // CHECK28-NEXT:    ret i32 [[TMP21]]
27644 //
27645 //
27646 // CHECK28-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
27647 // CHECK28-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat {
27648 // CHECK28-NEXT:  entry:
27649 // CHECK28-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
27650 // CHECK28-NEXT:    [[A:%.*]] = alloca i32, align 4
27651 // CHECK28-NEXT:    [[AA:%.*]] = alloca i16, align 2
27652 // CHECK28-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
27653 // CHECK28-NEXT:    [[TMP:%.*]] = alloca i32, align 4
27654 // CHECK28-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
27655 // CHECK28-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
27656 // CHECK28-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
27657 // CHECK28-NEXT:    [[I:%.*]] = alloca i32, align 4
27658 // CHECK28-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
27659 // CHECK28-NEXT:    store i32 0, i32* [[A]], align 4
27660 // CHECK28-NEXT:    store i16 0, i16* [[AA]], align 2
27661 // CHECK28-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
27662 // CHECK28-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
27663 // CHECK28-NEXT:    [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
27664 // CHECK28-NEXT:    store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4
27665 // CHECK28-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
27666 // CHECK28:       omp.inner.for.cond:
27667 // CHECK28-NEXT:    [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25
27668 // CHECK28-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !25
27669 // CHECK28-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
27670 // CHECK28-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
27671 // CHECK28:       omp.inner.for.body:
27672 // CHECK28-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25
27673 // CHECK28-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1
27674 // CHECK28-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
27675 // CHECK28-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !25
27676 // CHECK28-NEXT:    [[TMP4:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !25
27677 // CHECK28-NEXT:    [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1
27678 // CHECK28-NEXT:    store i32 [[ADD1]], i32* [[A]], align 4, !llvm.access.group !25
27679 // CHECK28-NEXT:    [[TMP5:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !25
27680 // CHECK28-NEXT:    [[CONV:%.*]] = sext i16 [[TMP5]] to i32
27681 // CHECK28-NEXT:    [[ADD2:%.*]] = add nsw i32 [[CONV]], 1
27682 // CHECK28-NEXT:    [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
27683 // CHECK28-NEXT:    store i16 [[CONV3]], i16* [[AA]], align 2, !llvm.access.group !25
27684 // CHECK28-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2
27685 // CHECK28-NEXT:    [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !25
27686 // CHECK28-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP6]], 1
27687 // CHECK28-NEXT:    store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !25
27688 // CHECK28-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
27689 // CHECK28:       omp.body.continue:
27690 // CHECK28-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
27691 // CHECK28:       omp.inner.for.inc:
27692 // CHECK28-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25
27693 // CHECK28-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP7]], 1
27694 // CHECK28-NEXT:    store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25
27695 // CHECK28-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP26:![0-9]+]]
27696 // CHECK28:       omp.inner.for.end:
27697 // CHECK28-NEXT:    store i32 10, i32* [[I]], align 4
27698 // CHECK28-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
27699 // CHECK28-NEXT:    ret i32 [[TMP8]]
27700 //
27701 //
27702 // CHECK29-LABEL: define {{[^@]+}}@_Z3fooi
27703 // CHECK29-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0:[0-9]+]] {
27704 // CHECK29-NEXT:  entry:
27705 // CHECK29-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
27706 // CHECK29-NEXT:    [[A:%.*]] = alloca i32, align 4
27707 // CHECK29-NEXT:    [[AA:%.*]] = alloca i16, align 2
27708 // CHECK29-NEXT:    [[B:%.*]] = alloca [10 x float], align 4
27709 // CHECK29-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 8
27710 // CHECK29-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
27711 // CHECK29-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 8
27712 // CHECK29-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i64, align 8
27713 // CHECK29-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8
27714 // CHECK29-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
27715 // CHECK29-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
27716 // CHECK29-NEXT:    [[TMP:%.*]] = alloca i32, align 4
27717 // CHECK29-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
27718 // CHECK29-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
27719 // CHECK29-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
27720 // CHECK29-NEXT:    [[I:%.*]] = alloca i32, align 4
27721 // CHECK29-NEXT:    [[_TMP4:%.*]] = alloca i32, align 4
27722 // CHECK29-NEXT:    [[DOTOMP_LB5:%.*]] = alloca i32, align 4
27723 // CHECK29-NEXT:    [[DOTOMP_UB6:%.*]] = alloca i32, align 4
27724 // CHECK29-NEXT:    [[DOTOMP_IV7:%.*]] = alloca i32, align 4
27725 // CHECK29-NEXT:    [[DOTLINEAR_START:%.*]] = alloca i32, align 4
27726 // CHECK29-NEXT:    [[A8:%.*]] = alloca i32, align 4
27727 // CHECK29-NEXT:    [[A9:%.*]] = alloca i32, align 4
27728 // CHECK29-NEXT:    [[_TMP20:%.*]] = alloca i32, align 4
27729 // CHECK29-NEXT:    [[DOTOMP_LB21:%.*]] = alloca i32, align 4
27730 // CHECK29-NEXT:    [[DOTOMP_UB22:%.*]] = alloca i32, align 4
27731 // CHECK29-NEXT:    [[DOTOMP_IV23:%.*]] = alloca i32, align 4
27732 // CHECK29-NEXT:    [[I24:%.*]] = alloca i32, align 4
27733 // CHECK29-NEXT:    [[_TMP36:%.*]] = alloca i32, align 4
27734 // CHECK29-NEXT:    [[DOTOMP_LB37:%.*]] = alloca i32, align 4
27735 // CHECK29-NEXT:    [[DOTOMP_UB38:%.*]] = alloca i32, align 4
27736 // CHECK29-NEXT:    [[DOTOMP_IV39:%.*]] = alloca i32, align 4
27737 // CHECK29-NEXT:    [[I40:%.*]] = alloca i32, align 4
27738 // CHECK29-NEXT:    [[_TMP54:%.*]] = alloca i32, align 4
27739 // CHECK29-NEXT:    [[DOTOMP_LB55:%.*]] = alloca i32, align 4
27740 // CHECK29-NEXT:    [[DOTOMP_UB56:%.*]] = alloca i32, align 4
27741 // CHECK29-NEXT:    [[DOTOMP_IV57:%.*]] = alloca i32, align 4
27742 // CHECK29-NEXT:    [[I58:%.*]] = alloca i32, align 4
27743 // CHECK29-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
27744 // CHECK29-NEXT:    store i32 0, i32* [[A]], align 4
27745 // CHECK29-NEXT:    store i16 0, i16* [[AA]], align 2
27746 // CHECK29-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
27747 // CHECK29-NEXT:    [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
27748 // CHECK29-NEXT:    [[TMP2:%.*]] = call i8* @llvm.stacksave()
27749 // CHECK29-NEXT:    store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8
27750 // CHECK29-NEXT:    [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4
27751 // CHECK29-NEXT:    store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8
27752 // CHECK29-NEXT:    [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
27753 // CHECK29-NEXT:    [[TMP4:%.*]] = zext i32 [[TMP3]] to i64
27754 // CHECK29-NEXT:    [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]]
27755 // CHECK29-NEXT:    [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8
27756 // CHECK29-NEXT:    store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8
27757 // CHECK29-NEXT:    [[TMP6:%.*]] = load i32, i32* [[A]], align 4
27758 // CHECK29-NEXT:    store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_]], align 4
27759 // CHECK29-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
27760 // CHECK29-NEXT:    store i32 [[TMP7]], i32* [[DOTCAPTURE_EXPR_2]], align 4
27761 // CHECK29-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
27762 // CHECK29-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
27763 // CHECK29-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
27764 // CHECK29-NEXT:    store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
27765 // CHECK29-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
27766 // CHECK29:       omp.inner.for.cond:
27767 // CHECK29-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
27768 // CHECK29-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !2
27769 // CHECK29-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
27770 // CHECK29-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
27771 // CHECK29:       omp.inner.for.body:
27772 // CHECK29-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
27773 // CHECK29-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
27774 // CHECK29-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
27775 // CHECK29-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !2
27776 // CHECK29-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
27777 // CHECK29:       omp.body.continue:
27778 // CHECK29-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
27779 // CHECK29:       omp.inner.for.inc:
27780 // CHECK29-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
27781 // CHECK29-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1
27782 // CHECK29-NEXT:    store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
27783 // CHECK29-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]
27784 // CHECK29:       omp.inner.for.end:
27785 // CHECK29-NEXT:    store i32 10, i32* [[I]], align 4
27786 // CHECK29-NEXT:    store i32 0, i32* [[DOTOMP_LB5]], align 4
27787 // CHECK29-NEXT:    store i32 9, i32* [[DOTOMP_UB6]], align 4
27788 // CHECK29-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB5]], align 4
27789 // CHECK29-NEXT:    store i32 [[TMP13]], i32* [[DOTOMP_IV7]], align 4
27790 // CHECK29-NEXT:    [[TMP14:%.*]] = load i32, i32* [[A]], align 4
27791 // CHECK29-NEXT:    store i32 [[TMP14]], i32* [[DOTLINEAR_START]], align 4
27792 // CHECK29-NEXT:    br label [[OMP_INNER_FOR_COND10:%.*]]
27793 // CHECK29:       omp.inner.for.cond10:
27794 // CHECK29-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV7]], align 4
27795 // CHECK29-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB6]], align 4
27796 // CHECK29-NEXT:    [[CMP11:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]]
27797 // CHECK29-NEXT:    br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY12:%.*]], label [[OMP_INNER_FOR_END19:%.*]]
27798 // CHECK29:       omp.inner.for.body12:
27799 // CHECK29-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV7]], align 4
27800 // CHECK29-NEXT:    [[MUL13:%.*]] = mul nsw i32 [[TMP17]], 1
27801 // CHECK29-NEXT:    [[ADD14:%.*]] = add nsw i32 0, [[MUL13]]
27802 // CHECK29-NEXT:    store i32 [[ADD14]], i32* [[A8]], align 4, !nontemporal !7
27803 // CHECK29-NEXT:    [[TMP18:%.*]] = load i32, i32* [[A8]], align 4, !nontemporal !7
27804 // CHECK29-NEXT:    [[ADD15:%.*]] = add nsw i32 [[TMP18]], 1
27805 // CHECK29-NEXT:    store i32 [[ADD15]], i32* [[A8]], align 4, !nontemporal !7
27806 // CHECK29-NEXT:    br label [[OMP_BODY_CONTINUE16:%.*]]
27807 // CHECK29:       omp.body.continue16:
27808 // CHECK29-NEXT:    br label [[OMP_INNER_FOR_INC17:%.*]]
27809 // CHECK29:       omp.inner.for.inc17:
27810 // CHECK29-NEXT:    [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV7]], align 4
27811 // CHECK29-NEXT:    [[ADD18:%.*]] = add nsw i32 [[TMP19]], 1
27812 // CHECK29-NEXT:    store i32 [[ADD18]], i32* [[DOTOMP_IV7]], align 4
27813 // CHECK29-NEXT:    br label [[OMP_INNER_FOR_COND10]], !llvm.loop [[LOOP8:![0-9]+]]
27814 // CHECK29:       omp.inner.for.end19:
27815 // CHECK29-NEXT:    store i32 10, i32* [[A]], align 4
27816 // CHECK29-NEXT:    store i32 0, i32* [[DOTOMP_LB21]], align 4
27817 // CHECK29-NEXT:    store i32 9, i32* [[DOTOMP_UB22]], align 4
27818 // CHECK29-NEXT:    [[TMP20:%.*]] = load i32, i32* [[DOTOMP_LB21]], align 4
27819 // CHECK29-NEXT:    store i32 [[TMP20]], i32* [[DOTOMP_IV23]], align 4
27820 // CHECK29-NEXT:    br label [[OMP_INNER_FOR_COND25:%.*]]
27821 // CHECK29:       omp.inner.for.cond25:
27822 // CHECK29-NEXT:    [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV23]], align 4, !llvm.access.group !10
27823 // CHECK29-NEXT:    [[TMP22:%.*]] = load i32, i32* [[DOTOMP_UB22]], align 4, !llvm.access.group !10
27824 // CHECK29-NEXT:    [[CMP26:%.*]] = icmp sle i32 [[TMP21]], [[TMP22]]
27825 // CHECK29-NEXT:    br i1 [[CMP26]], label [[OMP_INNER_FOR_BODY27:%.*]], label [[OMP_INNER_FOR_END35:%.*]]
27826 // CHECK29:       omp.inner.for.body27:
27827 // CHECK29-NEXT:    [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV23]], align 4, !llvm.access.group !10
27828 // CHECK29-NEXT:    [[MUL28:%.*]] = mul nsw i32 [[TMP23]], 1
27829 // CHECK29-NEXT:    [[ADD29:%.*]] = add nsw i32 0, [[MUL28]]
27830 // CHECK29-NEXT:    store i32 [[ADD29]], i32* [[I24]], align 4, !llvm.access.group !10
27831 // CHECK29-NEXT:    [[TMP24:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !10
27832 // CHECK29-NEXT:    [[CONV:%.*]] = sext i16 [[TMP24]] to i32
27833 // CHECK29-NEXT:    [[ADD30:%.*]] = add nsw i32 [[CONV]], 1
27834 // CHECK29-NEXT:    [[CONV31:%.*]] = trunc i32 [[ADD30]] to i16
27835 // CHECK29-NEXT:    store i16 [[CONV31]], i16* [[AA]], align 2, !llvm.access.group !10
27836 // CHECK29-NEXT:    br label [[OMP_BODY_CONTINUE32:%.*]]
27837 // CHECK29:       omp.body.continue32:
27838 // CHECK29-NEXT:    br label [[OMP_INNER_FOR_INC33:%.*]]
27839 // CHECK29:       omp.inner.for.inc33:
27840 // CHECK29-NEXT:    [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IV23]], align 4, !llvm.access.group !10
27841 // CHECK29-NEXT:    [[ADD34:%.*]] = add nsw i32 [[TMP25]], 1
27842 // CHECK29-NEXT:    store i32 [[ADD34]], i32* [[DOTOMP_IV23]], align 4, !llvm.access.group !10
27843 // CHECK29-NEXT:    br label [[OMP_INNER_FOR_COND25]], !llvm.loop [[LOOP11:![0-9]+]]
27844 // CHECK29:       omp.inner.for.end35:
27845 // CHECK29-NEXT:    store i32 10, i32* [[I24]], align 4
27846 // CHECK29-NEXT:    store i32 0, i32* [[DOTOMP_LB37]], align 4
27847 // CHECK29-NEXT:    store i32 9, i32* [[DOTOMP_UB38]], align 4
27848 // CHECK29-NEXT:    [[TMP26:%.*]] = load i32, i32* [[DOTOMP_LB37]], align 4
27849 // CHECK29-NEXT:    store i32 [[TMP26]], i32* [[DOTOMP_IV39]], align 4
27850 // CHECK29-NEXT:    br label [[OMP_INNER_FOR_COND41:%.*]]
27851 // CHECK29:       omp.inner.for.cond41:
27852 // CHECK29-NEXT:    [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV39]], align 4, !llvm.access.group !13
27853 // CHECK29-NEXT:    [[TMP28:%.*]] = load i32, i32* [[DOTOMP_UB38]], align 4, !llvm.access.group !13
27854 // CHECK29-NEXT:    [[CMP42:%.*]] = icmp sle i32 [[TMP27]], [[TMP28]]
27855 // CHECK29-NEXT:    br i1 [[CMP42]], label [[OMP_INNER_FOR_BODY43:%.*]], label [[OMP_INNER_FOR_END53:%.*]]
27856 // CHECK29:       omp.inner.for.body43:
27857 // CHECK29-NEXT:    [[TMP29:%.*]] = load i32, i32* [[DOTOMP_IV39]], align 4, !llvm.access.group !13
27858 // CHECK29-NEXT:    [[MUL44:%.*]] = mul nsw i32 [[TMP29]], 1
27859 // CHECK29-NEXT:    [[ADD45:%.*]] = add nsw i32 0, [[MUL44]]
27860 // CHECK29-NEXT:    store i32 [[ADD45]], i32* [[I40]], align 4, !llvm.access.group !13
27861 // CHECK29-NEXT:    [[TMP30:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !13
27862 // CHECK29-NEXT:    [[ADD46:%.*]] = add nsw i32 [[TMP30]], 1
27863 // CHECK29-NEXT:    store i32 [[ADD46]], i32* [[A]], align 4, !llvm.access.group !13
27864 // CHECK29-NEXT:    [[TMP31:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !13
27865 // CHECK29-NEXT:    [[CONV47:%.*]] = sext i16 [[TMP31]] to i32
27866 // CHECK29-NEXT:    [[ADD48:%.*]] = add nsw i32 [[CONV47]], 1
27867 // CHECK29-NEXT:    [[CONV49:%.*]] = trunc i32 [[ADD48]] to i16
27868 // CHECK29-NEXT:    store i16 [[CONV49]], i16* [[AA]], align 2, !llvm.access.group !13
27869 // CHECK29-NEXT:    br label [[OMP_BODY_CONTINUE50:%.*]]
27870 // CHECK29:       omp.body.continue50:
27871 // CHECK29-NEXT:    br label [[OMP_INNER_FOR_INC51:%.*]]
27872 // CHECK29:       omp.inner.for.inc51:
27873 // CHECK29-NEXT:    [[TMP32:%.*]] = load i32, i32* [[DOTOMP_IV39]], align 4, !llvm.access.group !13
27874 // CHECK29-NEXT:    [[ADD52:%.*]] = add nsw i32 [[TMP32]], 1
27875 // CHECK29-NEXT:    store i32 [[ADD52]], i32* [[DOTOMP_IV39]], align 4, !llvm.access.group !13
27876 // CHECK29-NEXT:    br label [[OMP_INNER_FOR_COND41]], !llvm.loop [[LOOP14:![0-9]+]]
27877 // CHECK29:       omp.inner.for.end53:
27878 // CHECK29-NEXT:    store i32 10, i32* [[I40]], align 4
27879 // CHECK29-NEXT:    store i32 0, i32* [[DOTOMP_LB55]], align 4
27880 // CHECK29-NEXT:    store i32 9, i32* [[DOTOMP_UB56]], align 4
27881 // CHECK29-NEXT:    [[TMP33:%.*]] = load i32, i32* [[DOTOMP_LB55]], align 4
27882 // CHECK29-NEXT:    store i32 [[TMP33]], i32* [[DOTOMP_IV57]], align 4
27883 // CHECK29-NEXT:    [[ARRAYDECAY:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 0
27884 // CHECK29-NEXT:    call void @llvm.assume(i1 true) [ "align"(float* [[ARRAYDECAY]], i64 16) ]
27885 // CHECK29-NEXT:    br label [[OMP_INNER_FOR_COND59:%.*]]
27886 // CHECK29:       omp.inner.for.cond59:
27887 // CHECK29-NEXT:    [[TMP34:%.*]] = load i32, i32* [[DOTOMP_IV57]], align 4, !llvm.access.group !16
27888 // CHECK29-NEXT:    [[TMP35:%.*]] = load i32, i32* [[DOTOMP_UB56]], align 4, !llvm.access.group !16
27889 // CHECK29-NEXT:    [[CMP60:%.*]] = icmp sle i32 [[TMP34]], [[TMP35]]
27890 // CHECK29-NEXT:    br i1 [[CMP60]], label [[OMP_INNER_FOR_BODY61:%.*]], label [[OMP_INNER_FOR_END85:%.*]]
27891 // CHECK29:       omp.inner.for.body61:
27892 // CHECK29-NEXT:    [[TMP36:%.*]] = load i32, i32* [[DOTOMP_IV57]], align 4, !llvm.access.group !16
27893 // CHECK29-NEXT:    [[MUL62:%.*]] = mul nsw i32 [[TMP36]], 1
27894 // CHECK29-NEXT:    [[ADD63:%.*]] = add nsw i32 0, [[MUL62]]
27895 // CHECK29-NEXT:    store i32 [[ADD63]], i32* [[I58]], align 4, !llvm.access.group !16
27896 // CHECK29-NEXT:    [[TMP37:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !16
27897 // CHECK29-NEXT:    [[ADD64:%.*]] = add nsw i32 [[TMP37]], 1
27898 // CHECK29-NEXT:    store i32 [[ADD64]], i32* [[A]], align 4, !llvm.access.group !16
27899 // CHECK29-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2
27900 // CHECK29-NEXT:    [[TMP38:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !16
27901 // CHECK29-NEXT:    [[CONV65:%.*]] = fpext float [[TMP38]] to double
27902 // CHECK29-NEXT:    [[ADD66:%.*]] = fadd double [[CONV65]], 1.000000e+00
27903 // CHECK29-NEXT:    [[CONV67:%.*]] = fptrunc double [[ADD66]] to float
27904 // CHECK29-NEXT:    store float [[CONV67]], float* [[ARRAYIDX]], align 4, !llvm.access.group !16
27905 // CHECK29-NEXT:    [[ARRAYIDX68:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3
27906 // CHECK29-NEXT:    [[TMP39:%.*]] = load float, float* [[ARRAYIDX68]], align 4, !llvm.access.group !16
27907 // CHECK29-NEXT:    [[CONV69:%.*]] = fpext float [[TMP39]] to double
27908 // CHECK29-NEXT:    [[ADD70:%.*]] = fadd double [[CONV69]], 1.000000e+00
27909 // CHECK29-NEXT:    [[CONV71:%.*]] = fptrunc double [[ADD70]] to float
27910 // CHECK29-NEXT:    store float [[CONV71]], float* [[ARRAYIDX68]], align 4, !llvm.access.group !16
27911 // CHECK29-NEXT:    [[ARRAYIDX72:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1
27912 // CHECK29-NEXT:    [[ARRAYIDX73:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX72]], i64 0, i64 2
27913 // CHECK29-NEXT:    [[TMP40:%.*]] = load double, double* [[ARRAYIDX73]], align 8, !llvm.access.group !16
27914 // CHECK29-NEXT:    [[ADD74:%.*]] = fadd double [[TMP40]], 1.000000e+00
27915 // CHECK29-NEXT:    store double [[ADD74]], double* [[ARRAYIDX73]], align 8, !llvm.access.group !16
27916 // CHECK29-NEXT:    [[TMP41:%.*]] = mul nsw i64 1, [[TMP4]]
27917 // CHECK29-NEXT:    [[ARRAYIDX75:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP41]]
27918 // CHECK29-NEXT:    [[ARRAYIDX76:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX75]], i64 3
27919 // CHECK29-NEXT:    [[TMP42:%.*]] = load double, double* [[ARRAYIDX76]], align 8, !llvm.access.group !16
27920 // CHECK29-NEXT:    [[ADD77:%.*]] = fadd double [[TMP42]], 1.000000e+00
27921 // CHECK29-NEXT:    store double [[ADD77]], double* [[ARRAYIDX76]], align 8, !llvm.access.group !16
27922 // CHECK29-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0
27923 // CHECK29-NEXT:    [[TMP43:%.*]] = load i64, i64* [[X]], align 8, !llvm.access.group !16
27924 // CHECK29-NEXT:    [[ADD78:%.*]] = add nsw i64 [[TMP43]], 1
27925 // CHECK29-NEXT:    store i64 [[ADD78]], i64* [[X]], align 8, !llvm.access.group !16
27926 // CHECK29-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1
27927 // CHECK29-NEXT:    [[TMP44:%.*]] = load i8, i8* [[Y]], align 8, !llvm.access.group !16
27928 // CHECK29-NEXT:    [[CONV79:%.*]] = sext i8 [[TMP44]] to i32
27929 // CHECK29-NEXT:    [[ADD80:%.*]] = add nsw i32 [[CONV79]], 1
27930 // CHECK29-NEXT:    [[CONV81:%.*]] = trunc i32 [[ADD80]] to i8
27931 // CHECK29-NEXT:    store i8 [[CONV81]], i8* [[Y]], align 8, !llvm.access.group !16
27932 // CHECK29-NEXT:    br label [[OMP_BODY_CONTINUE82:%.*]]
27933 // CHECK29:       omp.body.continue82:
27934 // CHECK29-NEXT:    br label [[OMP_INNER_FOR_INC83:%.*]]
27935 // CHECK29:       omp.inner.for.inc83:
27936 // CHECK29-NEXT:    [[TMP45:%.*]] = load i32, i32* [[DOTOMP_IV57]], align 4, !llvm.access.group !16
27937 // CHECK29-NEXT:    [[ADD84:%.*]] = add nsw i32 [[TMP45]], 1
27938 // CHECK29-NEXT:    store i32 [[ADD84]], i32* [[DOTOMP_IV57]], align 4, !llvm.access.group !16
27939 // CHECK29-NEXT:    br label [[OMP_INNER_FOR_COND59]], !llvm.loop [[LOOP17:![0-9]+]]
27940 // CHECK29:       omp.inner.for.end85:
27941 // CHECK29-NEXT:    store i32 10, i32* [[I58]], align 4
27942 // CHECK29-NEXT:    [[TMP46:%.*]] = load i32, i32* [[A]], align 4
27943 // CHECK29-NEXT:    [[TMP47:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
27944 // CHECK29-NEXT:    call void @llvm.stackrestore(i8* [[TMP47]])
27945 // CHECK29-NEXT:    ret i32 [[TMP46]]
27946 //
27947 //
27948 // CHECK29-LABEL: define {{[^@]+}}@_Z3bari
27949 // CHECK29-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {
27950 // CHECK29-NEXT:  entry:
27951 // CHECK29-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
27952 // CHECK29-NEXT:    [[A:%.*]] = alloca i32, align 4
27953 // CHECK29-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8
27954 // CHECK29-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
27955 // CHECK29-NEXT:    store i32 0, i32* [[A]], align 4
27956 // CHECK29-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
27957 // CHECK29-NEXT:    [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]])
27958 // CHECK29-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
27959 // CHECK29-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
27960 // CHECK29-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
27961 // CHECK29-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
27962 // CHECK29-NEXT:    [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP2]])
27963 // CHECK29-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
27964 // CHECK29-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
27965 // CHECK29-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
27966 // CHECK29-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
27967 // CHECK29-NEXT:    [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]])
27968 // CHECK29-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
27969 // CHECK29-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
27970 // CHECK29-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
27971 // CHECK29-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
27972 // CHECK29-NEXT:    [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]])
27973 // CHECK29-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
27974 // CHECK29-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
27975 // CHECK29-NEXT:    store i32 [[ADD6]], i32* [[A]], align 4
27976 // CHECK29-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
27977 // CHECK29-NEXT:    ret i32 [[TMP8]]
27978 //
27979 //
27980 // CHECK29-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
27981 // CHECK29-SAME: (%struct.S1* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 {
27982 // CHECK29-NEXT:  entry:
27983 // CHECK29-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
27984 // CHECK29-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
27985 // CHECK29-NEXT:    [[B:%.*]] = alloca i32, align 4
27986 // CHECK29-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 8
27987 // CHECK29-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
27988 // CHECK29-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
27989 // CHECK29-NEXT:    [[TMP:%.*]] = alloca i32, align 4
27990 // CHECK29-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
27991 // CHECK29-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
27992 // CHECK29-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
27993 // CHECK29-NEXT:    [[I:%.*]] = alloca i32, align 4
27994 // CHECK29-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
27995 // CHECK29-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
27996 // CHECK29-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
27997 // CHECK29-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
27998 // CHECK29-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
27999 // CHECK29-NEXT:    store i32 [[ADD]], i32* [[B]], align 4
28000 // CHECK29-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
28001 // CHECK29-NEXT:    [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
28002 // CHECK29-NEXT:    [[TMP3:%.*]] = call i8* @llvm.stacksave()
28003 // CHECK29-NEXT:    store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8
28004 // CHECK29-NEXT:    [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]
28005 // CHECK29-NEXT:    [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2
28006 // CHECK29-NEXT:    store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8
28007 // CHECK29-NEXT:    [[TMP5:%.*]] = load i32, i32* [[N_ADDR]], align 4
28008 // CHECK29-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 60
28009 // CHECK29-NEXT:    [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8
28010 // CHECK29-NEXT:    store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
28011 // CHECK29-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
28012 // CHECK29-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
28013 // CHECK29-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
28014 // CHECK29-NEXT:    store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
28015 // CHECK29-NEXT:    [[TMP7:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
28016 // CHECK29-NEXT:    [[TOBOOL:%.*]] = trunc i8 [[TMP7]] to i1
28017 // CHECK29-NEXT:    br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
28018 // CHECK29:       omp_if.then:
28019 // CHECK29-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
28020 // CHECK29:       omp.inner.for.cond:
28021 // CHECK29-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
28022 // CHECK29-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !19
28023 // CHECK29-NEXT:    [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
28024 // CHECK29-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
28025 // CHECK29:       omp.inner.for.body:
28026 // CHECK29-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
28027 // CHECK29-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
28028 // CHECK29-NEXT:    [[ADD3:%.*]] = add nsw i32 0, [[MUL]]
28029 // CHECK29-NEXT:    store i32 [[ADD3]], i32* [[I]], align 4, !llvm.access.group !19
28030 // CHECK29-NEXT:    [[TMP11:%.*]] = load i32, i32* [[B]], align 4, !llvm.access.group !19
28031 // CHECK29-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP11]] to double
28032 // CHECK29-NEXT:    [[ADD4:%.*]] = fadd double [[CONV]], 1.500000e+00
28033 // CHECK29-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
28034 // CHECK29-NEXT:    store double [[ADD4]], double* [[A]], align 8, !llvm.access.group !19
28035 // CHECK29-NEXT:    [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
28036 // CHECK29-NEXT:    [[TMP12:%.*]] = load double, double* [[A5]], align 8, !llvm.access.group !19
28037 // CHECK29-NEXT:    [[INC:%.*]] = fadd double [[TMP12]], 1.000000e+00
28038 // CHECK29-NEXT:    store double [[INC]], double* [[A5]], align 8, !llvm.access.group !19
28039 // CHECK29-NEXT:    [[CONV6:%.*]] = fptosi double [[INC]] to i16
28040 // CHECK29-NEXT:    [[TMP13:%.*]] = mul nsw i64 1, [[TMP2]]
28041 // CHECK29-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP13]]
28042 // CHECK29-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
28043 // CHECK29-NEXT:    store i16 [[CONV6]], i16* [[ARRAYIDX7]], align 2, !llvm.access.group !19
28044 // CHECK29-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
28045 // CHECK29:       omp.body.continue:
28046 // CHECK29-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
28047 // CHECK29:       omp.inner.for.inc:
28048 // CHECK29-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
28049 // CHECK29-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP14]], 1
28050 // CHECK29-NEXT:    store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
28051 // CHECK29-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]]
28052 // CHECK29:       omp.inner.for.end:
28053 // CHECK29-NEXT:    br label [[OMP_IF_END:%.*]]
28054 // CHECK29:       omp_if.else:
28055 // CHECK29-NEXT:    br label [[OMP_INNER_FOR_COND9:%.*]]
28056 // CHECK29:       omp.inner.for.cond9:
28057 // CHECK29-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
28058 // CHECK29-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
28059 // CHECK29-NEXT:    [[CMP10:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]]
28060 // CHECK29-NEXT:    br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY11:%.*]], label [[OMP_INNER_FOR_END25:%.*]]
28061 // CHECK29:       omp.inner.for.body11:
28062 // CHECK29-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
28063 // CHECK29-NEXT:    [[MUL12:%.*]] = mul nsw i32 [[TMP17]], 1
28064 // CHECK29-NEXT:    [[ADD13:%.*]] = add nsw i32 0, [[MUL12]]
28065 // CHECK29-NEXT:    store i32 [[ADD13]], i32* [[I]], align 4
28066 // CHECK29-NEXT:    [[TMP18:%.*]] = load i32, i32* [[B]], align 4
28067 // CHECK29-NEXT:    [[CONV14:%.*]] = sitofp i32 [[TMP18]] to double
28068 // CHECK29-NEXT:    [[ADD15:%.*]] = fadd double [[CONV14]], 1.500000e+00
28069 // CHECK29-NEXT:    [[A16:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
28070 // CHECK29-NEXT:    store double [[ADD15]], double* [[A16]], align 8
28071 // CHECK29-NEXT:    [[A17:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
28072 // CHECK29-NEXT:    [[TMP19:%.*]] = load double, double* [[A17]], align 8
28073 // CHECK29-NEXT:    [[INC18:%.*]] = fadd double [[TMP19]], 1.000000e+00
28074 // CHECK29-NEXT:    store double [[INC18]], double* [[A17]], align 8
28075 // CHECK29-NEXT:    [[CONV19:%.*]] = fptosi double [[INC18]] to i16
28076 // CHECK29-NEXT:    [[TMP20:%.*]] = mul nsw i64 1, [[TMP2]]
28077 // CHECK29-NEXT:    [[ARRAYIDX20:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP20]]
28078 // CHECK29-NEXT:    [[ARRAYIDX21:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX20]], i64 1
28079 // CHECK29-NEXT:    store i16 [[CONV19]], i16* [[ARRAYIDX21]], align 2
28080 // CHECK29-NEXT:    br label [[OMP_BODY_CONTINUE22:%.*]]
28081 // CHECK29:       omp.body.continue22:
28082 // CHECK29-NEXT:    br label [[OMP_INNER_FOR_INC23:%.*]]
28083 // CHECK29:       omp.inner.for.inc23:
28084 // CHECK29-NEXT:    [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
28085 // CHECK29-NEXT:    [[ADD24:%.*]] = add nsw i32 [[TMP21]], 1
28086 // CHECK29-NEXT:    store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4
28087 // CHECK29-NEXT:    br label [[OMP_INNER_FOR_COND9]], !llvm.loop [[LOOP22:![0-9]+]]
28088 // CHECK29:       omp.inner.for.end25:
28089 // CHECK29-NEXT:    br label [[OMP_IF_END]]
28090 // CHECK29:       omp_if.end:
28091 // CHECK29-NEXT:    store i32 10, i32* [[I]], align 4
28092 // CHECK29-NEXT:    [[TMP22:%.*]] = mul nsw i64 1, [[TMP2]]
28093 // CHECK29-NEXT:    [[ARRAYIDX26:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP22]]
28094 // CHECK29-NEXT:    [[ARRAYIDX27:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX26]], i64 1
28095 // CHECK29-NEXT:    [[TMP23:%.*]] = load i16, i16* [[ARRAYIDX27]], align 2
28096 // CHECK29-NEXT:    [[CONV28:%.*]] = sext i16 [[TMP23]] to i32
28097 // CHECK29-NEXT:    [[TMP24:%.*]] = load i32, i32* [[B]], align 4
28098 // CHECK29-NEXT:    [[ADD29:%.*]] = add nsw i32 [[CONV28]], [[TMP24]]
28099 // CHECK29-NEXT:    [[TMP25:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
28100 // CHECK29-NEXT:    call void @llvm.stackrestore(i8* [[TMP25]])
28101 // CHECK29-NEXT:    ret i32 [[ADD29]]
28102 //
28103 //
28104 // CHECK29-LABEL: define {{[^@]+}}@_ZL7fstatici
28105 // CHECK29-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {
28106 // CHECK29-NEXT:  entry:
28107 // CHECK29-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
28108 // CHECK29-NEXT:    [[A:%.*]] = alloca i32, align 4
28109 // CHECK29-NEXT:    [[AA:%.*]] = alloca i16, align 2
28110 // CHECK29-NEXT:    [[AAA:%.*]] = alloca i8, align 1
28111 // CHECK29-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
28112 // CHECK29-NEXT:    [[TMP:%.*]] = alloca i32, align 4
28113 // CHECK29-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
28114 // CHECK29-NEXT:    [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
28115 // CHECK29-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
28116 // CHECK29-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
28117 // CHECK29-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
28118 // CHECK29-NEXT:    [[I:%.*]] = alloca i32, align 4
28119 // CHECK29-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
28120 // CHECK29-NEXT:    [[I5:%.*]] = alloca i32, align 4
28121 // CHECK29-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
28122 // CHECK29-NEXT:    store i32 0, i32* [[A]], align 4
28123 // CHECK29-NEXT:    store i16 0, i16* [[AA]], align 2
28124 // CHECK29-NEXT:    store i8 0, i8* [[AAA]], align 1
28125 // CHECK29-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
28126 // CHECK29-NEXT:    store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4
28127 // CHECK29-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
28128 // CHECK29-NEXT:    store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_1]], align 4
28129 // CHECK29-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
28130 // CHECK29-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
28131 // CHECK29-NEXT:    [[SUB:%.*]] = sub i32 [[TMP2]], [[TMP3]]
28132 // CHECK29-NEXT:    [[SUB3:%.*]] = sub i32 [[SUB]], 1
28133 // CHECK29-NEXT:    [[ADD:%.*]] = add i32 [[SUB3]], 1
28134 // CHECK29-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], 1
28135 // CHECK29-NEXT:    [[SUB4:%.*]] = sub i32 [[DIV]], 1
28136 // CHECK29-NEXT:    store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_2]], align 4
28137 // CHECK29-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
28138 // CHECK29-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
28139 // CHECK29-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_UB]], align 4
28140 // CHECK29-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
28141 // CHECK29-NEXT:    store i32 [[TMP5]], i32* [[I]], align 4
28142 // CHECK29-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
28143 // CHECK29-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
28144 // CHECK29-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]]
28145 // CHECK29-NEXT:    br i1 [[CMP]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END:%.*]]
28146 // CHECK29:       simd.if.then:
28147 // CHECK29-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
28148 // CHECK29-NEXT:    store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
28149 // CHECK29-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
28150 // CHECK29:       omp.inner.for.cond:
28151 // CHECK29-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
28152 // CHECK29-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !24
28153 // CHECK29-NEXT:    [[ADD6:%.*]] = add i32 [[TMP10]], 1
28154 // CHECK29-NEXT:    [[CMP7:%.*]] = icmp ult i32 [[TMP9]], [[ADD6]]
28155 // CHECK29-NEXT:    br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
28156 // CHECK29:       omp.inner.for.body:
28157 // CHECK29-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group !24
28158 // CHECK29-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
28159 // CHECK29-NEXT:    [[MUL:%.*]] = mul i32 [[TMP12]], 1
28160 // CHECK29-NEXT:    [[ADD8:%.*]] = add i32 [[TMP11]], [[MUL]]
28161 // CHECK29-NEXT:    store i32 [[ADD8]], i32* [[I5]], align 4, !llvm.access.group !24
28162 // CHECK29-NEXT:    [[TMP13:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !24
28163 // CHECK29-NEXT:    [[ADD9:%.*]] = add nsw i32 [[TMP13]], 1
28164 // CHECK29-NEXT:    store i32 [[ADD9]], i32* [[A]], align 4, !llvm.access.group !24
28165 // CHECK29-NEXT:    [[TMP14:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !24
28166 // CHECK29-NEXT:    [[CONV:%.*]] = sext i16 [[TMP14]] to i32
28167 // CHECK29-NEXT:    [[ADD10:%.*]] = add nsw i32 [[CONV]], 1
28168 // CHECK29-NEXT:    [[CONV11:%.*]] = trunc i32 [[ADD10]] to i16
28169 // CHECK29-NEXT:    store i16 [[CONV11]], i16* [[AA]], align 2, !llvm.access.group !24
28170 // CHECK29-NEXT:    [[TMP15:%.*]] = load i8, i8* [[AAA]], align 1, !llvm.access.group !24
28171 // CHECK29-NEXT:    [[CONV12:%.*]] = sext i8 [[TMP15]] to i32
28172 // CHECK29-NEXT:    [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1
28173 // CHECK29-NEXT:    [[CONV14:%.*]] = trunc i32 [[ADD13]] to i8
28174 // CHECK29-NEXT:    store i8 [[CONV14]], i8* [[AAA]], align 1, !llvm.access.group !24
28175 // CHECK29-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2
28176 // CHECK29-NEXT:    [[TMP16:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !24
28177 // CHECK29-NEXT:    [[ADD15:%.*]] = add nsw i32 [[TMP16]], 1
28178 // CHECK29-NEXT:    store i32 [[ADD15]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !24
28179 // CHECK29-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
28180 // CHECK29:       omp.body.continue:
28181 // CHECK29-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
28182 // CHECK29:       omp.inner.for.inc:
28183 // CHECK29-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
28184 // CHECK29-NEXT:    [[ADD16:%.*]] = add i32 [[TMP17]], 1
28185 // CHECK29-NEXT:    store i32 [[ADD16]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
28186 // CHECK29-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]]
28187 // CHECK29:       omp.inner.for.end:
28188 // CHECK29-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
28189 // CHECK29-NEXT:    [[TMP19:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
28190 // CHECK29-NEXT:    [[TMP20:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
28191 // CHECK29-NEXT:    [[SUB17:%.*]] = sub i32 [[TMP19]], [[TMP20]]
28192 // CHECK29-NEXT:    [[SUB18:%.*]] = sub i32 [[SUB17]], 1
28193 // CHECK29-NEXT:    [[ADD19:%.*]] = add i32 [[SUB18]], 1
28194 // CHECK29-NEXT:    [[DIV20:%.*]] = udiv i32 [[ADD19]], 1
28195 // CHECK29-NEXT:    [[MUL21:%.*]] = mul i32 [[DIV20]], 1
28196 // CHECK29-NEXT:    [[ADD22:%.*]] = add i32 [[TMP18]], [[MUL21]]
28197 // CHECK29-NEXT:    store i32 [[ADD22]], i32* [[I5]], align 4
28198 // CHECK29-NEXT:    br label [[SIMD_IF_END]]
28199 // CHECK29:       simd.if.end:
28200 // CHECK29-NEXT:    [[TMP21:%.*]] = load i32, i32* [[A]], align 4
28201 // CHECK29-NEXT:    ret i32 [[TMP21]]
28202 //
28203 //
28204 // CHECK29-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
28205 // CHECK29-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat {
28206 // CHECK29-NEXT:  entry:
28207 // CHECK29-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
28208 // CHECK29-NEXT:    [[A:%.*]] = alloca i32, align 4
28209 // CHECK29-NEXT:    [[AA:%.*]] = alloca i16, align 2
28210 // CHECK29-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
28211 // CHECK29-NEXT:    [[TMP:%.*]] = alloca i32, align 4
28212 // CHECK29-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
28213 // CHECK29-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
28214 // CHECK29-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
28215 // CHECK29-NEXT:    [[I:%.*]] = alloca i32, align 4
28216 // CHECK29-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
28217 // CHECK29-NEXT:    store i32 0, i32* [[A]], align 4
28218 // CHECK29-NEXT:    store i16 0, i16* [[AA]], align 2
28219 // CHECK29-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
28220 // CHECK29-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
28221 // CHECK29-NEXT:    [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
28222 // CHECK29-NEXT:    store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4
28223 // CHECK29-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
28224 // CHECK29:       omp.inner.for.cond:
28225 // CHECK29-NEXT:    [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27
28226 // CHECK29-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !27
28227 // CHECK29-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
28228 // CHECK29-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
28229 // CHECK29:       omp.inner.for.body:
28230 // CHECK29-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27
28231 // CHECK29-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1
28232 // CHECK29-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
28233 // CHECK29-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !27
28234 // CHECK29-NEXT:    [[TMP4:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !27
28235 // CHECK29-NEXT:    [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1
28236 // CHECK29-NEXT:    store i32 [[ADD1]], i32* [[A]], align 4, !llvm.access.group !27
28237 // CHECK29-NEXT:    [[TMP5:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !27
28238 // CHECK29-NEXT:    [[CONV:%.*]] = sext i16 [[TMP5]] to i32
28239 // CHECK29-NEXT:    [[ADD2:%.*]] = add nsw i32 [[CONV]], 1
28240 // CHECK29-NEXT:    [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
28241 // CHECK29-NEXT:    store i16 [[CONV3]], i16* [[AA]], align 2, !llvm.access.group !27
28242 // CHECK29-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2
28243 // CHECK29-NEXT:    [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !27
28244 // CHECK29-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP6]], 1
28245 // CHECK29-NEXT:    store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !27
28246 // CHECK29-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
28247 // CHECK29:       omp.body.continue:
28248 // CHECK29-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
28249 // CHECK29:       omp.inner.for.inc:
28250 // CHECK29-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27
28251 // CHECK29-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP7]], 1
28252 // CHECK29-NEXT:    store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27
28253 // CHECK29-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]]
28254 // CHECK29:       omp.inner.for.end:
28255 // CHECK29-NEXT:    store i32 10, i32* [[I]], align 4
28256 // CHECK29-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
28257 // CHECK29-NEXT:    ret i32 [[TMP8]]
28258 //
28259 //
28260 // CHECK30-LABEL: define {{[^@]+}}@_Z3fooi
28261 // CHECK30-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0:[0-9]+]] {
28262 // CHECK30-NEXT:  entry:
28263 // CHECK30-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
28264 // CHECK30-NEXT:    [[A:%.*]] = alloca i32, align 4
28265 // CHECK30-NEXT:    [[AA:%.*]] = alloca i16, align 2
28266 // CHECK30-NEXT:    [[B:%.*]] = alloca [10 x float], align 4
28267 // CHECK30-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 8
28268 // CHECK30-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
28269 // CHECK30-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 8
28270 // CHECK30-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i64, align 8
28271 // CHECK30-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8
28272 // CHECK30-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
28273 // CHECK30-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
28274 // CHECK30-NEXT:    [[TMP:%.*]] = alloca i32, align 4
28275 // CHECK30-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
28276 // CHECK30-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
28277 // CHECK30-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
28278 // CHECK30-NEXT:    [[I:%.*]] = alloca i32, align 4
28279 // CHECK30-NEXT:    [[_TMP4:%.*]] = alloca i32, align 4
28280 // CHECK30-NEXT:    [[DOTOMP_LB5:%.*]] = alloca i32, align 4
28281 // CHECK30-NEXT:    [[DOTOMP_UB6:%.*]] = alloca i32, align 4
28282 // CHECK30-NEXT:    [[DOTOMP_IV7:%.*]] = alloca i32, align 4
28283 // CHECK30-NEXT:    [[DOTLINEAR_START:%.*]] = alloca i32, align 4
28284 // CHECK30-NEXT:    [[A8:%.*]] = alloca i32, align 4
28285 // CHECK30-NEXT:    [[A9:%.*]] = alloca i32, align 4
28286 // CHECK30-NEXT:    [[_TMP20:%.*]] = alloca i32, align 4
28287 // CHECK30-NEXT:    [[DOTOMP_LB21:%.*]] = alloca i32, align 4
28288 // CHECK30-NEXT:    [[DOTOMP_UB22:%.*]] = alloca i32, align 4
28289 // CHECK30-NEXT:    [[DOTOMP_IV23:%.*]] = alloca i32, align 4
28290 // CHECK30-NEXT:    [[I24:%.*]] = alloca i32, align 4
28291 // CHECK30-NEXT:    [[_TMP36:%.*]] = alloca i32, align 4
28292 // CHECK30-NEXT:    [[DOTOMP_LB37:%.*]] = alloca i32, align 4
28293 // CHECK30-NEXT:    [[DOTOMP_UB38:%.*]] = alloca i32, align 4
28294 // CHECK30-NEXT:    [[DOTOMP_IV39:%.*]] = alloca i32, align 4
28295 // CHECK30-NEXT:    [[I40:%.*]] = alloca i32, align 4
28296 // CHECK30-NEXT:    [[_TMP54:%.*]] = alloca i32, align 4
28297 // CHECK30-NEXT:    [[DOTOMP_LB55:%.*]] = alloca i32, align 4
28298 // CHECK30-NEXT:    [[DOTOMP_UB56:%.*]] = alloca i32, align 4
28299 // CHECK30-NEXT:    [[DOTOMP_IV57:%.*]] = alloca i32, align 4
28300 // CHECK30-NEXT:    [[I58:%.*]] = alloca i32, align 4
28301 // CHECK30-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
28302 // CHECK30-NEXT:    store i32 0, i32* [[A]], align 4
28303 // CHECK30-NEXT:    store i16 0, i16* [[AA]], align 2
28304 // CHECK30-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
28305 // CHECK30-NEXT:    [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
28306 // CHECK30-NEXT:    [[TMP2:%.*]] = call i8* @llvm.stacksave()
28307 // CHECK30-NEXT:    store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8
28308 // CHECK30-NEXT:    [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4
28309 // CHECK30-NEXT:    store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8
28310 // CHECK30-NEXT:    [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
28311 // CHECK30-NEXT:    [[TMP4:%.*]] = zext i32 [[TMP3]] to i64
28312 // CHECK30-NEXT:    [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]]
28313 // CHECK30-NEXT:    [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8
28314 // CHECK30-NEXT:    store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8
28315 // CHECK30-NEXT:    [[TMP6:%.*]] = load i32, i32* [[A]], align 4
28316 // CHECK30-NEXT:    store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_]], align 4
28317 // CHECK30-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
28318 // CHECK30-NEXT:    store i32 [[TMP7]], i32* [[DOTCAPTURE_EXPR_2]], align 4
28319 // CHECK30-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
28320 // CHECK30-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
28321 // CHECK30-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
28322 // CHECK30-NEXT:    store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
28323 // CHECK30-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
28324 // CHECK30:       omp.inner.for.cond:
28325 // CHECK30-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
28326 // CHECK30-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !2
28327 // CHECK30-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
28328 // CHECK30-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
28329 // CHECK30:       omp.inner.for.body:
28330 // CHECK30-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
28331 // CHECK30-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
28332 // CHECK30-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
28333 // CHECK30-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !2
28334 // CHECK30-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
28335 // CHECK30:       omp.body.continue:
28336 // CHECK30-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
28337 // CHECK30:       omp.inner.for.inc:
28338 // CHECK30-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
28339 // CHECK30-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1
28340 // CHECK30-NEXT:    store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
28341 // CHECK30-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]
28342 // CHECK30:       omp.inner.for.end:
28343 // CHECK30-NEXT:    store i32 10, i32* [[I]], align 4
28344 // CHECK30-NEXT:    store i32 0, i32* [[DOTOMP_LB5]], align 4
28345 // CHECK30-NEXT:    store i32 9, i32* [[DOTOMP_UB6]], align 4
28346 // CHECK30-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB5]], align 4
28347 // CHECK30-NEXT:    store i32 [[TMP13]], i32* [[DOTOMP_IV7]], align 4
28348 // CHECK30-NEXT:    [[TMP14:%.*]] = load i32, i32* [[A]], align 4
28349 // CHECK30-NEXT:    store i32 [[TMP14]], i32* [[DOTLINEAR_START]], align 4
28350 // CHECK30-NEXT:    br label [[OMP_INNER_FOR_COND10:%.*]]
28351 // CHECK30:       omp.inner.for.cond10:
28352 // CHECK30-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV7]], align 4
28353 // CHECK30-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB6]], align 4
28354 // CHECK30-NEXT:    [[CMP11:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]]
28355 // CHECK30-NEXT:    br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY12:%.*]], label [[OMP_INNER_FOR_END19:%.*]]
28356 // CHECK30:       omp.inner.for.body12:
28357 // CHECK30-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV7]], align 4
28358 // CHECK30-NEXT:    [[MUL13:%.*]] = mul nsw i32 [[TMP17]], 1
28359 // CHECK30-NEXT:    [[ADD14:%.*]] = add nsw i32 0, [[MUL13]]
28360 // CHECK30-NEXT:    store i32 [[ADD14]], i32* [[A8]], align 4, !nontemporal !7
28361 // CHECK30-NEXT:    [[TMP18:%.*]] = load i32, i32* [[A8]], align 4, !nontemporal !7
28362 // CHECK30-NEXT:    [[ADD15:%.*]] = add nsw i32 [[TMP18]], 1
28363 // CHECK30-NEXT:    store i32 [[ADD15]], i32* [[A8]], align 4, !nontemporal !7
28364 // CHECK30-NEXT:    br label [[OMP_BODY_CONTINUE16:%.*]]
28365 // CHECK30:       omp.body.continue16:
28366 // CHECK30-NEXT:    br label [[OMP_INNER_FOR_INC17:%.*]]
28367 // CHECK30:       omp.inner.for.inc17:
28368 // CHECK30-NEXT:    [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV7]], align 4
28369 // CHECK30-NEXT:    [[ADD18:%.*]] = add nsw i32 [[TMP19]], 1
28370 // CHECK30-NEXT:    store i32 [[ADD18]], i32* [[DOTOMP_IV7]], align 4
28371 // CHECK30-NEXT:    br label [[OMP_INNER_FOR_COND10]], !llvm.loop [[LOOP8:![0-9]+]]
28372 // CHECK30:       omp.inner.for.end19:
28373 // CHECK30-NEXT:    store i32 10, i32* [[A]], align 4
28374 // CHECK30-NEXT:    store i32 0, i32* [[DOTOMP_LB21]], align 4
28375 // CHECK30-NEXT:    store i32 9, i32* [[DOTOMP_UB22]], align 4
28376 // CHECK30-NEXT:    [[TMP20:%.*]] = load i32, i32* [[DOTOMP_LB21]], align 4
28377 // CHECK30-NEXT:    store i32 [[TMP20]], i32* [[DOTOMP_IV23]], align 4
28378 // CHECK30-NEXT:    br label [[OMP_INNER_FOR_COND25:%.*]]
28379 // CHECK30:       omp.inner.for.cond25:
28380 // CHECK30-NEXT:    [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV23]], align 4, !llvm.access.group !10
28381 // CHECK30-NEXT:    [[TMP22:%.*]] = load i32, i32* [[DOTOMP_UB22]], align 4, !llvm.access.group !10
28382 // CHECK30-NEXT:    [[CMP26:%.*]] = icmp sle i32 [[TMP21]], [[TMP22]]
28383 // CHECK30-NEXT:    br i1 [[CMP26]], label [[OMP_INNER_FOR_BODY27:%.*]], label [[OMP_INNER_FOR_END35:%.*]]
28384 // CHECK30:       omp.inner.for.body27:
28385 // CHECK30-NEXT:    [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV23]], align 4, !llvm.access.group !10
28386 // CHECK30-NEXT:    [[MUL28:%.*]] = mul nsw i32 [[TMP23]], 1
28387 // CHECK30-NEXT:    [[ADD29:%.*]] = add nsw i32 0, [[MUL28]]
28388 // CHECK30-NEXT:    store i32 [[ADD29]], i32* [[I24]], align 4, !llvm.access.group !10
28389 // CHECK30-NEXT:    [[TMP24:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !10
28390 // CHECK30-NEXT:    [[CONV:%.*]] = sext i16 [[TMP24]] to i32
28391 // CHECK30-NEXT:    [[ADD30:%.*]] = add nsw i32 [[CONV]], 1
28392 // CHECK30-NEXT:    [[CONV31:%.*]] = trunc i32 [[ADD30]] to i16
28393 // CHECK30-NEXT:    store i16 [[CONV31]], i16* [[AA]], align 2, !llvm.access.group !10
28394 // CHECK30-NEXT:    br label [[OMP_BODY_CONTINUE32:%.*]]
28395 // CHECK30:       omp.body.continue32:
28396 // CHECK30-NEXT:    br label [[OMP_INNER_FOR_INC33:%.*]]
28397 // CHECK30:       omp.inner.for.inc33:
28398 // CHECK30-NEXT:    [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IV23]], align 4, !llvm.access.group !10
28399 // CHECK30-NEXT:    [[ADD34:%.*]] = add nsw i32 [[TMP25]], 1
28400 // CHECK30-NEXT:    store i32 [[ADD34]], i32* [[DOTOMP_IV23]], align 4, !llvm.access.group !10
28401 // CHECK30-NEXT:    br label [[OMP_INNER_FOR_COND25]], !llvm.loop [[LOOP11:![0-9]+]]
28402 // CHECK30:       omp.inner.for.end35:
28403 // CHECK30-NEXT:    store i32 10, i32* [[I24]], align 4
28404 // CHECK30-NEXT:    store i32 0, i32* [[DOTOMP_LB37]], align 4
28405 // CHECK30-NEXT:    store i32 9, i32* [[DOTOMP_UB38]], align 4
28406 // CHECK30-NEXT:    [[TMP26:%.*]] = load i32, i32* [[DOTOMP_LB37]], align 4
28407 // CHECK30-NEXT:    store i32 [[TMP26]], i32* [[DOTOMP_IV39]], align 4
28408 // CHECK30-NEXT:    br label [[OMP_INNER_FOR_COND41:%.*]]
28409 // CHECK30:       omp.inner.for.cond41:
28410 // CHECK30-NEXT:    [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV39]], align 4, !llvm.access.group !13
28411 // CHECK30-NEXT:    [[TMP28:%.*]] = load i32, i32* [[DOTOMP_UB38]], align 4, !llvm.access.group !13
28412 // CHECK30-NEXT:    [[CMP42:%.*]] = icmp sle i32 [[TMP27]], [[TMP28]]
28413 // CHECK30-NEXT:    br i1 [[CMP42]], label [[OMP_INNER_FOR_BODY43:%.*]], label [[OMP_INNER_FOR_END53:%.*]]
28414 // CHECK30:       omp.inner.for.body43:
28415 // CHECK30-NEXT:    [[TMP29:%.*]] = load i32, i32* [[DOTOMP_IV39]], align 4, !llvm.access.group !13
28416 // CHECK30-NEXT:    [[MUL44:%.*]] = mul nsw i32 [[TMP29]], 1
28417 // CHECK30-NEXT:    [[ADD45:%.*]] = add nsw i32 0, [[MUL44]]
28418 // CHECK30-NEXT:    store i32 [[ADD45]], i32* [[I40]], align 4, !llvm.access.group !13
28419 // CHECK30-NEXT:    [[TMP30:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !13
28420 // CHECK30-NEXT:    [[ADD46:%.*]] = add nsw i32 [[TMP30]], 1
28421 // CHECK30-NEXT:    store i32 [[ADD46]], i32* [[A]], align 4, !llvm.access.group !13
28422 // CHECK30-NEXT:    [[TMP31:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !13
28423 // CHECK30-NEXT:    [[CONV47:%.*]] = sext i16 [[TMP31]] to i32
28424 // CHECK30-NEXT:    [[ADD48:%.*]] = add nsw i32 [[CONV47]], 1
28425 // CHECK30-NEXT:    [[CONV49:%.*]] = trunc i32 [[ADD48]] to i16
28426 // CHECK30-NEXT:    store i16 [[CONV49]], i16* [[AA]], align 2, !llvm.access.group !13
28427 // CHECK30-NEXT:    br label [[OMP_BODY_CONTINUE50:%.*]]
28428 // CHECK30:       omp.body.continue50:
28429 // CHECK30-NEXT:    br label [[OMP_INNER_FOR_INC51:%.*]]
28430 // CHECK30:       omp.inner.for.inc51:
28431 // CHECK30-NEXT:    [[TMP32:%.*]] = load i32, i32* [[DOTOMP_IV39]], align 4, !llvm.access.group !13
28432 // CHECK30-NEXT:    [[ADD52:%.*]] = add nsw i32 [[TMP32]], 1
28433 // CHECK30-NEXT:    store i32 [[ADD52]], i32* [[DOTOMP_IV39]], align 4, !llvm.access.group !13
28434 // CHECK30-NEXT:    br label [[OMP_INNER_FOR_COND41]], !llvm.loop [[LOOP14:![0-9]+]]
28435 // CHECK30:       omp.inner.for.end53:
28436 // CHECK30-NEXT:    store i32 10, i32* [[I40]], align 4
28437 // CHECK30-NEXT:    store i32 0, i32* [[DOTOMP_LB55]], align 4
28438 // CHECK30-NEXT:    store i32 9, i32* [[DOTOMP_UB56]], align 4
28439 // CHECK30-NEXT:    [[TMP33:%.*]] = load i32, i32* [[DOTOMP_LB55]], align 4
28440 // CHECK30-NEXT:    store i32 [[TMP33]], i32* [[DOTOMP_IV57]], align 4
28441 // CHECK30-NEXT:    [[ARRAYDECAY:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 0
28442 // CHECK30-NEXT:    call void @llvm.assume(i1 true) [ "align"(float* [[ARRAYDECAY]], i64 16) ]
28443 // CHECK30-NEXT:    br label [[OMP_INNER_FOR_COND59:%.*]]
28444 // CHECK30:       omp.inner.for.cond59:
28445 // CHECK30-NEXT:    [[TMP34:%.*]] = load i32, i32* [[DOTOMP_IV57]], align 4, !llvm.access.group !16
28446 // CHECK30-NEXT:    [[TMP35:%.*]] = load i32, i32* [[DOTOMP_UB56]], align 4, !llvm.access.group !16
28447 // CHECK30-NEXT:    [[CMP60:%.*]] = icmp sle i32 [[TMP34]], [[TMP35]]
28448 // CHECK30-NEXT:    br i1 [[CMP60]], label [[OMP_INNER_FOR_BODY61:%.*]], label [[OMP_INNER_FOR_END85:%.*]]
28449 // CHECK30:       omp.inner.for.body61:
28450 // CHECK30-NEXT:    [[TMP36:%.*]] = load i32, i32* [[DOTOMP_IV57]], align 4, !llvm.access.group !16
28451 // CHECK30-NEXT:    [[MUL62:%.*]] = mul nsw i32 [[TMP36]], 1
28452 // CHECK30-NEXT:    [[ADD63:%.*]] = add nsw i32 0, [[MUL62]]
28453 // CHECK30-NEXT:    store i32 [[ADD63]], i32* [[I58]], align 4, !llvm.access.group !16
28454 // CHECK30-NEXT:    [[TMP37:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !16
28455 // CHECK30-NEXT:    [[ADD64:%.*]] = add nsw i32 [[TMP37]], 1
28456 // CHECK30-NEXT:    store i32 [[ADD64]], i32* [[A]], align 4, !llvm.access.group !16
28457 // CHECK30-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2
28458 // CHECK30-NEXT:    [[TMP38:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !16
28459 // CHECK30-NEXT:    [[CONV65:%.*]] = fpext float [[TMP38]] to double
28460 // CHECK30-NEXT:    [[ADD66:%.*]] = fadd double [[CONV65]], 1.000000e+00
28461 // CHECK30-NEXT:    [[CONV67:%.*]] = fptrunc double [[ADD66]] to float
28462 // CHECK30-NEXT:    store float [[CONV67]], float* [[ARRAYIDX]], align 4, !llvm.access.group !16
28463 // CHECK30-NEXT:    [[ARRAYIDX68:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3
28464 // CHECK30-NEXT:    [[TMP39:%.*]] = load float, float* [[ARRAYIDX68]], align 4, !llvm.access.group !16
28465 // CHECK30-NEXT:    [[CONV69:%.*]] = fpext float [[TMP39]] to double
28466 // CHECK30-NEXT:    [[ADD70:%.*]] = fadd double [[CONV69]], 1.000000e+00
28467 // CHECK30-NEXT:    [[CONV71:%.*]] = fptrunc double [[ADD70]] to float
28468 // CHECK30-NEXT:    store float [[CONV71]], float* [[ARRAYIDX68]], align 4, !llvm.access.group !16
28469 // CHECK30-NEXT:    [[ARRAYIDX72:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1
28470 // CHECK30-NEXT:    [[ARRAYIDX73:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX72]], i64 0, i64 2
28471 // CHECK30-NEXT:    [[TMP40:%.*]] = load double, double* [[ARRAYIDX73]], align 8, !llvm.access.group !16
28472 // CHECK30-NEXT:    [[ADD74:%.*]] = fadd double [[TMP40]], 1.000000e+00
28473 // CHECK30-NEXT:    store double [[ADD74]], double* [[ARRAYIDX73]], align 8, !llvm.access.group !16
28474 // CHECK30-NEXT:    [[TMP41:%.*]] = mul nsw i64 1, [[TMP4]]
28475 // CHECK30-NEXT:    [[ARRAYIDX75:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP41]]
28476 // CHECK30-NEXT:    [[ARRAYIDX76:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX75]], i64 3
28477 // CHECK30-NEXT:    [[TMP42:%.*]] = load double, double* [[ARRAYIDX76]], align 8, !llvm.access.group !16
28478 // CHECK30-NEXT:    [[ADD77:%.*]] = fadd double [[TMP42]], 1.000000e+00
28479 // CHECK30-NEXT:    store double [[ADD77]], double* [[ARRAYIDX76]], align 8, !llvm.access.group !16
28480 // CHECK30-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0
28481 // CHECK30-NEXT:    [[TMP43:%.*]] = load i64, i64* [[X]], align 8, !llvm.access.group !16
28482 // CHECK30-NEXT:    [[ADD78:%.*]] = add nsw i64 [[TMP43]], 1
28483 // CHECK30-NEXT:    store i64 [[ADD78]], i64* [[X]], align 8, !llvm.access.group !16
28484 // CHECK30-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1
28485 // CHECK30-NEXT:    [[TMP44:%.*]] = load i8, i8* [[Y]], align 8, !llvm.access.group !16
28486 // CHECK30-NEXT:    [[CONV79:%.*]] = sext i8 [[TMP44]] to i32
28487 // CHECK30-NEXT:    [[ADD80:%.*]] = add nsw i32 [[CONV79]], 1
28488 // CHECK30-NEXT:    [[CONV81:%.*]] = trunc i32 [[ADD80]] to i8
28489 // CHECK30-NEXT:    store i8 [[CONV81]], i8* [[Y]], align 8, !llvm.access.group !16
28490 // CHECK30-NEXT:    br label [[OMP_BODY_CONTINUE82:%.*]]
28491 // CHECK30:       omp.body.continue82:
28492 // CHECK30-NEXT:    br label [[OMP_INNER_FOR_INC83:%.*]]
28493 // CHECK30:       omp.inner.for.inc83:
28494 // CHECK30-NEXT:    [[TMP45:%.*]] = load i32, i32* [[DOTOMP_IV57]], align 4, !llvm.access.group !16
28495 // CHECK30-NEXT:    [[ADD84:%.*]] = add nsw i32 [[TMP45]], 1
28496 // CHECK30-NEXT:    store i32 [[ADD84]], i32* [[DOTOMP_IV57]], align 4, !llvm.access.group !16
28497 // CHECK30-NEXT:    br label [[OMP_INNER_FOR_COND59]], !llvm.loop [[LOOP17:![0-9]+]]
28498 // CHECK30:       omp.inner.for.end85:
28499 // CHECK30-NEXT:    store i32 10, i32* [[I58]], align 4
28500 // CHECK30-NEXT:    [[TMP46:%.*]] = load i32, i32* [[A]], align 4
28501 // CHECK30-NEXT:    [[TMP47:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
28502 // CHECK30-NEXT:    call void @llvm.stackrestore(i8* [[TMP47]])
28503 // CHECK30-NEXT:    ret i32 [[TMP46]]
28504 //
28505 //
28506 // CHECK30-LABEL: define {{[^@]+}}@_Z3bari
28507 // CHECK30-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {
28508 // CHECK30-NEXT:  entry:
28509 // CHECK30-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
28510 // CHECK30-NEXT:    [[A:%.*]] = alloca i32, align 4
28511 // CHECK30-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8
28512 // CHECK30-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
28513 // CHECK30-NEXT:    store i32 0, i32* [[A]], align 4
28514 // CHECK30-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
28515 // CHECK30-NEXT:    [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]])
28516 // CHECK30-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
28517 // CHECK30-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
28518 // CHECK30-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
28519 // CHECK30-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
28520 // CHECK30-NEXT:    [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP2]])
28521 // CHECK30-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
28522 // CHECK30-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
28523 // CHECK30-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
28524 // CHECK30-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
28525 // CHECK30-NEXT:    [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]])
28526 // CHECK30-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
28527 // CHECK30-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
28528 // CHECK30-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
28529 // CHECK30-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
28530 // CHECK30-NEXT:    [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]])
28531 // CHECK30-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
28532 // CHECK30-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
28533 // CHECK30-NEXT:    store i32 [[ADD6]], i32* [[A]], align 4
28534 // CHECK30-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
28535 // CHECK30-NEXT:    ret i32 [[TMP8]]
28536 //
28537 //
28538 // CHECK30-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
28539 // CHECK30-SAME: (%struct.S1* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 {
28540 // CHECK30-NEXT:  entry:
28541 // CHECK30-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
28542 // CHECK30-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
28543 // CHECK30-NEXT:    [[B:%.*]] = alloca i32, align 4
28544 // CHECK30-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 8
28545 // CHECK30-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
28546 // CHECK30-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
28547 // CHECK30-NEXT:    [[TMP:%.*]] = alloca i32, align 4
28548 // CHECK30-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
28549 // CHECK30-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
28550 // CHECK30-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
28551 // CHECK30-NEXT:    [[I:%.*]] = alloca i32, align 4
28552 // CHECK30-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
28553 // CHECK30-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
28554 // CHECK30-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
28555 // CHECK30-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
28556 // CHECK30-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
28557 // CHECK30-NEXT:    store i32 [[ADD]], i32* [[B]], align 4
28558 // CHECK30-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
28559 // CHECK30-NEXT:    [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
28560 // CHECK30-NEXT:    [[TMP3:%.*]] = call i8* @llvm.stacksave()
28561 // CHECK30-NEXT:    store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8
28562 // CHECK30-NEXT:    [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]
28563 // CHECK30-NEXT:    [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2
28564 // CHECK30-NEXT:    store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8
28565 // CHECK30-NEXT:    [[TMP5:%.*]] = load i32, i32* [[N_ADDR]], align 4
28566 // CHECK30-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 60
28567 // CHECK30-NEXT:    [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8
28568 // CHECK30-NEXT:    store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
28569 // CHECK30-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
28570 // CHECK30-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
28571 // CHECK30-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
28572 // CHECK30-NEXT:    store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
28573 // CHECK30-NEXT:    [[TMP7:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
28574 // CHECK30-NEXT:    [[TOBOOL:%.*]] = trunc i8 [[TMP7]] to i1
28575 // CHECK30-NEXT:    br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
28576 // CHECK30:       omp_if.then:
28577 // CHECK30-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
28578 // CHECK30:       omp.inner.for.cond:
28579 // CHECK30-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
28580 // CHECK30-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !19
28581 // CHECK30-NEXT:    [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
28582 // CHECK30-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
28583 // CHECK30:       omp.inner.for.body:
28584 // CHECK30-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
28585 // CHECK30-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
28586 // CHECK30-NEXT:    [[ADD3:%.*]] = add nsw i32 0, [[MUL]]
28587 // CHECK30-NEXT:    store i32 [[ADD3]], i32* [[I]], align 4, !llvm.access.group !19
28588 // CHECK30-NEXT:    [[TMP11:%.*]] = load i32, i32* [[B]], align 4, !llvm.access.group !19
28589 // CHECK30-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP11]] to double
28590 // CHECK30-NEXT:    [[ADD4:%.*]] = fadd double [[CONV]], 1.500000e+00
28591 // CHECK30-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
28592 // CHECK30-NEXT:    store double [[ADD4]], double* [[A]], align 8, !llvm.access.group !19
28593 // CHECK30-NEXT:    [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
28594 // CHECK30-NEXT:    [[TMP12:%.*]] = load double, double* [[A5]], align 8, !llvm.access.group !19
28595 // CHECK30-NEXT:    [[INC:%.*]] = fadd double [[TMP12]], 1.000000e+00
28596 // CHECK30-NEXT:    store double [[INC]], double* [[A5]], align 8, !llvm.access.group !19
28597 // CHECK30-NEXT:    [[CONV6:%.*]] = fptosi double [[INC]] to i16
28598 // CHECK30-NEXT:    [[TMP13:%.*]] = mul nsw i64 1, [[TMP2]]
28599 // CHECK30-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP13]]
28600 // CHECK30-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
28601 // CHECK30-NEXT:    store i16 [[CONV6]], i16* [[ARRAYIDX7]], align 2, !llvm.access.group !19
28602 // CHECK30-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
28603 // CHECK30:       omp.body.continue:
28604 // CHECK30-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
28605 // CHECK30:       omp.inner.for.inc:
28606 // CHECK30-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
28607 // CHECK30-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP14]], 1
28608 // CHECK30-NEXT:    store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
28609 // CHECK30-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]]
28610 // CHECK30:       omp.inner.for.end:
28611 // CHECK30-NEXT:    br label [[OMP_IF_END:%.*]]
28612 // CHECK30:       omp_if.else:
28613 // CHECK30-NEXT:    br label [[OMP_INNER_FOR_COND9:%.*]]
28614 // CHECK30:       omp.inner.for.cond9:
28615 // CHECK30-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
28616 // CHECK30-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
28617 // CHECK30-NEXT:    [[CMP10:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]]
28618 // CHECK30-NEXT:    br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY11:%.*]], label [[OMP_INNER_FOR_END25:%.*]]
28619 // CHECK30:       omp.inner.for.body11:
28620 // CHECK30-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
28621 // CHECK30-NEXT:    [[MUL12:%.*]] = mul nsw i32 [[TMP17]], 1
28622 // CHECK30-NEXT:    [[ADD13:%.*]] = add nsw i32 0, [[MUL12]]
28623 // CHECK30-NEXT:    store i32 [[ADD13]], i32* [[I]], align 4
28624 // CHECK30-NEXT:    [[TMP18:%.*]] = load i32, i32* [[B]], align 4
28625 // CHECK30-NEXT:    [[CONV14:%.*]] = sitofp i32 [[TMP18]] to double
28626 // CHECK30-NEXT:    [[ADD15:%.*]] = fadd double [[CONV14]], 1.500000e+00
28627 // CHECK30-NEXT:    [[A16:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
28628 // CHECK30-NEXT:    store double [[ADD15]], double* [[A16]], align 8
28629 // CHECK30-NEXT:    [[A17:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
28630 // CHECK30-NEXT:    [[TMP19:%.*]] = load double, double* [[A17]], align 8
28631 // CHECK30-NEXT:    [[INC18:%.*]] = fadd double [[TMP19]], 1.000000e+00
28632 // CHECK30-NEXT:    store double [[INC18]], double* [[A17]], align 8
28633 // CHECK30-NEXT:    [[CONV19:%.*]] = fptosi double [[INC18]] to i16
28634 // CHECK30-NEXT:    [[TMP20:%.*]] = mul nsw i64 1, [[TMP2]]
28635 // CHECK30-NEXT:    [[ARRAYIDX20:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP20]]
28636 // CHECK30-NEXT:    [[ARRAYIDX21:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX20]], i64 1
28637 // CHECK30-NEXT:    store i16 [[CONV19]], i16* [[ARRAYIDX21]], align 2
28638 // CHECK30-NEXT:    br label [[OMP_BODY_CONTINUE22:%.*]]
28639 // CHECK30:       omp.body.continue22:
28640 // CHECK30-NEXT:    br label [[OMP_INNER_FOR_INC23:%.*]]
28641 // CHECK30:       omp.inner.for.inc23:
28642 // CHECK30-NEXT:    [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
28643 // CHECK30-NEXT:    [[ADD24:%.*]] = add nsw i32 [[TMP21]], 1
28644 // CHECK30-NEXT:    store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4
28645 // CHECK30-NEXT:    br label [[OMP_INNER_FOR_COND9]], !llvm.loop [[LOOP22:![0-9]+]]
28646 // CHECK30:       omp.inner.for.end25:
28647 // CHECK30-NEXT:    br label [[OMP_IF_END]]
28648 // CHECK30:       omp_if.end:
28649 // CHECK30-NEXT:    store i32 10, i32* [[I]], align 4
28650 // CHECK30-NEXT:    [[TMP22:%.*]] = mul nsw i64 1, [[TMP2]]
28651 // CHECK30-NEXT:    [[ARRAYIDX26:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP22]]
28652 // CHECK30-NEXT:    [[ARRAYIDX27:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX26]], i64 1
28653 // CHECK30-NEXT:    [[TMP23:%.*]] = load i16, i16* [[ARRAYIDX27]], align 2
28654 // CHECK30-NEXT:    [[CONV28:%.*]] = sext i16 [[TMP23]] to i32
28655 // CHECK30-NEXT:    [[TMP24:%.*]] = load i32, i32* [[B]], align 4
28656 // CHECK30-NEXT:    [[ADD29:%.*]] = add nsw i32 [[CONV28]], [[TMP24]]
28657 // CHECK30-NEXT:    [[TMP25:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
28658 // CHECK30-NEXT:    call void @llvm.stackrestore(i8* [[TMP25]])
28659 // CHECK30-NEXT:    ret i32 [[ADD29]]
28660 //
28661 //
28662 // CHECK30-LABEL: define {{[^@]+}}@_ZL7fstatici
28663 // CHECK30-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {
28664 // CHECK30-NEXT:  entry:
28665 // CHECK30-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
28666 // CHECK30-NEXT:    [[A:%.*]] = alloca i32, align 4
28667 // CHECK30-NEXT:    [[AA:%.*]] = alloca i16, align 2
28668 // CHECK30-NEXT:    [[AAA:%.*]] = alloca i8, align 1
28669 // CHECK30-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
28670 // CHECK30-NEXT:    [[TMP:%.*]] = alloca i32, align 4
28671 // CHECK30-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
28672 // CHECK30-NEXT:    [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
28673 // CHECK30-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
28674 // CHECK30-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
28675 // CHECK30-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
28676 // CHECK30-NEXT:    [[I:%.*]] = alloca i32, align 4
28677 // CHECK30-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
28678 // CHECK30-NEXT:    [[I5:%.*]] = alloca i32, align 4
28679 // CHECK30-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
28680 // CHECK30-NEXT:    store i32 0, i32* [[A]], align 4
28681 // CHECK30-NEXT:    store i16 0, i16* [[AA]], align 2
28682 // CHECK30-NEXT:    store i8 0, i8* [[AAA]], align 1
28683 // CHECK30-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
28684 // CHECK30-NEXT:    store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4
28685 // CHECK30-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
28686 // CHECK30-NEXT:    store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_1]], align 4
28687 // CHECK30-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
28688 // CHECK30-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
28689 // CHECK30-NEXT:    [[SUB:%.*]] = sub i32 [[TMP2]], [[TMP3]]
28690 // CHECK30-NEXT:    [[SUB3:%.*]] = sub i32 [[SUB]], 1
28691 // CHECK30-NEXT:    [[ADD:%.*]] = add i32 [[SUB3]], 1
28692 // CHECK30-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], 1
28693 // CHECK30-NEXT:    [[SUB4:%.*]] = sub i32 [[DIV]], 1
28694 // CHECK30-NEXT:    store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_2]], align 4
28695 // CHECK30-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
28696 // CHECK30-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
28697 // CHECK30-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_UB]], align 4
28698 // CHECK30-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
28699 // CHECK30-NEXT:    store i32 [[TMP5]], i32* [[I]], align 4
28700 // CHECK30-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
28701 // CHECK30-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
28702 // CHECK30-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]]
28703 // CHECK30-NEXT:    br i1 [[CMP]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END:%.*]]
28704 // CHECK30:       simd.if.then:
28705 // CHECK30-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
28706 // CHECK30-NEXT:    store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
28707 // CHECK30-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
28708 // CHECK30:       omp.inner.for.cond:
28709 // CHECK30-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
28710 // CHECK30-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !24
28711 // CHECK30-NEXT:    [[ADD6:%.*]] = add i32 [[TMP10]], 1
28712 // CHECK30-NEXT:    [[CMP7:%.*]] = icmp ult i32 [[TMP9]], [[ADD6]]
28713 // CHECK30-NEXT:    br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
28714 // CHECK30:       omp.inner.for.body:
28715 // CHECK30-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group !24
28716 // CHECK30-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
28717 // CHECK30-NEXT:    [[MUL:%.*]] = mul i32 [[TMP12]], 1
28718 // CHECK30-NEXT:    [[ADD8:%.*]] = add i32 [[TMP11]], [[MUL]]
28719 // CHECK30-NEXT:    store i32 [[ADD8]], i32* [[I5]], align 4, !llvm.access.group !24
28720 // CHECK30-NEXT:    [[TMP13:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !24
28721 // CHECK30-NEXT:    [[ADD9:%.*]] = add nsw i32 [[TMP13]], 1
28722 // CHECK30-NEXT:    store i32 [[ADD9]], i32* [[A]], align 4, !llvm.access.group !24
28723 // CHECK30-NEXT:    [[TMP14:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !24
28724 // CHECK30-NEXT:    [[CONV:%.*]] = sext i16 [[TMP14]] to i32
28725 // CHECK30-NEXT:    [[ADD10:%.*]] = add nsw i32 [[CONV]], 1
28726 // CHECK30-NEXT:    [[CONV11:%.*]] = trunc i32 [[ADD10]] to i16
28727 // CHECK30-NEXT:    store i16 [[CONV11]], i16* [[AA]], align 2, !llvm.access.group !24
28728 // CHECK30-NEXT:    [[TMP15:%.*]] = load i8, i8* [[AAA]], align 1, !llvm.access.group !24
28729 // CHECK30-NEXT:    [[CONV12:%.*]] = sext i8 [[TMP15]] to i32
28730 // CHECK30-NEXT:    [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1
28731 // CHECK30-NEXT:    [[CONV14:%.*]] = trunc i32 [[ADD13]] to i8
28732 // CHECK30-NEXT:    store i8 [[CONV14]], i8* [[AAA]], align 1, !llvm.access.group !24
28733 // CHECK30-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2
28734 // CHECK30-NEXT:    [[TMP16:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !24
28735 // CHECK30-NEXT:    [[ADD15:%.*]] = add nsw i32 [[TMP16]], 1
28736 // CHECK30-NEXT:    store i32 [[ADD15]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !24
28737 // CHECK30-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
28738 // CHECK30:       omp.body.continue:
28739 // CHECK30-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
28740 // CHECK30:       omp.inner.for.inc:
28741 // CHECK30-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
28742 // CHECK30-NEXT:    [[ADD16:%.*]] = add i32 [[TMP17]], 1
28743 // CHECK30-NEXT:    store i32 [[ADD16]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
28744 // CHECK30-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]]
28745 // CHECK30:       omp.inner.for.end:
28746 // CHECK30-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
28747 // CHECK30-NEXT:    [[TMP19:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
28748 // CHECK30-NEXT:    [[TMP20:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
28749 // CHECK30-NEXT:    [[SUB17:%.*]] = sub i32 [[TMP19]], [[TMP20]]
28750 // CHECK30-NEXT:    [[SUB18:%.*]] = sub i32 [[SUB17]], 1
28751 // CHECK30-NEXT:    [[ADD19:%.*]] = add i32 [[SUB18]], 1
28752 // CHECK30-NEXT:    [[DIV20:%.*]] = udiv i32 [[ADD19]], 1
28753 // CHECK30-NEXT:    [[MUL21:%.*]] = mul i32 [[DIV20]], 1
28754 // CHECK30-NEXT:    [[ADD22:%.*]] = add i32 [[TMP18]], [[MUL21]]
28755 // CHECK30-NEXT:    store i32 [[ADD22]], i32* [[I5]], align 4
28756 // CHECK30-NEXT:    br label [[SIMD_IF_END]]
28757 // CHECK30:       simd.if.end:
28758 // CHECK30-NEXT:    [[TMP21:%.*]] = load i32, i32* [[A]], align 4
28759 // CHECK30-NEXT:    ret i32 [[TMP21]]
28760 //
28761 //
28762 // CHECK30-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
28763 // CHECK30-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat {
28764 // CHECK30-NEXT:  entry:
28765 // CHECK30-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
28766 // CHECK30-NEXT:    [[A:%.*]] = alloca i32, align 4
28767 // CHECK30-NEXT:    [[AA:%.*]] = alloca i16, align 2
28768 // CHECK30-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
28769 // CHECK30-NEXT:    [[TMP:%.*]] = alloca i32, align 4
28770 // CHECK30-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
28771 // CHECK30-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
28772 // CHECK30-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
28773 // CHECK30-NEXT:    [[I:%.*]] = alloca i32, align 4
28774 // CHECK30-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
28775 // CHECK30-NEXT:    store i32 0, i32* [[A]], align 4
28776 // CHECK30-NEXT:    store i16 0, i16* [[AA]], align 2
28777 // CHECK30-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
28778 // CHECK30-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
28779 // CHECK30-NEXT:    [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
28780 // CHECK30-NEXT:    store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4
28781 // CHECK30-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
28782 // CHECK30:       omp.inner.for.cond:
28783 // CHECK30-NEXT:    [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27
28784 // CHECK30-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !27
28785 // CHECK30-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
28786 // CHECK30-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
28787 // CHECK30:       omp.inner.for.body:
28788 // CHECK30-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27
28789 // CHECK30-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1
28790 // CHECK30-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
28791 // CHECK30-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !27
28792 // CHECK30-NEXT:    [[TMP4:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !27
28793 // CHECK30-NEXT:    [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1
28794 // CHECK30-NEXT:    store i32 [[ADD1]], i32* [[A]], align 4, !llvm.access.group !27
28795 // CHECK30-NEXT:    [[TMP5:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !27
28796 // CHECK30-NEXT:    [[CONV:%.*]] = sext i16 [[TMP5]] to i32
28797 // CHECK30-NEXT:    [[ADD2:%.*]] = add nsw i32 [[CONV]], 1
28798 // CHECK30-NEXT:    [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
28799 // CHECK30-NEXT:    store i16 [[CONV3]], i16* [[AA]], align 2, !llvm.access.group !27
28800 // CHECK30-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2
28801 // CHECK30-NEXT:    [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !27
28802 // CHECK30-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP6]], 1
28803 // CHECK30-NEXT:    store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !27
28804 // CHECK30-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
28805 // CHECK30:       omp.body.continue:
28806 // CHECK30-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
28807 // CHECK30:       omp.inner.for.inc:
28808 // CHECK30-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27
28809 // CHECK30-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP7]], 1
28810 // CHECK30-NEXT:    store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27
28811 // CHECK30-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]]
28812 // CHECK30:       omp.inner.for.end:
28813 // CHECK30-NEXT:    store i32 10, i32* [[I]], align 4
28814 // CHECK30-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
28815 // CHECK30-NEXT:    ret i32 [[TMP8]]
28816 //
28817 //
28818 // CHECK31-LABEL: define {{[^@]+}}@_Z3fooi
28819 // CHECK31-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0:[0-9]+]] {
28820 // CHECK31-NEXT:  entry:
28821 // CHECK31-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
28822 // CHECK31-NEXT:    [[A:%.*]] = alloca i32, align 4
28823 // CHECK31-NEXT:    [[AA:%.*]] = alloca i16, align 2
28824 // CHECK31-NEXT:    [[B:%.*]] = alloca [10 x float], align 4
28825 // CHECK31-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 4
28826 // CHECK31-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 4
28827 // CHECK31-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 8
28828 // CHECK31-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i32, align 4
28829 // CHECK31-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4
28830 // CHECK31-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
28831 // CHECK31-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
28832 // CHECK31-NEXT:    [[TMP:%.*]] = alloca i32, align 4
28833 // CHECK31-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
28834 // CHECK31-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
28835 // CHECK31-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
28836 // CHECK31-NEXT:    [[I:%.*]] = alloca i32, align 4
28837 // CHECK31-NEXT:    [[_TMP4:%.*]] = alloca i32, align 4
28838 // CHECK31-NEXT:    [[DOTOMP_LB5:%.*]] = alloca i32, align 4
28839 // CHECK31-NEXT:    [[DOTOMP_UB6:%.*]] = alloca i32, align 4
28840 // CHECK31-NEXT:    [[DOTOMP_IV7:%.*]] = alloca i32, align 4
28841 // CHECK31-NEXT:    [[DOTLINEAR_START:%.*]] = alloca i32, align 4
28842 // CHECK31-NEXT:    [[A8:%.*]] = alloca i32, align 4
28843 // CHECK31-NEXT:    [[A9:%.*]] = alloca i32, align 4
28844 // CHECK31-NEXT:    [[_TMP20:%.*]] = alloca i32, align 4
28845 // CHECK31-NEXT:    [[DOTOMP_LB21:%.*]] = alloca i32, align 4
28846 // CHECK31-NEXT:    [[DOTOMP_UB22:%.*]] = alloca i32, align 4
28847 // CHECK31-NEXT:    [[DOTOMP_IV23:%.*]] = alloca i32, align 4
28848 // CHECK31-NEXT:    [[I24:%.*]] = alloca i32, align 4
28849 // CHECK31-NEXT:    [[_TMP36:%.*]] = alloca i32, align 4
28850 // CHECK31-NEXT:    [[DOTOMP_LB37:%.*]] = alloca i32, align 4
28851 // CHECK31-NEXT:    [[DOTOMP_UB38:%.*]] = alloca i32, align 4
28852 // CHECK31-NEXT:    [[DOTOMP_IV39:%.*]] = alloca i32, align 4
28853 // CHECK31-NEXT:    [[I40:%.*]] = alloca i32, align 4
28854 // CHECK31-NEXT:    [[_TMP54:%.*]] = alloca i32, align 4
28855 // CHECK31-NEXT:    [[DOTOMP_LB55:%.*]] = alloca i32, align 4
28856 // CHECK31-NEXT:    [[DOTOMP_UB56:%.*]] = alloca i32, align 4
28857 // CHECK31-NEXT:    [[DOTOMP_IV57:%.*]] = alloca i32, align 4
28858 // CHECK31-NEXT:    [[I58:%.*]] = alloca i32, align 4
28859 // CHECK31-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
28860 // CHECK31-NEXT:    store i32 0, i32* [[A]], align 4
28861 // CHECK31-NEXT:    store i16 0, i16* [[AA]], align 2
28862 // CHECK31-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
28863 // CHECK31-NEXT:    [[TMP1:%.*]] = call i8* @llvm.stacksave()
28864 // CHECK31-NEXT:    store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4
28865 // CHECK31-NEXT:    [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4
28866 // CHECK31-NEXT:    store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4
28867 // CHECK31-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
28868 // CHECK31-NEXT:    [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]]
28869 // CHECK31-NEXT:    [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8
28870 // CHECK31-NEXT:    store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4
28871 // CHECK31-NEXT:    [[TMP4:%.*]] = load i32, i32* [[A]], align 4
28872 // CHECK31-NEXT:    store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4
28873 // CHECK31-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
28874 // CHECK31-NEXT:    store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_2]], align 4
28875 // CHECK31-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
28876 // CHECK31-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
28877 // CHECK31-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
28878 // CHECK31-NEXT:    store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
28879 // CHECK31-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
28880 // CHECK31:       omp.inner.for.cond:
28881 // CHECK31-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
28882 // CHECK31-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !3
28883 // CHECK31-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
28884 // CHECK31-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
28885 // CHECK31:       omp.inner.for.body:
28886 // CHECK31-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
28887 // CHECK31-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
28888 // CHECK31-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
28889 // CHECK31-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !3
28890 // CHECK31-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
28891 // CHECK31:       omp.body.continue:
28892 // CHECK31-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
28893 // CHECK31:       omp.inner.for.inc:
28894 // CHECK31-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
28895 // CHECK31-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
28896 // CHECK31-NEXT:    store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
28897 // CHECK31-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]
28898 // CHECK31:       omp.inner.for.end:
28899 // CHECK31-NEXT:    store i32 10, i32* [[I]], align 4
28900 // CHECK31-NEXT:    store i32 0, i32* [[DOTOMP_LB5]], align 4
28901 // CHECK31-NEXT:    store i32 9, i32* [[DOTOMP_UB6]], align 4
28902 // CHECK31-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_LB5]], align 4
28903 // CHECK31-NEXT:    store i32 [[TMP11]], i32* [[DOTOMP_IV7]], align 4
28904 // CHECK31-NEXT:    [[TMP12:%.*]] = load i32, i32* [[A]], align 4
28905 // CHECK31-NEXT:    store i32 [[TMP12]], i32* [[DOTLINEAR_START]], align 4
28906 // CHECK31-NEXT:    br label [[OMP_INNER_FOR_COND10:%.*]]
28907 // CHECK31:       omp.inner.for.cond10:
28908 // CHECK31-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV7]], align 4
28909 // CHECK31-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB6]], align 4
28910 // CHECK31-NEXT:    [[CMP11:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
28911 // CHECK31-NEXT:    br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY12:%.*]], label [[OMP_INNER_FOR_END19:%.*]]
28912 // CHECK31:       omp.inner.for.body12:
28913 // CHECK31-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV7]], align 4
28914 // CHECK31-NEXT:    [[MUL13:%.*]] = mul nsw i32 [[TMP15]], 1
28915 // CHECK31-NEXT:    [[ADD14:%.*]] = add nsw i32 0, [[MUL13]]
28916 // CHECK31-NEXT:    store i32 [[ADD14]], i32* [[A8]], align 4, !nontemporal !8
28917 // CHECK31-NEXT:    [[TMP16:%.*]] = load i32, i32* [[A8]], align 4, !nontemporal !8
28918 // CHECK31-NEXT:    [[ADD15:%.*]] = add nsw i32 [[TMP16]], 1
28919 // CHECK31-NEXT:    store i32 [[ADD15]], i32* [[A8]], align 4, !nontemporal !8
28920 // CHECK31-NEXT:    br label [[OMP_BODY_CONTINUE16:%.*]]
28921 // CHECK31:       omp.body.continue16:
28922 // CHECK31-NEXT:    br label [[OMP_INNER_FOR_INC17:%.*]]
28923 // CHECK31:       omp.inner.for.inc17:
28924 // CHECK31-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV7]], align 4
28925 // CHECK31-NEXT:    [[ADD18:%.*]] = add nsw i32 [[TMP17]], 1
28926 // CHECK31-NEXT:    store i32 [[ADD18]], i32* [[DOTOMP_IV7]], align 4
28927 // CHECK31-NEXT:    br label [[OMP_INNER_FOR_COND10]], !llvm.loop [[LOOP9:![0-9]+]]
28928 // CHECK31:       omp.inner.for.end19:
28929 // CHECK31-NEXT:    store i32 10, i32* [[A]], align 4
28930 // CHECK31-NEXT:    store i32 0, i32* [[DOTOMP_LB21]], align 4
28931 // CHECK31-NEXT:    store i32 9, i32* [[DOTOMP_UB22]], align 4
28932 // CHECK31-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTOMP_LB21]], align 4
28933 // CHECK31-NEXT:    store i32 [[TMP18]], i32* [[DOTOMP_IV23]], align 4
28934 // CHECK31-NEXT:    br label [[OMP_INNER_FOR_COND25:%.*]]
28935 // CHECK31:       omp.inner.for.cond25:
28936 // CHECK31-NEXT:    [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV23]], align 4, !llvm.access.group !11
28937 // CHECK31-NEXT:    [[TMP20:%.*]] = load i32, i32* [[DOTOMP_UB22]], align 4, !llvm.access.group !11
28938 // CHECK31-NEXT:    [[CMP26:%.*]] = icmp sle i32 [[TMP19]], [[TMP20]]
28939 // CHECK31-NEXT:    br i1 [[CMP26]], label [[OMP_INNER_FOR_BODY27:%.*]], label [[OMP_INNER_FOR_END35:%.*]]
28940 // CHECK31:       omp.inner.for.body27:
28941 // CHECK31-NEXT:    [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV23]], align 4, !llvm.access.group !11
28942 // CHECK31-NEXT:    [[MUL28:%.*]] = mul nsw i32 [[TMP21]], 1
28943 // CHECK31-NEXT:    [[ADD29:%.*]] = add nsw i32 0, [[MUL28]]
28944 // CHECK31-NEXT:    store i32 [[ADD29]], i32* [[I24]], align 4, !llvm.access.group !11
28945 // CHECK31-NEXT:    [[TMP22:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !11
28946 // CHECK31-NEXT:    [[CONV:%.*]] = sext i16 [[TMP22]] to i32
28947 // CHECK31-NEXT:    [[ADD30:%.*]] = add nsw i32 [[CONV]], 1
28948 // CHECK31-NEXT:    [[CONV31:%.*]] = trunc i32 [[ADD30]] to i16
28949 // CHECK31-NEXT:    store i16 [[CONV31]], i16* [[AA]], align 2, !llvm.access.group !11
28950 // CHECK31-NEXT:    br label [[OMP_BODY_CONTINUE32:%.*]]
28951 // CHECK31:       omp.body.continue32:
28952 // CHECK31-NEXT:    br label [[OMP_INNER_FOR_INC33:%.*]]
28953 // CHECK31:       omp.inner.for.inc33:
28954 // CHECK31-NEXT:    [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV23]], align 4, !llvm.access.group !11
28955 // CHECK31-NEXT:    [[ADD34:%.*]] = add nsw i32 [[TMP23]], 1
28956 // CHECK31-NEXT:    store i32 [[ADD34]], i32* [[DOTOMP_IV23]], align 4, !llvm.access.group !11
28957 // CHECK31-NEXT:    br label [[OMP_INNER_FOR_COND25]], !llvm.loop [[LOOP12:![0-9]+]]
28958 // CHECK31:       omp.inner.for.end35:
28959 // CHECK31-NEXT:    store i32 10, i32* [[I24]], align 4
28960 // CHECK31-NEXT:    store i32 0, i32* [[DOTOMP_LB37]], align 4
28961 // CHECK31-NEXT:    store i32 9, i32* [[DOTOMP_UB38]], align 4
28962 // CHECK31-NEXT:    [[TMP24:%.*]] = load i32, i32* [[DOTOMP_LB37]], align 4
28963 // CHECK31-NEXT:    store i32 [[TMP24]], i32* [[DOTOMP_IV39]], align 4
28964 // CHECK31-NEXT:    br label [[OMP_INNER_FOR_COND41:%.*]]
28965 // CHECK31:       omp.inner.for.cond41:
28966 // CHECK31-NEXT:    [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IV39]], align 4, !llvm.access.group !14
28967 // CHECK31-NEXT:    [[TMP26:%.*]] = load i32, i32* [[DOTOMP_UB38]], align 4, !llvm.access.group !14
28968 // CHECK31-NEXT:    [[CMP42:%.*]] = icmp sle i32 [[TMP25]], [[TMP26]]
28969 // CHECK31-NEXT:    br i1 [[CMP42]], label [[OMP_INNER_FOR_BODY43:%.*]], label [[OMP_INNER_FOR_END53:%.*]]
28970 // CHECK31:       omp.inner.for.body43:
28971 // CHECK31-NEXT:    [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV39]], align 4, !llvm.access.group !14
28972 // CHECK31-NEXT:    [[MUL44:%.*]] = mul nsw i32 [[TMP27]], 1
28973 // CHECK31-NEXT:    [[ADD45:%.*]] = add nsw i32 0, [[MUL44]]
28974 // CHECK31-NEXT:    store i32 [[ADD45]], i32* [[I40]], align 4, !llvm.access.group !14
28975 // CHECK31-NEXT:    [[TMP28:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !14
28976 // CHECK31-NEXT:    [[ADD46:%.*]] = add nsw i32 [[TMP28]], 1
28977 // CHECK31-NEXT:    store i32 [[ADD46]], i32* [[A]], align 4, !llvm.access.group !14
28978 // CHECK31-NEXT:    [[TMP29:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !14
28979 // CHECK31-NEXT:    [[CONV47:%.*]] = sext i16 [[TMP29]] to i32
28980 // CHECK31-NEXT:    [[ADD48:%.*]] = add nsw i32 [[CONV47]], 1
28981 // CHECK31-NEXT:    [[CONV49:%.*]] = trunc i32 [[ADD48]] to i16
28982 // CHECK31-NEXT:    store i16 [[CONV49]], i16* [[AA]], align 2, !llvm.access.group !14
28983 // CHECK31-NEXT:    br label [[OMP_BODY_CONTINUE50:%.*]]
28984 // CHECK31:       omp.body.continue50:
28985 // CHECK31-NEXT:    br label [[OMP_INNER_FOR_INC51:%.*]]
28986 // CHECK31:       omp.inner.for.inc51:
28987 // CHECK31-NEXT:    [[TMP30:%.*]] = load i32, i32* [[DOTOMP_IV39]], align 4, !llvm.access.group !14
28988 // CHECK31-NEXT:    [[ADD52:%.*]] = add nsw i32 [[TMP30]], 1
28989 // CHECK31-NEXT:    store i32 [[ADD52]], i32* [[DOTOMP_IV39]], align 4, !llvm.access.group !14
28990 // CHECK31-NEXT:    br label [[OMP_INNER_FOR_COND41]], !llvm.loop [[LOOP15:![0-9]+]]
28991 // CHECK31:       omp.inner.for.end53:
28992 // CHECK31-NEXT:    store i32 10, i32* [[I40]], align 4
28993 // CHECK31-NEXT:    store i32 0, i32* [[DOTOMP_LB55]], align 4
28994 // CHECK31-NEXT:    store i32 9, i32* [[DOTOMP_UB56]], align 4
28995 // CHECK31-NEXT:    [[TMP31:%.*]] = load i32, i32* [[DOTOMP_LB55]], align 4
28996 // CHECK31-NEXT:    store i32 [[TMP31]], i32* [[DOTOMP_IV57]], align 4
28997 // CHECK31-NEXT:    [[ARRAYDECAY:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 0
28998 // CHECK31-NEXT:    call void @llvm.assume(i1 true) [ "align"(float* [[ARRAYDECAY]], i32 16) ]
28999 // CHECK31-NEXT:    br label [[OMP_INNER_FOR_COND59:%.*]]
29000 // CHECK31:       omp.inner.for.cond59:
29001 // CHECK31-NEXT:    [[TMP32:%.*]] = load i32, i32* [[DOTOMP_IV57]], align 4, !llvm.access.group !17
29002 // CHECK31-NEXT:    [[TMP33:%.*]] = load i32, i32* [[DOTOMP_UB56]], align 4, !llvm.access.group !17
29003 // CHECK31-NEXT:    [[CMP60:%.*]] = icmp sle i32 [[TMP32]], [[TMP33]]
29004 // CHECK31-NEXT:    br i1 [[CMP60]], label [[OMP_INNER_FOR_BODY61:%.*]], label [[OMP_INNER_FOR_END85:%.*]]
29005 // CHECK31:       omp.inner.for.body61:
29006 // CHECK31-NEXT:    [[TMP34:%.*]] = load i32, i32* [[DOTOMP_IV57]], align 4, !llvm.access.group !17
29007 // CHECK31-NEXT:    [[MUL62:%.*]] = mul nsw i32 [[TMP34]], 1
29008 // CHECK31-NEXT:    [[ADD63:%.*]] = add nsw i32 0, [[MUL62]]
29009 // CHECK31-NEXT:    store i32 [[ADD63]], i32* [[I58]], align 4, !llvm.access.group !17
29010 // CHECK31-NEXT:    [[TMP35:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !17
29011 // CHECK31-NEXT:    [[ADD64:%.*]] = add nsw i32 [[TMP35]], 1
29012 // CHECK31-NEXT:    store i32 [[ADD64]], i32* [[A]], align 4, !llvm.access.group !17
29013 // CHECK31-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2
29014 // CHECK31-NEXT:    [[TMP36:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !17
29015 // CHECK31-NEXT:    [[CONV65:%.*]] = fpext float [[TMP36]] to double
29016 // CHECK31-NEXT:    [[ADD66:%.*]] = fadd double [[CONV65]], 1.000000e+00
29017 // CHECK31-NEXT:    [[CONV67:%.*]] = fptrunc double [[ADD66]] to float
29018 // CHECK31-NEXT:    store float [[CONV67]], float* [[ARRAYIDX]], align 4, !llvm.access.group !17
29019 // CHECK31-NEXT:    [[ARRAYIDX68:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3
29020 // CHECK31-NEXT:    [[TMP37:%.*]] = load float, float* [[ARRAYIDX68]], align 4, !llvm.access.group !17
29021 // CHECK31-NEXT:    [[CONV69:%.*]] = fpext float [[TMP37]] to double
29022 // CHECK31-NEXT:    [[ADD70:%.*]] = fadd double [[CONV69]], 1.000000e+00
29023 // CHECK31-NEXT:    [[CONV71:%.*]] = fptrunc double [[ADD70]] to float
29024 // CHECK31-NEXT:    store float [[CONV71]], float* [[ARRAYIDX68]], align 4, !llvm.access.group !17
29025 // CHECK31-NEXT:    [[ARRAYIDX72:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1
29026 // CHECK31-NEXT:    [[ARRAYIDX73:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX72]], i32 0, i32 2
29027 // CHECK31-NEXT:    [[TMP38:%.*]] = load double, double* [[ARRAYIDX73]], align 8, !llvm.access.group !17
29028 // CHECK31-NEXT:    [[ADD74:%.*]] = fadd double [[TMP38]], 1.000000e+00
29029 // CHECK31-NEXT:    store double [[ADD74]], double* [[ARRAYIDX73]], align 8, !llvm.access.group !17
29030 // CHECK31-NEXT:    [[TMP39:%.*]] = mul nsw i32 1, [[TMP2]]
29031 // CHECK31-NEXT:    [[ARRAYIDX75:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP39]]
29032 // CHECK31-NEXT:    [[ARRAYIDX76:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX75]], i32 3
29033 // CHECK31-NEXT:    [[TMP40:%.*]] = load double, double* [[ARRAYIDX76]], align 8, !llvm.access.group !17
29034 // CHECK31-NEXT:    [[ADD77:%.*]] = fadd double [[TMP40]], 1.000000e+00
29035 // CHECK31-NEXT:    store double [[ADD77]], double* [[ARRAYIDX76]], align 8, !llvm.access.group !17
29036 // CHECK31-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0
29037 // CHECK31-NEXT:    [[TMP41:%.*]] = load i64, i64* [[X]], align 4, !llvm.access.group !17
29038 // CHECK31-NEXT:    [[ADD78:%.*]] = add nsw i64 [[TMP41]], 1
29039 // CHECK31-NEXT:    store i64 [[ADD78]], i64* [[X]], align 4, !llvm.access.group !17
29040 // CHECK31-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1
29041 // CHECK31-NEXT:    [[TMP42:%.*]] = load i8, i8* [[Y]], align 4, !llvm.access.group !17
29042 // CHECK31-NEXT:    [[CONV79:%.*]] = sext i8 [[TMP42]] to i32
29043 // CHECK31-NEXT:    [[ADD80:%.*]] = add nsw i32 [[CONV79]], 1
29044 // CHECK31-NEXT:    [[CONV81:%.*]] = trunc i32 [[ADD80]] to i8
29045 // CHECK31-NEXT:    store i8 [[CONV81]], i8* [[Y]], align 4, !llvm.access.group !17
29046 // CHECK31-NEXT:    br label [[OMP_BODY_CONTINUE82:%.*]]
29047 // CHECK31:       omp.body.continue82:
29048 // CHECK31-NEXT:    br label [[OMP_INNER_FOR_INC83:%.*]]
29049 // CHECK31:       omp.inner.for.inc83:
29050 // CHECK31-NEXT:    [[TMP43:%.*]] = load i32, i32* [[DOTOMP_IV57]], align 4, !llvm.access.group !17
29051 // CHECK31-NEXT:    [[ADD84:%.*]] = add nsw i32 [[TMP43]], 1
29052 // CHECK31-NEXT:    store i32 [[ADD84]], i32* [[DOTOMP_IV57]], align 4, !llvm.access.group !17
29053 // CHECK31-NEXT:    br label [[OMP_INNER_FOR_COND59]], !llvm.loop [[LOOP18:![0-9]+]]
29054 // CHECK31:       omp.inner.for.end85:
29055 // CHECK31-NEXT:    store i32 10, i32* [[I58]], align 4
29056 // CHECK31-NEXT:    [[TMP44:%.*]] = load i32, i32* [[A]], align 4
29057 // CHECK31-NEXT:    [[TMP45:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
29058 // CHECK31-NEXT:    call void @llvm.stackrestore(i8* [[TMP45]])
29059 // CHECK31-NEXT:    ret i32 [[TMP44]]
29060 //
29061 //
29062 // CHECK31-LABEL: define {{[^@]+}}@_Z3bari
29063 // CHECK31-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {
29064 // CHECK31-NEXT:  entry:
29065 // CHECK31-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
29066 // CHECK31-NEXT:    [[A:%.*]] = alloca i32, align 4
29067 // CHECK31-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4
29068 // CHECK31-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
29069 // CHECK31-NEXT:    store i32 0, i32* [[A]], align 4
29070 // CHECK31-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
29071 // CHECK31-NEXT:    [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]])
29072 // CHECK31-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
29073 // CHECK31-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
29074 // CHECK31-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
29075 // CHECK31-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
29076 // CHECK31-NEXT:    [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP2]])
29077 // CHECK31-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
29078 // CHECK31-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
29079 // CHECK31-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
29080 // CHECK31-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
29081 // CHECK31-NEXT:    [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]])
29082 // CHECK31-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
29083 // CHECK31-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
29084 // CHECK31-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
29085 // CHECK31-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
29086 // CHECK31-NEXT:    [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]])
29087 // CHECK31-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
29088 // CHECK31-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
29089 // CHECK31-NEXT:    store i32 [[ADD6]], i32* [[A]], align 4
29090 // CHECK31-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
29091 // CHECK31-NEXT:    ret i32 [[TMP8]]
29092 //
29093 //
29094 // CHECK31-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
29095 // CHECK31-SAME: (%struct.S1* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 {
29096 // CHECK31-NEXT:  entry:
29097 // CHECK31-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
29098 // CHECK31-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
29099 // CHECK31-NEXT:    [[B:%.*]] = alloca i32, align 4
29100 // CHECK31-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 4
29101 // CHECK31-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 4
29102 // CHECK31-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
29103 // CHECK31-NEXT:    [[TMP:%.*]] = alloca i32, align 4
29104 // CHECK31-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
29105 // CHECK31-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
29106 // CHECK31-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
29107 // CHECK31-NEXT:    [[I:%.*]] = alloca i32, align 4
29108 // CHECK31-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
29109 // CHECK31-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
29110 // CHECK31-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
29111 // CHECK31-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
29112 // CHECK31-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
29113 // CHECK31-NEXT:    store i32 [[ADD]], i32* [[B]], align 4
29114 // CHECK31-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
29115 // CHECK31-NEXT:    [[TMP2:%.*]] = call i8* @llvm.stacksave()
29116 // CHECK31-NEXT:    store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4
29117 // CHECK31-NEXT:    [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]
29118 // CHECK31-NEXT:    [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2
29119 // CHECK31-NEXT:    store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
29120 // CHECK31-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
29121 // CHECK31-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 60
29122 // CHECK31-NEXT:    [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8
29123 // CHECK31-NEXT:    store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
29124 // CHECK31-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
29125 // CHECK31-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
29126 // CHECK31-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
29127 // CHECK31-NEXT:    store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
29128 // CHECK31-NEXT:    [[TMP6:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
29129 // CHECK31-NEXT:    [[TOBOOL:%.*]] = trunc i8 [[TMP6]] to i1
29130 // CHECK31-NEXT:    br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
29131 // CHECK31:       omp_if.then:
29132 // CHECK31-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
29133 // CHECK31:       omp.inner.for.cond:
29134 // CHECK31-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20
29135 // CHECK31-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !20
29136 // CHECK31-NEXT:    [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
29137 // CHECK31-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
29138 // CHECK31:       omp.inner.for.body:
29139 // CHECK31-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20
29140 // CHECK31-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
29141 // CHECK31-NEXT:    [[ADD3:%.*]] = add nsw i32 0, [[MUL]]
29142 // CHECK31-NEXT:    store i32 [[ADD3]], i32* [[I]], align 4, !llvm.access.group !20
29143 // CHECK31-NEXT:    [[TMP10:%.*]] = load i32, i32* [[B]], align 4, !llvm.access.group !20
29144 // CHECK31-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP10]] to double
29145 // CHECK31-NEXT:    [[ADD4:%.*]] = fadd double [[CONV]], 1.500000e+00
29146 // CHECK31-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
29147 // CHECK31-NEXT:    store double [[ADD4]], double* [[A]], align 4, !llvm.access.group !20
29148 // CHECK31-NEXT:    [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
29149 // CHECK31-NEXT:    [[TMP11:%.*]] = load double, double* [[A5]], align 4, !llvm.access.group !20
29150 // CHECK31-NEXT:    [[INC:%.*]] = fadd double [[TMP11]], 1.000000e+00
29151 // CHECK31-NEXT:    store double [[INC]], double* [[A5]], align 4, !llvm.access.group !20
29152 // CHECK31-NEXT:    [[CONV6:%.*]] = fptosi double [[INC]] to i16
29153 // CHECK31-NEXT:    [[TMP12:%.*]] = mul nsw i32 1, [[TMP1]]
29154 // CHECK31-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP12]]
29155 // CHECK31-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
29156 // CHECK31-NEXT:    store i16 [[CONV6]], i16* [[ARRAYIDX7]], align 2, !llvm.access.group !20
29157 // CHECK31-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
29158 // CHECK31:       omp.body.continue:
29159 // CHECK31-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
29160 // CHECK31:       omp.inner.for.inc:
29161 // CHECK31-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20
29162 // CHECK31-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP13]], 1
29163 // CHECK31-NEXT:    store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20
29164 // CHECK31-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]]
29165 // CHECK31:       omp.inner.for.end:
29166 // CHECK31-NEXT:    br label [[OMP_IF_END:%.*]]
29167 // CHECK31:       omp_if.else:
29168 // CHECK31-NEXT:    br label [[OMP_INNER_FOR_COND9:%.*]]
29169 // CHECK31:       omp.inner.for.cond9:
29170 // CHECK31-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
29171 // CHECK31-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
29172 // CHECK31-NEXT:    [[CMP10:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
29173 // CHECK31-NEXT:    br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY11:%.*]], label [[OMP_INNER_FOR_END25:%.*]]
29174 // CHECK31:       omp.inner.for.body11:
29175 // CHECK31-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
29176 // CHECK31-NEXT:    [[MUL12:%.*]] = mul nsw i32 [[TMP16]], 1
29177 // CHECK31-NEXT:    [[ADD13:%.*]] = add nsw i32 0, [[MUL12]]
29178 // CHECK31-NEXT:    store i32 [[ADD13]], i32* [[I]], align 4
29179 // CHECK31-NEXT:    [[TMP17:%.*]] = load i32, i32* [[B]], align 4
29180 // CHECK31-NEXT:    [[CONV14:%.*]] = sitofp i32 [[TMP17]] to double
29181 // CHECK31-NEXT:    [[ADD15:%.*]] = fadd double [[CONV14]], 1.500000e+00
29182 // CHECK31-NEXT:    [[A16:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
29183 // CHECK31-NEXT:    store double [[ADD15]], double* [[A16]], align 4
29184 // CHECK31-NEXT:    [[A17:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
29185 // CHECK31-NEXT:    [[TMP18:%.*]] = load double, double* [[A17]], align 4
29186 // CHECK31-NEXT:    [[INC18:%.*]] = fadd double [[TMP18]], 1.000000e+00
29187 // CHECK31-NEXT:    store double [[INC18]], double* [[A17]], align 4
29188 // CHECK31-NEXT:    [[CONV19:%.*]] = fptosi double [[INC18]] to i16
29189 // CHECK31-NEXT:    [[TMP19:%.*]] = mul nsw i32 1, [[TMP1]]
29190 // CHECK31-NEXT:    [[ARRAYIDX20:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP19]]
29191 // CHECK31-NEXT:    [[ARRAYIDX21:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX20]], i32 1
29192 // CHECK31-NEXT:    store i16 [[CONV19]], i16* [[ARRAYIDX21]], align 2
29193 // CHECK31-NEXT:    br label [[OMP_BODY_CONTINUE22:%.*]]
29194 // CHECK31:       omp.body.continue22:
29195 // CHECK31-NEXT:    br label [[OMP_INNER_FOR_INC23:%.*]]
29196 // CHECK31:       omp.inner.for.inc23:
29197 // CHECK31-NEXT:    [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
29198 // CHECK31-NEXT:    [[ADD24:%.*]] = add nsw i32 [[TMP20]], 1
29199 // CHECK31-NEXT:    store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4
29200 // CHECK31-NEXT:    br label [[OMP_INNER_FOR_COND9]], !llvm.loop [[LOOP23:![0-9]+]]
29201 // CHECK31:       omp.inner.for.end25:
29202 // CHECK31-NEXT:    br label [[OMP_IF_END]]
29203 // CHECK31:       omp_if.end:
29204 // CHECK31-NEXT:    store i32 10, i32* [[I]], align 4
29205 // CHECK31-NEXT:    [[TMP21:%.*]] = mul nsw i32 1, [[TMP1]]
29206 // CHECK31-NEXT:    [[ARRAYIDX26:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP21]]
29207 // CHECK31-NEXT:    [[ARRAYIDX27:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX26]], i32 1
29208 // CHECK31-NEXT:    [[TMP22:%.*]] = load i16, i16* [[ARRAYIDX27]], align 2
29209 // CHECK31-NEXT:    [[CONV28:%.*]] = sext i16 [[TMP22]] to i32
29210 // CHECK31-NEXT:    [[TMP23:%.*]] = load i32, i32* [[B]], align 4
29211 // CHECK31-NEXT:    [[ADD29:%.*]] = add nsw i32 [[CONV28]], [[TMP23]]
29212 // CHECK31-NEXT:    [[TMP24:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
29213 // CHECK31-NEXT:    call void @llvm.stackrestore(i8* [[TMP24]])
29214 // CHECK31-NEXT:    ret i32 [[ADD29]]
29215 //
29216 //
29217 // CHECK31-LABEL: define {{[^@]+}}@_ZL7fstatici
29218 // CHECK31-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {
29219 // CHECK31-NEXT:  entry:
29220 // CHECK31-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
29221 // CHECK31-NEXT:    [[A:%.*]] = alloca i32, align 4
29222 // CHECK31-NEXT:    [[AA:%.*]] = alloca i16, align 2
29223 // CHECK31-NEXT:    [[AAA:%.*]] = alloca i8, align 1
29224 // CHECK31-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
29225 // CHECK31-NEXT:    [[TMP:%.*]] = alloca i32, align 4
29226 // CHECK31-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
29227 // CHECK31-NEXT:    [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
29228 // CHECK31-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
29229 // CHECK31-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
29230 // CHECK31-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
29231 // CHECK31-NEXT:    [[I:%.*]] = alloca i32, align 4
29232 // CHECK31-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
29233 // CHECK31-NEXT:    [[I5:%.*]] = alloca i32, align 4
29234 // CHECK31-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
29235 // CHECK31-NEXT:    store i32 0, i32* [[A]], align 4
29236 // CHECK31-NEXT:    store i16 0, i16* [[AA]], align 2
29237 // CHECK31-NEXT:    store i8 0, i8* [[AAA]], align 1
29238 // CHECK31-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
29239 // CHECK31-NEXT:    store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4
29240 // CHECK31-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
29241 // CHECK31-NEXT:    store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_1]], align 4
29242 // CHECK31-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
29243 // CHECK31-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
29244 // CHECK31-NEXT:    [[SUB:%.*]] = sub i32 [[TMP2]], [[TMP3]]
29245 // CHECK31-NEXT:    [[SUB3:%.*]] = sub i32 [[SUB]], 1
29246 // CHECK31-NEXT:    [[ADD:%.*]] = add i32 [[SUB3]], 1
29247 // CHECK31-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], 1
29248 // CHECK31-NEXT:    [[SUB4:%.*]] = sub i32 [[DIV]], 1
29249 // CHECK31-NEXT:    store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_2]], align 4
29250 // CHECK31-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
29251 // CHECK31-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
29252 // CHECK31-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_UB]], align 4
29253 // CHECK31-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
29254 // CHECK31-NEXT:    store i32 [[TMP5]], i32* [[I]], align 4
29255 // CHECK31-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
29256 // CHECK31-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
29257 // CHECK31-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]]
29258 // CHECK31-NEXT:    br i1 [[CMP]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END:%.*]]
29259 // CHECK31:       simd.if.then:
29260 // CHECK31-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
29261 // CHECK31-NEXT:    store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
29262 // CHECK31-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
29263 // CHECK31:       omp.inner.for.cond:
29264 // CHECK31-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25
29265 // CHECK31-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !25
29266 // CHECK31-NEXT:    [[ADD6:%.*]] = add i32 [[TMP10]], 1
29267 // CHECK31-NEXT:    [[CMP7:%.*]] = icmp ult i32 [[TMP9]], [[ADD6]]
29268 // CHECK31-NEXT:    br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
29269 // CHECK31:       omp.inner.for.body:
29270 // CHECK31-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group !25
29271 // CHECK31-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25
29272 // CHECK31-NEXT:    [[MUL:%.*]] = mul i32 [[TMP12]], 1
29273 // CHECK31-NEXT:    [[ADD8:%.*]] = add i32 [[TMP11]], [[MUL]]
29274 // CHECK31-NEXT:    store i32 [[ADD8]], i32* [[I5]], align 4, !llvm.access.group !25
29275 // CHECK31-NEXT:    [[TMP13:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !25
29276 // CHECK31-NEXT:    [[ADD9:%.*]] = add nsw i32 [[TMP13]], 1
29277 // CHECK31-NEXT:    store i32 [[ADD9]], i32* [[A]], align 4, !llvm.access.group !25
29278 // CHECK31-NEXT:    [[TMP14:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !25
29279 // CHECK31-NEXT:    [[CONV:%.*]] = sext i16 [[TMP14]] to i32
29280 // CHECK31-NEXT:    [[ADD10:%.*]] = add nsw i32 [[CONV]], 1
29281 // CHECK31-NEXT:    [[CONV11:%.*]] = trunc i32 [[ADD10]] to i16
29282 // CHECK31-NEXT:    store i16 [[CONV11]], i16* [[AA]], align 2, !llvm.access.group !25
29283 // CHECK31-NEXT:    [[TMP15:%.*]] = load i8, i8* [[AAA]], align 1, !llvm.access.group !25
29284 // CHECK31-NEXT:    [[CONV12:%.*]] = sext i8 [[TMP15]] to i32
29285 // CHECK31-NEXT:    [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1
29286 // CHECK31-NEXT:    [[CONV14:%.*]] = trunc i32 [[ADD13]] to i8
29287 // CHECK31-NEXT:    store i8 [[CONV14]], i8* [[AAA]], align 1, !llvm.access.group !25
29288 // CHECK31-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2
29289 // CHECK31-NEXT:    [[TMP16:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !25
29290 // CHECK31-NEXT:    [[ADD15:%.*]] = add nsw i32 [[TMP16]], 1
29291 // CHECK31-NEXT:    store i32 [[ADD15]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !25
29292 // CHECK31-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
29293 // CHECK31:       omp.body.continue:
29294 // CHECK31-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
29295 // CHECK31:       omp.inner.for.inc:
29296 // CHECK31-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25
29297 // CHECK31-NEXT:    [[ADD16:%.*]] = add i32 [[TMP17]], 1
29298 // CHECK31-NEXT:    store i32 [[ADD16]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25
29299 // CHECK31-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP26:![0-9]+]]
29300 // CHECK31:       omp.inner.for.end:
29301 // CHECK31-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
29302 // CHECK31-NEXT:    [[TMP19:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
29303 // CHECK31-NEXT:    [[TMP20:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
29304 // CHECK31-NEXT:    [[SUB17:%.*]] = sub i32 [[TMP19]], [[TMP20]]
29305 // CHECK31-NEXT:    [[SUB18:%.*]] = sub i32 [[SUB17]], 1
29306 // CHECK31-NEXT:    [[ADD19:%.*]] = add i32 [[SUB18]], 1
29307 // CHECK31-NEXT:    [[DIV20:%.*]] = udiv i32 [[ADD19]], 1
29308 // CHECK31-NEXT:    [[MUL21:%.*]] = mul i32 [[DIV20]], 1
29309 // CHECK31-NEXT:    [[ADD22:%.*]] = add i32 [[TMP18]], [[MUL21]]
29310 // CHECK31-NEXT:    store i32 [[ADD22]], i32* [[I5]], align 4
29311 // CHECK31-NEXT:    br label [[SIMD_IF_END]]
29312 // CHECK31:       simd.if.end:
29313 // CHECK31-NEXT:    [[TMP21:%.*]] = load i32, i32* [[A]], align 4
29314 // CHECK31-NEXT:    ret i32 [[TMP21]]
29315 //
29316 //
29317 // CHECK31-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
29318 // CHECK31-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat {
29319 // CHECK31-NEXT:  entry:
29320 // CHECK31-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
29321 // CHECK31-NEXT:    [[A:%.*]] = alloca i32, align 4
29322 // CHECK31-NEXT:    [[AA:%.*]] = alloca i16, align 2
29323 // CHECK31-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
29324 // CHECK31-NEXT:    [[TMP:%.*]] = alloca i32, align 4
29325 // CHECK31-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
29326 // CHECK31-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
29327 // CHECK31-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
29328 // CHECK31-NEXT:    [[I:%.*]] = alloca i32, align 4
29329 // CHECK31-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
29330 // CHECK31-NEXT:    store i32 0, i32* [[A]], align 4
29331 // CHECK31-NEXT:    store i16 0, i16* [[AA]], align 2
29332 // CHECK31-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
29333 // CHECK31-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
29334 // CHECK31-NEXT:    [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
29335 // CHECK31-NEXT:    store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4
29336 // CHECK31-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
29337 // CHECK31:       omp.inner.for.cond:
29338 // CHECK31-NEXT:    [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28
29339 // CHECK31-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !28
29340 // CHECK31-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
29341 // CHECK31-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
29342 // CHECK31:       omp.inner.for.body:
29343 // CHECK31-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28
29344 // CHECK31-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1
29345 // CHECK31-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
29346 // CHECK31-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !28
29347 // CHECK31-NEXT:    [[TMP4:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !28
29348 // CHECK31-NEXT:    [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1
29349 // CHECK31-NEXT:    store i32 [[ADD1]], i32* [[A]], align 4, !llvm.access.group !28
29350 // CHECK31-NEXT:    [[TMP5:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !28
29351 // CHECK31-NEXT:    [[CONV:%.*]] = sext i16 [[TMP5]] to i32
29352 // CHECK31-NEXT:    [[ADD2:%.*]] = add nsw i32 [[CONV]], 1
29353 // CHECK31-NEXT:    [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
29354 // CHECK31-NEXT:    store i16 [[CONV3]], i16* [[AA]], align 2, !llvm.access.group !28
29355 // CHECK31-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2
29356 // CHECK31-NEXT:    [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !28
29357 // CHECK31-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP6]], 1
29358 // CHECK31-NEXT:    store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !28
29359 // CHECK31-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
29360 // CHECK31:       omp.body.continue:
29361 // CHECK31-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
29362 // CHECK31:       omp.inner.for.inc:
29363 // CHECK31-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28
29364 // CHECK31-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP7]], 1
29365 // CHECK31-NEXT:    store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28
29366 // CHECK31-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP29:![0-9]+]]
29367 // CHECK31:       omp.inner.for.end:
29368 // CHECK31-NEXT:    store i32 10, i32* [[I]], align 4
29369 // CHECK31-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
29370 // CHECK31-NEXT:    ret i32 [[TMP8]]
29371 //
29372 //
29373 // CHECK32-LABEL: define {{[^@]+}}@_Z3fooi
29374 // CHECK32-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0:[0-9]+]] {
29375 // CHECK32-NEXT:  entry:
29376 // CHECK32-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
29377 // CHECK32-NEXT:    [[A:%.*]] = alloca i32, align 4
29378 // CHECK32-NEXT:    [[AA:%.*]] = alloca i16, align 2
29379 // CHECK32-NEXT:    [[B:%.*]] = alloca [10 x float], align 4
29380 // CHECK32-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 4
29381 // CHECK32-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 4
29382 // CHECK32-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 8
29383 // CHECK32-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i32, align 4
29384 // CHECK32-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4
29385 // CHECK32-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
29386 // CHECK32-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
29387 // CHECK32-NEXT:    [[TMP:%.*]] = alloca i32, align 4
29388 // CHECK32-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
29389 // CHECK32-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
29390 // CHECK32-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
29391 // CHECK32-NEXT:    [[I:%.*]] = alloca i32, align 4
29392 // CHECK32-NEXT:    [[_TMP4:%.*]] = alloca i32, align 4
29393 // CHECK32-NEXT:    [[DOTOMP_LB5:%.*]] = alloca i32, align 4
29394 // CHECK32-NEXT:    [[DOTOMP_UB6:%.*]] = alloca i32, align 4
29395 // CHECK32-NEXT:    [[DOTOMP_IV7:%.*]] = alloca i32, align 4
29396 // CHECK32-NEXT:    [[DOTLINEAR_START:%.*]] = alloca i32, align 4
29397 // CHECK32-NEXT:    [[A8:%.*]] = alloca i32, align 4
29398 // CHECK32-NEXT:    [[A9:%.*]] = alloca i32, align 4
29399 // CHECK32-NEXT:    [[_TMP20:%.*]] = alloca i32, align 4
29400 // CHECK32-NEXT:    [[DOTOMP_LB21:%.*]] = alloca i32, align 4
29401 // CHECK32-NEXT:    [[DOTOMP_UB22:%.*]] = alloca i32, align 4
29402 // CHECK32-NEXT:    [[DOTOMP_IV23:%.*]] = alloca i32, align 4
29403 // CHECK32-NEXT:    [[I24:%.*]] = alloca i32, align 4
29404 // CHECK32-NEXT:    [[_TMP36:%.*]] = alloca i32, align 4
29405 // CHECK32-NEXT:    [[DOTOMP_LB37:%.*]] = alloca i32, align 4
29406 // CHECK32-NEXT:    [[DOTOMP_UB38:%.*]] = alloca i32, align 4
29407 // CHECK32-NEXT:    [[DOTOMP_IV39:%.*]] = alloca i32, align 4
29408 // CHECK32-NEXT:    [[I40:%.*]] = alloca i32, align 4
29409 // CHECK32-NEXT:    [[_TMP54:%.*]] = alloca i32, align 4
29410 // CHECK32-NEXT:    [[DOTOMP_LB55:%.*]] = alloca i32, align 4
29411 // CHECK32-NEXT:    [[DOTOMP_UB56:%.*]] = alloca i32, align 4
29412 // CHECK32-NEXT:    [[DOTOMP_IV57:%.*]] = alloca i32, align 4
29413 // CHECK32-NEXT:    [[I58:%.*]] = alloca i32, align 4
29414 // CHECK32-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
29415 // CHECK32-NEXT:    store i32 0, i32* [[A]], align 4
29416 // CHECK32-NEXT:    store i16 0, i16* [[AA]], align 2
29417 // CHECK32-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
29418 // CHECK32-NEXT:    [[TMP1:%.*]] = call i8* @llvm.stacksave()
29419 // CHECK32-NEXT:    store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4
29420 // CHECK32-NEXT:    [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4
29421 // CHECK32-NEXT:    store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4
29422 // CHECK32-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
29423 // CHECK32-NEXT:    [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]]
29424 // CHECK32-NEXT:    [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8
29425 // CHECK32-NEXT:    store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4
29426 // CHECK32-NEXT:    [[TMP4:%.*]] = load i32, i32* [[A]], align 4
29427 // CHECK32-NEXT:    store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4
29428 // CHECK32-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
29429 // CHECK32-NEXT:    store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_2]], align 4
29430 // CHECK32-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
29431 // CHECK32-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
29432 // CHECK32-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
29433 // CHECK32-NEXT:    store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
29434 // CHECK32-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
29435 // CHECK32:       omp.inner.for.cond:
29436 // CHECK32-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
29437 // CHECK32-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !3
29438 // CHECK32-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
29439 // CHECK32-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
29440 // CHECK32:       omp.inner.for.body:
29441 // CHECK32-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
29442 // CHECK32-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
29443 // CHECK32-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
29444 // CHECK32-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !3
29445 // CHECK32-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
29446 // CHECK32:       omp.body.continue:
29447 // CHECK32-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
29448 // CHECK32:       omp.inner.for.inc:
29449 // CHECK32-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
29450 // CHECK32-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
29451 // CHECK32-NEXT:    store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
29452 // CHECK32-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]
29453 // CHECK32:       omp.inner.for.end:
29454 // CHECK32-NEXT:    store i32 10, i32* [[I]], align 4
29455 // CHECK32-NEXT:    store i32 0, i32* [[DOTOMP_LB5]], align 4
29456 // CHECK32-NEXT:    store i32 9, i32* [[DOTOMP_UB6]], align 4
29457 // CHECK32-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_LB5]], align 4
29458 // CHECK32-NEXT:    store i32 [[TMP11]], i32* [[DOTOMP_IV7]], align 4
29459 // CHECK32-NEXT:    [[TMP12:%.*]] = load i32, i32* [[A]], align 4
29460 // CHECK32-NEXT:    store i32 [[TMP12]], i32* [[DOTLINEAR_START]], align 4
29461 // CHECK32-NEXT:    br label [[OMP_INNER_FOR_COND10:%.*]]
29462 // CHECK32:       omp.inner.for.cond10:
29463 // CHECK32-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV7]], align 4
29464 // CHECK32-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB6]], align 4
29465 // CHECK32-NEXT:    [[CMP11:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
29466 // CHECK32-NEXT:    br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY12:%.*]], label [[OMP_INNER_FOR_END19:%.*]]
29467 // CHECK32:       omp.inner.for.body12:
29468 // CHECK32-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV7]], align 4
29469 // CHECK32-NEXT:    [[MUL13:%.*]] = mul nsw i32 [[TMP15]], 1
29470 // CHECK32-NEXT:    [[ADD14:%.*]] = add nsw i32 0, [[MUL13]]
29471 // CHECK32-NEXT:    store i32 [[ADD14]], i32* [[A8]], align 4, !nontemporal !8
29472 // CHECK32-NEXT:    [[TMP16:%.*]] = load i32, i32* [[A8]], align 4, !nontemporal !8
29473 // CHECK32-NEXT:    [[ADD15:%.*]] = add nsw i32 [[TMP16]], 1
29474 // CHECK32-NEXT:    store i32 [[ADD15]], i32* [[A8]], align 4, !nontemporal !8
29475 // CHECK32-NEXT:    br label [[OMP_BODY_CONTINUE16:%.*]]
29476 // CHECK32:       omp.body.continue16:
29477 // CHECK32-NEXT:    br label [[OMP_INNER_FOR_INC17:%.*]]
29478 // CHECK32:       omp.inner.for.inc17:
29479 // CHECK32-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV7]], align 4
29480 // CHECK32-NEXT:    [[ADD18:%.*]] = add nsw i32 [[TMP17]], 1
29481 // CHECK32-NEXT:    store i32 [[ADD18]], i32* [[DOTOMP_IV7]], align 4
29482 // CHECK32-NEXT:    br label [[OMP_INNER_FOR_COND10]], !llvm.loop [[LOOP9:![0-9]+]]
29483 // CHECK32:       omp.inner.for.end19:
29484 // CHECK32-NEXT:    store i32 10, i32* [[A]], align 4
29485 // CHECK32-NEXT:    store i32 0, i32* [[DOTOMP_LB21]], align 4
29486 // CHECK32-NEXT:    store i32 9, i32* [[DOTOMP_UB22]], align 4
29487 // CHECK32-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTOMP_LB21]], align 4
29488 // CHECK32-NEXT:    store i32 [[TMP18]], i32* [[DOTOMP_IV23]], align 4
29489 // CHECK32-NEXT:    br label [[OMP_INNER_FOR_COND25:%.*]]
29490 // CHECK32:       omp.inner.for.cond25:
29491 // CHECK32-NEXT:    [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV23]], align 4, !llvm.access.group !11
29492 // CHECK32-NEXT:    [[TMP20:%.*]] = load i32, i32* [[DOTOMP_UB22]], align 4, !llvm.access.group !11
29493 // CHECK32-NEXT:    [[CMP26:%.*]] = icmp sle i32 [[TMP19]], [[TMP20]]
29494 // CHECK32-NEXT:    br i1 [[CMP26]], label [[OMP_INNER_FOR_BODY27:%.*]], label [[OMP_INNER_FOR_END35:%.*]]
29495 // CHECK32:       omp.inner.for.body27:
29496 // CHECK32-NEXT:    [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV23]], align 4, !llvm.access.group !11
29497 // CHECK32-NEXT:    [[MUL28:%.*]] = mul nsw i32 [[TMP21]], 1
29498 // CHECK32-NEXT:    [[ADD29:%.*]] = add nsw i32 0, [[MUL28]]
29499 // CHECK32-NEXT:    store i32 [[ADD29]], i32* [[I24]], align 4, !llvm.access.group !11
29500 // CHECK32-NEXT:    [[TMP22:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !11
29501 // CHECK32-NEXT:    [[CONV:%.*]] = sext i16 [[TMP22]] to i32
29502 // CHECK32-NEXT:    [[ADD30:%.*]] = add nsw i32 [[CONV]], 1
29503 // CHECK32-NEXT:    [[CONV31:%.*]] = trunc i32 [[ADD30]] to i16
29504 // CHECK32-NEXT:    store i16 [[CONV31]], i16* [[AA]], align 2, !llvm.access.group !11
29505 // CHECK32-NEXT:    br label [[OMP_BODY_CONTINUE32:%.*]]
29506 // CHECK32:       omp.body.continue32:
29507 // CHECK32-NEXT:    br label [[OMP_INNER_FOR_INC33:%.*]]
29508 // CHECK32:       omp.inner.for.inc33:
29509 // CHECK32-NEXT:    [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV23]], align 4, !llvm.access.group !11
29510 // CHECK32-NEXT:    [[ADD34:%.*]] = add nsw i32 [[TMP23]], 1
29511 // CHECK32-NEXT:    store i32 [[ADD34]], i32* [[DOTOMP_IV23]], align 4, !llvm.access.group !11
29512 // CHECK32-NEXT:    br label [[OMP_INNER_FOR_COND25]], !llvm.loop [[LOOP12:![0-9]+]]
29513 // CHECK32:       omp.inner.for.end35:
29514 // CHECK32-NEXT:    store i32 10, i32* [[I24]], align 4
29515 // CHECK32-NEXT:    store i32 0, i32* [[DOTOMP_LB37]], align 4
29516 // CHECK32-NEXT:    store i32 9, i32* [[DOTOMP_UB38]], align 4
29517 // CHECK32-NEXT:    [[TMP24:%.*]] = load i32, i32* [[DOTOMP_LB37]], align 4
29518 // CHECK32-NEXT:    store i32 [[TMP24]], i32* [[DOTOMP_IV39]], align 4
29519 // CHECK32-NEXT:    br label [[OMP_INNER_FOR_COND41:%.*]]
29520 // CHECK32:       omp.inner.for.cond41:
29521 // CHECK32-NEXT:    [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IV39]], align 4, !llvm.access.group !14
29522 // CHECK32-NEXT:    [[TMP26:%.*]] = load i32, i32* [[DOTOMP_UB38]], align 4, !llvm.access.group !14
29523 // CHECK32-NEXT:    [[CMP42:%.*]] = icmp sle i32 [[TMP25]], [[TMP26]]
29524 // CHECK32-NEXT:    br i1 [[CMP42]], label [[OMP_INNER_FOR_BODY43:%.*]], label [[OMP_INNER_FOR_END53:%.*]]
29525 // CHECK32:       omp.inner.for.body43:
29526 // CHECK32-NEXT:    [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV39]], align 4, !llvm.access.group !14
29527 // CHECK32-NEXT:    [[MUL44:%.*]] = mul nsw i32 [[TMP27]], 1
29528 // CHECK32-NEXT:    [[ADD45:%.*]] = add nsw i32 0, [[MUL44]]
29529 // CHECK32-NEXT:    store i32 [[ADD45]], i32* [[I40]], align 4, !llvm.access.group !14
29530 // CHECK32-NEXT:    [[TMP28:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !14
29531 // CHECK32-NEXT:    [[ADD46:%.*]] = add nsw i32 [[TMP28]], 1
29532 // CHECK32-NEXT:    store i32 [[ADD46]], i32* [[A]], align 4, !llvm.access.group !14
29533 // CHECK32-NEXT:    [[TMP29:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !14
29534 // CHECK32-NEXT:    [[CONV47:%.*]] = sext i16 [[TMP29]] to i32
29535 // CHECK32-NEXT:    [[ADD48:%.*]] = add nsw i32 [[CONV47]], 1
29536 // CHECK32-NEXT:    [[CONV49:%.*]] = trunc i32 [[ADD48]] to i16
29537 // CHECK32-NEXT:    store i16 [[CONV49]], i16* [[AA]], align 2, !llvm.access.group !14
29538 // CHECK32-NEXT:    br label [[OMP_BODY_CONTINUE50:%.*]]
29539 // CHECK32:       omp.body.continue50:
29540 // CHECK32-NEXT:    br label [[OMP_INNER_FOR_INC51:%.*]]
29541 // CHECK32:       omp.inner.for.inc51:
29542 // CHECK32-NEXT:    [[TMP30:%.*]] = load i32, i32* [[DOTOMP_IV39]], align 4, !llvm.access.group !14
29543 // CHECK32-NEXT:    [[ADD52:%.*]] = add nsw i32 [[TMP30]], 1
29544 // CHECK32-NEXT:    store i32 [[ADD52]], i32* [[DOTOMP_IV39]], align 4, !llvm.access.group !14
29545 // CHECK32-NEXT:    br label [[OMP_INNER_FOR_COND41]], !llvm.loop [[LOOP15:![0-9]+]]
29546 // CHECK32:       omp.inner.for.end53:
29547 // CHECK32-NEXT:    store i32 10, i32* [[I40]], align 4
29548 // CHECK32-NEXT:    store i32 0, i32* [[DOTOMP_LB55]], align 4
29549 // CHECK32-NEXT:    store i32 9, i32* [[DOTOMP_UB56]], align 4
29550 // CHECK32-NEXT:    [[TMP31:%.*]] = load i32, i32* [[DOTOMP_LB55]], align 4
29551 // CHECK32-NEXT:    store i32 [[TMP31]], i32* [[DOTOMP_IV57]], align 4
29552 // CHECK32-NEXT:    [[ARRAYDECAY:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 0
29553 // CHECK32-NEXT:    call void @llvm.assume(i1 true) [ "align"(float* [[ARRAYDECAY]], i32 16) ]
29554 // CHECK32-NEXT:    br label [[OMP_INNER_FOR_COND59:%.*]]
29555 // CHECK32:       omp.inner.for.cond59:
29556 // CHECK32-NEXT:    [[TMP32:%.*]] = load i32, i32* [[DOTOMP_IV57]], align 4, !llvm.access.group !17
29557 // CHECK32-NEXT:    [[TMP33:%.*]] = load i32, i32* [[DOTOMP_UB56]], align 4, !llvm.access.group !17
29558 // CHECK32-NEXT:    [[CMP60:%.*]] = icmp sle i32 [[TMP32]], [[TMP33]]
29559 // CHECK32-NEXT:    br i1 [[CMP60]], label [[OMP_INNER_FOR_BODY61:%.*]], label [[OMP_INNER_FOR_END85:%.*]]
29560 // CHECK32:       omp.inner.for.body61:
29561 // CHECK32-NEXT:    [[TMP34:%.*]] = load i32, i32* [[DOTOMP_IV57]], align 4, !llvm.access.group !17
29562 // CHECK32-NEXT:    [[MUL62:%.*]] = mul nsw i32 [[TMP34]], 1
29563 // CHECK32-NEXT:    [[ADD63:%.*]] = add nsw i32 0, [[MUL62]]
29564 // CHECK32-NEXT:    store i32 [[ADD63]], i32* [[I58]], align 4, !llvm.access.group !17
29565 // CHECK32-NEXT:    [[TMP35:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !17
29566 // CHECK32-NEXT:    [[ADD64:%.*]] = add nsw i32 [[TMP35]], 1
29567 // CHECK32-NEXT:    store i32 [[ADD64]], i32* [[A]], align 4, !llvm.access.group !17
29568 // CHECK32-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2
29569 // CHECK32-NEXT:    [[TMP36:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !17
29570 // CHECK32-NEXT:    [[CONV65:%.*]] = fpext float [[TMP36]] to double
29571 // CHECK32-NEXT:    [[ADD66:%.*]] = fadd double [[CONV65]], 1.000000e+00
29572 // CHECK32-NEXT:    [[CONV67:%.*]] = fptrunc double [[ADD66]] to float
29573 // CHECK32-NEXT:    store float [[CONV67]], float* [[ARRAYIDX]], align 4, !llvm.access.group !17
29574 // CHECK32-NEXT:    [[ARRAYIDX68:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3
29575 // CHECK32-NEXT:    [[TMP37:%.*]] = load float, float* [[ARRAYIDX68]], align 4, !llvm.access.group !17
29576 // CHECK32-NEXT:    [[CONV69:%.*]] = fpext float [[TMP37]] to double
29577 // CHECK32-NEXT:    [[ADD70:%.*]] = fadd double [[CONV69]], 1.000000e+00
29578 // CHECK32-NEXT:    [[CONV71:%.*]] = fptrunc double [[ADD70]] to float
29579 // CHECK32-NEXT:    store float [[CONV71]], float* [[ARRAYIDX68]], align 4, !llvm.access.group !17
29580 // CHECK32-NEXT:    [[ARRAYIDX72:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1
29581 // CHECK32-NEXT:    [[ARRAYIDX73:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX72]], i32 0, i32 2
29582 // CHECK32-NEXT:    [[TMP38:%.*]] = load double, double* [[ARRAYIDX73]], align 8, !llvm.access.group !17
29583 // CHECK32-NEXT:    [[ADD74:%.*]] = fadd double [[TMP38]], 1.000000e+00
29584 // CHECK32-NEXT:    store double [[ADD74]], double* [[ARRAYIDX73]], align 8, !llvm.access.group !17
29585 // CHECK32-NEXT:    [[TMP39:%.*]] = mul nsw i32 1, [[TMP2]]
29586 // CHECK32-NEXT:    [[ARRAYIDX75:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP39]]
29587 // CHECK32-NEXT:    [[ARRAYIDX76:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX75]], i32 3
29588 // CHECK32-NEXT:    [[TMP40:%.*]] = load double, double* [[ARRAYIDX76]], align 8, !llvm.access.group !17
29589 // CHECK32-NEXT:    [[ADD77:%.*]] = fadd double [[TMP40]], 1.000000e+00
29590 // CHECK32-NEXT:    store double [[ADD77]], double* [[ARRAYIDX76]], align 8, !llvm.access.group !17
29591 // CHECK32-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0
29592 // CHECK32-NEXT:    [[TMP41:%.*]] = load i64, i64* [[X]], align 4, !llvm.access.group !17
29593 // CHECK32-NEXT:    [[ADD78:%.*]] = add nsw i64 [[TMP41]], 1
29594 // CHECK32-NEXT:    store i64 [[ADD78]], i64* [[X]], align 4, !llvm.access.group !17
29595 // CHECK32-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1
29596 // CHECK32-NEXT:    [[TMP42:%.*]] = load i8, i8* [[Y]], align 4, !llvm.access.group !17
29597 // CHECK32-NEXT:    [[CONV79:%.*]] = sext i8 [[TMP42]] to i32
29598 // CHECK32-NEXT:    [[ADD80:%.*]] = add nsw i32 [[CONV79]], 1
29599 // CHECK32-NEXT:    [[CONV81:%.*]] = trunc i32 [[ADD80]] to i8
29600 // CHECK32-NEXT:    store i8 [[CONV81]], i8* [[Y]], align 4, !llvm.access.group !17
29601 // CHECK32-NEXT:    br label [[OMP_BODY_CONTINUE82:%.*]]
29602 // CHECK32:       omp.body.continue82:
29603 // CHECK32-NEXT:    br label [[OMP_INNER_FOR_INC83:%.*]]
29604 // CHECK32:       omp.inner.for.inc83:
29605 // CHECK32-NEXT:    [[TMP43:%.*]] = load i32, i32* [[DOTOMP_IV57]], align 4, !llvm.access.group !17
29606 // CHECK32-NEXT:    [[ADD84:%.*]] = add nsw i32 [[TMP43]], 1
29607 // CHECK32-NEXT:    store i32 [[ADD84]], i32* [[DOTOMP_IV57]], align 4, !llvm.access.group !17
29608 // CHECK32-NEXT:    br label [[OMP_INNER_FOR_COND59]], !llvm.loop [[LOOP18:![0-9]+]]
29609 // CHECK32:       omp.inner.for.end85:
29610 // CHECK32-NEXT:    store i32 10, i32* [[I58]], align 4
29611 // CHECK32-NEXT:    [[TMP44:%.*]] = load i32, i32* [[A]], align 4
29612 // CHECK32-NEXT:    [[TMP45:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
29613 // CHECK32-NEXT:    call void @llvm.stackrestore(i8* [[TMP45]])
29614 // CHECK32-NEXT:    ret i32 [[TMP44]]
29615 //
29616 //
29617 // CHECK32-LABEL: define {{[^@]+}}@_Z3bari
29618 // CHECK32-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {
29619 // CHECK32-NEXT:  entry:
29620 // CHECK32-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
29621 // CHECK32-NEXT:    [[A:%.*]] = alloca i32, align 4
29622 // CHECK32-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4
29623 // CHECK32-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
29624 // CHECK32-NEXT:    store i32 0, i32* [[A]], align 4
29625 // CHECK32-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
29626 // CHECK32-NEXT:    [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]])
29627 // CHECK32-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
29628 // CHECK32-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
29629 // CHECK32-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
29630 // CHECK32-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
29631 // CHECK32-NEXT:    [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP2]])
29632 // CHECK32-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
29633 // CHECK32-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
29634 // CHECK32-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
29635 // CHECK32-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
29636 // CHECK32-NEXT:    [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]])
29637 // CHECK32-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
29638 // CHECK32-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
29639 // CHECK32-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
29640 // CHECK32-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
29641 // CHECK32-NEXT:    [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]])
29642 // CHECK32-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
29643 // CHECK32-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
29644 // CHECK32-NEXT:    store i32 [[ADD6]], i32* [[A]], align 4
29645 // CHECK32-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
29646 // CHECK32-NEXT:    ret i32 [[TMP8]]
29647 //
29648 //
29649 // CHECK32-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
29650 // CHECK32-SAME: (%struct.S1* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 {
29651 // CHECK32-NEXT:  entry:
29652 // CHECK32-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
29653 // CHECK32-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
29654 // CHECK32-NEXT:    [[B:%.*]] = alloca i32, align 4
29655 // CHECK32-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 4
29656 // CHECK32-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 4
29657 // CHECK32-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
29658 // CHECK32-NEXT:    [[TMP:%.*]] = alloca i32, align 4
29659 // CHECK32-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
29660 // CHECK32-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
29661 // CHECK32-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
29662 // CHECK32-NEXT:    [[I:%.*]] = alloca i32, align 4
29663 // CHECK32-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
29664 // CHECK32-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
29665 // CHECK32-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
29666 // CHECK32-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
29667 // CHECK32-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
29668 // CHECK32-NEXT:    store i32 [[ADD]], i32* [[B]], align 4
29669 // CHECK32-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
29670 // CHECK32-NEXT:    [[TMP2:%.*]] = call i8* @llvm.stacksave()
29671 // CHECK32-NEXT:    store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4
29672 // CHECK32-NEXT:    [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]
29673 // CHECK32-NEXT:    [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2
29674 // CHECK32-NEXT:    store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
29675 // CHECK32-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
29676 // CHECK32-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 60
29677 // CHECK32-NEXT:    [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8
29678 // CHECK32-NEXT:    store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
29679 // CHECK32-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
29680 // CHECK32-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
29681 // CHECK32-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
29682 // CHECK32-NEXT:    store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
29683 // CHECK32-NEXT:    [[TMP6:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
29684 // CHECK32-NEXT:    [[TOBOOL:%.*]] = trunc i8 [[TMP6]] to i1
29685 // CHECK32-NEXT:    br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
29686 // CHECK32:       omp_if.then:
29687 // CHECK32-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
29688 // CHECK32:       omp.inner.for.cond:
29689 // CHECK32-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20
29690 // CHECK32-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !20
29691 // CHECK32-NEXT:    [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
29692 // CHECK32-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
29693 // CHECK32:       omp.inner.for.body:
29694 // CHECK32-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20
29695 // CHECK32-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
29696 // CHECK32-NEXT:    [[ADD3:%.*]] = add nsw i32 0, [[MUL]]
29697 // CHECK32-NEXT:    store i32 [[ADD3]], i32* [[I]], align 4, !llvm.access.group !20
29698 // CHECK32-NEXT:    [[TMP10:%.*]] = load i32, i32* [[B]], align 4, !llvm.access.group !20
29699 // CHECK32-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP10]] to double
29700 // CHECK32-NEXT:    [[ADD4:%.*]] = fadd double [[CONV]], 1.500000e+00
29701 // CHECK32-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
29702 // CHECK32-NEXT:    store double [[ADD4]], double* [[A]], align 4, !llvm.access.group !20
29703 // CHECK32-NEXT:    [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
29704 // CHECK32-NEXT:    [[TMP11:%.*]] = load double, double* [[A5]], align 4, !llvm.access.group !20
29705 // CHECK32-NEXT:    [[INC:%.*]] = fadd double [[TMP11]], 1.000000e+00
29706 // CHECK32-NEXT:    store double [[INC]], double* [[A5]], align 4, !llvm.access.group !20
29707 // CHECK32-NEXT:    [[CONV6:%.*]] = fptosi double [[INC]] to i16
29708 // CHECK32-NEXT:    [[TMP12:%.*]] = mul nsw i32 1, [[TMP1]]
29709 // CHECK32-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP12]]
29710 // CHECK32-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
29711 // CHECK32-NEXT:    store i16 [[CONV6]], i16* [[ARRAYIDX7]], align 2, !llvm.access.group !20
29712 // CHECK32-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
29713 // CHECK32:       omp.body.continue:
29714 // CHECK32-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
29715 // CHECK32:       omp.inner.for.inc:
29716 // CHECK32-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20
29717 // CHECK32-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP13]], 1
29718 // CHECK32-NEXT:    store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20
29719 // CHECK32-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]]
29720 // CHECK32:       omp.inner.for.end:
29721 // CHECK32-NEXT:    br label [[OMP_IF_END:%.*]]
29722 // CHECK32:       omp_if.else:
29723 // CHECK32-NEXT:    br label [[OMP_INNER_FOR_COND9:%.*]]
29724 // CHECK32:       omp.inner.for.cond9:
29725 // CHECK32-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
29726 // CHECK32-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
29727 // CHECK32-NEXT:    [[CMP10:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
29728 // CHECK32-NEXT:    br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY11:%.*]], label [[OMP_INNER_FOR_END25:%.*]]
29729 // CHECK32:       omp.inner.for.body11:
29730 // CHECK32-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
29731 // CHECK32-NEXT:    [[MUL12:%.*]] = mul nsw i32 [[TMP16]], 1
29732 // CHECK32-NEXT:    [[ADD13:%.*]] = add nsw i32 0, [[MUL12]]
29733 // CHECK32-NEXT:    store i32 [[ADD13]], i32* [[I]], align 4
29734 // CHECK32-NEXT:    [[TMP17:%.*]] = load i32, i32* [[B]], align 4
29735 // CHECK32-NEXT:    [[CONV14:%.*]] = sitofp i32 [[TMP17]] to double
29736 // CHECK32-NEXT:    [[ADD15:%.*]] = fadd double [[CONV14]], 1.500000e+00
29737 // CHECK32-NEXT:    [[A16:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
29738 // CHECK32-NEXT:    store double [[ADD15]], double* [[A16]], align 4
29739 // CHECK32-NEXT:    [[A17:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
29740 // CHECK32-NEXT:    [[TMP18:%.*]] = load double, double* [[A17]], align 4
29741 // CHECK32-NEXT:    [[INC18:%.*]] = fadd double [[TMP18]], 1.000000e+00
29742 // CHECK32-NEXT:    store double [[INC18]], double* [[A17]], align 4
29743 // CHECK32-NEXT:    [[CONV19:%.*]] = fptosi double [[INC18]] to i16
29744 // CHECK32-NEXT:    [[TMP19:%.*]] = mul nsw i32 1, [[TMP1]]
29745 // CHECK32-NEXT:    [[ARRAYIDX20:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP19]]
29746 // CHECK32-NEXT:    [[ARRAYIDX21:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX20]], i32 1
29747 // CHECK32-NEXT:    store i16 [[CONV19]], i16* [[ARRAYIDX21]], align 2
29748 // CHECK32-NEXT:    br label [[OMP_BODY_CONTINUE22:%.*]]
29749 // CHECK32:       omp.body.continue22:
29750 // CHECK32-NEXT:    br label [[OMP_INNER_FOR_INC23:%.*]]
29751 // CHECK32:       omp.inner.for.inc23:
29752 // CHECK32-NEXT:    [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
29753 // CHECK32-NEXT:    [[ADD24:%.*]] = add nsw i32 [[TMP20]], 1
29754 // CHECK32-NEXT:    store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4
29755 // CHECK32-NEXT:    br label [[OMP_INNER_FOR_COND9]], !llvm.loop [[LOOP23:![0-9]+]]
29756 // CHECK32:       omp.inner.for.end25:
29757 // CHECK32-NEXT:    br label [[OMP_IF_END]]
29758 // CHECK32:       omp_if.end:
29759 // CHECK32-NEXT:    store i32 10, i32* [[I]], align 4
29760 // CHECK32-NEXT:    [[TMP21:%.*]] = mul nsw i32 1, [[TMP1]]
29761 // CHECK32-NEXT:    [[ARRAYIDX26:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP21]]
29762 // CHECK32-NEXT:    [[ARRAYIDX27:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX26]], i32 1
29763 // CHECK32-NEXT:    [[TMP22:%.*]] = load i16, i16* [[ARRAYIDX27]], align 2
29764 // CHECK32-NEXT:    [[CONV28:%.*]] = sext i16 [[TMP22]] to i32
29765 // CHECK32-NEXT:    [[TMP23:%.*]] = load i32, i32* [[B]], align 4
29766 // CHECK32-NEXT:    [[ADD29:%.*]] = add nsw i32 [[CONV28]], [[TMP23]]
29767 // CHECK32-NEXT:    [[TMP24:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
29768 // CHECK32-NEXT:    call void @llvm.stackrestore(i8* [[TMP24]])
29769 // CHECK32-NEXT:    ret i32 [[ADD29]]
29770 //
29771 //
29772 // CHECK32-LABEL: define {{[^@]+}}@_ZL7fstatici
29773 // CHECK32-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {
29774 // CHECK32-NEXT:  entry:
29775 // CHECK32-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
29776 // CHECK32-NEXT:    [[A:%.*]] = alloca i32, align 4
29777 // CHECK32-NEXT:    [[AA:%.*]] = alloca i16, align 2
29778 // CHECK32-NEXT:    [[AAA:%.*]] = alloca i8, align 1
29779 // CHECK32-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
29780 // CHECK32-NEXT:    [[TMP:%.*]] = alloca i32, align 4
29781 // CHECK32-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
29782 // CHECK32-NEXT:    [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
29783 // CHECK32-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
29784 // CHECK32-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
29785 // CHECK32-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
29786 // CHECK32-NEXT:    [[I:%.*]] = alloca i32, align 4
29787 // CHECK32-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
29788 // CHECK32-NEXT:    [[I5:%.*]] = alloca i32, align 4
29789 // CHECK32-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
29790 // CHECK32-NEXT:    store i32 0, i32* [[A]], align 4
29791 // CHECK32-NEXT:    store i16 0, i16* [[AA]], align 2
29792 // CHECK32-NEXT:    store i8 0, i8* [[AAA]], align 1
29793 // CHECK32-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
29794 // CHECK32-NEXT:    store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4
29795 // CHECK32-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
29796 // CHECK32-NEXT:    store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_1]], align 4
29797 // CHECK32-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
29798 // CHECK32-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
29799 // CHECK32-NEXT:    [[SUB:%.*]] = sub i32 [[TMP2]], [[TMP3]]
29800 // CHECK32-NEXT:    [[SUB3:%.*]] = sub i32 [[SUB]], 1
29801 // CHECK32-NEXT:    [[ADD:%.*]] = add i32 [[SUB3]], 1
29802 // CHECK32-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], 1
29803 // CHECK32-NEXT:    [[SUB4:%.*]] = sub i32 [[DIV]], 1
29804 // CHECK32-NEXT:    store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_2]], align 4
29805 // CHECK32-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
29806 // CHECK32-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
29807 // CHECK32-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_UB]], align 4
29808 // CHECK32-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
29809 // CHECK32-NEXT:    store i32 [[TMP5]], i32* [[I]], align 4
29810 // CHECK32-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
29811 // CHECK32-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
29812 // CHECK32-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]]
29813 // CHECK32-NEXT:    br i1 [[CMP]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END:%.*]]
29814 // CHECK32:       simd.if.then:
29815 // CHECK32-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
29816 // CHECK32-NEXT:    store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
29817 // CHECK32-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
29818 // CHECK32:       omp.inner.for.cond:
29819 // CHECK32-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25
29820 // CHECK32-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !25
29821 // CHECK32-NEXT:    [[ADD6:%.*]] = add i32 [[TMP10]], 1
29822 // CHECK32-NEXT:    [[CMP7:%.*]] = icmp ult i32 [[TMP9]], [[ADD6]]
29823 // CHECK32-NEXT:    br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
29824 // CHECK32:       omp.inner.for.body:
29825 // CHECK32-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group !25
29826 // CHECK32-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25
29827 // CHECK32-NEXT:    [[MUL:%.*]] = mul i32 [[TMP12]], 1
29828 // CHECK32-NEXT:    [[ADD8:%.*]] = add i32 [[TMP11]], [[MUL]]
29829 // CHECK32-NEXT:    store i32 [[ADD8]], i32* [[I5]], align 4, !llvm.access.group !25
29830 // CHECK32-NEXT:    [[TMP13:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !25
29831 // CHECK32-NEXT:    [[ADD9:%.*]] = add nsw i32 [[TMP13]], 1
29832 // CHECK32-NEXT:    store i32 [[ADD9]], i32* [[A]], align 4, !llvm.access.group !25
29833 // CHECK32-NEXT:    [[TMP14:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !25
29834 // CHECK32-NEXT:    [[CONV:%.*]] = sext i16 [[TMP14]] to i32
29835 // CHECK32-NEXT:    [[ADD10:%.*]] = add nsw i32 [[CONV]], 1
29836 // CHECK32-NEXT:    [[CONV11:%.*]] = trunc i32 [[ADD10]] to i16
29837 // CHECK32-NEXT:    store i16 [[CONV11]], i16* [[AA]], align 2, !llvm.access.group !25
29838 // CHECK32-NEXT:    [[TMP15:%.*]] = load i8, i8* [[AAA]], align 1, !llvm.access.group !25
29839 // CHECK32-NEXT:    [[CONV12:%.*]] = sext i8 [[TMP15]] to i32
29840 // CHECK32-NEXT:    [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1
29841 // CHECK32-NEXT:    [[CONV14:%.*]] = trunc i32 [[ADD13]] to i8
29842 // CHECK32-NEXT:    store i8 [[CONV14]], i8* [[AAA]], align 1, !llvm.access.group !25
29843 // CHECK32-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2
29844 // CHECK32-NEXT:    [[TMP16:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !25
29845 // CHECK32-NEXT:    [[ADD15:%.*]] = add nsw i32 [[TMP16]], 1
29846 // CHECK32-NEXT:    store i32 [[ADD15]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !25
29847 // CHECK32-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
29848 // CHECK32:       omp.body.continue:
29849 // CHECK32-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
29850 // CHECK32:       omp.inner.for.inc:
29851 // CHECK32-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25
29852 // CHECK32-NEXT:    [[ADD16:%.*]] = add i32 [[TMP17]], 1
29853 // CHECK32-NEXT:    store i32 [[ADD16]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25
29854 // CHECK32-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP26:![0-9]+]]
29855 // CHECK32:       omp.inner.for.end:
29856 // CHECK32-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
29857 // CHECK32-NEXT:    [[TMP19:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
29858 // CHECK32-NEXT:    [[TMP20:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
29859 // CHECK32-NEXT:    [[SUB17:%.*]] = sub i32 [[TMP19]], [[TMP20]]
29860 // CHECK32-NEXT:    [[SUB18:%.*]] = sub i32 [[SUB17]], 1
29861 // CHECK32-NEXT:    [[ADD19:%.*]] = add i32 [[SUB18]], 1
29862 // CHECK32-NEXT:    [[DIV20:%.*]] = udiv i32 [[ADD19]], 1
29863 // CHECK32-NEXT:    [[MUL21:%.*]] = mul i32 [[DIV20]], 1
29864 // CHECK32-NEXT:    [[ADD22:%.*]] = add i32 [[TMP18]], [[MUL21]]
29865 // CHECK32-NEXT:    store i32 [[ADD22]], i32* [[I5]], align 4
29866 // CHECK32-NEXT:    br label [[SIMD_IF_END]]
29867 // CHECK32:       simd.if.end:
29868 // CHECK32-NEXT:    [[TMP21:%.*]] = load i32, i32* [[A]], align 4
29869 // CHECK32-NEXT:    ret i32 [[TMP21]]
29870 //
29871 //
29872 // CHECK32-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
29873 // CHECK32-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat {
29874 // CHECK32-NEXT:  entry:
29875 // CHECK32-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
29876 // CHECK32-NEXT:    [[A:%.*]] = alloca i32, align 4
29877 // CHECK32-NEXT:    [[AA:%.*]] = alloca i16, align 2
29878 // CHECK32-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
29879 // CHECK32-NEXT:    [[TMP:%.*]] = alloca i32, align 4
29880 // CHECK32-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
29881 // CHECK32-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
29882 // CHECK32-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
29883 // CHECK32-NEXT:    [[I:%.*]] = alloca i32, align 4
29884 // CHECK32-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
29885 // CHECK32-NEXT:    store i32 0, i32* [[A]], align 4
29886 // CHECK32-NEXT:    store i16 0, i16* [[AA]], align 2
29887 // CHECK32-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
29888 // CHECK32-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
29889 // CHECK32-NEXT:    [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
29890 // CHECK32-NEXT:    store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4
29891 // CHECK32-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
29892 // CHECK32:       omp.inner.for.cond:
29893 // CHECK32-NEXT:    [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28
29894 // CHECK32-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !28
29895 // CHECK32-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
29896 // CHECK32-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
29897 // CHECK32:       omp.inner.for.body:
29898 // CHECK32-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28
29899 // CHECK32-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1
29900 // CHECK32-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
29901 // CHECK32-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !28
29902 // CHECK32-NEXT:    [[TMP4:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !28
29903 // CHECK32-NEXT:    [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1
29904 // CHECK32-NEXT:    store i32 [[ADD1]], i32* [[A]], align 4, !llvm.access.group !28
29905 // CHECK32-NEXT:    [[TMP5:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !28
29906 // CHECK32-NEXT:    [[CONV:%.*]] = sext i16 [[TMP5]] to i32
29907 // CHECK32-NEXT:    [[ADD2:%.*]] = add nsw i32 [[CONV]], 1
29908 // CHECK32-NEXT:    [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
29909 // CHECK32-NEXT:    store i16 [[CONV3]], i16* [[AA]], align 2, !llvm.access.group !28
29910 // CHECK32-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2
29911 // CHECK32-NEXT:    [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !28
29912 // CHECK32-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP6]], 1
29913 // CHECK32-NEXT:    store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !28
29914 // CHECK32-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
29915 // CHECK32:       omp.body.continue:
29916 // CHECK32-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
29917 // CHECK32:       omp.inner.for.inc:
29918 // CHECK32-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28
29919 // CHECK32-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP7]], 1
29920 // CHECK32-NEXT:    store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28
29921 // CHECK32-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP29:![0-9]+]]
29922 // CHECK32:       omp.inner.for.end:
29923 // CHECK32-NEXT:    store i32 10, i32* [[I]], align 4
29924 // CHECK32-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
29925 // CHECK32-NEXT:    ret i32 [[TMP8]]
29926 //
29927