1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _
2 // Test host codegen.
3 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck  %s --check-prefix=CHECK1
4 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
5 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck  %s --check-prefix=CHECK1
6 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck  %s --check-prefix=CHECK3
7 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
8 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck  %s --check-prefix=CHECK3
9 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=50 -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck  %s --check-prefix=CHECK5
10 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=50 -DOMP5 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
11 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=50 -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck  %s --check-prefix=CHECK5
12 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=50 -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck  %s --check-prefix=CHECK7
13 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=50 -DOMP5 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
14 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=50 -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck  %s --check-prefix=CHECK7
15 
16 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck  %s --check-prefix=CHECK9
17 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
18 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck  %s --check-prefix=CHECK9
19 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck  %s --check-prefix=CHECK11
20 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
21 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck  %s --check-prefix=CHECK11
22 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -fopenmp-version=50 -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck  %s --check-prefix=CHECK13
23 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=50 -DOMP5 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
24 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=50 -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck  %s --check-prefix=CHECK13
25 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -fopenmp-version=50 -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck  %s --check-prefix=CHECK15
26 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=50 -DOMP5 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
27 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=50 -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck  %s --check-prefix=CHECK15
28 
29 // Test target codegen - host bc file has to be created first.
30 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc
31 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck  %s --check-prefix=CHECK17
32 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s
33 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck  %s --check-prefix=CHECK17
34 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc
35 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck  %s --check-prefix=CHECK19
36 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s
37 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck  %s --check-prefix=CHECK19
38 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=50 -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc
39 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=50 -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck  %s --check-prefix=CHECK21
40 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=50 -DOMP5 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s
41 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=50 -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck  %s --check-prefix=CHECK21
42 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=50 -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc
43 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=50 -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck  %s --check-prefix=CHECK23
44 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=50 -DOMP5 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s
45 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=50 -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck  %s --check-prefix=CHECK23
46 
47 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc
48 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck  %s --check-prefix=CHECK9
49 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s
50 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck  %s --check-prefix=CHECK9
51 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc
52 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck  %s --check-prefix=CHECK11
53 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s
54 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck  %s --check-prefix=CHECK11
55 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -fopenmp-version=50 -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc
56 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -fopenmp-version=50 -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck  %s --check-prefix=CHECK13
57 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=50 -DOMP5 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s
58 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=50 -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck  %s --check-prefix=CHECK13
59 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -fopenmp-version=50 -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc
60 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -fopenmp-version=50 -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck  %s --check-prefix=CHECK15
61 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=50 -DOMP5 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s
62 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=50 -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck  %s --check-prefix=CHECK15
63 // expected-no-diagnostics
64 
65 #ifndef HEADER
66 #define HEADER
67 
68 
69 
70 
71 // We have 8 target regions, but only 7 that actually will generate offloading
72 // code, only 6 will have mapped arguments, and only 4 have all-constant map
73 // sizes.
74 
75 
76 
77 // Check target registration is registered as a Ctor.
78 
79 
80 template<typename tx, typename ty>
81 struct TT{
82   tx X;
83   ty Y;
84 };
85 
86 int global;
87 
88 int foo(int n) {
89   int a = 0;
90   short aa = 0;
91   float b[10];
92   float bn[n];
93   double c[5][10];
94   double cn[5][n];
95   TT<long long, char> d;
96 
97   #pragma omp target teams distribute simd num_teams(a) thread_limit(a) firstprivate(aa) simdlen(16) nowait
98   for (int i = 0; i < 10; ++i) {
99   }
100 
101 #ifdef OMP5
102   #pragma omp target teams distribute simd if(target: 0) safelen(32) linear(a) if(simd: 1) nontemporal(a)
103 #else
104   #pragma omp target teams distribute simd if(target: 0) safelen(32) linear(a)
105 #endif // OMP5
106   for (a = 0; a < 10; ++a) {
107     a += 1;
108   }
109 
110 
111   #pragma omp target teams distribute simd if(target: 1)
112   for (int i = 0; i < 10; ++i) {
113     aa += 1;
114   }
115 
116 
117 
118   #pragma omp target teams distribute simd if(target: n>10)
119   for (int i = 0; i < 10; ++i) {
120     a += 1;
121     aa += 1;
122   }
123 
124   // We capture 3 VLA sizes in this target region
125 
126 
127 
128 
129 
130   // The names below are not necessarily consistent with the names used for the
131   // addresses above as some are repeated.
132 
133 
134 
135 
136 
137 
138 
139 
140 
141 
142   #pragma omp target teams distribute simd if(target: n>20) aligned(b)
143   for (int i = 0; i < 10; ++i) {
144     a += 1;
145     b[2] += 1.0;
146     bn[3] += 1.0;
147     c[1][2] += 1.0;
148     cn[1][3] += 1.0;
149     d.X += 1;
150     d.Y += 1;
151   }
152 
153   return a;
154 }
155 
156 // Check that the offloading functions are emitted and that the arguments are
157 // correct and loaded correctly for the target regions in foo().
158 
159 
160 
161 
162 // Create stack storage and store argument in there.
163 
164 // Create stack storage and store argument in there.
165 
166 // Create stack storage and store argument in there.
167 
168 // Create local storage for each capture.
169 
170 
171 
172 // To reduce complexity, we're only going as far as validating the signature of the outlined parallel function.
173 
174 template<typename tx>
175 tx ftemplate(int n) {
176   tx a = 0;
177   short aa = 0;
178   tx b[10];
179 
180   #pragma omp target teams distribute simd if(target: n>40)
181   for (int i = 0; i < 10; ++i) {
182     a += 1;
183     aa += 1;
184     b[2] += 1;
185   }
186 
187   return a;
188 }
189 
190 static
191 int fstatic(int n) {
192   int a = 0;
193   short aa = 0;
194   char aaa = 0;
195   int b[10];
196 
197   #pragma omp target teams distribute simd if(target: n>50)
198   for (int i = a; i < n; ++i) {
199     a += 1;
200     aa += 1;
201     aaa += 1;
202     b[2] += 1;
203   }
204 
205   return a;
206 }
207 
208 struct S1 {
209   double a;
210 
211   int r1(int n){
212     int b = n+1;
213     short int c[2][n];
214 
215     #pragma omp target teams distribute simd if(n>60)
216     for (int i = 0; i < 10; ++i) {
217       this->a = (double)b + 1.5;
218       c[1][1] = ++a;
219     }
220 
221     return c[1][1] + (int)b;
222   }
223 };
224 
225 int bar(int n){
226   int a = 0;
227 
228   a += foo(n);
229 
230   S1 S;
231   a += S.r1(n);
232 
233   a += fstatic(n);
234 
235   a += ftemplate<int>(n);
236 
237   return a;
238 }
239 
240 
241 
242 // We capture 2 VLA sizes in this target region
243 
244 
245 // The names below are not necessarily consistent with the names used for the
246 // addresses above as some are repeated.
247 
248 
249 
250 
251 
252 
253 
254 
255 
256 
257 
258 
259 
260 
261 
262 
263 
264 
265 
266 
267 
268 
269 // Check that the offloading functions are emitted and that the arguments are
270 // correct and loaded correctly for the target regions of the callees of bar().
271 
272 // Create local storage for each capture.
273 // Store captures in the context.
274 
275 
276 // To reduce complexity, we're only going as far as validating the signature of the outlined parallel function.
277 
278 
279 // Create local storage for each capture.
280 // Store captures in the context.
281 
282 
283 
284 
285 // To reduce complexity, we're only going as far as validating the signature of the outlined parallel function.
286 
287 // Create local storage for each capture.
288 // Store captures in the context.
289 
290 
291 
292 // To reduce complexity, we're only going as far as validating the signature of the outlined parallel function.
293 
294 
295 #endif
296 // CHECK1-LABEL: define {{[^@]+}}@_Z3fooi
297 // CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0:[0-9]+]] {
298 // CHECK1-NEXT:  entry:
299 // CHECK1-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
300 // CHECK1-NEXT:    [[A:%.*]] = alloca i32, align 4
301 // CHECK1-NEXT:    [[AA:%.*]] = alloca i16, align 2
302 // CHECK1-NEXT:    [[B:%.*]] = alloca [10 x float], align 4
303 // CHECK1-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 8
304 // CHECK1-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
305 // CHECK1-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 8
306 // CHECK1-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i64, align 8
307 // CHECK1-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8
308 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
309 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
310 // CHECK1-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
311 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
312 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR__CASTED4:%.*]] = alloca i64, align 8
313 // CHECK1-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8
314 // CHECK1-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8
315 // CHECK1-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8
316 // CHECK1-NEXT:    [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4
317 // CHECK1-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
318 // CHECK1-NEXT:    [[AA_CASTED7:%.*]] = alloca i64, align 8
319 // CHECK1-NEXT:    [[DOTOFFLOAD_BASEPTRS9:%.*]] = alloca [1 x i8*], align 8
320 // CHECK1-NEXT:    [[DOTOFFLOAD_PTRS10:%.*]] = alloca [1 x i8*], align 8
321 // CHECK1-NEXT:    [[DOTOFFLOAD_MAPPERS11:%.*]] = alloca [1 x i8*], align 8
322 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
323 // CHECK1-NEXT:    [[A_CASTED12:%.*]] = alloca i64, align 8
324 // CHECK1-NEXT:    [[AA_CASTED14:%.*]] = alloca i64, align 8
325 // CHECK1-NEXT:    [[DOTOFFLOAD_BASEPTRS16:%.*]] = alloca [2 x i8*], align 8
326 // CHECK1-NEXT:    [[DOTOFFLOAD_PTRS17:%.*]] = alloca [2 x i8*], align 8
327 // CHECK1-NEXT:    [[DOTOFFLOAD_MAPPERS18:%.*]] = alloca [2 x i8*], align 8
328 // CHECK1-NEXT:    [[_TMP19:%.*]] = alloca i32, align 4
329 // CHECK1-NEXT:    [[A_CASTED23:%.*]] = alloca i64, align 8
330 // CHECK1-NEXT:    [[DOTOFFLOAD_BASEPTRS27:%.*]] = alloca [9 x i8*], align 8
331 // CHECK1-NEXT:    [[DOTOFFLOAD_PTRS28:%.*]] = alloca [9 x i8*], align 8
332 // CHECK1-NEXT:    [[DOTOFFLOAD_MAPPERS29:%.*]] = alloca [9 x i8*], align 8
333 // CHECK1-NEXT:    [[DOTOFFLOAD_SIZES:%.*]] = alloca [9 x i64], align 8
334 // CHECK1-NEXT:    [[_TMP30:%.*]] = alloca i32, align 4
335 // CHECK1-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]])
336 // CHECK1-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
337 // CHECK1-NEXT:    store i32 0, i32* [[A]], align 4
338 // CHECK1-NEXT:    store i16 0, i16* [[AA]], align 2
339 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
340 // CHECK1-NEXT:    [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
341 // CHECK1-NEXT:    [[TMP3:%.*]] = call i8* @llvm.stacksave()
342 // CHECK1-NEXT:    store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8
343 // CHECK1-NEXT:    [[VLA:%.*]] = alloca float, i64 [[TMP2]], align 4
344 // CHECK1-NEXT:    store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8
345 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
346 // CHECK1-NEXT:    [[TMP5:%.*]] = zext i32 [[TMP4]] to i64
347 // CHECK1-NEXT:    [[TMP6:%.*]] = mul nuw i64 5, [[TMP5]]
348 // CHECK1-NEXT:    [[VLA1:%.*]] = alloca double, i64 [[TMP6]], align 8
349 // CHECK1-NEXT:    store i64 [[TMP5]], i64* [[__VLA_EXPR1]], align 8
350 // CHECK1-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
351 // CHECK1-NEXT:    store i32 [[TMP7]], i32* [[DOTCAPTURE_EXPR_]], align 4
352 // CHECK1-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
353 // CHECK1-NEXT:    store i32 [[TMP8]], i32* [[DOTCAPTURE_EXPR_2]], align 4
354 // CHECK1-NEXT:    [[TMP9:%.*]] = load i16, i16* [[AA]], align 2
355 // CHECK1-NEXT:    [[CONV:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
356 // CHECK1-NEXT:    store i16 [[TMP9]], i16* [[CONV]], align 2
357 // CHECK1-NEXT:    [[TMP10:%.*]] = load i64, i64* [[AA_CASTED]], align 8
358 // CHECK1-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
359 // CHECK1-NEXT:    [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
360 // CHECK1-NEXT:    store i32 [[TMP11]], i32* [[CONV3]], align 4
361 // CHECK1-NEXT:    [[TMP12:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
362 // CHECK1-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
363 // CHECK1-NEXT:    [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED4]] to i32*
364 // CHECK1-NEXT:    store i32 [[TMP13]], i32* [[CONV5]], align 4
365 // CHECK1-NEXT:    [[TMP14:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED4]], align 8
366 // CHECK1-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
367 // CHECK1-NEXT:    [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i64*
368 // CHECK1-NEXT:    store i64 [[TMP10]], i64* [[TMP16]], align 8
369 // CHECK1-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
370 // CHECK1-NEXT:    [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64*
371 // CHECK1-NEXT:    store i64 [[TMP10]], i64* [[TMP18]], align 8
372 // CHECK1-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
373 // CHECK1-NEXT:    store i8* null, i8** [[TMP19]], align 8
374 // CHECK1-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
375 // CHECK1-NEXT:    [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i64*
376 // CHECK1-NEXT:    store i64 [[TMP12]], i64* [[TMP21]], align 8
377 // CHECK1-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
378 // CHECK1-NEXT:    [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i64*
379 // CHECK1-NEXT:    store i64 [[TMP12]], i64* [[TMP23]], align 8
380 // CHECK1-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
381 // CHECK1-NEXT:    store i8* null, i8** [[TMP24]], align 8
382 // CHECK1-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
383 // CHECK1-NEXT:    [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i64*
384 // CHECK1-NEXT:    store i64 [[TMP14]], i64* [[TMP26]], align 8
385 // CHECK1-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
386 // CHECK1-NEXT:    [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i64*
387 // CHECK1-NEXT:    store i64 [[TMP14]], i64* [[TMP28]], align 8
388 // CHECK1-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
389 // CHECK1-NEXT:    store i8* null, i8** [[TMP29]], align 8
390 // CHECK1-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
391 // CHECK1-NEXT:    [[TMP31:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
392 // CHECK1-NEXT:    [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 0
393 // CHECK1-NEXT:    [[TMP33:%.*]] = load i16, i16* [[AA]], align 2
394 // CHECK1-NEXT:    store i16 [[TMP33]], i16* [[TMP32]], align 4
395 // CHECK1-NEXT:    [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 1
396 // CHECK1-NEXT:    [[TMP35:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
397 // CHECK1-NEXT:    store i32 [[TMP35]], i32* [[TMP34]], align 4
398 // CHECK1-NEXT:    [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 2
399 // CHECK1-NEXT:    [[TMP37:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
400 // CHECK1-NEXT:    store i32 [[TMP37]], i32* [[TMP36]], align 4
401 // CHECK1-NEXT:    [[TMP38:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 1, i64 120, i64 12, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1)
402 // CHECK1-NEXT:    [[TMP39:%.*]] = bitcast i8* [[TMP38]] to %struct.kmp_task_t_with_privates*
403 // CHECK1-NEXT:    [[TMP40:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP39]], i32 0, i32 0
404 // CHECK1-NEXT:    [[TMP41:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP40]], i32 0, i32 0
405 // CHECK1-NEXT:    [[TMP42:%.*]] = load i8*, i8** [[TMP41]], align 8
406 // CHECK1-NEXT:    [[TMP43:%.*]] = bitcast %struct.anon* [[AGG_CAPTURED]] to i8*
407 // CHECK1-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP42]], i8* align 4 [[TMP43]], i64 12, i1 false)
408 // CHECK1-NEXT:    [[TMP44:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP39]], i32 0, i32 1
409 // CHECK1-NEXT:    [[TMP45:%.*]] = bitcast i8* [[TMP42]] to %struct.anon*
410 // CHECK1-NEXT:    [[TMP46:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 0
411 // CHECK1-NEXT:    [[TMP47:%.*]] = bitcast [3 x i8*]* [[TMP46]] to i8*
412 // CHECK1-NEXT:    [[TMP48:%.*]] = bitcast i8** [[TMP30]] to i8*
413 // CHECK1-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP47]], i8* align 8 [[TMP48]], i64 24, i1 false)
414 // CHECK1-NEXT:    [[TMP49:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 1
415 // CHECK1-NEXT:    [[TMP50:%.*]] = bitcast [3 x i8*]* [[TMP49]] to i8*
416 // CHECK1-NEXT:    [[TMP51:%.*]] = bitcast i8** [[TMP31]] to i8*
417 // CHECK1-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP50]], i8* align 8 [[TMP51]], i64 24, i1 false)
418 // CHECK1-NEXT:    [[TMP52:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 2
419 // CHECK1-NEXT:    [[TMP53:%.*]] = bitcast [3 x i64]* [[TMP52]] to i8*
420 // CHECK1-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP53]], i8* align 8 bitcast ([3 x i64]* @.offload_sizes to i8*), i64 24, i1 false)
421 // CHECK1-NEXT:    [[TMP54:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 3
422 // CHECK1-NEXT:    [[TMP55:%.*]] = load i16, i16* [[AA]], align 2
423 // CHECK1-NEXT:    store i16 [[TMP55]], i16* [[TMP54]], align 8
424 // CHECK1-NEXT:    [[TMP56:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i8* [[TMP38]])
425 // CHECK1-NEXT:    [[TMP57:%.*]] = load i32, i32* [[A]], align 4
426 // CHECK1-NEXT:    [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32*
427 // CHECK1-NEXT:    store i32 [[TMP57]], i32* [[CONV6]], align 4
428 // CHECK1-NEXT:    [[TMP58:%.*]] = load i64, i64* [[A_CASTED]], align 8
429 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104(i64 [[TMP58]]) #[[ATTR4:[0-9]+]]
430 // CHECK1-NEXT:    [[TMP59:%.*]] = load i16, i16* [[AA]], align 2
431 // CHECK1-NEXT:    [[CONV8:%.*]] = bitcast i64* [[AA_CASTED7]] to i16*
432 // CHECK1-NEXT:    store i16 [[TMP59]], i16* [[CONV8]], align 2
433 // CHECK1-NEXT:    [[TMP60:%.*]] = load i64, i64* [[AA_CASTED7]], align 8
434 // CHECK1-NEXT:    [[TMP61:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS9]], i32 0, i32 0
435 // CHECK1-NEXT:    [[TMP62:%.*]] = bitcast i8** [[TMP61]] to i64*
436 // CHECK1-NEXT:    store i64 [[TMP60]], i64* [[TMP62]], align 8
437 // CHECK1-NEXT:    [[TMP63:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS10]], i32 0, i32 0
438 // CHECK1-NEXT:    [[TMP64:%.*]] = bitcast i8** [[TMP63]] to i64*
439 // CHECK1-NEXT:    store i64 [[TMP60]], i64* [[TMP64]], align 8
440 // CHECK1-NEXT:    [[TMP65:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS11]], i64 0, i64 0
441 // CHECK1-NEXT:    store i8* null, i8** [[TMP65]], align 8
442 // CHECK1-NEXT:    [[TMP66:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS9]], i32 0, i32 0
443 // CHECK1-NEXT:    [[TMP67:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS10]], i32 0, i32 0
444 // CHECK1-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
445 // CHECK1-NEXT:    [[TMP68:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
446 // CHECK1-NEXT:    store i32 1, i32* [[TMP68]], align 4
447 // CHECK1-NEXT:    [[TMP69:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
448 // CHECK1-NEXT:    store i32 1, i32* [[TMP69]], align 4
449 // CHECK1-NEXT:    [[TMP70:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
450 // CHECK1-NEXT:    store i8** [[TMP66]], i8*** [[TMP70]], align 8
451 // CHECK1-NEXT:    [[TMP71:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
452 // CHECK1-NEXT:    store i8** [[TMP67]], i8*** [[TMP71]], align 8
453 // CHECK1-NEXT:    [[TMP72:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
454 // CHECK1-NEXT:    store i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.4, i32 0, i32 0), i64** [[TMP72]], align 8
455 // CHECK1-NEXT:    [[TMP73:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
456 // CHECK1-NEXT:    store i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.5, i32 0, i32 0), i64** [[TMP73]], align 8
457 // CHECK1-NEXT:    [[TMP74:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
458 // CHECK1-NEXT:    store i8** null, i8*** [[TMP74]], align 8
459 // CHECK1-NEXT:    [[TMP75:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
460 // CHECK1-NEXT:    store i8** null, i8*** [[TMP75]], align 8
461 // CHECK1-NEXT:    [[TMP76:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
462 // CHECK1-NEXT:    store i64 10, i64* [[TMP76]], align 8
463 // CHECK1-NEXT:    [[TMP77:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB2]], i64 -1, i32 0, i32 1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
464 // CHECK1-NEXT:    [[TMP78:%.*]] = icmp ne i32 [[TMP77]], 0
465 // CHECK1-NEXT:    br i1 [[TMP78]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
466 // CHECK1:       omp_offload.failed:
467 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111(i64 [[TMP60]]) #[[ATTR4]]
468 // CHECK1-NEXT:    br label [[OMP_OFFLOAD_CONT]]
469 // CHECK1:       omp_offload.cont:
470 // CHECK1-NEXT:    [[TMP79:%.*]] = load i32, i32* [[A]], align 4
471 // CHECK1-NEXT:    [[CONV13:%.*]] = bitcast i64* [[A_CASTED12]] to i32*
472 // CHECK1-NEXT:    store i32 [[TMP79]], i32* [[CONV13]], align 4
473 // CHECK1-NEXT:    [[TMP80:%.*]] = load i64, i64* [[A_CASTED12]], align 8
474 // CHECK1-NEXT:    [[TMP81:%.*]] = load i16, i16* [[AA]], align 2
475 // CHECK1-NEXT:    [[CONV15:%.*]] = bitcast i64* [[AA_CASTED14]] to i16*
476 // CHECK1-NEXT:    store i16 [[TMP81]], i16* [[CONV15]], align 2
477 // CHECK1-NEXT:    [[TMP82:%.*]] = load i64, i64* [[AA_CASTED14]], align 8
478 // CHECK1-NEXT:    [[TMP83:%.*]] = load i32, i32* [[N_ADDR]], align 4
479 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP83]], 10
480 // CHECK1-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
481 // CHECK1:       omp_if.then:
482 // CHECK1-NEXT:    [[TMP84:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 0
483 // CHECK1-NEXT:    [[TMP85:%.*]] = bitcast i8** [[TMP84]] to i64*
484 // CHECK1-NEXT:    store i64 [[TMP80]], i64* [[TMP85]], align 8
485 // CHECK1-NEXT:    [[TMP86:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 0
486 // CHECK1-NEXT:    [[TMP87:%.*]] = bitcast i8** [[TMP86]] to i64*
487 // CHECK1-NEXT:    store i64 [[TMP80]], i64* [[TMP87]], align 8
488 // CHECK1-NEXT:    [[TMP88:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 0
489 // CHECK1-NEXT:    store i8* null, i8** [[TMP88]], align 8
490 // CHECK1-NEXT:    [[TMP89:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 1
491 // CHECK1-NEXT:    [[TMP90:%.*]] = bitcast i8** [[TMP89]] to i64*
492 // CHECK1-NEXT:    store i64 [[TMP82]], i64* [[TMP90]], align 8
493 // CHECK1-NEXT:    [[TMP91:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 1
494 // CHECK1-NEXT:    [[TMP92:%.*]] = bitcast i8** [[TMP91]] to i64*
495 // CHECK1-NEXT:    store i64 [[TMP82]], i64* [[TMP92]], align 8
496 // CHECK1-NEXT:    [[TMP93:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 1
497 // CHECK1-NEXT:    store i8* null, i8** [[TMP93]], align 8
498 // CHECK1-NEXT:    [[TMP94:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 0
499 // CHECK1-NEXT:    [[TMP95:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 0
500 // CHECK1-NEXT:    [[KERNEL_ARGS20:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
501 // CHECK1-NEXT:    [[TMP96:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS20]], i32 0, i32 0
502 // CHECK1-NEXT:    store i32 1, i32* [[TMP96]], align 4
503 // CHECK1-NEXT:    [[TMP97:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS20]], i32 0, i32 1
504 // CHECK1-NEXT:    store i32 2, i32* [[TMP97]], align 4
505 // CHECK1-NEXT:    [[TMP98:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS20]], i32 0, i32 2
506 // CHECK1-NEXT:    store i8** [[TMP94]], i8*** [[TMP98]], align 8
507 // CHECK1-NEXT:    [[TMP99:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS20]], i32 0, i32 3
508 // CHECK1-NEXT:    store i8** [[TMP95]], i8*** [[TMP99]], align 8
509 // CHECK1-NEXT:    [[TMP100:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS20]], i32 0, i32 4
510 // CHECK1-NEXT:    store i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.7, i32 0, i32 0), i64** [[TMP100]], align 8
511 // CHECK1-NEXT:    [[TMP101:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS20]], i32 0, i32 5
512 // CHECK1-NEXT:    store i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.8, i32 0, i32 0), i64** [[TMP101]], align 8
513 // CHECK1-NEXT:    [[TMP102:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS20]], i32 0, i32 6
514 // CHECK1-NEXT:    store i8** null, i8*** [[TMP102]], align 8
515 // CHECK1-NEXT:    [[TMP103:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS20]], i32 0, i32 7
516 // CHECK1-NEXT:    store i8** null, i8*** [[TMP103]], align 8
517 // CHECK1-NEXT:    [[TMP104:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS20]], i32 0, i32 8
518 // CHECK1-NEXT:    store i64 10, i64* [[TMP104]], align 8
519 // CHECK1-NEXT:    [[TMP105:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB2]], i64 -1, i32 0, i32 1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS20]])
520 // CHECK1-NEXT:    [[TMP106:%.*]] = icmp ne i32 [[TMP105]], 0
521 // CHECK1-NEXT:    br i1 [[TMP106]], label [[OMP_OFFLOAD_FAILED21:%.*]], label [[OMP_OFFLOAD_CONT22:%.*]]
522 // CHECK1:       omp_offload.failed21:
523 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i64 [[TMP80]], i64 [[TMP82]]) #[[ATTR4]]
524 // CHECK1-NEXT:    br label [[OMP_OFFLOAD_CONT22]]
525 // CHECK1:       omp_offload.cont22:
526 // CHECK1-NEXT:    br label [[OMP_IF_END:%.*]]
527 // CHECK1:       omp_if.else:
528 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i64 [[TMP80]], i64 [[TMP82]]) #[[ATTR4]]
529 // CHECK1-NEXT:    br label [[OMP_IF_END]]
530 // CHECK1:       omp_if.end:
531 // CHECK1-NEXT:    [[TMP107:%.*]] = load i32, i32* [[A]], align 4
532 // CHECK1-NEXT:    [[CONV24:%.*]] = bitcast i64* [[A_CASTED23]] to i32*
533 // CHECK1-NEXT:    store i32 [[TMP107]], i32* [[CONV24]], align 4
534 // CHECK1-NEXT:    [[TMP108:%.*]] = load i64, i64* [[A_CASTED23]], align 8
535 // CHECK1-NEXT:    [[TMP109:%.*]] = load i32, i32* [[N_ADDR]], align 4
536 // CHECK1-NEXT:    [[CMP25:%.*]] = icmp sgt i32 [[TMP109]], 20
537 // CHECK1-NEXT:    br i1 [[CMP25]], label [[OMP_IF_THEN26:%.*]], label [[OMP_IF_ELSE34:%.*]]
538 // CHECK1:       omp_if.then26:
539 // CHECK1-NEXT:    [[TMP110:%.*]] = mul nuw i64 [[TMP2]], 4
540 // CHECK1-NEXT:    [[TMP111:%.*]] = mul nuw i64 5, [[TMP5]]
541 // CHECK1-NEXT:    [[TMP112:%.*]] = mul nuw i64 [[TMP111]], 8
542 // CHECK1-NEXT:    [[TMP113:%.*]] = bitcast [9 x i64]* [[DOTOFFLOAD_SIZES]] to i8*
543 // CHECK1-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP113]], i8* align 8 bitcast ([9 x i64]* @.offload_sizes.10 to i8*), i64 72, i1 false)
544 // CHECK1-NEXT:    [[TMP114:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS27]], i32 0, i32 0
545 // CHECK1-NEXT:    [[TMP115:%.*]] = bitcast i8** [[TMP114]] to i64*
546 // CHECK1-NEXT:    store i64 [[TMP108]], i64* [[TMP115]], align 8
547 // CHECK1-NEXT:    [[TMP116:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS28]], i32 0, i32 0
548 // CHECK1-NEXT:    [[TMP117:%.*]] = bitcast i8** [[TMP116]] to i64*
549 // CHECK1-NEXT:    store i64 [[TMP108]], i64* [[TMP117]], align 8
550 // CHECK1-NEXT:    [[TMP118:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS29]], i64 0, i64 0
551 // CHECK1-NEXT:    store i8* null, i8** [[TMP118]], align 8
552 // CHECK1-NEXT:    [[TMP119:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS27]], i32 0, i32 1
553 // CHECK1-NEXT:    [[TMP120:%.*]] = bitcast i8** [[TMP119]] to [10 x float]**
554 // CHECK1-NEXT:    store [10 x float]* [[B]], [10 x float]** [[TMP120]], align 8
555 // CHECK1-NEXT:    [[TMP121:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS28]], i32 0, i32 1
556 // CHECK1-NEXT:    [[TMP122:%.*]] = bitcast i8** [[TMP121]] to [10 x float]**
557 // CHECK1-NEXT:    store [10 x float]* [[B]], [10 x float]** [[TMP122]], align 8
558 // CHECK1-NEXT:    [[TMP123:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS29]], i64 0, i64 1
559 // CHECK1-NEXT:    store i8* null, i8** [[TMP123]], align 8
560 // CHECK1-NEXT:    [[TMP124:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS27]], i32 0, i32 2
561 // CHECK1-NEXT:    [[TMP125:%.*]] = bitcast i8** [[TMP124]] to i64*
562 // CHECK1-NEXT:    store i64 [[TMP2]], i64* [[TMP125]], align 8
563 // CHECK1-NEXT:    [[TMP126:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS28]], i32 0, i32 2
564 // CHECK1-NEXT:    [[TMP127:%.*]] = bitcast i8** [[TMP126]] to i64*
565 // CHECK1-NEXT:    store i64 [[TMP2]], i64* [[TMP127]], align 8
566 // CHECK1-NEXT:    [[TMP128:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS29]], i64 0, i64 2
567 // CHECK1-NEXT:    store i8* null, i8** [[TMP128]], align 8
568 // CHECK1-NEXT:    [[TMP129:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS27]], i32 0, i32 3
569 // CHECK1-NEXT:    [[TMP130:%.*]] = bitcast i8** [[TMP129]] to float**
570 // CHECK1-NEXT:    store float* [[VLA]], float** [[TMP130]], align 8
571 // CHECK1-NEXT:    [[TMP131:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS28]], i32 0, i32 3
572 // CHECK1-NEXT:    [[TMP132:%.*]] = bitcast i8** [[TMP131]] to float**
573 // CHECK1-NEXT:    store float* [[VLA]], float** [[TMP132]], align 8
574 // CHECK1-NEXT:    [[TMP133:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3
575 // CHECK1-NEXT:    store i64 [[TMP110]], i64* [[TMP133]], align 8
576 // CHECK1-NEXT:    [[TMP134:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS29]], i64 0, i64 3
577 // CHECK1-NEXT:    store i8* null, i8** [[TMP134]], align 8
578 // CHECK1-NEXT:    [[TMP135:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS27]], i32 0, i32 4
579 // CHECK1-NEXT:    [[TMP136:%.*]] = bitcast i8** [[TMP135]] to [5 x [10 x double]]**
580 // CHECK1-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP136]], align 8
581 // CHECK1-NEXT:    [[TMP137:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS28]], i32 0, i32 4
582 // CHECK1-NEXT:    [[TMP138:%.*]] = bitcast i8** [[TMP137]] to [5 x [10 x double]]**
583 // CHECK1-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP138]], align 8
584 // CHECK1-NEXT:    [[TMP139:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS29]], i64 0, i64 4
585 // CHECK1-NEXT:    store i8* null, i8** [[TMP139]], align 8
586 // CHECK1-NEXT:    [[TMP140:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS27]], i32 0, i32 5
587 // CHECK1-NEXT:    [[TMP141:%.*]] = bitcast i8** [[TMP140]] to i64*
588 // CHECK1-NEXT:    store i64 5, i64* [[TMP141]], align 8
589 // CHECK1-NEXT:    [[TMP142:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS28]], i32 0, i32 5
590 // CHECK1-NEXT:    [[TMP143:%.*]] = bitcast i8** [[TMP142]] to i64*
591 // CHECK1-NEXT:    store i64 5, i64* [[TMP143]], align 8
592 // CHECK1-NEXT:    [[TMP144:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS29]], i64 0, i64 5
593 // CHECK1-NEXT:    store i8* null, i8** [[TMP144]], align 8
594 // CHECK1-NEXT:    [[TMP145:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS27]], i32 0, i32 6
595 // CHECK1-NEXT:    [[TMP146:%.*]] = bitcast i8** [[TMP145]] to i64*
596 // CHECK1-NEXT:    store i64 [[TMP5]], i64* [[TMP146]], align 8
597 // CHECK1-NEXT:    [[TMP147:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS28]], i32 0, i32 6
598 // CHECK1-NEXT:    [[TMP148:%.*]] = bitcast i8** [[TMP147]] to i64*
599 // CHECK1-NEXT:    store i64 [[TMP5]], i64* [[TMP148]], align 8
600 // CHECK1-NEXT:    [[TMP149:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS29]], i64 0, i64 6
601 // CHECK1-NEXT:    store i8* null, i8** [[TMP149]], align 8
602 // CHECK1-NEXT:    [[TMP150:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS27]], i32 0, i32 7
603 // CHECK1-NEXT:    [[TMP151:%.*]] = bitcast i8** [[TMP150]] to double**
604 // CHECK1-NEXT:    store double* [[VLA1]], double** [[TMP151]], align 8
605 // CHECK1-NEXT:    [[TMP152:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS28]], i32 0, i32 7
606 // CHECK1-NEXT:    [[TMP153:%.*]] = bitcast i8** [[TMP152]] to double**
607 // CHECK1-NEXT:    store double* [[VLA1]], double** [[TMP153]], align 8
608 // CHECK1-NEXT:    [[TMP154:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7
609 // CHECK1-NEXT:    store i64 [[TMP112]], i64* [[TMP154]], align 8
610 // CHECK1-NEXT:    [[TMP155:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS29]], i64 0, i64 7
611 // CHECK1-NEXT:    store i8* null, i8** [[TMP155]], align 8
612 // CHECK1-NEXT:    [[TMP156:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS27]], i32 0, i32 8
613 // CHECK1-NEXT:    [[TMP157:%.*]] = bitcast i8** [[TMP156]] to %struct.TT**
614 // CHECK1-NEXT:    store %struct.TT* [[D]], %struct.TT** [[TMP157]], align 8
615 // CHECK1-NEXT:    [[TMP158:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS28]], i32 0, i32 8
616 // CHECK1-NEXT:    [[TMP159:%.*]] = bitcast i8** [[TMP158]] to %struct.TT**
617 // CHECK1-NEXT:    store %struct.TT* [[D]], %struct.TT** [[TMP159]], align 8
618 // CHECK1-NEXT:    [[TMP160:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS29]], i64 0, i64 8
619 // CHECK1-NEXT:    store i8* null, i8** [[TMP160]], align 8
620 // CHECK1-NEXT:    [[TMP161:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS27]], i32 0, i32 0
621 // CHECK1-NEXT:    [[TMP162:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS28]], i32 0, i32 0
622 // CHECK1-NEXT:    [[TMP163:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
623 // CHECK1-NEXT:    [[KERNEL_ARGS31:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
624 // CHECK1-NEXT:    [[TMP164:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS31]], i32 0, i32 0
625 // CHECK1-NEXT:    store i32 1, i32* [[TMP164]], align 4
626 // CHECK1-NEXT:    [[TMP165:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS31]], i32 0, i32 1
627 // CHECK1-NEXT:    store i32 9, i32* [[TMP165]], align 4
628 // CHECK1-NEXT:    [[TMP166:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS31]], i32 0, i32 2
629 // CHECK1-NEXT:    store i8** [[TMP161]], i8*** [[TMP166]], align 8
630 // CHECK1-NEXT:    [[TMP167:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS31]], i32 0, i32 3
631 // CHECK1-NEXT:    store i8** [[TMP162]], i8*** [[TMP167]], align 8
632 // CHECK1-NEXT:    [[TMP168:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS31]], i32 0, i32 4
633 // CHECK1-NEXT:    store i64* [[TMP163]], i64** [[TMP168]], align 8
634 // CHECK1-NEXT:    [[TMP169:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS31]], i32 0, i32 5
635 // CHECK1-NEXT:    store i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_maptypes.11, i32 0, i32 0), i64** [[TMP169]], align 8
636 // CHECK1-NEXT:    [[TMP170:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS31]], i32 0, i32 6
637 // CHECK1-NEXT:    store i8** null, i8*** [[TMP170]], align 8
638 // CHECK1-NEXT:    [[TMP171:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS31]], i32 0, i32 7
639 // CHECK1-NEXT:    store i8** null, i8*** [[TMP171]], align 8
640 // CHECK1-NEXT:    [[TMP172:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS31]], i32 0, i32 8
641 // CHECK1-NEXT:    store i64 10, i64* [[TMP172]], align 8
642 // CHECK1-NEXT:    [[TMP173:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB2]], i64 -1, i32 0, i32 1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS31]])
643 // CHECK1-NEXT:    [[TMP174:%.*]] = icmp ne i32 [[TMP173]], 0
644 // CHECK1-NEXT:    br i1 [[TMP174]], label [[OMP_OFFLOAD_FAILED32:%.*]], label [[OMP_OFFLOAD_CONT33:%.*]]
645 // CHECK1:       omp_offload.failed32:
646 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i64 [[TMP108]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR4]]
647 // CHECK1-NEXT:    br label [[OMP_OFFLOAD_CONT33]]
648 // CHECK1:       omp_offload.cont33:
649 // CHECK1-NEXT:    br label [[OMP_IF_END35:%.*]]
650 // CHECK1:       omp_if.else34:
651 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i64 [[TMP108]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR4]]
652 // CHECK1-NEXT:    br label [[OMP_IF_END35]]
653 // CHECK1:       omp_if.end35:
654 // CHECK1-NEXT:    [[TMP175:%.*]] = load i32, i32* [[A]], align 4
655 // CHECK1-NEXT:    [[TMP176:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
656 // CHECK1-NEXT:    call void @llvm.stackrestore(i8* [[TMP176]])
657 // CHECK1-NEXT:    ret i32 [[TMP175]]
658 //
659 //
660 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97
661 // CHECK1-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] {
662 // CHECK1-NEXT:  entry:
663 // CHECK1-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
664 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
665 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8
666 // CHECK1-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
667 // CHECK1-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]])
668 // CHECK1-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
669 // CHECK1-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
670 // CHECK1-NEXT:    store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8
671 // CHECK1-NEXT:    [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
672 // CHECK1-NEXT:    [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
673 // CHECK1-NEXT:    [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32*
674 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 4
675 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 4
676 // CHECK1-NEXT:    call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
677 // CHECK1-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
678 // CHECK1-NEXT:    [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
679 // CHECK1-NEXT:    store i16 [[TMP3]], i16* [[CONV5]], align 2
680 // CHECK1-NEXT:    [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
681 // CHECK1-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]])
682 // CHECK1-NEXT:    ret void
683 //
684 //
685 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined.
686 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR3:[0-9]+]] {
687 // CHECK1-NEXT:  entry:
688 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
689 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
690 // CHECK1-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
691 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
692 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
693 // CHECK1-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
694 // CHECK1-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
695 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
696 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
697 // CHECK1-NEXT:    [[I:%.*]] = alloca i32, align 4
698 // CHECK1-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
699 // CHECK1-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
700 // CHECK1-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
701 // CHECK1-NEXT:    [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
702 // CHECK1-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
703 // CHECK1-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
704 // CHECK1-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
705 // CHECK1-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
706 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
707 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
708 // CHECK1-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
709 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
710 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
711 // CHECK1-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
712 // CHECK1:       cond.true:
713 // CHECK1-NEXT:    br label [[COND_END:%.*]]
714 // CHECK1:       cond.false:
715 // CHECK1-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
716 // CHECK1-NEXT:    br label [[COND_END]]
717 // CHECK1:       cond.end:
718 // CHECK1-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
719 // CHECK1-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
720 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
721 // CHECK1-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
722 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
723 // CHECK1:       omp.inner.for.cond:
724 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
725 // CHECK1-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !10
726 // CHECK1-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
727 // CHECK1-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
728 // CHECK1:       omp.inner.for.body:
729 // CHECK1-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
730 // CHECK1-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
731 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
732 // CHECK1-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10
733 // CHECK1-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
734 // CHECK1:       omp.body.continue:
735 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
736 // CHECK1:       omp.inner.for.inc:
737 // CHECK1-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
738 // CHECK1-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
739 // CHECK1-NEXT:    store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
740 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]
741 // CHECK1:       omp.inner.for.end:
742 // CHECK1-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
743 // CHECK1:       omp.loop.exit:
744 // CHECK1-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
745 // CHECK1-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
746 // CHECK1-NEXT:    [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0
747 // CHECK1-NEXT:    br i1 [[TMP10]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
748 // CHECK1:       .omp.final.then:
749 // CHECK1-NEXT:    store i32 10, i32* [[I]], align 4
750 // CHECK1-NEXT:    br label [[DOTOMP_FINAL_DONE]]
751 // CHECK1:       .omp.final.done:
752 // CHECK1-NEXT:    ret void
753 //
754 //
755 // CHECK1-LABEL: define {{[^@]+}}@.omp_task_privates_map.
756 // CHECK1-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], i16** noalias noundef [[TMP1:%.*]], [3 x i8*]** noalias noundef [[TMP2:%.*]], [3 x i8*]** noalias noundef [[TMP3:%.*]], [3 x i64]** noalias noundef [[TMP4:%.*]]) #[[ATTR5:[0-9]+]] {
757 // CHECK1-NEXT:  entry:
758 // CHECK1-NEXT:    [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 8
759 // CHECK1-NEXT:    [[DOTADDR1:%.*]] = alloca i16**, align 8
760 // CHECK1-NEXT:    [[DOTADDR2:%.*]] = alloca [3 x i8*]**, align 8
761 // CHECK1-NEXT:    [[DOTADDR3:%.*]] = alloca [3 x i8*]**, align 8
762 // CHECK1-NEXT:    [[DOTADDR4:%.*]] = alloca [3 x i64]**, align 8
763 // CHECK1-NEXT:    store %struct..kmp_privates.t* [[TMP0]], %struct..kmp_privates.t** [[DOTADDR]], align 8
764 // CHECK1-NEXT:    store i16** [[TMP1]], i16*** [[DOTADDR1]], align 8
765 // CHECK1-NEXT:    store [3 x i8*]** [[TMP2]], [3 x i8*]*** [[DOTADDR2]], align 8
766 // CHECK1-NEXT:    store [3 x i8*]** [[TMP3]], [3 x i8*]*** [[DOTADDR3]], align 8
767 // CHECK1-NEXT:    store [3 x i64]** [[TMP4]], [3 x i64]*** [[DOTADDR4]], align 8
768 // CHECK1-NEXT:    [[TMP5:%.*]] = load %struct..kmp_privates.t*, %struct..kmp_privates.t** [[DOTADDR]], align 8
769 // CHECK1-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 0
770 // CHECK1-NEXT:    [[TMP7:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR2]], align 8
771 // CHECK1-NEXT:    store [3 x i8*]* [[TMP6]], [3 x i8*]** [[TMP7]], align 8
772 // CHECK1-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 1
773 // CHECK1-NEXT:    [[TMP9:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR3]], align 8
774 // CHECK1-NEXT:    store [3 x i8*]* [[TMP8]], [3 x i8*]** [[TMP9]], align 8
775 // CHECK1-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 2
776 // CHECK1-NEXT:    [[TMP11:%.*]] = load [3 x i64]**, [3 x i64]*** [[DOTADDR4]], align 8
777 // CHECK1-NEXT:    store [3 x i64]* [[TMP10]], [3 x i64]** [[TMP11]], align 8
778 // CHECK1-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 3
779 // CHECK1-NEXT:    [[TMP13:%.*]] = load i16**, i16*** [[DOTADDR1]], align 8
780 // CHECK1-NEXT:    store i16* [[TMP12]], i16** [[TMP13]], align 8
781 // CHECK1-NEXT:    ret void
782 //
783 //
784 // CHECK1-LABEL: define {{[^@]+}}@.omp_task_entry.
785 // CHECK1-SAME: (i32 noundef signext [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] {
786 // CHECK1-NEXT:  entry:
787 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
788 // CHECK1-NEXT:    [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8
789 // CHECK1-NEXT:    [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8
790 // CHECK1-NEXT:    [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8
791 // CHECK1-NEXT:    [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8
792 // CHECK1-NEXT:    [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 8
793 // CHECK1-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca i16*, align 8
794 // CHECK1-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca [3 x i8*]*, align 8
795 // CHECK1-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca [3 x i8*]*, align 8
796 // CHECK1-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca [3 x i64]*, align 8
797 // CHECK1-NEXT:    [[AA_CASTED_I:%.*]] = alloca i64, align 8
798 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR__CASTED_I:%.*]] = alloca i64, align 8
799 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR__CASTED5_I:%.*]] = alloca i64, align 8
800 // CHECK1-NEXT:    [[KERNEL_ARGS_I:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
801 // CHECK1-NEXT:    [[DOTADDR:%.*]] = alloca i32, align 4
802 // CHECK1-NEXT:    [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8
803 // CHECK1-NEXT:    store i32 [[TMP0]], i32* [[DOTADDR]], align 4
804 // CHECK1-NEXT:    store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8
805 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4
806 // CHECK1-NEXT:    [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8
807 // CHECK1-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
808 // CHECK1-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
809 // CHECK1-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0
810 // CHECK1-NEXT:    [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8
811 // CHECK1-NEXT:    [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon*
812 // CHECK1-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1
813 // CHECK1-NEXT:    [[TMP10:%.*]] = bitcast %struct..kmp_privates.t* [[TMP9]] to i8*
814 // CHECK1-NEXT:    [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8*
815 // CHECK1-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META17:![0-9]+]])
816 // CHECK1-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]])
817 // CHECK1-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META22:![0-9]+]])
818 // CHECK1-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META24:![0-9]+]])
819 // CHECK1-NEXT:    store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !26
820 // CHECK1-NEXT:    store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !26
821 // CHECK1-NEXT:    store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !26
822 // CHECK1-NEXT:    store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* @.omp_task_privates_map. to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !26
823 // CHECK1-NEXT:    store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !26
824 // CHECK1-NEXT:    store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !26
825 // CHECK1-NEXT:    [[TMP12:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !26
826 // CHECK1-NEXT:    [[TMP13:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !26
827 // CHECK1-NEXT:    [[TMP14:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !26
828 // CHECK1-NEXT:    [[TMP15:%.*]] = bitcast void (i8*, ...)* [[TMP13]] to void (i8*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)*
829 // CHECK1-NEXT:    call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR4]]
830 // CHECK1-NEXT:    [[TMP16:%.*]] = load i16*, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !26
831 // CHECK1-NEXT:    [[TMP17:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !26
832 // CHECK1-NEXT:    [[TMP18:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 8, !noalias !26
833 // CHECK1-NEXT:    [[TMP19:%.*]] = load [3 x i64]*, [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 8, !noalias !26
834 // CHECK1-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP17]], i64 0, i64 0
835 // CHECK1-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP18]], i64 0, i64 0
836 // CHECK1-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[TMP19]], i64 0, i64 0
837 // CHECK1-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP12]], i32 0, i32 1
838 // CHECK1-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[TMP12]], i32 0, i32 2
839 // CHECK1-NEXT:    [[TMP25:%.*]] = load i32, i32* [[TMP23]], align 4
840 // CHECK1-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i32 0
841 // CHECK1-NEXT:    store i32 1, i32* [[TMP26]], align 4, !noalias !26
842 // CHECK1-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i32 1
843 // CHECK1-NEXT:    store i32 3, i32* [[TMP27]], align 4, !noalias !26
844 // CHECK1-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i32 2
845 // CHECK1-NEXT:    store i8** [[TMP20]], i8*** [[TMP28]], align 8, !noalias !26
846 // CHECK1-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i32 3
847 // CHECK1-NEXT:    store i8** [[TMP21]], i8*** [[TMP29]], align 8, !noalias !26
848 // CHECK1-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i32 4
849 // CHECK1-NEXT:    store i64* [[TMP22]], i64** [[TMP30]], align 8, !noalias !26
850 // CHECK1-NEXT:    [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i32 5
851 // CHECK1-NEXT:    store i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i64** [[TMP31]], align 8, !noalias !26
852 // CHECK1-NEXT:    [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i32 6
853 // CHECK1-NEXT:    store i8** null, i8*** [[TMP32]], align 8, !noalias !26
854 // CHECK1-NEXT:    [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i32 7
855 // CHECK1-NEXT:    store i8** null, i8*** [[TMP33]], align 8, !noalias !26
856 // CHECK1-NEXT:    [[TMP34:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i32 8
857 // CHECK1-NEXT:    store i64 10, i64* [[TMP34]], align 8, !noalias !26
858 // CHECK1-NEXT:    [[TMP35:%.*]] = call i32 @__tgt_target_kernel_nowait(%struct.ident_t* @[[GLOB2]], i64 -1, i32 [[TMP25]], i32 1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i8* null, i32 0, i8* null) #[[ATTR4]]
859 // CHECK1-NEXT:    [[TMP36:%.*]] = icmp ne i32 [[TMP35]], 0
860 // CHECK1-NEXT:    br i1 [[TMP36]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]]
861 // CHECK1:       omp_offload.failed.i:
862 // CHECK1-NEXT:    [[TMP37:%.*]] = load i16, i16* [[TMP16]], align 2
863 // CHECK1-NEXT:    [[CONV_I:%.*]] = bitcast i64* [[AA_CASTED_I]] to i16*
864 // CHECK1-NEXT:    store i16 [[TMP37]], i16* [[CONV_I]], align 2, !noalias !26
865 // CHECK1-NEXT:    [[TMP38:%.*]] = load i64, i64* [[AA_CASTED_I]], align 8, !noalias !26
866 // CHECK1-NEXT:    [[TMP39:%.*]] = load i32, i32* [[TMP23]], align 4
867 // CHECK1-NEXT:    [[CONV4_I:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED_I]] to i32*
868 // CHECK1-NEXT:    store i32 [[TMP39]], i32* [[CONV4_I]], align 4, !noalias !26
869 // CHECK1-NEXT:    [[TMP40:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED_I]], align 8, !noalias !26
870 // CHECK1-NEXT:    [[TMP41:%.*]] = load i32, i32* [[TMP24]], align 4
871 // CHECK1-NEXT:    [[CONV6_I:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED5_I]] to i32*
872 // CHECK1-NEXT:    store i32 [[TMP41]], i32* [[CONV6_I]], align 4, !noalias !26
873 // CHECK1-NEXT:    [[TMP42:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED5_I]], align 8, !noalias !26
874 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97(i64 [[TMP38]], i64 [[TMP40]], i64 [[TMP42]]) #[[ATTR4]]
875 // CHECK1-NEXT:    br label [[DOTOMP_OUTLINED__1_EXIT]]
876 // CHECK1:       .omp_outlined..1.exit:
877 // CHECK1-NEXT:    ret i32 0
878 //
879 //
880 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104
881 // CHECK1-SAME: (i64 noundef [[A:%.*]]) #[[ATTR3]] {
882 // CHECK1-NEXT:  entry:
883 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
884 // CHECK1-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
885 // CHECK1-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
886 // CHECK1-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
887 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
888 // CHECK1-NEXT:    [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32*
889 // CHECK1-NEXT:    store i32 [[TMP0]], i32* [[CONV1]], align 4
890 // CHECK1-NEXT:    [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
891 // CHECK1-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]])
892 // CHECK1-NEXT:    ret void
893 //
894 //
895 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..2
896 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]]) #[[ATTR3]] {
897 // CHECK1-NEXT:  entry:
898 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
899 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
900 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
901 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
902 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
903 // CHECK1-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
904 // CHECK1-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
905 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
906 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
907 // CHECK1-NEXT:    [[A1:%.*]] = alloca i32, align 4
908 // CHECK1-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
909 // CHECK1-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
910 // CHECK1-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
911 // CHECK1-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
912 // CHECK1-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
913 // CHECK1-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
914 // CHECK1-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
915 // CHECK1-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
916 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
917 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
918 // CHECK1-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
919 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
920 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
921 // CHECK1-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
922 // CHECK1:       cond.true:
923 // CHECK1-NEXT:    br label [[COND_END:%.*]]
924 // CHECK1:       cond.false:
925 // CHECK1-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
926 // CHECK1-NEXT:    br label [[COND_END]]
927 // CHECK1:       cond.end:
928 // CHECK1-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
929 // CHECK1-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
930 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
931 // CHECK1-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
932 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
933 // CHECK1:       omp.inner.for.cond:
934 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
935 // CHECK1-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
936 // CHECK1-NEXT:    [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
937 // CHECK1-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
938 // CHECK1:       omp.inner.for.body:
939 // CHECK1-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
940 // CHECK1-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
941 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
942 // CHECK1-NEXT:    store i32 [[ADD]], i32* [[A1]], align 4
943 // CHECK1-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A1]], align 4
944 // CHECK1-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
945 // CHECK1-NEXT:    store i32 [[ADD3]], i32* [[A1]], align 4
946 // CHECK1-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
947 // CHECK1:       omp.body.continue:
948 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
949 // CHECK1:       omp.inner.for.inc:
950 // CHECK1-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
951 // CHECK1-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP9]], 1
952 // CHECK1-NEXT:    store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4
953 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP27:![0-9]+]]
954 // CHECK1:       omp.inner.for.end:
955 // CHECK1-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
956 // CHECK1:       omp.loop.exit:
957 // CHECK1-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
958 // CHECK1-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
959 // CHECK1-NEXT:    [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0
960 // CHECK1-NEXT:    br i1 [[TMP11]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
961 // CHECK1:       .omp.final.then:
962 // CHECK1-NEXT:    store i32 10, i32* [[CONV]], align 4
963 // CHECK1-NEXT:    br label [[DOTOMP_FINAL_DONE]]
964 // CHECK1:       .omp.final.done:
965 // CHECK1-NEXT:    ret void
966 //
967 //
968 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111
969 // CHECK1-SAME: (i64 noundef [[AA:%.*]]) #[[ATTR2]] {
970 // CHECK1-NEXT:  entry:
971 // CHECK1-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
972 // CHECK1-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
973 // CHECK1-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
974 // CHECK1-NEXT:    [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
975 // CHECK1-NEXT:    [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
976 // CHECK1-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
977 // CHECK1-NEXT:    store i16 [[TMP0]], i16* [[CONV1]], align 2
978 // CHECK1-NEXT:    [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
979 // CHECK1-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP1]])
980 // CHECK1-NEXT:    ret void
981 //
982 //
983 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..3
984 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR3]] {
985 // CHECK1-NEXT:  entry:
986 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
987 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
988 // CHECK1-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
989 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
990 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
991 // CHECK1-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
992 // CHECK1-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
993 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
994 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
995 // CHECK1-NEXT:    [[I:%.*]] = alloca i32, align 4
996 // CHECK1-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
997 // CHECK1-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
998 // CHECK1-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
999 // CHECK1-NEXT:    [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
1000 // CHECK1-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
1001 // CHECK1-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
1002 // CHECK1-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
1003 // CHECK1-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
1004 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
1005 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
1006 // CHECK1-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
1007 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1008 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
1009 // CHECK1-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1010 // CHECK1:       cond.true:
1011 // CHECK1-NEXT:    br label [[COND_END:%.*]]
1012 // CHECK1:       cond.false:
1013 // CHECK1-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1014 // CHECK1-NEXT:    br label [[COND_END]]
1015 // CHECK1:       cond.end:
1016 // CHECK1-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
1017 // CHECK1-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
1018 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
1019 // CHECK1-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
1020 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
1021 // CHECK1:       omp.inner.for.cond:
1022 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !29
1023 // CHECK1-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !29
1024 // CHECK1-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
1025 // CHECK1-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1026 // CHECK1:       omp.inner.for.body:
1027 // CHECK1-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !29
1028 // CHECK1-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
1029 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1030 // CHECK1-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !29
1031 // CHECK1-NEXT:    [[TMP8:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !29
1032 // CHECK1-NEXT:    [[CONV2:%.*]] = sext i16 [[TMP8]] to i32
1033 // CHECK1-NEXT:    [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
1034 // CHECK1-NEXT:    [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
1035 // CHECK1-NEXT:    store i16 [[CONV4]], i16* [[CONV]], align 2, !llvm.access.group !29
1036 // CHECK1-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
1037 // CHECK1:       omp.body.continue:
1038 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
1039 // CHECK1:       omp.inner.for.inc:
1040 // CHECK1-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !29
1041 // CHECK1-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP9]], 1
1042 // CHECK1-NEXT:    store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !29
1043 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP30:![0-9]+]]
1044 // CHECK1:       omp.inner.for.end:
1045 // CHECK1-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
1046 // CHECK1:       omp.loop.exit:
1047 // CHECK1-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
1048 // CHECK1-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
1049 // CHECK1-NEXT:    [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0
1050 // CHECK1-NEXT:    br i1 [[TMP11]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
1051 // CHECK1:       .omp.final.then:
1052 // CHECK1-NEXT:    store i32 10, i32* [[I]], align 4
1053 // CHECK1-NEXT:    br label [[DOTOMP_FINAL_DONE]]
1054 // CHECK1:       .omp.final.done:
1055 // CHECK1-NEXT:    ret void
1056 //
1057 //
1058 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118
1059 // CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] {
1060 // CHECK1-NEXT:  entry:
1061 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
1062 // CHECK1-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
1063 // CHECK1-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
1064 // CHECK1-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
1065 // CHECK1-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
1066 // CHECK1-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
1067 // CHECK1-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
1068 // CHECK1-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
1069 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
1070 // CHECK1-NEXT:    [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
1071 // CHECK1-NEXT:    store i32 [[TMP0]], i32* [[CONV2]], align 4
1072 // CHECK1-NEXT:    [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
1073 // CHECK1-NEXT:    [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
1074 // CHECK1-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
1075 // CHECK1-NEXT:    store i16 [[TMP2]], i16* [[CONV3]], align 2
1076 // CHECK1-NEXT:    [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
1077 // CHECK1-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
1078 // CHECK1-NEXT:    ret void
1079 //
1080 //
1081 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..6
1082 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR3]] {
1083 // CHECK1-NEXT:  entry:
1084 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
1085 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
1086 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
1087 // CHECK1-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
1088 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
1089 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
1090 // CHECK1-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
1091 // CHECK1-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
1092 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1093 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1094 // CHECK1-NEXT:    [[I:%.*]] = alloca i32, align 4
1095 // CHECK1-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
1096 // CHECK1-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
1097 // CHECK1-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
1098 // CHECK1-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
1099 // CHECK1-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
1100 // CHECK1-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
1101 // CHECK1-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
1102 // CHECK1-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
1103 // CHECK1-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
1104 // CHECK1-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
1105 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
1106 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
1107 // CHECK1-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
1108 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1109 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
1110 // CHECK1-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1111 // CHECK1:       cond.true:
1112 // CHECK1-NEXT:    br label [[COND_END:%.*]]
1113 // CHECK1:       cond.false:
1114 // CHECK1-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1115 // CHECK1-NEXT:    br label [[COND_END]]
1116 // CHECK1:       cond.end:
1117 // CHECK1-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
1118 // CHECK1-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
1119 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
1120 // CHECK1-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
1121 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
1122 // CHECK1:       omp.inner.for.cond:
1123 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !32
1124 // CHECK1-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !32
1125 // CHECK1-NEXT:    [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
1126 // CHECK1-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1127 // CHECK1:       omp.inner.for.body:
1128 // CHECK1-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !32
1129 // CHECK1-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
1130 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1131 // CHECK1-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !32
1132 // CHECK1-NEXT:    [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !32
1133 // CHECK1-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
1134 // CHECK1-NEXT:    store i32 [[ADD3]], i32* [[CONV]], align 4, !llvm.access.group !32
1135 // CHECK1-NEXT:    [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 2, !llvm.access.group !32
1136 // CHECK1-NEXT:    [[CONV4:%.*]] = sext i16 [[TMP9]] to i32
1137 // CHECK1-NEXT:    [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
1138 // CHECK1-NEXT:    [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
1139 // CHECK1-NEXT:    store i16 [[CONV6]], i16* [[CONV1]], align 2, !llvm.access.group !32
1140 // CHECK1-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
1141 // CHECK1:       omp.body.continue:
1142 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
1143 // CHECK1:       omp.inner.for.inc:
1144 // CHECK1-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !32
1145 // CHECK1-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1
1146 // CHECK1-NEXT:    store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !32
1147 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP33:![0-9]+]]
1148 // CHECK1:       omp.inner.for.end:
1149 // CHECK1-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
1150 // CHECK1:       omp.loop.exit:
1151 // CHECK1-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
1152 // CHECK1-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
1153 // CHECK1-NEXT:    [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
1154 // CHECK1-NEXT:    br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
1155 // CHECK1:       .omp.final.then:
1156 // CHECK1-NEXT:    store i32 10, i32* [[I]], align 4
1157 // CHECK1-NEXT:    br label [[DOTOMP_FINAL_DONE]]
1158 // CHECK1:       .omp.final.done:
1159 // CHECK1-NEXT:    ret void
1160 //
1161 //
1162 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142
1163 // CHECK1-SAME: (i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] {
1164 // CHECK1-NEXT:  entry:
1165 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
1166 // CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
1167 // CHECK1-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
1168 // CHECK1-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 8
1169 // CHECK1-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
1170 // CHECK1-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
1171 // CHECK1-NEXT:    [[VLA_ADDR4:%.*]] = alloca i64, align 8
1172 // CHECK1-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 8
1173 // CHECK1-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
1174 // CHECK1-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
1175 // CHECK1-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
1176 // CHECK1-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
1177 // CHECK1-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
1178 // CHECK1-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 8
1179 // CHECK1-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
1180 // CHECK1-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
1181 // CHECK1-NEXT:    store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
1182 // CHECK1-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 8
1183 // CHECK1-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
1184 // CHECK1-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
1185 // CHECK1-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
1186 // CHECK1-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
1187 // CHECK1-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
1188 // CHECK1-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
1189 // CHECK1-NEXT:    [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
1190 // CHECK1-NEXT:    [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
1191 // CHECK1-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
1192 // CHECK1-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
1193 // CHECK1-NEXT:    [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
1194 // CHECK1-NEXT:    [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
1195 // CHECK1-NEXT:    store i32 [[TMP8]], i32* [[CONV5]], align 4
1196 // CHECK1-NEXT:    [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
1197 // CHECK1-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]])
1198 // CHECK1-NEXT:    ret void
1199 //
1200 //
1201 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..9
1202 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR3]] {
1203 // CHECK1-NEXT:  entry:
1204 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
1205 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
1206 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
1207 // CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
1208 // CHECK1-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
1209 // CHECK1-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 8
1210 // CHECK1-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
1211 // CHECK1-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
1212 // CHECK1-NEXT:    [[VLA_ADDR4:%.*]] = alloca i64, align 8
1213 // CHECK1-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 8
1214 // CHECK1-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
1215 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
1216 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
1217 // CHECK1-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
1218 // CHECK1-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
1219 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1220 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1221 // CHECK1-NEXT:    [[I:%.*]] = alloca i32, align 4
1222 // CHECK1-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
1223 // CHECK1-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
1224 // CHECK1-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
1225 // CHECK1-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
1226 // CHECK1-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
1227 // CHECK1-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 8
1228 // CHECK1-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
1229 // CHECK1-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
1230 // CHECK1-NEXT:    store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
1231 // CHECK1-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 8
1232 // CHECK1-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
1233 // CHECK1-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
1234 // CHECK1-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
1235 // CHECK1-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
1236 // CHECK1-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
1237 // CHECK1-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
1238 // CHECK1-NEXT:    [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
1239 // CHECK1-NEXT:    [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
1240 // CHECK1-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
1241 // CHECK1-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
1242 // CHECK1-NEXT:    [[ARRAYDECAY:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 0
1243 // CHECK1-NEXT:    call void @llvm.assume(i1 true) [ "align"(float* [[ARRAYDECAY]], i64 16) ]
1244 // CHECK1-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
1245 // CHECK1-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
1246 // CHECK1-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
1247 // CHECK1-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
1248 // CHECK1-NEXT:    [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
1249 // CHECK1-NEXT:    [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4
1250 // CHECK1-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
1251 // CHECK1-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1252 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP10]], 9
1253 // CHECK1-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1254 // CHECK1:       cond.true:
1255 // CHECK1-NEXT:    br label [[COND_END:%.*]]
1256 // CHECK1:       cond.false:
1257 // CHECK1-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1258 // CHECK1-NEXT:    br label [[COND_END]]
1259 // CHECK1:       cond.end:
1260 // CHECK1-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ]
1261 // CHECK1-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
1262 // CHECK1-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
1263 // CHECK1-NEXT:    store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4
1264 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
1265 // CHECK1:       omp.inner.for.cond:
1266 // CHECK1-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !35
1267 // CHECK1-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !35
1268 // CHECK1-NEXT:    [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
1269 // CHECK1-NEXT:    br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1270 // CHECK1:       omp.inner.for.body:
1271 // CHECK1-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !35
1272 // CHECK1-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1
1273 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1274 // CHECK1-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !35
1275 // CHECK1-NEXT:    [[TMP16:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !35
1276 // CHECK1-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP16]], 1
1277 // CHECK1-NEXT:    store i32 [[ADD6]], i32* [[CONV]], align 4, !llvm.access.group !35
1278 // CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
1279 // CHECK1-NEXT:    [[TMP17:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !35
1280 // CHECK1-NEXT:    [[CONV7:%.*]] = fpext float [[TMP17]] to double
1281 // CHECK1-NEXT:    [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00
1282 // CHECK1-NEXT:    [[CONV9:%.*]] = fptrunc double [[ADD8]] to float
1283 // CHECK1-NEXT:    store float [[CONV9]], float* [[ARRAYIDX]], align 4, !llvm.access.group !35
1284 // CHECK1-NEXT:    [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3
1285 // CHECK1-NEXT:    [[TMP18:%.*]] = load float, float* [[ARRAYIDX10]], align 4, !llvm.access.group !35
1286 // CHECK1-NEXT:    [[CONV11:%.*]] = fpext float [[TMP18]] to double
1287 // CHECK1-NEXT:    [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00
1288 // CHECK1-NEXT:    [[CONV13:%.*]] = fptrunc double [[ADD12]] to float
1289 // CHECK1-NEXT:    store float [[CONV13]], float* [[ARRAYIDX10]], align 4, !llvm.access.group !35
1290 // CHECK1-NEXT:    [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1
1291 // CHECK1-NEXT:    [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX14]], i64 0, i64 2
1292 // CHECK1-NEXT:    [[TMP19:%.*]] = load double, double* [[ARRAYIDX15]], align 8, !llvm.access.group !35
1293 // CHECK1-NEXT:    [[ADD16:%.*]] = fadd double [[TMP19]], 1.000000e+00
1294 // CHECK1-NEXT:    store double [[ADD16]], double* [[ARRAYIDX15]], align 8, !llvm.access.group !35
1295 // CHECK1-NEXT:    [[TMP20:%.*]] = mul nsw i64 1, [[TMP5]]
1296 // CHECK1-NEXT:    [[ARRAYIDX17:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP20]]
1297 // CHECK1-NEXT:    [[ARRAYIDX18:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX17]], i64 3
1298 // CHECK1-NEXT:    [[TMP21:%.*]] = load double, double* [[ARRAYIDX18]], align 8, !llvm.access.group !35
1299 // CHECK1-NEXT:    [[ADD19:%.*]] = fadd double [[TMP21]], 1.000000e+00
1300 // CHECK1-NEXT:    store double [[ADD19]], double* [[ARRAYIDX18]], align 8, !llvm.access.group !35
1301 // CHECK1-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0
1302 // CHECK1-NEXT:    [[TMP22:%.*]] = load i64, i64* [[X]], align 8, !llvm.access.group !35
1303 // CHECK1-NEXT:    [[ADD20:%.*]] = add nsw i64 [[TMP22]], 1
1304 // CHECK1-NEXT:    store i64 [[ADD20]], i64* [[X]], align 8, !llvm.access.group !35
1305 // CHECK1-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1
1306 // CHECK1-NEXT:    [[TMP23:%.*]] = load i8, i8* [[Y]], align 8, !llvm.access.group !35
1307 // CHECK1-NEXT:    [[CONV21:%.*]] = sext i8 [[TMP23]] to i32
1308 // CHECK1-NEXT:    [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1
1309 // CHECK1-NEXT:    [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8
1310 // CHECK1-NEXT:    store i8 [[CONV23]], i8* [[Y]], align 8, !llvm.access.group !35
1311 // CHECK1-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
1312 // CHECK1:       omp.body.continue:
1313 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
1314 // CHECK1:       omp.inner.for.inc:
1315 // CHECK1-NEXT:    [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !35
1316 // CHECK1-NEXT:    [[ADD24:%.*]] = add nsw i32 [[TMP24]], 1
1317 // CHECK1-NEXT:    store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !35
1318 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP36:![0-9]+]]
1319 // CHECK1:       omp.inner.for.end:
1320 // CHECK1-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
1321 // CHECK1:       omp.loop.exit:
1322 // CHECK1-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]])
1323 // CHECK1-NEXT:    [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
1324 // CHECK1-NEXT:    [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
1325 // CHECK1-NEXT:    br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
1326 // CHECK1:       .omp.final.then:
1327 // CHECK1-NEXT:    store i32 10, i32* [[I]], align 4
1328 // CHECK1-NEXT:    br label [[DOTOMP_FINAL_DONE]]
1329 // CHECK1:       .omp.final.done:
1330 // CHECK1-NEXT:    ret void
1331 //
1332 //
1333 // CHECK1-LABEL: define {{[^@]+}}@_Z3bari
1334 // CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {
1335 // CHECK1-NEXT:  entry:
1336 // CHECK1-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
1337 // CHECK1-NEXT:    [[A:%.*]] = alloca i32, align 4
1338 // CHECK1-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8
1339 // CHECK1-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
1340 // CHECK1-NEXT:    store i32 0, i32* [[A]], align 4
1341 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
1342 // CHECK1-NEXT:    [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]])
1343 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
1344 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
1345 // CHECK1-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
1346 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
1347 // CHECK1-NEXT:    [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP2]])
1348 // CHECK1-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
1349 // CHECK1-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
1350 // CHECK1-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
1351 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
1352 // CHECK1-NEXT:    [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]])
1353 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
1354 // CHECK1-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
1355 // CHECK1-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
1356 // CHECK1-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
1357 // CHECK1-NEXT:    [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]])
1358 // CHECK1-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
1359 // CHECK1-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
1360 // CHECK1-NEXT:    store i32 [[ADD6]], i32* [[A]], align 4
1361 // CHECK1-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
1362 // CHECK1-NEXT:    ret i32 [[TMP8]]
1363 //
1364 //
1365 // CHECK1-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
1366 // CHECK1-SAME: (%struct.S1* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 {
1367 // CHECK1-NEXT:  entry:
1368 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
1369 // CHECK1-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
1370 // CHECK1-NEXT:    [[B:%.*]] = alloca i32, align 4
1371 // CHECK1-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 8
1372 // CHECK1-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
1373 // CHECK1-NEXT:    [[B_CASTED:%.*]] = alloca i64, align 8
1374 // CHECK1-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8
1375 // CHECK1-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8
1376 // CHECK1-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8
1377 // CHECK1-NEXT:    [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 8
1378 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
1379 // CHECK1-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
1380 // CHECK1-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
1381 // CHECK1-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
1382 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
1383 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
1384 // CHECK1-NEXT:    store i32 [[ADD]], i32* [[B]], align 4
1385 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
1386 // CHECK1-NEXT:    [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
1387 // CHECK1-NEXT:    [[TMP3:%.*]] = call i8* @llvm.stacksave()
1388 // CHECK1-NEXT:    store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8
1389 // CHECK1-NEXT:    [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]
1390 // CHECK1-NEXT:    [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2
1391 // CHECK1-NEXT:    store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8
1392 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, i32* [[B]], align 4
1393 // CHECK1-NEXT:    [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32*
1394 // CHECK1-NEXT:    store i32 [[TMP5]], i32* [[CONV]], align 4
1395 // CHECK1-NEXT:    [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8
1396 // CHECK1-NEXT:    [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4
1397 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 60
1398 // CHECK1-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
1399 // CHECK1:       omp_if.then:
1400 // CHECK1-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
1401 // CHECK1-NEXT:    [[TMP8:%.*]] = mul nuw i64 2, [[TMP2]]
1402 // CHECK1-NEXT:    [[TMP9:%.*]] = mul nuw i64 [[TMP8]], 2
1403 // CHECK1-NEXT:    [[TMP10:%.*]] = bitcast [5 x i64]* [[DOTOFFLOAD_SIZES]] to i8*
1404 // CHECK1-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP10]], i8* align 8 bitcast ([5 x i64]* @.offload_sizes.13 to i8*), i64 40, i1 false)
1405 // CHECK1-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1406 // CHECK1-NEXT:    [[TMP12:%.*]] = bitcast i8** [[TMP11]] to %struct.S1**
1407 // CHECK1-NEXT:    store %struct.S1* [[THIS1]], %struct.S1** [[TMP12]], align 8
1408 // CHECK1-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1409 // CHECK1-NEXT:    [[TMP14:%.*]] = bitcast i8** [[TMP13]] to double**
1410 // CHECK1-NEXT:    store double* [[A]], double** [[TMP14]], align 8
1411 // CHECK1-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
1412 // CHECK1-NEXT:    store i8* null, i8** [[TMP15]], align 8
1413 // CHECK1-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
1414 // CHECK1-NEXT:    [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64*
1415 // CHECK1-NEXT:    store i64 [[TMP6]], i64* [[TMP17]], align 8
1416 // CHECK1-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
1417 // CHECK1-NEXT:    [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64*
1418 // CHECK1-NEXT:    store i64 [[TMP6]], i64* [[TMP19]], align 8
1419 // CHECK1-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
1420 // CHECK1-NEXT:    store i8* null, i8** [[TMP20]], align 8
1421 // CHECK1-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
1422 // CHECK1-NEXT:    [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i64*
1423 // CHECK1-NEXT:    store i64 2, i64* [[TMP22]], align 8
1424 // CHECK1-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
1425 // CHECK1-NEXT:    [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i64*
1426 // CHECK1-NEXT:    store i64 2, i64* [[TMP24]], align 8
1427 // CHECK1-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
1428 // CHECK1-NEXT:    store i8* null, i8** [[TMP25]], align 8
1429 // CHECK1-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
1430 // CHECK1-NEXT:    [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64*
1431 // CHECK1-NEXT:    store i64 [[TMP2]], i64* [[TMP27]], align 8
1432 // CHECK1-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
1433 // CHECK1-NEXT:    [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i64*
1434 // CHECK1-NEXT:    store i64 [[TMP2]], i64* [[TMP29]], align 8
1435 // CHECK1-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
1436 // CHECK1-NEXT:    store i8* null, i8** [[TMP30]], align 8
1437 // CHECK1-NEXT:    [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
1438 // CHECK1-NEXT:    [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i16**
1439 // CHECK1-NEXT:    store i16* [[VLA]], i16** [[TMP32]], align 8
1440 // CHECK1-NEXT:    [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
1441 // CHECK1-NEXT:    [[TMP34:%.*]] = bitcast i8** [[TMP33]] to i16**
1442 // CHECK1-NEXT:    store i16* [[VLA]], i16** [[TMP34]], align 8
1443 // CHECK1-NEXT:    [[TMP35:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4
1444 // CHECK1-NEXT:    store i64 [[TMP9]], i64* [[TMP35]], align 8
1445 // CHECK1-NEXT:    [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4
1446 // CHECK1-NEXT:    store i8* null, i8** [[TMP36]], align 8
1447 // CHECK1-NEXT:    [[TMP37:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1448 // CHECK1-NEXT:    [[TMP38:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1449 // CHECK1-NEXT:    [[TMP39:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
1450 // CHECK1-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
1451 // CHECK1-NEXT:    [[TMP40:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
1452 // CHECK1-NEXT:    store i32 1, i32* [[TMP40]], align 4
1453 // CHECK1-NEXT:    [[TMP41:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
1454 // CHECK1-NEXT:    store i32 5, i32* [[TMP41]], align 4
1455 // CHECK1-NEXT:    [[TMP42:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
1456 // CHECK1-NEXT:    store i8** [[TMP37]], i8*** [[TMP42]], align 8
1457 // CHECK1-NEXT:    [[TMP43:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
1458 // CHECK1-NEXT:    store i8** [[TMP38]], i8*** [[TMP43]], align 8
1459 // CHECK1-NEXT:    [[TMP44:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
1460 // CHECK1-NEXT:    store i64* [[TMP39]], i64** [[TMP44]], align 8
1461 // CHECK1-NEXT:    [[TMP45:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
1462 // CHECK1-NEXT:    store i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.14, i32 0, i32 0), i64** [[TMP45]], align 8
1463 // CHECK1-NEXT:    [[TMP46:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
1464 // CHECK1-NEXT:    store i8** null, i8*** [[TMP46]], align 8
1465 // CHECK1-NEXT:    [[TMP47:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
1466 // CHECK1-NEXT:    store i8** null, i8*** [[TMP47]], align 8
1467 // CHECK1-NEXT:    [[TMP48:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
1468 // CHECK1-NEXT:    store i64 10, i64* [[TMP48]], align 8
1469 // CHECK1-NEXT:    [[TMP49:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB2]], i64 -1, i32 0, i32 1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
1470 // CHECK1-NEXT:    [[TMP50:%.*]] = icmp ne i32 [[TMP49]], 0
1471 // CHECK1-NEXT:    br i1 [[TMP50]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
1472 // CHECK1:       omp_offload.failed:
1473 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR4]]
1474 // CHECK1-NEXT:    br label [[OMP_OFFLOAD_CONT]]
1475 // CHECK1:       omp_offload.cont:
1476 // CHECK1-NEXT:    br label [[OMP_IF_END:%.*]]
1477 // CHECK1:       omp_if.else:
1478 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR4]]
1479 // CHECK1-NEXT:    br label [[OMP_IF_END]]
1480 // CHECK1:       omp_if.end:
1481 // CHECK1-NEXT:    [[TMP51:%.*]] = mul nsw i64 1, [[TMP2]]
1482 // CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP51]]
1483 // CHECK1-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
1484 // CHECK1-NEXT:    [[TMP52:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2
1485 // CHECK1-NEXT:    [[CONV3:%.*]] = sext i16 [[TMP52]] to i32
1486 // CHECK1-NEXT:    [[TMP53:%.*]] = load i32, i32* [[B]], align 4
1487 // CHECK1-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], [[TMP53]]
1488 // CHECK1-NEXT:    [[TMP54:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
1489 // CHECK1-NEXT:    call void @llvm.stackrestore(i8* [[TMP54]])
1490 // CHECK1-NEXT:    ret i32 [[ADD4]]
1491 //
1492 //
1493 // CHECK1-LABEL: define {{[^@]+}}@_ZL7fstatici
1494 // CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {
1495 // CHECK1-NEXT:  entry:
1496 // CHECK1-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
1497 // CHECK1-NEXT:    [[A:%.*]] = alloca i32, align 4
1498 // CHECK1-NEXT:    [[AA:%.*]] = alloca i16, align 2
1499 // CHECK1-NEXT:    [[AAA:%.*]] = alloca i8, align 1
1500 // CHECK1-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
1501 // CHECK1-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
1502 // CHECK1-NEXT:    [[N_CASTED:%.*]] = alloca i64, align 8
1503 // CHECK1-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
1504 // CHECK1-NEXT:    [[AAA_CASTED:%.*]] = alloca i64, align 8
1505 // CHECK1-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8
1506 // CHECK1-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8
1507 // CHECK1-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8
1508 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
1509 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
1510 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4
1511 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR_5:%.*]] = alloca i32, align 4
1512 // CHECK1-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
1513 // CHECK1-NEXT:    store i32 0, i32* [[A]], align 4
1514 // CHECK1-NEXT:    store i16 0, i16* [[AA]], align 2
1515 // CHECK1-NEXT:    store i8 0, i8* [[AAA]], align 1
1516 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
1517 // CHECK1-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32*
1518 // CHECK1-NEXT:    store i32 [[TMP0]], i32* [[CONV]], align 4
1519 // CHECK1-NEXT:    [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
1520 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
1521 // CHECK1-NEXT:    [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32*
1522 // CHECK1-NEXT:    store i32 [[TMP2]], i32* [[CONV1]], align 4
1523 // CHECK1-NEXT:    [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8
1524 // CHECK1-NEXT:    [[TMP4:%.*]] = load i16, i16* [[AA]], align 2
1525 // CHECK1-NEXT:    [[CONV2:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
1526 // CHECK1-NEXT:    store i16 [[TMP4]], i16* [[CONV2]], align 2
1527 // CHECK1-NEXT:    [[TMP5:%.*]] = load i64, i64* [[AA_CASTED]], align 8
1528 // CHECK1-NEXT:    [[TMP6:%.*]] = load i8, i8* [[AAA]], align 1
1529 // CHECK1-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
1530 // CHECK1-NEXT:    store i8 [[TMP6]], i8* [[CONV3]], align 1
1531 // CHECK1-NEXT:    [[TMP7:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
1532 // CHECK1-NEXT:    [[TMP8:%.*]] = load i32, i32* [[N_ADDR]], align 4
1533 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP8]], 50
1534 // CHECK1-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
1535 // CHECK1:       omp_if.then:
1536 // CHECK1-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1537 // CHECK1-NEXT:    [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64*
1538 // CHECK1-NEXT:    store i64 [[TMP1]], i64* [[TMP10]], align 8
1539 // CHECK1-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1540 // CHECK1-NEXT:    [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64*
1541 // CHECK1-NEXT:    store i64 [[TMP1]], i64* [[TMP12]], align 8
1542 // CHECK1-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
1543 // CHECK1-NEXT:    store i8* null, i8** [[TMP13]], align 8
1544 // CHECK1-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
1545 // CHECK1-NEXT:    [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64*
1546 // CHECK1-NEXT:    store i64 [[TMP3]], i64* [[TMP15]], align 8
1547 // CHECK1-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
1548 // CHECK1-NEXT:    [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64*
1549 // CHECK1-NEXT:    store i64 [[TMP3]], i64* [[TMP17]], align 8
1550 // CHECK1-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
1551 // CHECK1-NEXT:    store i8* null, i8** [[TMP18]], align 8
1552 // CHECK1-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
1553 // CHECK1-NEXT:    [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64*
1554 // CHECK1-NEXT:    store i64 [[TMP5]], i64* [[TMP20]], align 8
1555 // CHECK1-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
1556 // CHECK1-NEXT:    [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i64*
1557 // CHECK1-NEXT:    store i64 [[TMP5]], i64* [[TMP22]], align 8
1558 // CHECK1-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
1559 // CHECK1-NEXT:    store i8* null, i8** [[TMP23]], align 8
1560 // CHECK1-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
1561 // CHECK1-NEXT:    [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i64*
1562 // CHECK1-NEXT:    store i64 [[TMP7]], i64* [[TMP25]], align 8
1563 // CHECK1-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
1564 // CHECK1-NEXT:    [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64*
1565 // CHECK1-NEXT:    store i64 [[TMP7]], i64* [[TMP27]], align 8
1566 // CHECK1-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
1567 // CHECK1-NEXT:    store i8* null, i8** [[TMP28]], align 8
1568 // CHECK1-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
1569 // CHECK1-NEXT:    [[TMP30:%.*]] = bitcast i8** [[TMP29]] to [10 x i32]**
1570 // CHECK1-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP30]], align 8
1571 // CHECK1-NEXT:    [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
1572 // CHECK1-NEXT:    [[TMP32:%.*]] = bitcast i8** [[TMP31]] to [10 x i32]**
1573 // CHECK1-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP32]], align 8
1574 // CHECK1-NEXT:    [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4
1575 // CHECK1-NEXT:    store i8* null, i8** [[TMP33]], align 8
1576 // CHECK1-NEXT:    [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1577 // CHECK1-NEXT:    [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1578 // CHECK1-NEXT:    [[TMP36:%.*]] = load i32, i32* [[A]], align 4
1579 // CHECK1-NEXT:    store i32 [[TMP36]], i32* [[DOTCAPTURE_EXPR_]], align 4
1580 // CHECK1-NEXT:    [[TMP37:%.*]] = load i32, i32* [[N_ADDR]], align 4
1581 // CHECK1-NEXT:    store i32 [[TMP37]], i32* [[DOTCAPTURE_EXPR_4]], align 4
1582 // CHECK1-NEXT:    [[TMP38:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4
1583 // CHECK1-NEXT:    [[TMP39:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
1584 // CHECK1-NEXT:    [[SUB:%.*]] = sub i32 [[TMP38]], [[TMP39]]
1585 // CHECK1-NEXT:    [[SUB6:%.*]] = sub i32 [[SUB]], 1
1586 // CHECK1-NEXT:    [[ADD:%.*]] = add i32 [[SUB6]], 1
1587 // CHECK1-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], 1
1588 // CHECK1-NEXT:    [[SUB7:%.*]] = sub i32 [[DIV]], 1
1589 // CHECK1-NEXT:    store i32 [[SUB7]], i32* [[DOTCAPTURE_EXPR_5]], align 4
1590 // CHECK1-NEXT:    [[TMP40:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4
1591 // CHECK1-NEXT:    [[ADD8:%.*]] = add i32 [[TMP40]], 1
1592 // CHECK1-NEXT:    [[TMP41:%.*]] = zext i32 [[ADD8]] to i64
1593 // CHECK1-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
1594 // CHECK1-NEXT:    [[TMP42:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
1595 // CHECK1-NEXT:    store i32 1, i32* [[TMP42]], align 4
1596 // CHECK1-NEXT:    [[TMP43:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
1597 // CHECK1-NEXT:    store i32 5, i32* [[TMP43]], align 4
1598 // CHECK1-NEXT:    [[TMP44:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
1599 // CHECK1-NEXT:    store i8** [[TMP34]], i8*** [[TMP44]], align 8
1600 // CHECK1-NEXT:    [[TMP45:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
1601 // CHECK1-NEXT:    store i8** [[TMP35]], i8*** [[TMP45]], align 8
1602 // CHECK1-NEXT:    [[TMP46:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
1603 // CHECK1-NEXT:    store i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes.16, i32 0, i32 0), i64** [[TMP46]], align 8
1604 // CHECK1-NEXT:    [[TMP47:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
1605 // CHECK1-NEXT:    store i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.17, i32 0, i32 0), i64** [[TMP47]], align 8
1606 // CHECK1-NEXT:    [[TMP48:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
1607 // CHECK1-NEXT:    store i8** null, i8*** [[TMP48]], align 8
1608 // CHECK1-NEXT:    [[TMP49:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
1609 // CHECK1-NEXT:    store i8** null, i8*** [[TMP49]], align 8
1610 // CHECK1-NEXT:    [[TMP50:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
1611 // CHECK1-NEXT:    store i64 [[TMP41]], i64* [[TMP50]], align 8
1612 // CHECK1-NEXT:    [[TMP51:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB2]], i64 -1, i32 0, i32 1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
1613 // CHECK1-NEXT:    [[TMP52:%.*]] = icmp ne i32 [[TMP51]], 0
1614 // CHECK1-NEXT:    br i1 [[TMP52]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
1615 // CHECK1:       omp_offload.failed:
1616 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], i64 [[TMP7]], [10 x i32]* [[B]]) #[[ATTR4]]
1617 // CHECK1-NEXT:    br label [[OMP_OFFLOAD_CONT]]
1618 // CHECK1:       omp_offload.cont:
1619 // CHECK1-NEXT:    br label [[OMP_IF_END:%.*]]
1620 // CHECK1:       omp_if.else:
1621 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], i64 [[TMP7]], [10 x i32]* [[B]]) #[[ATTR4]]
1622 // CHECK1-NEXT:    br label [[OMP_IF_END]]
1623 // CHECK1:       omp_if.end:
1624 // CHECK1-NEXT:    [[TMP53:%.*]] = load i32, i32* [[A]], align 4
1625 // CHECK1-NEXT:    ret i32 [[TMP53]]
1626 //
1627 //
1628 // CHECK1-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
1629 // CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat {
1630 // CHECK1-NEXT:  entry:
1631 // CHECK1-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
1632 // CHECK1-NEXT:    [[A:%.*]] = alloca i32, align 4
1633 // CHECK1-NEXT:    [[AA:%.*]] = alloca i16, align 2
1634 // CHECK1-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
1635 // CHECK1-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
1636 // CHECK1-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
1637 // CHECK1-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8
1638 // CHECK1-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8
1639 // CHECK1-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8
1640 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
1641 // CHECK1-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
1642 // CHECK1-NEXT:    store i32 0, i32* [[A]], align 4
1643 // CHECK1-NEXT:    store i16 0, i16* [[AA]], align 2
1644 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
1645 // CHECK1-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32*
1646 // CHECK1-NEXT:    store i32 [[TMP0]], i32* [[CONV]], align 4
1647 // CHECK1-NEXT:    [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
1648 // CHECK1-NEXT:    [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
1649 // CHECK1-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
1650 // CHECK1-NEXT:    store i16 [[TMP2]], i16* [[CONV1]], align 2
1651 // CHECK1-NEXT:    [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
1652 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
1653 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40
1654 // CHECK1-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
1655 // CHECK1:       omp_if.then:
1656 // CHECK1-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1657 // CHECK1-NEXT:    [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64*
1658 // CHECK1-NEXT:    store i64 [[TMP1]], i64* [[TMP6]], align 8
1659 // CHECK1-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1660 // CHECK1-NEXT:    [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64*
1661 // CHECK1-NEXT:    store i64 [[TMP1]], i64* [[TMP8]], align 8
1662 // CHECK1-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
1663 // CHECK1-NEXT:    store i8* null, i8** [[TMP9]], align 8
1664 // CHECK1-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
1665 // CHECK1-NEXT:    [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i64*
1666 // CHECK1-NEXT:    store i64 [[TMP3]], i64* [[TMP11]], align 8
1667 // CHECK1-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
1668 // CHECK1-NEXT:    [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64*
1669 // CHECK1-NEXT:    store i64 [[TMP3]], i64* [[TMP13]], align 8
1670 // CHECK1-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
1671 // CHECK1-NEXT:    store i8* null, i8** [[TMP14]], align 8
1672 // CHECK1-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
1673 // CHECK1-NEXT:    [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]**
1674 // CHECK1-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 8
1675 // CHECK1-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
1676 // CHECK1-NEXT:    [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]**
1677 // CHECK1-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 8
1678 // CHECK1-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
1679 // CHECK1-NEXT:    store i8* null, i8** [[TMP19]], align 8
1680 // CHECK1-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1681 // CHECK1-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1682 // CHECK1-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
1683 // CHECK1-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
1684 // CHECK1-NEXT:    store i32 1, i32* [[TMP22]], align 4
1685 // CHECK1-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
1686 // CHECK1-NEXT:    store i32 3, i32* [[TMP23]], align 4
1687 // CHECK1-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
1688 // CHECK1-NEXT:    store i8** [[TMP20]], i8*** [[TMP24]], align 8
1689 // CHECK1-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
1690 // CHECK1-NEXT:    store i8** [[TMP21]], i8*** [[TMP25]], align 8
1691 // CHECK1-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
1692 // CHECK1-NEXT:    store i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.19, i32 0, i32 0), i64** [[TMP26]], align 8
1693 // CHECK1-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
1694 // CHECK1-NEXT:    store i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.20, i32 0, i32 0), i64** [[TMP27]], align 8
1695 // CHECK1-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
1696 // CHECK1-NEXT:    store i8** null, i8*** [[TMP28]], align 8
1697 // CHECK1-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
1698 // CHECK1-NEXT:    store i8** null, i8*** [[TMP29]], align 8
1699 // CHECK1-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
1700 // CHECK1-NEXT:    store i64 10, i64* [[TMP30]], align 8
1701 // CHECK1-NEXT:    [[TMP31:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB2]], i64 -1, i32 0, i32 1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
1702 // CHECK1-NEXT:    [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0
1703 // CHECK1-NEXT:    br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
1704 // CHECK1:       omp_offload.failed:
1705 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]]
1706 // CHECK1-NEXT:    br label [[OMP_OFFLOAD_CONT]]
1707 // CHECK1:       omp_offload.cont:
1708 // CHECK1-NEXT:    br label [[OMP_IF_END:%.*]]
1709 // CHECK1:       omp_if.else:
1710 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]]
1711 // CHECK1-NEXT:    br label [[OMP_IF_END]]
1712 // CHECK1:       omp_if.end:
1713 // CHECK1-NEXT:    [[TMP33:%.*]] = load i32, i32* [[A]], align 4
1714 // CHECK1-NEXT:    ret i32 [[TMP33]]
1715 //
1716 //
1717 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215
1718 // CHECK1-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {
1719 // CHECK1-NEXT:  entry:
1720 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
1721 // CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
1722 // CHECK1-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
1723 // CHECK1-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
1724 // CHECK1-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 8
1725 // CHECK1-NEXT:    [[B_CASTED:%.*]] = alloca i64, align 8
1726 // CHECK1-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
1727 // CHECK1-NEXT:    store i64 [[B]], i64* [[B_ADDR]], align 8
1728 // CHECK1-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
1729 // CHECK1-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
1730 // CHECK1-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 8
1731 // CHECK1-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
1732 // CHECK1-NEXT:    [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
1733 // CHECK1-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
1734 // CHECK1-NEXT:    [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
1735 // CHECK1-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
1736 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
1737 // CHECK1-NEXT:    [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32*
1738 // CHECK1-NEXT:    store i32 [[TMP4]], i32* [[CONV3]], align 4
1739 // CHECK1-NEXT:    [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
1740 // CHECK1-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..12 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]])
1741 // CHECK1-NEXT:    ret void
1742 //
1743 //
1744 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..12
1745 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] {
1746 // CHECK1-NEXT:  entry:
1747 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
1748 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
1749 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
1750 // CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
1751 // CHECK1-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
1752 // CHECK1-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
1753 // CHECK1-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 8
1754 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
1755 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
1756 // CHECK1-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
1757 // CHECK1-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
1758 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1759 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1760 // CHECK1-NEXT:    [[I:%.*]] = alloca i32, align 4
1761 // CHECK1-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
1762 // CHECK1-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
1763 // CHECK1-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
1764 // CHECK1-NEXT:    store i64 [[B]], i64* [[B_ADDR]], align 8
1765 // CHECK1-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
1766 // CHECK1-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
1767 // CHECK1-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 8
1768 // CHECK1-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
1769 // CHECK1-NEXT:    [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
1770 // CHECK1-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
1771 // CHECK1-NEXT:    [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
1772 // CHECK1-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
1773 // CHECK1-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
1774 // CHECK1-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
1775 // CHECK1-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
1776 // CHECK1-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
1777 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
1778 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
1779 // CHECK1-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
1780 // CHECK1-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1781 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 9
1782 // CHECK1-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1783 // CHECK1:       cond.true:
1784 // CHECK1-NEXT:    br label [[COND_END:%.*]]
1785 // CHECK1:       cond.false:
1786 // CHECK1-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1787 // CHECK1-NEXT:    br label [[COND_END]]
1788 // CHECK1:       cond.end:
1789 // CHECK1-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
1790 // CHECK1-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
1791 // CHECK1-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
1792 // CHECK1-NEXT:    store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
1793 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
1794 // CHECK1:       omp.inner.for.cond:
1795 // CHECK1-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !38
1796 // CHECK1-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !38
1797 // CHECK1-NEXT:    [[CMP3:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
1798 // CHECK1-NEXT:    br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1799 // CHECK1:       omp.inner.for.body:
1800 // CHECK1-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !38
1801 // CHECK1-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
1802 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1803 // CHECK1-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !38
1804 // CHECK1-NEXT:    [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !38
1805 // CHECK1-NEXT:    [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double
1806 // CHECK1-NEXT:    [[ADD5:%.*]] = fadd double [[CONV4]], 1.500000e+00
1807 // CHECK1-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
1808 // CHECK1-NEXT:    store double [[ADD5]], double* [[A]], align 8, !llvm.access.group !38
1809 // CHECK1-NEXT:    [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
1810 // CHECK1-NEXT:    [[TMP13:%.*]] = load double, double* [[A6]], align 8, !llvm.access.group !38
1811 // CHECK1-NEXT:    [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00
1812 // CHECK1-NEXT:    store double [[INC]], double* [[A6]], align 8, !llvm.access.group !38
1813 // CHECK1-NEXT:    [[CONV7:%.*]] = fptosi double [[INC]] to i16
1814 // CHECK1-NEXT:    [[TMP14:%.*]] = mul nsw i64 1, [[TMP2]]
1815 // CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP14]]
1816 // CHECK1-NEXT:    [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
1817 // CHECK1-NEXT:    store i16 [[CONV7]], i16* [[ARRAYIDX8]], align 2, !llvm.access.group !38
1818 // CHECK1-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
1819 // CHECK1:       omp.body.continue:
1820 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
1821 // CHECK1:       omp.inner.for.inc:
1822 // CHECK1-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !38
1823 // CHECK1-NEXT:    [[ADD9:%.*]] = add nsw i32 [[TMP15]], 1
1824 // CHECK1-NEXT:    store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !38
1825 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP39:![0-9]+]]
1826 // CHECK1:       omp.inner.for.end:
1827 // CHECK1-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
1828 // CHECK1:       omp.loop.exit:
1829 // CHECK1-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
1830 // CHECK1-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
1831 // CHECK1-NEXT:    [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0
1832 // CHECK1-NEXT:    br i1 [[TMP17]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
1833 // CHECK1:       .omp.final.then:
1834 // CHECK1-NEXT:    store i32 10, i32* [[I]], align 4
1835 // CHECK1-NEXT:    br label [[DOTOMP_FINAL_DONE]]
1836 // CHECK1:       .omp.final.done:
1837 // CHECK1-NEXT:    ret void
1838 //
1839 //
1840 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197
1841 // CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[N:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
1842 // CHECK1-NEXT:  entry:
1843 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
1844 // CHECK1-NEXT:    [[N_ADDR:%.*]] = alloca i64, align 8
1845 // CHECK1-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
1846 // CHECK1-NEXT:    [[AAA_ADDR:%.*]] = alloca i64, align 8
1847 // CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
1848 // CHECK1-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
1849 // CHECK1-NEXT:    [[N_CASTED:%.*]] = alloca i64, align 8
1850 // CHECK1-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
1851 // CHECK1-NEXT:    [[AAA_CASTED:%.*]] = alloca i64, align 8
1852 // CHECK1-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
1853 // CHECK1-NEXT:    store i64 [[N]], i64* [[N_ADDR]], align 8
1854 // CHECK1-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
1855 // CHECK1-NEXT:    store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
1856 // CHECK1-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
1857 // CHECK1-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
1858 // CHECK1-NEXT:    [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32*
1859 // CHECK1-NEXT:    [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
1860 // CHECK1-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
1861 // CHECK1-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
1862 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
1863 // CHECK1-NEXT:    [[CONV4:%.*]] = bitcast i64* [[A_CASTED]] to i32*
1864 // CHECK1-NEXT:    store i32 [[TMP1]], i32* [[CONV4]], align 4
1865 // CHECK1-NEXT:    [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
1866 // CHECK1-NEXT:    [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 4
1867 // CHECK1-NEXT:    [[CONV5:%.*]] = bitcast i64* [[N_CASTED]] to i32*
1868 // CHECK1-NEXT:    store i32 [[TMP3]], i32* [[CONV5]], align 4
1869 // CHECK1-NEXT:    [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8
1870 // CHECK1-NEXT:    [[TMP5:%.*]] = load i16, i16* [[CONV2]], align 2
1871 // CHECK1-NEXT:    [[CONV6:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
1872 // CHECK1-NEXT:    store i16 [[TMP5]], i16* [[CONV6]], align 2
1873 // CHECK1-NEXT:    [[TMP6:%.*]] = load i64, i64* [[AA_CASTED]], align 8
1874 // CHECK1-NEXT:    [[TMP7:%.*]] = load i8, i8* [[CONV3]], align 1
1875 // CHECK1-NEXT:    [[CONV7:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
1876 // CHECK1-NEXT:    store i8 [[TMP7]], i8* [[CONV7]], align 1
1877 // CHECK1-NEXT:    [[TMP8:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
1878 // CHECK1-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, [10 x i32]*)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]], [10 x i32]* [[TMP0]])
1879 // CHECK1-NEXT:    ret void
1880 //
1881 //
1882 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..15
1883 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[N:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] {
1884 // CHECK1-NEXT:  entry:
1885 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
1886 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
1887 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
1888 // CHECK1-NEXT:    [[N_ADDR:%.*]] = alloca i64, align 8
1889 // CHECK1-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
1890 // CHECK1-NEXT:    [[AAA_ADDR:%.*]] = alloca i64, align 8
1891 // CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
1892 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
1893 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
1894 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
1895 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4
1896 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR_5:%.*]] = alloca i32, align 4
1897 // CHECK1-NEXT:    [[I:%.*]] = alloca i32, align 4
1898 // CHECK1-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
1899 // CHECK1-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
1900 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1901 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1902 // CHECK1-NEXT:    [[I8:%.*]] = alloca i32, align 4
1903 // CHECK1-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
1904 // CHECK1-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
1905 // CHECK1-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
1906 // CHECK1-NEXT:    store i64 [[N]], i64* [[N_ADDR]], align 8
1907 // CHECK1-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
1908 // CHECK1-NEXT:    store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
1909 // CHECK1-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
1910 // CHECK1-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
1911 // CHECK1-NEXT:    [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32*
1912 // CHECK1-NEXT:    [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
1913 // CHECK1-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
1914 // CHECK1-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
1915 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
1916 // CHECK1-NEXT:    store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
1917 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4
1918 // CHECK1-NEXT:    store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_4]], align 4
1919 // CHECK1-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4
1920 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
1921 // CHECK1-NEXT:    [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]]
1922 // CHECK1-NEXT:    [[SUB6:%.*]] = sub i32 [[SUB]], 1
1923 // CHECK1-NEXT:    [[ADD:%.*]] = add i32 [[SUB6]], 1
1924 // CHECK1-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], 1
1925 // CHECK1-NEXT:    [[SUB7:%.*]] = sub i32 [[DIV]], 1
1926 // CHECK1-NEXT:    store i32 [[SUB7]], i32* [[DOTCAPTURE_EXPR_5]], align 4
1927 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
1928 // CHECK1-NEXT:    store i32 [[TMP5]], i32* [[I]], align 4
1929 // CHECK1-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
1930 // CHECK1-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4
1931 // CHECK1-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]]
1932 // CHECK1-NEXT:    br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
1933 // CHECK1:       omp.precond.then:
1934 // CHECK1-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
1935 // CHECK1-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4
1936 // CHECK1-NEXT:    store i32 [[TMP8]], i32* [[DOTOMP_UB]], align 4
1937 // CHECK1-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
1938 // CHECK1-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
1939 // CHECK1-NEXT:    [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
1940 // CHECK1-NEXT:    [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
1941 // CHECK1-NEXT:    call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
1942 // CHECK1-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1943 // CHECK1-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4
1944 // CHECK1-NEXT:    [[CMP9:%.*]] = icmp ugt i32 [[TMP11]], [[TMP12]]
1945 // CHECK1-NEXT:    br i1 [[CMP9]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1946 // CHECK1:       cond.true:
1947 // CHECK1-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4
1948 // CHECK1-NEXT:    br label [[COND_END:%.*]]
1949 // CHECK1:       cond.false:
1950 // CHECK1-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1951 // CHECK1-NEXT:    br label [[COND_END]]
1952 // CHECK1:       cond.end:
1953 // CHECK1-NEXT:    [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ]
1954 // CHECK1-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
1955 // CHECK1-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
1956 // CHECK1-NEXT:    store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4
1957 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
1958 // CHECK1:       omp.inner.for.cond:
1959 // CHECK1-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !41
1960 // CHECK1-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !41
1961 // CHECK1-NEXT:    [[ADD10:%.*]] = add i32 [[TMP17]], 1
1962 // CHECK1-NEXT:    [[CMP11:%.*]] = icmp ult i32 [[TMP16]], [[ADD10]]
1963 // CHECK1-NEXT:    br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1964 // CHECK1:       omp.inner.for.body:
1965 // CHECK1-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group !41
1966 // CHECK1-NEXT:    [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !41
1967 // CHECK1-NEXT:    [[MUL:%.*]] = mul i32 [[TMP19]], 1
1968 // CHECK1-NEXT:    [[ADD12:%.*]] = add i32 [[TMP18]], [[MUL]]
1969 // CHECK1-NEXT:    store i32 [[ADD12]], i32* [[I8]], align 4, !llvm.access.group !41
1970 // CHECK1-NEXT:    [[TMP20:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !41
1971 // CHECK1-NEXT:    [[ADD13:%.*]] = add nsw i32 [[TMP20]], 1
1972 // CHECK1-NEXT:    store i32 [[ADD13]], i32* [[CONV]], align 4, !llvm.access.group !41
1973 // CHECK1-NEXT:    [[TMP21:%.*]] = load i16, i16* [[CONV2]], align 2, !llvm.access.group !41
1974 // CHECK1-NEXT:    [[CONV14:%.*]] = sext i16 [[TMP21]] to i32
1975 // CHECK1-NEXT:    [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1
1976 // CHECK1-NEXT:    [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16
1977 // CHECK1-NEXT:    store i16 [[CONV16]], i16* [[CONV2]], align 2, !llvm.access.group !41
1978 // CHECK1-NEXT:    [[TMP22:%.*]] = load i8, i8* [[CONV3]], align 1, !llvm.access.group !41
1979 // CHECK1-NEXT:    [[CONV17:%.*]] = sext i8 [[TMP22]] to i32
1980 // CHECK1-NEXT:    [[ADD18:%.*]] = add nsw i32 [[CONV17]], 1
1981 // CHECK1-NEXT:    [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8
1982 // CHECK1-NEXT:    store i8 [[CONV19]], i8* [[CONV3]], align 1, !llvm.access.group !41
1983 // CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
1984 // CHECK1-NEXT:    [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !41
1985 // CHECK1-NEXT:    [[ADD20:%.*]] = add nsw i32 [[TMP23]], 1
1986 // CHECK1-NEXT:    store i32 [[ADD20]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !41
1987 // CHECK1-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
1988 // CHECK1:       omp.body.continue:
1989 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
1990 // CHECK1:       omp.inner.for.inc:
1991 // CHECK1-NEXT:    [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !41
1992 // CHECK1-NEXT:    [[ADD21:%.*]] = add i32 [[TMP24]], 1
1993 // CHECK1-NEXT:    store i32 [[ADD21]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !41
1994 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP42:![0-9]+]]
1995 // CHECK1:       omp.inner.for.end:
1996 // CHECK1-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
1997 // CHECK1:       omp.loop.exit:
1998 // CHECK1-NEXT:    [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
1999 // CHECK1-NEXT:    [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4
2000 // CHECK1-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]])
2001 // CHECK1-NEXT:    [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
2002 // CHECK1-NEXT:    [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0
2003 // CHECK1-NEXT:    br i1 [[TMP28]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
2004 // CHECK1:       .omp.final.then:
2005 // CHECK1-NEXT:    [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
2006 // CHECK1-NEXT:    [[TMP30:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4
2007 // CHECK1-NEXT:    [[TMP31:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
2008 // CHECK1-NEXT:    [[SUB22:%.*]] = sub i32 [[TMP30]], [[TMP31]]
2009 // CHECK1-NEXT:    [[SUB23:%.*]] = sub i32 [[SUB22]], 1
2010 // CHECK1-NEXT:    [[ADD24:%.*]] = add i32 [[SUB23]], 1
2011 // CHECK1-NEXT:    [[DIV25:%.*]] = udiv i32 [[ADD24]], 1
2012 // CHECK1-NEXT:    [[MUL26:%.*]] = mul i32 [[DIV25]], 1
2013 // CHECK1-NEXT:    [[ADD27:%.*]] = add i32 [[TMP29]], [[MUL26]]
2014 // CHECK1-NEXT:    store i32 [[ADD27]], i32* [[I8]], align 4
2015 // CHECK1-NEXT:    br label [[DOTOMP_FINAL_DONE]]
2016 // CHECK1:       .omp.final.done:
2017 // CHECK1-NEXT:    br label [[OMP_PRECOND_END]]
2018 // CHECK1:       omp.precond.end:
2019 // CHECK1-NEXT:    ret void
2020 //
2021 //
2022 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180
2023 // CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
2024 // CHECK1-NEXT:  entry:
2025 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
2026 // CHECK1-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
2027 // CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
2028 // CHECK1-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
2029 // CHECK1-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
2030 // CHECK1-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
2031 // CHECK1-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
2032 // CHECK1-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
2033 // CHECK1-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
2034 // CHECK1-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
2035 // CHECK1-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
2036 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
2037 // CHECK1-NEXT:    [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
2038 // CHECK1-NEXT:    store i32 [[TMP1]], i32* [[CONV2]], align 4
2039 // CHECK1-NEXT:    [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
2040 // CHECK1-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
2041 // CHECK1-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
2042 // CHECK1-NEXT:    store i16 [[TMP3]], i16* [[CONV3]], align 2
2043 // CHECK1-NEXT:    [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
2044 // CHECK1-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..18 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]])
2045 // CHECK1-NEXT:    ret void
2046 //
2047 //
2048 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..18
2049 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] {
2050 // CHECK1-NEXT:  entry:
2051 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
2052 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
2053 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
2054 // CHECK1-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
2055 // CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
2056 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
2057 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
2058 // CHECK1-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
2059 // CHECK1-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
2060 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2061 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2062 // CHECK1-NEXT:    [[I:%.*]] = alloca i32, align 4
2063 // CHECK1-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
2064 // CHECK1-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
2065 // CHECK1-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
2066 // CHECK1-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
2067 // CHECK1-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
2068 // CHECK1-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
2069 // CHECK1-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
2070 // CHECK1-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
2071 // CHECK1-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
2072 // CHECK1-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
2073 // CHECK1-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
2074 // CHECK1-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
2075 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
2076 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
2077 // CHECK1-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
2078 // CHECK1-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2079 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9
2080 // CHECK1-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2081 // CHECK1:       cond.true:
2082 // CHECK1-NEXT:    br label [[COND_END:%.*]]
2083 // CHECK1:       cond.false:
2084 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2085 // CHECK1-NEXT:    br label [[COND_END]]
2086 // CHECK1:       cond.end:
2087 // CHECK1-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
2088 // CHECK1-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
2089 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
2090 // CHECK1-NEXT:    store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
2091 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
2092 // CHECK1:       omp.inner.for.cond:
2093 // CHECK1-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !44
2094 // CHECK1-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !44
2095 // CHECK1-NEXT:    [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
2096 // CHECK1-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2097 // CHECK1:       omp.inner.for.body:
2098 // CHECK1-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !44
2099 // CHECK1-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
2100 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
2101 // CHECK1-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !44
2102 // CHECK1-NEXT:    [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !44
2103 // CHECK1-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1
2104 // CHECK1-NEXT:    store i32 [[ADD3]], i32* [[CONV]], align 4, !llvm.access.group !44
2105 // CHECK1-NEXT:    [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 2, !llvm.access.group !44
2106 // CHECK1-NEXT:    [[CONV4:%.*]] = sext i16 [[TMP10]] to i32
2107 // CHECK1-NEXT:    [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
2108 // CHECK1-NEXT:    [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
2109 // CHECK1-NEXT:    store i16 [[CONV6]], i16* [[CONV1]], align 2, !llvm.access.group !44
2110 // CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
2111 // CHECK1-NEXT:    [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !44
2112 // CHECK1-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1
2113 // CHECK1-NEXT:    store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !44
2114 // CHECK1-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
2115 // CHECK1:       omp.body.continue:
2116 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
2117 // CHECK1:       omp.inner.for.inc:
2118 // CHECK1-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !44
2119 // CHECK1-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP12]], 1
2120 // CHECK1-NEXT:    store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !44
2121 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP45:![0-9]+]]
2122 // CHECK1:       omp.inner.for.end:
2123 // CHECK1-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
2124 // CHECK1:       omp.loop.exit:
2125 // CHECK1-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
2126 // CHECK1-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
2127 // CHECK1-NEXT:    [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
2128 // CHECK1-NEXT:    br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
2129 // CHECK1:       .omp.final.then:
2130 // CHECK1-NEXT:    store i32 10, i32* [[I]], align 4
2131 // CHECK1-NEXT:    br label [[DOTOMP_FINAL_DONE]]
2132 // CHECK1:       .omp.final.done:
2133 // CHECK1-NEXT:    ret void
2134 //
2135 //
2136 // CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
2137 // CHECK1-SAME: () #[[ATTR5]] {
2138 // CHECK1-NEXT:  entry:
2139 // CHECK1-NEXT:    call void @__tgt_register_requires(i64 1)
2140 // CHECK1-NEXT:    ret void
2141 //
2142 //
2143 // CHECK3-LABEL: define {{[^@]+}}@_Z3fooi
2144 // CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0:[0-9]+]] {
2145 // CHECK3-NEXT:  entry:
2146 // CHECK3-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
2147 // CHECK3-NEXT:    [[A:%.*]] = alloca i32, align 4
2148 // CHECK3-NEXT:    [[AA:%.*]] = alloca i16, align 2
2149 // CHECK3-NEXT:    [[B:%.*]] = alloca [10 x float], align 4
2150 // CHECK3-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 4
2151 // CHECK3-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 4
2152 // CHECK3-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 8
2153 // CHECK3-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i32, align 4
2154 // CHECK3-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4
2155 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
2156 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
2157 // CHECK3-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
2158 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
2159 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR__CASTED3:%.*]] = alloca i32, align 4
2160 // CHECK3-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4
2161 // CHECK3-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4
2162 // CHECK3-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4
2163 // CHECK3-NEXT:    [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4
2164 // CHECK3-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
2165 // CHECK3-NEXT:    [[AA_CASTED4:%.*]] = alloca i32, align 4
2166 // CHECK3-NEXT:    [[DOTOFFLOAD_BASEPTRS6:%.*]] = alloca [1 x i8*], align 4
2167 // CHECK3-NEXT:    [[DOTOFFLOAD_PTRS7:%.*]] = alloca [1 x i8*], align 4
2168 // CHECK3-NEXT:    [[DOTOFFLOAD_MAPPERS8:%.*]] = alloca [1 x i8*], align 4
2169 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 4
2170 // CHECK3-NEXT:    [[A_CASTED9:%.*]] = alloca i32, align 4
2171 // CHECK3-NEXT:    [[AA_CASTED10:%.*]] = alloca i32, align 4
2172 // CHECK3-NEXT:    [[DOTOFFLOAD_BASEPTRS12:%.*]] = alloca [2 x i8*], align 4
2173 // CHECK3-NEXT:    [[DOTOFFLOAD_PTRS13:%.*]] = alloca [2 x i8*], align 4
2174 // CHECK3-NEXT:    [[DOTOFFLOAD_MAPPERS14:%.*]] = alloca [2 x i8*], align 4
2175 // CHECK3-NEXT:    [[_TMP15:%.*]] = alloca i32, align 4
2176 // CHECK3-NEXT:    [[A_CASTED19:%.*]] = alloca i32, align 4
2177 // CHECK3-NEXT:    [[DOTOFFLOAD_BASEPTRS22:%.*]] = alloca [9 x i8*], align 4
2178 // CHECK3-NEXT:    [[DOTOFFLOAD_PTRS23:%.*]] = alloca [9 x i8*], align 4
2179 // CHECK3-NEXT:    [[DOTOFFLOAD_MAPPERS24:%.*]] = alloca [9 x i8*], align 4
2180 // CHECK3-NEXT:    [[DOTOFFLOAD_SIZES:%.*]] = alloca [9 x i64], align 4
2181 // CHECK3-NEXT:    [[_TMP25:%.*]] = alloca i32, align 4
2182 // CHECK3-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]])
2183 // CHECK3-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
2184 // CHECK3-NEXT:    store i32 0, i32* [[A]], align 4
2185 // CHECK3-NEXT:    store i16 0, i16* [[AA]], align 2
2186 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
2187 // CHECK3-NEXT:    [[TMP2:%.*]] = call i8* @llvm.stacksave()
2188 // CHECK3-NEXT:    store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4
2189 // CHECK3-NEXT:    [[VLA:%.*]] = alloca float, i32 [[TMP1]], align 4
2190 // CHECK3-NEXT:    store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
2191 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
2192 // CHECK3-NEXT:    [[TMP4:%.*]] = mul nuw i32 5, [[TMP3]]
2193 // CHECK3-NEXT:    [[VLA1:%.*]] = alloca double, i32 [[TMP4]], align 8
2194 // CHECK3-NEXT:    store i32 [[TMP3]], i32* [[__VLA_EXPR1]], align 4
2195 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
2196 // CHECK3-NEXT:    store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_]], align 4
2197 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, i32* [[A]], align 4
2198 // CHECK3-NEXT:    store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_2]], align 4
2199 // CHECK3-NEXT:    [[TMP7:%.*]] = load i16, i16* [[AA]], align 2
2200 // CHECK3-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
2201 // CHECK3-NEXT:    store i16 [[TMP7]], i16* [[CONV]], align 2
2202 // CHECK3-NEXT:    [[TMP8:%.*]] = load i32, i32* [[AA_CASTED]], align 4
2203 // CHECK3-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
2204 // CHECK3-NEXT:    store i32 [[TMP9]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
2205 // CHECK3-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
2206 // CHECK3-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
2207 // CHECK3-NEXT:    store i32 [[TMP11]], i32* [[DOTCAPTURE_EXPR__CASTED3]], align 4
2208 // CHECK3-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED3]], align 4
2209 // CHECK3-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
2210 // CHECK3-NEXT:    [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i32*
2211 // CHECK3-NEXT:    store i32 [[TMP8]], i32* [[TMP14]], align 4
2212 // CHECK3-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
2213 // CHECK3-NEXT:    [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i32*
2214 // CHECK3-NEXT:    store i32 [[TMP8]], i32* [[TMP16]], align 4
2215 // CHECK3-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
2216 // CHECK3-NEXT:    store i8* null, i8** [[TMP17]], align 4
2217 // CHECK3-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
2218 // CHECK3-NEXT:    [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32*
2219 // CHECK3-NEXT:    store i32 [[TMP10]], i32* [[TMP19]], align 4
2220 // CHECK3-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
2221 // CHECK3-NEXT:    [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32*
2222 // CHECK3-NEXT:    store i32 [[TMP10]], i32* [[TMP21]], align 4
2223 // CHECK3-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
2224 // CHECK3-NEXT:    store i8* null, i8** [[TMP22]], align 4
2225 // CHECK3-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
2226 // CHECK3-NEXT:    [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i32*
2227 // CHECK3-NEXT:    store i32 [[TMP12]], i32* [[TMP24]], align 4
2228 // CHECK3-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
2229 // CHECK3-NEXT:    [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i32*
2230 // CHECK3-NEXT:    store i32 [[TMP12]], i32* [[TMP26]], align 4
2231 // CHECK3-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
2232 // CHECK3-NEXT:    store i8* null, i8** [[TMP27]], align 4
2233 // CHECK3-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
2234 // CHECK3-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
2235 // CHECK3-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 0
2236 // CHECK3-NEXT:    [[TMP31:%.*]] = load i16, i16* [[AA]], align 2
2237 // CHECK3-NEXT:    store i16 [[TMP31]], i16* [[TMP30]], align 4
2238 // CHECK3-NEXT:    [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 1
2239 // CHECK3-NEXT:    [[TMP33:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
2240 // CHECK3-NEXT:    store i32 [[TMP33]], i32* [[TMP32]], align 4
2241 // CHECK3-NEXT:    [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 2
2242 // CHECK3-NEXT:    [[TMP35:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
2243 // CHECK3-NEXT:    store i32 [[TMP35]], i32* [[TMP34]], align 4
2244 // CHECK3-NEXT:    [[TMP36:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 1, i32 72, i32 12, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1)
2245 // CHECK3-NEXT:    [[TMP37:%.*]] = bitcast i8* [[TMP36]] to %struct.kmp_task_t_with_privates*
2246 // CHECK3-NEXT:    [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP37]], i32 0, i32 0
2247 // CHECK3-NEXT:    [[TMP39:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP38]], i32 0, i32 0
2248 // CHECK3-NEXT:    [[TMP40:%.*]] = load i8*, i8** [[TMP39]], align 4
2249 // CHECK3-NEXT:    [[TMP41:%.*]] = bitcast %struct.anon* [[AGG_CAPTURED]] to i8*
2250 // CHECK3-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP40]], i8* align 4 [[TMP41]], i32 12, i1 false)
2251 // CHECK3-NEXT:    [[TMP42:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP37]], i32 0, i32 1
2252 // CHECK3-NEXT:    [[TMP43:%.*]] = bitcast i8* [[TMP40]] to %struct.anon*
2253 // CHECK3-NEXT:    [[TMP44:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 0
2254 // CHECK3-NEXT:    [[TMP45:%.*]] = bitcast [3 x i64]* [[TMP44]] to i8*
2255 // CHECK3-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP45]], i8* align 4 bitcast ([3 x i64]* @.offload_sizes to i8*), i32 24, i1 false)
2256 // CHECK3-NEXT:    [[TMP46:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 1
2257 // CHECK3-NEXT:    [[TMP47:%.*]] = bitcast [3 x i8*]* [[TMP46]] to i8*
2258 // CHECK3-NEXT:    [[TMP48:%.*]] = bitcast i8** [[TMP28]] to i8*
2259 // CHECK3-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP47]], i8* align 4 [[TMP48]], i32 12, i1 false)
2260 // CHECK3-NEXT:    [[TMP49:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 2
2261 // CHECK3-NEXT:    [[TMP50:%.*]] = bitcast [3 x i8*]* [[TMP49]] to i8*
2262 // CHECK3-NEXT:    [[TMP51:%.*]] = bitcast i8** [[TMP29]] to i8*
2263 // CHECK3-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP50]], i8* align 4 [[TMP51]], i32 12, i1 false)
2264 // CHECK3-NEXT:    [[TMP52:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 3
2265 // CHECK3-NEXT:    [[TMP53:%.*]] = load i16, i16* [[AA]], align 2
2266 // CHECK3-NEXT:    store i16 [[TMP53]], i16* [[TMP52]], align 4
2267 // CHECK3-NEXT:    [[TMP54:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i8* [[TMP36]])
2268 // CHECK3-NEXT:    [[TMP55:%.*]] = load i32, i32* [[A]], align 4
2269 // CHECK3-NEXT:    store i32 [[TMP55]], i32* [[A_CASTED]], align 4
2270 // CHECK3-NEXT:    [[TMP56:%.*]] = load i32, i32* [[A_CASTED]], align 4
2271 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104(i32 [[TMP56]]) #[[ATTR4:[0-9]+]]
2272 // CHECK3-NEXT:    [[TMP57:%.*]] = load i16, i16* [[AA]], align 2
2273 // CHECK3-NEXT:    [[CONV5:%.*]] = bitcast i32* [[AA_CASTED4]] to i16*
2274 // CHECK3-NEXT:    store i16 [[TMP57]], i16* [[CONV5]], align 2
2275 // CHECK3-NEXT:    [[TMP58:%.*]] = load i32, i32* [[AA_CASTED4]], align 4
2276 // CHECK3-NEXT:    [[TMP59:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0
2277 // CHECK3-NEXT:    [[TMP60:%.*]] = bitcast i8** [[TMP59]] to i32*
2278 // CHECK3-NEXT:    store i32 [[TMP58]], i32* [[TMP60]], align 4
2279 // CHECK3-NEXT:    [[TMP61:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0
2280 // CHECK3-NEXT:    [[TMP62:%.*]] = bitcast i8** [[TMP61]] to i32*
2281 // CHECK3-NEXT:    store i32 [[TMP58]], i32* [[TMP62]], align 4
2282 // CHECK3-NEXT:    [[TMP63:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS8]], i32 0, i32 0
2283 // CHECK3-NEXT:    store i8* null, i8** [[TMP63]], align 4
2284 // CHECK3-NEXT:    [[TMP64:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0
2285 // CHECK3-NEXT:    [[TMP65:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0
2286 // CHECK3-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
2287 // CHECK3-NEXT:    [[TMP66:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
2288 // CHECK3-NEXT:    store i32 1, i32* [[TMP66]], align 4
2289 // CHECK3-NEXT:    [[TMP67:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
2290 // CHECK3-NEXT:    store i32 1, i32* [[TMP67]], align 4
2291 // CHECK3-NEXT:    [[TMP68:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
2292 // CHECK3-NEXT:    store i8** [[TMP64]], i8*** [[TMP68]], align 4
2293 // CHECK3-NEXT:    [[TMP69:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
2294 // CHECK3-NEXT:    store i8** [[TMP65]], i8*** [[TMP69]], align 4
2295 // CHECK3-NEXT:    [[TMP70:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
2296 // CHECK3-NEXT:    store i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.4, i32 0, i32 0), i64** [[TMP70]], align 4
2297 // CHECK3-NEXT:    [[TMP71:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
2298 // CHECK3-NEXT:    store i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.5, i32 0, i32 0), i64** [[TMP71]], align 4
2299 // CHECK3-NEXT:    [[TMP72:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
2300 // CHECK3-NEXT:    store i8** null, i8*** [[TMP72]], align 4
2301 // CHECK3-NEXT:    [[TMP73:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
2302 // CHECK3-NEXT:    store i8** null, i8*** [[TMP73]], align 4
2303 // CHECK3-NEXT:    [[TMP74:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
2304 // CHECK3-NEXT:    store i64 10, i64* [[TMP74]], align 8
2305 // CHECK3-NEXT:    [[TMP75:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB2]], i64 -1, i32 0, i32 1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
2306 // CHECK3-NEXT:    [[TMP76:%.*]] = icmp ne i32 [[TMP75]], 0
2307 // CHECK3-NEXT:    br i1 [[TMP76]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
2308 // CHECK3:       omp_offload.failed:
2309 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111(i32 [[TMP58]]) #[[ATTR4]]
2310 // CHECK3-NEXT:    br label [[OMP_OFFLOAD_CONT]]
2311 // CHECK3:       omp_offload.cont:
2312 // CHECK3-NEXT:    [[TMP77:%.*]] = load i32, i32* [[A]], align 4
2313 // CHECK3-NEXT:    store i32 [[TMP77]], i32* [[A_CASTED9]], align 4
2314 // CHECK3-NEXT:    [[TMP78:%.*]] = load i32, i32* [[A_CASTED9]], align 4
2315 // CHECK3-NEXT:    [[TMP79:%.*]] = load i16, i16* [[AA]], align 2
2316 // CHECK3-NEXT:    [[CONV11:%.*]] = bitcast i32* [[AA_CASTED10]] to i16*
2317 // CHECK3-NEXT:    store i16 [[TMP79]], i16* [[CONV11]], align 2
2318 // CHECK3-NEXT:    [[TMP80:%.*]] = load i32, i32* [[AA_CASTED10]], align 4
2319 // CHECK3-NEXT:    [[TMP81:%.*]] = load i32, i32* [[N_ADDR]], align 4
2320 // CHECK3-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP81]], 10
2321 // CHECK3-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
2322 // CHECK3:       omp_if.then:
2323 // CHECK3-NEXT:    [[TMP82:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS12]], i32 0, i32 0
2324 // CHECK3-NEXT:    [[TMP83:%.*]] = bitcast i8** [[TMP82]] to i32*
2325 // CHECK3-NEXT:    store i32 [[TMP78]], i32* [[TMP83]], align 4
2326 // CHECK3-NEXT:    [[TMP84:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS13]], i32 0, i32 0
2327 // CHECK3-NEXT:    [[TMP85:%.*]] = bitcast i8** [[TMP84]] to i32*
2328 // CHECK3-NEXT:    store i32 [[TMP78]], i32* [[TMP85]], align 4
2329 // CHECK3-NEXT:    [[TMP86:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS14]], i32 0, i32 0
2330 // CHECK3-NEXT:    store i8* null, i8** [[TMP86]], align 4
2331 // CHECK3-NEXT:    [[TMP87:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS12]], i32 0, i32 1
2332 // CHECK3-NEXT:    [[TMP88:%.*]] = bitcast i8** [[TMP87]] to i32*
2333 // CHECK3-NEXT:    store i32 [[TMP80]], i32* [[TMP88]], align 4
2334 // CHECK3-NEXT:    [[TMP89:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS13]], i32 0, i32 1
2335 // CHECK3-NEXT:    [[TMP90:%.*]] = bitcast i8** [[TMP89]] to i32*
2336 // CHECK3-NEXT:    store i32 [[TMP80]], i32* [[TMP90]], align 4
2337 // CHECK3-NEXT:    [[TMP91:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS14]], i32 0, i32 1
2338 // CHECK3-NEXT:    store i8* null, i8** [[TMP91]], align 4
2339 // CHECK3-NEXT:    [[TMP92:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS12]], i32 0, i32 0
2340 // CHECK3-NEXT:    [[TMP93:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS13]], i32 0, i32 0
2341 // CHECK3-NEXT:    [[KERNEL_ARGS16:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
2342 // CHECK3-NEXT:    [[TMP94:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS16]], i32 0, i32 0
2343 // CHECK3-NEXT:    store i32 1, i32* [[TMP94]], align 4
2344 // CHECK3-NEXT:    [[TMP95:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS16]], i32 0, i32 1
2345 // CHECK3-NEXT:    store i32 2, i32* [[TMP95]], align 4
2346 // CHECK3-NEXT:    [[TMP96:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS16]], i32 0, i32 2
2347 // CHECK3-NEXT:    store i8** [[TMP92]], i8*** [[TMP96]], align 4
2348 // CHECK3-NEXT:    [[TMP97:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS16]], i32 0, i32 3
2349 // CHECK3-NEXT:    store i8** [[TMP93]], i8*** [[TMP97]], align 4
2350 // CHECK3-NEXT:    [[TMP98:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS16]], i32 0, i32 4
2351 // CHECK3-NEXT:    store i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.7, i32 0, i32 0), i64** [[TMP98]], align 4
2352 // CHECK3-NEXT:    [[TMP99:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS16]], i32 0, i32 5
2353 // CHECK3-NEXT:    store i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.8, i32 0, i32 0), i64** [[TMP99]], align 4
2354 // CHECK3-NEXT:    [[TMP100:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS16]], i32 0, i32 6
2355 // CHECK3-NEXT:    store i8** null, i8*** [[TMP100]], align 4
2356 // CHECK3-NEXT:    [[TMP101:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS16]], i32 0, i32 7
2357 // CHECK3-NEXT:    store i8** null, i8*** [[TMP101]], align 4
2358 // CHECK3-NEXT:    [[TMP102:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS16]], i32 0, i32 8
2359 // CHECK3-NEXT:    store i64 10, i64* [[TMP102]], align 8
2360 // CHECK3-NEXT:    [[TMP103:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB2]], i64 -1, i32 0, i32 1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS16]])
2361 // CHECK3-NEXT:    [[TMP104:%.*]] = icmp ne i32 [[TMP103]], 0
2362 // CHECK3-NEXT:    br i1 [[TMP104]], label [[OMP_OFFLOAD_FAILED17:%.*]], label [[OMP_OFFLOAD_CONT18:%.*]]
2363 // CHECK3:       omp_offload.failed17:
2364 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i32 [[TMP78]], i32 [[TMP80]]) #[[ATTR4]]
2365 // CHECK3-NEXT:    br label [[OMP_OFFLOAD_CONT18]]
2366 // CHECK3:       omp_offload.cont18:
2367 // CHECK3-NEXT:    br label [[OMP_IF_END:%.*]]
2368 // CHECK3:       omp_if.else:
2369 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i32 [[TMP78]], i32 [[TMP80]]) #[[ATTR4]]
2370 // CHECK3-NEXT:    br label [[OMP_IF_END]]
2371 // CHECK3:       omp_if.end:
2372 // CHECK3-NEXT:    [[TMP105:%.*]] = load i32, i32* [[A]], align 4
2373 // CHECK3-NEXT:    store i32 [[TMP105]], i32* [[A_CASTED19]], align 4
2374 // CHECK3-NEXT:    [[TMP106:%.*]] = load i32, i32* [[A_CASTED19]], align 4
2375 // CHECK3-NEXT:    [[TMP107:%.*]] = load i32, i32* [[N_ADDR]], align 4
2376 // CHECK3-NEXT:    [[CMP20:%.*]] = icmp sgt i32 [[TMP107]], 20
2377 // CHECK3-NEXT:    br i1 [[CMP20]], label [[OMP_IF_THEN21:%.*]], label [[OMP_IF_ELSE29:%.*]]
2378 // CHECK3:       omp_if.then21:
2379 // CHECK3-NEXT:    [[TMP108:%.*]] = mul nuw i32 [[TMP1]], 4
2380 // CHECK3-NEXT:    [[TMP109:%.*]] = sext i32 [[TMP108]] to i64
2381 // CHECK3-NEXT:    [[TMP110:%.*]] = mul nuw i32 5, [[TMP3]]
2382 // CHECK3-NEXT:    [[TMP111:%.*]] = mul nuw i32 [[TMP110]], 8
2383 // CHECK3-NEXT:    [[TMP112:%.*]] = sext i32 [[TMP111]] to i64
2384 // CHECK3-NEXT:    [[TMP113:%.*]] = bitcast [9 x i64]* [[DOTOFFLOAD_SIZES]] to i8*
2385 // CHECK3-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP113]], i8* align 4 bitcast ([9 x i64]* @.offload_sizes.10 to i8*), i32 72, i1 false)
2386 // CHECK3-NEXT:    [[TMP114:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 0
2387 // CHECK3-NEXT:    [[TMP115:%.*]] = bitcast i8** [[TMP114]] to i32*
2388 // CHECK3-NEXT:    store i32 [[TMP106]], i32* [[TMP115]], align 4
2389 // CHECK3-NEXT:    [[TMP116:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS23]], i32 0, i32 0
2390 // CHECK3-NEXT:    [[TMP117:%.*]] = bitcast i8** [[TMP116]] to i32*
2391 // CHECK3-NEXT:    store i32 [[TMP106]], i32* [[TMP117]], align 4
2392 // CHECK3-NEXT:    [[TMP118:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS24]], i32 0, i32 0
2393 // CHECK3-NEXT:    store i8* null, i8** [[TMP118]], align 4
2394 // CHECK3-NEXT:    [[TMP119:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 1
2395 // CHECK3-NEXT:    [[TMP120:%.*]] = bitcast i8** [[TMP119]] to [10 x float]**
2396 // CHECK3-NEXT:    store [10 x float]* [[B]], [10 x float]** [[TMP120]], align 4
2397 // CHECK3-NEXT:    [[TMP121:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS23]], i32 0, i32 1
2398 // CHECK3-NEXT:    [[TMP122:%.*]] = bitcast i8** [[TMP121]] to [10 x float]**
2399 // CHECK3-NEXT:    store [10 x float]* [[B]], [10 x float]** [[TMP122]], align 4
2400 // CHECK3-NEXT:    [[TMP123:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS24]], i32 0, i32 1
2401 // CHECK3-NEXT:    store i8* null, i8** [[TMP123]], align 4
2402 // CHECK3-NEXT:    [[TMP124:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 2
2403 // CHECK3-NEXT:    [[TMP125:%.*]] = bitcast i8** [[TMP124]] to i32*
2404 // CHECK3-NEXT:    store i32 [[TMP1]], i32* [[TMP125]], align 4
2405 // CHECK3-NEXT:    [[TMP126:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS23]], i32 0, i32 2
2406 // CHECK3-NEXT:    [[TMP127:%.*]] = bitcast i8** [[TMP126]] to i32*
2407 // CHECK3-NEXT:    store i32 [[TMP1]], i32* [[TMP127]], align 4
2408 // CHECK3-NEXT:    [[TMP128:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS24]], i32 0, i32 2
2409 // CHECK3-NEXT:    store i8* null, i8** [[TMP128]], align 4
2410 // CHECK3-NEXT:    [[TMP129:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 3
2411 // CHECK3-NEXT:    [[TMP130:%.*]] = bitcast i8** [[TMP129]] to float**
2412 // CHECK3-NEXT:    store float* [[VLA]], float** [[TMP130]], align 4
2413 // CHECK3-NEXT:    [[TMP131:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS23]], i32 0, i32 3
2414 // CHECK3-NEXT:    [[TMP132:%.*]] = bitcast i8** [[TMP131]] to float**
2415 // CHECK3-NEXT:    store float* [[VLA]], float** [[TMP132]], align 4
2416 // CHECK3-NEXT:    [[TMP133:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3
2417 // CHECK3-NEXT:    store i64 [[TMP109]], i64* [[TMP133]], align 4
2418 // CHECK3-NEXT:    [[TMP134:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS24]], i32 0, i32 3
2419 // CHECK3-NEXT:    store i8* null, i8** [[TMP134]], align 4
2420 // CHECK3-NEXT:    [[TMP135:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 4
2421 // CHECK3-NEXT:    [[TMP136:%.*]] = bitcast i8** [[TMP135]] to [5 x [10 x double]]**
2422 // CHECK3-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP136]], align 4
2423 // CHECK3-NEXT:    [[TMP137:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS23]], i32 0, i32 4
2424 // CHECK3-NEXT:    [[TMP138:%.*]] = bitcast i8** [[TMP137]] to [5 x [10 x double]]**
2425 // CHECK3-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP138]], align 4
2426 // CHECK3-NEXT:    [[TMP139:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS24]], i32 0, i32 4
2427 // CHECK3-NEXT:    store i8* null, i8** [[TMP139]], align 4
2428 // CHECK3-NEXT:    [[TMP140:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 5
2429 // CHECK3-NEXT:    [[TMP141:%.*]] = bitcast i8** [[TMP140]] to i32*
2430 // CHECK3-NEXT:    store i32 5, i32* [[TMP141]], align 4
2431 // CHECK3-NEXT:    [[TMP142:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS23]], i32 0, i32 5
2432 // CHECK3-NEXT:    [[TMP143:%.*]] = bitcast i8** [[TMP142]] to i32*
2433 // CHECK3-NEXT:    store i32 5, i32* [[TMP143]], align 4
2434 // CHECK3-NEXT:    [[TMP144:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS24]], i32 0, i32 5
2435 // CHECK3-NEXT:    store i8* null, i8** [[TMP144]], align 4
2436 // CHECK3-NEXT:    [[TMP145:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 6
2437 // CHECK3-NEXT:    [[TMP146:%.*]] = bitcast i8** [[TMP145]] to i32*
2438 // CHECK3-NEXT:    store i32 [[TMP3]], i32* [[TMP146]], align 4
2439 // CHECK3-NEXT:    [[TMP147:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS23]], i32 0, i32 6
2440 // CHECK3-NEXT:    [[TMP148:%.*]] = bitcast i8** [[TMP147]] to i32*
2441 // CHECK3-NEXT:    store i32 [[TMP3]], i32* [[TMP148]], align 4
2442 // CHECK3-NEXT:    [[TMP149:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS24]], i32 0, i32 6
2443 // CHECK3-NEXT:    store i8* null, i8** [[TMP149]], align 4
2444 // CHECK3-NEXT:    [[TMP150:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 7
2445 // CHECK3-NEXT:    [[TMP151:%.*]] = bitcast i8** [[TMP150]] to double**
2446 // CHECK3-NEXT:    store double* [[VLA1]], double** [[TMP151]], align 4
2447 // CHECK3-NEXT:    [[TMP152:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS23]], i32 0, i32 7
2448 // CHECK3-NEXT:    [[TMP153:%.*]] = bitcast i8** [[TMP152]] to double**
2449 // CHECK3-NEXT:    store double* [[VLA1]], double** [[TMP153]], align 4
2450 // CHECK3-NEXT:    [[TMP154:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7
2451 // CHECK3-NEXT:    store i64 [[TMP112]], i64* [[TMP154]], align 4
2452 // CHECK3-NEXT:    [[TMP155:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS24]], i32 0, i32 7
2453 // CHECK3-NEXT:    store i8* null, i8** [[TMP155]], align 4
2454 // CHECK3-NEXT:    [[TMP156:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 8
2455 // CHECK3-NEXT:    [[TMP157:%.*]] = bitcast i8** [[TMP156]] to %struct.TT**
2456 // CHECK3-NEXT:    store %struct.TT* [[D]], %struct.TT** [[TMP157]], align 4
2457 // CHECK3-NEXT:    [[TMP158:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS23]], i32 0, i32 8
2458 // CHECK3-NEXT:    [[TMP159:%.*]] = bitcast i8** [[TMP158]] to %struct.TT**
2459 // CHECK3-NEXT:    store %struct.TT* [[D]], %struct.TT** [[TMP159]], align 4
2460 // CHECK3-NEXT:    [[TMP160:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS24]], i32 0, i32 8
2461 // CHECK3-NEXT:    store i8* null, i8** [[TMP160]], align 4
2462 // CHECK3-NEXT:    [[TMP161:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 0
2463 // CHECK3-NEXT:    [[TMP162:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS23]], i32 0, i32 0
2464 // CHECK3-NEXT:    [[TMP163:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
2465 // CHECK3-NEXT:    [[KERNEL_ARGS26:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
2466 // CHECK3-NEXT:    [[TMP164:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS26]], i32 0, i32 0
2467 // CHECK3-NEXT:    store i32 1, i32* [[TMP164]], align 4
2468 // CHECK3-NEXT:    [[TMP165:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS26]], i32 0, i32 1
2469 // CHECK3-NEXT:    store i32 9, i32* [[TMP165]], align 4
2470 // CHECK3-NEXT:    [[TMP166:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS26]], i32 0, i32 2
2471 // CHECK3-NEXT:    store i8** [[TMP161]], i8*** [[TMP166]], align 4
2472 // CHECK3-NEXT:    [[TMP167:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS26]], i32 0, i32 3
2473 // CHECK3-NEXT:    store i8** [[TMP162]], i8*** [[TMP167]], align 4
2474 // CHECK3-NEXT:    [[TMP168:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS26]], i32 0, i32 4
2475 // CHECK3-NEXT:    store i64* [[TMP163]], i64** [[TMP168]], align 4
2476 // CHECK3-NEXT:    [[TMP169:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS26]], i32 0, i32 5
2477 // CHECK3-NEXT:    store i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_maptypes.11, i32 0, i32 0), i64** [[TMP169]], align 4
2478 // CHECK3-NEXT:    [[TMP170:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS26]], i32 0, i32 6
2479 // CHECK3-NEXT:    store i8** null, i8*** [[TMP170]], align 4
2480 // CHECK3-NEXT:    [[TMP171:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS26]], i32 0, i32 7
2481 // CHECK3-NEXT:    store i8** null, i8*** [[TMP171]], align 4
2482 // CHECK3-NEXT:    [[TMP172:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS26]], i32 0, i32 8
2483 // CHECK3-NEXT:    store i64 10, i64* [[TMP172]], align 8
2484 // CHECK3-NEXT:    [[TMP173:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB2]], i64 -1, i32 0, i32 1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS26]])
2485 // CHECK3-NEXT:    [[TMP174:%.*]] = icmp ne i32 [[TMP173]], 0
2486 // CHECK3-NEXT:    br i1 [[TMP174]], label [[OMP_OFFLOAD_FAILED27:%.*]], label [[OMP_OFFLOAD_CONT28:%.*]]
2487 // CHECK3:       omp_offload.failed27:
2488 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i32 [[TMP106]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR4]]
2489 // CHECK3-NEXT:    br label [[OMP_OFFLOAD_CONT28]]
2490 // CHECK3:       omp_offload.cont28:
2491 // CHECK3-NEXT:    br label [[OMP_IF_END30:%.*]]
2492 // CHECK3:       omp_if.else29:
2493 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i32 [[TMP106]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR4]]
2494 // CHECK3-NEXT:    br label [[OMP_IF_END30]]
2495 // CHECK3:       omp_if.end30:
2496 // CHECK3-NEXT:    [[TMP175:%.*]] = load i32, i32* [[A]], align 4
2497 // CHECK3-NEXT:    [[TMP176:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
2498 // CHECK3-NEXT:    call void @llvm.stackrestore(i8* [[TMP176]])
2499 // CHECK3-NEXT:    ret i32 [[TMP175]]
2500 //
2501 //
2502 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97
2503 // CHECK3-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]], i32 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] {
2504 // CHECK3-NEXT:  entry:
2505 // CHECK3-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
2506 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
2507 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4
2508 // CHECK3-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
2509 // CHECK3-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]])
2510 // CHECK3-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
2511 // CHECK3-NEXT:    store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
2512 // CHECK3-NEXT:    store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4
2513 // CHECK3-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
2514 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
2515 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4
2516 // CHECK3-NEXT:    call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
2517 // CHECK3-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
2518 // CHECK3-NEXT:    [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
2519 // CHECK3-NEXT:    store i16 [[TMP3]], i16* [[CONV3]], align 2
2520 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
2521 // CHECK3-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]])
2522 // CHECK3-NEXT:    ret void
2523 //
2524 //
2525 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined.
2526 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR3:[0-9]+]] {
2527 // CHECK3-NEXT:  entry:
2528 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
2529 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
2530 // CHECK3-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
2531 // CHECK3-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
2532 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 4
2533 // CHECK3-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
2534 // CHECK3-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
2535 // CHECK3-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2536 // CHECK3-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2537 // CHECK3-NEXT:    [[I:%.*]] = alloca i32, align 4
2538 // CHECK3-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
2539 // CHECK3-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
2540 // CHECK3-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
2541 // CHECK3-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
2542 // CHECK3-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
2543 // CHECK3-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
2544 // CHECK3-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
2545 // CHECK3-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
2546 // CHECK3-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
2547 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
2548 // CHECK3-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
2549 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2550 // CHECK3-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
2551 // CHECK3-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2552 // CHECK3:       cond.true:
2553 // CHECK3-NEXT:    br label [[COND_END:%.*]]
2554 // CHECK3:       cond.false:
2555 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2556 // CHECK3-NEXT:    br label [[COND_END]]
2557 // CHECK3:       cond.end:
2558 // CHECK3-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
2559 // CHECK3-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
2560 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
2561 // CHECK3-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
2562 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
2563 // CHECK3:       omp.inner.for.cond:
2564 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
2565 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !11
2566 // CHECK3-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
2567 // CHECK3-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2568 // CHECK3:       omp.inner.for.body:
2569 // CHECK3-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
2570 // CHECK3-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
2571 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
2572 // CHECK3-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11
2573 // CHECK3-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
2574 // CHECK3:       omp.body.continue:
2575 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
2576 // CHECK3:       omp.inner.for.inc:
2577 // CHECK3-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
2578 // CHECK3-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
2579 // CHECK3-NEXT:    store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
2580 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]
2581 // CHECK3:       omp.inner.for.end:
2582 // CHECK3-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
2583 // CHECK3:       omp.loop.exit:
2584 // CHECK3-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
2585 // CHECK3-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
2586 // CHECK3-NEXT:    [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0
2587 // CHECK3-NEXT:    br i1 [[TMP10]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
2588 // CHECK3:       .omp.final.then:
2589 // CHECK3-NEXT:    store i32 10, i32* [[I]], align 4
2590 // CHECK3-NEXT:    br label [[DOTOMP_FINAL_DONE]]
2591 // CHECK3:       .omp.final.done:
2592 // CHECK3-NEXT:    ret void
2593 //
2594 //
2595 // CHECK3-LABEL: define {{[^@]+}}@.omp_task_privates_map.
2596 // CHECK3-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], i16** noalias noundef [[TMP1:%.*]], [3 x i8*]** noalias noundef [[TMP2:%.*]], [3 x i8*]** noalias noundef [[TMP3:%.*]], [3 x i64]** noalias noundef [[TMP4:%.*]]) #[[ATTR5:[0-9]+]] {
2597 // CHECK3-NEXT:  entry:
2598 // CHECK3-NEXT:    [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 4
2599 // CHECK3-NEXT:    [[DOTADDR1:%.*]] = alloca i16**, align 4
2600 // CHECK3-NEXT:    [[DOTADDR2:%.*]] = alloca [3 x i8*]**, align 4
2601 // CHECK3-NEXT:    [[DOTADDR3:%.*]] = alloca [3 x i8*]**, align 4
2602 // CHECK3-NEXT:    [[DOTADDR4:%.*]] = alloca [3 x i64]**, align 4
2603 // CHECK3-NEXT:    store %struct..kmp_privates.t* [[TMP0]], %struct..kmp_privates.t** [[DOTADDR]], align 4
2604 // CHECK3-NEXT:    store i16** [[TMP1]], i16*** [[DOTADDR1]], align 4
2605 // CHECK3-NEXT:    store [3 x i8*]** [[TMP2]], [3 x i8*]*** [[DOTADDR2]], align 4
2606 // CHECK3-NEXT:    store [3 x i8*]** [[TMP3]], [3 x i8*]*** [[DOTADDR3]], align 4
2607 // CHECK3-NEXT:    store [3 x i64]** [[TMP4]], [3 x i64]*** [[DOTADDR4]], align 4
2608 // CHECK3-NEXT:    [[TMP5:%.*]] = load %struct..kmp_privates.t*, %struct..kmp_privates.t** [[DOTADDR]], align 4
2609 // CHECK3-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 0
2610 // CHECK3-NEXT:    [[TMP7:%.*]] = load [3 x i64]**, [3 x i64]*** [[DOTADDR4]], align 4
2611 // CHECK3-NEXT:    store [3 x i64]* [[TMP6]], [3 x i64]** [[TMP7]], align 4
2612 // CHECK3-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 1
2613 // CHECK3-NEXT:    [[TMP9:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR2]], align 4
2614 // CHECK3-NEXT:    store [3 x i8*]* [[TMP8]], [3 x i8*]** [[TMP9]], align 4
2615 // CHECK3-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 2
2616 // CHECK3-NEXT:    [[TMP11:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR3]], align 4
2617 // CHECK3-NEXT:    store [3 x i8*]* [[TMP10]], [3 x i8*]** [[TMP11]], align 4
2618 // CHECK3-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 3
2619 // CHECK3-NEXT:    [[TMP13:%.*]] = load i16**, i16*** [[DOTADDR1]], align 4
2620 // CHECK3-NEXT:    store i16* [[TMP12]], i16** [[TMP13]], align 4
2621 // CHECK3-NEXT:    ret void
2622 //
2623 //
2624 // CHECK3-LABEL: define {{[^@]+}}@.omp_task_entry.
2625 // CHECK3-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] {
2626 // CHECK3-NEXT:  entry:
2627 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
2628 // CHECK3-NEXT:    [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 4
2629 // CHECK3-NEXT:    [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 4
2630 // CHECK3-NEXT:    [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 4
2631 // CHECK3-NEXT:    [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 4
2632 // CHECK3-NEXT:    [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 4
2633 // CHECK3-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca i16*, align 4
2634 // CHECK3-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca [3 x i8*]*, align 4
2635 // CHECK3-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca [3 x i8*]*, align 4
2636 // CHECK3-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca [3 x i64]*, align 4
2637 // CHECK3-NEXT:    [[AA_CASTED_I:%.*]] = alloca i32, align 4
2638 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR__CASTED_I:%.*]] = alloca i32, align 4
2639 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR__CASTED4_I:%.*]] = alloca i32, align 4
2640 // CHECK3-NEXT:    [[KERNEL_ARGS_I:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
2641 // CHECK3-NEXT:    [[DOTADDR:%.*]] = alloca i32, align 4
2642 // CHECK3-NEXT:    [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 4
2643 // CHECK3-NEXT:    store i32 [[TMP0]], i32* [[DOTADDR]], align 4
2644 // CHECK3-NEXT:    store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4
2645 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4
2646 // CHECK3-NEXT:    [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4
2647 // CHECK3-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
2648 // CHECK3-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
2649 // CHECK3-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0
2650 // CHECK3-NEXT:    [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 4
2651 // CHECK3-NEXT:    [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon*
2652 // CHECK3-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1
2653 // CHECK3-NEXT:    [[TMP10:%.*]] = bitcast %struct..kmp_privates.t* [[TMP9]] to i8*
2654 // CHECK3-NEXT:    [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8*
2655 // CHECK3-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]])
2656 // CHECK3-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META21:![0-9]+]])
2657 // CHECK3-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META23:![0-9]+]])
2658 // CHECK3-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META25:![0-9]+]])
2659 // CHECK3-NEXT:    store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !27
2660 // CHECK3-NEXT:    store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 4, !noalias !27
2661 // CHECK3-NEXT:    store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !27
2662 // CHECK3-NEXT:    store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* @.omp_task_privates_map. to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !27
2663 // CHECK3-NEXT:    store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 4, !noalias !27
2664 // CHECK3-NEXT:    store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !27
2665 // CHECK3-NEXT:    [[TMP12:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !27
2666 // CHECK3-NEXT:    [[TMP13:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !27
2667 // CHECK3-NEXT:    [[TMP14:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !27
2668 // CHECK3-NEXT:    [[TMP15:%.*]] = bitcast void (i8*, ...)* [[TMP13]] to void (i8*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)*
2669 // CHECK3-NEXT:    call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR4]]
2670 // CHECK3-NEXT:    [[TMP16:%.*]] = load i16*, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 4, !noalias !27
2671 // CHECK3-NEXT:    [[TMP17:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 4, !noalias !27
2672 // CHECK3-NEXT:    [[TMP18:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 4, !noalias !27
2673 // CHECK3-NEXT:    [[TMP19:%.*]] = load [3 x i64]*, [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 4, !noalias !27
2674 // CHECK3-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP17]], i32 0, i32 0
2675 // CHECK3-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP18]], i32 0, i32 0
2676 // CHECK3-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[TMP19]], i32 0, i32 0
2677 // CHECK3-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP12]], i32 0, i32 1
2678 // CHECK3-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[TMP12]], i32 0, i32 2
2679 // CHECK3-NEXT:    [[TMP25:%.*]] = load i32, i32* [[TMP23]], align 4
2680 // CHECK3-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i32 0
2681 // CHECK3-NEXT:    store i32 1, i32* [[TMP26]], align 4, !noalias !27
2682 // CHECK3-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i32 1
2683 // CHECK3-NEXT:    store i32 3, i32* [[TMP27]], align 4, !noalias !27
2684 // CHECK3-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i32 2
2685 // CHECK3-NEXT:    store i8** [[TMP20]], i8*** [[TMP28]], align 4, !noalias !27
2686 // CHECK3-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i32 3
2687 // CHECK3-NEXT:    store i8** [[TMP21]], i8*** [[TMP29]], align 4, !noalias !27
2688 // CHECK3-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i32 4
2689 // CHECK3-NEXT:    store i64* [[TMP22]], i64** [[TMP30]], align 4, !noalias !27
2690 // CHECK3-NEXT:    [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i32 5
2691 // CHECK3-NEXT:    store i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i64** [[TMP31]], align 4, !noalias !27
2692 // CHECK3-NEXT:    [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i32 6
2693 // CHECK3-NEXT:    store i8** null, i8*** [[TMP32]], align 4, !noalias !27
2694 // CHECK3-NEXT:    [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i32 7
2695 // CHECK3-NEXT:    store i8** null, i8*** [[TMP33]], align 4, !noalias !27
2696 // CHECK3-NEXT:    [[TMP34:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i32 8
2697 // CHECK3-NEXT:    store i64 10, i64* [[TMP34]], align 8, !noalias !27
2698 // CHECK3-NEXT:    [[TMP35:%.*]] = call i32 @__tgt_target_kernel_nowait(%struct.ident_t* @[[GLOB2]], i64 -1, i32 [[TMP25]], i32 1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i8* null, i32 0, i8* null) #[[ATTR4]]
2699 // CHECK3-NEXT:    [[TMP36:%.*]] = icmp ne i32 [[TMP35]], 0
2700 // CHECK3-NEXT:    br i1 [[TMP36]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]]
2701 // CHECK3:       omp_offload.failed.i:
2702 // CHECK3-NEXT:    [[TMP37:%.*]] = load i16, i16* [[TMP16]], align 2
2703 // CHECK3-NEXT:    [[CONV_I:%.*]] = bitcast i32* [[AA_CASTED_I]] to i16*
2704 // CHECK3-NEXT:    store i16 [[TMP37]], i16* [[CONV_I]], align 2, !noalias !27
2705 // CHECK3-NEXT:    [[TMP38:%.*]] = load i32, i32* [[AA_CASTED_I]], align 4, !noalias !27
2706 // CHECK3-NEXT:    [[TMP39:%.*]] = load i32, i32* [[TMP23]], align 4
2707 // CHECK3-NEXT:    store i32 [[TMP39]], i32* [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias !27
2708 // CHECK3-NEXT:    [[TMP40:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias !27
2709 // CHECK3-NEXT:    [[TMP41:%.*]] = load i32, i32* [[TMP24]], align 4
2710 // CHECK3-NEXT:    store i32 [[TMP41]], i32* [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias !27
2711 // CHECK3-NEXT:    [[TMP42:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias !27
2712 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97(i32 [[TMP38]], i32 [[TMP40]], i32 [[TMP42]]) #[[ATTR4]]
2713 // CHECK3-NEXT:    br label [[DOTOMP_OUTLINED__1_EXIT]]
2714 // CHECK3:       .omp_outlined..1.exit:
2715 // CHECK3-NEXT:    ret i32 0
2716 //
2717 //
2718 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104
2719 // CHECK3-SAME: (i32 noundef [[A:%.*]]) #[[ATTR3]] {
2720 // CHECK3-NEXT:  entry:
2721 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
2722 // CHECK3-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
2723 // CHECK3-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
2724 // CHECK3-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
2725 // CHECK3-NEXT:    store i32 [[TMP0]], i32* [[A_CASTED]], align 4
2726 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
2727 // CHECK3-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]])
2728 // CHECK3-NEXT:    ret void
2729 //
2730 //
2731 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..2
2732 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]]) #[[ATTR3]] {
2733 // CHECK3-NEXT:  entry:
2734 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
2735 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
2736 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
2737 // CHECK3-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
2738 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 4
2739 // CHECK3-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
2740 // CHECK3-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
2741 // CHECK3-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2742 // CHECK3-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2743 // CHECK3-NEXT:    [[A1:%.*]] = alloca i32, align 4
2744 // CHECK3-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
2745 // CHECK3-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
2746 // CHECK3-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
2747 // CHECK3-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
2748 // CHECK3-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
2749 // CHECK3-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
2750 // CHECK3-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
2751 // CHECK3-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
2752 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
2753 // CHECK3-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
2754 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2755 // CHECK3-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
2756 // CHECK3-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2757 // CHECK3:       cond.true:
2758 // CHECK3-NEXT:    br label [[COND_END:%.*]]
2759 // CHECK3:       cond.false:
2760 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2761 // CHECK3-NEXT:    br label [[COND_END]]
2762 // CHECK3:       cond.end:
2763 // CHECK3-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
2764 // CHECK3-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
2765 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
2766 // CHECK3-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
2767 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
2768 // CHECK3:       omp.inner.for.cond:
2769 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2770 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2771 // CHECK3-NEXT:    [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
2772 // CHECK3-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2773 // CHECK3:       omp.inner.for.body:
2774 // CHECK3-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2775 // CHECK3-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
2776 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
2777 // CHECK3-NEXT:    store i32 [[ADD]], i32* [[A1]], align 4
2778 // CHECK3-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A1]], align 4
2779 // CHECK3-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
2780 // CHECK3-NEXT:    store i32 [[ADD3]], i32* [[A1]], align 4
2781 // CHECK3-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
2782 // CHECK3:       omp.body.continue:
2783 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
2784 // CHECK3:       omp.inner.for.inc:
2785 // CHECK3-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2786 // CHECK3-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP9]], 1
2787 // CHECK3-NEXT:    store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4
2788 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]]
2789 // CHECK3:       omp.inner.for.end:
2790 // CHECK3-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
2791 // CHECK3:       omp.loop.exit:
2792 // CHECK3-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
2793 // CHECK3-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
2794 // CHECK3-NEXT:    [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0
2795 // CHECK3-NEXT:    br i1 [[TMP11]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
2796 // CHECK3:       .omp.final.then:
2797 // CHECK3-NEXT:    store i32 10, i32* [[A_ADDR]], align 4
2798 // CHECK3-NEXT:    br label [[DOTOMP_FINAL_DONE]]
2799 // CHECK3:       .omp.final.done:
2800 // CHECK3-NEXT:    ret void
2801 //
2802 //
2803 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111
2804 // CHECK3-SAME: (i32 noundef [[AA:%.*]]) #[[ATTR2]] {
2805 // CHECK3-NEXT:  entry:
2806 // CHECK3-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
2807 // CHECK3-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
2808 // CHECK3-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
2809 // CHECK3-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
2810 // CHECK3-NEXT:    [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
2811 // CHECK3-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
2812 // CHECK3-NEXT:    store i16 [[TMP0]], i16* [[CONV1]], align 2
2813 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
2814 // CHECK3-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP1]])
2815 // CHECK3-NEXT:    ret void
2816 //
2817 //
2818 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..3
2819 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR3]] {
2820 // CHECK3-NEXT:  entry:
2821 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
2822 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
2823 // CHECK3-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
2824 // CHECK3-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
2825 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 4
2826 // CHECK3-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
2827 // CHECK3-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
2828 // CHECK3-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2829 // CHECK3-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2830 // CHECK3-NEXT:    [[I:%.*]] = alloca i32, align 4
2831 // CHECK3-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
2832 // CHECK3-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
2833 // CHECK3-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
2834 // CHECK3-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
2835 // CHECK3-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
2836 // CHECK3-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
2837 // CHECK3-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
2838 // CHECK3-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
2839 // CHECK3-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
2840 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
2841 // CHECK3-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
2842 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2843 // CHECK3-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
2844 // CHECK3-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2845 // CHECK3:       cond.true:
2846 // CHECK3-NEXT:    br label [[COND_END:%.*]]
2847 // CHECK3:       cond.false:
2848 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2849 // CHECK3-NEXT:    br label [[COND_END]]
2850 // CHECK3:       cond.end:
2851 // CHECK3-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
2852 // CHECK3-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
2853 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
2854 // CHECK3-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
2855 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
2856 // CHECK3:       omp.inner.for.cond:
2857 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30
2858 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !30
2859 // CHECK3-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
2860 // CHECK3-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2861 // CHECK3:       omp.inner.for.body:
2862 // CHECK3-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30
2863 // CHECK3-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
2864 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
2865 // CHECK3-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !30
2866 // CHECK3-NEXT:    [[TMP8:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !30
2867 // CHECK3-NEXT:    [[CONV2:%.*]] = sext i16 [[TMP8]] to i32
2868 // CHECK3-NEXT:    [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
2869 // CHECK3-NEXT:    [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
2870 // CHECK3-NEXT:    store i16 [[CONV4]], i16* [[CONV]], align 2, !llvm.access.group !30
2871 // CHECK3-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
2872 // CHECK3:       omp.body.continue:
2873 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
2874 // CHECK3:       omp.inner.for.inc:
2875 // CHECK3-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30
2876 // CHECK3-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP9]], 1
2877 // CHECK3-NEXT:    store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30
2878 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP31:![0-9]+]]
2879 // CHECK3:       omp.inner.for.end:
2880 // CHECK3-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
2881 // CHECK3:       omp.loop.exit:
2882 // CHECK3-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
2883 // CHECK3-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
2884 // CHECK3-NEXT:    [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0
2885 // CHECK3-NEXT:    br i1 [[TMP11]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
2886 // CHECK3:       .omp.final.then:
2887 // CHECK3-NEXT:    store i32 10, i32* [[I]], align 4
2888 // CHECK3-NEXT:    br label [[DOTOMP_FINAL_DONE]]
2889 // CHECK3:       .omp.final.done:
2890 // CHECK3-NEXT:    ret void
2891 //
2892 //
2893 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118
2894 // CHECK3-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] {
2895 // CHECK3-NEXT:  entry:
2896 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
2897 // CHECK3-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
2898 // CHECK3-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
2899 // CHECK3-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
2900 // CHECK3-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
2901 // CHECK3-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
2902 // CHECK3-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
2903 // CHECK3-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
2904 // CHECK3-NEXT:    store i32 [[TMP0]], i32* [[A_CASTED]], align 4
2905 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
2906 // CHECK3-NEXT:    [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
2907 // CHECK3-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
2908 // CHECK3-NEXT:    store i16 [[TMP2]], i16* [[CONV1]], align 2
2909 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
2910 // CHECK3-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]])
2911 // CHECK3-NEXT:    ret void
2912 //
2913 //
2914 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..6
2915 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR3]] {
2916 // CHECK3-NEXT:  entry:
2917 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
2918 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
2919 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
2920 // CHECK3-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
2921 // CHECK3-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
2922 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 4
2923 // CHECK3-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
2924 // CHECK3-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
2925 // CHECK3-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2926 // CHECK3-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2927 // CHECK3-NEXT:    [[I:%.*]] = alloca i32, align 4
2928 // CHECK3-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
2929 // CHECK3-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
2930 // CHECK3-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
2931 // CHECK3-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
2932 // CHECK3-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
2933 // CHECK3-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
2934 // CHECK3-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
2935 // CHECK3-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
2936 // CHECK3-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
2937 // CHECK3-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
2938 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
2939 // CHECK3-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
2940 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2941 // CHECK3-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
2942 // CHECK3-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2943 // CHECK3:       cond.true:
2944 // CHECK3-NEXT:    br label [[COND_END:%.*]]
2945 // CHECK3:       cond.false:
2946 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2947 // CHECK3-NEXT:    br label [[COND_END]]
2948 // CHECK3:       cond.end:
2949 // CHECK3-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
2950 // CHECK3-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
2951 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
2952 // CHECK3-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
2953 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
2954 // CHECK3:       omp.inner.for.cond:
2955 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33
2956 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !33
2957 // CHECK3-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
2958 // CHECK3-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2959 // CHECK3:       omp.inner.for.body:
2960 // CHECK3-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33
2961 // CHECK3-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
2962 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
2963 // CHECK3-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !33
2964 // CHECK3-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !33
2965 // CHECK3-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
2966 // CHECK3-NEXT:    store i32 [[ADD2]], i32* [[A_ADDR]], align 4, !llvm.access.group !33
2967 // CHECK3-NEXT:    [[TMP9:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !33
2968 // CHECK3-NEXT:    [[CONV3:%.*]] = sext i16 [[TMP9]] to i32
2969 // CHECK3-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
2970 // CHECK3-NEXT:    [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
2971 // CHECK3-NEXT:    store i16 [[CONV5]], i16* [[CONV]], align 2, !llvm.access.group !33
2972 // CHECK3-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
2973 // CHECK3:       omp.body.continue:
2974 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
2975 // CHECK3:       omp.inner.for.inc:
2976 // CHECK3-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33
2977 // CHECK3-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP10]], 1
2978 // CHECK3-NEXT:    store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33
2979 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP34:![0-9]+]]
2980 // CHECK3:       omp.inner.for.end:
2981 // CHECK3-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
2982 // CHECK3:       omp.loop.exit:
2983 // CHECK3-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
2984 // CHECK3-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
2985 // CHECK3-NEXT:    [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
2986 // CHECK3-NEXT:    br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
2987 // CHECK3:       .omp.final.then:
2988 // CHECK3-NEXT:    store i32 10, i32* [[I]], align 4
2989 // CHECK3-NEXT:    br label [[DOTOMP_FINAL_DONE]]
2990 // CHECK3:       .omp.final.done:
2991 // CHECK3-NEXT:    ret void
2992 //
2993 //
2994 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142
2995 // CHECK3-SAME: (i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] {
2996 // CHECK3-NEXT:  entry:
2997 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
2998 // CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
2999 // CHECK3-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
3000 // CHECK3-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 4
3001 // CHECK3-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
3002 // CHECK3-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
3003 // CHECK3-NEXT:    [[VLA_ADDR4:%.*]] = alloca i32, align 4
3004 // CHECK3-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 4
3005 // CHECK3-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
3006 // CHECK3-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
3007 // CHECK3-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
3008 // CHECK3-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
3009 // CHECK3-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
3010 // CHECK3-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 4
3011 // CHECK3-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
3012 // CHECK3-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
3013 // CHECK3-NEXT:    store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
3014 // CHECK3-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 4
3015 // CHECK3-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
3016 // CHECK3-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
3017 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
3018 // CHECK3-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
3019 // CHECK3-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
3020 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
3021 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
3022 // CHECK3-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
3023 // CHECK3-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
3024 // CHECK3-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
3025 // CHECK3-NEXT:    store i32 [[TMP8]], i32* [[A_CASTED]], align 4
3026 // CHECK3-NEXT:    [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4
3027 // CHECK3-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]])
3028 // CHECK3-NEXT:    ret void
3029 //
3030 //
3031 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..9
3032 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR3]] {
3033 // CHECK3-NEXT:  entry:
3034 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
3035 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
3036 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
3037 // CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
3038 // CHECK3-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
3039 // CHECK3-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 4
3040 // CHECK3-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
3041 // CHECK3-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
3042 // CHECK3-NEXT:    [[VLA_ADDR4:%.*]] = alloca i32, align 4
3043 // CHECK3-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 4
3044 // CHECK3-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
3045 // CHECK3-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
3046 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 4
3047 // CHECK3-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
3048 // CHECK3-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
3049 // CHECK3-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
3050 // CHECK3-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
3051 // CHECK3-NEXT:    [[I:%.*]] = alloca i32, align 4
3052 // CHECK3-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
3053 // CHECK3-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
3054 // CHECK3-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
3055 // CHECK3-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
3056 // CHECK3-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
3057 // CHECK3-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 4
3058 // CHECK3-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
3059 // CHECK3-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
3060 // CHECK3-NEXT:    store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
3061 // CHECK3-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 4
3062 // CHECK3-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
3063 // CHECK3-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
3064 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
3065 // CHECK3-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
3066 // CHECK3-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
3067 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
3068 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
3069 // CHECK3-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
3070 // CHECK3-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
3071 // CHECK3-NEXT:    [[ARRAYDECAY:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 0
3072 // CHECK3-NEXT:    call void @llvm.assume(i1 true) [ "align"(float* [[ARRAYDECAY]], i32 16) ]
3073 // CHECK3-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
3074 // CHECK3-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
3075 // CHECK3-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
3076 // CHECK3-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
3077 // CHECK3-NEXT:    [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
3078 // CHECK3-NEXT:    [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4
3079 // CHECK3-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
3080 // CHECK3-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
3081 // CHECK3-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP10]], 9
3082 // CHECK3-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
3083 // CHECK3:       cond.true:
3084 // CHECK3-NEXT:    br label [[COND_END:%.*]]
3085 // CHECK3:       cond.false:
3086 // CHECK3-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
3087 // CHECK3-NEXT:    br label [[COND_END]]
3088 // CHECK3:       cond.end:
3089 // CHECK3-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ]
3090 // CHECK3-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
3091 // CHECK3-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
3092 // CHECK3-NEXT:    store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4
3093 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
3094 // CHECK3:       omp.inner.for.cond:
3095 // CHECK3-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36
3096 // CHECK3-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !36
3097 // CHECK3-NEXT:    [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
3098 // CHECK3-NEXT:    br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
3099 // CHECK3:       omp.inner.for.body:
3100 // CHECK3-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36
3101 // CHECK3-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1
3102 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
3103 // CHECK3-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !36
3104 // CHECK3-NEXT:    [[TMP16:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !36
3105 // CHECK3-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP16]], 1
3106 // CHECK3-NEXT:    store i32 [[ADD6]], i32* [[A_ADDR]], align 4, !llvm.access.group !36
3107 // CHECK3-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2
3108 // CHECK3-NEXT:    [[TMP17:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !36
3109 // CHECK3-NEXT:    [[CONV:%.*]] = fpext float [[TMP17]] to double
3110 // CHECK3-NEXT:    [[ADD7:%.*]] = fadd double [[CONV]], 1.000000e+00
3111 // CHECK3-NEXT:    [[CONV8:%.*]] = fptrunc double [[ADD7]] to float
3112 // CHECK3-NEXT:    store float [[CONV8]], float* [[ARRAYIDX]], align 4, !llvm.access.group !36
3113 // CHECK3-NEXT:    [[ARRAYIDX9:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3
3114 // CHECK3-NEXT:    [[TMP18:%.*]] = load float, float* [[ARRAYIDX9]], align 4, !llvm.access.group !36
3115 // CHECK3-NEXT:    [[CONV10:%.*]] = fpext float [[TMP18]] to double
3116 // CHECK3-NEXT:    [[ADD11:%.*]] = fadd double [[CONV10]], 1.000000e+00
3117 // CHECK3-NEXT:    [[CONV12:%.*]] = fptrunc double [[ADD11]] to float
3118 // CHECK3-NEXT:    store float [[CONV12]], float* [[ARRAYIDX9]], align 4, !llvm.access.group !36
3119 // CHECK3-NEXT:    [[ARRAYIDX13:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1
3120 // CHECK3-NEXT:    [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX13]], i32 0, i32 2
3121 // CHECK3-NEXT:    [[TMP19:%.*]] = load double, double* [[ARRAYIDX14]], align 8, !llvm.access.group !36
3122 // CHECK3-NEXT:    [[ADD15:%.*]] = fadd double [[TMP19]], 1.000000e+00
3123 // CHECK3-NEXT:    store double [[ADD15]], double* [[ARRAYIDX14]], align 8, !llvm.access.group !36
3124 // CHECK3-NEXT:    [[TMP20:%.*]] = mul nsw i32 1, [[TMP5]]
3125 // CHECK3-NEXT:    [[ARRAYIDX16:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP20]]
3126 // CHECK3-NEXT:    [[ARRAYIDX17:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX16]], i32 3
3127 // CHECK3-NEXT:    [[TMP21:%.*]] = load double, double* [[ARRAYIDX17]], align 8, !llvm.access.group !36
3128 // CHECK3-NEXT:    [[ADD18:%.*]] = fadd double [[TMP21]], 1.000000e+00
3129 // CHECK3-NEXT:    store double [[ADD18]], double* [[ARRAYIDX17]], align 8, !llvm.access.group !36
3130 // CHECK3-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0
3131 // CHECK3-NEXT:    [[TMP22:%.*]] = load i64, i64* [[X]], align 4, !llvm.access.group !36
3132 // CHECK3-NEXT:    [[ADD19:%.*]] = add nsw i64 [[TMP22]], 1
3133 // CHECK3-NEXT:    store i64 [[ADD19]], i64* [[X]], align 4, !llvm.access.group !36
3134 // CHECK3-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1
3135 // CHECK3-NEXT:    [[TMP23:%.*]] = load i8, i8* [[Y]], align 4, !llvm.access.group !36
3136 // CHECK3-NEXT:    [[CONV20:%.*]] = sext i8 [[TMP23]] to i32
3137 // CHECK3-NEXT:    [[ADD21:%.*]] = add nsw i32 [[CONV20]], 1
3138 // CHECK3-NEXT:    [[CONV22:%.*]] = trunc i32 [[ADD21]] to i8
3139 // CHECK3-NEXT:    store i8 [[CONV22]], i8* [[Y]], align 4, !llvm.access.group !36
3140 // CHECK3-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
3141 // CHECK3:       omp.body.continue:
3142 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
3143 // CHECK3:       omp.inner.for.inc:
3144 // CHECK3-NEXT:    [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36
3145 // CHECK3-NEXT:    [[ADD23:%.*]] = add nsw i32 [[TMP24]], 1
3146 // CHECK3-NEXT:    store i32 [[ADD23]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36
3147 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP37:![0-9]+]]
3148 // CHECK3:       omp.inner.for.end:
3149 // CHECK3-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
3150 // CHECK3:       omp.loop.exit:
3151 // CHECK3-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]])
3152 // CHECK3-NEXT:    [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
3153 // CHECK3-NEXT:    [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
3154 // CHECK3-NEXT:    br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
3155 // CHECK3:       .omp.final.then:
3156 // CHECK3-NEXT:    store i32 10, i32* [[I]], align 4
3157 // CHECK3-NEXT:    br label [[DOTOMP_FINAL_DONE]]
3158 // CHECK3:       .omp.final.done:
3159 // CHECK3-NEXT:    ret void
3160 //
3161 //
3162 // CHECK3-LABEL: define {{[^@]+}}@_Z3bari
3163 // CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {
3164 // CHECK3-NEXT:  entry:
3165 // CHECK3-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
3166 // CHECK3-NEXT:    [[A:%.*]] = alloca i32, align 4
3167 // CHECK3-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4
3168 // CHECK3-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
3169 // CHECK3-NEXT:    store i32 0, i32* [[A]], align 4
3170 // CHECK3-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
3171 // CHECK3-NEXT:    [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]])
3172 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
3173 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
3174 // CHECK3-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
3175 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
3176 // CHECK3-NEXT:    [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP2]])
3177 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
3178 // CHECK3-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
3179 // CHECK3-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
3180 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
3181 // CHECK3-NEXT:    [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]])
3182 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
3183 // CHECK3-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
3184 // CHECK3-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
3185 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
3186 // CHECK3-NEXT:    [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]])
3187 // CHECK3-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
3188 // CHECK3-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
3189 // CHECK3-NEXT:    store i32 [[ADD6]], i32* [[A]], align 4
3190 // CHECK3-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
3191 // CHECK3-NEXT:    ret i32 [[TMP8]]
3192 //
3193 //
3194 // CHECK3-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
3195 // CHECK3-SAME: (%struct.S1* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 {
3196 // CHECK3-NEXT:  entry:
3197 // CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
3198 // CHECK3-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
3199 // CHECK3-NEXT:    [[B:%.*]] = alloca i32, align 4
3200 // CHECK3-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 4
3201 // CHECK3-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 4
3202 // CHECK3-NEXT:    [[B_CASTED:%.*]] = alloca i32, align 4
3203 // CHECK3-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4
3204 // CHECK3-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4
3205 // CHECK3-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4
3206 // CHECK3-NEXT:    [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 4
3207 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 4
3208 // CHECK3-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
3209 // CHECK3-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
3210 // CHECK3-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
3211 // CHECK3-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
3212 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
3213 // CHECK3-NEXT:    store i32 [[ADD]], i32* [[B]], align 4
3214 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
3215 // CHECK3-NEXT:    [[TMP2:%.*]] = call i8* @llvm.stacksave()
3216 // CHECK3-NEXT:    store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4
3217 // CHECK3-NEXT:    [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]
3218 // CHECK3-NEXT:    [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2
3219 // CHECK3-NEXT:    store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
3220 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, i32* [[B]], align 4
3221 // CHECK3-NEXT:    store i32 [[TMP4]], i32* [[B_CASTED]], align 4
3222 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4
3223 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
3224 // CHECK3-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 60
3225 // CHECK3-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
3226 // CHECK3:       omp_if.then:
3227 // CHECK3-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
3228 // CHECK3-NEXT:    [[TMP7:%.*]] = mul nuw i32 2, [[TMP1]]
3229 // CHECK3-NEXT:    [[TMP8:%.*]] = mul nuw i32 [[TMP7]], 2
3230 // CHECK3-NEXT:    [[TMP9:%.*]] = sext i32 [[TMP8]] to i64
3231 // CHECK3-NEXT:    [[TMP10:%.*]] = bitcast [5 x i64]* [[DOTOFFLOAD_SIZES]] to i8*
3232 // CHECK3-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP10]], i8* align 4 bitcast ([5 x i64]* @.offload_sizes.13 to i8*), i32 40, i1 false)
3233 // CHECK3-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
3234 // CHECK3-NEXT:    [[TMP12:%.*]] = bitcast i8** [[TMP11]] to %struct.S1**
3235 // CHECK3-NEXT:    store %struct.S1* [[THIS1]], %struct.S1** [[TMP12]], align 4
3236 // CHECK3-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
3237 // CHECK3-NEXT:    [[TMP14:%.*]] = bitcast i8** [[TMP13]] to double**
3238 // CHECK3-NEXT:    store double* [[A]], double** [[TMP14]], align 4
3239 // CHECK3-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
3240 // CHECK3-NEXT:    store i8* null, i8** [[TMP15]], align 4
3241 // CHECK3-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
3242 // CHECK3-NEXT:    [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32*
3243 // CHECK3-NEXT:    store i32 [[TMP5]], i32* [[TMP17]], align 4
3244 // CHECK3-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
3245 // CHECK3-NEXT:    [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32*
3246 // CHECK3-NEXT:    store i32 [[TMP5]], i32* [[TMP19]], align 4
3247 // CHECK3-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
3248 // CHECK3-NEXT:    store i8* null, i8** [[TMP20]], align 4
3249 // CHECK3-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
3250 // CHECK3-NEXT:    [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i32*
3251 // CHECK3-NEXT:    store i32 2, i32* [[TMP22]], align 4
3252 // CHECK3-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
3253 // CHECK3-NEXT:    [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i32*
3254 // CHECK3-NEXT:    store i32 2, i32* [[TMP24]], align 4
3255 // CHECK3-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
3256 // CHECK3-NEXT:    store i8* null, i8** [[TMP25]], align 4
3257 // CHECK3-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
3258 // CHECK3-NEXT:    [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i32*
3259 // CHECK3-NEXT:    store i32 [[TMP1]], i32* [[TMP27]], align 4
3260 // CHECK3-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
3261 // CHECK3-NEXT:    [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i32*
3262 // CHECK3-NEXT:    store i32 [[TMP1]], i32* [[TMP29]], align 4
3263 // CHECK3-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
3264 // CHECK3-NEXT:    store i8* null, i8** [[TMP30]], align 4
3265 // CHECK3-NEXT:    [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
3266 // CHECK3-NEXT:    [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i16**
3267 // CHECK3-NEXT:    store i16* [[VLA]], i16** [[TMP32]], align 4
3268 // CHECK3-NEXT:    [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
3269 // CHECK3-NEXT:    [[TMP34:%.*]] = bitcast i8** [[TMP33]] to i16**
3270 // CHECK3-NEXT:    store i16* [[VLA]], i16** [[TMP34]], align 4
3271 // CHECK3-NEXT:    [[TMP35:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4
3272 // CHECK3-NEXT:    store i64 [[TMP9]], i64* [[TMP35]], align 4
3273 // CHECK3-NEXT:    [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4
3274 // CHECK3-NEXT:    store i8* null, i8** [[TMP36]], align 4
3275 // CHECK3-NEXT:    [[TMP37:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
3276 // CHECK3-NEXT:    [[TMP38:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
3277 // CHECK3-NEXT:    [[TMP39:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
3278 // CHECK3-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
3279 // CHECK3-NEXT:    [[TMP40:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
3280 // CHECK3-NEXT:    store i32 1, i32* [[TMP40]], align 4
3281 // CHECK3-NEXT:    [[TMP41:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
3282 // CHECK3-NEXT:    store i32 5, i32* [[TMP41]], align 4
3283 // CHECK3-NEXT:    [[TMP42:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
3284 // CHECK3-NEXT:    store i8** [[TMP37]], i8*** [[TMP42]], align 4
3285 // CHECK3-NEXT:    [[TMP43:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
3286 // CHECK3-NEXT:    store i8** [[TMP38]], i8*** [[TMP43]], align 4
3287 // CHECK3-NEXT:    [[TMP44:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
3288 // CHECK3-NEXT:    store i64* [[TMP39]], i64** [[TMP44]], align 4
3289 // CHECK3-NEXT:    [[TMP45:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
3290 // CHECK3-NEXT:    store i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.14, i32 0, i32 0), i64** [[TMP45]], align 4
3291 // CHECK3-NEXT:    [[TMP46:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
3292 // CHECK3-NEXT:    store i8** null, i8*** [[TMP46]], align 4
3293 // CHECK3-NEXT:    [[TMP47:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
3294 // CHECK3-NEXT:    store i8** null, i8*** [[TMP47]], align 4
3295 // CHECK3-NEXT:    [[TMP48:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
3296 // CHECK3-NEXT:    store i64 10, i64* [[TMP48]], align 8
3297 // CHECK3-NEXT:    [[TMP49:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB2]], i64 -1, i32 0, i32 1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
3298 // CHECK3-NEXT:    [[TMP50:%.*]] = icmp ne i32 [[TMP49]], 0
3299 // CHECK3-NEXT:    br i1 [[TMP50]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
3300 // CHECK3:       omp_offload.failed:
3301 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR4]]
3302 // CHECK3-NEXT:    br label [[OMP_OFFLOAD_CONT]]
3303 // CHECK3:       omp_offload.cont:
3304 // CHECK3-NEXT:    br label [[OMP_IF_END:%.*]]
3305 // CHECK3:       omp_if.else:
3306 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR4]]
3307 // CHECK3-NEXT:    br label [[OMP_IF_END]]
3308 // CHECK3:       omp_if.end:
3309 // CHECK3-NEXT:    [[TMP51:%.*]] = mul nsw i32 1, [[TMP1]]
3310 // CHECK3-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP51]]
3311 // CHECK3-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
3312 // CHECK3-NEXT:    [[TMP52:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2
3313 // CHECK3-NEXT:    [[CONV:%.*]] = sext i16 [[TMP52]] to i32
3314 // CHECK3-NEXT:    [[TMP53:%.*]] = load i32, i32* [[B]], align 4
3315 // CHECK3-NEXT:    [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP53]]
3316 // CHECK3-NEXT:    [[TMP54:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
3317 // CHECK3-NEXT:    call void @llvm.stackrestore(i8* [[TMP54]])
3318 // CHECK3-NEXT:    ret i32 [[ADD3]]
3319 //
3320 //
3321 // CHECK3-LABEL: define {{[^@]+}}@_ZL7fstatici
3322 // CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {
3323 // CHECK3-NEXT:  entry:
3324 // CHECK3-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
3325 // CHECK3-NEXT:    [[A:%.*]] = alloca i32, align 4
3326 // CHECK3-NEXT:    [[AA:%.*]] = alloca i16, align 2
3327 // CHECK3-NEXT:    [[AAA:%.*]] = alloca i8, align 1
3328 // CHECK3-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
3329 // CHECK3-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
3330 // CHECK3-NEXT:    [[N_CASTED:%.*]] = alloca i32, align 4
3331 // CHECK3-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
3332 // CHECK3-NEXT:    [[AAA_CASTED:%.*]] = alloca i32, align 4
3333 // CHECK3-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4
3334 // CHECK3-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4
3335 // CHECK3-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4
3336 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 4
3337 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
3338 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
3339 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4
3340 // CHECK3-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
3341 // CHECK3-NEXT:    store i32 0, i32* [[A]], align 4
3342 // CHECK3-NEXT:    store i16 0, i16* [[AA]], align 2
3343 // CHECK3-NEXT:    store i8 0, i8* [[AAA]], align 1
3344 // CHECK3-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
3345 // CHECK3-NEXT:    store i32 [[TMP0]], i32* [[A_CASTED]], align 4
3346 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
3347 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
3348 // CHECK3-NEXT:    store i32 [[TMP2]], i32* [[N_CASTED]], align 4
3349 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, i32* [[N_CASTED]], align 4
3350 // CHECK3-NEXT:    [[TMP4:%.*]] = load i16, i16* [[AA]], align 2
3351 // CHECK3-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
3352 // CHECK3-NEXT:    store i16 [[TMP4]], i16* [[CONV]], align 2
3353 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, i32* [[AA_CASTED]], align 4
3354 // CHECK3-NEXT:    [[TMP6:%.*]] = load i8, i8* [[AAA]], align 1
3355 // CHECK3-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
3356 // CHECK3-NEXT:    store i8 [[TMP6]], i8* [[CONV1]], align 1
3357 // CHECK3-NEXT:    [[TMP7:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
3358 // CHECK3-NEXT:    [[TMP8:%.*]] = load i32, i32* [[N_ADDR]], align 4
3359 // CHECK3-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP8]], 50
3360 // CHECK3-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
3361 // CHECK3:       omp_if.then:
3362 // CHECK3-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
3363 // CHECK3-NEXT:    [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32*
3364 // CHECK3-NEXT:    store i32 [[TMP1]], i32* [[TMP10]], align 4
3365 // CHECK3-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
3366 // CHECK3-NEXT:    [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32*
3367 // CHECK3-NEXT:    store i32 [[TMP1]], i32* [[TMP12]], align 4
3368 // CHECK3-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
3369 // CHECK3-NEXT:    store i8* null, i8** [[TMP13]], align 4
3370 // CHECK3-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
3371 // CHECK3-NEXT:    [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32*
3372 // CHECK3-NEXT:    store i32 [[TMP3]], i32* [[TMP15]], align 4
3373 // CHECK3-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
3374 // CHECK3-NEXT:    [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32*
3375 // CHECK3-NEXT:    store i32 [[TMP3]], i32* [[TMP17]], align 4
3376 // CHECK3-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
3377 // CHECK3-NEXT:    store i8* null, i8** [[TMP18]], align 4
3378 // CHECK3-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
3379 // CHECK3-NEXT:    [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32*
3380 // CHECK3-NEXT:    store i32 [[TMP5]], i32* [[TMP20]], align 4
3381 // CHECK3-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
3382 // CHECK3-NEXT:    [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i32*
3383 // CHECK3-NEXT:    store i32 [[TMP5]], i32* [[TMP22]], align 4
3384 // CHECK3-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
3385 // CHECK3-NEXT:    store i8* null, i8** [[TMP23]], align 4
3386 // CHECK3-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
3387 // CHECK3-NEXT:    [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i32*
3388 // CHECK3-NEXT:    store i32 [[TMP7]], i32* [[TMP25]], align 4
3389 // CHECK3-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
3390 // CHECK3-NEXT:    [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i32*
3391 // CHECK3-NEXT:    store i32 [[TMP7]], i32* [[TMP27]], align 4
3392 // CHECK3-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
3393 // CHECK3-NEXT:    store i8* null, i8** [[TMP28]], align 4
3394 // CHECK3-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
3395 // CHECK3-NEXT:    [[TMP30:%.*]] = bitcast i8** [[TMP29]] to [10 x i32]**
3396 // CHECK3-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP30]], align 4
3397 // CHECK3-NEXT:    [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
3398 // CHECK3-NEXT:    [[TMP32:%.*]] = bitcast i8** [[TMP31]] to [10 x i32]**
3399 // CHECK3-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP32]], align 4
3400 // CHECK3-NEXT:    [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4
3401 // CHECK3-NEXT:    store i8* null, i8** [[TMP33]], align 4
3402 // CHECK3-NEXT:    [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
3403 // CHECK3-NEXT:    [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
3404 // CHECK3-NEXT:    [[TMP36:%.*]] = load i32, i32* [[A]], align 4
3405 // CHECK3-NEXT:    store i32 [[TMP36]], i32* [[DOTCAPTURE_EXPR_]], align 4
3406 // CHECK3-NEXT:    [[TMP37:%.*]] = load i32, i32* [[N_ADDR]], align 4
3407 // CHECK3-NEXT:    store i32 [[TMP37]], i32* [[DOTCAPTURE_EXPR_2]], align 4
3408 // CHECK3-NEXT:    [[TMP38:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
3409 // CHECK3-NEXT:    [[TMP39:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
3410 // CHECK3-NEXT:    [[SUB:%.*]] = sub i32 [[TMP38]], [[TMP39]]
3411 // CHECK3-NEXT:    [[SUB4:%.*]] = sub i32 [[SUB]], 1
3412 // CHECK3-NEXT:    [[ADD:%.*]] = add i32 [[SUB4]], 1
3413 // CHECK3-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], 1
3414 // CHECK3-NEXT:    [[SUB5:%.*]] = sub i32 [[DIV]], 1
3415 // CHECK3-NEXT:    store i32 [[SUB5]], i32* [[DOTCAPTURE_EXPR_3]], align 4
3416 // CHECK3-NEXT:    [[TMP40:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
3417 // CHECK3-NEXT:    [[ADD6:%.*]] = add i32 [[TMP40]], 1
3418 // CHECK3-NEXT:    [[TMP41:%.*]] = zext i32 [[ADD6]] to i64
3419 // CHECK3-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
3420 // CHECK3-NEXT:    [[TMP42:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
3421 // CHECK3-NEXT:    store i32 1, i32* [[TMP42]], align 4
3422 // CHECK3-NEXT:    [[TMP43:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
3423 // CHECK3-NEXT:    store i32 5, i32* [[TMP43]], align 4
3424 // CHECK3-NEXT:    [[TMP44:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
3425 // CHECK3-NEXT:    store i8** [[TMP34]], i8*** [[TMP44]], align 4
3426 // CHECK3-NEXT:    [[TMP45:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
3427 // CHECK3-NEXT:    store i8** [[TMP35]], i8*** [[TMP45]], align 4
3428 // CHECK3-NEXT:    [[TMP46:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
3429 // CHECK3-NEXT:    store i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes.16, i32 0, i32 0), i64** [[TMP46]], align 4
3430 // CHECK3-NEXT:    [[TMP47:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
3431 // CHECK3-NEXT:    store i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.17, i32 0, i32 0), i64** [[TMP47]], align 4
3432 // CHECK3-NEXT:    [[TMP48:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
3433 // CHECK3-NEXT:    store i8** null, i8*** [[TMP48]], align 4
3434 // CHECK3-NEXT:    [[TMP49:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
3435 // CHECK3-NEXT:    store i8** null, i8*** [[TMP49]], align 4
3436 // CHECK3-NEXT:    [[TMP50:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
3437 // CHECK3-NEXT:    store i64 [[TMP41]], i64* [[TMP50]], align 8
3438 // CHECK3-NEXT:    [[TMP51:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB2]], i64 -1, i32 0, i32 1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
3439 // CHECK3-NEXT:    [[TMP52:%.*]] = icmp ne i32 [[TMP51]], 0
3440 // CHECK3-NEXT:    br i1 [[TMP52]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
3441 // CHECK3:       omp_offload.failed:
3442 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], i32 [[TMP7]], [10 x i32]* [[B]]) #[[ATTR4]]
3443 // CHECK3-NEXT:    br label [[OMP_OFFLOAD_CONT]]
3444 // CHECK3:       omp_offload.cont:
3445 // CHECK3-NEXT:    br label [[OMP_IF_END:%.*]]
3446 // CHECK3:       omp_if.else:
3447 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], i32 [[TMP7]], [10 x i32]* [[B]]) #[[ATTR4]]
3448 // CHECK3-NEXT:    br label [[OMP_IF_END]]
3449 // CHECK3:       omp_if.end:
3450 // CHECK3-NEXT:    [[TMP53:%.*]] = load i32, i32* [[A]], align 4
3451 // CHECK3-NEXT:    ret i32 [[TMP53]]
3452 //
3453 //
3454 // CHECK3-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
3455 // CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat {
3456 // CHECK3-NEXT:  entry:
3457 // CHECK3-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
3458 // CHECK3-NEXT:    [[A:%.*]] = alloca i32, align 4
3459 // CHECK3-NEXT:    [[AA:%.*]] = alloca i16, align 2
3460 // CHECK3-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
3461 // CHECK3-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
3462 // CHECK3-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
3463 // CHECK3-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4
3464 // CHECK3-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4
3465 // CHECK3-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4
3466 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 4
3467 // CHECK3-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
3468 // CHECK3-NEXT:    store i32 0, i32* [[A]], align 4
3469 // CHECK3-NEXT:    store i16 0, i16* [[AA]], align 2
3470 // CHECK3-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
3471 // CHECK3-NEXT:    store i32 [[TMP0]], i32* [[A_CASTED]], align 4
3472 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
3473 // CHECK3-NEXT:    [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
3474 // CHECK3-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
3475 // CHECK3-NEXT:    store i16 [[TMP2]], i16* [[CONV]], align 2
3476 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
3477 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
3478 // CHECK3-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40
3479 // CHECK3-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
3480 // CHECK3:       omp_if.then:
3481 // CHECK3-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
3482 // CHECK3-NEXT:    [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i32*
3483 // CHECK3-NEXT:    store i32 [[TMP1]], i32* [[TMP6]], align 4
3484 // CHECK3-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
3485 // CHECK3-NEXT:    [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32*
3486 // CHECK3-NEXT:    store i32 [[TMP1]], i32* [[TMP8]], align 4
3487 // CHECK3-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
3488 // CHECK3-NEXT:    store i8* null, i8** [[TMP9]], align 4
3489 // CHECK3-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
3490 // CHECK3-NEXT:    [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i32*
3491 // CHECK3-NEXT:    store i32 [[TMP3]], i32* [[TMP11]], align 4
3492 // CHECK3-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
3493 // CHECK3-NEXT:    [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32*
3494 // CHECK3-NEXT:    store i32 [[TMP3]], i32* [[TMP13]], align 4
3495 // CHECK3-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
3496 // CHECK3-NEXT:    store i8* null, i8** [[TMP14]], align 4
3497 // CHECK3-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
3498 // CHECK3-NEXT:    [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]**
3499 // CHECK3-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 4
3500 // CHECK3-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
3501 // CHECK3-NEXT:    [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]**
3502 // CHECK3-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 4
3503 // CHECK3-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
3504 // CHECK3-NEXT:    store i8* null, i8** [[TMP19]], align 4
3505 // CHECK3-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
3506 // CHECK3-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
3507 // CHECK3-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
3508 // CHECK3-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
3509 // CHECK3-NEXT:    store i32 1, i32* [[TMP22]], align 4
3510 // CHECK3-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
3511 // CHECK3-NEXT:    store i32 3, i32* [[TMP23]], align 4
3512 // CHECK3-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
3513 // CHECK3-NEXT:    store i8** [[TMP20]], i8*** [[TMP24]], align 4
3514 // CHECK3-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
3515 // CHECK3-NEXT:    store i8** [[TMP21]], i8*** [[TMP25]], align 4
3516 // CHECK3-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
3517 // CHECK3-NEXT:    store i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.19, i32 0, i32 0), i64** [[TMP26]], align 4
3518 // CHECK3-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
3519 // CHECK3-NEXT:    store i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.20, i32 0, i32 0), i64** [[TMP27]], align 4
3520 // CHECK3-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
3521 // CHECK3-NEXT:    store i8** null, i8*** [[TMP28]], align 4
3522 // CHECK3-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
3523 // CHECK3-NEXT:    store i8** null, i8*** [[TMP29]], align 4
3524 // CHECK3-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
3525 // CHECK3-NEXT:    store i64 10, i64* [[TMP30]], align 8
3526 // CHECK3-NEXT:    [[TMP31:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB2]], i64 -1, i32 0, i32 1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
3527 // CHECK3-NEXT:    [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0
3528 // CHECK3-NEXT:    br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
3529 // CHECK3:       omp_offload.failed:
3530 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]]
3531 // CHECK3-NEXT:    br label [[OMP_OFFLOAD_CONT]]
3532 // CHECK3:       omp_offload.cont:
3533 // CHECK3-NEXT:    br label [[OMP_IF_END:%.*]]
3534 // CHECK3:       omp_if.else:
3535 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]]
3536 // CHECK3-NEXT:    br label [[OMP_IF_END]]
3537 // CHECK3:       omp_if.end:
3538 // CHECK3-NEXT:    [[TMP33:%.*]] = load i32, i32* [[A]], align 4
3539 // CHECK3-NEXT:    ret i32 [[TMP33]]
3540 //
3541 //
3542 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215
3543 // CHECK3-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {
3544 // CHECK3-NEXT:  entry:
3545 // CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
3546 // CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
3547 // CHECK3-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
3548 // CHECK3-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
3549 // CHECK3-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 4
3550 // CHECK3-NEXT:    [[B_CASTED:%.*]] = alloca i32, align 4
3551 // CHECK3-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
3552 // CHECK3-NEXT:    store i32 [[B]], i32* [[B_ADDR]], align 4
3553 // CHECK3-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
3554 // CHECK3-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
3555 // CHECK3-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 4
3556 // CHECK3-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
3557 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
3558 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
3559 // CHECK3-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
3560 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4
3561 // CHECK3-NEXT:    store i32 [[TMP4]], i32* [[B_CASTED]], align 4
3562 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4
3563 // CHECK3-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..12 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]])
3564 // CHECK3-NEXT:    ret void
3565 //
3566 //
3567 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..12
3568 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] {
3569 // CHECK3-NEXT:  entry:
3570 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
3571 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
3572 // CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
3573 // CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
3574 // CHECK3-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
3575 // CHECK3-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
3576 // CHECK3-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 4
3577 // CHECK3-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
3578 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 4
3579 // CHECK3-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
3580 // CHECK3-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
3581 // CHECK3-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
3582 // CHECK3-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
3583 // CHECK3-NEXT:    [[I:%.*]] = alloca i32, align 4
3584 // CHECK3-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
3585 // CHECK3-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
3586 // CHECK3-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
3587 // CHECK3-NEXT:    store i32 [[B]], i32* [[B_ADDR]], align 4
3588 // CHECK3-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
3589 // CHECK3-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
3590 // CHECK3-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 4
3591 // CHECK3-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
3592 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
3593 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
3594 // CHECK3-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
3595 // CHECK3-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
3596 // CHECK3-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
3597 // CHECK3-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
3598 // CHECK3-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
3599 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
3600 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
3601 // CHECK3-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
3602 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
3603 // CHECK3-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 9
3604 // CHECK3-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
3605 // CHECK3:       cond.true:
3606 // CHECK3-NEXT:    br label [[COND_END:%.*]]
3607 // CHECK3:       cond.false:
3608 // CHECK3-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
3609 // CHECK3-NEXT:    br label [[COND_END]]
3610 // CHECK3:       cond.end:
3611 // CHECK3-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
3612 // CHECK3-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
3613 // CHECK3-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
3614 // CHECK3-NEXT:    store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
3615 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
3616 // CHECK3:       omp.inner.for.cond:
3617 // CHECK3-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39
3618 // CHECK3-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !39
3619 // CHECK3-NEXT:    [[CMP3:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
3620 // CHECK3-NEXT:    br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
3621 // CHECK3:       omp.inner.for.body:
3622 // CHECK3-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39
3623 // CHECK3-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
3624 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
3625 // CHECK3-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !39
3626 // CHECK3-NEXT:    [[TMP12:%.*]] = load i32, i32* [[B_ADDR]], align 4, !llvm.access.group !39
3627 // CHECK3-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP12]] to double
3628 // CHECK3-NEXT:    [[ADD4:%.*]] = fadd double [[CONV]], 1.500000e+00
3629 // CHECK3-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
3630 // CHECK3-NEXT:    store double [[ADD4]], double* [[A]], align 4, !llvm.access.group !39
3631 // CHECK3-NEXT:    [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
3632 // CHECK3-NEXT:    [[TMP13:%.*]] = load double, double* [[A5]], align 4, !llvm.access.group !39
3633 // CHECK3-NEXT:    [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00
3634 // CHECK3-NEXT:    store double [[INC]], double* [[A5]], align 4, !llvm.access.group !39
3635 // CHECK3-NEXT:    [[CONV6:%.*]] = fptosi double [[INC]] to i16
3636 // CHECK3-NEXT:    [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]]
3637 // CHECK3-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP14]]
3638 // CHECK3-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
3639 // CHECK3-NEXT:    store i16 [[CONV6]], i16* [[ARRAYIDX7]], align 2, !llvm.access.group !39
3640 // CHECK3-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
3641 // CHECK3:       omp.body.continue:
3642 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
3643 // CHECK3:       omp.inner.for.inc:
3644 // CHECK3-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39
3645 // CHECK3-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP15]], 1
3646 // CHECK3-NEXT:    store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39
3647 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP40:![0-9]+]]
3648 // CHECK3:       omp.inner.for.end:
3649 // CHECK3-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
3650 // CHECK3:       omp.loop.exit:
3651 // CHECK3-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
3652 // CHECK3-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
3653 // CHECK3-NEXT:    [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0
3654 // CHECK3-NEXT:    br i1 [[TMP17]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
3655 // CHECK3:       .omp.final.then:
3656 // CHECK3-NEXT:    store i32 10, i32* [[I]], align 4
3657 // CHECK3-NEXT:    br label [[DOTOMP_FINAL_DONE]]
3658 // CHECK3:       .omp.final.done:
3659 // CHECK3-NEXT:    ret void
3660 //
3661 //
3662 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197
3663 // CHECK3-SAME: (i32 noundef [[A:%.*]], i32 noundef [[N:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
3664 // CHECK3-NEXT:  entry:
3665 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
3666 // CHECK3-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
3667 // CHECK3-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
3668 // CHECK3-NEXT:    [[AAA_ADDR:%.*]] = alloca i32, align 4
3669 // CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
3670 // CHECK3-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
3671 // CHECK3-NEXT:    [[N_CASTED:%.*]] = alloca i32, align 4
3672 // CHECK3-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
3673 // CHECK3-NEXT:    [[AAA_CASTED:%.*]] = alloca i32, align 4
3674 // CHECK3-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
3675 // CHECK3-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
3676 // CHECK3-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
3677 // CHECK3-NEXT:    store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
3678 // CHECK3-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
3679 // CHECK3-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
3680 // CHECK3-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
3681 // CHECK3-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
3682 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
3683 // CHECK3-NEXT:    store i32 [[TMP1]], i32* [[A_CASTED]], align 4
3684 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
3685 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
3686 // CHECK3-NEXT:    store i32 [[TMP3]], i32* [[N_CASTED]], align 4
3687 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_CASTED]], align 4
3688 // CHECK3-NEXT:    [[TMP5:%.*]] = load i16, i16* [[CONV]], align 2
3689 // CHECK3-NEXT:    [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
3690 // CHECK3-NEXT:    store i16 [[TMP5]], i16* [[CONV2]], align 2
3691 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, i32* [[AA_CASTED]], align 4
3692 // CHECK3-NEXT:    [[TMP7:%.*]] = load i8, i8* [[CONV1]], align 1
3693 // CHECK3-NEXT:    [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
3694 // CHECK3-NEXT:    store i8 [[TMP7]], i8* [[CONV3]], align 1
3695 // CHECK3-NEXT:    [[TMP8:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
3696 // CHECK3-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, [10 x i32]*)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP8]], [10 x i32]* [[TMP0]])
3697 // CHECK3-NEXT:    ret void
3698 //
3699 //
3700 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..15
3701 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[N:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] {
3702 // CHECK3-NEXT:  entry:
3703 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
3704 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
3705 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
3706 // CHECK3-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
3707 // CHECK3-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
3708 // CHECK3-NEXT:    [[AAA_ADDR:%.*]] = alloca i32, align 4
3709 // CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
3710 // CHECK3-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
3711 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 4
3712 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
3713 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
3714 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4
3715 // CHECK3-NEXT:    [[I:%.*]] = alloca i32, align 4
3716 // CHECK3-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
3717 // CHECK3-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
3718 // CHECK3-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
3719 // CHECK3-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
3720 // CHECK3-NEXT:    [[I6:%.*]] = alloca i32, align 4
3721 // CHECK3-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
3722 // CHECK3-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
3723 // CHECK3-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
3724 // CHECK3-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
3725 // CHECK3-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
3726 // CHECK3-NEXT:    store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
3727 // CHECK3-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
3728 // CHECK3-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
3729 // CHECK3-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
3730 // CHECK3-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
3731 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
3732 // CHECK3-NEXT:    store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
3733 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
3734 // CHECK3-NEXT:    store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4
3735 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
3736 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
3737 // CHECK3-NEXT:    [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]]
3738 // CHECK3-NEXT:    [[SUB4:%.*]] = sub i32 [[SUB]], 1
3739 // CHECK3-NEXT:    [[ADD:%.*]] = add i32 [[SUB4]], 1
3740 // CHECK3-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], 1
3741 // CHECK3-NEXT:    [[SUB5:%.*]] = sub i32 [[DIV]], 1
3742 // CHECK3-NEXT:    store i32 [[SUB5]], i32* [[DOTCAPTURE_EXPR_3]], align 4
3743 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
3744 // CHECK3-NEXT:    store i32 [[TMP5]], i32* [[I]], align 4
3745 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
3746 // CHECK3-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
3747 // CHECK3-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]]
3748 // CHECK3-NEXT:    br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
3749 // CHECK3:       omp.precond.then:
3750 // CHECK3-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
3751 // CHECK3-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
3752 // CHECK3-NEXT:    store i32 [[TMP8]], i32* [[DOTOMP_UB]], align 4
3753 // CHECK3-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
3754 // CHECK3-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
3755 // CHECK3-NEXT:    [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
3756 // CHECK3-NEXT:    [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
3757 // CHECK3-NEXT:    call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
3758 // CHECK3-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
3759 // CHECK3-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
3760 // CHECK3-NEXT:    [[CMP7:%.*]] = icmp ugt i32 [[TMP11]], [[TMP12]]
3761 // CHECK3-NEXT:    br i1 [[CMP7]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
3762 // CHECK3:       cond.true:
3763 // CHECK3-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
3764 // CHECK3-NEXT:    br label [[COND_END:%.*]]
3765 // CHECK3:       cond.false:
3766 // CHECK3-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
3767 // CHECK3-NEXT:    br label [[COND_END]]
3768 // CHECK3:       cond.end:
3769 // CHECK3-NEXT:    [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ]
3770 // CHECK3-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
3771 // CHECK3-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
3772 // CHECK3-NEXT:    store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4
3773 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
3774 // CHECK3:       omp.inner.for.cond:
3775 // CHECK3-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !42
3776 // CHECK3-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !42
3777 // CHECK3-NEXT:    [[ADD8:%.*]] = add i32 [[TMP17]], 1
3778 // CHECK3-NEXT:    [[CMP9:%.*]] = icmp ult i32 [[TMP16]], [[ADD8]]
3779 // CHECK3-NEXT:    br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
3780 // CHECK3:       omp.inner.for.body:
3781 // CHECK3-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group !42
3782 // CHECK3-NEXT:    [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !42
3783 // CHECK3-NEXT:    [[MUL:%.*]] = mul i32 [[TMP19]], 1
3784 // CHECK3-NEXT:    [[ADD10:%.*]] = add i32 [[TMP18]], [[MUL]]
3785 // CHECK3-NEXT:    store i32 [[ADD10]], i32* [[I6]], align 4, !llvm.access.group !42
3786 // CHECK3-NEXT:    [[TMP20:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !42
3787 // CHECK3-NEXT:    [[ADD11:%.*]] = add nsw i32 [[TMP20]], 1
3788 // CHECK3-NEXT:    store i32 [[ADD11]], i32* [[A_ADDR]], align 4, !llvm.access.group !42
3789 // CHECK3-NEXT:    [[TMP21:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !42
3790 // CHECK3-NEXT:    [[CONV12:%.*]] = sext i16 [[TMP21]] to i32
3791 // CHECK3-NEXT:    [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1
3792 // CHECK3-NEXT:    [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16
3793 // CHECK3-NEXT:    store i16 [[CONV14]], i16* [[CONV]], align 2, !llvm.access.group !42
3794 // CHECK3-NEXT:    [[TMP22:%.*]] = load i8, i8* [[CONV1]], align 1, !llvm.access.group !42
3795 // CHECK3-NEXT:    [[CONV15:%.*]] = sext i8 [[TMP22]] to i32
3796 // CHECK3-NEXT:    [[ADD16:%.*]] = add nsw i32 [[CONV15]], 1
3797 // CHECK3-NEXT:    [[CONV17:%.*]] = trunc i32 [[ADD16]] to i8
3798 // CHECK3-NEXT:    store i8 [[CONV17]], i8* [[CONV1]], align 1, !llvm.access.group !42
3799 // CHECK3-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
3800 // CHECK3-NEXT:    [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !42
3801 // CHECK3-NEXT:    [[ADD18:%.*]] = add nsw i32 [[TMP23]], 1
3802 // CHECK3-NEXT:    store i32 [[ADD18]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !42
3803 // CHECK3-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
3804 // CHECK3:       omp.body.continue:
3805 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
3806 // CHECK3:       omp.inner.for.inc:
3807 // CHECK3-NEXT:    [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !42
3808 // CHECK3-NEXT:    [[ADD19:%.*]] = add i32 [[TMP24]], 1
3809 // CHECK3-NEXT:    store i32 [[ADD19]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !42
3810 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP43:![0-9]+]]
3811 // CHECK3:       omp.inner.for.end:
3812 // CHECK3-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
3813 // CHECK3:       omp.loop.exit:
3814 // CHECK3-NEXT:    [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
3815 // CHECK3-NEXT:    [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4
3816 // CHECK3-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]])
3817 // CHECK3-NEXT:    [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
3818 // CHECK3-NEXT:    [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0
3819 // CHECK3-NEXT:    br i1 [[TMP28]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
3820 // CHECK3:       .omp.final.then:
3821 // CHECK3-NEXT:    [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
3822 // CHECK3-NEXT:    [[TMP30:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
3823 // CHECK3-NEXT:    [[TMP31:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
3824 // CHECK3-NEXT:    [[SUB20:%.*]] = sub i32 [[TMP30]], [[TMP31]]
3825 // CHECK3-NEXT:    [[SUB21:%.*]] = sub i32 [[SUB20]], 1
3826 // CHECK3-NEXT:    [[ADD22:%.*]] = add i32 [[SUB21]], 1
3827 // CHECK3-NEXT:    [[DIV23:%.*]] = udiv i32 [[ADD22]], 1
3828 // CHECK3-NEXT:    [[MUL24:%.*]] = mul i32 [[DIV23]], 1
3829 // CHECK3-NEXT:    [[ADD25:%.*]] = add i32 [[TMP29]], [[MUL24]]
3830 // CHECK3-NEXT:    store i32 [[ADD25]], i32* [[I6]], align 4
3831 // CHECK3-NEXT:    br label [[DOTOMP_FINAL_DONE]]
3832 // CHECK3:       .omp.final.done:
3833 // CHECK3-NEXT:    br label [[OMP_PRECOND_END]]
3834 // CHECK3:       omp.precond.end:
3835 // CHECK3-NEXT:    ret void
3836 //
3837 //
3838 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180
3839 // CHECK3-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
3840 // CHECK3-NEXT:  entry:
3841 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
3842 // CHECK3-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
3843 // CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
3844 // CHECK3-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
3845 // CHECK3-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
3846 // CHECK3-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
3847 // CHECK3-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
3848 // CHECK3-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
3849 // CHECK3-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
3850 // CHECK3-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
3851 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
3852 // CHECK3-NEXT:    store i32 [[TMP1]], i32* [[A_CASTED]], align 4
3853 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
3854 // CHECK3-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
3855 // CHECK3-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
3856 // CHECK3-NEXT:    store i16 [[TMP3]], i16* [[CONV1]], align 2
3857 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
3858 // CHECK3-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..18 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]])
3859 // CHECK3-NEXT:    ret void
3860 //
3861 //
3862 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..18
3863 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] {
3864 // CHECK3-NEXT:  entry:
3865 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
3866 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
3867 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
3868 // CHECK3-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
3869 // CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
3870 // CHECK3-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
3871 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 4
3872 // CHECK3-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
3873 // CHECK3-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
3874 // CHECK3-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
3875 // CHECK3-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
3876 // CHECK3-NEXT:    [[I:%.*]] = alloca i32, align 4
3877 // CHECK3-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
3878 // CHECK3-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
3879 // CHECK3-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
3880 // CHECK3-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
3881 // CHECK3-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
3882 // CHECK3-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
3883 // CHECK3-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
3884 // CHECK3-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
3885 // CHECK3-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
3886 // CHECK3-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
3887 // CHECK3-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
3888 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
3889 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
3890 // CHECK3-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
3891 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
3892 // CHECK3-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9
3893 // CHECK3-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
3894 // CHECK3:       cond.true:
3895 // CHECK3-NEXT:    br label [[COND_END:%.*]]
3896 // CHECK3:       cond.false:
3897 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
3898 // CHECK3-NEXT:    br label [[COND_END]]
3899 // CHECK3:       cond.end:
3900 // CHECK3-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
3901 // CHECK3-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
3902 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
3903 // CHECK3-NEXT:    store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
3904 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
3905 // CHECK3:       omp.inner.for.cond:
3906 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !45
3907 // CHECK3-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !45
3908 // CHECK3-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
3909 // CHECK3-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
3910 // CHECK3:       omp.inner.for.body:
3911 // CHECK3-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !45
3912 // CHECK3-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
3913 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
3914 // CHECK3-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !45
3915 // CHECK3-NEXT:    [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !45
3916 // CHECK3-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
3917 // CHECK3-NEXT:    store i32 [[ADD2]], i32* [[A_ADDR]], align 4, !llvm.access.group !45
3918 // CHECK3-NEXT:    [[TMP10:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !45
3919 // CHECK3-NEXT:    [[CONV3:%.*]] = sext i16 [[TMP10]] to i32
3920 // CHECK3-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
3921 // CHECK3-NEXT:    [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
3922 // CHECK3-NEXT:    store i16 [[CONV5]], i16* [[CONV]], align 2, !llvm.access.group !45
3923 // CHECK3-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
3924 // CHECK3-NEXT:    [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !45
3925 // CHECK3-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1
3926 // CHECK3-NEXT:    store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !45
3927 // CHECK3-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
3928 // CHECK3:       omp.body.continue:
3929 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
3930 // CHECK3:       omp.inner.for.inc:
3931 // CHECK3-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !45
3932 // CHECK3-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP12]], 1
3933 // CHECK3-NEXT:    store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !45
3934 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP46:![0-9]+]]
3935 // CHECK3:       omp.inner.for.end:
3936 // CHECK3-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
3937 // CHECK3:       omp.loop.exit:
3938 // CHECK3-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
3939 // CHECK3-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
3940 // CHECK3-NEXT:    [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
3941 // CHECK3-NEXT:    br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
3942 // CHECK3:       .omp.final.then:
3943 // CHECK3-NEXT:    store i32 10, i32* [[I]], align 4
3944 // CHECK3-NEXT:    br label [[DOTOMP_FINAL_DONE]]
3945 // CHECK3:       .omp.final.done:
3946 // CHECK3-NEXT:    ret void
3947 //
3948 //
3949 // CHECK3-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
3950 // CHECK3-SAME: () #[[ATTR5]] {
3951 // CHECK3-NEXT:  entry:
3952 // CHECK3-NEXT:    call void @__tgt_register_requires(i64 1)
3953 // CHECK3-NEXT:    ret void
3954 //
3955 //
3956 // CHECK5-LABEL: define {{[^@]+}}@_Z3fooi
3957 // CHECK5-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0:[0-9]+]] {
3958 // CHECK5-NEXT:  entry:
3959 // CHECK5-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
3960 // CHECK5-NEXT:    [[A:%.*]] = alloca i32, align 4
3961 // CHECK5-NEXT:    [[AA:%.*]] = alloca i16, align 2
3962 // CHECK5-NEXT:    [[B:%.*]] = alloca [10 x float], align 4
3963 // CHECK5-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 8
3964 // CHECK5-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
3965 // CHECK5-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 8
3966 // CHECK5-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i64, align 8
3967 // CHECK5-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8
3968 // CHECK5-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
3969 // CHECK5-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
3970 // CHECK5-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
3971 // CHECK5-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
3972 // CHECK5-NEXT:    [[DOTCAPTURE_EXPR__CASTED4:%.*]] = alloca i64, align 8
3973 // CHECK5-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8
3974 // CHECK5-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8
3975 // CHECK5-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8
3976 // CHECK5-NEXT:    [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4
3977 // CHECK5-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
3978 // CHECK5-NEXT:    [[AA_CASTED7:%.*]] = alloca i64, align 8
3979 // CHECK5-NEXT:    [[DOTOFFLOAD_BASEPTRS9:%.*]] = alloca [1 x i8*], align 8
3980 // CHECK5-NEXT:    [[DOTOFFLOAD_PTRS10:%.*]] = alloca [1 x i8*], align 8
3981 // CHECK5-NEXT:    [[DOTOFFLOAD_MAPPERS11:%.*]] = alloca [1 x i8*], align 8
3982 // CHECK5-NEXT:    [[TMP:%.*]] = alloca i32, align 4
3983 // CHECK5-NEXT:    [[A_CASTED12:%.*]] = alloca i64, align 8
3984 // CHECK5-NEXT:    [[AA_CASTED14:%.*]] = alloca i64, align 8
3985 // CHECK5-NEXT:    [[DOTOFFLOAD_BASEPTRS16:%.*]] = alloca [2 x i8*], align 8
3986 // CHECK5-NEXT:    [[DOTOFFLOAD_PTRS17:%.*]] = alloca [2 x i8*], align 8
3987 // CHECK5-NEXT:    [[DOTOFFLOAD_MAPPERS18:%.*]] = alloca [2 x i8*], align 8
3988 // CHECK5-NEXT:    [[_TMP19:%.*]] = alloca i32, align 4
3989 // CHECK5-NEXT:    [[A_CASTED23:%.*]] = alloca i64, align 8
3990 // CHECK5-NEXT:    [[DOTOFFLOAD_BASEPTRS27:%.*]] = alloca [9 x i8*], align 8
3991 // CHECK5-NEXT:    [[DOTOFFLOAD_PTRS28:%.*]] = alloca [9 x i8*], align 8
3992 // CHECK5-NEXT:    [[DOTOFFLOAD_MAPPERS29:%.*]] = alloca [9 x i8*], align 8
3993 // CHECK5-NEXT:    [[DOTOFFLOAD_SIZES:%.*]] = alloca [9 x i64], align 8
3994 // CHECK5-NEXT:    [[_TMP30:%.*]] = alloca i32, align 4
3995 // CHECK5-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]])
3996 // CHECK5-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
3997 // CHECK5-NEXT:    store i32 0, i32* [[A]], align 4
3998 // CHECK5-NEXT:    store i16 0, i16* [[AA]], align 2
3999 // CHECK5-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
4000 // CHECK5-NEXT:    [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
4001 // CHECK5-NEXT:    [[TMP3:%.*]] = call i8* @llvm.stacksave()
4002 // CHECK5-NEXT:    store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8
4003 // CHECK5-NEXT:    [[VLA:%.*]] = alloca float, i64 [[TMP2]], align 4
4004 // CHECK5-NEXT:    store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8
4005 // CHECK5-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
4006 // CHECK5-NEXT:    [[TMP5:%.*]] = zext i32 [[TMP4]] to i64
4007 // CHECK5-NEXT:    [[TMP6:%.*]] = mul nuw i64 5, [[TMP5]]
4008 // CHECK5-NEXT:    [[VLA1:%.*]] = alloca double, i64 [[TMP6]], align 8
4009 // CHECK5-NEXT:    store i64 [[TMP5]], i64* [[__VLA_EXPR1]], align 8
4010 // CHECK5-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
4011 // CHECK5-NEXT:    store i32 [[TMP7]], i32* [[DOTCAPTURE_EXPR_]], align 4
4012 // CHECK5-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
4013 // CHECK5-NEXT:    store i32 [[TMP8]], i32* [[DOTCAPTURE_EXPR_2]], align 4
4014 // CHECK5-NEXT:    [[TMP9:%.*]] = load i16, i16* [[AA]], align 2
4015 // CHECK5-NEXT:    [[CONV:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
4016 // CHECK5-NEXT:    store i16 [[TMP9]], i16* [[CONV]], align 2
4017 // CHECK5-NEXT:    [[TMP10:%.*]] = load i64, i64* [[AA_CASTED]], align 8
4018 // CHECK5-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
4019 // CHECK5-NEXT:    [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
4020 // CHECK5-NEXT:    store i32 [[TMP11]], i32* [[CONV3]], align 4
4021 // CHECK5-NEXT:    [[TMP12:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
4022 // CHECK5-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
4023 // CHECK5-NEXT:    [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED4]] to i32*
4024 // CHECK5-NEXT:    store i32 [[TMP13]], i32* [[CONV5]], align 4
4025 // CHECK5-NEXT:    [[TMP14:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED4]], align 8
4026 // CHECK5-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
4027 // CHECK5-NEXT:    [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i64*
4028 // CHECK5-NEXT:    store i64 [[TMP10]], i64* [[TMP16]], align 8
4029 // CHECK5-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
4030 // CHECK5-NEXT:    [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64*
4031 // CHECK5-NEXT:    store i64 [[TMP10]], i64* [[TMP18]], align 8
4032 // CHECK5-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
4033 // CHECK5-NEXT:    store i8* null, i8** [[TMP19]], align 8
4034 // CHECK5-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
4035 // CHECK5-NEXT:    [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i64*
4036 // CHECK5-NEXT:    store i64 [[TMP12]], i64* [[TMP21]], align 8
4037 // CHECK5-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
4038 // CHECK5-NEXT:    [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i64*
4039 // CHECK5-NEXT:    store i64 [[TMP12]], i64* [[TMP23]], align 8
4040 // CHECK5-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
4041 // CHECK5-NEXT:    store i8* null, i8** [[TMP24]], align 8
4042 // CHECK5-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
4043 // CHECK5-NEXT:    [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i64*
4044 // CHECK5-NEXT:    store i64 [[TMP14]], i64* [[TMP26]], align 8
4045 // CHECK5-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
4046 // CHECK5-NEXT:    [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i64*
4047 // CHECK5-NEXT:    store i64 [[TMP14]], i64* [[TMP28]], align 8
4048 // CHECK5-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
4049 // CHECK5-NEXT:    store i8* null, i8** [[TMP29]], align 8
4050 // CHECK5-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
4051 // CHECK5-NEXT:    [[TMP31:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
4052 // CHECK5-NEXT:    [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 0
4053 // CHECK5-NEXT:    [[TMP33:%.*]] = load i16, i16* [[AA]], align 2
4054 // CHECK5-NEXT:    store i16 [[TMP33]], i16* [[TMP32]], align 4
4055 // CHECK5-NEXT:    [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 1
4056 // CHECK5-NEXT:    [[TMP35:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
4057 // CHECK5-NEXT:    store i32 [[TMP35]], i32* [[TMP34]], align 4
4058 // CHECK5-NEXT:    [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 2
4059 // CHECK5-NEXT:    [[TMP37:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
4060 // CHECK5-NEXT:    store i32 [[TMP37]], i32* [[TMP36]], align 4
4061 // CHECK5-NEXT:    [[TMP38:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 1, i64 120, i64 12, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1)
4062 // CHECK5-NEXT:    [[TMP39:%.*]] = bitcast i8* [[TMP38]] to %struct.kmp_task_t_with_privates*
4063 // CHECK5-NEXT:    [[TMP40:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP39]], i32 0, i32 0
4064 // CHECK5-NEXT:    [[TMP41:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP40]], i32 0, i32 0
4065 // CHECK5-NEXT:    [[TMP42:%.*]] = load i8*, i8** [[TMP41]], align 8
4066 // CHECK5-NEXT:    [[TMP43:%.*]] = bitcast %struct.anon* [[AGG_CAPTURED]] to i8*
4067 // CHECK5-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP42]], i8* align 4 [[TMP43]], i64 12, i1 false)
4068 // CHECK5-NEXT:    [[TMP44:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP39]], i32 0, i32 1
4069 // CHECK5-NEXT:    [[TMP45:%.*]] = bitcast i8* [[TMP42]] to %struct.anon*
4070 // CHECK5-NEXT:    [[TMP46:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 0
4071 // CHECK5-NEXT:    [[TMP47:%.*]] = bitcast [3 x i8*]* [[TMP46]] to i8*
4072 // CHECK5-NEXT:    [[TMP48:%.*]] = bitcast i8** [[TMP30]] to i8*
4073 // CHECK5-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP47]], i8* align 8 [[TMP48]], i64 24, i1 false)
4074 // CHECK5-NEXT:    [[TMP49:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 1
4075 // CHECK5-NEXT:    [[TMP50:%.*]] = bitcast [3 x i8*]* [[TMP49]] to i8*
4076 // CHECK5-NEXT:    [[TMP51:%.*]] = bitcast i8** [[TMP31]] to i8*
4077 // CHECK5-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP50]], i8* align 8 [[TMP51]], i64 24, i1 false)
4078 // CHECK5-NEXT:    [[TMP52:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 2
4079 // CHECK5-NEXT:    [[TMP53:%.*]] = bitcast [3 x i64]* [[TMP52]] to i8*
4080 // CHECK5-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP53]], i8* align 8 bitcast ([3 x i64]* @.offload_sizes to i8*), i64 24, i1 false)
4081 // CHECK5-NEXT:    [[TMP54:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 3
4082 // CHECK5-NEXT:    [[TMP55:%.*]] = load i16, i16* [[AA]], align 2
4083 // CHECK5-NEXT:    store i16 [[TMP55]], i16* [[TMP54]], align 8
4084 // CHECK5-NEXT:    [[TMP56:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i8* [[TMP38]])
4085 // CHECK5-NEXT:    [[TMP57:%.*]] = load i32, i32* [[A]], align 4
4086 // CHECK5-NEXT:    [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32*
4087 // CHECK5-NEXT:    store i32 [[TMP57]], i32* [[CONV6]], align 4
4088 // CHECK5-NEXT:    [[TMP58:%.*]] = load i64, i64* [[A_CASTED]], align 8
4089 // CHECK5-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l102(i64 [[TMP58]]) #[[ATTR4:[0-9]+]]
4090 // CHECK5-NEXT:    [[TMP59:%.*]] = load i16, i16* [[AA]], align 2
4091 // CHECK5-NEXT:    [[CONV8:%.*]] = bitcast i64* [[AA_CASTED7]] to i16*
4092 // CHECK5-NEXT:    store i16 [[TMP59]], i16* [[CONV8]], align 2
4093 // CHECK5-NEXT:    [[TMP60:%.*]] = load i64, i64* [[AA_CASTED7]], align 8
4094 // CHECK5-NEXT:    [[TMP61:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS9]], i32 0, i32 0
4095 // CHECK5-NEXT:    [[TMP62:%.*]] = bitcast i8** [[TMP61]] to i64*
4096 // CHECK5-NEXT:    store i64 [[TMP60]], i64* [[TMP62]], align 8
4097 // CHECK5-NEXT:    [[TMP63:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS10]], i32 0, i32 0
4098 // CHECK5-NEXT:    [[TMP64:%.*]] = bitcast i8** [[TMP63]] to i64*
4099 // CHECK5-NEXT:    store i64 [[TMP60]], i64* [[TMP64]], align 8
4100 // CHECK5-NEXT:    [[TMP65:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS11]], i64 0, i64 0
4101 // CHECK5-NEXT:    store i8* null, i8** [[TMP65]], align 8
4102 // CHECK5-NEXT:    [[TMP66:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS9]], i32 0, i32 0
4103 // CHECK5-NEXT:    [[TMP67:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS10]], i32 0, i32 0
4104 // CHECK5-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
4105 // CHECK5-NEXT:    [[TMP68:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
4106 // CHECK5-NEXT:    store i32 1, i32* [[TMP68]], align 4
4107 // CHECK5-NEXT:    [[TMP69:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
4108 // CHECK5-NEXT:    store i32 1, i32* [[TMP69]], align 4
4109 // CHECK5-NEXT:    [[TMP70:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
4110 // CHECK5-NEXT:    store i8** [[TMP66]], i8*** [[TMP70]], align 8
4111 // CHECK5-NEXT:    [[TMP71:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
4112 // CHECK5-NEXT:    store i8** [[TMP67]], i8*** [[TMP71]], align 8
4113 // CHECK5-NEXT:    [[TMP72:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
4114 // CHECK5-NEXT:    store i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.4, i32 0, i32 0), i64** [[TMP72]], align 8
4115 // CHECK5-NEXT:    [[TMP73:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
4116 // CHECK5-NEXT:    store i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.5, i32 0, i32 0), i64** [[TMP73]], align 8
4117 // CHECK5-NEXT:    [[TMP74:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
4118 // CHECK5-NEXT:    store i8** null, i8*** [[TMP74]], align 8
4119 // CHECK5-NEXT:    [[TMP75:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
4120 // CHECK5-NEXT:    store i8** null, i8*** [[TMP75]], align 8
4121 // CHECK5-NEXT:    [[TMP76:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
4122 // CHECK5-NEXT:    store i64 10, i64* [[TMP76]], align 8
4123 // CHECK5-NEXT:    [[TMP77:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB2]], i64 -1, i32 0, i32 1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
4124 // CHECK5-NEXT:    [[TMP78:%.*]] = icmp ne i32 [[TMP77]], 0
4125 // CHECK5-NEXT:    br i1 [[TMP78]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
4126 // CHECK5:       omp_offload.failed:
4127 // CHECK5-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111(i64 [[TMP60]]) #[[ATTR4]]
4128 // CHECK5-NEXT:    br label [[OMP_OFFLOAD_CONT]]
4129 // CHECK5:       omp_offload.cont:
4130 // CHECK5-NEXT:    [[TMP79:%.*]] = load i32, i32* [[A]], align 4
4131 // CHECK5-NEXT:    [[CONV13:%.*]] = bitcast i64* [[A_CASTED12]] to i32*
4132 // CHECK5-NEXT:    store i32 [[TMP79]], i32* [[CONV13]], align 4
4133 // CHECK5-NEXT:    [[TMP80:%.*]] = load i64, i64* [[A_CASTED12]], align 8
4134 // CHECK5-NEXT:    [[TMP81:%.*]] = load i16, i16* [[AA]], align 2
4135 // CHECK5-NEXT:    [[CONV15:%.*]] = bitcast i64* [[AA_CASTED14]] to i16*
4136 // CHECK5-NEXT:    store i16 [[TMP81]], i16* [[CONV15]], align 2
4137 // CHECK5-NEXT:    [[TMP82:%.*]] = load i64, i64* [[AA_CASTED14]], align 8
4138 // CHECK5-NEXT:    [[TMP83:%.*]] = load i32, i32* [[N_ADDR]], align 4
4139 // CHECK5-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP83]], 10
4140 // CHECK5-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
4141 // CHECK5:       omp_if.then:
4142 // CHECK5-NEXT:    [[TMP84:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 0
4143 // CHECK5-NEXT:    [[TMP85:%.*]] = bitcast i8** [[TMP84]] to i64*
4144 // CHECK5-NEXT:    store i64 [[TMP80]], i64* [[TMP85]], align 8
4145 // CHECK5-NEXT:    [[TMP86:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 0
4146 // CHECK5-NEXT:    [[TMP87:%.*]] = bitcast i8** [[TMP86]] to i64*
4147 // CHECK5-NEXT:    store i64 [[TMP80]], i64* [[TMP87]], align 8
4148 // CHECK5-NEXT:    [[TMP88:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 0
4149 // CHECK5-NEXT:    store i8* null, i8** [[TMP88]], align 8
4150 // CHECK5-NEXT:    [[TMP89:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 1
4151 // CHECK5-NEXT:    [[TMP90:%.*]] = bitcast i8** [[TMP89]] to i64*
4152 // CHECK5-NEXT:    store i64 [[TMP82]], i64* [[TMP90]], align 8
4153 // CHECK5-NEXT:    [[TMP91:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 1
4154 // CHECK5-NEXT:    [[TMP92:%.*]] = bitcast i8** [[TMP91]] to i64*
4155 // CHECK5-NEXT:    store i64 [[TMP82]], i64* [[TMP92]], align 8
4156 // CHECK5-NEXT:    [[TMP93:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 1
4157 // CHECK5-NEXT:    store i8* null, i8** [[TMP93]], align 8
4158 // CHECK5-NEXT:    [[TMP94:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 0
4159 // CHECK5-NEXT:    [[TMP95:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 0
4160 // CHECK5-NEXT:    [[KERNEL_ARGS20:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
4161 // CHECK5-NEXT:    [[TMP96:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS20]], i32 0, i32 0
4162 // CHECK5-NEXT:    store i32 1, i32* [[TMP96]], align 4
4163 // CHECK5-NEXT:    [[TMP97:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS20]], i32 0, i32 1
4164 // CHECK5-NEXT:    store i32 2, i32* [[TMP97]], align 4
4165 // CHECK5-NEXT:    [[TMP98:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS20]], i32 0, i32 2
4166 // CHECK5-NEXT:    store i8** [[TMP94]], i8*** [[TMP98]], align 8
4167 // CHECK5-NEXT:    [[TMP99:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS20]], i32 0, i32 3
4168 // CHECK5-NEXT:    store i8** [[TMP95]], i8*** [[TMP99]], align 8
4169 // CHECK5-NEXT:    [[TMP100:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS20]], i32 0, i32 4
4170 // CHECK5-NEXT:    store i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.7, i32 0, i32 0), i64** [[TMP100]], align 8
4171 // CHECK5-NEXT:    [[TMP101:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS20]], i32 0, i32 5
4172 // CHECK5-NEXT:    store i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.8, i32 0, i32 0), i64** [[TMP101]], align 8
4173 // CHECK5-NEXT:    [[TMP102:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS20]], i32 0, i32 6
4174 // CHECK5-NEXT:    store i8** null, i8*** [[TMP102]], align 8
4175 // CHECK5-NEXT:    [[TMP103:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS20]], i32 0, i32 7
4176 // CHECK5-NEXT:    store i8** null, i8*** [[TMP103]], align 8
4177 // CHECK5-NEXT:    [[TMP104:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS20]], i32 0, i32 8
4178 // CHECK5-NEXT:    store i64 10, i64* [[TMP104]], align 8
4179 // CHECK5-NEXT:    [[TMP105:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB2]], i64 -1, i32 0, i32 1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS20]])
4180 // CHECK5-NEXT:    [[TMP106:%.*]] = icmp ne i32 [[TMP105]], 0
4181 // CHECK5-NEXT:    br i1 [[TMP106]], label [[OMP_OFFLOAD_FAILED21:%.*]], label [[OMP_OFFLOAD_CONT22:%.*]]
4182 // CHECK5:       omp_offload.failed21:
4183 // CHECK5-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i64 [[TMP80]], i64 [[TMP82]]) #[[ATTR4]]
4184 // CHECK5-NEXT:    br label [[OMP_OFFLOAD_CONT22]]
4185 // CHECK5:       omp_offload.cont22:
4186 // CHECK5-NEXT:    br label [[OMP_IF_END:%.*]]
4187 // CHECK5:       omp_if.else:
4188 // CHECK5-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i64 [[TMP80]], i64 [[TMP82]]) #[[ATTR4]]
4189 // CHECK5-NEXT:    br label [[OMP_IF_END]]
4190 // CHECK5:       omp_if.end:
4191 // CHECK5-NEXT:    [[TMP107:%.*]] = load i32, i32* [[A]], align 4
4192 // CHECK5-NEXT:    [[CONV24:%.*]] = bitcast i64* [[A_CASTED23]] to i32*
4193 // CHECK5-NEXT:    store i32 [[TMP107]], i32* [[CONV24]], align 4
4194 // CHECK5-NEXT:    [[TMP108:%.*]] = load i64, i64* [[A_CASTED23]], align 8
4195 // CHECK5-NEXT:    [[TMP109:%.*]] = load i32, i32* [[N_ADDR]], align 4
4196 // CHECK5-NEXT:    [[CMP25:%.*]] = icmp sgt i32 [[TMP109]], 20
4197 // CHECK5-NEXT:    br i1 [[CMP25]], label [[OMP_IF_THEN26:%.*]], label [[OMP_IF_ELSE34:%.*]]
4198 // CHECK5:       omp_if.then26:
4199 // CHECK5-NEXT:    [[TMP110:%.*]] = mul nuw i64 [[TMP2]], 4
4200 // CHECK5-NEXT:    [[TMP111:%.*]] = mul nuw i64 5, [[TMP5]]
4201 // CHECK5-NEXT:    [[TMP112:%.*]] = mul nuw i64 [[TMP111]], 8
4202 // CHECK5-NEXT:    [[TMP113:%.*]] = bitcast [9 x i64]* [[DOTOFFLOAD_SIZES]] to i8*
4203 // CHECK5-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP113]], i8* align 8 bitcast ([9 x i64]* @.offload_sizes.10 to i8*), i64 72, i1 false)
4204 // CHECK5-NEXT:    [[TMP114:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS27]], i32 0, i32 0
4205 // CHECK5-NEXT:    [[TMP115:%.*]] = bitcast i8** [[TMP114]] to i64*
4206 // CHECK5-NEXT:    store i64 [[TMP108]], i64* [[TMP115]], align 8
4207 // CHECK5-NEXT:    [[TMP116:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS28]], i32 0, i32 0
4208 // CHECK5-NEXT:    [[TMP117:%.*]] = bitcast i8** [[TMP116]] to i64*
4209 // CHECK5-NEXT:    store i64 [[TMP108]], i64* [[TMP117]], align 8
4210 // CHECK5-NEXT:    [[TMP118:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS29]], i64 0, i64 0
4211 // CHECK5-NEXT:    store i8* null, i8** [[TMP118]], align 8
4212 // CHECK5-NEXT:    [[TMP119:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS27]], i32 0, i32 1
4213 // CHECK5-NEXT:    [[TMP120:%.*]] = bitcast i8** [[TMP119]] to [10 x float]**
4214 // CHECK5-NEXT:    store [10 x float]* [[B]], [10 x float]** [[TMP120]], align 8
4215 // CHECK5-NEXT:    [[TMP121:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS28]], i32 0, i32 1
4216 // CHECK5-NEXT:    [[TMP122:%.*]] = bitcast i8** [[TMP121]] to [10 x float]**
4217 // CHECK5-NEXT:    store [10 x float]* [[B]], [10 x float]** [[TMP122]], align 8
4218 // CHECK5-NEXT:    [[TMP123:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS29]], i64 0, i64 1
4219 // CHECK5-NEXT:    store i8* null, i8** [[TMP123]], align 8
4220 // CHECK5-NEXT:    [[TMP124:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS27]], i32 0, i32 2
4221 // CHECK5-NEXT:    [[TMP125:%.*]] = bitcast i8** [[TMP124]] to i64*
4222 // CHECK5-NEXT:    store i64 [[TMP2]], i64* [[TMP125]], align 8
4223 // CHECK5-NEXT:    [[TMP126:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS28]], i32 0, i32 2
4224 // CHECK5-NEXT:    [[TMP127:%.*]] = bitcast i8** [[TMP126]] to i64*
4225 // CHECK5-NEXT:    store i64 [[TMP2]], i64* [[TMP127]], align 8
4226 // CHECK5-NEXT:    [[TMP128:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS29]], i64 0, i64 2
4227 // CHECK5-NEXT:    store i8* null, i8** [[TMP128]], align 8
4228 // CHECK5-NEXT:    [[TMP129:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS27]], i32 0, i32 3
4229 // CHECK5-NEXT:    [[TMP130:%.*]] = bitcast i8** [[TMP129]] to float**
4230 // CHECK5-NEXT:    store float* [[VLA]], float** [[TMP130]], align 8
4231 // CHECK5-NEXT:    [[TMP131:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS28]], i32 0, i32 3
4232 // CHECK5-NEXT:    [[TMP132:%.*]] = bitcast i8** [[TMP131]] to float**
4233 // CHECK5-NEXT:    store float* [[VLA]], float** [[TMP132]], align 8
4234 // CHECK5-NEXT:    [[TMP133:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3
4235 // CHECK5-NEXT:    store i64 [[TMP110]], i64* [[TMP133]], align 8
4236 // CHECK5-NEXT:    [[TMP134:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS29]], i64 0, i64 3
4237 // CHECK5-NEXT:    store i8* null, i8** [[TMP134]], align 8
4238 // CHECK5-NEXT:    [[TMP135:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS27]], i32 0, i32 4
4239 // CHECK5-NEXT:    [[TMP136:%.*]] = bitcast i8** [[TMP135]] to [5 x [10 x double]]**
4240 // CHECK5-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP136]], align 8
4241 // CHECK5-NEXT:    [[TMP137:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS28]], i32 0, i32 4
4242 // CHECK5-NEXT:    [[TMP138:%.*]] = bitcast i8** [[TMP137]] to [5 x [10 x double]]**
4243 // CHECK5-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP138]], align 8
4244 // CHECK5-NEXT:    [[TMP139:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS29]], i64 0, i64 4
4245 // CHECK5-NEXT:    store i8* null, i8** [[TMP139]], align 8
4246 // CHECK5-NEXT:    [[TMP140:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS27]], i32 0, i32 5
4247 // CHECK5-NEXT:    [[TMP141:%.*]] = bitcast i8** [[TMP140]] to i64*
4248 // CHECK5-NEXT:    store i64 5, i64* [[TMP141]], align 8
4249 // CHECK5-NEXT:    [[TMP142:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS28]], i32 0, i32 5
4250 // CHECK5-NEXT:    [[TMP143:%.*]] = bitcast i8** [[TMP142]] to i64*
4251 // CHECK5-NEXT:    store i64 5, i64* [[TMP143]], align 8
4252 // CHECK5-NEXT:    [[TMP144:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS29]], i64 0, i64 5
4253 // CHECK5-NEXT:    store i8* null, i8** [[TMP144]], align 8
4254 // CHECK5-NEXT:    [[TMP145:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS27]], i32 0, i32 6
4255 // CHECK5-NEXT:    [[TMP146:%.*]] = bitcast i8** [[TMP145]] to i64*
4256 // CHECK5-NEXT:    store i64 [[TMP5]], i64* [[TMP146]], align 8
4257 // CHECK5-NEXT:    [[TMP147:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS28]], i32 0, i32 6
4258 // CHECK5-NEXT:    [[TMP148:%.*]] = bitcast i8** [[TMP147]] to i64*
4259 // CHECK5-NEXT:    store i64 [[TMP5]], i64* [[TMP148]], align 8
4260 // CHECK5-NEXT:    [[TMP149:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS29]], i64 0, i64 6
4261 // CHECK5-NEXT:    store i8* null, i8** [[TMP149]], align 8
4262 // CHECK5-NEXT:    [[TMP150:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS27]], i32 0, i32 7
4263 // CHECK5-NEXT:    [[TMP151:%.*]] = bitcast i8** [[TMP150]] to double**
4264 // CHECK5-NEXT:    store double* [[VLA1]], double** [[TMP151]], align 8
4265 // CHECK5-NEXT:    [[TMP152:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS28]], i32 0, i32 7
4266 // CHECK5-NEXT:    [[TMP153:%.*]] = bitcast i8** [[TMP152]] to double**
4267 // CHECK5-NEXT:    store double* [[VLA1]], double** [[TMP153]], align 8
4268 // CHECK5-NEXT:    [[TMP154:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7
4269 // CHECK5-NEXT:    store i64 [[TMP112]], i64* [[TMP154]], align 8
4270 // CHECK5-NEXT:    [[TMP155:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS29]], i64 0, i64 7
4271 // CHECK5-NEXT:    store i8* null, i8** [[TMP155]], align 8
4272 // CHECK5-NEXT:    [[TMP156:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS27]], i32 0, i32 8
4273 // CHECK5-NEXT:    [[TMP157:%.*]] = bitcast i8** [[TMP156]] to %struct.TT**
4274 // CHECK5-NEXT:    store %struct.TT* [[D]], %struct.TT** [[TMP157]], align 8
4275 // CHECK5-NEXT:    [[TMP158:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS28]], i32 0, i32 8
4276 // CHECK5-NEXT:    [[TMP159:%.*]] = bitcast i8** [[TMP158]] to %struct.TT**
4277 // CHECK5-NEXT:    store %struct.TT* [[D]], %struct.TT** [[TMP159]], align 8
4278 // CHECK5-NEXT:    [[TMP160:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS29]], i64 0, i64 8
4279 // CHECK5-NEXT:    store i8* null, i8** [[TMP160]], align 8
4280 // CHECK5-NEXT:    [[TMP161:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS27]], i32 0, i32 0
4281 // CHECK5-NEXT:    [[TMP162:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS28]], i32 0, i32 0
4282 // CHECK5-NEXT:    [[TMP163:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
4283 // CHECK5-NEXT:    [[KERNEL_ARGS31:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
4284 // CHECK5-NEXT:    [[TMP164:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS31]], i32 0, i32 0
4285 // CHECK5-NEXT:    store i32 1, i32* [[TMP164]], align 4
4286 // CHECK5-NEXT:    [[TMP165:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS31]], i32 0, i32 1
4287 // CHECK5-NEXT:    store i32 9, i32* [[TMP165]], align 4
4288 // CHECK5-NEXT:    [[TMP166:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS31]], i32 0, i32 2
4289 // CHECK5-NEXT:    store i8** [[TMP161]], i8*** [[TMP166]], align 8
4290 // CHECK5-NEXT:    [[TMP167:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS31]], i32 0, i32 3
4291 // CHECK5-NEXT:    store i8** [[TMP162]], i8*** [[TMP167]], align 8
4292 // CHECK5-NEXT:    [[TMP168:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS31]], i32 0, i32 4
4293 // CHECK5-NEXT:    store i64* [[TMP163]], i64** [[TMP168]], align 8
4294 // CHECK5-NEXT:    [[TMP169:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS31]], i32 0, i32 5
4295 // CHECK5-NEXT:    store i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_maptypes.11, i32 0, i32 0), i64** [[TMP169]], align 8
4296 // CHECK5-NEXT:    [[TMP170:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS31]], i32 0, i32 6
4297 // CHECK5-NEXT:    store i8** null, i8*** [[TMP170]], align 8
4298 // CHECK5-NEXT:    [[TMP171:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS31]], i32 0, i32 7
4299 // CHECK5-NEXT:    store i8** null, i8*** [[TMP171]], align 8
4300 // CHECK5-NEXT:    [[TMP172:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS31]], i32 0, i32 8
4301 // CHECK5-NEXT:    store i64 10, i64* [[TMP172]], align 8
4302 // CHECK5-NEXT:    [[TMP173:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB2]], i64 -1, i32 0, i32 1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS31]])
4303 // CHECK5-NEXT:    [[TMP174:%.*]] = icmp ne i32 [[TMP173]], 0
4304 // CHECK5-NEXT:    br i1 [[TMP174]], label [[OMP_OFFLOAD_FAILED32:%.*]], label [[OMP_OFFLOAD_CONT33:%.*]]
4305 // CHECK5:       omp_offload.failed32:
4306 // CHECK5-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i64 [[TMP108]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR4]]
4307 // CHECK5-NEXT:    br label [[OMP_OFFLOAD_CONT33]]
4308 // CHECK5:       omp_offload.cont33:
4309 // CHECK5-NEXT:    br label [[OMP_IF_END35:%.*]]
4310 // CHECK5:       omp_if.else34:
4311 // CHECK5-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i64 [[TMP108]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR4]]
4312 // CHECK5-NEXT:    br label [[OMP_IF_END35]]
4313 // CHECK5:       omp_if.end35:
4314 // CHECK5-NEXT:    [[TMP175:%.*]] = load i32, i32* [[A]], align 4
4315 // CHECK5-NEXT:    [[TMP176:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
4316 // CHECK5-NEXT:    call void @llvm.stackrestore(i8* [[TMP176]])
4317 // CHECK5-NEXT:    ret i32 [[TMP175]]
4318 //
4319 //
4320 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97
4321 // CHECK5-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] {
4322 // CHECK5-NEXT:  entry:
4323 // CHECK5-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
4324 // CHECK5-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
4325 // CHECK5-NEXT:    [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8
4326 // CHECK5-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
4327 // CHECK5-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]])
4328 // CHECK5-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
4329 // CHECK5-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
4330 // CHECK5-NEXT:    store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8
4331 // CHECK5-NEXT:    [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
4332 // CHECK5-NEXT:    [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
4333 // CHECK5-NEXT:    [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32*
4334 // CHECK5-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 4
4335 // CHECK5-NEXT:    [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 4
4336 // CHECK5-NEXT:    call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
4337 // CHECK5-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
4338 // CHECK5-NEXT:    [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
4339 // CHECK5-NEXT:    store i16 [[TMP3]], i16* [[CONV5]], align 2
4340 // CHECK5-NEXT:    [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
4341 // CHECK5-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]])
4342 // CHECK5-NEXT:    ret void
4343 //
4344 //
4345 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined.
4346 // CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR3:[0-9]+]] {
4347 // CHECK5-NEXT:  entry:
4348 // CHECK5-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
4349 // CHECK5-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
4350 // CHECK5-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
4351 // CHECK5-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
4352 // CHECK5-NEXT:    [[TMP:%.*]] = alloca i32, align 4
4353 // CHECK5-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
4354 // CHECK5-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
4355 // CHECK5-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
4356 // CHECK5-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
4357 // CHECK5-NEXT:    [[I:%.*]] = alloca i32, align 4
4358 // CHECK5-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
4359 // CHECK5-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
4360 // CHECK5-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
4361 // CHECK5-NEXT:    [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
4362 // CHECK5-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
4363 // CHECK5-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
4364 // CHECK5-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
4365 // CHECK5-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
4366 // CHECK5-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
4367 // CHECK5-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
4368 // CHECK5-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
4369 // CHECK5-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
4370 // CHECK5-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
4371 // CHECK5-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
4372 // CHECK5:       cond.true:
4373 // CHECK5-NEXT:    br label [[COND_END:%.*]]
4374 // CHECK5:       cond.false:
4375 // CHECK5-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
4376 // CHECK5-NEXT:    br label [[COND_END]]
4377 // CHECK5:       cond.end:
4378 // CHECK5-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
4379 // CHECK5-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
4380 // CHECK5-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
4381 // CHECK5-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
4382 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
4383 // CHECK5:       omp.inner.for.cond:
4384 // CHECK5-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
4385 // CHECK5-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !10
4386 // CHECK5-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
4387 // CHECK5-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
4388 // CHECK5:       omp.inner.for.body:
4389 // CHECK5-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
4390 // CHECK5-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
4391 // CHECK5-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
4392 // CHECK5-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10
4393 // CHECK5-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
4394 // CHECK5:       omp.body.continue:
4395 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
4396 // CHECK5:       omp.inner.for.inc:
4397 // CHECK5-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
4398 // CHECK5-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
4399 // CHECK5-NEXT:    store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
4400 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]
4401 // CHECK5:       omp.inner.for.end:
4402 // CHECK5-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
4403 // CHECK5:       omp.loop.exit:
4404 // CHECK5-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
4405 // CHECK5-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
4406 // CHECK5-NEXT:    [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0
4407 // CHECK5-NEXT:    br i1 [[TMP10]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
4408 // CHECK5:       .omp.final.then:
4409 // CHECK5-NEXT:    store i32 10, i32* [[I]], align 4
4410 // CHECK5-NEXT:    br label [[DOTOMP_FINAL_DONE]]
4411 // CHECK5:       .omp.final.done:
4412 // CHECK5-NEXT:    ret void
4413 //
4414 //
4415 // CHECK5-LABEL: define {{[^@]+}}@.omp_task_privates_map.
4416 // CHECK5-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], i16** noalias noundef [[TMP1:%.*]], [3 x i8*]** noalias noundef [[TMP2:%.*]], [3 x i8*]** noalias noundef [[TMP3:%.*]], [3 x i64]** noalias noundef [[TMP4:%.*]]) #[[ATTR5:[0-9]+]] {
4417 // CHECK5-NEXT:  entry:
4418 // CHECK5-NEXT:    [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 8
4419 // CHECK5-NEXT:    [[DOTADDR1:%.*]] = alloca i16**, align 8
4420 // CHECK5-NEXT:    [[DOTADDR2:%.*]] = alloca [3 x i8*]**, align 8
4421 // CHECK5-NEXT:    [[DOTADDR3:%.*]] = alloca [3 x i8*]**, align 8
4422 // CHECK5-NEXT:    [[DOTADDR4:%.*]] = alloca [3 x i64]**, align 8
4423 // CHECK5-NEXT:    store %struct..kmp_privates.t* [[TMP0]], %struct..kmp_privates.t** [[DOTADDR]], align 8
4424 // CHECK5-NEXT:    store i16** [[TMP1]], i16*** [[DOTADDR1]], align 8
4425 // CHECK5-NEXT:    store [3 x i8*]** [[TMP2]], [3 x i8*]*** [[DOTADDR2]], align 8
4426 // CHECK5-NEXT:    store [3 x i8*]** [[TMP3]], [3 x i8*]*** [[DOTADDR3]], align 8
4427 // CHECK5-NEXT:    store [3 x i64]** [[TMP4]], [3 x i64]*** [[DOTADDR4]], align 8
4428 // CHECK5-NEXT:    [[TMP5:%.*]] = load %struct..kmp_privates.t*, %struct..kmp_privates.t** [[DOTADDR]], align 8
4429 // CHECK5-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 0
4430 // CHECK5-NEXT:    [[TMP7:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR2]], align 8
4431 // CHECK5-NEXT:    store [3 x i8*]* [[TMP6]], [3 x i8*]** [[TMP7]], align 8
4432 // CHECK5-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 1
4433 // CHECK5-NEXT:    [[TMP9:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR3]], align 8
4434 // CHECK5-NEXT:    store [3 x i8*]* [[TMP8]], [3 x i8*]** [[TMP9]], align 8
4435 // CHECK5-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 2
4436 // CHECK5-NEXT:    [[TMP11:%.*]] = load [3 x i64]**, [3 x i64]*** [[DOTADDR4]], align 8
4437 // CHECK5-NEXT:    store [3 x i64]* [[TMP10]], [3 x i64]** [[TMP11]], align 8
4438 // CHECK5-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 3
4439 // CHECK5-NEXT:    [[TMP13:%.*]] = load i16**, i16*** [[DOTADDR1]], align 8
4440 // CHECK5-NEXT:    store i16* [[TMP12]], i16** [[TMP13]], align 8
4441 // CHECK5-NEXT:    ret void
4442 //
4443 //
4444 // CHECK5-LABEL: define {{[^@]+}}@.omp_task_entry.
4445 // CHECK5-SAME: (i32 noundef signext [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] {
4446 // CHECK5-NEXT:  entry:
4447 // CHECK5-NEXT:    [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
4448 // CHECK5-NEXT:    [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8
4449 // CHECK5-NEXT:    [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8
4450 // CHECK5-NEXT:    [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8
4451 // CHECK5-NEXT:    [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8
4452 // CHECK5-NEXT:    [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 8
4453 // CHECK5-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca i16*, align 8
4454 // CHECK5-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca [3 x i8*]*, align 8
4455 // CHECK5-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca [3 x i8*]*, align 8
4456 // CHECK5-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca [3 x i64]*, align 8
4457 // CHECK5-NEXT:    [[AA_CASTED_I:%.*]] = alloca i64, align 8
4458 // CHECK5-NEXT:    [[DOTCAPTURE_EXPR__CASTED_I:%.*]] = alloca i64, align 8
4459 // CHECK5-NEXT:    [[DOTCAPTURE_EXPR__CASTED5_I:%.*]] = alloca i64, align 8
4460 // CHECK5-NEXT:    [[KERNEL_ARGS_I:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
4461 // CHECK5-NEXT:    [[DOTADDR:%.*]] = alloca i32, align 4
4462 // CHECK5-NEXT:    [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8
4463 // CHECK5-NEXT:    store i32 [[TMP0]], i32* [[DOTADDR]], align 4
4464 // CHECK5-NEXT:    store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8
4465 // CHECK5-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4
4466 // CHECK5-NEXT:    [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8
4467 // CHECK5-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
4468 // CHECK5-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
4469 // CHECK5-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0
4470 // CHECK5-NEXT:    [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8
4471 // CHECK5-NEXT:    [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon*
4472 // CHECK5-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1
4473 // CHECK5-NEXT:    [[TMP10:%.*]] = bitcast %struct..kmp_privates.t* [[TMP9]] to i8*
4474 // CHECK5-NEXT:    [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8*
4475 // CHECK5-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META17:![0-9]+]])
4476 // CHECK5-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]])
4477 // CHECK5-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META22:![0-9]+]])
4478 // CHECK5-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META24:![0-9]+]])
4479 // CHECK5-NEXT:    store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !26
4480 // CHECK5-NEXT:    store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !26
4481 // CHECK5-NEXT:    store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !26
4482 // CHECK5-NEXT:    store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* @.omp_task_privates_map. to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !26
4483 // CHECK5-NEXT:    store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !26
4484 // CHECK5-NEXT:    store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !26
4485 // CHECK5-NEXT:    [[TMP12:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !26
4486 // CHECK5-NEXT:    [[TMP13:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !26
4487 // CHECK5-NEXT:    [[TMP14:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !26
4488 // CHECK5-NEXT:    [[TMP15:%.*]] = bitcast void (i8*, ...)* [[TMP13]] to void (i8*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)*
4489 // CHECK5-NEXT:    call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR4]]
4490 // CHECK5-NEXT:    [[TMP16:%.*]] = load i16*, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !26
4491 // CHECK5-NEXT:    [[TMP17:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !26
4492 // CHECK5-NEXT:    [[TMP18:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 8, !noalias !26
4493 // CHECK5-NEXT:    [[TMP19:%.*]] = load [3 x i64]*, [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 8, !noalias !26
4494 // CHECK5-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP17]], i64 0, i64 0
4495 // CHECK5-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP18]], i64 0, i64 0
4496 // CHECK5-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[TMP19]], i64 0, i64 0
4497 // CHECK5-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP12]], i32 0, i32 1
4498 // CHECK5-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[TMP12]], i32 0, i32 2
4499 // CHECK5-NEXT:    [[TMP25:%.*]] = load i32, i32* [[TMP23]], align 4
4500 // CHECK5-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i32 0
4501 // CHECK5-NEXT:    store i32 1, i32* [[TMP26]], align 4, !noalias !26
4502 // CHECK5-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i32 1
4503 // CHECK5-NEXT:    store i32 3, i32* [[TMP27]], align 4, !noalias !26
4504 // CHECK5-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i32 2
4505 // CHECK5-NEXT:    store i8** [[TMP20]], i8*** [[TMP28]], align 8, !noalias !26
4506 // CHECK5-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i32 3
4507 // CHECK5-NEXT:    store i8** [[TMP21]], i8*** [[TMP29]], align 8, !noalias !26
4508 // CHECK5-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i32 4
4509 // CHECK5-NEXT:    store i64* [[TMP22]], i64** [[TMP30]], align 8, !noalias !26
4510 // CHECK5-NEXT:    [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i32 5
4511 // CHECK5-NEXT:    store i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i64** [[TMP31]], align 8, !noalias !26
4512 // CHECK5-NEXT:    [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i32 6
4513 // CHECK5-NEXT:    store i8** null, i8*** [[TMP32]], align 8, !noalias !26
4514 // CHECK5-NEXT:    [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i32 7
4515 // CHECK5-NEXT:    store i8** null, i8*** [[TMP33]], align 8, !noalias !26
4516 // CHECK5-NEXT:    [[TMP34:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i32 8
4517 // CHECK5-NEXT:    store i64 10, i64* [[TMP34]], align 8, !noalias !26
4518 // CHECK5-NEXT:    [[TMP35:%.*]] = call i32 @__tgt_target_kernel_nowait(%struct.ident_t* @[[GLOB2]], i64 -1, i32 [[TMP25]], i32 1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i8* null, i32 0, i8* null) #[[ATTR4]]
4519 // CHECK5-NEXT:    [[TMP36:%.*]] = icmp ne i32 [[TMP35]], 0
4520 // CHECK5-NEXT:    br i1 [[TMP36]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]]
4521 // CHECK5:       omp_offload.failed.i:
4522 // CHECK5-NEXT:    [[TMP37:%.*]] = load i16, i16* [[TMP16]], align 2
4523 // CHECK5-NEXT:    [[CONV_I:%.*]] = bitcast i64* [[AA_CASTED_I]] to i16*
4524 // CHECK5-NEXT:    store i16 [[TMP37]], i16* [[CONV_I]], align 2, !noalias !26
4525 // CHECK5-NEXT:    [[TMP38:%.*]] = load i64, i64* [[AA_CASTED_I]], align 8, !noalias !26
4526 // CHECK5-NEXT:    [[TMP39:%.*]] = load i32, i32* [[TMP23]], align 4
4527 // CHECK5-NEXT:    [[CONV4_I:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED_I]] to i32*
4528 // CHECK5-NEXT:    store i32 [[TMP39]], i32* [[CONV4_I]], align 4, !noalias !26
4529 // CHECK5-NEXT:    [[TMP40:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED_I]], align 8, !noalias !26
4530 // CHECK5-NEXT:    [[TMP41:%.*]] = load i32, i32* [[TMP24]], align 4
4531 // CHECK5-NEXT:    [[CONV6_I:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED5_I]] to i32*
4532 // CHECK5-NEXT:    store i32 [[TMP41]], i32* [[CONV6_I]], align 4, !noalias !26
4533 // CHECK5-NEXT:    [[TMP42:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED5_I]], align 8, !noalias !26
4534 // CHECK5-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97(i64 [[TMP38]], i64 [[TMP40]], i64 [[TMP42]]) #[[ATTR4]]
4535 // CHECK5-NEXT:    br label [[DOTOMP_OUTLINED__1_EXIT]]
4536 // CHECK5:       .omp_outlined..1.exit:
4537 // CHECK5-NEXT:    ret i32 0
4538 //
4539 //
4540 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l102
4541 // CHECK5-SAME: (i64 noundef [[A:%.*]]) #[[ATTR3]] {
4542 // CHECK5-NEXT:  entry:
4543 // CHECK5-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
4544 // CHECK5-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
4545 // CHECK5-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
4546 // CHECK5-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
4547 // CHECK5-NEXT:    [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
4548 // CHECK5-NEXT:    [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32*
4549 // CHECK5-NEXT:    store i32 [[TMP0]], i32* [[CONV1]], align 4
4550 // CHECK5-NEXT:    [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
4551 // CHECK5-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]])
4552 // CHECK5-NEXT:    ret void
4553 //
4554 //
4555 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..2
4556 // CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]]) #[[ATTR3]] {
4557 // CHECK5-NEXT:  entry:
4558 // CHECK5-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
4559 // CHECK5-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
4560 // CHECK5-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
4561 // CHECK5-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
4562 // CHECK5-NEXT:    [[TMP:%.*]] = alloca i32, align 4
4563 // CHECK5-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
4564 // CHECK5-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
4565 // CHECK5-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
4566 // CHECK5-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
4567 // CHECK5-NEXT:    [[A1:%.*]] = alloca i32, align 4
4568 // CHECK5-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
4569 // CHECK5-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
4570 // CHECK5-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
4571 // CHECK5-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
4572 // CHECK5-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
4573 // CHECK5-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
4574 // CHECK5-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
4575 // CHECK5-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
4576 // CHECK5-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
4577 // CHECK5-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
4578 // CHECK5-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
4579 // CHECK5-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
4580 // CHECK5-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
4581 // CHECK5-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
4582 // CHECK5:       cond.true:
4583 // CHECK5-NEXT:    br label [[COND_END:%.*]]
4584 // CHECK5:       cond.false:
4585 // CHECK5-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
4586 // CHECK5-NEXT:    br label [[COND_END]]
4587 // CHECK5:       cond.end:
4588 // CHECK5-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
4589 // CHECK5-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
4590 // CHECK5-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
4591 // CHECK5-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
4592 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
4593 // CHECK5:       omp.inner.for.cond:
4594 // CHECK5-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
4595 // CHECK5-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
4596 // CHECK5-NEXT:    [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
4597 // CHECK5-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
4598 // CHECK5:       omp.inner.for.body:
4599 // CHECK5-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
4600 // CHECK5-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
4601 // CHECK5-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
4602 // CHECK5-NEXT:    store i32 [[ADD]], i32* [[A1]], align 4, !nontemporal !27
4603 // CHECK5-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A1]], align 4, !nontemporal !27
4604 // CHECK5-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
4605 // CHECK5-NEXT:    store i32 [[ADD3]], i32* [[A1]], align 4, !nontemporal !27
4606 // CHECK5-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
4607 // CHECK5:       omp.body.continue:
4608 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
4609 // CHECK5:       omp.inner.for.inc:
4610 // CHECK5-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
4611 // CHECK5-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP9]], 1
4612 // CHECK5-NEXT:    store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4
4613 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]]
4614 // CHECK5:       omp.inner.for.end:
4615 // CHECK5-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
4616 // CHECK5:       omp.loop.exit:
4617 // CHECK5-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
4618 // CHECK5-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
4619 // CHECK5-NEXT:    [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0
4620 // CHECK5-NEXT:    br i1 [[TMP11]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
4621 // CHECK5:       .omp.final.then:
4622 // CHECK5-NEXT:    store i32 10, i32* [[CONV]], align 4
4623 // CHECK5-NEXT:    br label [[DOTOMP_FINAL_DONE]]
4624 // CHECK5:       .omp.final.done:
4625 // CHECK5-NEXT:    ret void
4626 //
4627 //
4628 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111
4629 // CHECK5-SAME: (i64 noundef [[AA:%.*]]) #[[ATTR2]] {
4630 // CHECK5-NEXT:  entry:
4631 // CHECK5-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
4632 // CHECK5-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
4633 // CHECK5-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
4634 // CHECK5-NEXT:    [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
4635 // CHECK5-NEXT:    [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
4636 // CHECK5-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
4637 // CHECK5-NEXT:    store i16 [[TMP0]], i16* [[CONV1]], align 2
4638 // CHECK5-NEXT:    [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
4639 // CHECK5-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP1]])
4640 // CHECK5-NEXT:    ret void
4641 //
4642 //
4643 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..3
4644 // CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR3]] {
4645 // CHECK5-NEXT:  entry:
4646 // CHECK5-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
4647 // CHECK5-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
4648 // CHECK5-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
4649 // CHECK5-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
4650 // CHECK5-NEXT:    [[TMP:%.*]] = alloca i32, align 4
4651 // CHECK5-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
4652 // CHECK5-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
4653 // CHECK5-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
4654 // CHECK5-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
4655 // CHECK5-NEXT:    [[I:%.*]] = alloca i32, align 4
4656 // CHECK5-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
4657 // CHECK5-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
4658 // CHECK5-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
4659 // CHECK5-NEXT:    [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
4660 // CHECK5-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
4661 // CHECK5-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
4662 // CHECK5-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
4663 // CHECK5-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
4664 // CHECK5-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
4665 // CHECK5-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
4666 // CHECK5-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
4667 // CHECK5-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
4668 // CHECK5-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
4669 // CHECK5-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
4670 // CHECK5:       cond.true:
4671 // CHECK5-NEXT:    br label [[COND_END:%.*]]
4672 // CHECK5:       cond.false:
4673 // CHECK5-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
4674 // CHECK5-NEXT:    br label [[COND_END]]
4675 // CHECK5:       cond.end:
4676 // CHECK5-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
4677 // CHECK5-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
4678 // CHECK5-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
4679 // CHECK5-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
4680 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
4681 // CHECK5:       omp.inner.for.cond:
4682 // CHECK5-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30
4683 // CHECK5-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !30
4684 // CHECK5-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
4685 // CHECK5-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
4686 // CHECK5:       omp.inner.for.body:
4687 // CHECK5-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30
4688 // CHECK5-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
4689 // CHECK5-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
4690 // CHECK5-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !30
4691 // CHECK5-NEXT:    [[TMP8:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !30
4692 // CHECK5-NEXT:    [[CONV2:%.*]] = sext i16 [[TMP8]] to i32
4693 // CHECK5-NEXT:    [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
4694 // CHECK5-NEXT:    [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
4695 // CHECK5-NEXT:    store i16 [[CONV4]], i16* [[CONV]], align 2, !llvm.access.group !30
4696 // CHECK5-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
4697 // CHECK5:       omp.body.continue:
4698 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
4699 // CHECK5:       omp.inner.for.inc:
4700 // CHECK5-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30
4701 // CHECK5-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP9]], 1
4702 // CHECK5-NEXT:    store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30
4703 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP31:![0-9]+]]
4704 // CHECK5:       omp.inner.for.end:
4705 // CHECK5-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
4706 // CHECK5:       omp.loop.exit:
4707 // CHECK5-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
4708 // CHECK5-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
4709 // CHECK5-NEXT:    [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0
4710 // CHECK5-NEXT:    br i1 [[TMP11]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
4711 // CHECK5:       .omp.final.then:
4712 // CHECK5-NEXT:    store i32 10, i32* [[I]], align 4
4713 // CHECK5-NEXT:    br label [[DOTOMP_FINAL_DONE]]
4714 // CHECK5:       .omp.final.done:
4715 // CHECK5-NEXT:    ret void
4716 //
4717 //
4718 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118
4719 // CHECK5-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] {
4720 // CHECK5-NEXT:  entry:
4721 // CHECK5-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
4722 // CHECK5-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
4723 // CHECK5-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
4724 // CHECK5-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
4725 // CHECK5-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
4726 // CHECK5-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
4727 // CHECK5-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
4728 // CHECK5-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
4729 // CHECK5-NEXT:    [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
4730 // CHECK5-NEXT:    [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
4731 // CHECK5-NEXT:    store i32 [[TMP0]], i32* [[CONV2]], align 4
4732 // CHECK5-NEXT:    [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
4733 // CHECK5-NEXT:    [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
4734 // CHECK5-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
4735 // CHECK5-NEXT:    store i16 [[TMP2]], i16* [[CONV3]], align 2
4736 // CHECK5-NEXT:    [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
4737 // CHECK5-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
4738 // CHECK5-NEXT:    ret void
4739 //
4740 //
4741 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..6
4742 // CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR3]] {
4743 // CHECK5-NEXT:  entry:
4744 // CHECK5-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
4745 // CHECK5-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
4746 // CHECK5-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
4747 // CHECK5-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
4748 // CHECK5-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
4749 // CHECK5-NEXT:    [[TMP:%.*]] = alloca i32, align 4
4750 // CHECK5-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
4751 // CHECK5-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
4752 // CHECK5-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
4753 // CHECK5-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
4754 // CHECK5-NEXT:    [[I:%.*]] = alloca i32, align 4
4755 // CHECK5-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
4756 // CHECK5-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
4757 // CHECK5-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
4758 // CHECK5-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
4759 // CHECK5-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
4760 // CHECK5-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
4761 // CHECK5-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
4762 // CHECK5-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
4763 // CHECK5-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
4764 // CHECK5-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
4765 // CHECK5-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
4766 // CHECK5-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
4767 // CHECK5-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
4768 // CHECK5-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
4769 // CHECK5-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
4770 // CHECK5-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
4771 // CHECK5:       cond.true:
4772 // CHECK5-NEXT:    br label [[COND_END:%.*]]
4773 // CHECK5:       cond.false:
4774 // CHECK5-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
4775 // CHECK5-NEXT:    br label [[COND_END]]
4776 // CHECK5:       cond.end:
4777 // CHECK5-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
4778 // CHECK5-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
4779 // CHECK5-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
4780 // CHECK5-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
4781 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
4782 // CHECK5:       omp.inner.for.cond:
4783 // CHECK5-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33
4784 // CHECK5-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !33
4785 // CHECK5-NEXT:    [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
4786 // CHECK5-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
4787 // CHECK5:       omp.inner.for.body:
4788 // CHECK5-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33
4789 // CHECK5-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
4790 // CHECK5-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
4791 // CHECK5-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !33
4792 // CHECK5-NEXT:    [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !33
4793 // CHECK5-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
4794 // CHECK5-NEXT:    store i32 [[ADD3]], i32* [[CONV]], align 4, !llvm.access.group !33
4795 // CHECK5-NEXT:    [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 2, !llvm.access.group !33
4796 // CHECK5-NEXT:    [[CONV4:%.*]] = sext i16 [[TMP9]] to i32
4797 // CHECK5-NEXT:    [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
4798 // CHECK5-NEXT:    [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
4799 // CHECK5-NEXT:    store i16 [[CONV6]], i16* [[CONV1]], align 2, !llvm.access.group !33
4800 // CHECK5-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
4801 // CHECK5:       omp.body.continue:
4802 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
4803 // CHECK5:       omp.inner.for.inc:
4804 // CHECK5-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33
4805 // CHECK5-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1
4806 // CHECK5-NEXT:    store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33
4807 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP34:![0-9]+]]
4808 // CHECK5:       omp.inner.for.end:
4809 // CHECK5-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
4810 // CHECK5:       omp.loop.exit:
4811 // CHECK5-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
4812 // CHECK5-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
4813 // CHECK5-NEXT:    [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
4814 // CHECK5-NEXT:    br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
4815 // CHECK5:       .omp.final.then:
4816 // CHECK5-NEXT:    store i32 10, i32* [[I]], align 4
4817 // CHECK5-NEXT:    br label [[DOTOMP_FINAL_DONE]]
4818 // CHECK5:       .omp.final.done:
4819 // CHECK5-NEXT:    ret void
4820 //
4821 //
4822 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142
4823 // CHECK5-SAME: (i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] {
4824 // CHECK5-NEXT:  entry:
4825 // CHECK5-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
4826 // CHECK5-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
4827 // CHECK5-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
4828 // CHECK5-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 8
4829 // CHECK5-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
4830 // CHECK5-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
4831 // CHECK5-NEXT:    [[VLA_ADDR4:%.*]] = alloca i64, align 8
4832 // CHECK5-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 8
4833 // CHECK5-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
4834 // CHECK5-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
4835 // CHECK5-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
4836 // CHECK5-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
4837 // CHECK5-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
4838 // CHECK5-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 8
4839 // CHECK5-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
4840 // CHECK5-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
4841 // CHECK5-NEXT:    store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
4842 // CHECK5-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 8
4843 // CHECK5-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
4844 // CHECK5-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
4845 // CHECK5-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
4846 // CHECK5-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
4847 // CHECK5-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
4848 // CHECK5-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
4849 // CHECK5-NEXT:    [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
4850 // CHECK5-NEXT:    [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
4851 // CHECK5-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
4852 // CHECK5-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
4853 // CHECK5-NEXT:    [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
4854 // CHECK5-NEXT:    [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
4855 // CHECK5-NEXT:    store i32 [[TMP8]], i32* [[CONV5]], align 4
4856 // CHECK5-NEXT:    [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
4857 // CHECK5-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]])
4858 // CHECK5-NEXT:    ret void
4859 //
4860 //
4861 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..9
4862 // CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR3]] {
4863 // CHECK5-NEXT:  entry:
4864 // CHECK5-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
4865 // CHECK5-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
4866 // CHECK5-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
4867 // CHECK5-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
4868 // CHECK5-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
4869 // CHECK5-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 8
4870 // CHECK5-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
4871 // CHECK5-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
4872 // CHECK5-NEXT:    [[VLA_ADDR4:%.*]] = alloca i64, align 8
4873 // CHECK5-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 8
4874 // CHECK5-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
4875 // CHECK5-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
4876 // CHECK5-NEXT:    [[TMP:%.*]] = alloca i32, align 4
4877 // CHECK5-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
4878 // CHECK5-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
4879 // CHECK5-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
4880 // CHECK5-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
4881 // CHECK5-NEXT:    [[I:%.*]] = alloca i32, align 4
4882 // CHECK5-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
4883 // CHECK5-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
4884 // CHECK5-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
4885 // CHECK5-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
4886 // CHECK5-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
4887 // CHECK5-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 8
4888 // CHECK5-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
4889 // CHECK5-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
4890 // CHECK5-NEXT:    store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
4891 // CHECK5-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 8
4892 // CHECK5-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
4893 // CHECK5-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
4894 // CHECK5-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
4895 // CHECK5-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
4896 // CHECK5-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
4897 // CHECK5-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
4898 // CHECK5-NEXT:    [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
4899 // CHECK5-NEXT:    [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
4900 // CHECK5-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
4901 // CHECK5-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
4902 // CHECK5-NEXT:    [[ARRAYDECAY:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 0
4903 // CHECK5-NEXT:    call void @llvm.assume(i1 true) [ "align"(float* [[ARRAYDECAY]], i64 16) ]
4904 // CHECK5-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
4905 // CHECK5-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
4906 // CHECK5-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
4907 // CHECK5-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
4908 // CHECK5-NEXT:    [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
4909 // CHECK5-NEXT:    [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4
4910 // CHECK5-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
4911 // CHECK5-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
4912 // CHECK5-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP10]], 9
4913 // CHECK5-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
4914 // CHECK5:       cond.true:
4915 // CHECK5-NEXT:    br label [[COND_END:%.*]]
4916 // CHECK5:       cond.false:
4917 // CHECK5-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
4918 // CHECK5-NEXT:    br label [[COND_END]]
4919 // CHECK5:       cond.end:
4920 // CHECK5-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ]
4921 // CHECK5-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
4922 // CHECK5-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
4923 // CHECK5-NEXT:    store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4
4924 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
4925 // CHECK5:       omp.inner.for.cond:
4926 // CHECK5-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36
4927 // CHECK5-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !36
4928 // CHECK5-NEXT:    [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
4929 // CHECK5-NEXT:    br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
4930 // CHECK5:       omp.inner.for.body:
4931 // CHECK5-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36
4932 // CHECK5-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1
4933 // CHECK5-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
4934 // CHECK5-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !36
4935 // CHECK5-NEXT:    [[TMP16:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !36
4936 // CHECK5-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP16]], 1
4937 // CHECK5-NEXT:    store i32 [[ADD6]], i32* [[CONV]], align 4, !llvm.access.group !36
4938 // CHECK5-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
4939 // CHECK5-NEXT:    [[TMP17:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !36
4940 // CHECK5-NEXT:    [[CONV7:%.*]] = fpext float [[TMP17]] to double
4941 // CHECK5-NEXT:    [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00
4942 // CHECK5-NEXT:    [[CONV9:%.*]] = fptrunc double [[ADD8]] to float
4943 // CHECK5-NEXT:    store float [[CONV9]], float* [[ARRAYIDX]], align 4, !llvm.access.group !36
4944 // CHECK5-NEXT:    [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3
4945 // CHECK5-NEXT:    [[TMP18:%.*]] = load float, float* [[ARRAYIDX10]], align 4, !llvm.access.group !36
4946 // CHECK5-NEXT:    [[CONV11:%.*]] = fpext float [[TMP18]] to double
4947 // CHECK5-NEXT:    [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00
4948 // CHECK5-NEXT:    [[CONV13:%.*]] = fptrunc double [[ADD12]] to float
4949 // CHECK5-NEXT:    store float [[CONV13]], float* [[ARRAYIDX10]], align 4, !llvm.access.group !36
4950 // CHECK5-NEXT:    [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1
4951 // CHECK5-NEXT:    [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX14]], i64 0, i64 2
4952 // CHECK5-NEXT:    [[TMP19:%.*]] = load double, double* [[ARRAYIDX15]], align 8, !llvm.access.group !36
4953 // CHECK5-NEXT:    [[ADD16:%.*]] = fadd double [[TMP19]], 1.000000e+00
4954 // CHECK5-NEXT:    store double [[ADD16]], double* [[ARRAYIDX15]], align 8, !llvm.access.group !36
4955 // CHECK5-NEXT:    [[TMP20:%.*]] = mul nsw i64 1, [[TMP5]]
4956 // CHECK5-NEXT:    [[ARRAYIDX17:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP20]]
4957 // CHECK5-NEXT:    [[ARRAYIDX18:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX17]], i64 3
4958 // CHECK5-NEXT:    [[TMP21:%.*]] = load double, double* [[ARRAYIDX18]], align 8, !llvm.access.group !36
4959 // CHECK5-NEXT:    [[ADD19:%.*]] = fadd double [[TMP21]], 1.000000e+00
4960 // CHECK5-NEXT:    store double [[ADD19]], double* [[ARRAYIDX18]], align 8, !llvm.access.group !36
4961 // CHECK5-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0
4962 // CHECK5-NEXT:    [[TMP22:%.*]] = load i64, i64* [[X]], align 8, !llvm.access.group !36
4963 // CHECK5-NEXT:    [[ADD20:%.*]] = add nsw i64 [[TMP22]], 1
4964 // CHECK5-NEXT:    store i64 [[ADD20]], i64* [[X]], align 8, !llvm.access.group !36
4965 // CHECK5-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1
4966 // CHECK5-NEXT:    [[TMP23:%.*]] = load i8, i8* [[Y]], align 8, !llvm.access.group !36
4967 // CHECK5-NEXT:    [[CONV21:%.*]] = sext i8 [[TMP23]] to i32
4968 // CHECK5-NEXT:    [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1
4969 // CHECK5-NEXT:    [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8
4970 // CHECK5-NEXT:    store i8 [[CONV23]], i8* [[Y]], align 8, !llvm.access.group !36
4971 // CHECK5-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
4972 // CHECK5:       omp.body.continue:
4973 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
4974 // CHECK5:       omp.inner.for.inc:
4975 // CHECK5-NEXT:    [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36
4976 // CHECK5-NEXT:    [[ADD24:%.*]] = add nsw i32 [[TMP24]], 1
4977 // CHECK5-NEXT:    store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36
4978 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP37:![0-9]+]]
4979 // CHECK5:       omp.inner.for.end:
4980 // CHECK5-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
4981 // CHECK5:       omp.loop.exit:
4982 // CHECK5-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]])
4983 // CHECK5-NEXT:    [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
4984 // CHECK5-NEXT:    [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
4985 // CHECK5-NEXT:    br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
4986 // CHECK5:       .omp.final.then:
4987 // CHECK5-NEXT:    store i32 10, i32* [[I]], align 4
4988 // CHECK5-NEXT:    br label [[DOTOMP_FINAL_DONE]]
4989 // CHECK5:       .omp.final.done:
4990 // CHECK5-NEXT:    ret void
4991 //
4992 //
4993 // CHECK5-LABEL: define {{[^@]+}}@_Z3bari
4994 // CHECK5-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {
4995 // CHECK5-NEXT:  entry:
4996 // CHECK5-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
4997 // CHECK5-NEXT:    [[A:%.*]] = alloca i32, align 4
4998 // CHECK5-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8
4999 // CHECK5-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
5000 // CHECK5-NEXT:    store i32 0, i32* [[A]], align 4
5001 // CHECK5-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
5002 // CHECK5-NEXT:    [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]])
5003 // CHECK5-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
5004 // CHECK5-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
5005 // CHECK5-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
5006 // CHECK5-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
5007 // CHECK5-NEXT:    [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP2]])
5008 // CHECK5-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
5009 // CHECK5-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
5010 // CHECK5-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
5011 // CHECK5-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
5012 // CHECK5-NEXT:    [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]])
5013 // CHECK5-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
5014 // CHECK5-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
5015 // CHECK5-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
5016 // CHECK5-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
5017 // CHECK5-NEXT:    [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]])
5018 // CHECK5-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
5019 // CHECK5-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
5020 // CHECK5-NEXT:    store i32 [[ADD6]], i32* [[A]], align 4
5021 // CHECK5-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
5022 // CHECK5-NEXT:    ret i32 [[TMP8]]
5023 //
5024 //
5025 // CHECK5-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
5026 // CHECK5-SAME: (%struct.S1* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 {
5027 // CHECK5-NEXT:  entry:
5028 // CHECK5-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
5029 // CHECK5-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
5030 // CHECK5-NEXT:    [[B:%.*]] = alloca i32, align 4
5031 // CHECK5-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 8
5032 // CHECK5-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
5033 // CHECK5-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
5034 // CHECK5-NEXT:    [[B_CASTED:%.*]] = alloca i64, align 8
5035 // CHECK5-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
5036 // CHECK5-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [6 x i8*], align 8
5037 // CHECK5-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [6 x i8*], align 8
5038 // CHECK5-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [6 x i8*], align 8
5039 // CHECK5-NEXT:    [[DOTOFFLOAD_SIZES:%.*]] = alloca [6 x i64], align 8
5040 // CHECK5-NEXT:    [[TMP:%.*]] = alloca i32, align 4
5041 // CHECK5-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
5042 // CHECK5-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
5043 // CHECK5-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
5044 // CHECK5-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
5045 // CHECK5-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
5046 // CHECK5-NEXT:    store i32 [[ADD]], i32* [[B]], align 4
5047 // CHECK5-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
5048 // CHECK5-NEXT:    [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
5049 // CHECK5-NEXT:    [[TMP3:%.*]] = call i8* @llvm.stacksave()
5050 // CHECK5-NEXT:    store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8
5051 // CHECK5-NEXT:    [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]
5052 // CHECK5-NEXT:    [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2
5053 // CHECK5-NEXT:    store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8
5054 // CHECK5-NEXT:    [[TMP5:%.*]] = load i32, i32* [[N_ADDR]], align 4
5055 // CHECK5-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 60
5056 // CHECK5-NEXT:    [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8
5057 // CHECK5-NEXT:    store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
5058 // CHECK5-NEXT:    [[TMP6:%.*]] = load i32, i32* [[B]], align 4
5059 // CHECK5-NEXT:    [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32*
5060 // CHECK5-NEXT:    store i32 [[TMP6]], i32* [[CONV]], align 4
5061 // CHECK5-NEXT:    [[TMP7:%.*]] = load i64, i64* [[B_CASTED]], align 8
5062 // CHECK5-NEXT:    [[TMP8:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
5063 // CHECK5-NEXT:    [[TOBOOL:%.*]] = trunc i8 [[TMP8]] to i1
5064 // CHECK5-NEXT:    [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
5065 // CHECK5-NEXT:    [[FROMBOOL3:%.*]] = zext i1 [[TOBOOL]] to i8
5066 // CHECK5-NEXT:    store i8 [[FROMBOOL3]], i8* [[CONV2]], align 1
5067 // CHECK5-NEXT:    [[TMP9:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
5068 // CHECK5-NEXT:    [[TMP10:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
5069 // CHECK5-NEXT:    [[TOBOOL4:%.*]] = trunc i8 [[TMP10]] to i1
5070 // CHECK5-NEXT:    br i1 [[TOBOOL4]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
5071 // CHECK5:       omp_if.then:
5072 // CHECK5-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
5073 // CHECK5-NEXT:    [[TMP11:%.*]] = mul nuw i64 2, [[TMP2]]
5074 // CHECK5-NEXT:    [[TMP12:%.*]] = mul nuw i64 [[TMP11]], 2
5075 // CHECK5-NEXT:    [[TMP13:%.*]] = bitcast [6 x i64]* [[DOTOFFLOAD_SIZES]] to i8*
5076 // CHECK5-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP13]], i8* align 8 bitcast ([6 x i64]* @.offload_sizes.13 to i8*), i64 48, i1 false)
5077 // CHECK5-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
5078 // CHECK5-NEXT:    [[TMP15:%.*]] = bitcast i8** [[TMP14]] to %struct.S1**
5079 // CHECK5-NEXT:    store %struct.S1* [[THIS1]], %struct.S1** [[TMP15]], align 8
5080 // CHECK5-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
5081 // CHECK5-NEXT:    [[TMP17:%.*]] = bitcast i8** [[TMP16]] to double**
5082 // CHECK5-NEXT:    store double* [[A]], double** [[TMP17]], align 8
5083 // CHECK5-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
5084 // CHECK5-NEXT:    store i8* null, i8** [[TMP18]], align 8
5085 // CHECK5-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
5086 // CHECK5-NEXT:    [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64*
5087 // CHECK5-NEXT:    store i64 [[TMP7]], i64* [[TMP20]], align 8
5088 // CHECK5-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
5089 // CHECK5-NEXT:    [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i64*
5090 // CHECK5-NEXT:    store i64 [[TMP7]], i64* [[TMP22]], align 8
5091 // CHECK5-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
5092 // CHECK5-NEXT:    store i8* null, i8** [[TMP23]], align 8
5093 // CHECK5-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
5094 // CHECK5-NEXT:    [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i64*
5095 // CHECK5-NEXT:    store i64 2, i64* [[TMP25]], align 8
5096 // CHECK5-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
5097 // CHECK5-NEXT:    [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64*
5098 // CHECK5-NEXT:    store i64 2, i64* [[TMP27]], align 8
5099 // CHECK5-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
5100 // CHECK5-NEXT:    store i8* null, i8** [[TMP28]], align 8
5101 // CHECK5-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
5102 // CHECK5-NEXT:    [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i64*
5103 // CHECK5-NEXT:    store i64 [[TMP2]], i64* [[TMP30]], align 8
5104 // CHECK5-NEXT:    [[TMP31:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
5105 // CHECK5-NEXT:    [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i64*
5106 // CHECK5-NEXT:    store i64 [[TMP2]], i64* [[TMP32]], align 8
5107 // CHECK5-NEXT:    [[TMP33:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
5108 // CHECK5-NEXT:    store i8* null, i8** [[TMP33]], align 8
5109 // CHECK5-NEXT:    [[TMP34:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
5110 // CHECK5-NEXT:    [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i16**
5111 // CHECK5-NEXT:    store i16* [[VLA]], i16** [[TMP35]], align 8
5112 // CHECK5-NEXT:    [[TMP36:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
5113 // CHECK5-NEXT:    [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i16**
5114 // CHECK5-NEXT:    store i16* [[VLA]], i16** [[TMP37]], align 8
5115 // CHECK5-NEXT:    [[TMP38:%.*]] = getelementptr inbounds [6 x i64], [6 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4
5116 // CHECK5-NEXT:    store i64 [[TMP12]], i64* [[TMP38]], align 8
5117 // CHECK5-NEXT:    [[TMP39:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4
5118 // CHECK5-NEXT:    store i8* null, i8** [[TMP39]], align 8
5119 // CHECK5-NEXT:    [[TMP40:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 5
5120 // CHECK5-NEXT:    [[TMP41:%.*]] = bitcast i8** [[TMP40]] to i64*
5121 // CHECK5-NEXT:    store i64 [[TMP9]], i64* [[TMP41]], align 8
5122 // CHECK5-NEXT:    [[TMP42:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 5
5123 // CHECK5-NEXT:    [[TMP43:%.*]] = bitcast i8** [[TMP42]] to i64*
5124 // CHECK5-NEXT:    store i64 [[TMP9]], i64* [[TMP43]], align 8
5125 // CHECK5-NEXT:    [[TMP44:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 5
5126 // CHECK5-NEXT:    store i8* null, i8** [[TMP44]], align 8
5127 // CHECK5-NEXT:    [[TMP45:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
5128 // CHECK5-NEXT:    [[TMP46:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
5129 // CHECK5-NEXT:    [[TMP47:%.*]] = getelementptr inbounds [6 x i64], [6 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
5130 // CHECK5-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
5131 // CHECK5-NEXT:    [[TMP48:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
5132 // CHECK5-NEXT:    store i32 1, i32* [[TMP48]], align 4
5133 // CHECK5-NEXT:    [[TMP49:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
5134 // CHECK5-NEXT:    store i32 6, i32* [[TMP49]], align 4
5135 // CHECK5-NEXT:    [[TMP50:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
5136 // CHECK5-NEXT:    store i8** [[TMP45]], i8*** [[TMP50]], align 8
5137 // CHECK5-NEXT:    [[TMP51:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
5138 // CHECK5-NEXT:    store i8** [[TMP46]], i8*** [[TMP51]], align 8
5139 // CHECK5-NEXT:    [[TMP52:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
5140 // CHECK5-NEXT:    store i64* [[TMP47]], i64** [[TMP52]], align 8
5141 // CHECK5-NEXT:    [[TMP53:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
5142 // CHECK5-NEXT:    store i64* getelementptr inbounds ([6 x i64], [6 x i64]* @.offload_maptypes.14, i32 0, i32 0), i64** [[TMP53]], align 8
5143 // CHECK5-NEXT:    [[TMP54:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
5144 // CHECK5-NEXT:    store i8** null, i8*** [[TMP54]], align 8
5145 // CHECK5-NEXT:    [[TMP55:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
5146 // CHECK5-NEXT:    store i8** null, i8*** [[TMP55]], align 8
5147 // CHECK5-NEXT:    [[TMP56:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
5148 // CHECK5-NEXT:    store i64 10, i64* [[TMP56]], align 8
5149 // CHECK5-NEXT:    [[TMP57:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB2]], i64 -1, i32 0, i32 1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
5150 // CHECK5-NEXT:    [[TMP58:%.*]] = icmp ne i32 [[TMP57]], 0
5151 // CHECK5-NEXT:    br i1 [[TMP58]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
5152 // CHECK5:       omp_offload.failed:
5153 // CHECK5-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215(%struct.S1* [[THIS1]], i64 [[TMP7]], i64 2, i64 [[TMP2]], i16* [[VLA]], i64 [[TMP9]]) #[[ATTR4]]
5154 // CHECK5-NEXT:    br label [[OMP_OFFLOAD_CONT]]
5155 // CHECK5:       omp_offload.cont:
5156 // CHECK5-NEXT:    br label [[OMP_IF_END:%.*]]
5157 // CHECK5:       omp_if.else:
5158 // CHECK5-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215(%struct.S1* [[THIS1]], i64 [[TMP7]], i64 2, i64 [[TMP2]], i16* [[VLA]], i64 [[TMP9]]) #[[ATTR4]]
5159 // CHECK5-NEXT:    br label [[OMP_IF_END]]
5160 // CHECK5:       omp_if.end:
5161 // CHECK5-NEXT:    [[TMP59:%.*]] = mul nsw i64 1, [[TMP2]]
5162 // CHECK5-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP59]]
5163 // CHECK5-NEXT:    [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
5164 // CHECK5-NEXT:    [[TMP60:%.*]] = load i16, i16* [[ARRAYIDX5]], align 2
5165 // CHECK5-NEXT:    [[CONV6:%.*]] = sext i16 [[TMP60]] to i32
5166 // CHECK5-NEXT:    [[TMP61:%.*]] = load i32, i32* [[B]], align 4
5167 // CHECK5-NEXT:    [[ADD7:%.*]] = add nsw i32 [[CONV6]], [[TMP61]]
5168 // CHECK5-NEXT:    [[TMP62:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
5169 // CHECK5-NEXT:    call void @llvm.stackrestore(i8* [[TMP62]])
5170 // CHECK5-NEXT:    ret i32 [[ADD7]]
5171 //
5172 //
5173 // CHECK5-LABEL: define {{[^@]+}}@_ZL7fstatici
5174 // CHECK5-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {
5175 // CHECK5-NEXT:  entry:
5176 // CHECK5-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
5177 // CHECK5-NEXT:    [[A:%.*]] = alloca i32, align 4
5178 // CHECK5-NEXT:    [[AA:%.*]] = alloca i16, align 2
5179 // CHECK5-NEXT:    [[AAA:%.*]] = alloca i8, align 1
5180 // CHECK5-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
5181 // CHECK5-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
5182 // CHECK5-NEXT:    [[N_CASTED:%.*]] = alloca i64, align 8
5183 // CHECK5-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
5184 // CHECK5-NEXT:    [[AAA_CASTED:%.*]] = alloca i64, align 8
5185 // CHECK5-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8
5186 // CHECK5-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8
5187 // CHECK5-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8
5188 // CHECK5-NEXT:    [[TMP:%.*]] = alloca i32, align 4
5189 // CHECK5-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
5190 // CHECK5-NEXT:    [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4
5191 // CHECK5-NEXT:    [[DOTCAPTURE_EXPR_5:%.*]] = alloca i32, align 4
5192 // CHECK5-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
5193 // CHECK5-NEXT:    store i32 0, i32* [[A]], align 4
5194 // CHECK5-NEXT:    store i16 0, i16* [[AA]], align 2
5195 // CHECK5-NEXT:    store i8 0, i8* [[AAA]], align 1
5196 // CHECK5-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
5197 // CHECK5-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32*
5198 // CHECK5-NEXT:    store i32 [[TMP0]], i32* [[CONV]], align 4
5199 // CHECK5-NEXT:    [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
5200 // CHECK5-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
5201 // CHECK5-NEXT:    [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32*
5202 // CHECK5-NEXT:    store i32 [[TMP2]], i32* [[CONV1]], align 4
5203 // CHECK5-NEXT:    [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8
5204 // CHECK5-NEXT:    [[TMP4:%.*]] = load i16, i16* [[AA]], align 2
5205 // CHECK5-NEXT:    [[CONV2:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
5206 // CHECK5-NEXT:    store i16 [[TMP4]], i16* [[CONV2]], align 2
5207 // CHECK5-NEXT:    [[TMP5:%.*]] = load i64, i64* [[AA_CASTED]], align 8
5208 // CHECK5-NEXT:    [[TMP6:%.*]] = load i8, i8* [[AAA]], align 1
5209 // CHECK5-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
5210 // CHECK5-NEXT:    store i8 [[TMP6]], i8* [[CONV3]], align 1
5211 // CHECK5-NEXT:    [[TMP7:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
5212 // CHECK5-NEXT:    [[TMP8:%.*]] = load i32, i32* [[N_ADDR]], align 4
5213 // CHECK5-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP8]], 50
5214 // CHECK5-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
5215 // CHECK5:       omp_if.then:
5216 // CHECK5-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
5217 // CHECK5-NEXT:    [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64*
5218 // CHECK5-NEXT:    store i64 [[TMP1]], i64* [[TMP10]], align 8
5219 // CHECK5-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
5220 // CHECK5-NEXT:    [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64*
5221 // CHECK5-NEXT:    store i64 [[TMP1]], i64* [[TMP12]], align 8
5222 // CHECK5-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
5223 // CHECK5-NEXT:    store i8* null, i8** [[TMP13]], align 8
5224 // CHECK5-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
5225 // CHECK5-NEXT:    [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64*
5226 // CHECK5-NEXT:    store i64 [[TMP3]], i64* [[TMP15]], align 8
5227 // CHECK5-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
5228 // CHECK5-NEXT:    [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64*
5229 // CHECK5-NEXT:    store i64 [[TMP3]], i64* [[TMP17]], align 8
5230 // CHECK5-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
5231 // CHECK5-NEXT:    store i8* null, i8** [[TMP18]], align 8
5232 // CHECK5-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
5233 // CHECK5-NEXT:    [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64*
5234 // CHECK5-NEXT:    store i64 [[TMP5]], i64* [[TMP20]], align 8
5235 // CHECK5-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
5236 // CHECK5-NEXT:    [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i64*
5237 // CHECK5-NEXT:    store i64 [[TMP5]], i64* [[TMP22]], align 8
5238 // CHECK5-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
5239 // CHECK5-NEXT:    store i8* null, i8** [[TMP23]], align 8
5240 // CHECK5-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
5241 // CHECK5-NEXT:    [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i64*
5242 // CHECK5-NEXT:    store i64 [[TMP7]], i64* [[TMP25]], align 8
5243 // CHECK5-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
5244 // CHECK5-NEXT:    [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64*
5245 // CHECK5-NEXT:    store i64 [[TMP7]], i64* [[TMP27]], align 8
5246 // CHECK5-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
5247 // CHECK5-NEXT:    store i8* null, i8** [[TMP28]], align 8
5248 // CHECK5-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
5249 // CHECK5-NEXT:    [[TMP30:%.*]] = bitcast i8** [[TMP29]] to [10 x i32]**
5250 // CHECK5-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP30]], align 8
5251 // CHECK5-NEXT:    [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
5252 // CHECK5-NEXT:    [[TMP32:%.*]] = bitcast i8** [[TMP31]] to [10 x i32]**
5253 // CHECK5-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP32]], align 8
5254 // CHECK5-NEXT:    [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4
5255 // CHECK5-NEXT:    store i8* null, i8** [[TMP33]], align 8
5256 // CHECK5-NEXT:    [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
5257 // CHECK5-NEXT:    [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
5258 // CHECK5-NEXT:    [[TMP36:%.*]] = load i32, i32* [[A]], align 4
5259 // CHECK5-NEXT:    store i32 [[TMP36]], i32* [[DOTCAPTURE_EXPR_]], align 4
5260 // CHECK5-NEXT:    [[TMP37:%.*]] = load i32, i32* [[N_ADDR]], align 4
5261 // CHECK5-NEXT:    store i32 [[TMP37]], i32* [[DOTCAPTURE_EXPR_4]], align 4
5262 // CHECK5-NEXT:    [[TMP38:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4
5263 // CHECK5-NEXT:    [[TMP39:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
5264 // CHECK5-NEXT:    [[SUB:%.*]] = sub i32 [[TMP38]], [[TMP39]]
5265 // CHECK5-NEXT:    [[SUB6:%.*]] = sub i32 [[SUB]], 1
5266 // CHECK5-NEXT:    [[ADD:%.*]] = add i32 [[SUB6]], 1
5267 // CHECK5-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], 1
5268 // CHECK5-NEXT:    [[SUB7:%.*]] = sub i32 [[DIV]], 1
5269 // CHECK5-NEXT:    store i32 [[SUB7]], i32* [[DOTCAPTURE_EXPR_5]], align 4
5270 // CHECK5-NEXT:    [[TMP40:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4
5271 // CHECK5-NEXT:    [[ADD8:%.*]] = add i32 [[TMP40]], 1
5272 // CHECK5-NEXT:    [[TMP41:%.*]] = zext i32 [[ADD8]] to i64
5273 // CHECK5-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
5274 // CHECK5-NEXT:    [[TMP42:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
5275 // CHECK5-NEXT:    store i32 1, i32* [[TMP42]], align 4
5276 // CHECK5-NEXT:    [[TMP43:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
5277 // CHECK5-NEXT:    store i32 5, i32* [[TMP43]], align 4
5278 // CHECK5-NEXT:    [[TMP44:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
5279 // CHECK5-NEXT:    store i8** [[TMP34]], i8*** [[TMP44]], align 8
5280 // CHECK5-NEXT:    [[TMP45:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
5281 // CHECK5-NEXT:    store i8** [[TMP35]], i8*** [[TMP45]], align 8
5282 // CHECK5-NEXT:    [[TMP46:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
5283 // CHECK5-NEXT:    store i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes.16, i32 0, i32 0), i64** [[TMP46]], align 8
5284 // CHECK5-NEXT:    [[TMP47:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
5285 // CHECK5-NEXT:    store i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.17, i32 0, i32 0), i64** [[TMP47]], align 8
5286 // CHECK5-NEXT:    [[TMP48:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
5287 // CHECK5-NEXT:    store i8** null, i8*** [[TMP48]], align 8
5288 // CHECK5-NEXT:    [[TMP49:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
5289 // CHECK5-NEXT:    store i8** null, i8*** [[TMP49]], align 8
5290 // CHECK5-NEXT:    [[TMP50:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
5291 // CHECK5-NEXT:    store i64 [[TMP41]], i64* [[TMP50]], align 8
5292 // CHECK5-NEXT:    [[TMP51:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB2]], i64 -1, i32 0, i32 1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
5293 // CHECK5-NEXT:    [[TMP52:%.*]] = icmp ne i32 [[TMP51]], 0
5294 // CHECK5-NEXT:    br i1 [[TMP52]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
5295 // CHECK5:       omp_offload.failed:
5296 // CHECK5-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], i64 [[TMP7]], [10 x i32]* [[B]]) #[[ATTR4]]
5297 // CHECK5-NEXT:    br label [[OMP_OFFLOAD_CONT]]
5298 // CHECK5:       omp_offload.cont:
5299 // CHECK5-NEXT:    br label [[OMP_IF_END:%.*]]
5300 // CHECK5:       omp_if.else:
5301 // CHECK5-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], i64 [[TMP7]], [10 x i32]* [[B]]) #[[ATTR4]]
5302 // CHECK5-NEXT:    br label [[OMP_IF_END]]
5303 // CHECK5:       omp_if.end:
5304 // CHECK5-NEXT:    [[TMP53:%.*]] = load i32, i32* [[A]], align 4
5305 // CHECK5-NEXT:    ret i32 [[TMP53]]
5306 //
5307 //
5308 // CHECK5-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
5309 // CHECK5-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat {
5310 // CHECK5-NEXT:  entry:
5311 // CHECK5-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
5312 // CHECK5-NEXT:    [[A:%.*]] = alloca i32, align 4
5313 // CHECK5-NEXT:    [[AA:%.*]] = alloca i16, align 2
5314 // CHECK5-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
5315 // CHECK5-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
5316 // CHECK5-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
5317 // CHECK5-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8
5318 // CHECK5-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8
5319 // CHECK5-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8
5320 // CHECK5-NEXT:    [[TMP:%.*]] = alloca i32, align 4
5321 // CHECK5-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
5322 // CHECK5-NEXT:    store i32 0, i32* [[A]], align 4
5323 // CHECK5-NEXT:    store i16 0, i16* [[AA]], align 2
5324 // CHECK5-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
5325 // CHECK5-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32*
5326 // CHECK5-NEXT:    store i32 [[TMP0]], i32* [[CONV]], align 4
5327 // CHECK5-NEXT:    [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
5328 // CHECK5-NEXT:    [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
5329 // CHECK5-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
5330 // CHECK5-NEXT:    store i16 [[TMP2]], i16* [[CONV1]], align 2
5331 // CHECK5-NEXT:    [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
5332 // CHECK5-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
5333 // CHECK5-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40
5334 // CHECK5-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
5335 // CHECK5:       omp_if.then:
5336 // CHECK5-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
5337 // CHECK5-NEXT:    [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64*
5338 // CHECK5-NEXT:    store i64 [[TMP1]], i64* [[TMP6]], align 8
5339 // CHECK5-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
5340 // CHECK5-NEXT:    [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64*
5341 // CHECK5-NEXT:    store i64 [[TMP1]], i64* [[TMP8]], align 8
5342 // CHECK5-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
5343 // CHECK5-NEXT:    store i8* null, i8** [[TMP9]], align 8
5344 // CHECK5-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
5345 // CHECK5-NEXT:    [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i64*
5346 // CHECK5-NEXT:    store i64 [[TMP3]], i64* [[TMP11]], align 8
5347 // CHECK5-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
5348 // CHECK5-NEXT:    [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64*
5349 // CHECK5-NEXT:    store i64 [[TMP3]], i64* [[TMP13]], align 8
5350 // CHECK5-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
5351 // CHECK5-NEXT:    store i8* null, i8** [[TMP14]], align 8
5352 // CHECK5-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
5353 // CHECK5-NEXT:    [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]**
5354 // CHECK5-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 8
5355 // CHECK5-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
5356 // CHECK5-NEXT:    [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]**
5357 // CHECK5-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 8
5358 // CHECK5-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
5359 // CHECK5-NEXT:    store i8* null, i8** [[TMP19]], align 8
5360 // CHECK5-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
5361 // CHECK5-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
5362 // CHECK5-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
5363 // CHECK5-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
5364 // CHECK5-NEXT:    store i32 1, i32* [[TMP22]], align 4
5365 // CHECK5-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
5366 // CHECK5-NEXT:    store i32 3, i32* [[TMP23]], align 4
5367 // CHECK5-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
5368 // CHECK5-NEXT:    store i8** [[TMP20]], i8*** [[TMP24]], align 8
5369 // CHECK5-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
5370 // CHECK5-NEXT:    store i8** [[TMP21]], i8*** [[TMP25]], align 8
5371 // CHECK5-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
5372 // CHECK5-NEXT:    store i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.19, i32 0, i32 0), i64** [[TMP26]], align 8
5373 // CHECK5-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
5374 // CHECK5-NEXT:    store i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.20, i32 0, i32 0), i64** [[TMP27]], align 8
5375 // CHECK5-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
5376 // CHECK5-NEXT:    store i8** null, i8*** [[TMP28]], align 8
5377 // CHECK5-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
5378 // CHECK5-NEXT:    store i8** null, i8*** [[TMP29]], align 8
5379 // CHECK5-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
5380 // CHECK5-NEXT:    store i64 10, i64* [[TMP30]], align 8
5381 // CHECK5-NEXT:    [[TMP31:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB2]], i64 -1, i32 0, i32 1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
5382 // CHECK5-NEXT:    [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0
5383 // CHECK5-NEXT:    br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
5384 // CHECK5:       omp_offload.failed:
5385 // CHECK5-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]]
5386 // CHECK5-NEXT:    br label [[OMP_OFFLOAD_CONT]]
5387 // CHECK5:       omp_offload.cont:
5388 // CHECK5-NEXT:    br label [[OMP_IF_END:%.*]]
5389 // CHECK5:       omp_if.else:
5390 // CHECK5-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]]
5391 // CHECK5-NEXT:    br label [[OMP_IF_END]]
5392 // CHECK5:       omp_if.end:
5393 // CHECK5-NEXT:    [[TMP33:%.*]] = load i32, i32* [[A]], align 4
5394 // CHECK5-NEXT:    ret i32 [[TMP33]]
5395 //
5396 //
5397 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215
5398 // CHECK5-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] {
5399 // CHECK5-NEXT:  entry:
5400 // CHECK5-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
5401 // CHECK5-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
5402 // CHECK5-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
5403 // CHECK5-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
5404 // CHECK5-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 8
5405 // CHECK5-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
5406 // CHECK5-NEXT:    [[B_CASTED:%.*]] = alloca i64, align 8
5407 // CHECK5-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
5408 // CHECK5-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
5409 // CHECK5-NEXT:    store i64 [[B]], i64* [[B_ADDR]], align 8
5410 // CHECK5-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
5411 // CHECK5-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
5412 // CHECK5-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 8
5413 // CHECK5-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
5414 // CHECK5-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
5415 // CHECK5-NEXT:    [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
5416 // CHECK5-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
5417 // CHECK5-NEXT:    [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
5418 // CHECK5-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
5419 // CHECK5-NEXT:    [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
5420 // CHECK5-NEXT:    [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
5421 // CHECK5-NEXT:    [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i32*
5422 // CHECK5-NEXT:    store i32 [[TMP4]], i32* [[CONV4]], align 4
5423 // CHECK5-NEXT:    [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
5424 // CHECK5-NEXT:    [[TMP6:%.*]] = load i8, i8* [[CONV3]], align 1
5425 // CHECK5-NEXT:    [[TOBOOL:%.*]] = trunc i8 [[TMP6]] to i1
5426 // CHECK5-NEXT:    [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
5427 // CHECK5-NEXT:    [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
5428 // CHECK5-NEXT:    store i8 [[FROMBOOL]], i8* [[CONV5]], align 1
5429 // CHECK5-NEXT:    [[TMP7:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
5430 // CHECK5-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*, i64)* @.omp_outlined..12 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]], i64 [[TMP7]])
5431 // CHECK5-NEXT:    ret void
5432 //
5433 //
5434 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..12
5435 // CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] {
5436 // CHECK5-NEXT:  entry:
5437 // CHECK5-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
5438 // CHECK5-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
5439 // CHECK5-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
5440 // CHECK5-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
5441 // CHECK5-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
5442 // CHECK5-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
5443 // CHECK5-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 8
5444 // CHECK5-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
5445 // CHECK5-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
5446 // CHECK5-NEXT:    [[TMP:%.*]] = alloca i32, align 4
5447 // CHECK5-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
5448 // CHECK5-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
5449 // CHECK5-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
5450 // CHECK5-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
5451 // CHECK5-NEXT:    [[I:%.*]] = alloca i32, align 4
5452 // CHECK5-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
5453 // CHECK5-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
5454 // CHECK5-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
5455 // CHECK5-NEXT:    store i64 [[B]], i64* [[B_ADDR]], align 8
5456 // CHECK5-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
5457 // CHECK5-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
5458 // CHECK5-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 8
5459 // CHECK5-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
5460 // CHECK5-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
5461 // CHECK5-NEXT:    [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
5462 // CHECK5-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
5463 // CHECK5-NEXT:    [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
5464 // CHECK5-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
5465 // CHECK5-NEXT:    [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
5466 // CHECK5-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
5467 // CHECK5-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
5468 // CHECK5-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
5469 // CHECK5-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
5470 // CHECK5-NEXT:    [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
5471 // CHECK5-NEXT:    [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
5472 // CHECK5-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
5473 // CHECK5-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
5474 // CHECK5-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 9
5475 // CHECK5-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
5476 // CHECK5:       cond.true:
5477 // CHECK5-NEXT:    br label [[COND_END:%.*]]
5478 // CHECK5:       cond.false:
5479 // CHECK5-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
5480 // CHECK5-NEXT:    br label [[COND_END]]
5481 // CHECK5:       cond.end:
5482 // CHECK5-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
5483 // CHECK5-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
5484 // CHECK5-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
5485 // CHECK5-NEXT:    store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
5486 // CHECK5-NEXT:    [[TMP9:%.*]] = load i8, i8* [[CONV3]], align 1
5487 // CHECK5-NEXT:    [[TOBOOL:%.*]] = trunc i8 [[TMP9]] to i1
5488 // CHECK5-NEXT:    br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
5489 // CHECK5:       omp_if.then:
5490 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
5491 // CHECK5:       omp.inner.for.cond:
5492 // CHECK5-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39
5493 // CHECK5-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !39
5494 // CHECK5-NEXT:    [[CMP4:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]
5495 // CHECK5-NEXT:    br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
5496 // CHECK5:       omp.inner.for.body:
5497 // CHECK5-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39
5498 // CHECK5-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1
5499 // CHECK5-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
5500 // CHECK5-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !39
5501 // CHECK5-NEXT:    [[TMP13:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !39
5502 // CHECK5-NEXT:    [[CONV5:%.*]] = sitofp i32 [[TMP13]] to double
5503 // CHECK5-NEXT:    [[ADD6:%.*]] = fadd double [[CONV5]], 1.500000e+00
5504 // CHECK5-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
5505 // CHECK5-NEXT:    store double [[ADD6]], double* [[A]], align 8, !llvm.access.group !39
5506 // CHECK5-NEXT:    [[A7:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
5507 // CHECK5-NEXT:    [[TMP14:%.*]] = load double, double* [[A7]], align 8, !llvm.access.group !39
5508 // CHECK5-NEXT:    [[INC:%.*]] = fadd double [[TMP14]], 1.000000e+00
5509 // CHECK5-NEXT:    store double [[INC]], double* [[A7]], align 8, !llvm.access.group !39
5510 // CHECK5-NEXT:    [[CONV8:%.*]] = fptosi double [[INC]] to i16
5511 // CHECK5-NEXT:    [[TMP15:%.*]] = mul nsw i64 1, [[TMP2]]
5512 // CHECK5-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP15]]
5513 // CHECK5-NEXT:    [[ARRAYIDX9:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
5514 // CHECK5-NEXT:    store i16 [[CONV8]], i16* [[ARRAYIDX9]], align 2, !llvm.access.group !39
5515 // CHECK5-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
5516 // CHECK5:       omp.body.continue:
5517 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
5518 // CHECK5:       omp.inner.for.inc:
5519 // CHECK5-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39
5520 // CHECK5-NEXT:    [[ADD10:%.*]] = add nsw i32 [[TMP16]], 1
5521 // CHECK5-NEXT:    store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39
5522 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP40:![0-9]+]]
5523 // CHECK5:       omp.inner.for.end:
5524 // CHECK5-NEXT:    br label [[OMP_IF_END:%.*]]
5525 // CHECK5:       omp_if.else:
5526 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND11:%.*]]
5527 // CHECK5:       omp.inner.for.cond11:
5528 // CHECK5-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
5529 // CHECK5-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
5530 // CHECK5-NEXT:    [[CMP12:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]]
5531 // CHECK5-NEXT:    br i1 [[CMP12]], label [[OMP_INNER_FOR_BODY13:%.*]], label [[OMP_INNER_FOR_END27:%.*]]
5532 // CHECK5:       omp.inner.for.body13:
5533 // CHECK5-NEXT:    [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
5534 // CHECK5-NEXT:    [[MUL14:%.*]] = mul nsw i32 [[TMP19]], 1
5535 // CHECK5-NEXT:    [[ADD15:%.*]] = add nsw i32 0, [[MUL14]]
5536 // CHECK5-NEXT:    store i32 [[ADD15]], i32* [[I]], align 4
5537 // CHECK5-NEXT:    [[TMP20:%.*]] = load i32, i32* [[CONV]], align 4
5538 // CHECK5-NEXT:    [[CONV16:%.*]] = sitofp i32 [[TMP20]] to double
5539 // CHECK5-NEXT:    [[ADD17:%.*]] = fadd double [[CONV16]], 1.500000e+00
5540 // CHECK5-NEXT:    [[A18:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
5541 // CHECK5-NEXT:    store double [[ADD17]], double* [[A18]], align 8
5542 // CHECK5-NEXT:    [[A19:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
5543 // CHECK5-NEXT:    [[TMP21:%.*]] = load double, double* [[A19]], align 8
5544 // CHECK5-NEXT:    [[INC20:%.*]] = fadd double [[TMP21]], 1.000000e+00
5545 // CHECK5-NEXT:    store double [[INC20]], double* [[A19]], align 8
5546 // CHECK5-NEXT:    [[CONV21:%.*]] = fptosi double [[INC20]] to i16
5547 // CHECK5-NEXT:    [[TMP22:%.*]] = mul nsw i64 1, [[TMP2]]
5548 // CHECK5-NEXT:    [[ARRAYIDX22:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP22]]
5549 // CHECK5-NEXT:    [[ARRAYIDX23:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX22]], i64 1
5550 // CHECK5-NEXT:    store i16 [[CONV21]], i16* [[ARRAYIDX23]], align 2
5551 // CHECK5-NEXT:    br label [[OMP_BODY_CONTINUE24:%.*]]
5552 // CHECK5:       omp.body.continue24:
5553 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_INC25:%.*]]
5554 // CHECK5:       omp.inner.for.inc25:
5555 // CHECK5-NEXT:    [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
5556 // CHECK5-NEXT:    [[ADD26:%.*]] = add nsw i32 [[TMP23]], 1
5557 // CHECK5-NEXT:    store i32 [[ADD26]], i32* [[DOTOMP_IV]], align 4
5558 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND11]], !llvm.loop [[LOOP42:![0-9]+]]
5559 // CHECK5:       omp.inner.for.end27:
5560 // CHECK5-NEXT:    br label [[OMP_IF_END]]
5561 // CHECK5:       omp_if.end:
5562 // CHECK5-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
5563 // CHECK5:       omp.loop.exit:
5564 // CHECK5-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
5565 // CHECK5-NEXT:    [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
5566 // CHECK5-NEXT:    [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0
5567 // CHECK5-NEXT:    br i1 [[TMP25]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
5568 // CHECK5:       .omp.final.then:
5569 // CHECK5-NEXT:    store i32 10, i32* [[I]], align 4
5570 // CHECK5-NEXT:    br label [[DOTOMP_FINAL_DONE]]
5571 // CHECK5:       .omp.final.done:
5572 // CHECK5-NEXT:    ret void
5573 //
5574 //
5575 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197
5576 // CHECK5-SAME: (i64 noundef [[A:%.*]], i64 noundef [[N:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
5577 // CHECK5-NEXT:  entry:
5578 // CHECK5-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
5579 // CHECK5-NEXT:    [[N_ADDR:%.*]] = alloca i64, align 8
5580 // CHECK5-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
5581 // CHECK5-NEXT:    [[AAA_ADDR:%.*]] = alloca i64, align 8
5582 // CHECK5-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
5583 // CHECK5-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
5584 // CHECK5-NEXT:    [[N_CASTED:%.*]] = alloca i64, align 8
5585 // CHECK5-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
5586 // CHECK5-NEXT:    [[AAA_CASTED:%.*]] = alloca i64, align 8
5587 // CHECK5-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
5588 // CHECK5-NEXT:    store i64 [[N]], i64* [[N_ADDR]], align 8
5589 // CHECK5-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
5590 // CHECK5-NEXT:    store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
5591 // CHECK5-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
5592 // CHECK5-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
5593 // CHECK5-NEXT:    [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32*
5594 // CHECK5-NEXT:    [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
5595 // CHECK5-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
5596 // CHECK5-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
5597 // CHECK5-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
5598 // CHECK5-NEXT:    [[CONV4:%.*]] = bitcast i64* [[A_CASTED]] to i32*
5599 // CHECK5-NEXT:    store i32 [[TMP1]], i32* [[CONV4]], align 4
5600 // CHECK5-NEXT:    [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
5601 // CHECK5-NEXT:    [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 4
5602 // CHECK5-NEXT:    [[CONV5:%.*]] = bitcast i64* [[N_CASTED]] to i32*
5603 // CHECK5-NEXT:    store i32 [[TMP3]], i32* [[CONV5]], align 4
5604 // CHECK5-NEXT:    [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8
5605 // CHECK5-NEXT:    [[TMP5:%.*]] = load i16, i16* [[CONV2]], align 2
5606 // CHECK5-NEXT:    [[CONV6:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
5607 // CHECK5-NEXT:    store i16 [[TMP5]], i16* [[CONV6]], align 2
5608 // CHECK5-NEXT:    [[TMP6:%.*]] = load i64, i64* [[AA_CASTED]], align 8
5609 // CHECK5-NEXT:    [[TMP7:%.*]] = load i8, i8* [[CONV3]], align 1
5610 // CHECK5-NEXT:    [[CONV7:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
5611 // CHECK5-NEXT:    store i8 [[TMP7]], i8* [[CONV7]], align 1
5612 // CHECK5-NEXT:    [[TMP8:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
5613 // CHECK5-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, [10 x i32]*)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]], [10 x i32]* [[TMP0]])
5614 // CHECK5-NEXT:    ret void
5615 //
5616 //
5617 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..15
5618 // CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[N:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] {
5619 // CHECK5-NEXT:  entry:
5620 // CHECK5-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
5621 // CHECK5-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
5622 // CHECK5-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
5623 // CHECK5-NEXT:    [[N_ADDR:%.*]] = alloca i64, align 8
5624 // CHECK5-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
5625 // CHECK5-NEXT:    [[AAA_ADDR:%.*]] = alloca i64, align 8
5626 // CHECK5-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
5627 // CHECK5-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
5628 // CHECK5-NEXT:    [[TMP:%.*]] = alloca i32, align 4
5629 // CHECK5-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
5630 // CHECK5-NEXT:    [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4
5631 // CHECK5-NEXT:    [[DOTCAPTURE_EXPR_5:%.*]] = alloca i32, align 4
5632 // CHECK5-NEXT:    [[I:%.*]] = alloca i32, align 4
5633 // CHECK5-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
5634 // CHECK5-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
5635 // CHECK5-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
5636 // CHECK5-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
5637 // CHECK5-NEXT:    [[I8:%.*]] = alloca i32, align 4
5638 // CHECK5-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
5639 // CHECK5-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
5640 // CHECK5-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
5641 // CHECK5-NEXT:    store i64 [[N]], i64* [[N_ADDR]], align 8
5642 // CHECK5-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
5643 // CHECK5-NEXT:    store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
5644 // CHECK5-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
5645 // CHECK5-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
5646 // CHECK5-NEXT:    [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32*
5647 // CHECK5-NEXT:    [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
5648 // CHECK5-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
5649 // CHECK5-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
5650 // CHECK5-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
5651 // CHECK5-NEXT:    store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
5652 // CHECK5-NEXT:    [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4
5653 // CHECK5-NEXT:    store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_4]], align 4
5654 // CHECK5-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4
5655 // CHECK5-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
5656 // CHECK5-NEXT:    [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]]
5657 // CHECK5-NEXT:    [[SUB6:%.*]] = sub i32 [[SUB]], 1
5658 // CHECK5-NEXT:    [[ADD:%.*]] = add i32 [[SUB6]], 1
5659 // CHECK5-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], 1
5660 // CHECK5-NEXT:    [[SUB7:%.*]] = sub i32 [[DIV]], 1
5661 // CHECK5-NEXT:    store i32 [[SUB7]], i32* [[DOTCAPTURE_EXPR_5]], align 4
5662 // CHECK5-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
5663 // CHECK5-NEXT:    store i32 [[TMP5]], i32* [[I]], align 4
5664 // CHECK5-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
5665 // CHECK5-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4
5666 // CHECK5-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]]
5667 // CHECK5-NEXT:    br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
5668 // CHECK5:       omp.precond.then:
5669 // CHECK5-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
5670 // CHECK5-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4
5671 // CHECK5-NEXT:    store i32 [[TMP8]], i32* [[DOTOMP_UB]], align 4
5672 // CHECK5-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
5673 // CHECK5-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
5674 // CHECK5-NEXT:    [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
5675 // CHECK5-NEXT:    [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
5676 // CHECK5-NEXT:    call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
5677 // CHECK5-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
5678 // CHECK5-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4
5679 // CHECK5-NEXT:    [[CMP9:%.*]] = icmp ugt i32 [[TMP11]], [[TMP12]]
5680 // CHECK5-NEXT:    br i1 [[CMP9]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
5681 // CHECK5:       cond.true:
5682 // CHECK5-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4
5683 // CHECK5-NEXT:    br label [[COND_END:%.*]]
5684 // CHECK5:       cond.false:
5685 // CHECK5-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
5686 // CHECK5-NEXT:    br label [[COND_END]]
5687 // CHECK5:       cond.end:
5688 // CHECK5-NEXT:    [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ]
5689 // CHECK5-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
5690 // CHECK5-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
5691 // CHECK5-NEXT:    store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4
5692 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
5693 // CHECK5:       omp.inner.for.cond:
5694 // CHECK5-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !44
5695 // CHECK5-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !44
5696 // CHECK5-NEXT:    [[ADD10:%.*]] = add i32 [[TMP17]], 1
5697 // CHECK5-NEXT:    [[CMP11:%.*]] = icmp ult i32 [[TMP16]], [[ADD10]]
5698 // CHECK5-NEXT:    br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
5699 // CHECK5:       omp.inner.for.body:
5700 // CHECK5-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group !44
5701 // CHECK5-NEXT:    [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !44
5702 // CHECK5-NEXT:    [[MUL:%.*]] = mul i32 [[TMP19]], 1
5703 // CHECK5-NEXT:    [[ADD12:%.*]] = add i32 [[TMP18]], [[MUL]]
5704 // CHECK5-NEXT:    store i32 [[ADD12]], i32* [[I8]], align 4, !llvm.access.group !44
5705 // CHECK5-NEXT:    [[TMP20:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !44
5706 // CHECK5-NEXT:    [[ADD13:%.*]] = add nsw i32 [[TMP20]], 1
5707 // CHECK5-NEXT:    store i32 [[ADD13]], i32* [[CONV]], align 4, !llvm.access.group !44
5708 // CHECK5-NEXT:    [[TMP21:%.*]] = load i16, i16* [[CONV2]], align 2, !llvm.access.group !44
5709 // CHECK5-NEXT:    [[CONV14:%.*]] = sext i16 [[TMP21]] to i32
5710 // CHECK5-NEXT:    [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1
5711 // CHECK5-NEXT:    [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16
5712 // CHECK5-NEXT:    store i16 [[CONV16]], i16* [[CONV2]], align 2, !llvm.access.group !44
5713 // CHECK5-NEXT:    [[TMP22:%.*]] = load i8, i8* [[CONV3]], align 1, !llvm.access.group !44
5714 // CHECK5-NEXT:    [[CONV17:%.*]] = sext i8 [[TMP22]] to i32
5715 // CHECK5-NEXT:    [[ADD18:%.*]] = add nsw i32 [[CONV17]], 1
5716 // CHECK5-NEXT:    [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8
5717 // CHECK5-NEXT:    store i8 [[CONV19]], i8* [[CONV3]], align 1, !llvm.access.group !44
5718 // CHECK5-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
5719 // CHECK5-NEXT:    [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !44
5720 // CHECK5-NEXT:    [[ADD20:%.*]] = add nsw i32 [[TMP23]], 1
5721 // CHECK5-NEXT:    store i32 [[ADD20]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !44
5722 // CHECK5-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
5723 // CHECK5:       omp.body.continue:
5724 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
5725 // CHECK5:       omp.inner.for.inc:
5726 // CHECK5-NEXT:    [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !44
5727 // CHECK5-NEXT:    [[ADD21:%.*]] = add i32 [[TMP24]], 1
5728 // CHECK5-NEXT:    store i32 [[ADD21]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !44
5729 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP45:![0-9]+]]
5730 // CHECK5:       omp.inner.for.end:
5731 // CHECK5-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
5732 // CHECK5:       omp.loop.exit:
5733 // CHECK5-NEXT:    [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
5734 // CHECK5-NEXT:    [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4
5735 // CHECK5-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]])
5736 // CHECK5-NEXT:    [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
5737 // CHECK5-NEXT:    [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0
5738 // CHECK5-NEXT:    br i1 [[TMP28]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
5739 // CHECK5:       .omp.final.then:
5740 // CHECK5-NEXT:    [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
5741 // CHECK5-NEXT:    [[TMP30:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4
5742 // CHECK5-NEXT:    [[TMP31:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
5743 // CHECK5-NEXT:    [[SUB22:%.*]] = sub i32 [[TMP30]], [[TMP31]]
5744 // CHECK5-NEXT:    [[SUB23:%.*]] = sub i32 [[SUB22]], 1
5745 // CHECK5-NEXT:    [[ADD24:%.*]] = add i32 [[SUB23]], 1
5746 // CHECK5-NEXT:    [[DIV25:%.*]] = udiv i32 [[ADD24]], 1
5747 // CHECK5-NEXT:    [[MUL26:%.*]] = mul i32 [[DIV25]], 1
5748 // CHECK5-NEXT:    [[ADD27:%.*]] = add i32 [[TMP29]], [[MUL26]]
5749 // CHECK5-NEXT:    store i32 [[ADD27]], i32* [[I8]], align 4
5750 // CHECK5-NEXT:    br label [[DOTOMP_FINAL_DONE]]
5751 // CHECK5:       .omp.final.done:
5752 // CHECK5-NEXT:    br label [[OMP_PRECOND_END]]
5753 // CHECK5:       omp.precond.end:
5754 // CHECK5-NEXT:    ret void
5755 //
5756 //
5757 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180
5758 // CHECK5-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
5759 // CHECK5-NEXT:  entry:
5760 // CHECK5-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
5761 // CHECK5-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
5762 // CHECK5-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
5763 // CHECK5-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
5764 // CHECK5-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
5765 // CHECK5-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
5766 // CHECK5-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
5767 // CHECK5-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
5768 // CHECK5-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
5769 // CHECK5-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
5770 // CHECK5-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
5771 // CHECK5-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
5772 // CHECK5-NEXT:    [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
5773 // CHECK5-NEXT:    store i32 [[TMP1]], i32* [[CONV2]], align 4
5774 // CHECK5-NEXT:    [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
5775 // CHECK5-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
5776 // CHECK5-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
5777 // CHECK5-NEXT:    store i16 [[TMP3]], i16* [[CONV3]], align 2
5778 // CHECK5-NEXT:    [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
5779 // CHECK5-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..18 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]])
5780 // CHECK5-NEXT:    ret void
5781 //
5782 //
5783 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..18
5784 // CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] {
5785 // CHECK5-NEXT:  entry:
5786 // CHECK5-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
5787 // CHECK5-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
5788 // CHECK5-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
5789 // CHECK5-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
5790 // CHECK5-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
5791 // CHECK5-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
5792 // CHECK5-NEXT:    [[TMP:%.*]] = alloca i32, align 4
5793 // CHECK5-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
5794 // CHECK5-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
5795 // CHECK5-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
5796 // CHECK5-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
5797 // CHECK5-NEXT:    [[I:%.*]] = alloca i32, align 4
5798 // CHECK5-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
5799 // CHECK5-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
5800 // CHECK5-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
5801 // CHECK5-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
5802 // CHECK5-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
5803 // CHECK5-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
5804 // CHECK5-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
5805 // CHECK5-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
5806 // CHECK5-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
5807 // CHECK5-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
5808 // CHECK5-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
5809 // CHECK5-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
5810 // CHECK5-NEXT:    [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
5811 // CHECK5-NEXT:    [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
5812 // CHECK5-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
5813 // CHECK5-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
5814 // CHECK5-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9
5815 // CHECK5-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
5816 // CHECK5:       cond.true:
5817 // CHECK5-NEXT:    br label [[COND_END:%.*]]
5818 // CHECK5:       cond.false:
5819 // CHECK5-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
5820 // CHECK5-NEXT:    br label [[COND_END]]
5821 // CHECK5:       cond.end:
5822 // CHECK5-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
5823 // CHECK5-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
5824 // CHECK5-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
5825 // CHECK5-NEXT:    store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
5826 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
5827 // CHECK5:       omp.inner.for.cond:
5828 // CHECK5-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !47
5829 // CHECK5-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !47
5830 // CHECK5-NEXT:    [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
5831 // CHECK5-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
5832 // CHECK5:       omp.inner.for.body:
5833 // CHECK5-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !47
5834 // CHECK5-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
5835 // CHECK5-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
5836 // CHECK5-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !47
5837 // CHECK5-NEXT:    [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !47
5838 // CHECK5-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1
5839 // CHECK5-NEXT:    store i32 [[ADD3]], i32* [[CONV]], align 4, !llvm.access.group !47
5840 // CHECK5-NEXT:    [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 2, !llvm.access.group !47
5841 // CHECK5-NEXT:    [[CONV4:%.*]] = sext i16 [[TMP10]] to i32
5842 // CHECK5-NEXT:    [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
5843 // CHECK5-NEXT:    [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
5844 // CHECK5-NEXT:    store i16 [[CONV6]], i16* [[CONV1]], align 2, !llvm.access.group !47
5845 // CHECK5-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
5846 // CHECK5-NEXT:    [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !47
5847 // CHECK5-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1
5848 // CHECK5-NEXT:    store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !47
5849 // CHECK5-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
5850 // CHECK5:       omp.body.continue:
5851 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
5852 // CHECK5:       omp.inner.for.inc:
5853 // CHECK5-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !47
5854 // CHECK5-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP12]], 1
5855 // CHECK5-NEXT:    store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !47
5856 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP48:![0-9]+]]
5857 // CHECK5:       omp.inner.for.end:
5858 // CHECK5-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
5859 // CHECK5:       omp.loop.exit:
5860 // CHECK5-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
5861 // CHECK5-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
5862 // CHECK5-NEXT:    [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
5863 // CHECK5-NEXT:    br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
5864 // CHECK5:       .omp.final.then:
5865 // CHECK5-NEXT:    store i32 10, i32* [[I]], align 4
5866 // CHECK5-NEXT:    br label [[DOTOMP_FINAL_DONE]]
5867 // CHECK5:       .omp.final.done:
5868 // CHECK5-NEXT:    ret void
5869 //
5870 //
5871 // CHECK5-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
5872 // CHECK5-SAME: () #[[ATTR5]] {
5873 // CHECK5-NEXT:  entry:
5874 // CHECK5-NEXT:    call void @__tgt_register_requires(i64 1)
5875 // CHECK5-NEXT:    ret void
5876 //
5877 //
5878 // CHECK7-LABEL: define {{[^@]+}}@_Z3fooi
5879 // CHECK7-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0:[0-9]+]] {
5880 // CHECK7-NEXT:  entry:
5881 // CHECK7-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
5882 // CHECK7-NEXT:    [[A:%.*]] = alloca i32, align 4
5883 // CHECK7-NEXT:    [[AA:%.*]] = alloca i16, align 2
5884 // CHECK7-NEXT:    [[B:%.*]] = alloca [10 x float], align 4
5885 // CHECK7-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 4
5886 // CHECK7-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 4
5887 // CHECK7-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 8
5888 // CHECK7-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i32, align 4
5889 // CHECK7-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4
5890 // CHECK7-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
5891 // CHECK7-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
5892 // CHECK7-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
5893 // CHECK7-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
5894 // CHECK7-NEXT:    [[DOTCAPTURE_EXPR__CASTED3:%.*]] = alloca i32, align 4
5895 // CHECK7-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4
5896 // CHECK7-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4
5897 // CHECK7-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4
5898 // CHECK7-NEXT:    [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4
5899 // CHECK7-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
5900 // CHECK7-NEXT:    [[AA_CASTED4:%.*]] = alloca i32, align 4
5901 // CHECK7-NEXT:    [[DOTOFFLOAD_BASEPTRS6:%.*]] = alloca [1 x i8*], align 4
5902 // CHECK7-NEXT:    [[DOTOFFLOAD_PTRS7:%.*]] = alloca [1 x i8*], align 4
5903 // CHECK7-NEXT:    [[DOTOFFLOAD_MAPPERS8:%.*]] = alloca [1 x i8*], align 4
5904 // CHECK7-NEXT:    [[TMP:%.*]] = alloca i32, align 4
5905 // CHECK7-NEXT:    [[A_CASTED9:%.*]] = alloca i32, align 4
5906 // CHECK7-NEXT:    [[AA_CASTED10:%.*]] = alloca i32, align 4
5907 // CHECK7-NEXT:    [[DOTOFFLOAD_BASEPTRS12:%.*]] = alloca [2 x i8*], align 4
5908 // CHECK7-NEXT:    [[DOTOFFLOAD_PTRS13:%.*]] = alloca [2 x i8*], align 4
5909 // CHECK7-NEXT:    [[DOTOFFLOAD_MAPPERS14:%.*]] = alloca [2 x i8*], align 4
5910 // CHECK7-NEXT:    [[_TMP15:%.*]] = alloca i32, align 4
5911 // CHECK7-NEXT:    [[A_CASTED19:%.*]] = alloca i32, align 4
5912 // CHECK7-NEXT:    [[DOTOFFLOAD_BASEPTRS22:%.*]] = alloca [9 x i8*], align 4
5913 // CHECK7-NEXT:    [[DOTOFFLOAD_PTRS23:%.*]] = alloca [9 x i8*], align 4
5914 // CHECK7-NEXT:    [[DOTOFFLOAD_MAPPERS24:%.*]] = alloca [9 x i8*], align 4
5915 // CHECK7-NEXT:    [[DOTOFFLOAD_SIZES:%.*]] = alloca [9 x i64], align 4
5916 // CHECK7-NEXT:    [[_TMP25:%.*]] = alloca i32, align 4
5917 // CHECK7-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]])
5918 // CHECK7-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
5919 // CHECK7-NEXT:    store i32 0, i32* [[A]], align 4
5920 // CHECK7-NEXT:    store i16 0, i16* [[AA]], align 2
5921 // CHECK7-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
5922 // CHECK7-NEXT:    [[TMP2:%.*]] = call i8* @llvm.stacksave()
5923 // CHECK7-NEXT:    store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4
5924 // CHECK7-NEXT:    [[VLA:%.*]] = alloca float, i32 [[TMP1]], align 4
5925 // CHECK7-NEXT:    store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
5926 // CHECK7-NEXT:    [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
5927 // CHECK7-NEXT:    [[TMP4:%.*]] = mul nuw i32 5, [[TMP3]]
5928 // CHECK7-NEXT:    [[VLA1:%.*]] = alloca double, i32 [[TMP4]], align 8
5929 // CHECK7-NEXT:    store i32 [[TMP3]], i32* [[__VLA_EXPR1]], align 4
5930 // CHECK7-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
5931 // CHECK7-NEXT:    store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_]], align 4
5932 // CHECK7-NEXT:    [[TMP6:%.*]] = load i32, i32* [[A]], align 4
5933 // CHECK7-NEXT:    store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_2]], align 4
5934 // CHECK7-NEXT:    [[TMP7:%.*]] = load i16, i16* [[AA]], align 2
5935 // CHECK7-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
5936 // CHECK7-NEXT:    store i16 [[TMP7]], i16* [[CONV]], align 2
5937 // CHECK7-NEXT:    [[TMP8:%.*]] = load i32, i32* [[AA_CASTED]], align 4
5938 // CHECK7-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
5939 // CHECK7-NEXT:    store i32 [[TMP9]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
5940 // CHECK7-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
5941 // CHECK7-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
5942 // CHECK7-NEXT:    store i32 [[TMP11]], i32* [[DOTCAPTURE_EXPR__CASTED3]], align 4
5943 // CHECK7-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED3]], align 4
5944 // CHECK7-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
5945 // CHECK7-NEXT:    [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i32*
5946 // CHECK7-NEXT:    store i32 [[TMP8]], i32* [[TMP14]], align 4
5947 // CHECK7-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
5948 // CHECK7-NEXT:    [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i32*
5949 // CHECK7-NEXT:    store i32 [[TMP8]], i32* [[TMP16]], align 4
5950 // CHECK7-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
5951 // CHECK7-NEXT:    store i8* null, i8** [[TMP17]], align 4
5952 // CHECK7-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
5953 // CHECK7-NEXT:    [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32*
5954 // CHECK7-NEXT:    store i32 [[TMP10]], i32* [[TMP19]], align 4
5955 // CHECK7-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
5956 // CHECK7-NEXT:    [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32*
5957 // CHECK7-NEXT:    store i32 [[TMP10]], i32* [[TMP21]], align 4
5958 // CHECK7-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
5959 // CHECK7-NEXT:    store i8* null, i8** [[TMP22]], align 4
5960 // CHECK7-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
5961 // CHECK7-NEXT:    [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i32*
5962 // CHECK7-NEXT:    store i32 [[TMP12]], i32* [[TMP24]], align 4
5963 // CHECK7-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
5964 // CHECK7-NEXT:    [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i32*
5965 // CHECK7-NEXT:    store i32 [[TMP12]], i32* [[TMP26]], align 4
5966 // CHECK7-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
5967 // CHECK7-NEXT:    store i8* null, i8** [[TMP27]], align 4
5968 // CHECK7-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
5969 // CHECK7-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
5970 // CHECK7-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 0
5971 // CHECK7-NEXT:    [[TMP31:%.*]] = load i16, i16* [[AA]], align 2
5972 // CHECK7-NEXT:    store i16 [[TMP31]], i16* [[TMP30]], align 4
5973 // CHECK7-NEXT:    [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 1
5974 // CHECK7-NEXT:    [[TMP33:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
5975 // CHECK7-NEXT:    store i32 [[TMP33]], i32* [[TMP32]], align 4
5976 // CHECK7-NEXT:    [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 2
5977 // CHECK7-NEXT:    [[TMP35:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
5978 // CHECK7-NEXT:    store i32 [[TMP35]], i32* [[TMP34]], align 4
5979 // CHECK7-NEXT:    [[TMP36:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 1, i32 72, i32 12, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1)
5980 // CHECK7-NEXT:    [[TMP37:%.*]] = bitcast i8* [[TMP36]] to %struct.kmp_task_t_with_privates*
5981 // CHECK7-NEXT:    [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP37]], i32 0, i32 0
5982 // CHECK7-NEXT:    [[TMP39:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP38]], i32 0, i32 0
5983 // CHECK7-NEXT:    [[TMP40:%.*]] = load i8*, i8** [[TMP39]], align 4
5984 // CHECK7-NEXT:    [[TMP41:%.*]] = bitcast %struct.anon* [[AGG_CAPTURED]] to i8*
5985 // CHECK7-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP40]], i8* align 4 [[TMP41]], i32 12, i1 false)
5986 // CHECK7-NEXT:    [[TMP42:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP37]], i32 0, i32 1
5987 // CHECK7-NEXT:    [[TMP43:%.*]] = bitcast i8* [[TMP40]] to %struct.anon*
5988 // CHECK7-NEXT:    [[TMP44:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 0
5989 // CHECK7-NEXT:    [[TMP45:%.*]] = bitcast [3 x i64]* [[TMP44]] to i8*
5990 // CHECK7-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP45]], i8* align 4 bitcast ([3 x i64]* @.offload_sizes to i8*), i32 24, i1 false)
5991 // CHECK7-NEXT:    [[TMP46:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 1
5992 // CHECK7-NEXT:    [[TMP47:%.*]] = bitcast [3 x i8*]* [[TMP46]] to i8*
5993 // CHECK7-NEXT:    [[TMP48:%.*]] = bitcast i8** [[TMP28]] to i8*
5994 // CHECK7-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP47]], i8* align 4 [[TMP48]], i32 12, i1 false)
5995 // CHECK7-NEXT:    [[TMP49:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 2
5996 // CHECK7-NEXT:    [[TMP50:%.*]] = bitcast [3 x i8*]* [[TMP49]] to i8*
5997 // CHECK7-NEXT:    [[TMP51:%.*]] = bitcast i8** [[TMP29]] to i8*
5998 // CHECK7-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP50]], i8* align 4 [[TMP51]], i32 12, i1 false)
5999 // CHECK7-NEXT:    [[TMP52:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 3
6000 // CHECK7-NEXT:    [[TMP53:%.*]] = load i16, i16* [[AA]], align 2
6001 // CHECK7-NEXT:    store i16 [[TMP53]], i16* [[TMP52]], align 4
6002 // CHECK7-NEXT:    [[TMP54:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i8* [[TMP36]])
6003 // CHECK7-NEXT:    [[TMP55:%.*]] = load i32, i32* [[A]], align 4
6004 // CHECK7-NEXT:    store i32 [[TMP55]], i32* [[A_CASTED]], align 4
6005 // CHECK7-NEXT:    [[TMP56:%.*]] = load i32, i32* [[A_CASTED]], align 4
6006 // CHECK7-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l102(i32 [[TMP56]]) #[[ATTR4:[0-9]+]]
6007 // CHECK7-NEXT:    [[TMP57:%.*]] = load i16, i16* [[AA]], align 2
6008 // CHECK7-NEXT:    [[CONV5:%.*]] = bitcast i32* [[AA_CASTED4]] to i16*
6009 // CHECK7-NEXT:    store i16 [[TMP57]], i16* [[CONV5]], align 2
6010 // CHECK7-NEXT:    [[TMP58:%.*]] = load i32, i32* [[AA_CASTED4]], align 4
6011 // CHECK7-NEXT:    [[TMP59:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0
6012 // CHECK7-NEXT:    [[TMP60:%.*]] = bitcast i8** [[TMP59]] to i32*
6013 // CHECK7-NEXT:    store i32 [[TMP58]], i32* [[TMP60]], align 4
6014 // CHECK7-NEXT:    [[TMP61:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0
6015 // CHECK7-NEXT:    [[TMP62:%.*]] = bitcast i8** [[TMP61]] to i32*
6016 // CHECK7-NEXT:    store i32 [[TMP58]], i32* [[TMP62]], align 4
6017 // CHECK7-NEXT:    [[TMP63:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS8]], i32 0, i32 0
6018 // CHECK7-NEXT:    store i8* null, i8** [[TMP63]], align 4
6019 // CHECK7-NEXT:    [[TMP64:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0
6020 // CHECK7-NEXT:    [[TMP65:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0
6021 // CHECK7-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
6022 // CHECK7-NEXT:    [[TMP66:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
6023 // CHECK7-NEXT:    store i32 1, i32* [[TMP66]], align 4
6024 // CHECK7-NEXT:    [[TMP67:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
6025 // CHECK7-NEXT:    store i32 1, i32* [[TMP67]], align 4
6026 // CHECK7-NEXT:    [[TMP68:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
6027 // CHECK7-NEXT:    store i8** [[TMP64]], i8*** [[TMP68]], align 4
6028 // CHECK7-NEXT:    [[TMP69:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
6029 // CHECK7-NEXT:    store i8** [[TMP65]], i8*** [[TMP69]], align 4
6030 // CHECK7-NEXT:    [[TMP70:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
6031 // CHECK7-NEXT:    store i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.4, i32 0, i32 0), i64** [[TMP70]], align 4
6032 // CHECK7-NEXT:    [[TMP71:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
6033 // CHECK7-NEXT:    store i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.5, i32 0, i32 0), i64** [[TMP71]], align 4
6034 // CHECK7-NEXT:    [[TMP72:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
6035 // CHECK7-NEXT:    store i8** null, i8*** [[TMP72]], align 4
6036 // CHECK7-NEXT:    [[TMP73:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
6037 // CHECK7-NEXT:    store i8** null, i8*** [[TMP73]], align 4
6038 // CHECK7-NEXT:    [[TMP74:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
6039 // CHECK7-NEXT:    store i64 10, i64* [[TMP74]], align 8
6040 // CHECK7-NEXT:    [[TMP75:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB2]], i64 -1, i32 0, i32 1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
6041 // CHECK7-NEXT:    [[TMP76:%.*]] = icmp ne i32 [[TMP75]], 0
6042 // CHECK7-NEXT:    br i1 [[TMP76]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
6043 // CHECK7:       omp_offload.failed:
6044 // CHECK7-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111(i32 [[TMP58]]) #[[ATTR4]]
6045 // CHECK7-NEXT:    br label [[OMP_OFFLOAD_CONT]]
6046 // CHECK7:       omp_offload.cont:
6047 // CHECK7-NEXT:    [[TMP77:%.*]] = load i32, i32* [[A]], align 4
6048 // CHECK7-NEXT:    store i32 [[TMP77]], i32* [[A_CASTED9]], align 4
6049 // CHECK7-NEXT:    [[TMP78:%.*]] = load i32, i32* [[A_CASTED9]], align 4
6050 // CHECK7-NEXT:    [[TMP79:%.*]] = load i16, i16* [[AA]], align 2
6051 // CHECK7-NEXT:    [[CONV11:%.*]] = bitcast i32* [[AA_CASTED10]] to i16*
6052 // CHECK7-NEXT:    store i16 [[TMP79]], i16* [[CONV11]], align 2
6053 // CHECK7-NEXT:    [[TMP80:%.*]] = load i32, i32* [[AA_CASTED10]], align 4
6054 // CHECK7-NEXT:    [[TMP81:%.*]] = load i32, i32* [[N_ADDR]], align 4
6055 // CHECK7-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP81]], 10
6056 // CHECK7-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
6057 // CHECK7:       omp_if.then:
6058 // CHECK7-NEXT:    [[TMP82:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS12]], i32 0, i32 0
6059 // CHECK7-NEXT:    [[TMP83:%.*]] = bitcast i8** [[TMP82]] to i32*
6060 // CHECK7-NEXT:    store i32 [[TMP78]], i32* [[TMP83]], align 4
6061 // CHECK7-NEXT:    [[TMP84:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS13]], i32 0, i32 0
6062 // CHECK7-NEXT:    [[TMP85:%.*]] = bitcast i8** [[TMP84]] to i32*
6063 // CHECK7-NEXT:    store i32 [[TMP78]], i32* [[TMP85]], align 4
6064 // CHECK7-NEXT:    [[TMP86:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS14]], i32 0, i32 0
6065 // CHECK7-NEXT:    store i8* null, i8** [[TMP86]], align 4
6066 // CHECK7-NEXT:    [[TMP87:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS12]], i32 0, i32 1
6067 // CHECK7-NEXT:    [[TMP88:%.*]] = bitcast i8** [[TMP87]] to i32*
6068 // CHECK7-NEXT:    store i32 [[TMP80]], i32* [[TMP88]], align 4
6069 // CHECK7-NEXT:    [[TMP89:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS13]], i32 0, i32 1
6070 // CHECK7-NEXT:    [[TMP90:%.*]] = bitcast i8** [[TMP89]] to i32*
6071 // CHECK7-NEXT:    store i32 [[TMP80]], i32* [[TMP90]], align 4
6072 // CHECK7-NEXT:    [[TMP91:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS14]], i32 0, i32 1
6073 // CHECK7-NEXT:    store i8* null, i8** [[TMP91]], align 4
6074 // CHECK7-NEXT:    [[TMP92:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS12]], i32 0, i32 0
6075 // CHECK7-NEXT:    [[TMP93:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS13]], i32 0, i32 0
6076 // CHECK7-NEXT:    [[KERNEL_ARGS16:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
6077 // CHECK7-NEXT:    [[TMP94:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS16]], i32 0, i32 0
6078 // CHECK7-NEXT:    store i32 1, i32* [[TMP94]], align 4
6079 // CHECK7-NEXT:    [[TMP95:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS16]], i32 0, i32 1
6080 // CHECK7-NEXT:    store i32 2, i32* [[TMP95]], align 4
6081 // CHECK7-NEXT:    [[TMP96:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS16]], i32 0, i32 2
6082 // CHECK7-NEXT:    store i8** [[TMP92]], i8*** [[TMP96]], align 4
6083 // CHECK7-NEXT:    [[TMP97:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS16]], i32 0, i32 3
6084 // CHECK7-NEXT:    store i8** [[TMP93]], i8*** [[TMP97]], align 4
6085 // CHECK7-NEXT:    [[TMP98:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS16]], i32 0, i32 4
6086 // CHECK7-NEXT:    store i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.7, i32 0, i32 0), i64** [[TMP98]], align 4
6087 // CHECK7-NEXT:    [[TMP99:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS16]], i32 0, i32 5
6088 // CHECK7-NEXT:    store i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.8, i32 0, i32 0), i64** [[TMP99]], align 4
6089 // CHECK7-NEXT:    [[TMP100:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS16]], i32 0, i32 6
6090 // CHECK7-NEXT:    store i8** null, i8*** [[TMP100]], align 4
6091 // CHECK7-NEXT:    [[TMP101:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS16]], i32 0, i32 7
6092 // CHECK7-NEXT:    store i8** null, i8*** [[TMP101]], align 4
6093 // CHECK7-NEXT:    [[TMP102:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS16]], i32 0, i32 8
6094 // CHECK7-NEXT:    store i64 10, i64* [[TMP102]], align 8
6095 // CHECK7-NEXT:    [[TMP103:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB2]], i64 -1, i32 0, i32 1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS16]])
6096 // CHECK7-NEXT:    [[TMP104:%.*]] = icmp ne i32 [[TMP103]], 0
6097 // CHECK7-NEXT:    br i1 [[TMP104]], label [[OMP_OFFLOAD_FAILED17:%.*]], label [[OMP_OFFLOAD_CONT18:%.*]]
6098 // CHECK7:       omp_offload.failed17:
6099 // CHECK7-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i32 [[TMP78]], i32 [[TMP80]]) #[[ATTR4]]
6100 // CHECK7-NEXT:    br label [[OMP_OFFLOAD_CONT18]]
6101 // CHECK7:       omp_offload.cont18:
6102 // CHECK7-NEXT:    br label [[OMP_IF_END:%.*]]
6103 // CHECK7:       omp_if.else:
6104 // CHECK7-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i32 [[TMP78]], i32 [[TMP80]]) #[[ATTR4]]
6105 // CHECK7-NEXT:    br label [[OMP_IF_END]]
6106 // CHECK7:       omp_if.end:
6107 // CHECK7-NEXT:    [[TMP105:%.*]] = load i32, i32* [[A]], align 4
6108 // CHECK7-NEXT:    store i32 [[TMP105]], i32* [[A_CASTED19]], align 4
6109 // CHECK7-NEXT:    [[TMP106:%.*]] = load i32, i32* [[A_CASTED19]], align 4
6110 // CHECK7-NEXT:    [[TMP107:%.*]] = load i32, i32* [[N_ADDR]], align 4
6111 // CHECK7-NEXT:    [[CMP20:%.*]] = icmp sgt i32 [[TMP107]], 20
6112 // CHECK7-NEXT:    br i1 [[CMP20]], label [[OMP_IF_THEN21:%.*]], label [[OMP_IF_ELSE29:%.*]]
6113 // CHECK7:       omp_if.then21:
6114 // CHECK7-NEXT:    [[TMP108:%.*]] = mul nuw i32 [[TMP1]], 4
6115 // CHECK7-NEXT:    [[TMP109:%.*]] = sext i32 [[TMP108]] to i64
6116 // CHECK7-NEXT:    [[TMP110:%.*]] = mul nuw i32 5, [[TMP3]]
6117 // CHECK7-NEXT:    [[TMP111:%.*]] = mul nuw i32 [[TMP110]], 8
6118 // CHECK7-NEXT:    [[TMP112:%.*]] = sext i32 [[TMP111]] to i64
6119 // CHECK7-NEXT:    [[TMP113:%.*]] = bitcast [9 x i64]* [[DOTOFFLOAD_SIZES]] to i8*
6120 // CHECK7-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP113]], i8* align 4 bitcast ([9 x i64]* @.offload_sizes.10 to i8*), i32 72, i1 false)
6121 // CHECK7-NEXT:    [[TMP114:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 0
6122 // CHECK7-NEXT:    [[TMP115:%.*]] = bitcast i8** [[TMP114]] to i32*
6123 // CHECK7-NEXT:    store i32 [[TMP106]], i32* [[TMP115]], align 4
6124 // CHECK7-NEXT:    [[TMP116:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS23]], i32 0, i32 0
6125 // CHECK7-NEXT:    [[TMP117:%.*]] = bitcast i8** [[TMP116]] to i32*
6126 // CHECK7-NEXT:    store i32 [[TMP106]], i32* [[TMP117]], align 4
6127 // CHECK7-NEXT:    [[TMP118:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS24]], i32 0, i32 0
6128 // CHECK7-NEXT:    store i8* null, i8** [[TMP118]], align 4
6129 // CHECK7-NEXT:    [[TMP119:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 1
6130 // CHECK7-NEXT:    [[TMP120:%.*]] = bitcast i8** [[TMP119]] to [10 x float]**
6131 // CHECK7-NEXT:    store [10 x float]* [[B]], [10 x float]** [[TMP120]], align 4
6132 // CHECK7-NEXT:    [[TMP121:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS23]], i32 0, i32 1
6133 // CHECK7-NEXT:    [[TMP122:%.*]] = bitcast i8** [[TMP121]] to [10 x float]**
6134 // CHECK7-NEXT:    store [10 x float]* [[B]], [10 x float]** [[TMP122]], align 4
6135 // CHECK7-NEXT:    [[TMP123:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS24]], i32 0, i32 1
6136 // CHECK7-NEXT:    store i8* null, i8** [[TMP123]], align 4
6137 // CHECK7-NEXT:    [[TMP124:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 2
6138 // CHECK7-NEXT:    [[TMP125:%.*]] = bitcast i8** [[TMP124]] to i32*
6139 // CHECK7-NEXT:    store i32 [[TMP1]], i32* [[TMP125]], align 4
6140 // CHECK7-NEXT:    [[TMP126:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS23]], i32 0, i32 2
6141 // CHECK7-NEXT:    [[TMP127:%.*]] = bitcast i8** [[TMP126]] to i32*
6142 // CHECK7-NEXT:    store i32 [[TMP1]], i32* [[TMP127]], align 4
6143 // CHECK7-NEXT:    [[TMP128:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS24]], i32 0, i32 2
6144 // CHECK7-NEXT:    store i8* null, i8** [[TMP128]], align 4
6145 // CHECK7-NEXT:    [[TMP129:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 3
6146 // CHECK7-NEXT:    [[TMP130:%.*]] = bitcast i8** [[TMP129]] to float**
6147 // CHECK7-NEXT:    store float* [[VLA]], float** [[TMP130]], align 4
6148 // CHECK7-NEXT:    [[TMP131:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS23]], i32 0, i32 3
6149 // CHECK7-NEXT:    [[TMP132:%.*]] = bitcast i8** [[TMP131]] to float**
6150 // CHECK7-NEXT:    store float* [[VLA]], float** [[TMP132]], align 4
6151 // CHECK7-NEXT:    [[TMP133:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3
6152 // CHECK7-NEXT:    store i64 [[TMP109]], i64* [[TMP133]], align 4
6153 // CHECK7-NEXT:    [[TMP134:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS24]], i32 0, i32 3
6154 // CHECK7-NEXT:    store i8* null, i8** [[TMP134]], align 4
6155 // CHECK7-NEXT:    [[TMP135:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 4
6156 // CHECK7-NEXT:    [[TMP136:%.*]] = bitcast i8** [[TMP135]] to [5 x [10 x double]]**
6157 // CHECK7-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP136]], align 4
6158 // CHECK7-NEXT:    [[TMP137:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS23]], i32 0, i32 4
6159 // CHECK7-NEXT:    [[TMP138:%.*]] = bitcast i8** [[TMP137]] to [5 x [10 x double]]**
6160 // CHECK7-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP138]], align 4
6161 // CHECK7-NEXT:    [[TMP139:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS24]], i32 0, i32 4
6162 // CHECK7-NEXT:    store i8* null, i8** [[TMP139]], align 4
6163 // CHECK7-NEXT:    [[TMP140:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 5
6164 // CHECK7-NEXT:    [[TMP141:%.*]] = bitcast i8** [[TMP140]] to i32*
6165 // CHECK7-NEXT:    store i32 5, i32* [[TMP141]], align 4
6166 // CHECK7-NEXT:    [[TMP142:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS23]], i32 0, i32 5
6167 // CHECK7-NEXT:    [[TMP143:%.*]] = bitcast i8** [[TMP142]] to i32*
6168 // CHECK7-NEXT:    store i32 5, i32* [[TMP143]], align 4
6169 // CHECK7-NEXT:    [[TMP144:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS24]], i32 0, i32 5
6170 // CHECK7-NEXT:    store i8* null, i8** [[TMP144]], align 4
6171 // CHECK7-NEXT:    [[TMP145:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 6
6172 // CHECK7-NEXT:    [[TMP146:%.*]] = bitcast i8** [[TMP145]] to i32*
6173 // CHECK7-NEXT:    store i32 [[TMP3]], i32* [[TMP146]], align 4
6174 // CHECK7-NEXT:    [[TMP147:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS23]], i32 0, i32 6
6175 // CHECK7-NEXT:    [[TMP148:%.*]] = bitcast i8** [[TMP147]] to i32*
6176 // CHECK7-NEXT:    store i32 [[TMP3]], i32* [[TMP148]], align 4
6177 // CHECK7-NEXT:    [[TMP149:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS24]], i32 0, i32 6
6178 // CHECK7-NEXT:    store i8* null, i8** [[TMP149]], align 4
6179 // CHECK7-NEXT:    [[TMP150:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 7
6180 // CHECK7-NEXT:    [[TMP151:%.*]] = bitcast i8** [[TMP150]] to double**
6181 // CHECK7-NEXT:    store double* [[VLA1]], double** [[TMP151]], align 4
6182 // CHECK7-NEXT:    [[TMP152:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS23]], i32 0, i32 7
6183 // CHECK7-NEXT:    [[TMP153:%.*]] = bitcast i8** [[TMP152]] to double**
6184 // CHECK7-NEXT:    store double* [[VLA1]], double** [[TMP153]], align 4
6185 // CHECK7-NEXT:    [[TMP154:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7
6186 // CHECK7-NEXT:    store i64 [[TMP112]], i64* [[TMP154]], align 4
6187 // CHECK7-NEXT:    [[TMP155:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS24]], i32 0, i32 7
6188 // CHECK7-NEXT:    store i8* null, i8** [[TMP155]], align 4
6189 // CHECK7-NEXT:    [[TMP156:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 8
6190 // CHECK7-NEXT:    [[TMP157:%.*]] = bitcast i8** [[TMP156]] to %struct.TT**
6191 // CHECK7-NEXT:    store %struct.TT* [[D]], %struct.TT** [[TMP157]], align 4
6192 // CHECK7-NEXT:    [[TMP158:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS23]], i32 0, i32 8
6193 // CHECK7-NEXT:    [[TMP159:%.*]] = bitcast i8** [[TMP158]] to %struct.TT**
6194 // CHECK7-NEXT:    store %struct.TT* [[D]], %struct.TT** [[TMP159]], align 4
6195 // CHECK7-NEXT:    [[TMP160:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS24]], i32 0, i32 8
6196 // CHECK7-NEXT:    store i8* null, i8** [[TMP160]], align 4
6197 // CHECK7-NEXT:    [[TMP161:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 0
6198 // CHECK7-NEXT:    [[TMP162:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS23]], i32 0, i32 0
6199 // CHECK7-NEXT:    [[TMP163:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
6200 // CHECK7-NEXT:    [[KERNEL_ARGS26:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
6201 // CHECK7-NEXT:    [[TMP164:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS26]], i32 0, i32 0
6202 // CHECK7-NEXT:    store i32 1, i32* [[TMP164]], align 4
6203 // CHECK7-NEXT:    [[TMP165:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS26]], i32 0, i32 1
6204 // CHECK7-NEXT:    store i32 9, i32* [[TMP165]], align 4
6205 // CHECK7-NEXT:    [[TMP166:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS26]], i32 0, i32 2
6206 // CHECK7-NEXT:    store i8** [[TMP161]], i8*** [[TMP166]], align 4
6207 // CHECK7-NEXT:    [[TMP167:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS26]], i32 0, i32 3
6208 // CHECK7-NEXT:    store i8** [[TMP162]], i8*** [[TMP167]], align 4
6209 // CHECK7-NEXT:    [[TMP168:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS26]], i32 0, i32 4
6210 // CHECK7-NEXT:    store i64* [[TMP163]], i64** [[TMP168]], align 4
6211 // CHECK7-NEXT:    [[TMP169:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS26]], i32 0, i32 5
6212 // CHECK7-NEXT:    store i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_maptypes.11, i32 0, i32 0), i64** [[TMP169]], align 4
6213 // CHECK7-NEXT:    [[TMP170:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS26]], i32 0, i32 6
6214 // CHECK7-NEXT:    store i8** null, i8*** [[TMP170]], align 4
6215 // CHECK7-NEXT:    [[TMP171:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS26]], i32 0, i32 7
6216 // CHECK7-NEXT:    store i8** null, i8*** [[TMP171]], align 4
6217 // CHECK7-NEXT:    [[TMP172:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS26]], i32 0, i32 8
6218 // CHECK7-NEXT:    store i64 10, i64* [[TMP172]], align 8
6219 // CHECK7-NEXT:    [[TMP173:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB2]], i64 -1, i32 0, i32 1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS26]])
6220 // CHECK7-NEXT:    [[TMP174:%.*]] = icmp ne i32 [[TMP173]], 0
6221 // CHECK7-NEXT:    br i1 [[TMP174]], label [[OMP_OFFLOAD_FAILED27:%.*]], label [[OMP_OFFLOAD_CONT28:%.*]]
6222 // CHECK7:       omp_offload.failed27:
6223 // CHECK7-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i32 [[TMP106]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR4]]
6224 // CHECK7-NEXT:    br label [[OMP_OFFLOAD_CONT28]]
6225 // CHECK7:       omp_offload.cont28:
6226 // CHECK7-NEXT:    br label [[OMP_IF_END30:%.*]]
6227 // CHECK7:       omp_if.else29:
6228 // CHECK7-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i32 [[TMP106]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR4]]
6229 // CHECK7-NEXT:    br label [[OMP_IF_END30]]
6230 // CHECK7:       omp_if.end30:
6231 // CHECK7-NEXT:    [[TMP175:%.*]] = load i32, i32* [[A]], align 4
6232 // CHECK7-NEXT:    [[TMP176:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
6233 // CHECK7-NEXT:    call void @llvm.stackrestore(i8* [[TMP176]])
6234 // CHECK7-NEXT:    ret i32 [[TMP175]]
6235 //
6236 //
6237 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97
6238 // CHECK7-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]], i32 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] {
6239 // CHECK7-NEXT:  entry:
6240 // CHECK7-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
6241 // CHECK7-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
6242 // CHECK7-NEXT:    [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4
6243 // CHECK7-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
6244 // CHECK7-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]])
6245 // CHECK7-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
6246 // CHECK7-NEXT:    store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
6247 // CHECK7-NEXT:    store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4
6248 // CHECK7-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
6249 // CHECK7-NEXT:    [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
6250 // CHECK7-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4
6251 // CHECK7-NEXT:    call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
6252 // CHECK7-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
6253 // CHECK7-NEXT:    [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
6254 // CHECK7-NEXT:    store i16 [[TMP3]], i16* [[CONV3]], align 2
6255 // CHECK7-NEXT:    [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
6256 // CHECK7-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]])
6257 // CHECK7-NEXT:    ret void
6258 //
6259 //
6260 // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined.
6261 // CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR3:[0-9]+]] {
6262 // CHECK7-NEXT:  entry:
6263 // CHECK7-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
6264 // CHECK7-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
6265 // CHECK7-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
6266 // CHECK7-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
6267 // CHECK7-NEXT:    [[TMP:%.*]] = alloca i32, align 4
6268 // CHECK7-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
6269 // CHECK7-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
6270 // CHECK7-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
6271 // CHECK7-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
6272 // CHECK7-NEXT:    [[I:%.*]] = alloca i32, align 4
6273 // CHECK7-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
6274 // CHECK7-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
6275 // CHECK7-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
6276 // CHECK7-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
6277 // CHECK7-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
6278 // CHECK7-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
6279 // CHECK7-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
6280 // CHECK7-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
6281 // CHECK7-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
6282 // CHECK7-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
6283 // CHECK7-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
6284 // CHECK7-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
6285 // CHECK7-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
6286 // CHECK7-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
6287 // CHECK7:       cond.true:
6288 // CHECK7-NEXT:    br label [[COND_END:%.*]]
6289 // CHECK7:       cond.false:
6290 // CHECK7-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
6291 // CHECK7-NEXT:    br label [[COND_END]]
6292 // CHECK7:       cond.end:
6293 // CHECK7-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
6294 // CHECK7-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
6295 // CHECK7-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
6296 // CHECK7-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
6297 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
6298 // CHECK7:       omp.inner.for.cond:
6299 // CHECK7-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
6300 // CHECK7-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !11
6301 // CHECK7-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
6302 // CHECK7-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
6303 // CHECK7:       omp.inner.for.body:
6304 // CHECK7-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
6305 // CHECK7-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
6306 // CHECK7-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
6307 // CHECK7-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11
6308 // CHECK7-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
6309 // CHECK7:       omp.body.continue:
6310 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
6311 // CHECK7:       omp.inner.for.inc:
6312 // CHECK7-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
6313 // CHECK7-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
6314 // CHECK7-NEXT:    store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
6315 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]
6316 // CHECK7:       omp.inner.for.end:
6317 // CHECK7-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
6318 // CHECK7:       omp.loop.exit:
6319 // CHECK7-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
6320 // CHECK7-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
6321 // CHECK7-NEXT:    [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0
6322 // CHECK7-NEXT:    br i1 [[TMP10]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
6323 // CHECK7:       .omp.final.then:
6324 // CHECK7-NEXT:    store i32 10, i32* [[I]], align 4
6325 // CHECK7-NEXT:    br label [[DOTOMP_FINAL_DONE]]
6326 // CHECK7:       .omp.final.done:
6327 // CHECK7-NEXT:    ret void
6328 //
6329 //
6330 // CHECK7-LABEL: define {{[^@]+}}@.omp_task_privates_map.
6331 // CHECK7-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], i16** noalias noundef [[TMP1:%.*]], [3 x i8*]** noalias noundef [[TMP2:%.*]], [3 x i8*]** noalias noundef [[TMP3:%.*]], [3 x i64]** noalias noundef [[TMP4:%.*]]) #[[ATTR5:[0-9]+]] {
6332 // CHECK7-NEXT:  entry:
6333 // CHECK7-NEXT:    [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 4
6334 // CHECK7-NEXT:    [[DOTADDR1:%.*]] = alloca i16**, align 4
6335 // CHECK7-NEXT:    [[DOTADDR2:%.*]] = alloca [3 x i8*]**, align 4
6336 // CHECK7-NEXT:    [[DOTADDR3:%.*]] = alloca [3 x i8*]**, align 4
6337 // CHECK7-NEXT:    [[DOTADDR4:%.*]] = alloca [3 x i64]**, align 4
6338 // CHECK7-NEXT:    store %struct..kmp_privates.t* [[TMP0]], %struct..kmp_privates.t** [[DOTADDR]], align 4
6339 // CHECK7-NEXT:    store i16** [[TMP1]], i16*** [[DOTADDR1]], align 4
6340 // CHECK7-NEXT:    store [3 x i8*]** [[TMP2]], [3 x i8*]*** [[DOTADDR2]], align 4
6341 // CHECK7-NEXT:    store [3 x i8*]** [[TMP3]], [3 x i8*]*** [[DOTADDR3]], align 4
6342 // CHECK7-NEXT:    store [3 x i64]** [[TMP4]], [3 x i64]*** [[DOTADDR4]], align 4
6343 // CHECK7-NEXT:    [[TMP5:%.*]] = load %struct..kmp_privates.t*, %struct..kmp_privates.t** [[DOTADDR]], align 4
6344 // CHECK7-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 0
6345 // CHECK7-NEXT:    [[TMP7:%.*]] = load [3 x i64]**, [3 x i64]*** [[DOTADDR4]], align 4
6346 // CHECK7-NEXT:    store [3 x i64]* [[TMP6]], [3 x i64]** [[TMP7]], align 4
6347 // CHECK7-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 1
6348 // CHECK7-NEXT:    [[TMP9:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR2]], align 4
6349 // CHECK7-NEXT:    store [3 x i8*]* [[TMP8]], [3 x i8*]** [[TMP9]], align 4
6350 // CHECK7-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 2
6351 // CHECK7-NEXT:    [[TMP11:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR3]], align 4
6352 // CHECK7-NEXT:    store [3 x i8*]* [[TMP10]], [3 x i8*]** [[TMP11]], align 4
6353 // CHECK7-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 3
6354 // CHECK7-NEXT:    [[TMP13:%.*]] = load i16**, i16*** [[DOTADDR1]], align 4
6355 // CHECK7-NEXT:    store i16* [[TMP12]], i16** [[TMP13]], align 4
6356 // CHECK7-NEXT:    ret void
6357 //
6358 //
6359 // CHECK7-LABEL: define {{[^@]+}}@.omp_task_entry.
6360 // CHECK7-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] {
6361 // CHECK7-NEXT:  entry:
6362 // CHECK7-NEXT:    [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
6363 // CHECK7-NEXT:    [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 4
6364 // CHECK7-NEXT:    [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 4
6365 // CHECK7-NEXT:    [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 4
6366 // CHECK7-NEXT:    [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 4
6367 // CHECK7-NEXT:    [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 4
6368 // CHECK7-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca i16*, align 4
6369 // CHECK7-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca [3 x i8*]*, align 4
6370 // CHECK7-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca [3 x i8*]*, align 4
6371 // CHECK7-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca [3 x i64]*, align 4
6372 // CHECK7-NEXT:    [[AA_CASTED_I:%.*]] = alloca i32, align 4
6373 // CHECK7-NEXT:    [[DOTCAPTURE_EXPR__CASTED_I:%.*]] = alloca i32, align 4
6374 // CHECK7-NEXT:    [[DOTCAPTURE_EXPR__CASTED4_I:%.*]] = alloca i32, align 4
6375 // CHECK7-NEXT:    [[KERNEL_ARGS_I:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
6376 // CHECK7-NEXT:    [[DOTADDR:%.*]] = alloca i32, align 4
6377 // CHECK7-NEXT:    [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 4
6378 // CHECK7-NEXT:    store i32 [[TMP0]], i32* [[DOTADDR]], align 4
6379 // CHECK7-NEXT:    store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4
6380 // CHECK7-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4
6381 // CHECK7-NEXT:    [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4
6382 // CHECK7-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
6383 // CHECK7-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
6384 // CHECK7-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0
6385 // CHECK7-NEXT:    [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 4
6386 // CHECK7-NEXT:    [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon*
6387 // CHECK7-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1
6388 // CHECK7-NEXT:    [[TMP10:%.*]] = bitcast %struct..kmp_privates.t* [[TMP9]] to i8*
6389 // CHECK7-NEXT:    [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8*
6390 // CHECK7-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]])
6391 // CHECK7-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META21:![0-9]+]])
6392 // CHECK7-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META23:![0-9]+]])
6393 // CHECK7-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META25:![0-9]+]])
6394 // CHECK7-NEXT:    store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !27
6395 // CHECK7-NEXT:    store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 4, !noalias !27
6396 // CHECK7-NEXT:    store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !27
6397 // CHECK7-NEXT:    store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* @.omp_task_privates_map. to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !27
6398 // CHECK7-NEXT:    store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 4, !noalias !27
6399 // CHECK7-NEXT:    store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !27
6400 // CHECK7-NEXT:    [[TMP12:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !27
6401 // CHECK7-NEXT:    [[TMP13:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !27
6402 // CHECK7-NEXT:    [[TMP14:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !27
6403 // CHECK7-NEXT:    [[TMP15:%.*]] = bitcast void (i8*, ...)* [[TMP13]] to void (i8*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)*
6404 // CHECK7-NEXT:    call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR4]]
6405 // CHECK7-NEXT:    [[TMP16:%.*]] = load i16*, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 4, !noalias !27
6406 // CHECK7-NEXT:    [[TMP17:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 4, !noalias !27
6407 // CHECK7-NEXT:    [[TMP18:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 4, !noalias !27
6408 // CHECK7-NEXT:    [[TMP19:%.*]] = load [3 x i64]*, [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 4, !noalias !27
6409 // CHECK7-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP17]], i32 0, i32 0
6410 // CHECK7-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP18]], i32 0, i32 0
6411 // CHECK7-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[TMP19]], i32 0, i32 0
6412 // CHECK7-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP12]], i32 0, i32 1
6413 // CHECK7-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[TMP12]], i32 0, i32 2
6414 // CHECK7-NEXT:    [[TMP25:%.*]] = load i32, i32* [[TMP23]], align 4
6415 // CHECK7-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i32 0
6416 // CHECK7-NEXT:    store i32 1, i32* [[TMP26]], align 4, !noalias !27
6417 // CHECK7-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i32 1
6418 // CHECK7-NEXT:    store i32 3, i32* [[TMP27]], align 4, !noalias !27
6419 // CHECK7-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i32 2
6420 // CHECK7-NEXT:    store i8** [[TMP20]], i8*** [[TMP28]], align 4, !noalias !27
6421 // CHECK7-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i32 3
6422 // CHECK7-NEXT:    store i8** [[TMP21]], i8*** [[TMP29]], align 4, !noalias !27
6423 // CHECK7-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i32 4
6424 // CHECK7-NEXT:    store i64* [[TMP22]], i64** [[TMP30]], align 4, !noalias !27
6425 // CHECK7-NEXT:    [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i32 5
6426 // CHECK7-NEXT:    store i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i64** [[TMP31]], align 4, !noalias !27
6427 // CHECK7-NEXT:    [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i32 6
6428 // CHECK7-NEXT:    store i8** null, i8*** [[TMP32]], align 4, !noalias !27
6429 // CHECK7-NEXT:    [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i32 7
6430 // CHECK7-NEXT:    store i8** null, i8*** [[TMP33]], align 4, !noalias !27
6431 // CHECK7-NEXT:    [[TMP34:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i32 8
6432 // CHECK7-NEXT:    store i64 10, i64* [[TMP34]], align 8, !noalias !27
6433 // CHECK7-NEXT:    [[TMP35:%.*]] = call i32 @__tgt_target_kernel_nowait(%struct.ident_t* @[[GLOB2]], i64 -1, i32 [[TMP25]], i32 1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i8* null, i32 0, i8* null) #[[ATTR4]]
6434 // CHECK7-NEXT:    [[TMP36:%.*]] = icmp ne i32 [[TMP35]], 0
6435 // CHECK7-NEXT:    br i1 [[TMP36]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]]
6436 // CHECK7:       omp_offload.failed.i:
6437 // CHECK7-NEXT:    [[TMP37:%.*]] = load i16, i16* [[TMP16]], align 2
6438 // CHECK7-NEXT:    [[CONV_I:%.*]] = bitcast i32* [[AA_CASTED_I]] to i16*
6439 // CHECK7-NEXT:    store i16 [[TMP37]], i16* [[CONV_I]], align 2, !noalias !27
6440 // CHECK7-NEXT:    [[TMP38:%.*]] = load i32, i32* [[AA_CASTED_I]], align 4, !noalias !27
6441 // CHECK7-NEXT:    [[TMP39:%.*]] = load i32, i32* [[TMP23]], align 4
6442 // CHECK7-NEXT:    store i32 [[TMP39]], i32* [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias !27
6443 // CHECK7-NEXT:    [[TMP40:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias !27
6444 // CHECK7-NEXT:    [[TMP41:%.*]] = load i32, i32* [[TMP24]], align 4
6445 // CHECK7-NEXT:    store i32 [[TMP41]], i32* [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias !27
6446 // CHECK7-NEXT:    [[TMP42:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias !27
6447 // CHECK7-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97(i32 [[TMP38]], i32 [[TMP40]], i32 [[TMP42]]) #[[ATTR4]]
6448 // CHECK7-NEXT:    br label [[DOTOMP_OUTLINED__1_EXIT]]
6449 // CHECK7:       .omp_outlined..1.exit:
6450 // CHECK7-NEXT:    ret i32 0
6451 //
6452 //
6453 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l102
6454 // CHECK7-SAME: (i32 noundef [[A:%.*]]) #[[ATTR3]] {
6455 // CHECK7-NEXT:  entry:
6456 // CHECK7-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
6457 // CHECK7-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
6458 // CHECK7-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
6459 // CHECK7-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
6460 // CHECK7-NEXT:    store i32 [[TMP0]], i32* [[A_CASTED]], align 4
6461 // CHECK7-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
6462 // CHECK7-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]])
6463 // CHECK7-NEXT:    ret void
6464 //
6465 //
6466 // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..2
6467 // CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]]) #[[ATTR3]] {
6468 // CHECK7-NEXT:  entry:
6469 // CHECK7-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
6470 // CHECK7-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
6471 // CHECK7-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
6472 // CHECK7-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
6473 // CHECK7-NEXT:    [[TMP:%.*]] = alloca i32, align 4
6474 // CHECK7-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
6475 // CHECK7-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
6476 // CHECK7-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
6477 // CHECK7-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
6478 // CHECK7-NEXT:    [[A1:%.*]] = alloca i32, align 4
6479 // CHECK7-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
6480 // CHECK7-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
6481 // CHECK7-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
6482 // CHECK7-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
6483 // CHECK7-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
6484 // CHECK7-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
6485 // CHECK7-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
6486 // CHECK7-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
6487 // CHECK7-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
6488 // CHECK7-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
6489 // CHECK7-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
6490 // CHECK7-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
6491 // CHECK7-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
6492 // CHECK7:       cond.true:
6493 // CHECK7-NEXT:    br label [[COND_END:%.*]]
6494 // CHECK7:       cond.false:
6495 // CHECK7-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
6496 // CHECK7-NEXT:    br label [[COND_END]]
6497 // CHECK7:       cond.end:
6498 // CHECK7-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
6499 // CHECK7-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
6500 // CHECK7-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
6501 // CHECK7-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
6502 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
6503 // CHECK7:       omp.inner.for.cond:
6504 // CHECK7-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
6505 // CHECK7-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
6506 // CHECK7-NEXT:    [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
6507 // CHECK7-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
6508 // CHECK7:       omp.inner.for.body:
6509 // CHECK7-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
6510 // CHECK7-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
6511 // CHECK7-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
6512 // CHECK7-NEXT:    store i32 [[ADD]], i32* [[A1]], align 4, !nontemporal !28
6513 // CHECK7-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A1]], align 4, !nontemporal !28
6514 // CHECK7-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
6515 // CHECK7-NEXT:    store i32 [[ADD3]], i32* [[A1]], align 4, !nontemporal !28
6516 // CHECK7-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
6517 // CHECK7:       omp.body.continue:
6518 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
6519 // CHECK7:       omp.inner.for.inc:
6520 // CHECK7-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
6521 // CHECK7-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP9]], 1
6522 // CHECK7-NEXT:    store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4
6523 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP29:![0-9]+]]
6524 // CHECK7:       omp.inner.for.end:
6525 // CHECK7-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
6526 // CHECK7:       omp.loop.exit:
6527 // CHECK7-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
6528 // CHECK7-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
6529 // CHECK7-NEXT:    [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0
6530 // CHECK7-NEXT:    br i1 [[TMP11]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
6531 // CHECK7:       .omp.final.then:
6532 // CHECK7-NEXT:    store i32 10, i32* [[A_ADDR]], align 4
6533 // CHECK7-NEXT:    br label [[DOTOMP_FINAL_DONE]]
6534 // CHECK7:       .omp.final.done:
6535 // CHECK7-NEXT:    ret void
6536 //
6537 //
6538 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111
6539 // CHECK7-SAME: (i32 noundef [[AA:%.*]]) #[[ATTR2]] {
6540 // CHECK7-NEXT:  entry:
6541 // CHECK7-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
6542 // CHECK7-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
6543 // CHECK7-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
6544 // CHECK7-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
6545 // CHECK7-NEXT:    [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
6546 // CHECK7-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
6547 // CHECK7-NEXT:    store i16 [[TMP0]], i16* [[CONV1]], align 2
6548 // CHECK7-NEXT:    [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
6549 // CHECK7-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP1]])
6550 // CHECK7-NEXT:    ret void
6551 //
6552 //
6553 // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..3
6554 // CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR3]] {
6555 // CHECK7-NEXT:  entry:
6556 // CHECK7-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
6557 // CHECK7-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
6558 // CHECK7-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
6559 // CHECK7-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
6560 // CHECK7-NEXT:    [[TMP:%.*]] = alloca i32, align 4
6561 // CHECK7-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
6562 // CHECK7-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
6563 // CHECK7-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
6564 // CHECK7-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
6565 // CHECK7-NEXT:    [[I:%.*]] = alloca i32, align 4
6566 // CHECK7-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
6567 // CHECK7-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
6568 // CHECK7-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
6569 // CHECK7-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
6570 // CHECK7-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
6571 // CHECK7-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
6572 // CHECK7-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
6573 // CHECK7-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
6574 // CHECK7-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
6575 // CHECK7-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
6576 // CHECK7-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
6577 // CHECK7-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
6578 // CHECK7-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
6579 // CHECK7-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
6580 // CHECK7:       cond.true:
6581 // CHECK7-NEXT:    br label [[COND_END:%.*]]
6582 // CHECK7:       cond.false:
6583 // CHECK7-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
6584 // CHECK7-NEXT:    br label [[COND_END]]
6585 // CHECK7:       cond.end:
6586 // CHECK7-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
6587 // CHECK7-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
6588 // CHECK7-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
6589 // CHECK7-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
6590 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
6591 // CHECK7:       omp.inner.for.cond:
6592 // CHECK7-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !31
6593 // CHECK7-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !31
6594 // CHECK7-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
6595 // CHECK7-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
6596 // CHECK7:       omp.inner.for.body:
6597 // CHECK7-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !31
6598 // CHECK7-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
6599 // CHECK7-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
6600 // CHECK7-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !31
6601 // CHECK7-NEXT:    [[TMP8:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !31
6602 // CHECK7-NEXT:    [[CONV2:%.*]] = sext i16 [[TMP8]] to i32
6603 // CHECK7-NEXT:    [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
6604 // CHECK7-NEXT:    [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
6605 // CHECK7-NEXT:    store i16 [[CONV4]], i16* [[CONV]], align 2, !llvm.access.group !31
6606 // CHECK7-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
6607 // CHECK7:       omp.body.continue:
6608 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
6609 // CHECK7:       omp.inner.for.inc:
6610 // CHECK7-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !31
6611 // CHECK7-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP9]], 1
6612 // CHECK7-NEXT:    store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !31
6613 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP32:![0-9]+]]
6614 // CHECK7:       omp.inner.for.end:
6615 // CHECK7-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
6616 // CHECK7:       omp.loop.exit:
6617 // CHECK7-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
6618 // CHECK7-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
6619 // CHECK7-NEXT:    [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0
6620 // CHECK7-NEXT:    br i1 [[TMP11]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
6621 // CHECK7:       .omp.final.then:
6622 // CHECK7-NEXT:    store i32 10, i32* [[I]], align 4
6623 // CHECK7-NEXT:    br label [[DOTOMP_FINAL_DONE]]
6624 // CHECK7:       .omp.final.done:
6625 // CHECK7-NEXT:    ret void
6626 //
6627 //
6628 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118
6629 // CHECK7-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] {
6630 // CHECK7-NEXT:  entry:
6631 // CHECK7-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
6632 // CHECK7-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
6633 // CHECK7-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
6634 // CHECK7-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
6635 // CHECK7-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
6636 // CHECK7-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
6637 // CHECK7-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
6638 // CHECK7-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
6639 // CHECK7-NEXT:    store i32 [[TMP0]], i32* [[A_CASTED]], align 4
6640 // CHECK7-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
6641 // CHECK7-NEXT:    [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
6642 // CHECK7-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
6643 // CHECK7-NEXT:    store i16 [[TMP2]], i16* [[CONV1]], align 2
6644 // CHECK7-NEXT:    [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
6645 // CHECK7-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]])
6646 // CHECK7-NEXT:    ret void
6647 //
6648 //
6649 // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..6
6650 // CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR3]] {
6651 // CHECK7-NEXT:  entry:
6652 // CHECK7-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
6653 // CHECK7-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
6654 // CHECK7-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
6655 // CHECK7-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
6656 // CHECK7-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
6657 // CHECK7-NEXT:    [[TMP:%.*]] = alloca i32, align 4
6658 // CHECK7-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
6659 // CHECK7-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
6660 // CHECK7-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
6661 // CHECK7-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
6662 // CHECK7-NEXT:    [[I:%.*]] = alloca i32, align 4
6663 // CHECK7-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
6664 // CHECK7-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
6665 // CHECK7-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
6666 // CHECK7-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
6667 // CHECK7-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
6668 // CHECK7-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
6669 // CHECK7-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
6670 // CHECK7-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
6671 // CHECK7-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
6672 // CHECK7-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
6673 // CHECK7-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
6674 // CHECK7-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
6675 // CHECK7-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
6676 // CHECK7-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
6677 // CHECK7-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
6678 // CHECK7:       cond.true:
6679 // CHECK7-NEXT:    br label [[COND_END:%.*]]
6680 // CHECK7:       cond.false:
6681 // CHECK7-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
6682 // CHECK7-NEXT:    br label [[COND_END]]
6683 // CHECK7:       cond.end:
6684 // CHECK7-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
6685 // CHECK7-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
6686 // CHECK7-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
6687 // CHECK7-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
6688 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
6689 // CHECK7:       omp.inner.for.cond:
6690 // CHECK7-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !34
6691 // CHECK7-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !34
6692 // CHECK7-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
6693 // CHECK7-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
6694 // CHECK7:       omp.inner.for.body:
6695 // CHECK7-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !34
6696 // CHECK7-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
6697 // CHECK7-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
6698 // CHECK7-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !34
6699 // CHECK7-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !34
6700 // CHECK7-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
6701 // CHECK7-NEXT:    store i32 [[ADD2]], i32* [[A_ADDR]], align 4, !llvm.access.group !34
6702 // CHECK7-NEXT:    [[TMP9:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !34
6703 // CHECK7-NEXT:    [[CONV3:%.*]] = sext i16 [[TMP9]] to i32
6704 // CHECK7-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
6705 // CHECK7-NEXT:    [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
6706 // CHECK7-NEXT:    store i16 [[CONV5]], i16* [[CONV]], align 2, !llvm.access.group !34
6707 // CHECK7-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
6708 // CHECK7:       omp.body.continue:
6709 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
6710 // CHECK7:       omp.inner.for.inc:
6711 // CHECK7-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !34
6712 // CHECK7-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP10]], 1
6713 // CHECK7-NEXT:    store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !34
6714 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP35:![0-9]+]]
6715 // CHECK7:       omp.inner.for.end:
6716 // CHECK7-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
6717 // CHECK7:       omp.loop.exit:
6718 // CHECK7-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
6719 // CHECK7-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
6720 // CHECK7-NEXT:    [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
6721 // CHECK7-NEXT:    br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
6722 // CHECK7:       .omp.final.then:
6723 // CHECK7-NEXT:    store i32 10, i32* [[I]], align 4
6724 // CHECK7-NEXT:    br label [[DOTOMP_FINAL_DONE]]
6725 // CHECK7:       .omp.final.done:
6726 // CHECK7-NEXT:    ret void
6727 //
6728 //
6729 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142
6730 // CHECK7-SAME: (i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] {
6731 // CHECK7-NEXT:  entry:
6732 // CHECK7-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
6733 // CHECK7-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
6734 // CHECK7-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
6735 // CHECK7-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 4
6736 // CHECK7-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
6737 // CHECK7-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
6738 // CHECK7-NEXT:    [[VLA_ADDR4:%.*]] = alloca i32, align 4
6739 // CHECK7-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 4
6740 // CHECK7-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
6741 // CHECK7-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
6742 // CHECK7-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
6743 // CHECK7-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
6744 // CHECK7-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
6745 // CHECK7-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 4
6746 // CHECK7-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
6747 // CHECK7-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
6748 // CHECK7-NEXT:    store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
6749 // CHECK7-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 4
6750 // CHECK7-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
6751 // CHECK7-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
6752 // CHECK7-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
6753 // CHECK7-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
6754 // CHECK7-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
6755 // CHECK7-NEXT:    [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
6756 // CHECK7-NEXT:    [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
6757 // CHECK7-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
6758 // CHECK7-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
6759 // CHECK7-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
6760 // CHECK7-NEXT:    store i32 [[TMP8]], i32* [[A_CASTED]], align 4
6761 // CHECK7-NEXT:    [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4
6762 // CHECK7-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]])
6763 // CHECK7-NEXT:    ret void
6764 //
6765 //
6766 // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..9
6767 // CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR3]] {
6768 // CHECK7-NEXT:  entry:
6769 // CHECK7-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
6770 // CHECK7-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
6771 // CHECK7-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
6772 // CHECK7-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
6773 // CHECK7-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
6774 // CHECK7-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 4
6775 // CHECK7-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
6776 // CHECK7-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
6777 // CHECK7-NEXT:    [[VLA_ADDR4:%.*]] = alloca i32, align 4
6778 // CHECK7-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 4
6779 // CHECK7-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
6780 // CHECK7-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
6781 // CHECK7-NEXT:    [[TMP:%.*]] = alloca i32, align 4
6782 // CHECK7-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
6783 // CHECK7-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
6784 // CHECK7-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
6785 // CHECK7-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
6786 // CHECK7-NEXT:    [[I:%.*]] = alloca i32, align 4
6787 // CHECK7-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
6788 // CHECK7-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
6789 // CHECK7-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
6790 // CHECK7-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
6791 // CHECK7-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
6792 // CHECK7-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 4
6793 // CHECK7-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
6794 // CHECK7-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
6795 // CHECK7-NEXT:    store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
6796 // CHECK7-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 4
6797 // CHECK7-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
6798 // CHECK7-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
6799 // CHECK7-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
6800 // CHECK7-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
6801 // CHECK7-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
6802 // CHECK7-NEXT:    [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
6803 // CHECK7-NEXT:    [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
6804 // CHECK7-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
6805 // CHECK7-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
6806 // CHECK7-NEXT:    [[ARRAYDECAY:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 0
6807 // CHECK7-NEXT:    call void @llvm.assume(i1 true) [ "align"(float* [[ARRAYDECAY]], i32 16) ]
6808 // CHECK7-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
6809 // CHECK7-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
6810 // CHECK7-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
6811 // CHECK7-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
6812 // CHECK7-NEXT:    [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
6813 // CHECK7-NEXT:    [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4
6814 // CHECK7-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
6815 // CHECK7-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
6816 // CHECK7-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP10]], 9
6817 // CHECK7-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
6818 // CHECK7:       cond.true:
6819 // CHECK7-NEXT:    br label [[COND_END:%.*]]
6820 // CHECK7:       cond.false:
6821 // CHECK7-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
6822 // CHECK7-NEXT:    br label [[COND_END]]
6823 // CHECK7:       cond.end:
6824 // CHECK7-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ]
6825 // CHECK7-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
6826 // CHECK7-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
6827 // CHECK7-NEXT:    store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4
6828 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
6829 // CHECK7:       omp.inner.for.cond:
6830 // CHECK7-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !37
6831 // CHECK7-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !37
6832 // CHECK7-NEXT:    [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
6833 // CHECK7-NEXT:    br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
6834 // CHECK7:       omp.inner.for.body:
6835 // CHECK7-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !37
6836 // CHECK7-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1
6837 // CHECK7-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
6838 // CHECK7-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !37
6839 // CHECK7-NEXT:    [[TMP16:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !37
6840 // CHECK7-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP16]], 1
6841 // CHECK7-NEXT:    store i32 [[ADD6]], i32* [[A_ADDR]], align 4, !llvm.access.group !37
6842 // CHECK7-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2
6843 // CHECK7-NEXT:    [[TMP17:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !37
6844 // CHECK7-NEXT:    [[CONV:%.*]] = fpext float [[TMP17]] to double
6845 // CHECK7-NEXT:    [[ADD7:%.*]] = fadd double [[CONV]], 1.000000e+00
6846 // CHECK7-NEXT:    [[CONV8:%.*]] = fptrunc double [[ADD7]] to float
6847 // CHECK7-NEXT:    store float [[CONV8]], float* [[ARRAYIDX]], align 4, !llvm.access.group !37
6848 // CHECK7-NEXT:    [[ARRAYIDX9:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3
6849 // CHECK7-NEXT:    [[TMP18:%.*]] = load float, float* [[ARRAYIDX9]], align 4, !llvm.access.group !37
6850 // CHECK7-NEXT:    [[CONV10:%.*]] = fpext float [[TMP18]] to double
6851 // CHECK7-NEXT:    [[ADD11:%.*]] = fadd double [[CONV10]], 1.000000e+00
6852 // CHECK7-NEXT:    [[CONV12:%.*]] = fptrunc double [[ADD11]] to float
6853 // CHECK7-NEXT:    store float [[CONV12]], float* [[ARRAYIDX9]], align 4, !llvm.access.group !37
6854 // CHECK7-NEXT:    [[ARRAYIDX13:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1
6855 // CHECK7-NEXT:    [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX13]], i32 0, i32 2
6856 // CHECK7-NEXT:    [[TMP19:%.*]] = load double, double* [[ARRAYIDX14]], align 8, !llvm.access.group !37
6857 // CHECK7-NEXT:    [[ADD15:%.*]] = fadd double [[TMP19]], 1.000000e+00
6858 // CHECK7-NEXT:    store double [[ADD15]], double* [[ARRAYIDX14]], align 8, !llvm.access.group !37
6859 // CHECK7-NEXT:    [[TMP20:%.*]] = mul nsw i32 1, [[TMP5]]
6860 // CHECK7-NEXT:    [[ARRAYIDX16:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP20]]
6861 // CHECK7-NEXT:    [[ARRAYIDX17:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX16]], i32 3
6862 // CHECK7-NEXT:    [[TMP21:%.*]] = load double, double* [[ARRAYIDX17]], align 8, !llvm.access.group !37
6863 // CHECK7-NEXT:    [[ADD18:%.*]] = fadd double [[TMP21]], 1.000000e+00
6864 // CHECK7-NEXT:    store double [[ADD18]], double* [[ARRAYIDX17]], align 8, !llvm.access.group !37
6865 // CHECK7-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0
6866 // CHECK7-NEXT:    [[TMP22:%.*]] = load i64, i64* [[X]], align 4, !llvm.access.group !37
6867 // CHECK7-NEXT:    [[ADD19:%.*]] = add nsw i64 [[TMP22]], 1
6868 // CHECK7-NEXT:    store i64 [[ADD19]], i64* [[X]], align 4, !llvm.access.group !37
6869 // CHECK7-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1
6870 // CHECK7-NEXT:    [[TMP23:%.*]] = load i8, i8* [[Y]], align 4, !llvm.access.group !37
6871 // CHECK7-NEXT:    [[CONV20:%.*]] = sext i8 [[TMP23]] to i32
6872 // CHECK7-NEXT:    [[ADD21:%.*]] = add nsw i32 [[CONV20]], 1
6873 // CHECK7-NEXT:    [[CONV22:%.*]] = trunc i32 [[ADD21]] to i8
6874 // CHECK7-NEXT:    store i8 [[CONV22]], i8* [[Y]], align 4, !llvm.access.group !37
6875 // CHECK7-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
6876 // CHECK7:       omp.body.continue:
6877 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
6878 // CHECK7:       omp.inner.for.inc:
6879 // CHECK7-NEXT:    [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !37
6880 // CHECK7-NEXT:    [[ADD23:%.*]] = add nsw i32 [[TMP24]], 1
6881 // CHECK7-NEXT:    store i32 [[ADD23]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !37
6882 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP38:![0-9]+]]
6883 // CHECK7:       omp.inner.for.end:
6884 // CHECK7-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
6885 // CHECK7:       omp.loop.exit:
6886 // CHECK7-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]])
6887 // CHECK7-NEXT:    [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
6888 // CHECK7-NEXT:    [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
6889 // CHECK7-NEXT:    br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
6890 // CHECK7:       .omp.final.then:
6891 // CHECK7-NEXT:    store i32 10, i32* [[I]], align 4
6892 // CHECK7-NEXT:    br label [[DOTOMP_FINAL_DONE]]
6893 // CHECK7:       .omp.final.done:
6894 // CHECK7-NEXT:    ret void
6895 //
6896 //
6897 // CHECK7-LABEL: define {{[^@]+}}@_Z3bari
6898 // CHECK7-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {
6899 // CHECK7-NEXT:  entry:
6900 // CHECK7-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
6901 // CHECK7-NEXT:    [[A:%.*]] = alloca i32, align 4
6902 // CHECK7-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4
6903 // CHECK7-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
6904 // CHECK7-NEXT:    store i32 0, i32* [[A]], align 4
6905 // CHECK7-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
6906 // CHECK7-NEXT:    [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]])
6907 // CHECK7-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
6908 // CHECK7-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
6909 // CHECK7-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
6910 // CHECK7-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
6911 // CHECK7-NEXT:    [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP2]])
6912 // CHECK7-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
6913 // CHECK7-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
6914 // CHECK7-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
6915 // CHECK7-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
6916 // CHECK7-NEXT:    [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]])
6917 // CHECK7-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
6918 // CHECK7-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
6919 // CHECK7-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
6920 // CHECK7-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
6921 // CHECK7-NEXT:    [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]])
6922 // CHECK7-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
6923 // CHECK7-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
6924 // CHECK7-NEXT:    store i32 [[ADD6]], i32* [[A]], align 4
6925 // CHECK7-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
6926 // CHECK7-NEXT:    ret i32 [[TMP8]]
6927 //
6928 //
6929 // CHECK7-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
6930 // CHECK7-SAME: (%struct.S1* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 {
6931 // CHECK7-NEXT:  entry:
6932 // CHECK7-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
6933 // CHECK7-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
6934 // CHECK7-NEXT:    [[B:%.*]] = alloca i32, align 4
6935 // CHECK7-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 4
6936 // CHECK7-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 4
6937 // CHECK7-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
6938 // CHECK7-NEXT:    [[B_CASTED:%.*]] = alloca i32, align 4
6939 // CHECK7-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
6940 // CHECK7-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [6 x i8*], align 4
6941 // CHECK7-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [6 x i8*], align 4
6942 // CHECK7-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [6 x i8*], align 4
6943 // CHECK7-NEXT:    [[DOTOFFLOAD_SIZES:%.*]] = alloca [6 x i64], align 4
6944 // CHECK7-NEXT:    [[TMP:%.*]] = alloca i32, align 4
6945 // CHECK7-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
6946 // CHECK7-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
6947 // CHECK7-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
6948 // CHECK7-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
6949 // CHECK7-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
6950 // CHECK7-NEXT:    store i32 [[ADD]], i32* [[B]], align 4
6951 // CHECK7-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
6952 // CHECK7-NEXT:    [[TMP2:%.*]] = call i8* @llvm.stacksave()
6953 // CHECK7-NEXT:    store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4
6954 // CHECK7-NEXT:    [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]
6955 // CHECK7-NEXT:    [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2
6956 // CHECK7-NEXT:    store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
6957 // CHECK7-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
6958 // CHECK7-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 60
6959 // CHECK7-NEXT:    [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8
6960 // CHECK7-NEXT:    store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
6961 // CHECK7-NEXT:    [[TMP5:%.*]] = load i32, i32* [[B]], align 4
6962 // CHECK7-NEXT:    store i32 [[TMP5]], i32* [[B_CASTED]], align 4
6963 // CHECK7-NEXT:    [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4
6964 // CHECK7-NEXT:    [[TMP7:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
6965 // CHECK7-NEXT:    [[TOBOOL:%.*]] = trunc i8 [[TMP7]] to i1
6966 // CHECK7-NEXT:    [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__CASTED]] to i8*
6967 // CHECK7-NEXT:    [[FROMBOOL2:%.*]] = zext i1 [[TOBOOL]] to i8
6968 // CHECK7-NEXT:    store i8 [[FROMBOOL2]], i8* [[CONV]], align 1
6969 // CHECK7-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
6970 // CHECK7-NEXT:    [[TMP9:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
6971 // CHECK7-NEXT:    [[TOBOOL3:%.*]] = trunc i8 [[TMP9]] to i1
6972 // CHECK7-NEXT:    br i1 [[TOBOOL3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
6973 // CHECK7:       omp_if.then:
6974 // CHECK7-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
6975 // CHECK7-NEXT:    [[TMP10:%.*]] = mul nuw i32 2, [[TMP1]]
6976 // CHECK7-NEXT:    [[TMP11:%.*]] = mul nuw i32 [[TMP10]], 2
6977 // CHECK7-NEXT:    [[TMP12:%.*]] = sext i32 [[TMP11]] to i64
6978 // CHECK7-NEXT:    [[TMP13:%.*]] = bitcast [6 x i64]* [[DOTOFFLOAD_SIZES]] to i8*
6979 // CHECK7-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP13]], i8* align 4 bitcast ([6 x i64]* @.offload_sizes.13 to i8*), i32 48, i1 false)
6980 // CHECK7-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
6981 // CHECK7-NEXT:    [[TMP15:%.*]] = bitcast i8** [[TMP14]] to %struct.S1**
6982 // CHECK7-NEXT:    store %struct.S1* [[THIS1]], %struct.S1** [[TMP15]], align 4
6983 // CHECK7-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
6984 // CHECK7-NEXT:    [[TMP17:%.*]] = bitcast i8** [[TMP16]] to double**
6985 // CHECK7-NEXT:    store double* [[A]], double** [[TMP17]], align 4
6986 // CHECK7-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
6987 // CHECK7-NEXT:    store i8* null, i8** [[TMP18]], align 4
6988 // CHECK7-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
6989 // CHECK7-NEXT:    [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32*
6990 // CHECK7-NEXT:    store i32 [[TMP6]], i32* [[TMP20]], align 4
6991 // CHECK7-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
6992 // CHECK7-NEXT:    [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i32*
6993 // CHECK7-NEXT:    store i32 [[TMP6]], i32* [[TMP22]], align 4
6994 // CHECK7-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
6995 // CHECK7-NEXT:    store i8* null, i8** [[TMP23]], align 4
6996 // CHECK7-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
6997 // CHECK7-NEXT:    [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i32*
6998 // CHECK7-NEXT:    store i32 2, i32* [[TMP25]], align 4
6999 // CHECK7-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
7000 // CHECK7-NEXT:    [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i32*
7001 // CHECK7-NEXT:    store i32 2, i32* [[TMP27]], align 4
7002 // CHECK7-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
7003 // CHECK7-NEXT:    store i8* null, i8** [[TMP28]], align 4
7004 // CHECK7-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
7005 // CHECK7-NEXT:    [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i32*
7006 // CHECK7-NEXT:    store i32 [[TMP1]], i32* [[TMP30]], align 4
7007 // CHECK7-NEXT:    [[TMP31:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
7008 // CHECK7-NEXT:    [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i32*
7009 // CHECK7-NEXT:    store i32 [[TMP1]], i32* [[TMP32]], align 4
7010 // CHECK7-NEXT:    [[TMP33:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
7011 // CHECK7-NEXT:    store i8* null, i8** [[TMP33]], align 4
7012 // CHECK7-NEXT:    [[TMP34:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
7013 // CHECK7-NEXT:    [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i16**
7014 // CHECK7-NEXT:    store i16* [[VLA]], i16** [[TMP35]], align 4
7015 // CHECK7-NEXT:    [[TMP36:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
7016 // CHECK7-NEXT:    [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i16**
7017 // CHECK7-NEXT:    store i16* [[VLA]], i16** [[TMP37]], align 4
7018 // CHECK7-NEXT:    [[TMP38:%.*]] = getelementptr inbounds [6 x i64], [6 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4
7019 // CHECK7-NEXT:    store i64 [[TMP12]], i64* [[TMP38]], align 4
7020 // CHECK7-NEXT:    [[TMP39:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4
7021 // CHECK7-NEXT:    store i8* null, i8** [[TMP39]], align 4
7022 // CHECK7-NEXT:    [[TMP40:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 5
7023 // CHECK7-NEXT:    [[TMP41:%.*]] = bitcast i8** [[TMP40]] to i32*
7024 // CHECK7-NEXT:    store i32 [[TMP8]], i32* [[TMP41]], align 4
7025 // CHECK7-NEXT:    [[TMP42:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 5
7026 // CHECK7-NEXT:    [[TMP43:%.*]] = bitcast i8** [[TMP42]] to i32*
7027 // CHECK7-NEXT:    store i32 [[TMP8]], i32* [[TMP43]], align 4
7028 // CHECK7-NEXT:    [[TMP44:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 5
7029 // CHECK7-NEXT:    store i8* null, i8** [[TMP44]], align 4
7030 // CHECK7-NEXT:    [[TMP45:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
7031 // CHECK7-NEXT:    [[TMP46:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
7032 // CHECK7-NEXT:    [[TMP47:%.*]] = getelementptr inbounds [6 x i64], [6 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
7033 // CHECK7-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
7034 // CHECK7-NEXT:    [[TMP48:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
7035 // CHECK7-NEXT:    store i32 1, i32* [[TMP48]], align 4
7036 // CHECK7-NEXT:    [[TMP49:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
7037 // CHECK7-NEXT:    store i32 6, i32* [[TMP49]], align 4
7038 // CHECK7-NEXT:    [[TMP50:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
7039 // CHECK7-NEXT:    store i8** [[TMP45]], i8*** [[TMP50]], align 4
7040 // CHECK7-NEXT:    [[TMP51:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
7041 // CHECK7-NEXT:    store i8** [[TMP46]], i8*** [[TMP51]], align 4
7042 // CHECK7-NEXT:    [[TMP52:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
7043 // CHECK7-NEXT:    store i64* [[TMP47]], i64** [[TMP52]], align 4
7044 // CHECK7-NEXT:    [[TMP53:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
7045 // CHECK7-NEXT:    store i64* getelementptr inbounds ([6 x i64], [6 x i64]* @.offload_maptypes.14, i32 0, i32 0), i64** [[TMP53]], align 4
7046 // CHECK7-NEXT:    [[TMP54:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
7047 // CHECK7-NEXT:    store i8** null, i8*** [[TMP54]], align 4
7048 // CHECK7-NEXT:    [[TMP55:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
7049 // CHECK7-NEXT:    store i8** null, i8*** [[TMP55]], align 4
7050 // CHECK7-NEXT:    [[TMP56:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
7051 // CHECK7-NEXT:    store i64 10, i64* [[TMP56]], align 8
7052 // CHECK7-NEXT:    [[TMP57:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB2]], i64 -1, i32 0, i32 1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
7053 // CHECK7-NEXT:    [[TMP58:%.*]] = icmp ne i32 [[TMP57]], 0
7054 // CHECK7-NEXT:    br i1 [[TMP58]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
7055 // CHECK7:       omp_offload.failed:
7056 // CHECK7-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215(%struct.S1* [[THIS1]], i32 [[TMP6]], i32 2, i32 [[TMP1]], i16* [[VLA]], i32 [[TMP8]]) #[[ATTR4]]
7057 // CHECK7-NEXT:    br label [[OMP_OFFLOAD_CONT]]
7058 // CHECK7:       omp_offload.cont:
7059 // CHECK7-NEXT:    br label [[OMP_IF_END:%.*]]
7060 // CHECK7:       omp_if.else:
7061 // CHECK7-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215(%struct.S1* [[THIS1]], i32 [[TMP6]], i32 2, i32 [[TMP1]], i16* [[VLA]], i32 [[TMP8]]) #[[ATTR4]]
7062 // CHECK7-NEXT:    br label [[OMP_IF_END]]
7063 // CHECK7:       omp_if.end:
7064 // CHECK7-NEXT:    [[TMP59:%.*]] = mul nsw i32 1, [[TMP1]]
7065 // CHECK7-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP59]]
7066 // CHECK7-NEXT:    [[ARRAYIDX4:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
7067 // CHECK7-NEXT:    [[TMP60:%.*]] = load i16, i16* [[ARRAYIDX4]], align 2
7068 // CHECK7-NEXT:    [[CONV5:%.*]] = sext i16 [[TMP60]] to i32
7069 // CHECK7-NEXT:    [[TMP61:%.*]] = load i32, i32* [[B]], align 4
7070 // CHECK7-NEXT:    [[ADD6:%.*]] = add nsw i32 [[CONV5]], [[TMP61]]
7071 // CHECK7-NEXT:    [[TMP62:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
7072 // CHECK7-NEXT:    call void @llvm.stackrestore(i8* [[TMP62]])
7073 // CHECK7-NEXT:    ret i32 [[ADD6]]
7074 //
7075 //
7076 // CHECK7-LABEL: define {{[^@]+}}@_ZL7fstatici
7077 // CHECK7-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {
7078 // CHECK7-NEXT:  entry:
7079 // CHECK7-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
7080 // CHECK7-NEXT:    [[A:%.*]] = alloca i32, align 4
7081 // CHECK7-NEXT:    [[AA:%.*]] = alloca i16, align 2
7082 // CHECK7-NEXT:    [[AAA:%.*]] = alloca i8, align 1
7083 // CHECK7-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
7084 // CHECK7-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
7085 // CHECK7-NEXT:    [[N_CASTED:%.*]] = alloca i32, align 4
7086 // CHECK7-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
7087 // CHECK7-NEXT:    [[AAA_CASTED:%.*]] = alloca i32, align 4
7088 // CHECK7-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4
7089 // CHECK7-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4
7090 // CHECK7-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4
7091 // CHECK7-NEXT:    [[TMP:%.*]] = alloca i32, align 4
7092 // CHECK7-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
7093 // CHECK7-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
7094 // CHECK7-NEXT:    [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4
7095 // CHECK7-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
7096 // CHECK7-NEXT:    store i32 0, i32* [[A]], align 4
7097 // CHECK7-NEXT:    store i16 0, i16* [[AA]], align 2
7098 // CHECK7-NEXT:    store i8 0, i8* [[AAA]], align 1
7099 // CHECK7-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
7100 // CHECK7-NEXT:    store i32 [[TMP0]], i32* [[A_CASTED]], align 4
7101 // CHECK7-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
7102 // CHECK7-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
7103 // CHECK7-NEXT:    store i32 [[TMP2]], i32* [[N_CASTED]], align 4
7104 // CHECK7-NEXT:    [[TMP3:%.*]] = load i32, i32* [[N_CASTED]], align 4
7105 // CHECK7-NEXT:    [[TMP4:%.*]] = load i16, i16* [[AA]], align 2
7106 // CHECK7-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
7107 // CHECK7-NEXT:    store i16 [[TMP4]], i16* [[CONV]], align 2
7108 // CHECK7-NEXT:    [[TMP5:%.*]] = load i32, i32* [[AA_CASTED]], align 4
7109 // CHECK7-NEXT:    [[TMP6:%.*]] = load i8, i8* [[AAA]], align 1
7110 // CHECK7-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
7111 // CHECK7-NEXT:    store i8 [[TMP6]], i8* [[CONV1]], align 1
7112 // CHECK7-NEXT:    [[TMP7:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
7113 // CHECK7-NEXT:    [[TMP8:%.*]] = load i32, i32* [[N_ADDR]], align 4
7114 // CHECK7-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP8]], 50
7115 // CHECK7-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
7116 // CHECK7:       omp_if.then:
7117 // CHECK7-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
7118 // CHECK7-NEXT:    [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32*
7119 // CHECK7-NEXT:    store i32 [[TMP1]], i32* [[TMP10]], align 4
7120 // CHECK7-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
7121 // CHECK7-NEXT:    [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32*
7122 // CHECK7-NEXT:    store i32 [[TMP1]], i32* [[TMP12]], align 4
7123 // CHECK7-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
7124 // CHECK7-NEXT:    store i8* null, i8** [[TMP13]], align 4
7125 // CHECK7-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
7126 // CHECK7-NEXT:    [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32*
7127 // CHECK7-NEXT:    store i32 [[TMP3]], i32* [[TMP15]], align 4
7128 // CHECK7-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
7129 // CHECK7-NEXT:    [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32*
7130 // CHECK7-NEXT:    store i32 [[TMP3]], i32* [[TMP17]], align 4
7131 // CHECK7-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
7132 // CHECK7-NEXT:    store i8* null, i8** [[TMP18]], align 4
7133 // CHECK7-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
7134 // CHECK7-NEXT:    [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32*
7135 // CHECK7-NEXT:    store i32 [[TMP5]], i32* [[TMP20]], align 4
7136 // CHECK7-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
7137 // CHECK7-NEXT:    [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i32*
7138 // CHECK7-NEXT:    store i32 [[TMP5]], i32* [[TMP22]], align 4
7139 // CHECK7-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
7140 // CHECK7-NEXT:    store i8* null, i8** [[TMP23]], align 4
7141 // CHECK7-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
7142 // CHECK7-NEXT:    [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i32*
7143 // CHECK7-NEXT:    store i32 [[TMP7]], i32* [[TMP25]], align 4
7144 // CHECK7-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
7145 // CHECK7-NEXT:    [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i32*
7146 // CHECK7-NEXT:    store i32 [[TMP7]], i32* [[TMP27]], align 4
7147 // CHECK7-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
7148 // CHECK7-NEXT:    store i8* null, i8** [[TMP28]], align 4
7149 // CHECK7-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
7150 // CHECK7-NEXT:    [[TMP30:%.*]] = bitcast i8** [[TMP29]] to [10 x i32]**
7151 // CHECK7-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP30]], align 4
7152 // CHECK7-NEXT:    [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
7153 // CHECK7-NEXT:    [[TMP32:%.*]] = bitcast i8** [[TMP31]] to [10 x i32]**
7154 // CHECK7-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP32]], align 4
7155 // CHECK7-NEXT:    [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4
7156 // CHECK7-NEXT:    store i8* null, i8** [[TMP33]], align 4
7157 // CHECK7-NEXT:    [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
7158 // CHECK7-NEXT:    [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
7159 // CHECK7-NEXT:    [[TMP36:%.*]] = load i32, i32* [[A]], align 4
7160 // CHECK7-NEXT:    store i32 [[TMP36]], i32* [[DOTCAPTURE_EXPR_]], align 4
7161 // CHECK7-NEXT:    [[TMP37:%.*]] = load i32, i32* [[N_ADDR]], align 4
7162 // CHECK7-NEXT:    store i32 [[TMP37]], i32* [[DOTCAPTURE_EXPR_2]], align 4
7163 // CHECK7-NEXT:    [[TMP38:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
7164 // CHECK7-NEXT:    [[TMP39:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
7165 // CHECK7-NEXT:    [[SUB:%.*]] = sub i32 [[TMP38]], [[TMP39]]
7166 // CHECK7-NEXT:    [[SUB4:%.*]] = sub i32 [[SUB]], 1
7167 // CHECK7-NEXT:    [[ADD:%.*]] = add i32 [[SUB4]], 1
7168 // CHECK7-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], 1
7169 // CHECK7-NEXT:    [[SUB5:%.*]] = sub i32 [[DIV]], 1
7170 // CHECK7-NEXT:    store i32 [[SUB5]], i32* [[DOTCAPTURE_EXPR_3]], align 4
7171 // CHECK7-NEXT:    [[TMP40:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
7172 // CHECK7-NEXT:    [[ADD6:%.*]] = add i32 [[TMP40]], 1
7173 // CHECK7-NEXT:    [[TMP41:%.*]] = zext i32 [[ADD6]] to i64
7174 // CHECK7-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
7175 // CHECK7-NEXT:    [[TMP42:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
7176 // CHECK7-NEXT:    store i32 1, i32* [[TMP42]], align 4
7177 // CHECK7-NEXT:    [[TMP43:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
7178 // CHECK7-NEXT:    store i32 5, i32* [[TMP43]], align 4
7179 // CHECK7-NEXT:    [[TMP44:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
7180 // CHECK7-NEXT:    store i8** [[TMP34]], i8*** [[TMP44]], align 4
7181 // CHECK7-NEXT:    [[TMP45:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
7182 // CHECK7-NEXT:    store i8** [[TMP35]], i8*** [[TMP45]], align 4
7183 // CHECK7-NEXT:    [[TMP46:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
7184 // CHECK7-NEXT:    store i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes.16, i32 0, i32 0), i64** [[TMP46]], align 4
7185 // CHECK7-NEXT:    [[TMP47:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
7186 // CHECK7-NEXT:    store i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.17, i32 0, i32 0), i64** [[TMP47]], align 4
7187 // CHECK7-NEXT:    [[TMP48:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
7188 // CHECK7-NEXT:    store i8** null, i8*** [[TMP48]], align 4
7189 // CHECK7-NEXT:    [[TMP49:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
7190 // CHECK7-NEXT:    store i8** null, i8*** [[TMP49]], align 4
7191 // CHECK7-NEXT:    [[TMP50:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
7192 // CHECK7-NEXT:    store i64 [[TMP41]], i64* [[TMP50]], align 8
7193 // CHECK7-NEXT:    [[TMP51:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB2]], i64 -1, i32 0, i32 1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
7194 // CHECK7-NEXT:    [[TMP52:%.*]] = icmp ne i32 [[TMP51]], 0
7195 // CHECK7-NEXT:    br i1 [[TMP52]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
7196 // CHECK7:       omp_offload.failed:
7197 // CHECK7-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], i32 [[TMP7]], [10 x i32]* [[B]]) #[[ATTR4]]
7198 // CHECK7-NEXT:    br label [[OMP_OFFLOAD_CONT]]
7199 // CHECK7:       omp_offload.cont:
7200 // CHECK7-NEXT:    br label [[OMP_IF_END:%.*]]
7201 // CHECK7:       omp_if.else:
7202 // CHECK7-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], i32 [[TMP7]], [10 x i32]* [[B]]) #[[ATTR4]]
7203 // CHECK7-NEXT:    br label [[OMP_IF_END]]
7204 // CHECK7:       omp_if.end:
7205 // CHECK7-NEXT:    [[TMP53:%.*]] = load i32, i32* [[A]], align 4
7206 // CHECK7-NEXT:    ret i32 [[TMP53]]
7207 //
7208 //
7209 // CHECK7-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
7210 // CHECK7-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat {
7211 // CHECK7-NEXT:  entry:
7212 // CHECK7-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
7213 // CHECK7-NEXT:    [[A:%.*]] = alloca i32, align 4
7214 // CHECK7-NEXT:    [[AA:%.*]] = alloca i16, align 2
7215 // CHECK7-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
7216 // CHECK7-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
7217 // CHECK7-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
7218 // CHECK7-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4
7219 // CHECK7-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4
7220 // CHECK7-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4
7221 // CHECK7-NEXT:    [[TMP:%.*]] = alloca i32, align 4
7222 // CHECK7-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
7223 // CHECK7-NEXT:    store i32 0, i32* [[A]], align 4
7224 // CHECK7-NEXT:    store i16 0, i16* [[AA]], align 2
7225 // CHECK7-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
7226 // CHECK7-NEXT:    store i32 [[TMP0]], i32* [[A_CASTED]], align 4
7227 // CHECK7-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
7228 // CHECK7-NEXT:    [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
7229 // CHECK7-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
7230 // CHECK7-NEXT:    store i16 [[TMP2]], i16* [[CONV]], align 2
7231 // CHECK7-NEXT:    [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
7232 // CHECK7-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
7233 // CHECK7-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40
7234 // CHECK7-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
7235 // CHECK7:       omp_if.then:
7236 // CHECK7-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
7237 // CHECK7-NEXT:    [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i32*
7238 // CHECK7-NEXT:    store i32 [[TMP1]], i32* [[TMP6]], align 4
7239 // CHECK7-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
7240 // CHECK7-NEXT:    [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32*
7241 // CHECK7-NEXT:    store i32 [[TMP1]], i32* [[TMP8]], align 4
7242 // CHECK7-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
7243 // CHECK7-NEXT:    store i8* null, i8** [[TMP9]], align 4
7244 // CHECK7-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
7245 // CHECK7-NEXT:    [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i32*
7246 // CHECK7-NEXT:    store i32 [[TMP3]], i32* [[TMP11]], align 4
7247 // CHECK7-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
7248 // CHECK7-NEXT:    [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32*
7249 // CHECK7-NEXT:    store i32 [[TMP3]], i32* [[TMP13]], align 4
7250 // CHECK7-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
7251 // CHECK7-NEXT:    store i8* null, i8** [[TMP14]], align 4
7252 // CHECK7-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
7253 // CHECK7-NEXT:    [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]**
7254 // CHECK7-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 4
7255 // CHECK7-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
7256 // CHECK7-NEXT:    [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]**
7257 // CHECK7-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 4
7258 // CHECK7-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
7259 // CHECK7-NEXT:    store i8* null, i8** [[TMP19]], align 4
7260 // CHECK7-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
7261 // CHECK7-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
7262 // CHECK7-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
7263 // CHECK7-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
7264 // CHECK7-NEXT:    store i32 1, i32* [[TMP22]], align 4
7265 // CHECK7-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
7266 // CHECK7-NEXT:    store i32 3, i32* [[TMP23]], align 4
7267 // CHECK7-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
7268 // CHECK7-NEXT:    store i8** [[TMP20]], i8*** [[TMP24]], align 4
7269 // CHECK7-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
7270 // CHECK7-NEXT:    store i8** [[TMP21]], i8*** [[TMP25]], align 4
7271 // CHECK7-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
7272 // CHECK7-NEXT:    store i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.19, i32 0, i32 0), i64** [[TMP26]], align 4
7273 // CHECK7-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
7274 // CHECK7-NEXT:    store i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.20, i32 0, i32 0), i64** [[TMP27]], align 4
7275 // CHECK7-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
7276 // CHECK7-NEXT:    store i8** null, i8*** [[TMP28]], align 4
7277 // CHECK7-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
7278 // CHECK7-NEXT:    store i8** null, i8*** [[TMP29]], align 4
7279 // CHECK7-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
7280 // CHECK7-NEXT:    store i64 10, i64* [[TMP30]], align 8
7281 // CHECK7-NEXT:    [[TMP31:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB2]], i64 -1, i32 0, i32 1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
7282 // CHECK7-NEXT:    [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0
7283 // CHECK7-NEXT:    br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
7284 // CHECK7:       omp_offload.failed:
7285 // CHECK7-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]]
7286 // CHECK7-NEXT:    br label [[OMP_OFFLOAD_CONT]]
7287 // CHECK7:       omp_offload.cont:
7288 // CHECK7-NEXT:    br label [[OMP_IF_END:%.*]]
7289 // CHECK7:       omp_if.else:
7290 // CHECK7-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]]
7291 // CHECK7-NEXT:    br label [[OMP_IF_END]]
7292 // CHECK7:       omp_if.end:
7293 // CHECK7-NEXT:    [[TMP33:%.*]] = load i32, i32* [[A]], align 4
7294 // CHECK7-NEXT:    ret i32 [[TMP33]]
7295 //
7296 //
7297 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215
7298 // CHECK7-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] {
7299 // CHECK7-NEXT:  entry:
7300 // CHECK7-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
7301 // CHECK7-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
7302 // CHECK7-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
7303 // CHECK7-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
7304 // CHECK7-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 4
7305 // CHECK7-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
7306 // CHECK7-NEXT:    [[B_CASTED:%.*]] = alloca i32, align 4
7307 // CHECK7-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
7308 // CHECK7-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
7309 // CHECK7-NEXT:    store i32 [[B]], i32* [[B_ADDR]], align 4
7310 // CHECK7-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
7311 // CHECK7-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
7312 // CHECK7-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 4
7313 // CHECK7-NEXT:    store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
7314 // CHECK7-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
7315 // CHECK7-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
7316 // CHECK7-NEXT:    [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
7317 // CHECK7-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
7318 // CHECK7-NEXT:    [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8*
7319 // CHECK7-NEXT:    [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4
7320 // CHECK7-NEXT:    store i32 [[TMP4]], i32* [[B_CASTED]], align 4
7321 // CHECK7-NEXT:    [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4
7322 // CHECK7-NEXT:    [[TMP6:%.*]] = load i8, i8* [[CONV]], align 1
7323 // CHECK7-NEXT:    [[TOBOOL:%.*]] = trunc i8 [[TMP6]] to i1
7324 // CHECK7-NEXT:    [[CONV3:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__CASTED]] to i8*
7325 // CHECK7-NEXT:    [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
7326 // CHECK7-NEXT:    store i8 [[FROMBOOL]], i8* [[CONV3]], align 1
7327 // CHECK7-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
7328 // CHECK7-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*, i32)* @.omp_outlined..12 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]], i32 [[TMP7]])
7329 // CHECK7-NEXT:    ret void
7330 //
7331 //
7332 // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..12
7333 // CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] {
7334 // CHECK7-NEXT:  entry:
7335 // CHECK7-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
7336 // CHECK7-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
7337 // CHECK7-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
7338 // CHECK7-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
7339 // CHECK7-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
7340 // CHECK7-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
7341 // CHECK7-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 4
7342 // CHECK7-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
7343 // CHECK7-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
7344 // CHECK7-NEXT:    [[TMP:%.*]] = alloca i32, align 4
7345 // CHECK7-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
7346 // CHECK7-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
7347 // CHECK7-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
7348 // CHECK7-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
7349 // CHECK7-NEXT:    [[I:%.*]] = alloca i32, align 4
7350 // CHECK7-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
7351 // CHECK7-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
7352 // CHECK7-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
7353 // CHECK7-NEXT:    store i32 [[B]], i32* [[B_ADDR]], align 4
7354 // CHECK7-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
7355 // CHECK7-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
7356 // CHECK7-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 4
7357 // CHECK7-NEXT:    store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
7358 // CHECK7-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
7359 // CHECK7-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
7360 // CHECK7-NEXT:    [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
7361 // CHECK7-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
7362 // CHECK7-NEXT:    [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8*
7363 // CHECK7-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
7364 // CHECK7-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
7365 // CHECK7-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
7366 // CHECK7-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
7367 // CHECK7-NEXT:    [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
7368 // CHECK7-NEXT:    [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
7369 // CHECK7-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
7370 // CHECK7-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
7371 // CHECK7-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 9
7372 // CHECK7-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
7373 // CHECK7:       cond.true:
7374 // CHECK7-NEXT:    br label [[COND_END:%.*]]
7375 // CHECK7:       cond.false:
7376 // CHECK7-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
7377 // CHECK7-NEXT:    br label [[COND_END]]
7378 // CHECK7:       cond.end:
7379 // CHECK7-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
7380 // CHECK7-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
7381 // CHECK7-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
7382 // CHECK7-NEXT:    store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
7383 // CHECK7-NEXT:    [[TMP9:%.*]] = load i8, i8* [[CONV]], align 1
7384 // CHECK7-NEXT:    [[TOBOOL:%.*]] = trunc i8 [[TMP9]] to i1
7385 // CHECK7-NEXT:    br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
7386 // CHECK7:       omp_if.then:
7387 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
7388 // CHECK7:       omp.inner.for.cond:
7389 // CHECK7-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !40
7390 // CHECK7-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !40
7391 // CHECK7-NEXT:    [[CMP3:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]
7392 // CHECK7-NEXT:    br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
7393 // CHECK7:       omp.inner.for.body:
7394 // CHECK7-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !40
7395 // CHECK7-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1
7396 // CHECK7-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
7397 // CHECK7-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !40
7398 // CHECK7-NEXT:    [[TMP13:%.*]] = load i32, i32* [[B_ADDR]], align 4, !llvm.access.group !40
7399 // CHECK7-NEXT:    [[CONV4:%.*]] = sitofp i32 [[TMP13]] to double
7400 // CHECK7-NEXT:    [[ADD5:%.*]] = fadd double [[CONV4]], 1.500000e+00
7401 // CHECK7-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
7402 // CHECK7-NEXT:    store double [[ADD5]], double* [[A]], align 4, !llvm.access.group !40
7403 // CHECK7-NEXT:    [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
7404 // CHECK7-NEXT:    [[TMP14:%.*]] = load double, double* [[A6]], align 4, !llvm.access.group !40
7405 // CHECK7-NEXT:    [[INC:%.*]] = fadd double [[TMP14]], 1.000000e+00
7406 // CHECK7-NEXT:    store double [[INC]], double* [[A6]], align 4, !llvm.access.group !40
7407 // CHECK7-NEXT:    [[CONV7:%.*]] = fptosi double [[INC]] to i16
7408 // CHECK7-NEXT:    [[TMP15:%.*]] = mul nsw i32 1, [[TMP2]]
7409 // CHECK7-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP15]]
7410 // CHECK7-NEXT:    [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
7411 // CHECK7-NEXT:    store i16 [[CONV7]], i16* [[ARRAYIDX8]], align 2, !llvm.access.group !40
7412 // CHECK7-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
7413 // CHECK7:       omp.body.continue:
7414 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
7415 // CHECK7:       omp.inner.for.inc:
7416 // CHECK7-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !40
7417 // CHECK7-NEXT:    [[ADD9:%.*]] = add nsw i32 [[TMP16]], 1
7418 // CHECK7-NEXT:    store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !40
7419 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP41:![0-9]+]]
7420 // CHECK7:       omp.inner.for.end:
7421 // CHECK7-NEXT:    br label [[OMP_IF_END:%.*]]
7422 // CHECK7:       omp_if.else:
7423 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_COND10:%.*]]
7424 // CHECK7:       omp.inner.for.cond10:
7425 // CHECK7-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
7426 // CHECK7-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
7427 // CHECK7-NEXT:    [[CMP11:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]]
7428 // CHECK7-NEXT:    br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY12:%.*]], label [[OMP_INNER_FOR_END26:%.*]]
7429 // CHECK7:       omp.inner.for.body12:
7430 // CHECK7-NEXT:    [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
7431 // CHECK7-NEXT:    [[MUL13:%.*]] = mul nsw i32 [[TMP19]], 1
7432 // CHECK7-NEXT:    [[ADD14:%.*]] = add nsw i32 0, [[MUL13]]
7433 // CHECK7-NEXT:    store i32 [[ADD14]], i32* [[I]], align 4
7434 // CHECK7-NEXT:    [[TMP20:%.*]] = load i32, i32* [[B_ADDR]], align 4
7435 // CHECK7-NEXT:    [[CONV15:%.*]] = sitofp i32 [[TMP20]] to double
7436 // CHECK7-NEXT:    [[ADD16:%.*]] = fadd double [[CONV15]], 1.500000e+00
7437 // CHECK7-NEXT:    [[A17:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
7438 // CHECK7-NEXT:    store double [[ADD16]], double* [[A17]], align 4
7439 // CHECK7-NEXT:    [[A18:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
7440 // CHECK7-NEXT:    [[TMP21:%.*]] = load double, double* [[A18]], align 4
7441 // CHECK7-NEXT:    [[INC19:%.*]] = fadd double [[TMP21]], 1.000000e+00
7442 // CHECK7-NEXT:    store double [[INC19]], double* [[A18]], align 4
7443 // CHECK7-NEXT:    [[CONV20:%.*]] = fptosi double [[INC19]] to i16
7444 // CHECK7-NEXT:    [[TMP22:%.*]] = mul nsw i32 1, [[TMP2]]
7445 // CHECK7-NEXT:    [[ARRAYIDX21:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP22]]
7446 // CHECK7-NEXT:    [[ARRAYIDX22:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX21]], i32 1
7447 // CHECK7-NEXT:    store i16 [[CONV20]], i16* [[ARRAYIDX22]], align 2
7448 // CHECK7-NEXT:    br label [[OMP_BODY_CONTINUE23:%.*]]
7449 // CHECK7:       omp.body.continue23:
7450 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_INC24:%.*]]
7451 // CHECK7:       omp.inner.for.inc24:
7452 // CHECK7-NEXT:    [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
7453 // CHECK7-NEXT:    [[ADD25:%.*]] = add nsw i32 [[TMP23]], 1
7454 // CHECK7-NEXT:    store i32 [[ADD25]], i32* [[DOTOMP_IV]], align 4
7455 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_COND10]], !llvm.loop [[LOOP43:![0-9]+]]
7456 // CHECK7:       omp.inner.for.end26:
7457 // CHECK7-NEXT:    br label [[OMP_IF_END]]
7458 // CHECK7:       omp_if.end:
7459 // CHECK7-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
7460 // CHECK7:       omp.loop.exit:
7461 // CHECK7-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
7462 // CHECK7-NEXT:    [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
7463 // CHECK7-NEXT:    [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0
7464 // CHECK7-NEXT:    br i1 [[TMP25]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
7465 // CHECK7:       .omp.final.then:
7466 // CHECK7-NEXT:    store i32 10, i32* [[I]], align 4
7467 // CHECK7-NEXT:    br label [[DOTOMP_FINAL_DONE]]
7468 // CHECK7:       .omp.final.done:
7469 // CHECK7-NEXT:    ret void
7470 //
7471 //
7472 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197
7473 // CHECK7-SAME: (i32 noundef [[A:%.*]], i32 noundef [[N:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
7474 // CHECK7-NEXT:  entry:
7475 // CHECK7-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
7476 // CHECK7-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
7477 // CHECK7-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
7478 // CHECK7-NEXT:    [[AAA_ADDR:%.*]] = alloca i32, align 4
7479 // CHECK7-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
7480 // CHECK7-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
7481 // CHECK7-NEXT:    [[N_CASTED:%.*]] = alloca i32, align 4
7482 // CHECK7-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
7483 // CHECK7-NEXT:    [[AAA_CASTED:%.*]] = alloca i32, align 4
7484 // CHECK7-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
7485 // CHECK7-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
7486 // CHECK7-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
7487 // CHECK7-NEXT:    store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
7488 // CHECK7-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
7489 // CHECK7-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
7490 // CHECK7-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
7491 // CHECK7-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
7492 // CHECK7-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
7493 // CHECK7-NEXT:    store i32 [[TMP1]], i32* [[A_CASTED]], align 4
7494 // CHECK7-NEXT:    [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
7495 // CHECK7-NEXT:    [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
7496 // CHECK7-NEXT:    store i32 [[TMP3]], i32* [[N_CASTED]], align 4
7497 // CHECK7-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_CASTED]], align 4
7498 // CHECK7-NEXT:    [[TMP5:%.*]] = load i16, i16* [[CONV]], align 2
7499 // CHECK7-NEXT:    [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
7500 // CHECK7-NEXT:    store i16 [[TMP5]], i16* [[CONV2]], align 2
7501 // CHECK7-NEXT:    [[TMP6:%.*]] = load i32, i32* [[AA_CASTED]], align 4
7502 // CHECK7-NEXT:    [[TMP7:%.*]] = load i8, i8* [[CONV1]], align 1
7503 // CHECK7-NEXT:    [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
7504 // CHECK7-NEXT:    store i8 [[TMP7]], i8* [[CONV3]], align 1
7505 // CHECK7-NEXT:    [[TMP8:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
7506 // CHECK7-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, [10 x i32]*)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP8]], [10 x i32]* [[TMP0]])
7507 // CHECK7-NEXT:    ret void
7508 //
7509 //
7510 // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..15
7511 // CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[N:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] {
7512 // CHECK7-NEXT:  entry:
7513 // CHECK7-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
7514 // CHECK7-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
7515 // CHECK7-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
7516 // CHECK7-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
7517 // CHECK7-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
7518 // CHECK7-NEXT:    [[AAA_ADDR:%.*]] = alloca i32, align 4
7519 // CHECK7-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
7520 // CHECK7-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
7521 // CHECK7-NEXT:    [[TMP:%.*]] = alloca i32, align 4
7522 // CHECK7-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
7523 // CHECK7-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
7524 // CHECK7-NEXT:    [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4
7525 // CHECK7-NEXT:    [[I:%.*]] = alloca i32, align 4
7526 // CHECK7-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
7527 // CHECK7-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
7528 // CHECK7-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
7529 // CHECK7-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
7530 // CHECK7-NEXT:    [[I6:%.*]] = alloca i32, align 4
7531 // CHECK7-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
7532 // CHECK7-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
7533 // CHECK7-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
7534 // CHECK7-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
7535 // CHECK7-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
7536 // CHECK7-NEXT:    store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
7537 // CHECK7-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
7538 // CHECK7-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
7539 // CHECK7-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
7540 // CHECK7-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
7541 // CHECK7-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
7542 // CHECK7-NEXT:    store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
7543 // CHECK7-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
7544 // CHECK7-NEXT:    store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4
7545 // CHECK7-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
7546 // CHECK7-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
7547 // CHECK7-NEXT:    [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]]
7548 // CHECK7-NEXT:    [[SUB4:%.*]] = sub i32 [[SUB]], 1
7549 // CHECK7-NEXT:    [[ADD:%.*]] = add i32 [[SUB4]], 1
7550 // CHECK7-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], 1
7551 // CHECK7-NEXT:    [[SUB5:%.*]] = sub i32 [[DIV]], 1
7552 // CHECK7-NEXT:    store i32 [[SUB5]], i32* [[DOTCAPTURE_EXPR_3]], align 4
7553 // CHECK7-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
7554 // CHECK7-NEXT:    store i32 [[TMP5]], i32* [[I]], align 4
7555 // CHECK7-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
7556 // CHECK7-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
7557 // CHECK7-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]]
7558 // CHECK7-NEXT:    br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
7559 // CHECK7:       omp.precond.then:
7560 // CHECK7-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
7561 // CHECK7-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
7562 // CHECK7-NEXT:    store i32 [[TMP8]], i32* [[DOTOMP_UB]], align 4
7563 // CHECK7-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
7564 // CHECK7-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
7565 // CHECK7-NEXT:    [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
7566 // CHECK7-NEXT:    [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
7567 // CHECK7-NEXT:    call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
7568 // CHECK7-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
7569 // CHECK7-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
7570 // CHECK7-NEXT:    [[CMP7:%.*]] = icmp ugt i32 [[TMP11]], [[TMP12]]
7571 // CHECK7-NEXT:    br i1 [[CMP7]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
7572 // CHECK7:       cond.true:
7573 // CHECK7-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
7574 // CHECK7-NEXT:    br label [[COND_END:%.*]]
7575 // CHECK7:       cond.false:
7576 // CHECK7-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
7577 // CHECK7-NEXT:    br label [[COND_END]]
7578 // CHECK7:       cond.end:
7579 // CHECK7-NEXT:    [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ]
7580 // CHECK7-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
7581 // CHECK7-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
7582 // CHECK7-NEXT:    store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4
7583 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
7584 // CHECK7:       omp.inner.for.cond:
7585 // CHECK7-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !45
7586 // CHECK7-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !45
7587 // CHECK7-NEXT:    [[ADD8:%.*]] = add i32 [[TMP17]], 1
7588 // CHECK7-NEXT:    [[CMP9:%.*]] = icmp ult i32 [[TMP16]], [[ADD8]]
7589 // CHECK7-NEXT:    br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
7590 // CHECK7:       omp.inner.for.body:
7591 // CHECK7-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group !45
7592 // CHECK7-NEXT:    [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !45
7593 // CHECK7-NEXT:    [[MUL:%.*]] = mul i32 [[TMP19]], 1
7594 // CHECK7-NEXT:    [[ADD10:%.*]] = add i32 [[TMP18]], [[MUL]]
7595 // CHECK7-NEXT:    store i32 [[ADD10]], i32* [[I6]], align 4, !llvm.access.group !45
7596 // CHECK7-NEXT:    [[TMP20:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !45
7597 // CHECK7-NEXT:    [[ADD11:%.*]] = add nsw i32 [[TMP20]], 1
7598 // CHECK7-NEXT:    store i32 [[ADD11]], i32* [[A_ADDR]], align 4, !llvm.access.group !45
7599 // CHECK7-NEXT:    [[TMP21:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !45
7600 // CHECK7-NEXT:    [[CONV12:%.*]] = sext i16 [[TMP21]] to i32
7601 // CHECK7-NEXT:    [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1
7602 // CHECK7-NEXT:    [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16
7603 // CHECK7-NEXT:    store i16 [[CONV14]], i16* [[CONV]], align 2, !llvm.access.group !45
7604 // CHECK7-NEXT:    [[TMP22:%.*]] = load i8, i8* [[CONV1]], align 1, !llvm.access.group !45
7605 // CHECK7-NEXT:    [[CONV15:%.*]] = sext i8 [[TMP22]] to i32
7606 // CHECK7-NEXT:    [[ADD16:%.*]] = add nsw i32 [[CONV15]], 1
7607 // CHECK7-NEXT:    [[CONV17:%.*]] = trunc i32 [[ADD16]] to i8
7608 // CHECK7-NEXT:    store i8 [[CONV17]], i8* [[CONV1]], align 1, !llvm.access.group !45
7609 // CHECK7-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
7610 // CHECK7-NEXT:    [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !45
7611 // CHECK7-NEXT:    [[ADD18:%.*]] = add nsw i32 [[TMP23]], 1
7612 // CHECK7-NEXT:    store i32 [[ADD18]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !45
7613 // CHECK7-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
7614 // CHECK7:       omp.body.continue:
7615 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
7616 // CHECK7:       omp.inner.for.inc:
7617 // CHECK7-NEXT:    [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !45
7618 // CHECK7-NEXT:    [[ADD19:%.*]] = add i32 [[TMP24]], 1
7619 // CHECK7-NEXT:    store i32 [[ADD19]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !45
7620 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP46:![0-9]+]]
7621 // CHECK7:       omp.inner.for.end:
7622 // CHECK7-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
7623 // CHECK7:       omp.loop.exit:
7624 // CHECK7-NEXT:    [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
7625 // CHECK7-NEXT:    [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4
7626 // CHECK7-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]])
7627 // CHECK7-NEXT:    [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
7628 // CHECK7-NEXT:    [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0
7629 // CHECK7-NEXT:    br i1 [[TMP28]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
7630 // CHECK7:       .omp.final.then:
7631 // CHECK7-NEXT:    [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
7632 // CHECK7-NEXT:    [[TMP30:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
7633 // CHECK7-NEXT:    [[TMP31:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
7634 // CHECK7-NEXT:    [[SUB20:%.*]] = sub i32 [[TMP30]], [[TMP31]]
7635 // CHECK7-NEXT:    [[SUB21:%.*]] = sub i32 [[SUB20]], 1
7636 // CHECK7-NEXT:    [[ADD22:%.*]] = add i32 [[SUB21]], 1
7637 // CHECK7-NEXT:    [[DIV23:%.*]] = udiv i32 [[ADD22]], 1
7638 // CHECK7-NEXT:    [[MUL24:%.*]] = mul i32 [[DIV23]], 1
7639 // CHECK7-NEXT:    [[ADD25:%.*]] = add i32 [[TMP29]], [[MUL24]]
7640 // CHECK7-NEXT:    store i32 [[ADD25]], i32* [[I6]], align 4
7641 // CHECK7-NEXT:    br label [[DOTOMP_FINAL_DONE]]
7642 // CHECK7:       .omp.final.done:
7643 // CHECK7-NEXT:    br label [[OMP_PRECOND_END]]
7644 // CHECK7:       omp.precond.end:
7645 // CHECK7-NEXT:    ret void
7646 //
7647 //
7648 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180
7649 // CHECK7-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
7650 // CHECK7-NEXT:  entry:
7651 // CHECK7-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
7652 // CHECK7-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
7653 // CHECK7-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
7654 // CHECK7-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
7655 // CHECK7-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
7656 // CHECK7-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
7657 // CHECK7-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
7658 // CHECK7-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
7659 // CHECK7-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
7660 // CHECK7-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
7661 // CHECK7-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
7662 // CHECK7-NEXT:    store i32 [[TMP1]], i32* [[A_CASTED]], align 4
7663 // CHECK7-NEXT:    [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
7664 // CHECK7-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
7665 // CHECK7-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
7666 // CHECK7-NEXT:    store i16 [[TMP3]], i16* [[CONV1]], align 2
7667 // CHECK7-NEXT:    [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
7668 // CHECK7-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..18 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]])
7669 // CHECK7-NEXT:    ret void
7670 //
7671 //
7672 // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..18
7673 // CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] {
7674 // CHECK7-NEXT:  entry:
7675 // CHECK7-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
7676 // CHECK7-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
7677 // CHECK7-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
7678 // CHECK7-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
7679 // CHECK7-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
7680 // CHECK7-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
7681 // CHECK7-NEXT:    [[TMP:%.*]] = alloca i32, align 4
7682 // CHECK7-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
7683 // CHECK7-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
7684 // CHECK7-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
7685 // CHECK7-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
7686 // CHECK7-NEXT:    [[I:%.*]] = alloca i32, align 4
7687 // CHECK7-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
7688 // CHECK7-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
7689 // CHECK7-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
7690 // CHECK7-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
7691 // CHECK7-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
7692 // CHECK7-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
7693 // CHECK7-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
7694 // CHECK7-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
7695 // CHECK7-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
7696 // CHECK7-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
7697 // CHECK7-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
7698 // CHECK7-NEXT:    [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
7699 // CHECK7-NEXT:    [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
7700 // CHECK7-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
7701 // CHECK7-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
7702 // CHECK7-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9
7703 // CHECK7-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
7704 // CHECK7:       cond.true:
7705 // CHECK7-NEXT:    br label [[COND_END:%.*]]
7706 // CHECK7:       cond.false:
7707 // CHECK7-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
7708 // CHECK7-NEXT:    br label [[COND_END]]
7709 // CHECK7:       cond.end:
7710 // CHECK7-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
7711 // CHECK7-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
7712 // CHECK7-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
7713 // CHECK7-NEXT:    store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
7714 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
7715 // CHECK7:       omp.inner.for.cond:
7716 // CHECK7-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !48
7717 // CHECK7-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !48
7718 // CHECK7-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
7719 // CHECK7-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
7720 // CHECK7:       omp.inner.for.body:
7721 // CHECK7-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !48
7722 // CHECK7-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
7723 // CHECK7-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
7724 // CHECK7-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !48
7725 // CHECK7-NEXT:    [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !48
7726 // CHECK7-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
7727 // CHECK7-NEXT:    store i32 [[ADD2]], i32* [[A_ADDR]], align 4, !llvm.access.group !48
7728 // CHECK7-NEXT:    [[TMP10:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !48
7729 // CHECK7-NEXT:    [[CONV3:%.*]] = sext i16 [[TMP10]] to i32
7730 // CHECK7-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
7731 // CHECK7-NEXT:    [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
7732 // CHECK7-NEXT:    store i16 [[CONV5]], i16* [[CONV]], align 2, !llvm.access.group !48
7733 // CHECK7-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
7734 // CHECK7-NEXT:    [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !48
7735 // CHECK7-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1
7736 // CHECK7-NEXT:    store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !48
7737 // CHECK7-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
7738 // CHECK7:       omp.body.continue:
7739 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
7740 // CHECK7:       omp.inner.for.inc:
7741 // CHECK7-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !48
7742 // CHECK7-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP12]], 1
7743 // CHECK7-NEXT:    store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !48
7744 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP49:![0-9]+]]
7745 // CHECK7:       omp.inner.for.end:
7746 // CHECK7-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
7747 // CHECK7:       omp.loop.exit:
7748 // CHECK7-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
7749 // CHECK7-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
7750 // CHECK7-NEXT:    [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
7751 // CHECK7-NEXT:    br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
7752 // CHECK7:       .omp.final.then:
7753 // CHECK7-NEXT:    store i32 10, i32* [[I]], align 4
7754 // CHECK7-NEXT:    br label [[DOTOMP_FINAL_DONE]]
7755 // CHECK7:       .omp.final.done:
7756 // CHECK7-NEXT:    ret void
7757 //
7758 //
7759 // CHECK7-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
7760 // CHECK7-SAME: () #[[ATTR5]] {
7761 // CHECK7-NEXT:  entry:
7762 // CHECK7-NEXT:    call void @__tgt_register_requires(i64 1)
7763 // CHECK7-NEXT:    ret void
7764 //
7765 //
7766 // CHECK9-LABEL: define {{[^@]+}}@_Z3fooi
7767 // CHECK9-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0:[0-9]+]] {
7768 // CHECK9-NEXT:  entry:
7769 // CHECK9-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
7770 // CHECK9-NEXT:    [[A:%.*]] = alloca i32, align 4
7771 // CHECK9-NEXT:    [[AA:%.*]] = alloca i16, align 2
7772 // CHECK9-NEXT:    [[B:%.*]] = alloca [10 x float], align 4
7773 // CHECK9-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 8
7774 // CHECK9-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
7775 // CHECK9-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 8
7776 // CHECK9-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i64, align 8
7777 // CHECK9-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8
7778 // CHECK9-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
7779 // CHECK9-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
7780 // CHECK9-NEXT:    [[TMP:%.*]] = alloca i32, align 4
7781 // CHECK9-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
7782 // CHECK9-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
7783 // CHECK9-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
7784 // CHECK9-NEXT:    [[I:%.*]] = alloca i32, align 4
7785 // CHECK9-NEXT:    [[_TMP4:%.*]] = alloca i32, align 4
7786 // CHECK9-NEXT:    [[DOTOMP_LB5:%.*]] = alloca i32, align 4
7787 // CHECK9-NEXT:    [[DOTOMP_UB6:%.*]] = alloca i32, align 4
7788 // CHECK9-NEXT:    [[DOTOMP_IV7:%.*]] = alloca i32, align 4
7789 // CHECK9-NEXT:    [[DOTLINEAR_START:%.*]] = alloca i32, align 4
7790 // CHECK9-NEXT:    [[A8:%.*]] = alloca i32, align 4
7791 // CHECK9-NEXT:    [[A9:%.*]] = alloca i32, align 4
7792 // CHECK9-NEXT:    [[_TMP20:%.*]] = alloca i32, align 4
7793 // CHECK9-NEXT:    [[DOTOMP_LB21:%.*]] = alloca i32, align 4
7794 // CHECK9-NEXT:    [[DOTOMP_UB22:%.*]] = alloca i32, align 4
7795 // CHECK9-NEXT:    [[DOTOMP_IV23:%.*]] = alloca i32, align 4
7796 // CHECK9-NEXT:    [[I24:%.*]] = alloca i32, align 4
7797 // CHECK9-NEXT:    [[_TMP36:%.*]] = alloca i32, align 4
7798 // CHECK9-NEXT:    [[DOTOMP_LB37:%.*]] = alloca i32, align 4
7799 // CHECK9-NEXT:    [[DOTOMP_UB38:%.*]] = alloca i32, align 4
7800 // CHECK9-NEXT:    [[DOTOMP_IV39:%.*]] = alloca i32, align 4
7801 // CHECK9-NEXT:    [[I40:%.*]] = alloca i32, align 4
7802 // CHECK9-NEXT:    [[_TMP54:%.*]] = alloca i32, align 4
7803 // CHECK9-NEXT:    [[DOTOMP_LB55:%.*]] = alloca i32, align 4
7804 // CHECK9-NEXT:    [[DOTOMP_UB56:%.*]] = alloca i32, align 4
7805 // CHECK9-NEXT:    [[DOTOMP_IV57:%.*]] = alloca i32, align 4
7806 // CHECK9-NEXT:    [[I58:%.*]] = alloca i32, align 4
7807 // CHECK9-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
7808 // CHECK9-NEXT:    store i32 0, i32* [[A]], align 4
7809 // CHECK9-NEXT:    store i16 0, i16* [[AA]], align 2
7810 // CHECK9-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
7811 // CHECK9-NEXT:    [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
7812 // CHECK9-NEXT:    [[TMP2:%.*]] = call i8* @llvm.stacksave()
7813 // CHECK9-NEXT:    store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8
7814 // CHECK9-NEXT:    [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4
7815 // CHECK9-NEXT:    store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8
7816 // CHECK9-NEXT:    [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
7817 // CHECK9-NEXT:    [[TMP4:%.*]] = zext i32 [[TMP3]] to i64
7818 // CHECK9-NEXT:    [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]]
7819 // CHECK9-NEXT:    [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8
7820 // CHECK9-NEXT:    store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8
7821 // CHECK9-NEXT:    [[TMP6:%.*]] = load i32, i32* [[A]], align 4
7822 // CHECK9-NEXT:    store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_]], align 4
7823 // CHECK9-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
7824 // CHECK9-NEXT:    store i32 [[TMP7]], i32* [[DOTCAPTURE_EXPR_2]], align 4
7825 // CHECK9-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
7826 // CHECK9-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
7827 // CHECK9-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
7828 // CHECK9-NEXT:    store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
7829 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
7830 // CHECK9:       omp.inner.for.cond:
7831 // CHECK9-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
7832 // CHECK9-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !2
7833 // CHECK9-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
7834 // CHECK9-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
7835 // CHECK9:       omp.inner.for.body:
7836 // CHECK9-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
7837 // CHECK9-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
7838 // CHECK9-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
7839 // CHECK9-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !2
7840 // CHECK9-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
7841 // CHECK9:       omp.body.continue:
7842 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
7843 // CHECK9:       omp.inner.for.inc:
7844 // CHECK9-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
7845 // CHECK9-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1
7846 // CHECK9-NEXT:    store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
7847 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]
7848 // CHECK9:       omp.inner.for.end:
7849 // CHECK9-NEXT:    store i32 10, i32* [[I]], align 4
7850 // CHECK9-NEXT:    store i32 0, i32* [[DOTOMP_LB5]], align 4
7851 // CHECK9-NEXT:    store i32 9, i32* [[DOTOMP_UB6]], align 4
7852 // CHECK9-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB5]], align 4
7853 // CHECK9-NEXT:    store i32 [[TMP13]], i32* [[DOTOMP_IV7]], align 4
7854 // CHECK9-NEXT:    [[TMP14:%.*]] = load i32, i32* [[A]], align 4
7855 // CHECK9-NEXT:    store i32 [[TMP14]], i32* [[DOTLINEAR_START]], align 4
7856 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND10:%.*]]
7857 // CHECK9:       omp.inner.for.cond10:
7858 // CHECK9-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV7]], align 4
7859 // CHECK9-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB6]], align 4
7860 // CHECK9-NEXT:    [[CMP11:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]]
7861 // CHECK9-NEXT:    br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY12:%.*]], label [[OMP_INNER_FOR_END19:%.*]]
7862 // CHECK9:       omp.inner.for.body12:
7863 // CHECK9-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV7]], align 4
7864 // CHECK9-NEXT:    [[MUL13:%.*]] = mul nsw i32 [[TMP17]], 1
7865 // CHECK9-NEXT:    [[ADD14:%.*]] = add nsw i32 0, [[MUL13]]
7866 // CHECK9-NEXT:    store i32 [[ADD14]], i32* [[A8]], align 4
7867 // CHECK9-NEXT:    [[TMP18:%.*]] = load i32, i32* [[A8]], align 4
7868 // CHECK9-NEXT:    [[ADD15:%.*]] = add nsw i32 [[TMP18]], 1
7869 // CHECK9-NEXT:    store i32 [[ADD15]], i32* [[A8]], align 4
7870 // CHECK9-NEXT:    br label [[OMP_BODY_CONTINUE16:%.*]]
7871 // CHECK9:       omp.body.continue16:
7872 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_INC17:%.*]]
7873 // CHECK9:       omp.inner.for.inc17:
7874 // CHECK9-NEXT:    [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV7]], align 4
7875 // CHECK9-NEXT:    [[ADD18:%.*]] = add nsw i32 [[TMP19]], 1
7876 // CHECK9-NEXT:    store i32 [[ADD18]], i32* [[DOTOMP_IV7]], align 4
7877 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND10]], !llvm.loop [[LOOP7:![0-9]+]]
7878 // CHECK9:       omp.inner.for.end19:
7879 // CHECK9-NEXT:    store i32 10, i32* [[A]], align 4
7880 // CHECK9-NEXT:    store i32 0, i32* [[DOTOMP_LB21]], align 4
7881 // CHECK9-NEXT:    store i32 9, i32* [[DOTOMP_UB22]], align 4
7882 // CHECK9-NEXT:    [[TMP20:%.*]] = load i32, i32* [[DOTOMP_LB21]], align 4
7883 // CHECK9-NEXT:    store i32 [[TMP20]], i32* [[DOTOMP_IV23]], align 4
7884 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND25:%.*]]
7885 // CHECK9:       omp.inner.for.cond25:
7886 // CHECK9-NEXT:    [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV23]], align 4, !llvm.access.group !9
7887 // CHECK9-NEXT:    [[TMP22:%.*]] = load i32, i32* [[DOTOMP_UB22]], align 4, !llvm.access.group !9
7888 // CHECK9-NEXT:    [[CMP26:%.*]] = icmp sle i32 [[TMP21]], [[TMP22]]
7889 // CHECK9-NEXT:    br i1 [[CMP26]], label [[OMP_INNER_FOR_BODY27:%.*]], label [[OMP_INNER_FOR_END35:%.*]]
7890 // CHECK9:       omp.inner.for.body27:
7891 // CHECK9-NEXT:    [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV23]], align 4, !llvm.access.group !9
7892 // CHECK9-NEXT:    [[MUL28:%.*]] = mul nsw i32 [[TMP23]], 1
7893 // CHECK9-NEXT:    [[ADD29:%.*]] = add nsw i32 0, [[MUL28]]
7894 // CHECK9-NEXT:    store i32 [[ADD29]], i32* [[I24]], align 4, !llvm.access.group !9
7895 // CHECK9-NEXT:    [[TMP24:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !9
7896 // CHECK9-NEXT:    [[CONV:%.*]] = sext i16 [[TMP24]] to i32
7897 // CHECK9-NEXT:    [[ADD30:%.*]] = add nsw i32 [[CONV]], 1
7898 // CHECK9-NEXT:    [[CONV31:%.*]] = trunc i32 [[ADD30]] to i16
7899 // CHECK9-NEXT:    store i16 [[CONV31]], i16* [[AA]], align 2, !llvm.access.group !9
7900 // CHECK9-NEXT:    br label [[OMP_BODY_CONTINUE32:%.*]]
7901 // CHECK9:       omp.body.continue32:
7902 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_INC33:%.*]]
7903 // CHECK9:       omp.inner.for.inc33:
7904 // CHECK9-NEXT:    [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IV23]], align 4, !llvm.access.group !9
7905 // CHECK9-NEXT:    [[ADD34:%.*]] = add nsw i32 [[TMP25]], 1
7906 // CHECK9-NEXT:    store i32 [[ADD34]], i32* [[DOTOMP_IV23]], align 4, !llvm.access.group !9
7907 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND25]], !llvm.loop [[LOOP10:![0-9]+]]
7908 // CHECK9:       omp.inner.for.end35:
7909 // CHECK9-NEXT:    store i32 10, i32* [[I24]], align 4
7910 // CHECK9-NEXT:    store i32 0, i32* [[DOTOMP_LB37]], align 4
7911 // CHECK9-NEXT:    store i32 9, i32* [[DOTOMP_UB38]], align 4
7912 // CHECK9-NEXT:    [[TMP26:%.*]] = load i32, i32* [[DOTOMP_LB37]], align 4
7913 // CHECK9-NEXT:    store i32 [[TMP26]], i32* [[DOTOMP_IV39]], align 4
7914 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND41:%.*]]
7915 // CHECK9:       omp.inner.for.cond41:
7916 // CHECK9-NEXT:    [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV39]], align 4, !llvm.access.group !12
7917 // CHECK9-NEXT:    [[TMP28:%.*]] = load i32, i32* [[DOTOMP_UB38]], align 4, !llvm.access.group !12
7918 // CHECK9-NEXT:    [[CMP42:%.*]] = icmp sle i32 [[TMP27]], [[TMP28]]
7919 // CHECK9-NEXT:    br i1 [[CMP42]], label [[OMP_INNER_FOR_BODY43:%.*]], label [[OMP_INNER_FOR_END53:%.*]]
7920 // CHECK9:       omp.inner.for.body43:
7921 // CHECK9-NEXT:    [[TMP29:%.*]] = load i32, i32* [[DOTOMP_IV39]], align 4, !llvm.access.group !12
7922 // CHECK9-NEXT:    [[MUL44:%.*]] = mul nsw i32 [[TMP29]], 1
7923 // CHECK9-NEXT:    [[ADD45:%.*]] = add nsw i32 0, [[MUL44]]
7924 // CHECK9-NEXT:    store i32 [[ADD45]], i32* [[I40]], align 4, !llvm.access.group !12
7925 // CHECK9-NEXT:    [[TMP30:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !12
7926 // CHECK9-NEXT:    [[ADD46:%.*]] = add nsw i32 [[TMP30]], 1
7927 // CHECK9-NEXT:    store i32 [[ADD46]], i32* [[A]], align 4, !llvm.access.group !12
7928 // CHECK9-NEXT:    [[TMP31:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !12
7929 // CHECK9-NEXT:    [[CONV47:%.*]] = sext i16 [[TMP31]] to i32
7930 // CHECK9-NEXT:    [[ADD48:%.*]] = add nsw i32 [[CONV47]], 1
7931 // CHECK9-NEXT:    [[CONV49:%.*]] = trunc i32 [[ADD48]] to i16
7932 // CHECK9-NEXT:    store i16 [[CONV49]], i16* [[AA]], align 2, !llvm.access.group !12
7933 // CHECK9-NEXT:    br label [[OMP_BODY_CONTINUE50:%.*]]
7934 // CHECK9:       omp.body.continue50:
7935 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_INC51:%.*]]
7936 // CHECK9:       omp.inner.for.inc51:
7937 // CHECK9-NEXT:    [[TMP32:%.*]] = load i32, i32* [[DOTOMP_IV39]], align 4, !llvm.access.group !12
7938 // CHECK9-NEXT:    [[ADD52:%.*]] = add nsw i32 [[TMP32]], 1
7939 // CHECK9-NEXT:    store i32 [[ADD52]], i32* [[DOTOMP_IV39]], align 4, !llvm.access.group !12
7940 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND41]], !llvm.loop [[LOOP13:![0-9]+]]
7941 // CHECK9:       omp.inner.for.end53:
7942 // CHECK9-NEXT:    store i32 10, i32* [[I40]], align 4
7943 // CHECK9-NEXT:    store i32 0, i32* [[DOTOMP_LB55]], align 4
7944 // CHECK9-NEXT:    store i32 9, i32* [[DOTOMP_UB56]], align 4
7945 // CHECK9-NEXT:    [[TMP33:%.*]] = load i32, i32* [[DOTOMP_LB55]], align 4
7946 // CHECK9-NEXT:    store i32 [[TMP33]], i32* [[DOTOMP_IV57]], align 4
7947 // CHECK9-NEXT:    [[ARRAYDECAY:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 0
7948 // CHECK9-NEXT:    call void @llvm.assume(i1 true) [ "align"(float* [[ARRAYDECAY]], i64 16) ]
7949 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND59:%.*]]
7950 // CHECK9:       omp.inner.for.cond59:
7951 // CHECK9-NEXT:    [[TMP34:%.*]] = load i32, i32* [[DOTOMP_IV57]], align 4, !llvm.access.group !15
7952 // CHECK9-NEXT:    [[TMP35:%.*]] = load i32, i32* [[DOTOMP_UB56]], align 4, !llvm.access.group !15
7953 // CHECK9-NEXT:    [[CMP60:%.*]] = icmp sle i32 [[TMP34]], [[TMP35]]
7954 // CHECK9-NEXT:    br i1 [[CMP60]], label [[OMP_INNER_FOR_BODY61:%.*]], label [[OMP_INNER_FOR_END85:%.*]]
7955 // CHECK9:       omp.inner.for.body61:
7956 // CHECK9-NEXT:    [[TMP36:%.*]] = load i32, i32* [[DOTOMP_IV57]], align 4, !llvm.access.group !15
7957 // CHECK9-NEXT:    [[MUL62:%.*]] = mul nsw i32 [[TMP36]], 1
7958 // CHECK9-NEXT:    [[ADD63:%.*]] = add nsw i32 0, [[MUL62]]
7959 // CHECK9-NEXT:    store i32 [[ADD63]], i32* [[I58]], align 4, !llvm.access.group !15
7960 // CHECK9-NEXT:    [[TMP37:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !15
7961 // CHECK9-NEXT:    [[ADD64:%.*]] = add nsw i32 [[TMP37]], 1
7962 // CHECK9-NEXT:    store i32 [[ADD64]], i32* [[A]], align 4, !llvm.access.group !15
7963 // CHECK9-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2
7964 // CHECK9-NEXT:    [[TMP38:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !15
7965 // CHECK9-NEXT:    [[CONV65:%.*]] = fpext float [[TMP38]] to double
7966 // CHECK9-NEXT:    [[ADD66:%.*]] = fadd double [[CONV65]], 1.000000e+00
7967 // CHECK9-NEXT:    [[CONV67:%.*]] = fptrunc double [[ADD66]] to float
7968 // CHECK9-NEXT:    store float [[CONV67]], float* [[ARRAYIDX]], align 4, !llvm.access.group !15
7969 // CHECK9-NEXT:    [[ARRAYIDX68:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3
7970 // CHECK9-NEXT:    [[TMP39:%.*]] = load float, float* [[ARRAYIDX68]], align 4, !llvm.access.group !15
7971 // CHECK9-NEXT:    [[CONV69:%.*]] = fpext float [[TMP39]] to double
7972 // CHECK9-NEXT:    [[ADD70:%.*]] = fadd double [[CONV69]], 1.000000e+00
7973 // CHECK9-NEXT:    [[CONV71:%.*]] = fptrunc double [[ADD70]] to float
7974 // CHECK9-NEXT:    store float [[CONV71]], float* [[ARRAYIDX68]], align 4, !llvm.access.group !15
7975 // CHECK9-NEXT:    [[ARRAYIDX72:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1
7976 // CHECK9-NEXT:    [[ARRAYIDX73:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX72]], i64 0, i64 2
7977 // CHECK9-NEXT:    [[TMP40:%.*]] = load double, double* [[ARRAYIDX73]], align 8, !llvm.access.group !15
7978 // CHECK9-NEXT:    [[ADD74:%.*]] = fadd double [[TMP40]], 1.000000e+00
7979 // CHECK9-NEXT:    store double [[ADD74]], double* [[ARRAYIDX73]], align 8, !llvm.access.group !15
7980 // CHECK9-NEXT:    [[TMP41:%.*]] = mul nsw i64 1, [[TMP4]]
7981 // CHECK9-NEXT:    [[ARRAYIDX75:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP41]]
7982 // CHECK9-NEXT:    [[ARRAYIDX76:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX75]], i64 3
7983 // CHECK9-NEXT:    [[TMP42:%.*]] = load double, double* [[ARRAYIDX76]], align 8, !llvm.access.group !15
7984 // CHECK9-NEXT:    [[ADD77:%.*]] = fadd double [[TMP42]], 1.000000e+00
7985 // CHECK9-NEXT:    store double [[ADD77]], double* [[ARRAYIDX76]], align 8, !llvm.access.group !15
7986 // CHECK9-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0
7987 // CHECK9-NEXT:    [[TMP43:%.*]] = load i64, i64* [[X]], align 8, !llvm.access.group !15
7988 // CHECK9-NEXT:    [[ADD78:%.*]] = add nsw i64 [[TMP43]], 1
7989 // CHECK9-NEXT:    store i64 [[ADD78]], i64* [[X]], align 8, !llvm.access.group !15
7990 // CHECK9-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1
7991 // CHECK9-NEXT:    [[TMP44:%.*]] = load i8, i8* [[Y]], align 8, !llvm.access.group !15
7992 // CHECK9-NEXT:    [[CONV79:%.*]] = sext i8 [[TMP44]] to i32
7993 // CHECK9-NEXT:    [[ADD80:%.*]] = add nsw i32 [[CONV79]], 1
7994 // CHECK9-NEXT:    [[CONV81:%.*]] = trunc i32 [[ADD80]] to i8
7995 // CHECK9-NEXT:    store i8 [[CONV81]], i8* [[Y]], align 8, !llvm.access.group !15
7996 // CHECK9-NEXT:    br label [[OMP_BODY_CONTINUE82:%.*]]
7997 // CHECK9:       omp.body.continue82:
7998 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_INC83:%.*]]
7999 // CHECK9:       omp.inner.for.inc83:
8000 // CHECK9-NEXT:    [[TMP45:%.*]] = load i32, i32* [[DOTOMP_IV57]], align 4, !llvm.access.group !15
8001 // CHECK9-NEXT:    [[ADD84:%.*]] = add nsw i32 [[TMP45]], 1
8002 // CHECK9-NEXT:    store i32 [[ADD84]], i32* [[DOTOMP_IV57]], align 4, !llvm.access.group !15
8003 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND59]], !llvm.loop [[LOOP16:![0-9]+]]
8004 // CHECK9:       omp.inner.for.end85:
8005 // CHECK9-NEXT:    store i32 10, i32* [[I58]], align 4
8006 // CHECK9-NEXT:    [[TMP46:%.*]] = load i32, i32* [[A]], align 4
8007 // CHECK9-NEXT:    [[TMP47:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
8008 // CHECK9-NEXT:    call void @llvm.stackrestore(i8* [[TMP47]])
8009 // CHECK9-NEXT:    ret i32 [[TMP46]]
8010 //
8011 //
8012 // CHECK9-LABEL: define {{[^@]+}}@_Z3bari
8013 // CHECK9-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {
8014 // CHECK9-NEXT:  entry:
8015 // CHECK9-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
8016 // CHECK9-NEXT:    [[A:%.*]] = alloca i32, align 4
8017 // CHECK9-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8
8018 // CHECK9-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
8019 // CHECK9-NEXT:    store i32 0, i32* [[A]], align 4
8020 // CHECK9-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
8021 // CHECK9-NEXT:    [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]])
8022 // CHECK9-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
8023 // CHECK9-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
8024 // CHECK9-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
8025 // CHECK9-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
8026 // CHECK9-NEXT:    [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP2]])
8027 // CHECK9-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
8028 // CHECK9-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
8029 // CHECK9-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
8030 // CHECK9-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
8031 // CHECK9-NEXT:    [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]])
8032 // CHECK9-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
8033 // CHECK9-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
8034 // CHECK9-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
8035 // CHECK9-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
8036 // CHECK9-NEXT:    [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]])
8037 // CHECK9-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
8038 // CHECK9-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
8039 // CHECK9-NEXT:    store i32 [[ADD6]], i32* [[A]], align 4
8040 // CHECK9-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
8041 // CHECK9-NEXT:    ret i32 [[TMP8]]
8042 //
8043 //
8044 // CHECK9-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
8045 // CHECK9-SAME: (%struct.S1* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 {
8046 // CHECK9-NEXT:  entry:
8047 // CHECK9-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
8048 // CHECK9-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
8049 // CHECK9-NEXT:    [[B:%.*]] = alloca i32, align 4
8050 // CHECK9-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 8
8051 // CHECK9-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
8052 // CHECK9-NEXT:    [[TMP:%.*]] = alloca i32, align 4
8053 // CHECK9-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
8054 // CHECK9-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
8055 // CHECK9-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
8056 // CHECK9-NEXT:    [[I:%.*]] = alloca i32, align 4
8057 // CHECK9-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
8058 // CHECK9-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
8059 // CHECK9-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
8060 // CHECK9-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
8061 // CHECK9-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
8062 // CHECK9-NEXT:    store i32 [[ADD]], i32* [[B]], align 4
8063 // CHECK9-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
8064 // CHECK9-NEXT:    [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
8065 // CHECK9-NEXT:    [[TMP3:%.*]] = call i8* @llvm.stacksave()
8066 // CHECK9-NEXT:    store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8
8067 // CHECK9-NEXT:    [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]
8068 // CHECK9-NEXT:    [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2
8069 // CHECK9-NEXT:    store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8
8070 // CHECK9-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
8071 // CHECK9-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
8072 // CHECK9-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
8073 // CHECK9-NEXT:    store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
8074 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
8075 // CHECK9:       omp.inner.for.cond:
8076 // CHECK9-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
8077 // CHECK9-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !18
8078 // CHECK9-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
8079 // CHECK9-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
8080 // CHECK9:       omp.inner.for.body:
8081 // CHECK9-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
8082 // CHECK9-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
8083 // CHECK9-NEXT:    [[ADD2:%.*]] = add nsw i32 0, [[MUL]]
8084 // CHECK9-NEXT:    store i32 [[ADD2]], i32* [[I]], align 4, !llvm.access.group !18
8085 // CHECK9-NEXT:    [[TMP9:%.*]] = load i32, i32* [[B]], align 4, !llvm.access.group !18
8086 // CHECK9-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP9]] to double
8087 // CHECK9-NEXT:    [[ADD3:%.*]] = fadd double [[CONV]], 1.500000e+00
8088 // CHECK9-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
8089 // CHECK9-NEXT:    store double [[ADD3]], double* [[A]], align 8, !llvm.access.group !18
8090 // CHECK9-NEXT:    [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
8091 // CHECK9-NEXT:    [[TMP10:%.*]] = load double, double* [[A4]], align 8, !llvm.access.group !18
8092 // CHECK9-NEXT:    [[INC:%.*]] = fadd double [[TMP10]], 1.000000e+00
8093 // CHECK9-NEXT:    store double [[INC]], double* [[A4]], align 8, !llvm.access.group !18
8094 // CHECK9-NEXT:    [[CONV5:%.*]] = fptosi double [[INC]] to i16
8095 // CHECK9-NEXT:    [[TMP11:%.*]] = mul nsw i64 1, [[TMP2]]
8096 // CHECK9-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP11]]
8097 // CHECK9-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
8098 // CHECK9-NEXT:    store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2, !llvm.access.group !18
8099 // CHECK9-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
8100 // CHECK9:       omp.body.continue:
8101 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
8102 // CHECK9:       omp.inner.for.inc:
8103 // CHECK9-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
8104 // CHECK9-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP12]], 1
8105 // CHECK9-NEXT:    store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
8106 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]
8107 // CHECK9:       omp.inner.for.end:
8108 // CHECK9-NEXT:    store i32 10, i32* [[I]], align 4
8109 // CHECK9-NEXT:    [[TMP13:%.*]] = mul nsw i64 1, [[TMP2]]
8110 // CHECK9-NEXT:    [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP13]]
8111 // CHECK9-NEXT:    [[ARRAYIDX9:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX8]], i64 1
8112 // CHECK9-NEXT:    [[TMP14:%.*]] = load i16, i16* [[ARRAYIDX9]], align 2
8113 // CHECK9-NEXT:    [[CONV10:%.*]] = sext i16 [[TMP14]] to i32
8114 // CHECK9-NEXT:    [[TMP15:%.*]] = load i32, i32* [[B]], align 4
8115 // CHECK9-NEXT:    [[ADD11:%.*]] = add nsw i32 [[CONV10]], [[TMP15]]
8116 // CHECK9-NEXT:    [[TMP16:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
8117 // CHECK9-NEXT:    call void @llvm.stackrestore(i8* [[TMP16]])
8118 // CHECK9-NEXT:    ret i32 [[ADD11]]
8119 //
8120 //
8121 // CHECK9-LABEL: define {{[^@]+}}@_ZL7fstatici
8122 // CHECK9-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {
8123 // CHECK9-NEXT:  entry:
8124 // CHECK9-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
8125 // CHECK9-NEXT:    [[A:%.*]] = alloca i32, align 4
8126 // CHECK9-NEXT:    [[AA:%.*]] = alloca i16, align 2
8127 // CHECK9-NEXT:    [[AAA:%.*]] = alloca i8, align 1
8128 // CHECK9-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
8129 // CHECK9-NEXT:    [[TMP:%.*]] = alloca i32, align 4
8130 // CHECK9-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
8131 // CHECK9-NEXT:    [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
8132 // CHECK9-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
8133 // CHECK9-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
8134 // CHECK9-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
8135 // CHECK9-NEXT:    [[I:%.*]] = alloca i32, align 4
8136 // CHECK9-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
8137 // CHECK9-NEXT:    [[I5:%.*]] = alloca i32, align 4
8138 // CHECK9-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
8139 // CHECK9-NEXT:    store i32 0, i32* [[A]], align 4
8140 // CHECK9-NEXT:    store i16 0, i16* [[AA]], align 2
8141 // CHECK9-NEXT:    store i8 0, i8* [[AAA]], align 1
8142 // CHECK9-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
8143 // CHECK9-NEXT:    store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4
8144 // CHECK9-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
8145 // CHECK9-NEXT:    store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_1]], align 4
8146 // CHECK9-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
8147 // CHECK9-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
8148 // CHECK9-NEXT:    [[SUB:%.*]] = sub i32 [[TMP2]], [[TMP3]]
8149 // CHECK9-NEXT:    [[SUB3:%.*]] = sub i32 [[SUB]], 1
8150 // CHECK9-NEXT:    [[ADD:%.*]] = add i32 [[SUB3]], 1
8151 // CHECK9-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], 1
8152 // CHECK9-NEXT:    [[SUB4:%.*]] = sub i32 [[DIV]], 1
8153 // CHECK9-NEXT:    store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_2]], align 4
8154 // CHECK9-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
8155 // CHECK9-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
8156 // CHECK9-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_UB]], align 4
8157 // CHECK9-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
8158 // CHECK9-NEXT:    store i32 [[TMP5]], i32* [[I]], align 4
8159 // CHECK9-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
8160 // CHECK9-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
8161 // CHECK9-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]]
8162 // CHECK9-NEXT:    br i1 [[CMP]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END:%.*]]
8163 // CHECK9:       simd.if.then:
8164 // CHECK9-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
8165 // CHECK9-NEXT:    store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
8166 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
8167 // CHECK9:       omp.inner.for.cond:
8168 // CHECK9-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
8169 // CHECK9-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !21
8170 // CHECK9-NEXT:    [[ADD6:%.*]] = add i32 [[TMP10]], 1
8171 // CHECK9-NEXT:    [[CMP7:%.*]] = icmp ult i32 [[TMP9]], [[ADD6]]
8172 // CHECK9-NEXT:    br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
8173 // CHECK9:       omp.inner.for.body:
8174 // CHECK9-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group !21
8175 // CHECK9-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
8176 // CHECK9-NEXT:    [[MUL:%.*]] = mul i32 [[TMP12]], 1
8177 // CHECK9-NEXT:    [[ADD8:%.*]] = add i32 [[TMP11]], [[MUL]]
8178 // CHECK9-NEXT:    store i32 [[ADD8]], i32* [[I5]], align 4, !llvm.access.group !21
8179 // CHECK9-NEXT:    [[TMP13:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !21
8180 // CHECK9-NEXT:    [[ADD9:%.*]] = add nsw i32 [[TMP13]], 1
8181 // CHECK9-NEXT:    store i32 [[ADD9]], i32* [[A]], align 4, !llvm.access.group !21
8182 // CHECK9-NEXT:    [[TMP14:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !21
8183 // CHECK9-NEXT:    [[CONV:%.*]] = sext i16 [[TMP14]] to i32
8184 // CHECK9-NEXT:    [[ADD10:%.*]] = add nsw i32 [[CONV]], 1
8185 // CHECK9-NEXT:    [[CONV11:%.*]] = trunc i32 [[ADD10]] to i16
8186 // CHECK9-NEXT:    store i16 [[CONV11]], i16* [[AA]], align 2, !llvm.access.group !21
8187 // CHECK9-NEXT:    [[TMP15:%.*]] = load i8, i8* [[AAA]], align 1, !llvm.access.group !21
8188 // CHECK9-NEXT:    [[CONV12:%.*]] = sext i8 [[TMP15]] to i32
8189 // CHECK9-NEXT:    [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1
8190 // CHECK9-NEXT:    [[CONV14:%.*]] = trunc i32 [[ADD13]] to i8
8191 // CHECK9-NEXT:    store i8 [[CONV14]], i8* [[AAA]], align 1, !llvm.access.group !21
8192 // CHECK9-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2
8193 // CHECK9-NEXT:    [[TMP16:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !21
8194 // CHECK9-NEXT:    [[ADD15:%.*]] = add nsw i32 [[TMP16]], 1
8195 // CHECK9-NEXT:    store i32 [[ADD15]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !21
8196 // CHECK9-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
8197 // CHECK9:       omp.body.continue:
8198 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
8199 // CHECK9:       omp.inner.for.inc:
8200 // CHECK9-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
8201 // CHECK9-NEXT:    [[ADD16:%.*]] = add i32 [[TMP17]], 1
8202 // CHECK9-NEXT:    store i32 [[ADD16]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
8203 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]]
8204 // CHECK9:       omp.inner.for.end:
8205 // CHECK9-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
8206 // CHECK9-NEXT:    [[TMP19:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
8207 // CHECK9-NEXT:    [[TMP20:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
8208 // CHECK9-NEXT:    [[SUB17:%.*]] = sub i32 [[TMP19]], [[TMP20]]
8209 // CHECK9-NEXT:    [[SUB18:%.*]] = sub i32 [[SUB17]], 1
8210 // CHECK9-NEXT:    [[ADD19:%.*]] = add i32 [[SUB18]], 1
8211 // CHECK9-NEXT:    [[DIV20:%.*]] = udiv i32 [[ADD19]], 1
8212 // CHECK9-NEXT:    [[MUL21:%.*]] = mul i32 [[DIV20]], 1
8213 // CHECK9-NEXT:    [[ADD22:%.*]] = add i32 [[TMP18]], [[MUL21]]
8214 // CHECK9-NEXT:    store i32 [[ADD22]], i32* [[I5]], align 4
8215 // CHECK9-NEXT:    br label [[SIMD_IF_END]]
8216 // CHECK9:       simd.if.end:
8217 // CHECK9-NEXT:    [[TMP21:%.*]] = load i32, i32* [[A]], align 4
8218 // CHECK9-NEXT:    ret i32 [[TMP21]]
8219 //
8220 //
8221 // CHECK9-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
8222 // CHECK9-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat {
8223 // CHECK9-NEXT:  entry:
8224 // CHECK9-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
8225 // CHECK9-NEXT:    [[A:%.*]] = alloca i32, align 4
8226 // CHECK9-NEXT:    [[AA:%.*]] = alloca i16, align 2
8227 // CHECK9-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
8228 // CHECK9-NEXT:    [[TMP:%.*]] = alloca i32, align 4
8229 // CHECK9-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
8230 // CHECK9-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
8231 // CHECK9-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
8232 // CHECK9-NEXT:    [[I:%.*]] = alloca i32, align 4
8233 // CHECK9-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
8234 // CHECK9-NEXT:    store i32 0, i32* [[A]], align 4
8235 // CHECK9-NEXT:    store i16 0, i16* [[AA]], align 2
8236 // CHECK9-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
8237 // CHECK9-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
8238 // CHECK9-NEXT:    [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
8239 // CHECK9-NEXT:    store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4
8240 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
8241 // CHECK9:       omp.inner.for.cond:
8242 // CHECK9-NEXT:    [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
8243 // CHECK9-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !24
8244 // CHECK9-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
8245 // CHECK9-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
8246 // CHECK9:       omp.inner.for.body:
8247 // CHECK9-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
8248 // CHECK9-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1
8249 // CHECK9-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
8250 // CHECK9-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !24
8251 // CHECK9-NEXT:    [[TMP4:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !24
8252 // CHECK9-NEXT:    [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1
8253 // CHECK9-NEXT:    store i32 [[ADD1]], i32* [[A]], align 4, !llvm.access.group !24
8254 // CHECK9-NEXT:    [[TMP5:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !24
8255 // CHECK9-NEXT:    [[CONV:%.*]] = sext i16 [[TMP5]] to i32
8256 // CHECK9-NEXT:    [[ADD2:%.*]] = add nsw i32 [[CONV]], 1
8257 // CHECK9-NEXT:    [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
8258 // CHECK9-NEXT:    store i16 [[CONV3]], i16* [[AA]], align 2, !llvm.access.group !24
8259 // CHECK9-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2
8260 // CHECK9-NEXT:    [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !24
8261 // CHECK9-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP6]], 1
8262 // CHECK9-NEXT:    store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !24
8263 // CHECK9-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
8264 // CHECK9:       omp.body.continue:
8265 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
8266 // CHECK9:       omp.inner.for.inc:
8267 // CHECK9-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
8268 // CHECK9-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP7]], 1
8269 // CHECK9-NEXT:    store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
8270 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]]
8271 // CHECK9:       omp.inner.for.end:
8272 // CHECK9-NEXT:    store i32 10, i32* [[I]], align 4
8273 // CHECK9-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
8274 // CHECK9-NEXT:    ret i32 [[TMP8]]
8275 //
8276 //
8277 // CHECK11-LABEL: define {{[^@]+}}@_Z3fooi
8278 // CHECK11-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0:[0-9]+]] {
8279 // CHECK11-NEXT:  entry:
8280 // CHECK11-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
8281 // CHECK11-NEXT:    [[A:%.*]] = alloca i32, align 4
8282 // CHECK11-NEXT:    [[AA:%.*]] = alloca i16, align 2
8283 // CHECK11-NEXT:    [[B:%.*]] = alloca [10 x float], align 4
8284 // CHECK11-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 4
8285 // CHECK11-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 4
8286 // CHECK11-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 8
8287 // CHECK11-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i32, align 4
8288 // CHECK11-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4
8289 // CHECK11-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
8290 // CHECK11-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
8291 // CHECK11-NEXT:    [[TMP:%.*]] = alloca i32, align 4
8292 // CHECK11-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
8293 // CHECK11-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
8294 // CHECK11-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
8295 // CHECK11-NEXT:    [[I:%.*]] = alloca i32, align 4
8296 // CHECK11-NEXT:    [[_TMP4:%.*]] = alloca i32, align 4
8297 // CHECK11-NEXT:    [[DOTOMP_LB5:%.*]] = alloca i32, align 4
8298 // CHECK11-NEXT:    [[DOTOMP_UB6:%.*]] = alloca i32, align 4
8299 // CHECK11-NEXT:    [[DOTOMP_IV7:%.*]] = alloca i32, align 4
8300 // CHECK11-NEXT:    [[DOTLINEAR_START:%.*]] = alloca i32, align 4
8301 // CHECK11-NEXT:    [[A8:%.*]] = alloca i32, align 4
8302 // CHECK11-NEXT:    [[A9:%.*]] = alloca i32, align 4
8303 // CHECK11-NEXT:    [[_TMP20:%.*]] = alloca i32, align 4
8304 // CHECK11-NEXT:    [[DOTOMP_LB21:%.*]] = alloca i32, align 4
8305 // CHECK11-NEXT:    [[DOTOMP_UB22:%.*]] = alloca i32, align 4
8306 // CHECK11-NEXT:    [[DOTOMP_IV23:%.*]] = alloca i32, align 4
8307 // CHECK11-NEXT:    [[I24:%.*]] = alloca i32, align 4
8308 // CHECK11-NEXT:    [[_TMP36:%.*]] = alloca i32, align 4
8309 // CHECK11-NEXT:    [[DOTOMP_LB37:%.*]] = alloca i32, align 4
8310 // CHECK11-NEXT:    [[DOTOMP_UB38:%.*]] = alloca i32, align 4
8311 // CHECK11-NEXT:    [[DOTOMP_IV39:%.*]] = alloca i32, align 4
8312 // CHECK11-NEXT:    [[I40:%.*]] = alloca i32, align 4
8313 // CHECK11-NEXT:    [[_TMP54:%.*]] = alloca i32, align 4
8314 // CHECK11-NEXT:    [[DOTOMP_LB55:%.*]] = alloca i32, align 4
8315 // CHECK11-NEXT:    [[DOTOMP_UB56:%.*]] = alloca i32, align 4
8316 // CHECK11-NEXT:    [[DOTOMP_IV57:%.*]] = alloca i32, align 4
8317 // CHECK11-NEXT:    [[I58:%.*]] = alloca i32, align 4
8318 // CHECK11-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
8319 // CHECK11-NEXT:    store i32 0, i32* [[A]], align 4
8320 // CHECK11-NEXT:    store i16 0, i16* [[AA]], align 2
8321 // CHECK11-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
8322 // CHECK11-NEXT:    [[TMP1:%.*]] = call i8* @llvm.stacksave()
8323 // CHECK11-NEXT:    store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4
8324 // CHECK11-NEXT:    [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4
8325 // CHECK11-NEXT:    store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4
8326 // CHECK11-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
8327 // CHECK11-NEXT:    [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]]
8328 // CHECK11-NEXT:    [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8
8329 // CHECK11-NEXT:    store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4
8330 // CHECK11-NEXT:    [[TMP4:%.*]] = load i32, i32* [[A]], align 4
8331 // CHECK11-NEXT:    store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4
8332 // CHECK11-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
8333 // CHECK11-NEXT:    store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_2]], align 4
8334 // CHECK11-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
8335 // CHECK11-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
8336 // CHECK11-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
8337 // CHECK11-NEXT:    store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
8338 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
8339 // CHECK11:       omp.inner.for.cond:
8340 // CHECK11-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
8341 // CHECK11-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !3
8342 // CHECK11-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
8343 // CHECK11-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
8344 // CHECK11:       omp.inner.for.body:
8345 // CHECK11-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
8346 // CHECK11-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
8347 // CHECK11-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
8348 // CHECK11-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !3
8349 // CHECK11-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
8350 // CHECK11:       omp.body.continue:
8351 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
8352 // CHECK11:       omp.inner.for.inc:
8353 // CHECK11-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
8354 // CHECK11-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
8355 // CHECK11-NEXT:    store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
8356 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]
8357 // CHECK11:       omp.inner.for.end:
8358 // CHECK11-NEXT:    store i32 10, i32* [[I]], align 4
8359 // CHECK11-NEXT:    store i32 0, i32* [[DOTOMP_LB5]], align 4
8360 // CHECK11-NEXT:    store i32 9, i32* [[DOTOMP_UB6]], align 4
8361 // CHECK11-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_LB5]], align 4
8362 // CHECK11-NEXT:    store i32 [[TMP11]], i32* [[DOTOMP_IV7]], align 4
8363 // CHECK11-NEXT:    [[TMP12:%.*]] = load i32, i32* [[A]], align 4
8364 // CHECK11-NEXT:    store i32 [[TMP12]], i32* [[DOTLINEAR_START]], align 4
8365 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_COND10:%.*]]
8366 // CHECK11:       omp.inner.for.cond10:
8367 // CHECK11-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV7]], align 4
8368 // CHECK11-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB6]], align 4
8369 // CHECK11-NEXT:    [[CMP11:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
8370 // CHECK11-NEXT:    br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY12:%.*]], label [[OMP_INNER_FOR_END19:%.*]]
8371 // CHECK11:       omp.inner.for.body12:
8372 // CHECK11-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV7]], align 4
8373 // CHECK11-NEXT:    [[MUL13:%.*]] = mul nsw i32 [[TMP15]], 1
8374 // CHECK11-NEXT:    [[ADD14:%.*]] = add nsw i32 0, [[MUL13]]
8375 // CHECK11-NEXT:    store i32 [[ADD14]], i32* [[A8]], align 4
8376 // CHECK11-NEXT:    [[TMP16:%.*]] = load i32, i32* [[A8]], align 4
8377 // CHECK11-NEXT:    [[ADD15:%.*]] = add nsw i32 [[TMP16]], 1
8378 // CHECK11-NEXT:    store i32 [[ADD15]], i32* [[A8]], align 4
8379 // CHECK11-NEXT:    br label [[OMP_BODY_CONTINUE16:%.*]]
8380 // CHECK11:       omp.body.continue16:
8381 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_INC17:%.*]]
8382 // CHECK11:       omp.inner.for.inc17:
8383 // CHECK11-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV7]], align 4
8384 // CHECK11-NEXT:    [[ADD18:%.*]] = add nsw i32 [[TMP17]], 1
8385 // CHECK11-NEXT:    store i32 [[ADD18]], i32* [[DOTOMP_IV7]], align 4
8386 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_COND10]], !llvm.loop [[LOOP8:![0-9]+]]
8387 // CHECK11:       omp.inner.for.end19:
8388 // CHECK11-NEXT:    store i32 10, i32* [[A]], align 4
8389 // CHECK11-NEXT:    store i32 0, i32* [[DOTOMP_LB21]], align 4
8390 // CHECK11-NEXT:    store i32 9, i32* [[DOTOMP_UB22]], align 4
8391 // CHECK11-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTOMP_LB21]], align 4
8392 // CHECK11-NEXT:    store i32 [[TMP18]], i32* [[DOTOMP_IV23]], align 4
8393 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_COND25:%.*]]
8394 // CHECK11:       omp.inner.for.cond25:
8395 // CHECK11-NEXT:    [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV23]], align 4, !llvm.access.group !10
8396 // CHECK11-NEXT:    [[TMP20:%.*]] = load i32, i32* [[DOTOMP_UB22]], align 4, !llvm.access.group !10
8397 // CHECK11-NEXT:    [[CMP26:%.*]] = icmp sle i32 [[TMP19]], [[TMP20]]
8398 // CHECK11-NEXT:    br i1 [[CMP26]], label [[OMP_INNER_FOR_BODY27:%.*]], label [[OMP_INNER_FOR_END35:%.*]]
8399 // CHECK11:       omp.inner.for.body27:
8400 // CHECK11-NEXT:    [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV23]], align 4, !llvm.access.group !10
8401 // CHECK11-NEXT:    [[MUL28:%.*]] = mul nsw i32 [[TMP21]], 1
8402 // CHECK11-NEXT:    [[ADD29:%.*]] = add nsw i32 0, [[MUL28]]
8403 // CHECK11-NEXT:    store i32 [[ADD29]], i32* [[I24]], align 4, !llvm.access.group !10
8404 // CHECK11-NEXT:    [[TMP22:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !10
8405 // CHECK11-NEXT:    [[CONV:%.*]] = sext i16 [[TMP22]] to i32
8406 // CHECK11-NEXT:    [[ADD30:%.*]] = add nsw i32 [[CONV]], 1
8407 // CHECK11-NEXT:    [[CONV31:%.*]] = trunc i32 [[ADD30]] to i16
8408 // CHECK11-NEXT:    store i16 [[CONV31]], i16* [[AA]], align 2, !llvm.access.group !10
8409 // CHECK11-NEXT:    br label [[OMP_BODY_CONTINUE32:%.*]]
8410 // CHECK11:       omp.body.continue32:
8411 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_INC33:%.*]]
8412 // CHECK11:       omp.inner.for.inc33:
8413 // CHECK11-NEXT:    [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV23]], align 4, !llvm.access.group !10
8414 // CHECK11-NEXT:    [[ADD34:%.*]] = add nsw i32 [[TMP23]], 1
8415 // CHECK11-NEXT:    store i32 [[ADD34]], i32* [[DOTOMP_IV23]], align 4, !llvm.access.group !10
8416 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_COND25]], !llvm.loop [[LOOP11:![0-9]+]]
8417 // CHECK11:       omp.inner.for.end35:
8418 // CHECK11-NEXT:    store i32 10, i32* [[I24]], align 4
8419 // CHECK11-NEXT:    store i32 0, i32* [[DOTOMP_LB37]], align 4
8420 // CHECK11-NEXT:    store i32 9, i32* [[DOTOMP_UB38]], align 4
8421 // CHECK11-NEXT:    [[TMP24:%.*]] = load i32, i32* [[DOTOMP_LB37]], align 4
8422 // CHECK11-NEXT:    store i32 [[TMP24]], i32* [[DOTOMP_IV39]], align 4
8423 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_COND41:%.*]]
8424 // CHECK11:       omp.inner.for.cond41:
8425 // CHECK11-NEXT:    [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IV39]], align 4, !llvm.access.group !13
8426 // CHECK11-NEXT:    [[TMP26:%.*]] = load i32, i32* [[DOTOMP_UB38]], align 4, !llvm.access.group !13
8427 // CHECK11-NEXT:    [[CMP42:%.*]] = icmp sle i32 [[TMP25]], [[TMP26]]
8428 // CHECK11-NEXT:    br i1 [[CMP42]], label [[OMP_INNER_FOR_BODY43:%.*]], label [[OMP_INNER_FOR_END53:%.*]]
8429 // CHECK11:       omp.inner.for.body43:
8430 // CHECK11-NEXT:    [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV39]], align 4, !llvm.access.group !13
8431 // CHECK11-NEXT:    [[MUL44:%.*]] = mul nsw i32 [[TMP27]], 1
8432 // CHECK11-NEXT:    [[ADD45:%.*]] = add nsw i32 0, [[MUL44]]
8433 // CHECK11-NEXT:    store i32 [[ADD45]], i32* [[I40]], align 4, !llvm.access.group !13
8434 // CHECK11-NEXT:    [[TMP28:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !13
8435 // CHECK11-NEXT:    [[ADD46:%.*]] = add nsw i32 [[TMP28]], 1
8436 // CHECK11-NEXT:    store i32 [[ADD46]], i32* [[A]], align 4, !llvm.access.group !13
8437 // CHECK11-NEXT:    [[TMP29:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !13
8438 // CHECK11-NEXT:    [[CONV47:%.*]] = sext i16 [[TMP29]] to i32
8439 // CHECK11-NEXT:    [[ADD48:%.*]] = add nsw i32 [[CONV47]], 1
8440 // CHECK11-NEXT:    [[CONV49:%.*]] = trunc i32 [[ADD48]] to i16
8441 // CHECK11-NEXT:    store i16 [[CONV49]], i16* [[AA]], align 2, !llvm.access.group !13
8442 // CHECK11-NEXT:    br label [[OMP_BODY_CONTINUE50:%.*]]
8443 // CHECK11:       omp.body.continue50:
8444 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_INC51:%.*]]
8445 // CHECK11:       omp.inner.for.inc51:
8446 // CHECK11-NEXT:    [[TMP30:%.*]] = load i32, i32* [[DOTOMP_IV39]], align 4, !llvm.access.group !13
8447 // CHECK11-NEXT:    [[ADD52:%.*]] = add nsw i32 [[TMP30]], 1
8448 // CHECK11-NEXT:    store i32 [[ADD52]], i32* [[DOTOMP_IV39]], align 4, !llvm.access.group !13
8449 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_COND41]], !llvm.loop [[LOOP14:![0-9]+]]
8450 // CHECK11:       omp.inner.for.end53:
8451 // CHECK11-NEXT:    store i32 10, i32* [[I40]], align 4
8452 // CHECK11-NEXT:    store i32 0, i32* [[DOTOMP_LB55]], align 4
8453 // CHECK11-NEXT:    store i32 9, i32* [[DOTOMP_UB56]], align 4
8454 // CHECK11-NEXT:    [[TMP31:%.*]] = load i32, i32* [[DOTOMP_LB55]], align 4
8455 // CHECK11-NEXT:    store i32 [[TMP31]], i32* [[DOTOMP_IV57]], align 4
8456 // CHECK11-NEXT:    [[ARRAYDECAY:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 0
8457 // CHECK11-NEXT:    call void @llvm.assume(i1 true) [ "align"(float* [[ARRAYDECAY]], i32 16) ]
8458 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_COND59:%.*]]
8459 // CHECK11:       omp.inner.for.cond59:
8460 // CHECK11-NEXT:    [[TMP32:%.*]] = load i32, i32* [[DOTOMP_IV57]], align 4, !llvm.access.group !16
8461 // CHECK11-NEXT:    [[TMP33:%.*]] = load i32, i32* [[DOTOMP_UB56]], align 4, !llvm.access.group !16
8462 // CHECK11-NEXT:    [[CMP60:%.*]] = icmp sle i32 [[TMP32]], [[TMP33]]
8463 // CHECK11-NEXT:    br i1 [[CMP60]], label [[OMP_INNER_FOR_BODY61:%.*]], label [[OMP_INNER_FOR_END85:%.*]]
8464 // CHECK11:       omp.inner.for.body61:
8465 // CHECK11-NEXT:    [[TMP34:%.*]] = load i32, i32* [[DOTOMP_IV57]], align 4, !llvm.access.group !16
8466 // CHECK11-NEXT:    [[MUL62:%.*]] = mul nsw i32 [[TMP34]], 1
8467 // CHECK11-NEXT:    [[ADD63:%.*]] = add nsw i32 0, [[MUL62]]
8468 // CHECK11-NEXT:    store i32 [[ADD63]], i32* [[I58]], align 4, !llvm.access.group !16
8469 // CHECK11-NEXT:    [[TMP35:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !16
8470 // CHECK11-NEXT:    [[ADD64:%.*]] = add nsw i32 [[TMP35]], 1
8471 // CHECK11-NEXT:    store i32 [[ADD64]], i32* [[A]], align 4, !llvm.access.group !16
8472 // CHECK11-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2
8473 // CHECK11-NEXT:    [[TMP36:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !16
8474 // CHECK11-NEXT:    [[CONV65:%.*]] = fpext float [[TMP36]] to double
8475 // CHECK11-NEXT:    [[ADD66:%.*]] = fadd double [[CONV65]], 1.000000e+00
8476 // CHECK11-NEXT:    [[CONV67:%.*]] = fptrunc double [[ADD66]] to float
8477 // CHECK11-NEXT:    store float [[CONV67]], float* [[ARRAYIDX]], align 4, !llvm.access.group !16
8478 // CHECK11-NEXT:    [[ARRAYIDX68:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3
8479 // CHECK11-NEXT:    [[TMP37:%.*]] = load float, float* [[ARRAYIDX68]], align 4, !llvm.access.group !16
8480 // CHECK11-NEXT:    [[CONV69:%.*]] = fpext float [[TMP37]] to double
8481 // CHECK11-NEXT:    [[ADD70:%.*]] = fadd double [[CONV69]], 1.000000e+00
8482 // CHECK11-NEXT:    [[CONV71:%.*]] = fptrunc double [[ADD70]] to float
8483 // CHECK11-NEXT:    store float [[CONV71]], float* [[ARRAYIDX68]], align 4, !llvm.access.group !16
8484 // CHECK11-NEXT:    [[ARRAYIDX72:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1
8485 // CHECK11-NEXT:    [[ARRAYIDX73:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX72]], i32 0, i32 2
8486 // CHECK11-NEXT:    [[TMP38:%.*]] = load double, double* [[ARRAYIDX73]], align 8, !llvm.access.group !16
8487 // CHECK11-NEXT:    [[ADD74:%.*]] = fadd double [[TMP38]], 1.000000e+00
8488 // CHECK11-NEXT:    store double [[ADD74]], double* [[ARRAYIDX73]], align 8, !llvm.access.group !16
8489 // CHECK11-NEXT:    [[TMP39:%.*]] = mul nsw i32 1, [[TMP2]]
8490 // CHECK11-NEXT:    [[ARRAYIDX75:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP39]]
8491 // CHECK11-NEXT:    [[ARRAYIDX76:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX75]], i32 3
8492 // CHECK11-NEXT:    [[TMP40:%.*]] = load double, double* [[ARRAYIDX76]], align 8, !llvm.access.group !16
8493 // CHECK11-NEXT:    [[ADD77:%.*]] = fadd double [[TMP40]], 1.000000e+00
8494 // CHECK11-NEXT:    store double [[ADD77]], double* [[ARRAYIDX76]], align 8, !llvm.access.group !16
8495 // CHECK11-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0
8496 // CHECK11-NEXT:    [[TMP41:%.*]] = load i64, i64* [[X]], align 4, !llvm.access.group !16
8497 // CHECK11-NEXT:    [[ADD78:%.*]] = add nsw i64 [[TMP41]], 1
8498 // CHECK11-NEXT:    store i64 [[ADD78]], i64* [[X]], align 4, !llvm.access.group !16
8499 // CHECK11-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1
8500 // CHECK11-NEXT:    [[TMP42:%.*]] = load i8, i8* [[Y]], align 4, !llvm.access.group !16
8501 // CHECK11-NEXT:    [[CONV79:%.*]] = sext i8 [[TMP42]] to i32
8502 // CHECK11-NEXT:    [[ADD80:%.*]] = add nsw i32 [[CONV79]], 1
8503 // CHECK11-NEXT:    [[CONV81:%.*]] = trunc i32 [[ADD80]] to i8
8504 // CHECK11-NEXT:    store i8 [[CONV81]], i8* [[Y]], align 4, !llvm.access.group !16
8505 // CHECK11-NEXT:    br label [[OMP_BODY_CONTINUE82:%.*]]
8506 // CHECK11:       omp.body.continue82:
8507 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_INC83:%.*]]
8508 // CHECK11:       omp.inner.for.inc83:
8509 // CHECK11-NEXT:    [[TMP43:%.*]] = load i32, i32* [[DOTOMP_IV57]], align 4, !llvm.access.group !16
8510 // CHECK11-NEXT:    [[ADD84:%.*]] = add nsw i32 [[TMP43]], 1
8511 // CHECK11-NEXT:    store i32 [[ADD84]], i32* [[DOTOMP_IV57]], align 4, !llvm.access.group !16
8512 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_COND59]], !llvm.loop [[LOOP17:![0-9]+]]
8513 // CHECK11:       omp.inner.for.end85:
8514 // CHECK11-NEXT:    store i32 10, i32* [[I58]], align 4
8515 // CHECK11-NEXT:    [[TMP44:%.*]] = load i32, i32* [[A]], align 4
8516 // CHECK11-NEXT:    [[TMP45:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
8517 // CHECK11-NEXT:    call void @llvm.stackrestore(i8* [[TMP45]])
8518 // CHECK11-NEXT:    ret i32 [[TMP44]]
8519 //
8520 //
8521 // CHECK11-LABEL: define {{[^@]+}}@_Z3bari
8522 // CHECK11-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {
8523 // CHECK11-NEXT:  entry:
8524 // CHECK11-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
8525 // CHECK11-NEXT:    [[A:%.*]] = alloca i32, align 4
8526 // CHECK11-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4
8527 // CHECK11-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
8528 // CHECK11-NEXT:    store i32 0, i32* [[A]], align 4
8529 // CHECK11-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
8530 // CHECK11-NEXT:    [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]])
8531 // CHECK11-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
8532 // CHECK11-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
8533 // CHECK11-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
8534 // CHECK11-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
8535 // CHECK11-NEXT:    [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP2]])
8536 // CHECK11-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
8537 // CHECK11-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
8538 // CHECK11-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
8539 // CHECK11-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
8540 // CHECK11-NEXT:    [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]])
8541 // CHECK11-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
8542 // CHECK11-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
8543 // CHECK11-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
8544 // CHECK11-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
8545 // CHECK11-NEXT:    [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]])
8546 // CHECK11-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
8547 // CHECK11-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
8548 // CHECK11-NEXT:    store i32 [[ADD6]], i32* [[A]], align 4
8549 // CHECK11-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
8550 // CHECK11-NEXT:    ret i32 [[TMP8]]
8551 //
8552 //
8553 // CHECK11-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
8554 // CHECK11-SAME: (%struct.S1* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 {
8555 // CHECK11-NEXT:  entry:
8556 // CHECK11-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
8557 // CHECK11-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
8558 // CHECK11-NEXT:    [[B:%.*]] = alloca i32, align 4
8559 // CHECK11-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 4
8560 // CHECK11-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 4
8561 // CHECK11-NEXT:    [[TMP:%.*]] = alloca i32, align 4
8562 // CHECK11-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
8563 // CHECK11-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
8564 // CHECK11-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
8565 // CHECK11-NEXT:    [[I:%.*]] = alloca i32, align 4
8566 // CHECK11-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
8567 // CHECK11-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
8568 // CHECK11-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
8569 // CHECK11-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
8570 // CHECK11-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
8571 // CHECK11-NEXT:    store i32 [[ADD]], i32* [[B]], align 4
8572 // CHECK11-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
8573 // CHECK11-NEXT:    [[TMP2:%.*]] = call i8* @llvm.stacksave()
8574 // CHECK11-NEXT:    store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4
8575 // CHECK11-NEXT:    [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]
8576 // CHECK11-NEXT:    [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2
8577 // CHECK11-NEXT:    store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
8578 // CHECK11-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
8579 // CHECK11-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
8580 // CHECK11-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
8581 // CHECK11-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
8582 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
8583 // CHECK11:       omp.inner.for.cond:
8584 // CHECK11-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
8585 // CHECK11-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !19
8586 // CHECK11-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
8587 // CHECK11-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
8588 // CHECK11:       omp.inner.for.body:
8589 // CHECK11-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
8590 // CHECK11-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
8591 // CHECK11-NEXT:    [[ADD2:%.*]] = add nsw i32 0, [[MUL]]
8592 // CHECK11-NEXT:    store i32 [[ADD2]], i32* [[I]], align 4, !llvm.access.group !19
8593 // CHECK11-NEXT:    [[TMP8:%.*]] = load i32, i32* [[B]], align 4, !llvm.access.group !19
8594 // CHECK11-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP8]] to double
8595 // CHECK11-NEXT:    [[ADD3:%.*]] = fadd double [[CONV]], 1.500000e+00
8596 // CHECK11-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
8597 // CHECK11-NEXT:    store double [[ADD3]], double* [[A]], align 4, !llvm.access.group !19
8598 // CHECK11-NEXT:    [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
8599 // CHECK11-NEXT:    [[TMP9:%.*]] = load double, double* [[A4]], align 4, !llvm.access.group !19
8600 // CHECK11-NEXT:    [[INC:%.*]] = fadd double [[TMP9]], 1.000000e+00
8601 // CHECK11-NEXT:    store double [[INC]], double* [[A4]], align 4, !llvm.access.group !19
8602 // CHECK11-NEXT:    [[CONV5:%.*]] = fptosi double [[INC]] to i16
8603 // CHECK11-NEXT:    [[TMP10:%.*]] = mul nsw i32 1, [[TMP1]]
8604 // CHECK11-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP10]]
8605 // CHECK11-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
8606 // CHECK11-NEXT:    store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2, !llvm.access.group !19
8607 // CHECK11-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
8608 // CHECK11:       omp.body.continue:
8609 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
8610 // CHECK11:       omp.inner.for.inc:
8611 // CHECK11-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
8612 // CHECK11-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1
8613 // CHECK11-NEXT:    store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
8614 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]]
8615 // CHECK11:       omp.inner.for.end:
8616 // CHECK11-NEXT:    store i32 10, i32* [[I]], align 4
8617 // CHECK11-NEXT:    [[TMP12:%.*]] = mul nsw i32 1, [[TMP1]]
8618 // CHECK11-NEXT:    [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP12]]
8619 // CHECK11-NEXT:    [[ARRAYIDX9:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX8]], i32 1
8620 // CHECK11-NEXT:    [[TMP13:%.*]] = load i16, i16* [[ARRAYIDX9]], align 2
8621 // CHECK11-NEXT:    [[CONV10:%.*]] = sext i16 [[TMP13]] to i32
8622 // CHECK11-NEXT:    [[TMP14:%.*]] = load i32, i32* [[B]], align 4
8623 // CHECK11-NEXT:    [[ADD11:%.*]] = add nsw i32 [[CONV10]], [[TMP14]]
8624 // CHECK11-NEXT:    [[TMP15:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
8625 // CHECK11-NEXT:    call void @llvm.stackrestore(i8* [[TMP15]])
8626 // CHECK11-NEXT:    ret i32 [[ADD11]]
8627 //
8628 //
8629 // CHECK11-LABEL: define {{[^@]+}}@_ZL7fstatici
8630 // CHECK11-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {
8631 // CHECK11-NEXT:  entry:
8632 // CHECK11-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
8633 // CHECK11-NEXT:    [[A:%.*]] = alloca i32, align 4
8634 // CHECK11-NEXT:    [[AA:%.*]] = alloca i16, align 2
8635 // CHECK11-NEXT:    [[AAA:%.*]] = alloca i8, align 1
8636 // CHECK11-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
8637 // CHECK11-NEXT:    [[TMP:%.*]] = alloca i32, align 4
8638 // CHECK11-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
8639 // CHECK11-NEXT:    [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
8640 // CHECK11-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
8641 // CHECK11-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
8642 // CHECK11-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
8643 // CHECK11-NEXT:    [[I:%.*]] = alloca i32, align 4
8644 // CHECK11-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
8645 // CHECK11-NEXT:    [[I5:%.*]] = alloca i32, align 4
8646 // CHECK11-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
8647 // CHECK11-NEXT:    store i32 0, i32* [[A]], align 4
8648 // CHECK11-NEXT:    store i16 0, i16* [[AA]], align 2
8649 // CHECK11-NEXT:    store i8 0, i8* [[AAA]], align 1
8650 // CHECK11-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
8651 // CHECK11-NEXT:    store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4
8652 // CHECK11-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
8653 // CHECK11-NEXT:    store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_1]], align 4
8654 // CHECK11-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
8655 // CHECK11-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
8656 // CHECK11-NEXT:    [[SUB:%.*]] = sub i32 [[TMP2]], [[TMP3]]
8657 // CHECK11-NEXT:    [[SUB3:%.*]] = sub i32 [[SUB]], 1
8658 // CHECK11-NEXT:    [[ADD:%.*]] = add i32 [[SUB3]], 1
8659 // CHECK11-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], 1
8660 // CHECK11-NEXT:    [[SUB4:%.*]] = sub i32 [[DIV]], 1
8661 // CHECK11-NEXT:    store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_2]], align 4
8662 // CHECK11-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
8663 // CHECK11-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
8664 // CHECK11-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_UB]], align 4
8665 // CHECK11-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
8666 // CHECK11-NEXT:    store i32 [[TMP5]], i32* [[I]], align 4
8667 // CHECK11-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
8668 // CHECK11-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
8669 // CHECK11-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]]
8670 // CHECK11-NEXT:    br i1 [[CMP]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END:%.*]]
8671 // CHECK11:       simd.if.then:
8672 // CHECK11-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
8673 // CHECK11-NEXT:    store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
8674 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
8675 // CHECK11:       omp.inner.for.cond:
8676 // CHECK11-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
8677 // CHECK11-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !22
8678 // CHECK11-NEXT:    [[ADD6:%.*]] = add i32 [[TMP10]], 1
8679 // CHECK11-NEXT:    [[CMP7:%.*]] = icmp ult i32 [[TMP9]], [[ADD6]]
8680 // CHECK11-NEXT:    br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
8681 // CHECK11:       omp.inner.for.body:
8682 // CHECK11-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group !22
8683 // CHECK11-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
8684 // CHECK11-NEXT:    [[MUL:%.*]] = mul i32 [[TMP12]], 1
8685 // CHECK11-NEXT:    [[ADD8:%.*]] = add i32 [[TMP11]], [[MUL]]
8686 // CHECK11-NEXT:    store i32 [[ADD8]], i32* [[I5]], align 4, !llvm.access.group !22
8687 // CHECK11-NEXT:    [[TMP13:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !22
8688 // CHECK11-NEXT:    [[ADD9:%.*]] = add nsw i32 [[TMP13]], 1
8689 // CHECK11-NEXT:    store i32 [[ADD9]], i32* [[A]], align 4, !llvm.access.group !22
8690 // CHECK11-NEXT:    [[TMP14:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !22
8691 // CHECK11-NEXT:    [[CONV:%.*]] = sext i16 [[TMP14]] to i32
8692 // CHECK11-NEXT:    [[ADD10:%.*]] = add nsw i32 [[CONV]], 1
8693 // CHECK11-NEXT:    [[CONV11:%.*]] = trunc i32 [[ADD10]] to i16
8694 // CHECK11-NEXT:    store i16 [[CONV11]], i16* [[AA]], align 2, !llvm.access.group !22
8695 // CHECK11-NEXT:    [[TMP15:%.*]] = load i8, i8* [[AAA]], align 1, !llvm.access.group !22
8696 // CHECK11-NEXT:    [[CONV12:%.*]] = sext i8 [[TMP15]] to i32
8697 // CHECK11-NEXT:    [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1
8698 // CHECK11-NEXT:    [[CONV14:%.*]] = trunc i32 [[ADD13]] to i8
8699 // CHECK11-NEXT:    store i8 [[CONV14]], i8* [[AAA]], align 1, !llvm.access.group !22
8700 // CHECK11-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2
8701 // CHECK11-NEXT:    [[TMP16:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !22
8702 // CHECK11-NEXT:    [[ADD15:%.*]] = add nsw i32 [[TMP16]], 1
8703 // CHECK11-NEXT:    store i32 [[ADD15]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !22
8704 // CHECK11-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
8705 // CHECK11:       omp.body.continue:
8706 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
8707 // CHECK11:       omp.inner.for.inc:
8708 // CHECK11-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
8709 // CHECK11-NEXT:    [[ADD16:%.*]] = add i32 [[TMP17]], 1
8710 // CHECK11-NEXT:    store i32 [[ADD16]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
8711 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]]
8712 // CHECK11:       omp.inner.for.end:
8713 // CHECK11-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
8714 // CHECK11-NEXT:    [[TMP19:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
8715 // CHECK11-NEXT:    [[TMP20:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
8716 // CHECK11-NEXT:    [[SUB17:%.*]] = sub i32 [[TMP19]], [[TMP20]]
8717 // CHECK11-NEXT:    [[SUB18:%.*]] = sub i32 [[SUB17]], 1
8718 // CHECK11-NEXT:    [[ADD19:%.*]] = add i32 [[SUB18]], 1
8719 // CHECK11-NEXT:    [[DIV20:%.*]] = udiv i32 [[ADD19]], 1
8720 // CHECK11-NEXT:    [[MUL21:%.*]] = mul i32 [[DIV20]], 1
8721 // CHECK11-NEXT:    [[ADD22:%.*]] = add i32 [[TMP18]], [[MUL21]]
8722 // CHECK11-NEXT:    store i32 [[ADD22]], i32* [[I5]], align 4
8723 // CHECK11-NEXT:    br label [[SIMD_IF_END]]
8724 // CHECK11:       simd.if.end:
8725 // CHECK11-NEXT:    [[TMP21:%.*]] = load i32, i32* [[A]], align 4
8726 // CHECK11-NEXT:    ret i32 [[TMP21]]
8727 //
8728 //
8729 // CHECK11-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
8730 // CHECK11-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat {
8731 // CHECK11-NEXT:  entry:
8732 // CHECK11-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
8733 // CHECK11-NEXT:    [[A:%.*]] = alloca i32, align 4
8734 // CHECK11-NEXT:    [[AA:%.*]] = alloca i16, align 2
8735 // CHECK11-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
8736 // CHECK11-NEXT:    [[TMP:%.*]] = alloca i32, align 4
8737 // CHECK11-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
8738 // CHECK11-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
8739 // CHECK11-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
8740 // CHECK11-NEXT:    [[I:%.*]] = alloca i32, align 4
8741 // CHECK11-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
8742 // CHECK11-NEXT:    store i32 0, i32* [[A]], align 4
8743 // CHECK11-NEXT:    store i16 0, i16* [[AA]], align 2
8744 // CHECK11-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
8745 // CHECK11-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
8746 // CHECK11-NEXT:    [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
8747 // CHECK11-NEXT:    store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4
8748 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
8749 // CHECK11:       omp.inner.for.cond:
8750 // CHECK11-NEXT:    [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25
8751 // CHECK11-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !25
8752 // CHECK11-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
8753 // CHECK11-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
8754 // CHECK11:       omp.inner.for.body:
8755 // CHECK11-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25
8756 // CHECK11-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1
8757 // CHECK11-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
8758 // CHECK11-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !25
8759 // CHECK11-NEXT:    [[TMP4:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !25
8760 // CHECK11-NEXT:    [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1
8761 // CHECK11-NEXT:    store i32 [[ADD1]], i32* [[A]], align 4, !llvm.access.group !25
8762 // CHECK11-NEXT:    [[TMP5:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !25
8763 // CHECK11-NEXT:    [[CONV:%.*]] = sext i16 [[TMP5]] to i32
8764 // CHECK11-NEXT:    [[ADD2:%.*]] = add nsw i32 [[CONV]], 1
8765 // CHECK11-NEXT:    [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
8766 // CHECK11-NEXT:    store i16 [[CONV3]], i16* [[AA]], align 2, !llvm.access.group !25
8767 // CHECK11-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2
8768 // CHECK11-NEXT:    [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !25
8769 // CHECK11-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP6]], 1
8770 // CHECK11-NEXT:    store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !25
8771 // CHECK11-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
8772 // CHECK11:       omp.body.continue:
8773 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
8774 // CHECK11:       omp.inner.for.inc:
8775 // CHECK11-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25
8776 // CHECK11-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP7]], 1
8777 // CHECK11-NEXT:    store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25
8778 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP26:![0-9]+]]
8779 // CHECK11:       omp.inner.for.end:
8780 // CHECK11-NEXT:    store i32 10, i32* [[I]], align 4
8781 // CHECK11-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
8782 // CHECK11-NEXT:    ret i32 [[TMP8]]
8783 //
8784 //
8785 // CHECK13-LABEL: define {{[^@]+}}@_Z3fooi
8786 // CHECK13-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0:[0-9]+]] {
8787 // CHECK13-NEXT:  entry:
8788 // CHECK13-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
8789 // CHECK13-NEXT:    [[A:%.*]] = alloca i32, align 4
8790 // CHECK13-NEXT:    [[AA:%.*]] = alloca i16, align 2
8791 // CHECK13-NEXT:    [[B:%.*]] = alloca [10 x float], align 4
8792 // CHECK13-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 8
8793 // CHECK13-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
8794 // CHECK13-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 8
8795 // CHECK13-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i64, align 8
8796 // CHECK13-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8
8797 // CHECK13-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
8798 // CHECK13-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
8799 // CHECK13-NEXT:    [[TMP:%.*]] = alloca i32, align 4
8800 // CHECK13-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
8801 // CHECK13-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
8802 // CHECK13-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
8803 // CHECK13-NEXT:    [[I:%.*]] = alloca i32, align 4
8804 // CHECK13-NEXT:    [[_TMP4:%.*]] = alloca i32, align 4
8805 // CHECK13-NEXT:    [[DOTOMP_LB5:%.*]] = alloca i32, align 4
8806 // CHECK13-NEXT:    [[DOTOMP_UB6:%.*]] = alloca i32, align 4
8807 // CHECK13-NEXT:    [[DOTOMP_IV7:%.*]] = alloca i32, align 4
8808 // CHECK13-NEXT:    [[DOTLINEAR_START:%.*]] = alloca i32, align 4
8809 // CHECK13-NEXT:    [[A8:%.*]] = alloca i32, align 4
8810 // CHECK13-NEXT:    [[A9:%.*]] = alloca i32, align 4
8811 // CHECK13-NEXT:    [[_TMP20:%.*]] = alloca i32, align 4
8812 // CHECK13-NEXT:    [[DOTOMP_LB21:%.*]] = alloca i32, align 4
8813 // CHECK13-NEXT:    [[DOTOMP_UB22:%.*]] = alloca i32, align 4
8814 // CHECK13-NEXT:    [[DOTOMP_IV23:%.*]] = alloca i32, align 4
8815 // CHECK13-NEXT:    [[I24:%.*]] = alloca i32, align 4
8816 // CHECK13-NEXT:    [[_TMP36:%.*]] = alloca i32, align 4
8817 // CHECK13-NEXT:    [[DOTOMP_LB37:%.*]] = alloca i32, align 4
8818 // CHECK13-NEXT:    [[DOTOMP_UB38:%.*]] = alloca i32, align 4
8819 // CHECK13-NEXT:    [[DOTOMP_IV39:%.*]] = alloca i32, align 4
8820 // CHECK13-NEXT:    [[I40:%.*]] = alloca i32, align 4
8821 // CHECK13-NEXT:    [[_TMP54:%.*]] = alloca i32, align 4
8822 // CHECK13-NEXT:    [[DOTOMP_LB55:%.*]] = alloca i32, align 4
8823 // CHECK13-NEXT:    [[DOTOMP_UB56:%.*]] = alloca i32, align 4
8824 // CHECK13-NEXT:    [[DOTOMP_IV57:%.*]] = alloca i32, align 4
8825 // CHECK13-NEXT:    [[I58:%.*]] = alloca i32, align 4
8826 // CHECK13-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
8827 // CHECK13-NEXT:    store i32 0, i32* [[A]], align 4
8828 // CHECK13-NEXT:    store i16 0, i16* [[AA]], align 2
8829 // CHECK13-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
8830 // CHECK13-NEXT:    [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
8831 // CHECK13-NEXT:    [[TMP2:%.*]] = call i8* @llvm.stacksave()
8832 // CHECK13-NEXT:    store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8
8833 // CHECK13-NEXT:    [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4
8834 // CHECK13-NEXT:    store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8
8835 // CHECK13-NEXT:    [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
8836 // CHECK13-NEXT:    [[TMP4:%.*]] = zext i32 [[TMP3]] to i64
8837 // CHECK13-NEXT:    [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]]
8838 // CHECK13-NEXT:    [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8
8839 // CHECK13-NEXT:    store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8
8840 // CHECK13-NEXT:    [[TMP6:%.*]] = load i32, i32* [[A]], align 4
8841 // CHECK13-NEXT:    store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_]], align 4
8842 // CHECK13-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
8843 // CHECK13-NEXT:    store i32 [[TMP7]], i32* [[DOTCAPTURE_EXPR_2]], align 4
8844 // CHECK13-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
8845 // CHECK13-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
8846 // CHECK13-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
8847 // CHECK13-NEXT:    store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
8848 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
8849 // CHECK13:       omp.inner.for.cond:
8850 // CHECK13-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
8851 // CHECK13-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !2
8852 // CHECK13-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
8853 // CHECK13-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
8854 // CHECK13:       omp.inner.for.body:
8855 // CHECK13-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
8856 // CHECK13-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
8857 // CHECK13-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
8858 // CHECK13-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !2
8859 // CHECK13-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
8860 // CHECK13:       omp.body.continue:
8861 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
8862 // CHECK13:       omp.inner.for.inc:
8863 // CHECK13-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
8864 // CHECK13-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1
8865 // CHECK13-NEXT:    store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
8866 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]
8867 // CHECK13:       omp.inner.for.end:
8868 // CHECK13-NEXT:    store i32 10, i32* [[I]], align 4
8869 // CHECK13-NEXT:    store i32 0, i32* [[DOTOMP_LB5]], align 4
8870 // CHECK13-NEXT:    store i32 9, i32* [[DOTOMP_UB6]], align 4
8871 // CHECK13-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB5]], align 4
8872 // CHECK13-NEXT:    store i32 [[TMP13]], i32* [[DOTOMP_IV7]], align 4
8873 // CHECK13-NEXT:    [[TMP14:%.*]] = load i32, i32* [[A]], align 4
8874 // CHECK13-NEXT:    store i32 [[TMP14]], i32* [[DOTLINEAR_START]], align 4
8875 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_COND10:%.*]]
8876 // CHECK13:       omp.inner.for.cond10:
8877 // CHECK13-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV7]], align 4
8878 // CHECK13-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB6]], align 4
8879 // CHECK13-NEXT:    [[CMP11:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]]
8880 // CHECK13-NEXT:    br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY12:%.*]], label [[OMP_INNER_FOR_END19:%.*]]
8881 // CHECK13:       omp.inner.for.body12:
8882 // CHECK13-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV7]], align 4
8883 // CHECK13-NEXT:    [[MUL13:%.*]] = mul nsw i32 [[TMP17]], 1
8884 // CHECK13-NEXT:    [[ADD14:%.*]] = add nsw i32 0, [[MUL13]]
8885 // CHECK13-NEXT:    store i32 [[ADD14]], i32* [[A8]], align 4, !nontemporal !7
8886 // CHECK13-NEXT:    [[TMP18:%.*]] = load i32, i32* [[A8]], align 4, !nontemporal !7
8887 // CHECK13-NEXT:    [[ADD15:%.*]] = add nsw i32 [[TMP18]], 1
8888 // CHECK13-NEXT:    store i32 [[ADD15]], i32* [[A8]], align 4, !nontemporal !7
8889 // CHECK13-NEXT:    br label [[OMP_BODY_CONTINUE16:%.*]]
8890 // CHECK13:       omp.body.continue16:
8891 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_INC17:%.*]]
8892 // CHECK13:       omp.inner.for.inc17:
8893 // CHECK13-NEXT:    [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV7]], align 4
8894 // CHECK13-NEXT:    [[ADD18:%.*]] = add nsw i32 [[TMP19]], 1
8895 // CHECK13-NEXT:    store i32 [[ADD18]], i32* [[DOTOMP_IV7]], align 4
8896 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_COND10]], !llvm.loop [[LOOP8:![0-9]+]]
8897 // CHECK13:       omp.inner.for.end19:
8898 // CHECK13-NEXT:    store i32 10, i32* [[A]], align 4
8899 // CHECK13-NEXT:    store i32 0, i32* [[DOTOMP_LB21]], align 4
8900 // CHECK13-NEXT:    store i32 9, i32* [[DOTOMP_UB22]], align 4
8901 // CHECK13-NEXT:    [[TMP20:%.*]] = load i32, i32* [[DOTOMP_LB21]], align 4
8902 // CHECK13-NEXT:    store i32 [[TMP20]], i32* [[DOTOMP_IV23]], align 4
8903 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_COND25:%.*]]
8904 // CHECK13:       omp.inner.for.cond25:
8905 // CHECK13-NEXT:    [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV23]], align 4, !llvm.access.group !10
8906 // CHECK13-NEXT:    [[TMP22:%.*]] = load i32, i32* [[DOTOMP_UB22]], align 4, !llvm.access.group !10
8907 // CHECK13-NEXT:    [[CMP26:%.*]] = icmp sle i32 [[TMP21]], [[TMP22]]
8908 // CHECK13-NEXT:    br i1 [[CMP26]], label [[OMP_INNER_FOR_BODY27:%.*]], label [[OMP_INNER_FOR_END35:%.*]]
8909 // CHECK13:       omp.inner.for.body27:
8910 // CHECK13-NEXT:    [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV23]], align 4, !llvm.access.group !10
8911 // CHECK13-NEXT:    [[MUL28:%.*]] = mul nsw i32 [[TMP23]], 1
8912 // CHECK13-NEXT:    [[ADD29:%.*]] = add nsw i32 0, [[MUL28]]
8913 // CHECK13-NEXT:    store i32 [[ADD29]], i32* [[I24]], align 4, !llvm.access.group !10
8914 // CHECK13-NEXT:    [[TMP24:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !10
8915 // CHECK13-NEXT:    [[CONV:%.*]] = sext i16 [[TMP24]] to i32
8916 // CHECK13-NEXT:    [[ADD30:%.*]] = add nsw i32 [[CONV]], 1
8917 // CHECK13-NEXT:    [[CONV31:%.*]] = trunc i32 [[ADD30]] to i16
8918 // CHECK13-NEXT:    store i16 [[CONV31]], i16* [[AA]], align 2, !llvm.access.group !10
8919 // CHECK13-NEXT:    br label [[OMP_BODY_CONTINUE32:%.*]]
8920 // CHECK13:       omp.body.continue32:
8921 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_INC33:%.*]]
8922 // CHECK13:       omp.inner.for.inc33:
8923 // CHECK13-NEXT:    [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IV23]], align 4, !llvm.access.group !10
8924 // CHECK13-NEXT:    [[ADD34:%.*]] = add nsw i32 [[TMP25]], 1
8925 // CHECK13-NEXT:    store i32 [[ADD34]], i32* [[DOTOMP_IV23]], align 4, !llvm.access.group !10
8926 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_COND25]], !llvm.loop [[LOOP11:![0-9]+]]
8927 // CHECK13:       omp.inner.for.end35:
8928 // CHECK13-NEXT:    store i32 10, i32* [[I24]], align 4
8929 // CHECK13-NEXT:    store i32 0, i32* [[DOTOMP_LB37]], align 4
8930 // CHECK13-NEXT:    store i32 9, i32* [[DOTOMP_UB38]], align 4
8931 // CHECK13-NEXT:    [[TMP26:%.*]] = load i32, i32* [[DOTOMP_LB37]], align 4
8932 // CHECK13-NEXT:    store i32 [[TMP26]], i32* [[DOTOMP_IV39]], align 4
8933 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_COND41:%.*]]
8934 // CHECK13:       omp.inner.for.cond41:
8935 // CHECK13-NEXT:    [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV39]], align 4, !llvm.access.group !13
8936 // CHECK13-NEXT:    [[TMP28:%.*]] = load i32, i32* [[DOTOMP_UB38]], align 4, !llvm.access.group !13
8937 // CHECK13-NEXT:    [[CMP42:%.*]] = icmp sle i32 [[TMP27]], [[TMP28]]
8938 // CHECK13-NEXT:    br i1 [[CMP42]], label [[OMP_INNER_FOR_BODY43:%.*]], label [[OMP_INNER_FOR_END53:%.*]]
8939 // CHECK13:       omp.inner.for.body43:
8940 // CHECK13-NEXT:    [[TMP29:%.*]] = load i32, i32* [[DOTOMP_IV39]], align 4, !llvm.access.group !13
8941 // CHECK13-NEXT:    [[MUL44:%.*]] = mul nsw i32 [[TMP29]], 1
8942 // CHECK13-NEXT:    [[ADD45:%.*]] = add nsw i32 0, [[MUL44]]
8943 // CHECK13-NEXT:    store i32 [[ADD45]], i32* [[I40]], align 4, !llvm.access.group !13
8944 // CHECK13-NEXT:    [[TMP30:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !13
8945 // CHECK13-NEXT:    [[ADD46:%.*]] = add nsw i32 [[TMP30]], 1
8946 // CHECK13-NEXT:    store i32 [[ADD46]], i32* [[A]], align 4, !llvm.access.group !13
8947 // CHECK13-NEXT:    [[TMP31:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !13
8948 // CHECK13-NEXT:    [[CONV47:%.*]] = sext i16 [[TMP31]] to i32
8949 // CHECK13-NEXT:    [[ADD48:%.*]] = add nsw i32 [[CONV47]], 1
8950 // CHECK13-NEXT:    [[CONV49:%.*]] = trunc i32 [[ADD48]] to i16
8951 // CHECK13-NEXT:    store i16 [[CONV49]], i16* [[AA]], align 2, !llvm.access.group !13
8952 // CHECK13-NEXT:    br label [[OMP_BODY_CONTINUE50:%.*]]
8953 // CHECK13:       omp.body.continue50:
8954 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_INC51:%.*]]
8955 // CHECK13:       omp.inner.for.inc51:
8956 // CHECK13-NEXT:    [[TMP32:%.*]] = load i32, i32* [[DOTOMP_IV39]], align 4, !llvm.access.group !13
8957 // CHECK13-NEXT:    [[ADD52:%.*]] = add nsw i32 [[TMP32]], 1
8958 // CHECK13-NEXT:    store i32 [[ADD52]], i32* [[DOTOMP_IV39]], align 4, !llvm.access.group !13
8959 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_COND41]], !llvm.loop [[LOOP14:![0-9]+]]
8960 // CHECK13:       omp.inner.for.end53:
8961 // CHECK13-NEXT:    store i32 10, i32* [[I40]], align 4
8962 // CHECK13-NEXT:    store i32 0, i32* [[DOTOMP_LB55]], align 4
8963 // CHECK13-NEXT:    store i32 9, i32* [[DOTOMP_UB56]], align 4
8964 // CHECK13-NEXT:    [[TMP33:%.*]] = load i32, i32* [[DOTOMP_LB55]], align 4
8965 // CHECK13-NEXT:    store i32 [[TMP33]], i32* [[DOTOMP_IV57]], align 4
8966 // CHECK13-NEXT:    [[ARRAYDECAY:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 0
8967 // CHECK13-NEXT:    call void @llvm.assume(i1 true) [ "align"(float* [[ARRAYDECAY]], i64 16) ]
8968 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_COND59:%.*]]
8969 // CHECK13:       omp.inner.for.cond59:
8970 // CHECK13-NEXT:    [[TMP34:%.*]] = load i32, i32* [[DOTOMP_IV57]], align 4, !llvm.access.group !16
8971 // CHECK13-NEXT:    [[TMP35:%.*]] = load i32, i32* [[DOTOMP_UB56]], align 4, !llvm.access.group !16
8972 // CHECK13-NEXT:    [[CMP60:%.*]] = icmp sle i32 [[TMP34]], [[TMP35]]
8973 // CHECK13-NEXT:    br i1 [[CMP60]], label [[OMP_INNER_FOR_BODY61:%.*]], label [[OMP_INNER_FOR_END85:%.*]]
8974 // CHECK13:       omp.inner.for.body61:
8975 // CHECK13-NEXT:    [[TMP36:%.*]] = load i32, i32* [[DOTOMP_IV57]], align 4, !llvm.access.group !16
8976 // CHECK13-NEXT:    [[MUL62:%.*]] = mul nsw i32 [[TMP36]], 1
8977 // CHECK13-NEXT:    [[ADD63:%.*]] = add nsw i32 0, [[MUL62]]
8978 // CHECK13-NEXT:    store i32 [[ADD63]], i32* [[I58]], align 4, !llvm.access.group !16
8979 // CHECK13-NEXT:    [[TMP37:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !16
8980 // CHECK13-NEXT:    [[ADD64:%.*]] = add nsw i32 [[TMP37]], 1
8981 // CHECK13-NEXT:    store i32 [[ADD64]], i32* [[A]], align 4, !llvm.access.group !16
8982 // CHECK13-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2
8983 // CHECK13-NEXT:    [[TMP38:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !16
8984 // CHECK13-NEXT:    [[CONV65:%.*]] = fpext float [[TMP38]] to double
8985 // CHECK13-NEXT:    [[ADD66:%.*]] = fadd double [[CONV65]], 1.000000e+00
8986 // CHECK13-NEXT:    [[CONV67:%.*]] = fptrunc double [[ADD66]] to float
8987 // CHECK13-NEXT:    store float [[CONV67]], float* [[ARRAYIDX]], align 4, !llvm.access.group !16
8988 // CHECK13-NEXT:    [[ARRAYIDX68:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3
8989 // CHECK13-NEXT:    [[TMP39:%.*]] = load float, float* [[ARRAYIDX68]], align 4, !llvm.access.group !16
8990 // CHECK13-NEXT:    [[CONV69:%.*]] = fpext float [[TMP39]] to double
8991 // CHECK13-NEXT:    [[ADD70:%.*]] = fadd double [[CONV69]], 1.000000e+00
8992 // CHECK13-NEXT:    [[CONV71:%.*]] = fptrunc double [[ADD70]] to float
8993 // CHECK13-NEXT:    store float [[CONV71]], float* [[ARRAYIDX68]], align 4, !llvm.access.group !16
8994 // CHECK13-NEXT:    [[ARRAYIDX72:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1
8995 // CHECK13-NEXT:    [[ARRAYIDX73:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX72]], i64 0, i64 2
8996 // CHECK13-NEXT:    [[TMP40:%.*]] = load double, double* [[ARRAYIDX73]], align 8, !llvm.access.group !16
8997 // CHECK13-NEXT:    [[ADD74:%.*]] = fadd double [[TMP40]], 1.000000e+00
8998 // CHECK13-NEXT:    store double [[ADD74]], double* [[ARRAYIDX73]], align 8, !llvm.access.group !16
8999 // CHECK13-NEXT:    [[TMP41:%.*]] = mul nsw i64 1, [[TMP4]]
9000 // CHECK13-NEXT:    [[ARRAYIDX75:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP41]]
9001 // CHECK13-NEXT:    [[ARRAYIDX76:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX75]], i64 3
9002 // CHECK13-NEXT:    [[TMP42:%.*]] = load double, double* [[ARRAYIDX76]], align 8, !llvm.access.group !16
9003 // CHECK13-NEXT:    [[ADD77:%.*]] = fadd double [[TMP42]], 1.000000e+00
9004 // CHECK13-NEXT:    store double [[ADD77]], double* [[ARRAYIDX76]], align 8, !llvm.access.group !16
9005 // CHECK13-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0
9006 // CHECK13-NEXT:    [[TMP43:%.*]] = load i64, i64* [[X]], align 8, !llvm.access.group !16
9007 // CHECK13-NEXT:    [[ADD78:%.*]] = add nsw i64 [[TMP43]], 1
9008 // CHECK13-NEXT:    store i64 [[ADD78]], i64* [[X]], align 8, !llvm.access.group !16
9009 // CHECK13-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1
9010 // CHECK13-NEXT:    [[TMP44:%.*]] = load i8, i8* [[Y]], align 8, !llvm.access.group !16
9011 // CHECK13-NEXT:    [[CONV79:%.*]] = sext i8 [[TMP44]] to i32
9012 // CHECK13-NEXT:    [[ADD80:%.*]] = add nsw i32 [[CONV79]], 1
9013 // CHECK13-NEXT:    [[CONV81:%.*]] = trunc i32 [[ADD80]] to i8
9014 // CHECK13-NEXT:    store i8 [[CONV81]], i8* [[Y]], align 8, !llvm.access.group !16
9015 // CHECK13-NEXT:    br label [[OMP_BODY_CONTINUE82:%.*]]
9016 // CHECK13:       omp.body.continue82:
9017 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_INC83:%.*]]
9018 // CHECK13:       omp.inner.for.inc83:
9019 // CHECK13-NEXT:    [[TMP45:%.*]] = load i32, i32* [[DOTOMP_IV57]], align 4, !llvm.access.group !16
9020 // CHECK13-NEXT:    [[ADD84:%.*]] = add nsw i32 [[TMP45]], 1
9021 // CHECK13-NEXT:    store i32 [[ADD84]], i32* [[DOTOMP_IV57]], align 4, !llvm.access.group !16
9022 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_COND59]], !llvm.loop [[LOOP17:![0-9]+]]
9023 // CHECK13:       omp.inner.for.end85:
9024 // CHECK13-NEXT:    store i32 10, i32* [[I58]], align 4
9025 // CHECK13-NEXT:    [[TMP46:%.*]] = load i32, i32* [[A]], align 4
9026 // CHECK13-NEXT:    [[TMP47:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
9027 // CHECK13-NEXT:    call void @llvm.stackrestore(i8* [[TMP47]])
9028 // CHECK13-NEXT:    ret i32 [[TMP46]]
9029 //
9030 //
9031 // CHECK13-LABEL: define {{[^@]+}}@_Z3bari
9032 // CHECK13-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {
9033 // CHECK13-NEXT:  entry:
9034 // CHECK13-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
9035 // CHECK13-NEXT:    [[A:%.*]] = alloca i32, align 4
9036 // CHECK13-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8
9037 // CHECK13-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
9038 // CHECK13-NEXT:    store i32 0, i32* [[A]], align 4
9039 // CHECK13-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
9040 // CHECK13-NEXT:    [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]])
9041 // CHECK13-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
9042 // CHECK13-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
9043 // CHECK13-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
9044 // CHECK13-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
9045 // CHECK13-NEXT:    [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP2]])
9046 // CHECK13-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
9047 // CHECK13-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
9048 // CHECK13-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
9049 // CHECK13-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
9050 // CHECK13-NEXT:    [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]])
9051 // CHECK13-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
9052 // CHECK13-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
9053 // CHECK13-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
9054 // CHECK13-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
9055 // CHECK13-NEXT:    [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]])
9056 // CHECK13-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
9057 // CHECK13-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
9058 // CHECK13-NEXT:    store i32 [[ADD6]], i32* [[A]], align 4
9059 // CHECK13-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
9060 // CHECK13-NEXT:    ret i32 [[TMP8]]
9061 //
9062 //
9063 // CHECK13-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
9064 // CHECK13-SAME: (%struct.S1* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 {
9065 // CHECK13-NEXT:  entry:
9066 // CHECK13-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
9067 // CHECK13-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
9068 // CHECK13-NEXT:    [[B:%.*]] = alloca i32, align 4
9069 // CHECK13-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 8
9070 // CHECK13-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
9071 // CHECK13-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
9072 // CHECK13-NEXT:    [[TMP:%.*]] = alloca i32, align 4
9073 // CHECK13-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
9074 // CHECK13-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
9075 // CHECK13-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
9076 // CHECK13-NEXT:    [[I:%.*]] = alloca i32, align 4
9077 // CHECK13-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
9078 // CHECK13-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
9079 // CHECK13-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
9080 // CHECK13-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
9081 // CHECK13-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
9082 // CHECK13-NEXT:    store i32 [[ADD]], i32* [[B]], align 4
9083 // CHECK13-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
9084 // CHECK13-NEXT:    [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
9085 // CHECK13-NEXT:    [[TMP3:%.*]] = call i8* @llvm.stacksave()
9086 // CHECK13-NEXT:    store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8
9087 // CHECK13-NEXT:    [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]
9088 // CHECK13-NEXT:    [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2
9089 // CHECK13-NEXT:    store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8
9090 // CHECK13-NEXT:    [[TMP5:%.*]] = load i32, i32* [[N_ADDR]], align 4
9091 // CHECK13-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 60
9092 // CHECK13-NEXT:    [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8
9093 // CHECK13-NEXT:    store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
9094 // CHECK13-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
9095 // CHECK13-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
9096 // CHECK13-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
9097 // CHECK13-NEXT:    store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
9098 // CHECK13-NEXT:    [[TMP7:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
9099 // CHECK13-NEXT:    [[TOBOOL:%.*]] = trunc i8 [[TMP7]] to i1
9100 // CHECK13-NEXT:    br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
9101 // CHECK13:       omp_if.then:
9102 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
9103 // CHECK13:       omp.inner.for.cond:
9104 // CHECK13-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
9105 // CHECK13-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !19
9106 // CHECK13-NEXT:    [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
9107 // CHECK13-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
9108 // CHECK13:       omp.inner.for.body:
9109 // CHECK13-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
9110 // CHECK13-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
9111 // CHECK13-NEXT:    [[ADD3:%.*]] = add nsw i32 0, [[MUL]]
9112 // CHECK13-NEXT:    store i32 [[ADD3]], i32* [[I]], align 4, !llvm.access.group !19
9113 // CHECK13-NEXT:    [[TMP11:%.*]] = load i32, i32* [[B]], align 4, !llvm.access.group !19
9114 // CHECK13-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP11]] to double
9115 // CHECK13-NEXT:    [[ADD4:%.*]] = fadd double [[CONV]], 1.500000e+00
9116 // CHECK13-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
9117 // CHECK13-NEXT:    store double [[ADD4]], double* [[A]], align 8, !llvm.access.group !19
9118 // CHECK13-NEXT:    [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
9119 // CHECK13-NEXT:    [[TMP12:%.*]] = load double, double* [[A5]], align 8, !llvm.access.group !19
9120 // CHECK13-NEXT:    [[INC:%.*]] = fadd double [[TMP12]], 1.000000e+00
9121 // CHECK13-NEXT:    store double [[INC]], double* [[A5]], align 8, !llvm.access.group !19
9122 // CHECK13-NEXT:    [[CONV6:%.*]] = fptosi double [[INC]] to i16
9123 // CHECK13-NEXT:    [[TMP13:%.*]] = mul nsw i64 1, [[TMP2]]
9124 // CHECK13-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP13]]
9125 // CHECK13-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
9126 // CHECK13-NEXT:    store i16 [[CONV6]], i16* [[ARRAYIDX7]], align 2, !llvm.access.group !19
9127 // CHECK13-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
9128 // CHECK13:       omp.body.continue:
9129 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
9130 // CHECK13:       omp.inner.for.inc:
9131 // CHECK13-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
9132 // CHECK13-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP14]], 1
9133 // CHECK13-NEXT:    store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
9134 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]]
9135 // CHECK13:       omp.inner.for.end:
9136 // CHECK13-NEXT:    br label [[OMP_IF_END:%.*]]
9137 // CHECK13:       omp_if.else:
9138 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_COND9:%.*]]
9139 // CHECK13:       omp.inner.for.cond9:
9140 // CHECK13-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
9141 // CHECK13-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
9142 // CHECK13-NEXT:    [[CMP10:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]]
9143 // CHECK13-NEXT:    br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY11:%.*]], label [[OMP_INNER_FOR_END25:%.*]]
9144 // CHECK13:       omp.inner.for.body11:
9145 // CHECK13-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
9146 // CHECK13-NEXT:    [[MUL12:%.*]] = mul nsw i32 [[TMP17]], 1
9147 // CHECK13-NEXT:    [[ADD13:%.*]] = add nsw i32 0, [[MUL12]]
9148 // CHECK13-NEXT:    store i32 [[ADD13]], i32* [[I]], align 4
9149 // CHECK13-NEXT:    [[TMP18:%.*]] = load i32, i32* [[B]], align 4
9150 // CHECK13-NEXT:    [[CONV14:%.*]] = sitofp i32 [[TMP18]] to double
9151 // CHECK13-NEXT:    [[ADD15:%.*]] = fadd double [[CONV14]], 1.500000e+00
9152 // CHECK13-NEXT:    [[A16:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
9153 // CHECK13-NEXT:    store double [[ADD15]], double* [[A16]], align 8
9154 // CHECK13-NEXT:    [[A17:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
9155 // CHECK13-NEXT:    [[TMP19:%.*]] = load double, double* [[A17]], align 8
9156 // CHECK13-NEXT:    [[INC18:%.*]] = fadd double [[TMP19]], 1.000000e+00
9157 // CHECK13-NEXT:    store double [[INC18]], double* [[A17]], align 8
9158 // CHECK13-NEXT:    [[CONV19:%.*]] = fptosi double [[INC18]] to i16
9159 // CHECK13-NEXT:    [[TMP20:%.*]] = mul nsw i64 1, [[TMP2]]
9160 // CHECK13-NEXT:    [[ARRAYIDX20:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP20]]
9161 // CHECK13-NEXT:    [[ARRAYIDX21:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX20]], i64 1
9162 // CHECK13-NEXT:    store i16 [[CONV19]], i16* [[ARRAYIDX21]], align 2
9163 // CHECK13-NEXT:    br label [[OMP_BODY_CONTINUE22:%.*]]
9164 // CHECK13:       omp.body.continue22:
9165 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_INC23:%.*]]
9166 // CHECK13:       omp.inner.for.inc23:
9167 // CHECK13-NEXT:    [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
9168 // CHECK13-NEXT:    [[ADD24:%.*]] = add nsw i32 [[TMP21]], 1
9169 // CHECK13-NEXT:    store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4
9170 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_COND9]], !llvm.loop [[LOOP22:![0-9]+]]
9171 // CHECK13:       omp.inner.for.end25:
9172 // CHECK13-NEXT:    br label [[OMP_IF_END]]
9173 // CHECK13:       omp_if.end:
9174 // CHECK13-NEXT:    store i32 10, i32* [[I]], align 4
9175 // CHECK13-NEXT:    [[TMP22:%.*]] = mul nsw i64 1, [[TMP2]]
9176 // CHECK13-NEXT:    [[ARRAYIDX26:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP22]]
9177 // CHECK13-NEXT:    [[ARRAYIDX27:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX26]], i64 1
9178 // CHECK13-NEXT:    [[TMP23:%.*]] = load i16, i16* [[ARRAYIDX27]], align 2
9179 // CHECK13-NEXT:    [[CONV28:%.*]] = sext i16 [[TMP23]] to i32
9180 // CHECK13-NEXT:    [[TMP24:%.*]] = load i32, i32* [[B]], align 4
9181 // CHECK13-NEXT:    [[ADD29:%.*]] = add nsw i32 [[CONV28]], [[TMP24]]
9182 // CHECK13-NEXT:    [[TMP25:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
9183 // CHECK13-NEXT:    call void @llvm.stackrestore(i8* [[TMP25]])
9184 // CHECK13-NEXT:    ret i32 [[ADD29]]
9185 //
9186 //
9187 // CHECK13-LABEL: define {{[^@]+}}@_ZL7fstatici
9188 // CHECK13-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {
9189 // CHECK13-NEXT:  entry:
9190 // CHECK13-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
9191 // CHECK13-NEXT:    [[A:%.*]] = alloca i32, align 4
9192 // CHECK13-NEXT:    [[AA:%.*]] = alloca i16, align 2
9193 // CHECK13-NEXT:    [[AAA:%.*]] = alloca i8, align 1
9194 // CHECK13-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
9195 // CHECK13-NEXT:    [[TMP:%.*]] = alloca i32, align 4
9196 // CHECK13-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
9197 // CHECK13-NEXT:    [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
9198 // CHECK13-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
9199 // CHECK13-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
9200 // CHECK13-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
9201 // CHECK13-NEXT:    [[I:%.*]] = alloca i32, align 4
9202 // CHECK13-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
9203 // CHECK13-NEXT:    [[I5:%.*]] = alloca i32, align 4
9204 // CHECK13-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
9205 // CHECK13-NEXT:    store i32 0, i32* [[A]], align 4
9206 // CHECK13-NEXT:    store i16 0, i16* [[AA]], align 2
9207 // CHECK13-NEXT:    store i8 0, i8* [[AAA]], align 1
9208 // CHECK13-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
9209 // CHECK13-NEXT:    store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4
9210 // CHECK13-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
9211 // CHECK13-NEXT:    store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_1]], align 4
9212 // CHECK13-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
9213 // CHECK13-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
9214 // CHECK13-NEXT:    [[SUB:%.*]] = sub i32 [[TMP2]], [[TMP3]]
9215 // CHECK13-NEXT:    [[SUB3:%.*]] = sub i32 [[SUB]], 1
9216 // CHECK13-NEXT:    [[ADD:%.*]] = add i32 [[SUB3]], 1
9217 // CHECK13-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], 1
9218 // CHECK13-NEXT:    [[SUB4:%.*]] = sub i32 [[DIV]], 1
9219 // CHECK13-NEXT:    store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_2]], align 4
9220 // CHECK13-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
9221 // CHECK13-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
9222 // CHECK13-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_UB]], align 4
9223 // CHECK13-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
9224 // CHECK13-NEXT:    store i32 [[TMP5]], i32* [[I]], align 4
9225 // CHECK13-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
9226 // CHECK13-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
9227 // CHECK13-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]]
9228 // CHECK13-NEXT:    br i1 [[CMP]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END:%.*]]
9229 // CHECK13:       simd.if.then:
9230 // CHECK13-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
9231 // CHECK13-NEXT:    store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
9232 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
9233 // CHECK13:       omp.inner.for.cond:
9234 // CHECK13-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
9235 // CHECK13-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !24
9236 // CHECK13-NEXT:    [[ADD6:%.*]] = add i32 [[TMP10]], 1
9237 // CHECK13-NEXT:    [[CMP7:%.*]] = icmp ult i32 [[TMP9]], [[ADD6]]
9238 // CHECK13-NEXT:    br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
9239 // CHECK13:       omp.inner.for.body:
9240 // CHECK13-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group !24
9241 // CHECK13-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
9242 // CHECK13-NEXT:    [[MUL:%.*]] = mul i32 [[TMP12]], 1
9243 // CHECK13-NEXT:    [[ADD8:%.*]] = add i32 [[TMP11]], [[MUL]]
9244 // CHECK13-NEXT:    store i32 [[ADD8]], i32* [[I5]], align 4, !llvm.access.group !24
9245 // CHECK13-NEXT:    [[TMP13:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !24
9246 // CHECK13-NEXT:    [[ADD9:%.*]] = add nsw i32 [[TMP13]], 1
9247 // CHECK13-NEXT:    store i32 [[ADD9]], i32* [[A]], align 4, !llvm.access.group !24
9248 // CHECK13-NEXT:    [[TMP14:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !24
9249 // CHECK13-NEXT:    [[CONV:%.*]] = sext i16 [[TMP14]] to i32
9250 // CHECK13-NEXT:    [[ADD10:%.*]] = add nsw i32 [[CONV]], 1
9251 // CHECK13-NEXT:    [[CONV11:%.*]] = trunc i32 [[ADD10]] to i16
9252 // CHECK13-NEXT:    store i16 [[CONV11]], i16* [[AA]], align 2, !llvm.access.group !24
9253 // CHECK13-NEXT:    [[TMP15:%.*]] = load i8, i8* [[AAA]], align 1, !llvm.access.group !24
9254 // CHECK13-NEXT:    [[CONV12:%.*]] = sext i8 [[TMP15]] to i32
9255 // CHECK13-NEXT:    [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1
9256 // CHECK13-NEXT:    [[CONV14:%.*]] = trunc i32 [[ADD13]] to i8
9257 // CHECK13-NEXT:    store i8 [[CONV14]], i8* [[AAA]], align 1, !llvm.access.group !24
9258 // CHECK13-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2
9259 // CHECK13-NEXT:    [[TMP16:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !24
9260 // CHECK13-NEXT:    [[ADD15:%.*]] = add nsw i32 [[TMP16]], 1
9261 // CHECK13-NEXT:    store i32 [[ADD15]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !24
9262 // CHECK13-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
9263 // CHECK13:       omp.body.continue:
9264 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
9265 // CHECK13:       omp.inner.for.inc:
9266 // CHECK13-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
9267 // CHECK13-NEXT:    [[ADD16:%.*]] = add i32 [[TMP17]], 1
9268 // CHECK13-NEXT:    store i32 [[ADD16]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
9269 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]]
9270 // CHECK13:       omp.inner.for.end:
9271 // CHECK13-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
9272 // CHECK13-NEXT:    [[TMP19:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
9273 // CHECK13-NEXT:    [[TMP20:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
9274 // CHECK13-NEXT:    [[SUB17:%.*]] = sub i32 [[TMP19]], [[TMP20]]
9275 // CHECK13-NEXT:    [[SUB18:%.*]] = sub i32 [[SUB17]], 1
9276 // CHECK13-NEXT:    [[ADD19:%.*]] = add i32 [[SUB18]], 1
9277 // CHECK13-NEXT:    [[DIV20:%.*]] = udiv i32 [[ADD19]], 1
9278 // CHECK13-NEXT:    [[MUL21:%.*]] = mul i32 [[DIV20]], 1
9279 // CHECK13-NEXT:    [[ADD22:%.*]] = add i32 [[TMP18]], [[MUL21]]
9280 // CHECK13-NEXT:    store i32 [[ADD22]], i32* [[I5]], align 4
9281 // CHECK13-NEXT:    br label [[SIMD_IF_END]]
9282 // CHECK13:       simd.if.end:
9283 // CHECK13-NEXT:    [[TMP21:%.*]] = load i32, i32* [[A]], align 4
9284 // CHECK13-NEXT:    ret i32 [[TMP21]]
9285 //
9286 //
9287 // CHECK13-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
9288 // CHECK13-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat {
9289 // CHECK13-NEXT:  entry:
9290 // CHECK13-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
9291 // CHECK13-NEXT:    [[A:%.*]] = alloca i32, align 4
9292 // CHECK13-NEXT:    [[AA:%.*]] = alloca i16, align 2
9293 // CHECK13-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
9294 // CHECK13-NEXT:    [[TMP:%.*]] = alloca i32, align 4
9295 // CHECK13-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
9296 // CHECK13-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
9297 // CHECK13-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
9298 // CHECK13-NEXT:    [[I:%.*]] = alloca i32, align 4
9299 // CHECK13-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
9300 // CHECK13-NEXT:    store i32 0, i32* [[A]], align 4
9301 // CHECK13-NEXT:    store i16 0, i16* [[AA]], align 2
9302 // CHECK13-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
9303 // CHECK13-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
9304 // CHECK13-NEXT:    [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
9305 // CHECK13-NEXT:    store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4
9306 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
9307 // CHECK13:       omp.inner.for.cond:
9308 // CHECK13-NEXT:    [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27
9309 // CHECK13-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !27
9310 // CHECK13-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
9311 // CHECK13-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
9312 // CHECK13:       omp.inner.for.body:
9313 // CHECK13-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27
9314 // CHECK13-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1
9315 // CHECK13-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
9316 // CHECK13-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !27
9317 // CHECK13-NEXT:    [[TMP4:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !27
9318 // CHECK13-NEXT:    [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1
9319 // CHECK13-NEXT:    store i32 [[ADD1]], i32* [[A]], align 4, !llvm.access.group !27
9320 // CHECK13-NEXT:    [[TMP5:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !27
9321 // CHECK13-NEXT:    [[CONV:%.*]] = sext i16 [[TMP5]] to i32
9322 // CHECK13-NEXT:    [[ADD2:%.*]] = add nsw i32 [[CONV]], 1
9323 // CHECK13-NEXT:    [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
9324 // CHECK13-NEXT:    store i16 [[CONV3]], i16* [[AA]], align 2, !llvm.access.group !27
9325 // CHECK13-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2
9326 // CHECK13-NEXT:    [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !27
9327 // CHECK13-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP6]], 1
9328 // CHECK13-NEXT:    store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !27
9329 // CHECK13-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
9330 // CHECK13:       omp.body.continue:
9331 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
9332 // CHECK13:       omp.inner.for.inc:
9333 // CHECK13-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27
9334 // CHECK13-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP7]], 1
9335 // CHECK13-NEXT:    store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27
9336 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]]
9337 // CHECK13:       omp.inner.for.end:
9338 // CHECK13-NEXT:    store i32 10, i32* [[I]], align 4
9339 // CHECK13-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
9340 // CHECK13-NEXT:    ret i32 [[TMP8]]
9341 //
9342 //
9343 // CHECK15-LABEL: define {{[^@]+}}@_Z3fooi
9344 // CHECK15-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0:[0-9]+]] {
9345 // CHECK15-NEXT:  entry:
9346 // CHECK15-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
9347 // CHECK15-NEXT:    [[A:%.*]] = alloca i32, align 4
9348 // CHECK15-NEXT:    [[AA:%.*]] = alloca i16, align 2
9349 // CHECK15-NEXT:    [[B:%.*]] = alloca [10 x float], align 4
9350 // CHECK15-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 4
9351 // CHECK15-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 4
9352 // CHECK15-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 8
9353 // CHECK15-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i32, align 4
9354 // CHECK15-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4
9355 // CHECK15-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
9356 // CHECK15-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
9357 // CHECK15-NEXT:    [[TMP:%.*]] = alloca i32, align 4
9358 // CHECK15-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
9359 // CHECK15-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
9360 // CHECK15-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
9361 // CHECK15-NEXT:    [[I:%.*]] = alloca i32, align 4
9362 // CHECK15-NEXT:    [[_TMP4:%.*]] = alloca i32, align 4
9363 // CHECK15-NEXT:    [[DOTOMP_LB5:%.*]] = alloca i32, align 4
9364 // CHECK15-NEXT:    [[DOTOMP_UB6:%.*]] = alloca i32, align 4
9365 // CHECK15-NEXT:    [[DOTOMP_IV7:%.*]] = alloca i32, align 4
9366 // CHECK15-NEXT:    [[DOTLINEAR_START:%.*]] = alloca i32, align 4
9367 // CHECK15-NEXT:    [[A8:%.*]] = alloca i32, align 4
9368 // CHECK15-NEXT:    [[A9:%.*]] = alloca i32, align 4
9369 // CHECK15-NEXT:    [[_TMP20:%.*]] = alloca i32, align 4
9370 // CHECK15-NEXT:    [[DOTOMP_LB21:%.*]] = alloca i32, align 4
9371 // CHECK15-NEXT:    [[DOTOMP_UB22:%.*]] = alloca i32, align 4
9372 // CHECK15-NEXT:    [[DOTOMP_IV23:%.*]] = alloca i32, align 4
9373 // CHECK15-NEXT:    [[I24:%.*]] = alloca i32, align 4
9374 // CHECK15-NEXT:    [[_TMP36:%.*]] = alloca i32, align 4
9375 // CHECK15-NEXT:    [[DOTOMP_LB37:%.*]] = alloca i32, align 4
9376 // CHECK15-NEXT:    [[DOTOMP_UB38:%.*]] = alloca i32, align 4
9377 // CHECK15-NEXT:    [[DOTOMP_IV39:%.*]] = alloca i32, align 4
9378 // CHECK15-NEXT:    [[I40:%.*]] = alloca i32, align 4
9379 // CHECK15-NEXT:    [[_TMP54:%.*]] = alloca i32, align 4
9380 // CHECK15-NEXT:    [[DOTOMP_LB55:%.*]] = alloca i32, align 4
9381 // CHECK15-NEXT:    [[DOTOMP_UB56:%.*]] = alloca i32, align 4
9382 // CHECK15-NEXT:    [[DOTOMP_IV57:%.*]] = alloca i32, align 4
9383 // CHECK15-NEXT:    [[I58:%.*]] = alloca i32, align 4
9384 // CHECK15-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
9385 // CHECK15-NEXT:    store i32 0, i32* [[A]], align 4
9386 // CHECK15-NEXT:    store i16 0, i16* [[AA]], align 2
9387 // CHECK15-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
9388 // CHECK15-NEXT:    [[TMP1:%.*]] = call i8* @llvm.stacksave()
9389 // CHECK15-NEXT:    store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4
9390 // CHECK15-NEXT:    [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4
9391 // CHECK15-NEXT:    store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4
9392 // CHECK15-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
9393 // CHECK15-NEXT:    [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]]
9394 // CHECK15-NEXT:    [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8
9395 // CHECK15-NEXT:    store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4
9396 // CHECK15-NEXT:    [[TMP4:%.*]] = load i32, i32* [[A]], align 4
9397 // CHECK15-NEXT:    store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4
9398 // CHECK15-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
9399 // CHECK15-NEXT:    store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_2]], align 4
9400 // CHECK15-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
9401 // CHECK15-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
9402 // CHECK15-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
9403 // CHECK15-NEXT:    store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
9404 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
9405 // CHECK15:       omp.inner.for.cond:
9406 // CHECK15-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
9407 // CHECK15-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !3
9408 // CHECK15-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
9409 // CHECK15-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
9410 // CHECK15:       omp.inner.for.body:
9411 // CHECK15-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
9412 // CHECK15-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
9413 // CHECK15-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
9414 // CHECK15-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !3
9415 // CHECK15-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
9416 // CHECK15:       omp.body.continue:
9417 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
9418 // CHECK15:       omp.inner.for.inc:
9419 // CHECK15-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
9420 // CHECK15-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
9421 // CHECK15-NEXT:    store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
9422 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]
9423 // CHECK15:       omp.inner.for.end:
9424 // CHECK15-NEXT:    store i32 10, i32* [[I]], align 4
9425 // CHECK15-NEXT:    store i32 0, i32* [[DOTOMP_LB5]], align 4
9426 // CHECK15-NEXT:    store i32 9, i32* [[DOTOMP_UB6]], align 4
9427 // CHECK15-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_LB5]], align 4
9428 // CHECK15-NEXT:    store i32 [[TMP11]], i32* [[DOTOMP_IV7]], align 4
9429 // CHECK15-NEXT:    [[TMP12:%.*]] = load i32, i32* [[A]], align 4
9430 // CHECK15-NEXT:    store i32 [[TMP12]], i32* [[DOTLINEAR_START]], align 4
9431 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_COND10:%.*]]
9432 // CHECK15:       omp.inner.for.cond10:
9433 // CHECK15-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV7]], align 4
9434 // CHECK15-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB6]], align 4
9435 // CHECK15-NEXT:    [[CMP11:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
9436 // CHECK15-NEXT:    br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY12:%.*]], label [[OMP_INNER_FOR_END19:%.*]]
9437 // CHECK15:       omp.inner.for.body12:
9438 // CHECK15-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV7]], align 4
9439 // CHECK15-NEXT:    [[MUL13:%.*]] = mul nsw i32 [[TMP15]], 1
9440 // CHECK15-NEXT:    [[ADD14:%.*]] = add nsw i32 0, [[MUL13]]
9441 // CHECK15-NEXT:    store i32 [[ADD14]], i32* [[A8]], align 4, !nontemporal !8
9442 // CHECK15-NEXT:    [[TMP16:%.*]] = load i32, i32* [[A8]], align 4, !nontemporal !8
9443 // CHECK15-NEXT:    [[ADD15:%.*]] = add nsw i32 [[TMP16]], 1
9444 // CHECK15-NEXT:    store i32 [[ADD15]], i32* [[A8]], align 4, !nontemporal !8
9445 // CHECK15-NEXT:    br label [[OMP_BODY_CONTINUE16:%.*]]
9446 // CHECK15:       omp.body.continue16:
9447 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_INC17:%.*]]
9448 // CHECK15:       omp.inner.for.inc17:
9449 // CHECK15-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV7]], align 4
9450 // CHECK15-NEXT:    [[ADD18:%.*]] = add nsw i32 [[TMP17]], 1
9451 // CHECK15-NEXT:    store i32 [[ADD18]], i32* [[DOTOMP_IV7]], align 4
9452 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_COND10]], !llvm.loop [[LOOP9:![0-9]+]]
9453 // CHECK15:       omp.inner.for.end19:
9454 // CHECK15-NEXT:    store i32 10, i32* [[A]], align 4
9455 // CHECK15-NEXT:    store i32 0, i32* [[DOTOMP_LB21]], align 4
9456 // CHECK15-NEXT:    store i32 9, i32* [[DOTOMP_UB22]], align 4
9457 // CHECK15-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTOMP_LB21]], align 4
9458 // CHECK15-NEXT:    store i32 [[TMP18]], i32* [[DOTOMP_IV23]], align 4
9459 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_COND25:%.*]]
9460 // CHECK15:       omp.inner.for.cond25:
9461 // CHECK15-NEXT:    [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV23]], align 4, !llvm.access.group !11
9462 // CHECK15-NEXT:    [[TMP20:%.*]] = load i32, i32* [[DOTOMP_UB22]], align 4, !llvm.access.group !11
9463 // CHECK15-NEXT:    [[CMP26:%.*]] = icmp sle i32 [[TMP19]], [[TMP20]]
9464 // CHECK15-NEXT:    br i1 [[CMP26]], label [[OMP_INNER_FOR_BODY27:%.*]], label [[OMP_INNER_FOR_END35:%.*]]
9465 // CHECK15:       omp.inner.for.body27:
9466 // CHECK15-NEXT:    [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV23]], align 4, !llvm.access.group !11
9467 // CHECK15-NEXT:    [[MUL28:%.*]] = mul nsw i32 [[TMP21]], 1
9468 // CHECK15-NEXT:    [[ADD29:%.*]] = add nsw i32 0, [[MUL28]]
9469 // CHECK15-NEXT:    store i32 [[ADD29]], i32* [[I24]], align 4, !llvm.access.group !11
9470 // CHECK15-NEXT:    [[TMP22:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !11
9471 // CHECK15-NEXT:    [[CONV:%.*]] = sext i16 [[TMP22]] to i32
9472 // CHECK15-NEXT:    [[ADD30:%.*]] = add nsw i32 [[CONV]], 1
9473 // CHECK15-NEXT:    [[CONV31:%.*]] = trunc i32 [[ADD30]] to i16
9474 // CHECK15-NEXT:    store i16 [[CONV31]], i16* [[AA]], align 2, !llvm.access.group !11
9475 // CHECK15-NEXT:    br label [[OMP_BODY_CONTINUE32:%.*]]
9476 // CHECK15:       omp.body.continue32:
9477 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_INC33:%.*]]
9478 // CHECK15:       omp.inner.for.inc33:
9479 // CHECK15-NEXT:    [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV23]], align 4, !llvm.access.group !11
9480 // CHECK15-NEXT:    [[ADD34:%.*]] = add nsw i32 [[TMP23]], 1
9481 // CHECK15-NEXT:    store i32 [[ADD34]], i32* [[DOTOMP_IV23]], align 4, !llvm.access.group !11
9482 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_COND25]], !llvm.loop [[LOOP12:![0-9]+]]
9483 // CHECK15:       omp.inner.for.end35:
9484 // CHECK15-NEXT:    store i32 10, i32* [[I24]], align 4
9485 // CHECK15-NEXT:    store i32 0, i32* [[DOTOMP_LB37]], align 4
9486 // CHECK15-NEXT:    store i32 9, i32* [[DOTOMP_UB38]], align 4
9487 // CHECK15-NEXT:    [[TMP24:%.*]] = load i32, i32* [[DOTOMP_LB37]], align 4
9488 // CHECK15-NEXT:    store i32 [[TMP24]], i32* [[DOTOMP_IV39]], align 4
9489 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_COND41:%.*]]
9490 // CHECK15:       omp.inner.for.cond41:
9491 // CHECK15-NEXT:    [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IV39]], align 4, !llvm.access.group !14
9492 // CHECK15-NEXT:    [[TMP26:%.*]] = load i32, i32* [[DOTOMP_UB38]], align 4, !llvm.access.group !14
9493 // CHECK15-NEXT:    [[CMP42:%.*]] = icmp sle i32 [[TMP25]], [[TMP26]]
9494 // CHECK15-NEXT:    br i1 [[CMP42]], label [[OMP_INNER_FOR_BODY43:%.*]], label [[OMP_INNER_FOR_END53:%.*]]
9495 // CHECK15:       omp.inner.for.body43:
9496 // CHECK15-NEXT:    [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV39]], align 4, !llvm.access.group !14
9497 // CHECK15-NEXT:    [[MUL44:%.*]] = mul nsw i32 [[TMP27]], 1
9498 // CHECK15-NEXT:    [[ADD45:%.*]] = add nsw i32 0, [[MUL44]]
9499 // CHECK15-NEXT:    store i32 [[ADD45]], i32* [[I40]], align 4, !llvm.access.group !14
9500 // CHECK15-NEXT:    [[TMP28:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !14
9501 // CHECK15-NEXT:    [[ADD46:%.*]] = add nsw i32 [[TMP28]], 1
9502 // CHECK15-NEXT:    store i32 [[ADD46]], i32* [[A]], align 4, !llvm.access.group !14
9503 // CHECK15-NEXT:    [[TMP29:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !14
9504 // CHECK15-NEXT:    [[CONV47:%.*]] = sext i16 [[TMP29]] to i32
9505 // CHECK15-NEXT:    [[ADD48:%.*]] = add nsw i32 [[CONV47]], 1
9506 // CHECK15-NEXT:    [[CONV49:%.*]] = trunc i32 [[ADD48]] to i16
9507 // CHECK15-NEXT:    store i16 [[CONV49]], i16* [[AA]], align 2, !llvm.access.group !14
9508 // CHECK15-NEXT:    br label [[OMP_BODY_CONTINUE50:%.*]]
9509 // CHECK15:       omp.body.continue50:
9510 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_INC51:%.*]]
9511 // CHECK15:       omp.inner.for.inc51:
9512 // CHECK15-NEXT:    [[TMP30:%.*]] = load i32, i32* [[DOTOMP_IV39]], align 4, !llvm.access.group !14
9513 // CHECK15-NEXT:    [[ADD52:%.*]] = add nsw i32 [[TMP30]], 1
9514 // CHECK15-NEXT:    store i32 [[ADD52]], i32* [[DOTOMP_IV39]], align 4, !llvm.access.group !14
9515 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_COND41]], !llvm.loop [[LOOP15:![0-9]+]]
9516 // CHECK15:       omp.inner.for.end53:
9517 // CHECK15-NEXT:    store i32 10, i32* [[I40]], align 4
9518 // CHECK15-NEXT:    store i32 0, i32* [[DOTOMP_LB55]], align 4
9519 // CHECK15-NEXT:    store i32 9, i32* [[DOTOMP_UB56]], align 4
9520 // CHECK15-NEXT:    [[TMP31:%.*]] = load i32, i32* [[DOTOMP_LB55]], align 4
9521 // CHECK15-NEXT:    store i32 [[TMP31]], i32* [[DOTOMP_IV57]], align 4
9522 // CHECK15-NEXT:    [[ARRAYDECAY:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 0
9523 // CHECK15-NEXT:    call void @llvm.assume(i1 true) [ "align"(float* [[ARRAYDECAY]], i32 16) ]
9524 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_COND59:%.*]]
9525 // CHECK15:       omp.inner.for.cond59:
9526 // CHECK15-NEXT:    [[TMP32:%.*]] = load i32, i32* [[DOTOMP_IV57]], align 4, !llvm.access.group !17
9527 // CHECK15-NEXT:    [[TMP33:%.*]] = load i32, i32* [[DOTOMP_UB56]], align 4, !llvm.access.group !17
9528 // CHECK15-NEXT:    [[CMP60:%.*]] = icmp sle i32 [[TMP32]], [[TMP33]]
9529 // CHECK15-NEXT:    br i1 [[CMP60]], label [[OMP_INNER_FOR_BODY61:%.*]], label [[OMP_INNER_FOR_END85:%.*]]
9530 // CHECK15:       omp.inner.for.body61:
9531 // CHECK15-NEXT:    [[TMP34:%.*]] = load i32, i32* [[DOTOMP_IV57]], align 4, !llvm.access.group !17
9532 // CHECK15-NEXT:    [[MUL62:%.*]] = mul nsw i32 [[TMP34]], 1
9533 // CHECK15-NEXT:    [[ADD63:%.*]] = add nsw i32 0, [[MUL62]]
9534 // CHECK15-NEXT:    store i32 [[ADD63]], i32* [[I58]], align 4, !llvm.access.group !17
9535 // CHECK15-NEXT:    [[TMP35:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !17
9536 // CHECK15-NEXT:    [[ADD64:%.*]] = add nsw i32 [[TMP35]], 1
9537 // CHECK15-NEXT:    store i32 [[ADD64]], i32* [[A]], align 4, !llvm.access.group !17
9538 // CHECK15-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2
9539 // CHECK15-NEXT:    [[TMP36:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !17
9540 // CHECK15-NEXT:    [[CONV65:%.*]] = fpext float [[TMP36]] to double
9541 // CHECK15-NEXT:    [[ADD66:%.*]] = fadd double [[CONV65]], 1.000000e+00
9542 // CHECK15-NEXT:    [[CONV67:%.*]] = fptrunc double [[ADD66]] to float
9543 // CHECK15-NEXT:    store float [[CONV67]], float* [[ARRAYIDX]], align 4, !llvm.access.group !17
9544 // CHECK15-NEXT:    [[ARRAYIDX68:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3
9545 // CHECK15-NEXT:    [[TMP37:%.*]] = load float, float* [[ARRAYIDX68]], align 4, !llvm.access.group !17
9546 // CHECK15-NEXT:    [[CONV69:%.*]] = fpext float [[TMP37]] to double
9547 // CHECK15-NEXT:    [[ADD70:%.*]] = fadd double [[CONV69]], 1.000000e+00
9548 // CHECK15-NEXT:    [[CONV71:%.*]] = fptrunc double [[ADD70]] to float
9549 // CHECK15-NEXT:    store float [[CONV71]], float* [[ARRAYIDX68]], align 4, !llvm.access.group !17
9550 // CHECK15-NEXT:    [[ARRAYIDX72:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1
9551 // CHECK15-NEXT:    [[ARRAYIDX73:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX72]], i32 0, i32 2
9552 // CHECK15-NEXT:    [[TMP38:%.*]] = load double, double* [[ARRAYIDX73]], align 8, !llvm.access.group !17
9553 // CHECK15-NEXT:    [[ADD74:%.*]] = fadd double [[TMP38]], 1.000000e+00
9554 // CHECK15-NEXT:    store double [[ADD74]], double* [[ARRAYIDX73]], align 8, !llvm.access.group !17
9555 // CHECK15-NEXT:    [[TMP39:%.*]] = mul nsw i32 1, [[TMP2]]
9556 // CHECK15-NEXT:    [[ARRAYIDX75:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP39]]
9557 // CHECK15-NEXT:    [[ARRAYIDX76:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX75]], i32 3
9558 // CHECK15-NEXT:    [[TMP40:%.*]] = load double, double* [[ARRAYIDX76]], align 8, !llvm.access.group !17
9559 // CHECK15-NEXT:    [[ADD77:%.*]] = fadd double [[TMP40]], 1.000000e+00
9560 // CHECK15-NEXT:    store double [[ADD77]], double* [[ARRAYIDX76]], align 8, !llvm.access.group !17
9561 // CHECK15-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0
9562 // CHECK15-NEXT:    [[TMP41:%.*]] = load i64, i64* [[X]], align 4, !llvm.access.group !17
9563 // CHECK15-NEXT:    [[ADD78:%.*]] = add nsw i64 [[TMP41]], 1
9564 // CHECK15-NEXT:    store i64 [[ADD78]], i64* [[X]], align 4, !llvm.access.group !17
9565 // CHECK15-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1
9566 // CHECK15-NEXT:    [[TMP42:%.*]] = load i8, i8* [[Y]], align 4, !llvm.access.group !17
9567 // CHECK15-NEXT:    [[CONV79:%.*]] = sext i8 [[TMP42]] to i32
9568 // CHECK15-NEXT:    [[ADD80:%.*]] = add nsw i32 [[CONV79]], 1
9569 // CHECK15-NEXT:    [[CONV81:%.*]] = trunc i32 [[ADD80]] to i8
9570 // CHECK15-NEXT:    store i8 [[CONV81]], i8* [[Y]], align 4, !llvm.access.group !17
9571 // CHECK15-NEXT:    br label [[OMP_BODY_CONTINUE82:%.*]]
9572 // CHECK15:       omp.body.continue82:
9573 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_INC83:%.*]]
9574 // CHECK15:       omp.inner.for.inc83:
9575 // CHECK15-NEXT:    [[TMP43:%.*]] = load i32, i32* [[DOTOMP_IV57]], align 4, !llvm.access.group !17
9576 // CHECK15-NEXT:    [[ADD84:%.*]] = add nsw i32 [[TMP43]], 1
9577 // CHECK15-NEXT:    store i32 [[ADD84]], i32* [[DOTOMP_IV57]], align 4, !llvm.access.group !17
9578 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_COND59]], !llvm.loop [[LOOP18:![0-9]+]]
9579 // CHECK15:       omp.inner.for.end85:
9580 // CHECK15-NEXT:    store i32 10, i32* [[I58]], align 4
9581 // CHECK15-NEXT:    [[TMP44:%.*]] = load i32, i32* [[A]], align 4
9582 // CHECK15-NEXT:    [[TMP45:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
9583 // CHECK15-NEXT:    call void @llvm.stackrestore(i8* [[TMP45]])
9584 // CHECK15-NEXT:    ret i32 [[TMP44]]
9585 //
9586 //
9587 // CHECK15-LABEL: define {{[^@]+}}@_Z3bari
9588 // CHECK15-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {
9589 // CHECK15-NEXT:  entry:
9590 // CHECK15-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
9591 // CHECK15-NEXT:    [[A:%.*]] = alloca i32, align 4
9592 // CHECK15-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4
9593 // CHECK15-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
9594 // CHECK15-NEXT:    store i32 0, i32* [[A]], align 4
9595 // CHECK15-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
9596 // CHECK15-NEXT:    [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]])
9597 // CHECK15-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
9598 // CHECK15-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
9599 // CHECK15-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
9600 // CHECK15-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
9601 // CHECK15-NEXT:    [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP2]])
9602 // CHECK15-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
9603 // CHECK15-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
9604 // CHECK15-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
9605 // CHECK15-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
9606 // CHECK15-NEXT:    [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]])
9607 // CHECK15-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
9608 // CHECK15-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
9609 // CHECK15-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
9610 // CHECK15-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
9611 // CHECK15-NEXT:    [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]])
9612 // CHECK15-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
9613 // CHECK15-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
9614 // CHECK15-NEXT:    store i32 [[ADD6]], i32* [[A]], align 4
9615 // CHECK15-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
9616 // CHECK15-NEXT:    ret i32 [[TMP8]]
9617 //
9618 //
9619 // CHECK15-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
9620 // CHECK15-SAME: (%struct.S1* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 {
9621 // CHECK15-NEXT:  entry:
9622 // CHECK15-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
9623 // CHECK15-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
9624 // CHECK15-NEXT:    [[B:%.*]] = alloca i32, align 4
9625 // CHECK15-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 4
9626 // CHECK15-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 4
9627 // CHECK15-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
9628 // CHECK15-NEXT:    [[TMP:%.*]] = alloca i32, align 4
9629 // CHECK15-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
9630 // CHECK15-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
9631 // CHECK15-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
9632 // CHECK15-NEXT:    [[I:%.*]] = alloca i32, align 4
9633 // CHECK15-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
9634 // CHECK15-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
9635 // CHECK15-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
9636 // CHECK15-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
9637 // CHECK15-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
9638 // CHECK15-NEXT:    store i32 [[ADD]], i32* [[B]], align 4
9639 // CHECK15-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
9640 // CHECK15-NEXT:    [[TMP2:%.*]] = call i8* @llvm.stacksave()
9641 // CHECK15-NEXT:    store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4
9642 // CHECK15-NEXT:    [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]
9643 // CHECK15-NEXT:    [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2
9644 // CHECK15-NEXT:    store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
9645 // CHECK15-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
9646 // CHECK15-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 60
9647 // CHECK15-NEXT:    [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8
9648 // CHECK15-NEXT:    store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
9649 // CHECK15-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
9650 // CHECK15-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
9651 // CHECK15-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
9652 // CHECK15-NEXT:    store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
9653 // CHECK15-NEXT:    [[TMP6:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
9654 // CHECK15-NEXT:    [[TOBOOL:%.*]] = trunc i8 [[TMP6]] to i1
9655 // CHECK15-NEXT:    br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
9656 // CHECK15:       omp_if.then:
9657 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
9658 // CHECK15:       omp.inner.for.cond:
9659 // CHECK15-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20
9660 // CHECK15-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !20
9661 // CHECK15-NEXT:    [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
9662 // CHECK15-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
9663 // CHECK15:       omp.inner.for.body:
9664 // CHECK15-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20
9665 // CHECK15-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
9666 // CHECK15-NEXT:    [[ADD3:%.*]] = add nsw i32 0, [[MUL]]
9667 // CHECK15-NEXT:    store i32 [[ADD3]], i32* [[I]], align 4, !llvm.access.group !20
9668 // CHECK15-NEXT:    [[TMP10:%.*]] = load i32, i32* [[B]], align 4, !llvm.access.group !20
9669 // CHECK15-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP10]] to double
9670 // CHECK15-NEXT:    [[ADD4:%.*]] = fadd double [[CONV]], 1.500000e+00
9671 // CHECK15-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
9672 // CHECK15-NEXT:    store double [[ADD4]], double* [[A]], align 4, !llvm.access.group !20
9673 // CHECK15-NEXT:    [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
9674 // CHECK15-NEXT:    [[TMP11:%.*]] = load double, double* [[A5]], align 4, !llvm.access.group !20
9675 // CHECK15-NEXT:    [[INC:%.*]] = fadd double [[TMP11]], 1.000000e+00
9676 // CHECK15-NEXT:    store double [[INC]], double* [[A5]], align 4, !llvm.access.group !20
9677 // CHECK15-NEXT:    [[CONV6:%.*]] = fptosi double [[INC]] to i16
9678 // CHECK15-NEXT:    [[TMP12:%.*]] = mul nsw i32 1, [[TMP1]]
9679 // CHECK15-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP12]]
9680 // CHECK15-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
9681 // CHECK15-NEXT:    store i16 [[CONV6]], i16* [[ARRAYIDX7]], align 2, !llvm.access.group !20
9682 // CHECK15-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
9683 // CHECK15:       omp.body.continue:
9684 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
9685 // CHECK15:       omp.inner.for.inc:
9686 // CHECK15-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20
9687 // CHECK15-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP13]], 1
9688 // CHECK15-NEXT:    store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20
9689 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]]
9690 // CHECK15:       omp.inner.for.end:
9691 // CHECK15-NEXT:    br label [[OMP_IF_END:%.*]]
9692 // CHECK15:       omp_if.else:
9693 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_COND9:%.*]]
9694 // CHECK15:       omp.inner.for.cond9:
9695 // CHECK15-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
9696 // CHECK15-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
9697 // CHECK15-NEXT:    [[CMP10:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
9698 // CHECK15-NEXT:    br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY11:%.*]], label [[OMP_INNER_FOR_END25:%.*]]
9699 // CHECK15:       omp.inner.for.body11:
9700 // CHECK15-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
9701 // CHECK15-NEXT:    [[MUL12:%.*]] = mul nsw i32 [[TMP16]], 1
9702 // CHECK15-NEXT:    [[ADD13:%.*]] = add nsw i32 0, [[MUL12]]
9703 // CHECK15-NEXT:    store i32 [[ADD13]], i32* [[I]], align 4
9704 // CHECK15-NEXT:    [[TMP17:%.*]] = load i32, i32* [[B]], align 4
9705 // CHECK15-NEXT:    [[CONV14:%.*]] = sitofp i32 [[TMP17]] to double
9706 // CHECK15-NEXT:    [[ADD15:%.*]] = fadd double [[CONV14]], 1.500000e+00
9707 // CHECK15-NEXT:    [[A16:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
9708 // CHECK15-NEXT:    store double [[ADD15]], double* [[A16]], align 4
9709 // CHECK15-NEXT:    [[A17:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
9710 // CHECK15-NEXT:    [[TMP18:%.*]] = load double, double* [[A17]], align 4
9711 // CHECK15-NEXT:    [[INC18:%.*]] = fadd double [[TMP18]], 1.000000e+00
9712 // CHECK15-NEXT:    store double [[INC18]], double* [[A17]], align 4
9713 // CHECK15-NEXT:    [[CONV19:%.*]] = fptosi double [[INC18]] to i16
9714 // CHECK15-NEXT:    [[TMP19:%.*]] = mul nsw i32 1, [[TMP1]]
9715 // CHECK15-NEXT:    [[ARRAYIDX20:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP19]]
9716 // CHECK15-NEXT:    [[ARRAYIDX21:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX20]], i32 1
9717 // CHECK15-NEXT:    store i16 [[CONV19]], i16* [[ARRAYIDX21]], align 2
9718 // CHECK15-NEXT:    br label [[OMP_BODY_CONTINUE22:%.*]]
9719 // CHECK15:       omp.body.continue22:
9720 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_INC23:%.*]]
9721 // CHECK15:       omp.inner.for.inc23:
9722 // CHECK15-NEXT:    [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
9723 // CHECK15-NEXT:    [[ADD24:%.*]] = add nsw i32 [[TMP20]], 1
9724 // CHECK15-NEXT:    store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4
9725 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_COND9]], !llvm.loop [[LOOP23:![0-9]+]]
9726 // CHECK15:       omp.inner.for.end25:
9727 // CHECK15-NEXT:    br label [[OMP_IF_END]]
9728 // CHECK15:       omp_if.end:
9729 // CHECK15-NEXT:    store i32 10, i32* [[I]], align 4
9730 // CHECK15-NEXT:    [[TMP21:%.*]] = mul nsw i32 1, [[TMP1]]
9731 // CHECK15-NEXT:    [[ARRAYIDX26:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP21]]
9732 // CHECK15-NEXT:    [[ARRAYIDX27:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX26]], i32 1
9733 // CHECK15-NEXT:    [[TMP22:%.*]] = load i16, i16* [[ARRAYIDX27]], align 2
9734 // CHECK15-NEXT:    [[CONV28:%.*]] = sext i16 [[TMP22]] to i32
9735 // CHECK15-NEXT:    [[TMP23:%.*]] = load i32, i32* [[B]], align 4
9736 // CHECK15-NEXT:    [[ADD29:%.*]] = add nsw i32 [[CONV28]], [[TMP23]]
9737 // CHECK15-NEXT:    [[TMP24:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
9738 // CHECK15-NEXT:    call void @llvm.stackrestore(i8* [[TMP24]])
9739 // CHECK15-NEXT:    ret i32 [[ADD29]]
9740 //
9741 //
9742 // CHECK15-LABEL: define {{[^@]+}}@_ZL7fstatici
9743 // CHECK15-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {
9744 // CHECK15-NEXT:  entry:
9745 // CHECK15-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
9746 // CHECK15-NEXT:    [[A:%.*]] = alloca i32, align 4
9747 // CHECK15-NEXT:    [[AA:%.*]] = alloca i16, align 2
9748 // CHECK15-NEXT:    [[AAA:%.*]] = alloca i8, align 1
9749 // CHECK15-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
9750 // CHECK15-NEXT:    [[TMP:%.*]] = alloca i32, align 4
9751 // CHECK15-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
9752 // CHECK15-NEXT:    [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
9753 // CHECK15-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
9754 // CHECK15-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
9755 // CHECK15-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
9756 // CHECK15-NEXT:    [[I:%.*]] = alloca i32, align 4
9757 // CHECK15-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
9758 // CHECK15-NEXT:    [[I5:%.*]] = alloca i32, align 4
9759 // CHECK15-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
9760 // CHECK15-NEXT:    store i32 0, i32* [[A]], align 4
9761 // CHECK15-NEXT:    store i16 0, i16* [[AA]], align 2
9762 // CHECK15-NEXT:    store i8 0, i8* [[AAA]], align 1
9763 // CHECK15-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
9764 // CHECK15-NEXT:    store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4
9765 // CHECK15-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
9766 // CHECK15-NEXT:    store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_1]], align 4
9767 // CHECK15-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
9768 // CHECK15-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
9769 // CHECK15-NEXT:    [[SUB:%.*]] = sub i32 [[TMP2]], [[TMP3]]
9770 // CHECK15-NEXT:    [[SUB3:%.*]] = sub i32 [[SUB]], 1
9771 // CHECK15-NEXT:    [[ADD:%.*]] = add i32 [[SUB3]], 1
9772 // CHECK15-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], 1
9773 // CHECK15-NEXT:    [[SUB4:%.*]] = sub i32 [[DIV]], 1
9774 // CHECK15-NEXT:    store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_2]], align 4
9775 // CHECK15-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
9776 // CHECK15-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
9777 // CHECK15-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_UB]], align 4
9778 // CHECK15-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
9779 // CHECK15-NEXT:    store i32 [[TMP5]], i32* [[I]], align 4
9780 // CHECK15-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
9781 // CHECK15-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
9782 // CHECK15-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]]
9783 // CHECK15-NEXT:    br i1 [[CMP]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END:%.*]]
9784 // CHECK15:       simd.if.then:
9785 // CHECK15-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
9786 // CHECK15-NEXT:    store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
9787 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
9788 // CHECK15:       omp.inner.for.cond:
9789 // CHECK15-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25
9790 // CHECK15-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !25
9791 // CHECK15-NEXT:    [[ADD6:%.*]] = add i32 [[TMP10]], 1
9792 // CHECK15-NEXT:    [[CMP7:%.*]] = icmp ult i32 [[TMP9]], [[ADD6]]
9793 // CHECK15-NEXT:    br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
9794 // CHECK15:       omp.inner.for.body:
9795 // CHECK15-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group !25
9796 // CHECK15-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25
9797 // CHECK15-NEXT:    [[MUL:%.*]] = mul i32 [[TMP12]], 1
9798 // CHECK15-NEXT:    [[ADD8:%.*]] = add i32 [[TMP11]], [[MUL]]
9799 // CHECK15-NEXT:    store i32 [[ADD8]], i32* [[I5]], align 4, !llvm.access.group !25
9800 // CHECK15-NEXT:    [[TMP13:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !25
9801 // CHECK15-NEXT:    [[ADD9:%.*]] = add nsw i32 [[TMP13]], 1
9802 // CHECK15-NEXT:    store i32 [[ADD9]], i32* [[A]], align 4, !llvm.access.group !25
9803 // CHECK15-NEXT:    [[TMP14:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !25
9804 // CHECK15-NEXT:    [[CONV:%.*]] = sext i16 [[TMP14]] to i32
9805 // CHECK15-NEXT:    [[ADD10:%.*]] = add nsw i32 [[CONV]], 1
9806 // CHECK15-NEXT:    [[CONV11:%.*]] = trunc i32 [[ADD10]] to i16
9807 // CHECK15-NEXT:    store i16 [[CONV11]], i16* [[AA]], align 2, !llvm.access.group !25
9808 // CHECK15-NEXT:    [[TMP15:%.*]] = load i8, i8* [[AAA]], align 1, !llvm.access.group !25
9809 // CHECK15-NEXT:    [[CONV12:%.*]] = sext i8 [[TMP15]] to i32
9810 // CHECK15-NEXT:    [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1
9811 // CHECK15-NEXT:    [[CONV14:%.*]] = trunc i32 [[ADD13]] to i8
9812 // CHECK15-NEXT:    store i8 [[CONV14]], i8* [[AAA]], align 1, !llvm.access.group !25
9813 // CHECK15-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2
9814 // CHECK15-NEXT:    [[TMP16:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !25
9815 // CHECK15-NEXT:    [[ADD15:%.*]] = add nsw i32 [[TMP16]], 1
9816 // CHECK15-NEXT:    store i32 [[ADD15]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !25
9817 // CHECK15-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
9818 // CHECK15:       omp.body.continue:
9819 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
9820 // CHECK15:       omp.inner.for.inc:
9821 // CHECK15-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25
9822 // CHECK15-NEXT:    [[ADD16:%.*]] = add i32 [[TMP17]], 1
9823 // CHECK15-NEXT:    store i32 [[ADD16]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25
9824 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP26:![0-9]+]]
9825 // CHECK15:       omp.inner.for.end:
9826 // CHECK15-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
9827 // CHECK15-NEXT:    [[TMP19:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
9828 // CHECK15-NEXT:    [[TMP20:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
9829 // CHECK15-NEXT:    [[SUB17:%.*]] = sub i32 [[TMP19]], [[TMP20]]
9830 // CHECK15-NEXT:    [[SUB18:%.*]] = sub i32 [[SUB17]], 1
9831 // CHECK15-NEXT:    [[ADD19:%.*]] = add i32 [[SUB18]], 1
9832 // CHECK15-NEXT:    [[DIV20:%.*]] = udiv i32 [[ADD19]], 1
9833 // CHECK15-NEXT:    [[MUL21:%.*]] = mul i32 [[DIV20]], 1
9834 // CHECK15-NEXT:    [[ADD22:%.*]] = add i32 [[TMP18]], [[MUL21]]
9835 // CHECK15-NEXT:    store i32 [[ADD22]], i32* [[I5]], align 4
9836 // CHECK15-NEXT:    br label [[SIMD_IF_END]]
9837 // CHECK15:       simd.if.end:
9838 // CHECK15-NEXT:    [[TMP21:%.*]] = load i32, i32* [[A]], align 4
9839 // CHECK15-NEXT:    ret i32 [[TMP21]]
9840 //
9841 //
9842 // CHECK15-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
9843 // CHECK15-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat {
9844 // CHECK15-NEXT:  entry:
9845 // CHECK15-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
9846 // CHECK15-NEXT:    [[A:%.*]] = alloca i32, align 4
9847 // CHECK15-NEXT:    [[AA:%.*]] = alloca i16, align 2
9848 // CHECK15-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
9849 // CHECK15-NEXT:    [[TMP:%.*]] = alloca i32, align 4
9850 // CHECK15-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
9851 // CHECK15-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
9852 // CHECK15-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
9853 // CHECK15-NEXT:    [[I:%.*]] = alloca i32, align 4
9854 // CHECK15-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
9855 // CHECK15-NEXT:    store i32 0, i32* [[A]], align 4
9856 // CHECK15-NEXT:    store i16 0, i16* [[AA]], align 2
9857 // CHECK15-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
9858 // CHECK15-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
9859 // CHECK15-NEXT:    [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
9860 // CHECK15-NEXT:    store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4
9861 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
9862 // CHECK15:       omp.inner.for.cond:
9863 // CHECK15-NEXT:    [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28
9864 // CHECK15-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !28
9865 // CHECK15-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
9866 // CHECK15-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
9867 // CHECK15:       omp.inner.for.body:
9868 // CHECK15-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28
9869 // CHECK15-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1
9870 // CHECK15-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
9871 // CHECK15-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !28
9872 // CHECK15-NEXT:    [[TMP4:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !28
9873 // CHECK15-NEXT:    [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1
9874 // CHECK15-NEXT:    store i32 [[ADD1]], i32* [[A]], align 4, !llvm.access.group !28
9875 // CHECK15-NEXT:    [[TMP5:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !28
9876 // CHECK15-NEXT:    [[CONV:%.*]] = sext i16 [[TMP5]] to i32
9877 // CHECK15-NEXT:    [[ADD2:%.*]] = add nsw i32 [[CONV]], 1
9878 // CHECK15-NEXT:    [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
9879 // CHECK15-NEXT:    store i16 [[CONV3]], i16* [[AA]], align 2, !llvm.access.group !28
9880 // CHECK15-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2
9881 // CHECK15-NEXT:    [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !28
9882 // CHECK15-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP6]], 1
9883 // CHECK15-NEXT:    store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !28
9884 // CHECK15-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
9885 // CHECK15:       omp.body.continue:
9886 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
9887 // CHECK15:       omp.inner.for.inc:
9888 // CHECK15-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28
9889 // CHECK15-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP7]], 1
9890 // CHECK15-NEXT:    store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28
9891 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP29:![0-9]+]]
9892 // CHECK15:       omp.inner.for.end:
9893 // CHECK15-NEXT:    store i32 10, i32* [[I]], align 4
9894 // CHECK15-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
9895 // CHECK15-NEXT:    ret i32 [[TMP8]]
9896 //
9897 //
9898 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97
9899 // CHECK17-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] {
9900 // CHECK17-NEXT:  entry:
9901 // CHECK17-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
9902 // CHECK17-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
9903 // CHECK17-NEXT:    [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8
9904 // CHECK17-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
9905 // CHECK17-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]])
9906 // CHECK17-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
9907 // CHECK17-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
9908 // CHECK17-NEXT:    store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8
9909 // CHECK17-NEXT:    [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
9910 // CHECK17-NEXT:    [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
9911 // CHECK17-NEXT:    [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32*
9912 // CHECK17-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 4
9913 // CHECK17-NEXT:    [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 4
9914 // CHECK17-NEXT:    call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
9915 // CHECK17-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
9916 // CHECK17-NEXT:    [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
9917 // CHECK17-NEXT:    store i16 [[TMP3]], i16* [[CONV5]], align 2
9918 // CHECK17-NEXT:    [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
9919 // CHECK17-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]])
9920 // CHECK17-NEXT:    ret void
9921 //
9922 //
9923 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined.
9924 // CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR1:[0-9]+]] {
9925 // CHECK17-NEXT:  entry:
9926 // CHECK17-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
9927 // CHECK17-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
9928 // CHECK17-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
9929 // CHECK17-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
9930 // CHECK17-NEXT:    [[TMP:%.*]] = alloca i32, align 4
9931 // CHECK17-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
9932 // CHECK17-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
9933 // CHECK17-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
9934 // CHECK17-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
9935 // CHECK17-NEXT:    [[I:%.*]] = alloca i32, align 4
9936 // CHECK17-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
9937 // CHECK17-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
9938 // CHECK17-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
9939 // CHECK17-NEXT:    [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
9940 // CHECK17-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
9941 // CHECK17-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
9942 // CHECK17-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
9943 // CHECK17-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
9944 // CHECK17-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
9945 // CHECK17-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
9946 // CHECK17-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
9947 // CHECK17-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
9948 // CHECK17-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
9949 // CHECK17-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
9950 // CHECK17:       cond.true:
9951 // CHECK17-NEXT:    br label [[COND_END:%.*]]
9952 // CHECK17:       cond.false:
9953 // CHECK17-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
9954 // CHECK17-NEXT:    br label [[COND_END]]
9955 // CHECK17:       cond.end:
9956 // CHECK17-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
9957 // CHECK17-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
9958 // CHECK17-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
9959 // CHECK17-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
9960 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
9961 // CHECK17:       omp.inner.for.cond:
9962 // CHECK17-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
9963 // CHECK17-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !11
9964 // CHECK17-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
9965 // CHECK17-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
9966 // CHECK17:       omp.inner.for.body:
9967 // CHECK17-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
9968 // CHECK17-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
9969 // CHECK17-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
9970 // CHECK17-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11
9971 // CHECK17-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
9972 // CHECK17:       omp.body.continue:
9973 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
9974 // CHECK17:       omp.inner.for.inc:
9975 // CHECK17-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
9976 // CHECK17-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
9977 // CHECK17-NEXT:    store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
9978 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]
9979 // CHECK17:       omp.inner.for.end:
9980 // CHECK17-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
9981 // CHECK17:       omp.loop.exit:
9982 // CHECK17-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
9983 // CHECK17-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
9984 // CHECK17-NEXT:    [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0
9985 // CHECK17-NEXT:    br i1 [[TMP10]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
9986 // CHECK17:       .omp.final.then:
9987 // CHECK17-NEXT:    store i32 10, i32* [[I]], align 4
9988 // CHECK17-NEXT:    br label [[DOTOMP_FINAL_DONE]]
9989 // CHECK17:       .omp.final.done:
9990 // CHECK17-NEXT:    ret void
9991 //
9992 //
9993 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111
9994 // CHECK17-SAME: (i64 noundef [[AA:%.*]]) #[[ATTR0]] {
9995 // CHECK17-NEXT:  entry:
9996 // CHECK17-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
9997 // CHECK17-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
9998 // CHECK17-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
9999 // CHECK17-NEXT:    [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
10000 // CHECK17-NEXT:    [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
10001 // CHECK17-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
10002 // CHECK17-NEXT:    store i16 [[TMP0]], i16* [[CONV1]], align 2
10003 // CHECK17-NEXT:    [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
10004 // CHECK17-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]])
10005 // CHECK17-NEXT:    ret void
10006 //
10007 //
10008 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..1
10009 // CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR1]] {
10010 // CHECK17-NEXT:  entry:
10011 // CHECK17-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
10012 // CHECK17-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
10013 // CHECK17-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
10014 // CHECK17-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
10015 // CHECK17-NEXT:    [[TMP:%.*]] = alloca i32, align 4
10016 // CHECK17-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
10017 // CHECK17-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
10018 // CHECK17-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
10019 // CHECK17-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
10020 // CHECK17-NEXT:    [[I:%.*]] = alloca i32, align 4
10021 // CHECK17-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
10022 // CHECK17-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
10023 // CHECK17-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
10024 // CHECK17-NEXT:    [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
10025 // CHECK17-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
10026 // CHECK17-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
10027 // CHECK17-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
10028 // CHECK17-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
10029 // CHECK17-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
10030 // CHECK17-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
10031 // CHECK17-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
10032 // CHECK17-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
10033 // CHECK17-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
10034 // CHECK17-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
10035 // CHECK17:       cond.true:
10036 // CHECK17-NEXT:    br label [[COND_END:%.*]]
10037 // CHECK17:       cond.false:
10038 // CHECK17-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
10039 // CHECK17-NEXT:    br label [[COND_END]]
10040 // CHECK17:       cond.end:
10041 // CHECK17-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
10042 // CHECK17-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
10043 // CHECK17-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
10044 // CHECK17-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
10045 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
10046 // CHECK17:       omp.inner.for.cond:
10047 // CHECK17-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
10048 // CHECK17-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !18
10049 // CHECK17-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
10050 // CHECK17-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
10051 // CHECK17:       omp.inner.for.body:
10052 // CHECK17-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
10053 // CHECK17-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
10054 // CHECK17-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
10055 // CHECK17-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18
10056 // CHECK17-NEXT:    [[TMP8:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !18
10057 // CHECK17-NEXT:    [[CONV2:%.*]] = sext i16 [[TMP8]] to i32
10058 // CHECK17-NEXT:    [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
10059 // CHECK17-NEXT:    [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
10060 // CHECK17-NEXT:    store i16 [[CONV4]], i16* [[CONV]], align 2, !llvm.access.group !18
10061 // CHECK17-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
10062 // CHECK17:       omp.body.continue:
10063 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
10064 // CHECK17:       omp.inner.for.inc:
10065 // CHECK17-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
10066 // CHECK17-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP9]], 1
10067 // CHECK17-NEXT:    store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
10068 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]
10069 // CHECK17:       omp.inner.for.end:
10070 // CHECK17-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
10071 // CHECK17:       omp.loop.exit:
10072 // CHECK17-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
10073 // CHECK17-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
10074 // CHECK17-NEXT:    [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0
10075 // CHECK17-NEXT:    br i1 [[TMP11]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
10076 // CHECK17:       .omp.final.then:
10077 // CHECK17-NEXT:    store i32 10, i32* [[I]], align 4
10078 // CHECK17-NEXT:    br label [[DOTOMP_FINAL_DONE]]
10079 // CHECK17:       .omp.final.done:
10080 // CHECK17-NEXT:    ret void
10081 //
10082 //
10083 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118
10084 // CHECK17-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] {
10085 // CHECK17-NEXT:  entry:
10086 // CHECK17-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
10087 // CHECK17-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
10088 // CHECK17-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
10089 // CHECK17-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
10090 // CHECK17-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
10091 // CHECK17-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
10092 // CHECK17-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
10093 // CHECK17-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
10094 // CHECK17-NEXT:    [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
10095 // CHECK17-NEXT:    [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
10096 // CHECK17-NEXT:    store i32 [[TMP0]], i32* [[CONV2]], align 4
10097 // CHECK17-NEXT:    [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
10098 // CHECK17-NEXT:    [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
10099 // CHECK17-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
10100 // CHECK17-NEXT:    store i16 [[TMP2]], i16* [[CONV3]], align 2
10101 // CHECK17-NEXT:    [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
10102 // CHECK17-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
10103 // CHECK17-NEXT:    ret void
10104 //
10105 //
10106 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..2
10107 // CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR1]] {
10108 // CHECK17-NEXT:  entry:
10109 // CHECK17-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
10110 // CHECK17-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
10111 // CHECK17-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
10112 // CHECK17-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
10113 // CHECK17-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
10114 // CHECK17-NEXT:    [[TMP:%.*]] = alloca i32, align 4
10115 // CHECK17-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
10116 // CHECK17-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
10117 // CHECK17-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
10118 // CHECK17-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
10119 // CHECK17-NEXT:    [[I:%.*]] = alloca i32, align 4
10120 // CHECK17-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
10121 // CHECK17-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
10122 // CHECK17-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
10123 // CHECK17-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
10124 // CHECK17-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
10125 // CHECK17-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
10126 // CHECK17-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
10127 // CHECK17-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
10128 // CHECK17-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
10129 // CHECK17-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
10130 // CHECK17-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
10131 // CHECK17-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
10132 // CHECK17-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
10133 // CHECK17-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
10134 // CHECK17-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
10135 // CHECK17-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
10136 // CHECK17:       cond.true:
10137 // CHECK17-NEXT:    br label [[COND_END:%.*]]
10138 // CHECK17:       cond.false:
10139 // CHECK17-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
10140 // CHECK17-NEXT:    br label [[COND_END]]
10141 // CHECK17:       cond.end:
10142 // CHECK17-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
10143 // CHECK17-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
10144 // CHECK17-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
10145 // CHECK17-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
10146 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
10147 // CHECK17:       omp.inner.for.cond:
10148 // CHECK17-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
10149 // CHECK17-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !21
10150 // CHECK17-NEXT:    [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
10151 // CHECK17-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
10152 // CHECK17:       omp.inner.for.body:
10153 // CHECK17-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
10154 // CHECK17-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
10155 // CHECK17-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
10156 // CHECK17-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !21
10157 // CHECK17-NEXT:    [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !21
10158 // CHECK17-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
10159 // CHECK17-NEXT:    store i32 [[ADD3]], i32* [[CONV]], align 4, !llvm.access.group !21
10160 // CHECK17-NEXT:    [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 2, !llvm.access.group !21
10161 // CHECK17-NEXT:    [[CONV4:%.*]] = sext i16 [[TMP9]] to i32
10162 // CHECK17-NEXT:    [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
10163 // CHECK17-NEXT:    [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
10164 // CHECK17-NEXT:    store i16 [[CONV6]], i16* [[CONV1]], align 2, !llvm.access.group !21
10165 // CHECK17-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
10166 // CHECK17:       omp.body.continue:
10167 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
10168 // CHECK17:       omp.inner.for.inc:
10169 // CHECK17-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
10170 // CHECK17-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1
10171 // CHECK17-NEXT:    store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
10172 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]]
10173 // CHECK17:       omp.inner.for.end:
10174 // CHECK17-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
10175 // CHECK17:       omp.loop.exit:
10176 // CHECK17-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
10177 // CHECK17-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
10178 // CHECK17-NEXT:    [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
10179 // CHECK17-NEXT:    br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
10180 // CHECK17:       .omp.final.then:
10181 // CHECK17-NEXT:    store i32 10, i32* [[I]], align 4
10182 // CHECK17-NEXT:    br label [[DOTOMP_FINAL_DONE]]
10183 // CHECK17:       .omp.final.done:
10184 // CHECK17-NEXT:    ret void
10185 //
10186 //
10187 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142
10188 // CHECK17-SAME: (i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] {
10189 // CHECK17-NEXT:  entry:
10190 // CHECK17-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
10191 // CHECK17-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
10192 // CHECK17-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
10193 // CHECK17-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 8
10194 // CHECK17-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
10195 // CHECK17-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
10196 // CHECK17-NEXT:    [[VLA_ADDR4:%.*]] = alloca i64, align 8
10197 // CHECK17-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 8
10198 // CHECK17-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
10199 // CHECK17-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
10200 // CHECK17-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
10201 // CHECK17-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
10202 // CHECK17-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
10203 // CHECK17-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 8
10204 // CHECK17-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
10205 // CHECK17-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
10206 // CHECK17-NEXT:    store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
10207 // CHECK17-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 8
10208 // CHECK17-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
10209 // CHECK17-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
10210 // CHECK17-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
10211 // CHECK17-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
10212 // CHECK17-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
10213 // CHECK17-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
10214 // CHECK17-NEXT:    [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
10215 // CHECK17-NEXT:    [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
10216 // CHECK17-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
10217 // CHECK17-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
10218 // CHECK17-NEXT:    [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
10219 // CHECK17-NEXT:    [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
10220 // CHECK17-NEXT:    store i32 [[TMP8]], i32* [[CONV5]], align 4
10221 // CHECK17-NEXT:    [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
10222 // CHECK17-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]])
10223 // CHECK17-NEXT:    ret void
10224 //
10225 //
10226 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..3
10227 // CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR1]] {
10228 // CHECK17-NEXT:  entry:
10229 // CHECK17-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
10230 // CHECK17-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
10231 // CHECK17-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
10232 // CHECK17-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
10233 // CHECK17-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
10234 // CHECK17-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 8
10235 // CHECK17-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
10236 // CHECK17-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
10237 // CHECK17-NEXT:    [[VLA_ADDR4:%.*]] = alloca i64, align 8
10238 // CHECK17-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 8
10239 // CHECK17-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
10240 // CHECK17-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
10241 // CHECK17-NEXT:    [[TMP:%.*]] = alloca i32, align 4
10242 // CHECK17-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
10243 // CHECK17-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
10244 // CHECK17-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
10245 // CHECK17-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
10246 // CHECK17-NEXT:    [[I:%.*]] = alloca i32, align 4
10247 // CHECK17-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
10248 // CHECK17-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
10249 // CHECK17-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
10250 // CHECK17-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
10251 // CHECK17-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
10252 // CHECK17-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 8
10253 // CHECK17-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
10254 // CHECK17-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
10255 // CHECK17-NEXT:    store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
10256 // CHECK17-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 8
10257 // CHECK17-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
10258 // CHECK17-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
10259 // CHECK17-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
10260 // CHECK17-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
10261 // CHECK17-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
10262 // CHECK17-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
10263 // CHECK17-NEXT:    [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
10264 // CHECK17-NEXT:    [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
10265 // CHECK17-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
10266 // CHECK17-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
10267 // CHECK17-NEXT:    [[ARRAYDECAY:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 0
10268 // CHECK17-NEXT:    call void @llvm.assume(i1 true) [ "align"(float* [[ARRAYDECAY]], i64 16) ]
10269 // CHECK17-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
10270 // CHECK17-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
10271 // CHECK17-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
10272 // CHECK17-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
10273 // CHECK17-NEXT:    [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
10274 // CHECK17-NEXT:    [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4
10275 // CHECK17-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
10276 // CHECK17-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
10277 // CHECK17-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP10]], 9
10278 // CHECK17-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
10279 // CHECK17:       cond.true:
10280 // CHECK17-NEXT:    br label [[COND_END:%.*]]
10281 // CHECK17:       cond.false:
10282 // CHECK17-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
10283 // CHECK17-NEXT:    br label [[COND_END]]
10284 // CHECK17:       cond.end:
10285 // CHECK17-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ]
10286 // CHECK17-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
10287 // CHECK17-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
10288 // CHECK17-NEXT:    store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4
10289 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
10290 // CHECK17:       omp.inner.for.cond:
10291 // CHECK17-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
10292 // CHECK17-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !24
10293 // CHECK17-NEXT:    [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
10294 // CHECK17-NEXT:    br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
10295 // CHECK17:       omp.inner.for.body:
10296 // CHECK17-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
10297 // CHECK17-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1
10298 // CHECK17-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
10299 // CHECK17-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !24
10300 // CHECK17-NEXT:    [[TMP16:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !24
10301 // CHECK17-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP16]], 1
10302 // CHECK17-NEXT:    store i32 [[ADD6]], i32* [[CONV]], align 4, !llvm.access.group !24
10303 // CHECK17-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
10304 // CHECK17-NEXT:    [[TMP17:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !24
10305 // CHECK17-NEXT:    [[CONV7:%.*]] = fpext float [[TMP17]] to double
10306 // CHECK17-NEXT:    [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00
10307 // CHECK17-NEXT:    [[CONV9:%.*]] = fptrunc double [[ADD8]] to float
10308 // CHECK17-NEXT:    store float [[CONV9]], float* [[ARRAYIDX]], align 4, !llvm.access.group !24
10309 // CHECK17-NEXT:    [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3
10310 // CHECK17-NEXT:    [[TMP18:%.*]] = load float, float* [[ARRAYIDX10]], align 4, !llvm.access.group !24
10311 // CHECK17-NEXT:    [[CONV11:%.*]] = fpext float [[TMP18]] to double
10312 // CHECK17-NEXT:    [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00
10313 // CHECK17-NEXT:    [[CONV13:%.*]] = fptrunc double [[ADD12]] to float
10314 // CHECK17-NEXT:    store float [[CONV13]], float* [[ARRAYIDX10]], align 4, !llvm.access.group !24
10315 // CHECK17-NEXT:    [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1
10316 // CHECK17-NEXT:    [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX14]], i64 0, i64 2
10317 // CHECK17-NEXT:    [[TMP19:%.*]] = load double, double* [[ARRAYIDX15]], align 8, !llvm.access.group !24
10318 // CHECK17-NEXT:    [[ADD16:%.*]] = fadd double [[TMP19]], 1.000000e+00
10319 // CHECK17-NEXT:    store double [[ADD16]], double* [[ARRAYIDX15]], align 8, !llvm.access.group !24
10320 // CHECK17-NEXT:    [[TMP20:%.*]] = mul nsw i64 1, [[TMP5]]
10321 // CHECK17-NEXT:    [[ARRAYIDX17:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP20]]
10322 // CHECK17-NEXT:    [[ARRAYIDX18:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX17]], i64 3
10323 // CHECK17-NEXT:    [[TMP21:%.*]] = load double, double* [[ARRAYIDX18]], align 8, !llvm.access.group !24
10324 // CHECK17-NEXT:    [[ADD19:%.*]] = fadd double [[TMP21]], 1.000000e+00
10325 // CHECK17-NEXT:    store double [[ADD19]], double* [[ARRAYIDX18]], align 8, !llvm.access.group !24
10326 // CHECK17-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0
10327 // CHECK17-NEXT:    [[TMP22:%.*]] = load i64, i64* [[X]], align 8, !llvm.access.group !24
10328 // CHECK17-NEXT:    [[ADD20:%.*]] = add nsw i64 [[TMP22]], 1
10329 // CHECK17-NEXT:    store i64 [[ADD20]], i64* [[X]], align 8, !llvm.access.group !24
10330 // CHECK17-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1
10331 // CHECK17-NEXT:    [[TMP23:%.*]] = load i8, i8* [[Y]], align 8, !llvm.access.group !24
10332 // CHECK17-NEXT:    [[CONV21:%.*]] = sext i8 [[TMP23]] to i32
10333 // CHECK17-NEXT:    [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1
10334 // CHECK17-NEXT:    [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8
10335 // CHECK17-NEXT:    store i8 [[CONV23]], i8* [[Y]], align 8, !llvm.access.group !24
10336 // CHECK17-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
10337 // CHECK17:       omp.body.continue:
10338 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
10339 // CHECK17:       omp.inner.for.inc:
10340 // CHECK17-NEXT:    [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
10341 // CHECK17-NEXT:    [[ADD24:%.*]] = add nsw i32 [[TMP24]], 1
10342 // CHECK17-NEXT:    store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
10343 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]]
10344 // CHECK17:       omp.inner.for.end:
10345 // CHECK17-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
10346 // CHECK17:       omp.loop.exit:
10347 // CHECK17-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]])
10348 // CHECK17-NEXT:    [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
10349 // CHECK17-NEXT:    [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
10350 // CHECK17-NEXT:    br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
10351 // CHECK17:       .omp.final.then:
10352 // CHECK17-NEXT:    store i32 10, i32* [[I]], align 4
10353 // CHECK17-NEXT:    br label [[DOTOMP_FINAL_DONE]]
10354 // CHECK17:       .omp.final.done:
10355 // CHECK17-NEXT:    ret void
10356 //
10357 //
10358 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197
10359 // CHECK17-SAME: (i64 noundef [[A:%.*]], i64 noundef [[N:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
10360 // CHECK17-NEXT:  entry:
10361 // CHECK17-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
10362 // CHECK17-NEXT:    [[N_ADDR:%.*]] = alloca i64, align 8
10363 // CHECK17-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
10364 // CHECK17-NEXT:    [[AAA_ADDR:%.*]] = alloca i64, align 8
10365 // CHECK17-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
10366 // CHECK17-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
10367 // CHECK17-NEXT:    [[N_CASTED:%.*]] = alloca i64, align 8
10368 // CHECK17-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
10369 // CHECK17-NEXT:    [[AAA_CASTED:%.*]] = alloca i64, align 8
10370 // CHECK17-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
10371 // CHECK17-NEXT:    store i64 [[N]], i64* [[N_ADDR]], align 8
10372 // CHECK17-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
10373 // CHECK17-NEXT:    store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
10374 // CHECK17-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
10375 // CHECK17-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
10376 // CHECK17-NEXT:    [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32*
10377 // CHECK17-NEXT:    [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
10378 // CHECK17-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
10379 // CHECK17-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
10380 // CHECK17-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
10381 // CHECK17-NEXT:    [[CONV4:%.*]] = bitcast i64* [[A_CASTED]] to i32*
10382 // CHECK17-NEXT:    store i32 [[TMP1]], i32* [[CONV4]], align 4
10383 // CHECK17-NEXT:    [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
10384 // CHECK17-NEXT:    [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 4
10385 // CHECK17-NEXT:    [[CONV5:%.*]] = bitcast i64* [[N_CASTED]] to i32*
10386 // CHECK17-NEXT:    store i32 [[TMP3]], i32* [[CONV5]], align 4
10387 // CHECK17-NEXT:    [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8
10388 // CHECK17-NEXT:    [[TMP5:%.*]] = load i16, i16* [[CONV2]], align 2
10389 // CHECK17-NEXT:    [[CONV6:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
10390 // CHECK17-NEXT:    store i16 [[TMP5]], i16* [[CONV6]], align 2
10391 // CHECK17-NEXT:    [[TMP6:%.*]] = load i64, i64* [[AA_CASTED]], align 8
10392 // CHECK17-NEXT:    [[TMP7:%.*]] = load i8, i8* [[CONV3]], align 1
10393 // CHECK17-NEXT:    [[CONV7:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
10394 // CHECK17-NEXT:    store i8 [[TMP7]], i8* [[CONV7]], align 1
10395 // CHECK17-NEXT:    [[TMP8:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
10396 // CHECK17-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]], [10 x i32]* [[TMP0]])
10397 // CHECK17-NEXT:    ret void
10398 //
10399 //
10400 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..4
10401 // CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[N:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {
10402 // CHECK17-NEXT:  entry:
10403 // CHECK17-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
10404 // CHECK17-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
10405 // CHECK17-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
10406 // CHECK17-NEXT:    [[N_ADDR:%.*]] = alloca i64, align 8
10407 // CHECK17-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
10408 // CHECK17-NEXT:    [[AAA_ADDR:%.*]] = alloca i64, align 8
10409 // CHECK17-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
10410 // CHECK17-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
10411 // CHECK17-NEXT:    [[TMP:%.*]] = alloca i32, align 4
10412 // CHECK17-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
10413 // CHECK17-NEXT:    [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4
10414 // CHECK17-NEXT:    [[DOTCAPTURE_EXPR_5:%.*]] = alloca i32, align 4
10415 // CHECK17-NEXT:    [[I:%.*]] = alloca i32, align 4
10416 // CHECK17-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
10417 // CHECK17-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
10418 // CHECK17-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
10419 // CHECK17-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
10420 // CHECK17-NEXT:    [[I8:%.*]] = alloca i32, align 4
10421 // CHECK17-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
10422 // CHECK17-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
10423 // CHECK17-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
10424 // CHECK17-NEXT:    store i64 [[N]], i64* [[N_ADDR]], align 8
10425 // CHECK17-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
10426 // CHECK17-NEXT:    store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
10427 // CHECK17-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
10428 // CHECK17-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
10429 // CHECK17-NEXT:    [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32*
10430 // CHECK17-NEXT:    [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
10431 // CHECK17-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
10432 // CHECK17-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
10433 // CHECK17-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
10434 // CHECK17-NEXT:    store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
10435 // CHECK17-NEXT:    [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4
10436 // CHECK17-NEXT:    store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_4]], align 4
10437 // CHECK17-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4
10438 // CHECK17-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
10439 // CHECK17-NEXT:    [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]]
10440 // CHECK17-NEXT:    [[SUB6:%.*]] = sub i32 [[SUB]], 1
10441 // CHECK17-NEXT:    [[ADD:%.*]] = add i32 [[SUB6]], 1
10442 // CHECK17-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], 1
10443 // CHECK17-NEXT:    [[SUB7:%.*]] = sub i32 [[DIV]], 1
10444 // CHECK17-NEXT:    store i32 [[SUB7]], i32* [[DOTCAPTURE_EXPR_5]], align 4
10445 // CHECK17-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
10446 // CHECK17-NEXT:    store i32 [[TMP5]], i32* [[I]], align 4
10447 // CHECK17-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
10448 // CHECK17-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4
10449 // CHECK17-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]]
10450 // CHECK17-NEXT:    br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
10451 // CHECK17:       omp.precond.then:
10452 // CHECK17-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
10453 // CHECK17-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4
10454 // CHECK17-NEXT:    store i32 [[TMP8]], i32* [[DOTOMP_UB]], align 4
10455 // CHECK17-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
10456 // CHECK17-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
10457 // CHECK17-NEXT:    [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
10458 // CHECK17-NEXT:    [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
10459 // CHECK17-NEXT:    call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
10460 // CHECK17-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
10461 // CHECK17-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4
10462 // CHECK17-NEXT:    [[CMP9:%.*]] = icmp ugt i32 [[TMP11]], [[TMP12]]
10463 // CHECK17-NEXT:    br i1 [[CMP9]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
10464 // CHECK17:       cond.true:
10465 // CHECK17-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4
10466 // CHECK17-NEXT:    br label [[COND_END:%.*]]
10467 // CHECK17:       cond.false:
10468 // CHECK17-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
10469 // CHECK17-NEXT:    br label [[COND_END]]
10470 // CHECK17:       cond.end:
10471 // CHECK17-NEXT:    [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ]
10472 // CHECK17-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
10473 // CHECK17-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
10474 // CHECK17-NEXT:    store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4
10475 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
10476 // CHECK17:       omp.inner.for.cond:
10477 // CHECK17-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27
10478 // CHECK17-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !27
10479 // CHECK17-NEXT:    [[ADD10:%.*]] = add i32 [[TMP17]], 1
10480 // CHECK17-NEXT:    [[CMP11:%.*]] = icmp ult i32 [[TMP16]], [[ADD10]]
10481 // CHECK17-NEXT:    br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
10482 // CHECK17:       omp.inner.for.body:
10483 // CHECK17-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group !27
10484 // CHECK17-NEXT:    [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27
10485 // CHECK17-NEXT:    [[MUL:%.*]] = mul i32 [[TMP19]], 1
10486 // CHECK17-NEXT:    [[ADD12:%.*]] = add i32 [[TMP18]], [[MUL]]
10487 // CHECK17-NEXT:    store i32 [[ADD12]], i32* [[I8]], align 4, !llvm.access.group !27
10488 // CHECK17-NEXT:    [[TMP20:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !27
10489 // CHECK17-NEXT:    [[ADD13:%.*]] = add nsw i32 [[TMP20]], 1
10490 // CHECK17-NEXT:    store i32 [[ADD13]], i32* [[CONV]], align 4, !llvm.access.group !27
10491 // CHECK17-NEXT:    [[TMP21:%.*]] = load i16, i16* [[CONV2]], align 2, !llvm.access.group !27
10492 // CHECK17-NEXT:    [[CONV14:%.*]] = sext i16 [[TMP21]] to i32
10493 // CHECK17-NEXT:    [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1
10494 // CHECK17-NEXT:    [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16
10495 // CHECK17-NEXT:    store i16 [[CONV16]], i16* [[CONV2]], align 2, !llvm.access.group !27
10496 // CHECK17-NEXT:    [[TMP22:%.*]] = load i8, i8* [[CONV3]], align 1, !llvm.access.group !27
10497 // CHECK17-NEXT:    [[CONV17:%.*]] = sext i8 [[TMP22]] to i32
10498 // CHECK17-NEXT:    [[ADD18:%.*]] = add nsw i32 [[CONV17]], 1
10499 // CHECK17-NEXT:    [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8
10500 // CHECK17-NEXT:    store i8 [[CONV19]], i8* [[CONV3]], align 1, !llvm.access.group !27
10501 // CHECK17-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
10502 // CHECK17-NEXT:    [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !27
10503 // CHECK17-NEXT:    [[ADD20:%.*]] = add nsw i32 [[TMP23]], 1
10504 // CHECK17-NEXT:    store i32 [[ADD20]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !27
10505 // CHECK17-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
10506 // CHECK17:       omp.body.continue:
10507 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
10508 // CHECK17:       omp.inner.for.inc:
10509 // CHECK17-NEXT:    [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27
10510 // CHECK17-NEXT:    [[ADD21:%.*]] = add i32 [[TMP24]], 1
10511 // CHECK17-NEXT:    store i32 [[ADD21]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27
10512 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]]
10513 // CHECK17:       omp.inner.for.end:
10514 // CHECK17-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
10515 // CHECK17:       omp.loop.exit:
10516 // CHECK17-NEXT:    [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
10517 // CHECK17-NEXT:    [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4
10518 // CHECK17-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]])
10519 // CHECK17-NEXT:    [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
10520 // CHECK17-NEXT:    [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0
10521 // CHECK17-NEXT:    br i1 [[TMP28]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
10522 // CHECK17:       .omp.final.then:
10523 // CHECK17-NEXT:    [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
10524 // CHECK17-NEXT:    [[TMP30:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4
10525 // CHECK17-NEXT:    [[TMP31:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
10526 // CHECK17-NEXT:    [[SUB22:%.*]] = sub i32 [[TMP30]], [[TMP31]]
10527 // CHECK17-NEXT:    [[SUB23:%.*]] = sub i32 [[SUB22]], 1
10528 // CHECK17-NEXT:    [[ADD24:%.*]] = add i32 [[SUB23]], 1
10529 // CHECK17-NEXT:    [[DIV25:%.*]] = udiv i32 [[ADD24]], 1
10530 // CHECK17-NEXT:    [[MUL26:%.*]] = mul i32 [[DIV25]], 1
10531 // CHECK17-NEXT:    [[ADD27:%.*]] = add i32 [[TMP29]], [[MUL26]]
10532 // CHECK17-NEXT:    store i32 [[ADD27]], i32* [[I8]], align 4
10533 // CHECK17-NEXT:    br label [[DOTOMP_FINAL_DONE]]
10534 // CHECK17:       .omp.final.done:
10535 // CHECK17-NEXT:    br label [[OMP_PRECOND_END]]
10536 // CHECK17:       omp.precond.end:
10537 // CHECK17-NEXT:    ret void
10538 //
10539 //
10540 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215
10541 // CHECK17-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {
10542 // CHECK17-NEXT:  entry:
10543 // CHECK17-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
10544 // CHECK17-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
10545 // CHECK17-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
10546 // CHECK17-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
10547 // CHECK17-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 8
10548 // CHECK17-NEXT:    [[B_CASTED:%.*]] = alloca i64, align 8
10549 // CHECK17-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
10550 // CHECK17-NEXT:    store i64 [[B]], i64* [[B_ADDR]], align 8
10551 // CHECK17-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
10552 // CHECK17-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
10553 // CHECK17-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 8
10554 // CHECK17-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
10555 // CHECK17-NEXT:    [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
10556 // CHECK17-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
10557 // CHECK17-NEXT:    [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
10558 // CHECK17-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
10559 // CHECK17-NEXT:    [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
10560 // CHECK17-NEXT:    [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32*
10561 // CHECK17-NEXT:    store i32 [[TMP4]], i32* [[CONV3]], align 4
10562 // CHECK17-NEXT:    [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
10563 // CHECK17-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]])
10564 // CHECK17-NEXT:    ret void
10565 //
10566 //
10567 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..5
10568 // CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] {
10569 // CHECK17-NEXT:  entry:
10570 // CHECK17-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
10571 // CHECK17-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
10572 // CHECK17-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
10573 // CHECK17-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
10574 // CHECK17-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
10575 // CHECK17-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
10576 // CHECK17-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 8
10577 // CHECK17-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
10578 // CHECK17-NEXT:    [[TMP:%.*]] = alloca i32, align 4
10579 // CHECK17-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
10580 // CHECK17-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
10581 // CHECK17-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
10582 // CHECK17-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
10583 // CHECK17-NEXT:    [[I:%.*]] = alloca i32, align 4
10584 // CHECK17-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
10585 // CHECK17-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
10586 // CHECK17-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
10587 // CHECK17-NEXT:    store i64 [[B]], i64* [[B_ADDR]], align 8
10588 // CHECK17-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
10589 // CHECK17-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
10590 // CHECK17-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 8
10591 // CHECK17-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
10592 // CHECK17-NEXT:    [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
10593 // CHECK17-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
10594 // CHECK17-NEXT:    [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
10595 // CHECK17-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
10596 // CHECK17-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
10597 // CHECK17-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
10598 // CHECK17-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
10599 // CHECK17-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
10600 // CHECK17-NEXT:    [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
10601 // CHECK17-NEXT:    [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
10602 // CHECK17-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
10603 // CHECK17-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
10604 // CHECK17-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 9
10605 // CHECK17-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
10606 // CHECK17:       cond.true:
10607 // CHECK17-NEXT:    br label [[COND_END:%.*]]
10608 // CHECK17:       cond.false:
10609 // CHECK17-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
10610 // CHECK17-NEXT:    br label [[COND_END]]
10611 // CHECK17:       cond.end:
10612 // CHECK17-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
10613 // CHECK17-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
10614 // CHECK17-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
10615 // CHECK17-NEXT:    store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
10616 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
10617 // CHECK17:       omp.inner.for.cond:
10618 // CHECK17-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30
10619 // CHECK17-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !30
10620 // CHECK17-NEXT:    [[CMP3:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
10621 // CHECK17-NEXT:    br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
10622 // CHECK17:       omp.inner.for.body:
10623 // CHECK17-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30
10624 // CHECK17-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
10625 // CHECK17-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
10626 // CHECK17-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !30
10627 // CHECK17-NEXT:    [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !30
10628 // CHECK17-NEXT:    [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double
10629 // CHECK17-NEXT:    [[ADD5:%.*]] = fadd double [[CONV4]], 1.500000e+00
10630 // CHECK17-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
10631 // CHECK17-NEXT:    store double [[ADD5]], double* [[A]], align 8, !llvm.access.group !30
10632 // CHECK17-NEXT:    [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
10633 // CHECK17-NEXT:    [[TMP13:%.*]] = load double, double* [[A6]], align 8, !llvm.access.group !30
10634 // CHECK17-NEXT:    [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00
10635 // CHECK17-NEXT:    store double [[INC]], double* [[A6]], align 8, !llvm.access.group !30
10636 // CHECK17-NEXT:    [[CONV7:%.*]] = fptosi double [[INC]] to i16
10637 // CHECK17-NEXT:    [[TMP14:%.*]] = mul nsw i64 1, [[TMP2]]
10638 // CHECK17-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP14]]
10639 // CHECK17-NEXT:    [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
10640 // CHECK17-NEXT:    store i16 [[CONV7]], i16* [[ARRAYIDX8]], align 2, !llvm.access.group !30
10641 // CHECK17-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
10642 // CHECK17:       omp.body.continue:
10643 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
10644 // CHECK17:       omp.inner.for.inc:
10645 // CHECK17-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30
10646 // CHECK17-NEXT:    [[ADD9:%.*]] = add nsw i32 [[TMP15]], 1
10647 // CHECK17-NEXT:    store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30
10648 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP31:![0-9]+]]
10649 // CHECK17:       omp.inner.for.end:
10650 // CHECK17-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
10651 // CHECK17:       omp.loop.exit:
10652 // CHECK17-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
10653 // CHECK17-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
10654 // CHECK17-NEXT:    [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0
10655 // CHECK17-NEXT:    br i1 [[TMP17]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
10656 // CHECK17:       .omp.final.then:
10657 // CHECK17-NEXT:    store i32 10, i32* [[I]], align 4
10658 // CHECK17-NEXT:    br label [[DOTOMP_FINAL_DONE]]
10659 // CHECK17:       .omp.final.done:
10660 // CHECK17-NEXT:    ret void
10661 //
10662 //
10663 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180
10664 // CHECK17-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
10665 // CHECK17-NEXT:  entry:
10666 // CHECK17-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
10667 // CHECK17-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
10668 // CHECK17-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
10669 // CHECK17-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
10670 // CHECK17-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
10671 // CHECK17-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
10672 // CHECK17-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
10673 // CHECK17-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
10674 // CHECK17-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
10675 // CHECK17-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
10676 // CHECK17-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
10677 // CHECK17-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
10678 // CHECK17-NEXT:    [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
10679 // CHECK17-NEXT:    store i32 [[TMP1]], i32* [[CONV2]], align 4
10680 // CHECK17-NEXT:    [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
10681 // CHECK17-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
10682 // CHECK17-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
10683 // CHECK17-NEXT:    store i16 [[TMP3]], i16* [[CONV3]], align 2
10684 // CHECK17-NEXT:    [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
10685 // CHECK17-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]])
10686 // CHECK17-NEXT:    ret void
10687 //
10688 //
10689 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..6
10690 // CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {
10691 // CHECK17-NEXT:  entry:
10692 // CHECK17-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
10693 // CHECK17-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
10694 // CHECK17-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
10695 // CHECK17-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
10696 // CHECK17-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
10697 // CHECK17-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
10698 // CHECK17-NEXT:    [[TMP:%.*]] = alloca i32, align 4
10699 // CHECK17-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
10700 // CHECK17-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
10701 // CHECK17-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
10702 // CHECK17-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
10703 // CHECK17-NEXT:    [[I:%.*]] = alloca i32, align 4
10704 // CHECK17-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
10705 // CHECK17-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
10706 // CHECK17-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
10707 // CHECK17-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
10708 // CHECK17-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
10709 // CHECK17-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
10710 // CHECK17-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
10711 // CHECK17-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
10712 // CHECK17-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
10713 // CHECK17-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
10714 // CHECK17-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
10715 // CHECK17-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
10716 // CHECK17-NEXT:    [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
10717 // CHECK17-NEXT:    [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
10718 // CHECK17-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
10719 // CHECK17-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
10720 // CHECK17-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9
10721 // CHECK17-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
10722 // CHECK17:       cond.true:
10723 // CHECK17-NEXT:    br label [[COND_END:%.*]]
10724 // CHECK17:       cond.false:
10725 // CHECK17-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
10726 // CHECK17-NEXT:    br label [[COND_END]]
10727 // CHECK17:       cond.end:
10728 // CHECK17-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
10729 // CHECK17-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
10730 // CHECK17-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
10731 // CHECK17-NEXT:    store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
10732 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
10733 // CHECK17:       omp.inner.for.cond:
10734 // CHECK17-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33
10735 // CHECK17-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !33
10736 // CHECK17-NEXT:    [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
10737 // CHECK17-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
10738 // CHECK17:       omp.inner.for.body:
10739 // CHECK17-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33
10740 // CHECK17-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
10741 // CHECK17-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
10742 // CHECK17-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !33
10743 // CHECK17-NEXT:    [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !33
10744 // CHECK17-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1
10745 // CHECK17-NEXT:    store i32 [[ADD3]], i32* [[CONV]], align 4, !llvm.access.group !33
10746 // CHECK17-NEXT:    [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 2, !llvm.access.group !33
10747 // CHECK17-NEXT:    [[CONV4:%.*]] = sext i16 [[TMP10]] to i32
10748 // CHECK17-NEXT:    [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
10749 // CHECK17-NEXT:    [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
10750 // CHECK17-NEXT:    store i16 [[CONV6]], i16* [[CONV1]], align 2, !llvm.access.group !33
10751 // CHECK17-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
10752 // CHECK17-NEXT:    [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !33
10753 // CHECK17-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1
10754 // CHECK17-NEXT:    store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !33
10755 // CHECK17-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
10756 // CHECK17:       omp.body.continue:
10757 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
10758 // CHECK17:       omp.inner.for.inc:
10759 // CHECK17-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33
10760 // CHECK17-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP12]], 1
10761 // CHECK17-NEXT:    store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33
10762 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP34:![0-9]+]]
10763 // CHECK17:       omp.inner.for.end:
10764 // CHECK17-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
10765 // CHECK17:       omp.loop.exit:
10766 // CHECK17-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
10767 // CHECK17-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
10768 // CHECK17-NEXT:    [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
10769 // CHECK17-NEXT:    br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
10770 // CHECK17:       .omp.final.then:
10771 // CHECK17-NEXT:    store i32 10, i32* [[I]], align 4
10772 // CHECK17-NEXT:    br label [[DOTOMP_FINAL_DONE]]
10773 // CHECK17:       .omp.final.done:
10774 // CHECK17-NEXT:    ret void
10775 //
10776 //
10777 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97
10778 // CHECK19-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]], i32 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] {
10779 // CHECK19-NEXT:  entry:
10780 // CHECK19-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
10781 // CHECK19-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
10782 // CHECK19-NEXT:    [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4
10783 // CHECK19-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
10784 // CHECK19-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]])
10785 // CHECK19-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
10786 // CHECK19-NEXT:    store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
10787 // CHECK19-NEXT:    store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4
10788 // CHECK19-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
10789 // CHECK19-NEXT:    [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
10790 // CHECK19-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4
10791 // CHECK19-NEXT:    call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
10792 // CHECK19-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
10793 // CHECK19-NEXT:    [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
10794 // CHECK19-NEXT:    store i16 [[TMP3]], i16* [[CONV3]], align 2
10795 // CHECK19-NEXT:    [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
10796 // CHECK19-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]])
10797 // CHECK19-NEXT:    ret void
10798 //
10799 //
10800 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined.
10801 // CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR1:[0-9]+]] {
10802 // CHECK19-NEXT:  entry:
10803 // CHECK19-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
10804 // CHECK19-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
10805 // CHECK19-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
10806 // CHECK19-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
10807 // CHECK19-NEXT:    [[TMP:%.*]] = alloca i32, align 4
10808 // CHECK19-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
10809 // CHECK19-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
10810 // CHECK19-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
10811 // CHECK19-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
10812 // CHECK19-NEXT:    [[I:%.*]] = alloca i32, align 4
10813 // CHECK19-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
10814 // CHECK19-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
10815 // CHECK19-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
10816 // CHECK19-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
10817 // CHECK19-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
10818 // CHECK19-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
10819 // CHECK19-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
10820 // CHECK19-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
10821 // CHECK19-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
10822 // CHECK19-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
10823 // CHECK19-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
10824 // CHECK19-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
10825 // CHECK19-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
10826 // CHECK19-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
10827 // CHECK19:       cond.true:
10828 // CHECK19-NEXT:    br label [[COND_END:%.*]]
10829 // CHECK19:       cond.false:
10830 // CHECK19-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
10831 // CHECK19-NEXT:    br label [[COND_END]]
10832 // CHECK19:       cond.end:
10833 // CHECK19-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
10834 // CHECK19-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
10835 // CHECK19-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
10836 // CHECK19-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
10837 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
10838 // CHECK19:       omp.inner.for.cond:
10839 // CHECK19-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
10840 // CHECK19-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !12
10841 // CHECK19-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
10842 // CHECK19-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
10843 // CHECK19:       omp.inner.for.body:
10844 // CHECK19-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
10845 // CHECK19-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
10846 // CHECK19-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
10847 // CHECK19-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !12
10848 // CHECK19-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
10849 // CHECK19:       omp.body.continue:
10850 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
10851 // CHECK19:       omp.inner.for.inc:
10852 // CHECK19-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
10853 // CHECK19-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
10854 // CHECK19-NEXT:    store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
10855 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]
10856 // CHECK19:       omp.inner.for.end:
10857 // CHECK19-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
10858 // CHECK19:       omp.loop.exit:
10859 // CHECK19-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
10860 // CHECK19-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
10861 // CHECK19-NEXT:    [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0
10862 // CHECK19-NEXT:    br i1 [[TMP10]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
10863 // CHECK19:       .omp.final.then:
10864 // CHECK19-NEXT:    store i32 10, i32* [[I]], align 4
10865 // CHECK19-NEXT:    br label [[DOTOMP_FINAL_DONE]]
10866 // CHECK19:       .omp.final.done:
10867 // CHECK19-NEXT:    ret void
10868 //
10869 //
10870 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111
10871 // CHECK19-SAME: (i32 noundef [[AA:%.*]]) #[[ATTR0]] {
10872 // CHECK19-NEXT:  entry:
10873 // CHECK19-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
10874 // CHECK19-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
10875 // CHECK19-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
10876 // CHECK19-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
10877 // CHECK19-NEXT:    [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
10878 // CHECK19-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
10879 // CHECK19-NEXT:    store i16 [[TMP0]], i16* [[CONV1]], align 2
10880 // CHECK19-NEXT:    [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
10881 // CHECK19-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]])
10882 // CHECK19-NEXT:    ret void
10883 //
10884 //
10885 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..1
10886 // CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR1]] {
10887 // CHECK19-NEXT:  entry:
10888 // CHECK19-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
10889 // CHECK19-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
10890 // CHECK19-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
10891 // CHECK19-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
10892 // CHECK19-NEXT:    [[TMP:%.*]] = alloca i32, align 4
10893 // CHECK19-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
10894 // CHECK19-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
10895 // CHECK19-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
10896 // CHECK19-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
10897 // CHECK19-NEXT:    [[I:%.*]] = alloca i32, align 4
10898 // CHECK19-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
10899 // CHECK19-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
10900 // CHECK19-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
10901 // CHECK19-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
10902 // CHECK19-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
10903 // CHECK19-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
10904 // CHECK19-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
10905 // CHECK19-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
10906 // CHECK19-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
10907 // CHECK19-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
10908 // CHECK19-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
10909 // CHECK19-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
10910 // CHECK19-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
10911 // CHECK19-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
10912 // CHECK19:       cond.true:
10913 // CHECK19-NEXT:    br label [[COND_END:%.*]]
10914 // CHECK19:       cond.false:
10915 // CHECK19-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
10916 // CHECK19-NEXT:    br label [[COND_END]]
10917 // CHECK19:       cond.end:
10918 // CHECK19-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
10919 // CHECK19-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
10920 // CHECK19-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
10921 // CHECK19-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
10922 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
10923 // CHECK19:       omp.inner.for.cond:
10924 // CHECK19-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
10925 // CHECK19-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !19
10926 // CHECK19-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
10927 // CHECK19-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
10928 // CHECK19:       omp.inner.for.body:
10929 // CHECK19-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
10930 // CHECK19-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
10931 // CHECK19-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
10932 // CHECK19-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !19
10933 // CHECK19-NEXT:    [[TMP8:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !19
10934 // CHECK19-NEXT:    [[CONV2:%.*]] = sext i16 [[TMP8]] to i32
10935 // CHECK19-NEXT:    [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
10936 // CHECK19-NEXT:    [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
10937 // CHECK19-NEXT:    store i16 [[CONV4]], i16* [[CONV]], align 2, !llvm.access.group !19
10938 // CHECK19-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
10939 // CHECK19:       omp.body.continue:
10940 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
10941 // CHECK19:       omp.inner.for.inc:
10942 // CHECK19-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
10943 // CHECK19-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP9]], 1
10944 // CHECK19-NEXT:    store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
10945 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]]
10946 // CHECK19:       omp.inner.for.end:
10947 // CHECK19-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
10948 // CHECK19:       omp.loop.exit:
10949 // CHECK19-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
10950 // CHECK19-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
10951 // CHECK19-NEXT:    [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0
10952 // CHECK19-NEXT:    br i1 [[TMP11]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
10953 // CHECK19:       .omp.final.then:
10954 // CHECK19-NEXT:    store i32 10, i32* [[I]], align 4
10955 // CHECK19-NEXT:    br label [[DOTOMP_FINAL_DONE]]
10956 // CHECK19:       .omp.final.done:
10957 // CHECK19-NEXT:    ret void
10958 //
10959 //
10960 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118
10961 // CHECK19-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] {
10962 // CHECK19-NEXT:  entry:
10963 // CHECK19-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
10964 // CHECK19-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
10965 // CHECK19-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
10966 // CHECK19-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
10967 // CHECK19-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
10968 // CHECK19-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
10969 // CHECK19-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
10970 // CHECK19-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
10971 // CHECK19-NEXT:    store i32 [[TMP0]], i32* [[A_CASTED]], align 4
10972 // CHECK19-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
10973 // CHECK19-NEXT:    [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
10974 // CHECK19-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
10975 // CHECK19-NEXT:    store i16 [[TMP2]], i16* [[CONV1]], align 2
10976 // CHECK19-NEXT:    [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
10977 // CHECK19-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]])
10978 // CHECK19-NEXT:    ret void
10979 //
10980 //
10981 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..2
10982 // CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR1]] {
10983 // CHECK19-NEXT:  entry:
10984 // CHECK19-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
10985 // CHECK19-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
10986 // CHECK19-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
10987 // CHECK19-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
10988 // CHECK19-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
10989 // CHECK19-NEXT:    [[TMP:%.*]] = alloca i32, align 4
10990 // CHECK19-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
10991 // CHECK19-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
10992 // CHECK19-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
10993 // CHECK19-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
10994 // CHECK19-NEXT:    [[I:%.*]] = alloca i32, align 4
10995 // CHECK19-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
10996 // CHECK19-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
10997 // CHECK19-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
10998 // CHECK19-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
10999 // CHECK19-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
11000 // CHECK19-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
11001 // CHECK19-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
11002 // CHECK19-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
11003 // CHECK19-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
11004 // CHECK19-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
11005 // CHECK19-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
11006 // CHECK19-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
11007 // CHECK19-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
11008 // CHECK19-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
11009 // CHECK19-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
11010 // CHECK19:       cond.true:
11011 // CHECK19-NEXT:    br label [[COND_END:%.*]]
11012 // CHECK19:       cond.false:
11013 // CHECK19-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
11014 // CHECK19-NEXT:    br label [[COND_END]]
11015 // CHECK19:       cond.end:
11016 // CHECK19-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
11017 // CHECK19-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
11018 // CHECK19-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
11019 // CHECK19-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
11020 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
11021 // CHECK19:       omp.inner.for.cond:
11022 // CHECK19-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
11023 // CHECK19-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !22
11024 // CHECK19-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
11025 // CHECK19-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
11026 // CHECK19:       omp.inner.for.body:
11027 // CHECK19-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
11028 // CHECK19-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
11029 // CHECK19-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
11030 // CHECK19-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !22
11031 // CHECK19-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !22
11032 // CHECK19-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
11033 // CHECK19-NEXT:    store i32 [[ADD2]], i32* [[A_ADDR]], align 4, !llvm.access.group !22
11034 // CHECK19-NEXT:    [[TMP9:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !22
11035 // CHECK19-NEXT:    [[CONV3:%.*]] = sext i16 [[TMP9]] to i32
11036 // CHECK19-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
11037 // CHECK19-NEXT:    [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
11038 // CHECK19-NEXT:    store i16 [[CONV5]], i16* [[CONV]], align 2, !llvm.access.group !22
11039 // CHECK19-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
11040 // CHECK19:       omp.body.continue:
11041 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
11042 // CHECK19:       omp.inner.for.inc:
11043 // CHECK19-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
11044 // CHECK19-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP10]], 1
11045 // CHECK19-NEXT:    store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
11046 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]]
11047 // CHECK19:       omp.inner.for.end:
11048 // CHECK19-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
11049 // CHECK19:       omp.loop.exit:
11050 // CHECK19-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
11051 // CHECK19-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
11052 // CHECK19-NEXT:    [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
11053 // CHECK19-NEXT:    br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
11054 // CHECK19:       .omp.final.then:
11055 // CHECK19-NEXT:    store i32 10, i32* [[I]], align 4
11056 // CHECK19-NEXT:    br label [[DOTOMP_FINAL_DONE]]
11057 // CHECK19:       .omp.final.done:
11058 // CHECK19-NEXT:    ret void
11059 //
11060 //
11061 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142
11062 // CHECK19-SAME: (i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] {
11063 // CHECK19-NEXT:  entry:
11064 // CHECK19-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
11065 // CHECK19-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
11066 // CHECK19-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
11067 // CHECK19-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 4
11068 // CHECK19-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
11069 // CHECK19-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
11070 // CHECK19-NEXT:    [[VLA_ADDR4:%.*]] = alloca i32, align 4
11071 // CHECK19-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 4
11072 // CHECK19-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
11073 // CHECK19-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
11074 // CHECK19-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
11075 // CHECK19-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
11076 // CHECK19-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
11077 // CHECK19-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 4
11078 // CHECK19-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
11079 // CHECK19-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
11080 // CHECK19-NEXT:    store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
11081 // CHECK19-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 4
11082 // CHECK19-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
11083 // CHECK19-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
11084 // CHECK19-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
11085 // CHECK19-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
11086 // CHECK19-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
11087 // CHECK19-NEXT:    [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
11088 // CHECK19-NEXT:    [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
11089 // CHECK19-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
11090 // CHECK19-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
11091 // CHECK19-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
11092 // CHECK19-NEXT:    store i32 [[TMP8]], i32* [[A_CASTED]], align 4
11093 // CHECK19-NEXT:    [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4
11094 // CHECK19-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]])
11095 // CHECK19-NEXT:    ret void
11096 //
11097 //
11098 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..3
11099 // CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR1]] {
11100 // CHECK19-NEXT:  entry:
11101 // CHECK19-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
11102 // CHECK19-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
11103 // CHECK19-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
11104 // CHECK19-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
11105 // CHECK19-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
11106 // CHECK19-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 4
11107 // CHECK19-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
11108 // CHECK19-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
11109 // CHECK19-NEXT:    [[VLA_ADDR4:%.*]] = alloca i32, align 4
11110 // CHECK19-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 4
11111 // CHECK19-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
11112 // CHECK19-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
11113 // CHECK19-NEXT:    [[TMP:%.*]] = alloca i32, align 4
11114 // CHECK19-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
11115 // CHECK19-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
11116 // CHECK19-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
11117 // CHECK19-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
11118 // CHECK19-NEXT:    [[I:%.*]] = alloca i32, align 4
11119 // CHECK19-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
11120 // CHECK19-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
11121 // CHECK19-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
11122 // CHECK19-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
11123 // CHECK19-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
11124 // CHECK19-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 4
11125 // CHECK19-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
11126 // CHECK19-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
11127 // CHECK19-NEXT:    store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
11128 // CHECK19-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 4
11129 // CHECK19-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
11130 // CHECK19-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
11131 // CHECK19-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
11132 // CHECK19-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
11133 // CHECK19-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
11134 // CHECK19-NEXT:    [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
11135 // CHECK19-NEXT:    [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
11136 // CHECK19-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
11137 // CHECK19-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
11138 // CHECK19-NEXT:    [[ARRAYDECAY:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 0
11139 // CHECK19-NEXT:    call void @llvm.assume(i1 true) [ "align"(float* [[ARRAYDECAY]], i32 16) ]
11140 // CHECK19-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
11141 // CHECK19-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
11142 // CHECK19-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
11143 // CHECK19-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
11144 // CHECK19-NEXT:    [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
11145 // CHECK19-NEXT:    [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4
11146 // CHECK19-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
11147 // CHECK19-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
11148 // CHECK19-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP10]], 9
11149 // CHECK19-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
11150 // CHECK19:       cond.true:
11151 // CHECK19-NEXT:    br label [[COND_END:%.*]]
11152 // CHECK19:       cond.false:
11153 // CHECK19-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
11154 // CHECK19-NEXT:    br label [[COND_END]]
11155 // CHECK19:       cond.end:
11156 // CHECK19-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ]
11157 // CHECK19-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
11158 // CHECK19-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
11159 // CHECK19-NEXT:    store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4
11160 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
11161 // CHECK19:       omp.inner.for.cond:
11162 // CHECK19-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25
11163 // CHECK19-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !25
11164 // CHECK19-NEXT:    [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
11165 // CHECK19-NEXT:    br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
11166 // CHECK19:       omp.inner.for.body:
11167 // CHECK19-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25
11168 // CHECK19-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1
11169 // CHECK19-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
11170 // CHECK19-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !25
11171 // CHECK19-NEXT:    [[TMP16:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !25
11172 // CHECK19-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP16]], 1
11173 // CHECK19-NEXT:    store i32 [[ADD6]], i32* [[A_ADDR]], align 4, !llvm.access.group !25
11174 // CHECK19-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2
11175 // CHECK19-NEXT:    [[TMP17:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !25
11176 // CHECK19-NEXT:    [[CONV:%.*]] = fpext float [[TMP17]] to double
11177 // CHECK19-NEXT:    [[ADD7:%.*]] = fadd double [[CONV]], 1.000000e+00
11178 // CHECK19-NEXT:    [[CONV8:%.*]] = fptrunc double [[ADD7]] to float
11179 // CHECK19-NEXT:    store float [[CONV8]], float* [[ARRAYIDX]], align 4, !llvm.access.group !25
11180 // CHECK19-NEXT:    [[ARRAYIDX9:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3
11181 // CHECK19-NEXT:    [[TMP18:%.*]] = load float, float* [[ARRAYIDX9]], align 4, !llvm.access.group !25
11182 // CHECK19-NEXT:    [[CONV10:%.*]] = fpext float [[TMP18]] to double
11183 // CHECK19-NEXT:    [[ADD11:%.*]] = fadd double [[CONV10]], 1.000000e+00
11184 // CHECK19-NEXT:    [[CONV12:%.*]] = fptrunc double [[ADD11]] to float
11185 // CHECK19-NEXT:    store float [[CONV12]], float* [[ARRAYIDX9]], align 4, !llvm.access.group !25
11186 // CHECK19-NEXT:    [[ARRAYIDX13:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1
11187 // CHECK19-NEXT:    [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX13]], i32 0, i32 2
11188 // CHECK19-NEXT:    [[TMP19:%.*]] = load double, double* [[ARRAYIDX14]], align 8, !llvm.access.group !25
11189 // CHECK19-NEXT:    [[ADD15:%.*]] = fadd double [[TMP19]], 1.000000e+00
11190 // CHECK19-NEXT:    store double [[ADD15]], double* [[ARRAYIDX14]], align 8, !llvm.access.group !25
11191 // CHECK19-NEXT:    [[TMP20:%.*]] = mul nsw i32 1, [[TMP5]]
11192 // CHECK19-NEXT:    [[ARRAYIDX16:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP20]]
11193 // CHECK19-NEXT:    [[ARRAYIDX17:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX16]], i32 3
11194 // CHECK19-NEXT:    [[TMP21:%.*]] = load double, double* [[ARRAYIDX17]], align 8, !llvm.access.group !25
11195 // CHECK19-NEXT:    [[ADD18:%.*]] = fadd double [[TMP21]], 1.000000e+00
11196 // CHECK19-NEXT:    store double [[ADD18]], double* [[ARRAYIDX17]], align 8, !llvm.access.group !25
11197 // CHECK19-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0
11198 // CHECK19-NEXT:    [[TMP22:%.*]] = load i64, i64* [[X]], align 4, !llvm.access.group !25
11199 // CHECK19-NEXT:    [[ADD19:%.*]] = add nsw i64 [[TMP22]], 1
11200 // CHECK19-NEXT:    store i64 [[ADD19]], i64* [[X]], align 4, !llvm.access.group !25
11201 // CHECK19-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1
11202 // CHECK19-NEXT:    [[TMP23:%.*]] = load i8, i8* [[Y]], align 4, !llvm.access.group !25
11203 // CHECK19-NEXT:    [[CONV20:%.*]] = sext i8 [[TMP23]] to i32
11204 // CHECK19-NEXT:    [[ADD21:%.*]] = add nsw i32 [[CONV20]], 1
11205 // CHECK19-NEXT:    [[CONV22:%.*]] = trunc i32 [[ADD21]] to i8
11206 // CHECK19-NEXT:    store i8 [[CONV22]], i8* [[Y]], align 4, !llvm.access.group !25
11207 // CHECK19-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
11208 // CHECK19:       omp.body.continue:
11209 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
11210 // CHECK19:       omp.inner.for.inc:
11211 // CHECK19-NEXT:    [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25
11212 // CHECK19-NEXT:    [[ADD23:%.*]] = add nsw i32 [[TMP24]], 1
11213 // CHECK19-NEXT:    store i32 [[ADD23]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25
11214 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP26:![0-9]+]]
11215 // CHECK19:       omp.inner.for.end:
11216 // CHECK19-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
11217 // CHECK19:       omp.loop.exit:
11218 // CHECK19-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]])
11219 // CHECK19-NEXT:    [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
11220 // CHECK19-NEXT:    [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
11221 // CHECK19-NEXT:    br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
11222 // CHECK19:       .omp.final.then:
11223 // CHECK19-NEXT:    store i32 10, i32* [[I]], align 4
11224 // CHECK19-NEXT:    br label [[DOTOMP_FINAL_DONE]]
11225 // CHECK19:       .omp.final.done:
11226 // CHECK19-NEXT:    ret void
11227 //
11228 //
11229 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197
11230 // CHECK19-SAME: (i32 noundef [[A:%.*]], i32 noundef [[N:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
11231 // CHECK19-NEXT:  entry:
11232 // CHECK19-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
11233 // CHECK19-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
11234 // CHECK19-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
11235 // CHECK19-NEXT:    [[AAA_ADDR:%.*]] = alloca i32, align 4
11236 // CHECK19-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
11237 // CHECK19-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
11238 // CHECK19-NEXT:    [[N_CASTED:%.*]] = alloca i32, align 4
11239 // CHECK19-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
11240 // CHECK19-NEXT:    [[AAA_CASTED:%.*]] = alloca i32, align 4
11241 // CHECK19-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
11242 // CHECK19-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
11243 // CHECK19-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
11244 // CHECK19-NEXT:    store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
11245 // CHECK19-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
11246 // CHECK19-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
11247 // CHECK19-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
11248 // CHECK19-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
11249 // CHECK19-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
11250 // CHECK19-NEXT:    store i32 [[TMP1]], i32* [[A_CASTED]], align 4
11251 // CHECK19-NEXT:    [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
11252 // CHECK19-NEXT:    [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
11253 // CHECK19-NEXT:    store i32 [[TMP3]], i32* [[N_CASTED]], align 4
11254 // CHECK19-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_CASTED]], align 4
11255 // CHECK19-NEXT:    [[TMP5:%.*]] = load i16, i16* [[CONV]], align 2
11256 // CHECK19-NEXT:    [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
11257 // CHECK19-NEXT:    store i16 [[TMP5]], i16* [[CONV2]], align 2
11258 // CHECK19-NEXT:    [[TMP6:%.*]] = load i32, i32* [[AA_CASTED]], align 4
11259 // CHECK19-NEXT:    [[TMP7:%.*]] = load i8, i8* [[CONV1]], align 1
11260 // CHECK19-NEXT:    [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
11261 // CHECK19-NEXT:    store i8 [[TMP7]], i8* [[CONV3]], align 1
11262 // CHECK19-NEXT:    [[TMP8:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
11263 // CHECK19-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP8]], [10 x i32]* [[TMP0]])
11264 // CHECK19-NEXT:    ret void
11265 //
11266 //
11267 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..4
11268 // CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[N:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {
11269 // CHECK19-NEXT:  entry:
11270 // CHECK19-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
11271 // CHECK19-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
11272 // CHECK19-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
11273 // CHECK19-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
11274 // CHECK19-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
11275 // CHECK19-NEXT:    [[AAA_ADDR:%.*]] = alloca i32, align 4
11276 // CHECK19-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
11277 // CHECK19-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
11278 // CHECK19-NEXT:    [[TMP:%.*]] = alloca i32, align 4
11279 // CHECK19-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
11280 // CHECK19-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
11281 // CHECK19-NEXT:    [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4
11282 // CHECK19-NEXT:    [[I:%.*]] = alloca i32, align 4
11283 // CHECK19-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
11284 // CHECK19-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
11285 // CHECK19-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
11286 // CHECK19-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
11287 // CHECK19-NEXT:    [[I6:%.*]] = alloca i32, align 4
11288 // CHECK19-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
11289 // CHECK19-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
11290 // CHECK19-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
11291 // CHECK19-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
11292 // CHECK19-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
11293 // CHECK19-NEXT:    store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
11294 // CHECK19-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
11295 // CHECK19-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
11296 // CHECK19-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
11297 // CHECK19-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
11298 // CHECK19-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
11299 // CHECK19-NEXT:    store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
11300 // CHECK19-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
11301 // CHECK19-NEXT:    store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4
11302 // CHECK19-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
11303 // CHECK19-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
11304 // CHECK19-NEXT:    [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]]
11305 // CHECK19-NEXT:    [[SUB4:%.*]] = sub i32 [[SUB]], 1
11306 // CHECK19-NEXT:    [[ADD:%.*]] = add i32 [[SUB4]], 1
11307 // CHECK19-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], 1
11308 // CHECK19-NEXT:    [[SUB5:%.*]] = sub i32 [[DIV]], 1
11309 // CHECK19-NEXT:    store i32 [[SUB5]], i32* [[DOTCAPTURE_EXPR_3]], align 4
11310 // CHECK19-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
11311 // CHECK19-NEXT:    store i32 [[TMP5]], i32* [[I]], align 4
11312 // CHECK19-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
11313 // CHECK19-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
11314 // CHECK19-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]]
11315 // CHECK19-NEXT:    br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
11316 // CHECK19:       omp.precond.then:
11317 // CHECK19-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
11318 // CHECK19-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
11319 // CHECK19-NEXT:    store i32 [[TMP8]], i32* [[DOTOMP_UB]], align 4
11320 // CHECK19-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
11321 // CHECK19-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
11322 // CHECK19-NEXT:    [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
11323 // CHECK19-NEXT:    [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
11324 // CHECK19-NEXT:    call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
11325 // CHECK19-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
11326 // CHECK19-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
11327 // CHECK19-NEXT:    [[CMP7:%.*]] = icmp ugt i32 [[TMP11]], [[TMP12]]
11328 // CHECK19-NEXT:    br i1 [[CMP7]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
11329 // CHECK19:       cond.true:
11330 // CHECK19-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
11331 // CHECK19-NEXT:    br label [[COND_END:%.*]]
11332 // CHECK19:       cond.false:
11333 // CHECK19-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
11334 // CHECK19-NEXT:    br label [[COND_END]]
11335 // CHECK19:       cond.end:
11336 // CHECK19-NEXT:    [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ]
11337 // CHECK19-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
11338 // CHECK19-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
11339 // CHECK19-NEXT:    store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4
11340 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
11341 // CHECK19:       omp.inner.for.cond:
11342 // CHECK19-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28
11343 // CHECK19-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !28
11344 // CHECK19-NEXT:    [[ADD8:%.*]] = add i32 [[TMP17]], 1
11345 // CHECK19-NEXT:    [[CMP9:%.*]] = icmp ult i32 [[TMP16]], [[ADD8]]
11346 // CHECK19-NEXT:    br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
11347 // CHECK19:       omp.inner.for.body:
11348 // CHECK19-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group !28
11349 // CHECK19-NEXT:    [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28
11350 // CHECK19-NEXT:    [[MUL:%.*]] = mul i32 [[TMP19]], 1
11351 // CHECK19-NEXT:    [[ADD10:%.*]] = add i32 [[TMP18]], [[MUL]]
11352 // CHECK19-NEXT:    store i32 [[ADD10]], i32* [[I6]], align 4, !llvm.access.group !28
11353 // CHECK19-NEXT:    [[TMP20:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !28
11354 // CHECK19-NEXT:    [[ADD11:%.*]] = add nsw i32 [[TMP20]], 1
11355 // CHECK19-NEXT:    store i32 [[ADD11]], i32* [[A_ADDR]], align 4, !llvm.access.group !28
11356 // CHECK19-NEXT:    [[TMP21:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !28
11357 // CHECK19-NEXT:    [[CONV12:%.*]] = sext i16 [[TMP21]] to i32
11358 // CHECK19-NEXT:    [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1
11359 // CHECK19-NEXT:    [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16
11360 // CHECK19-NEXT:    store i16 [[CONV14]], i16* [[CONV]], align 2, !llvm.access.group !28
11361 // CHECK19-NEXT:    [[TMP22:%.*]] = load i8, i8* [[CONV1]], align 1, !llvm.access.group !28
11362 // CHECK19-NEXT:    [[CONV15:%.*]] = sext i8 [[TMP22]] to i32
11363 // CHECK19-NEXT:    [[ADD16:%.*]] = add nsw i32 [[CONV15]], 1
11364 // CHECK19-NEXT:    [[CONV17:%.*]] = trunc i32 [[ADD16]] to i8
11365 // CHECK19-NEXT:    store i8 [[CONV17]], i8* [[CONV1]], align 1, !llvm.access.group !28
11366 // CHECK19-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
11367 // CHECK19-NEXT:    [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !28
11368 // CHECK19-NEXT:    [[ADD18:%.*]] = add nsw i32 [[TMP23]], 1
11369 // CHECK19-NEXT:    store i32 [[ADD18]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !28
11370 // CHECK19-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
11371 // CHECK19:       omp.body.continue:
11372 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
11373 // CHECK19:       omp.inner.for.inc:
11374 // CHECK19-NEXT:    [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28
11375 // CHECK19-NEXT:    [[ADD19:%.*]] = add i32 [[TMP24]], 1
11376 // CHECK19-NEXT:    store i32 [[ADD19]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28
11377 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP29:![0-9]+]]
11378 // CHECK19:       omp.inner.for.end:
11379 // CHECK19-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
11380 // CHECK19:       omp.loop.exit:
11381 // CHECK19-NEXT:    [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
11382 // CHECK19-NEXT:    [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4
11383 // CHECK19-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]])
11384 // CHECK19-NEXT:    [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
11385 // CHECK19-NEXT:    [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0
11386 // CHECK19-NEXT:    br i1 [[TMP28]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
11387 // CHECK19:       .omp.final.then:
11388 // CHECK19-NEXT:    [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
11389 // CHECK19-NEXT:    [[TMP30:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
11390 // CHECK19-NEXT:    [[TMP31:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
11391 // CHECK19-NEXT:    [[SUB20:%.*]] = sub i32 [[TMP30]], [[TMP31]]
11392 // CHECK19-NEXT:    [[SUB21:%.*]] = sub i32 [[SUB20]], 1
11393 // CHECK19-NEXT:    [[ADD22:%.*]] = add i32 [[SUB21]], 1
11394 // CHECK19-NEXT:    [[DIV23:%.*]] = udiv i32 [[ADD22]], 1
11395 // CHECK19-NEXT:    [[MUL24:%.*]] = mul i32 [[DIV23]], 1
11396 // CHECK19-NEXT:    [[ADD25:%.*]] = add i32 [[TMP29]], [[MUL24]]
11397 // CHECK19-NEXT:    store i32 [[ADD25]], i32* [[I6]], align 4
11398 // CHECK19-NEXT:    br label [[DOTOMP_FINAL_DONE]]
11399 // CHECK19:       .omp.final.done:
11400 // CHECK19-NEXT:    br label [[OMP_PRECOND_END]]
11401 // CHECK19:       omp.precond.end:
11402 // CHECK19-NEXT:    ret void
11403 //
11404 //
11405 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215
11406 // CHECK19-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {
11407 // CHECK19-NEXT:  entry:
11408 // CHECK19-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
11409 // CHECK19-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
11410 // CHECK19-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
11411 // CHECK19-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
11412 // CHECK19-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 4
11413 // CHECK19-NEXT:    [[B_CASTED:%.*]] = alloca i32, align 4
11414 // CHECK19-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
11415 // CHECK19-NEXT:    store i32 [[B]], i32* [[B_ADDR]], align 4
11416 // CHECK19-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
11417 // CHECK19-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
11418 // CHECK19-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 4
11419 // CHECK19-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
11420 // CHECK19-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
11421 // CHECK19-NEXT:    [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
11422 // CHECK19-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
11423 // CHECK19-NEXT:    [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4
11424 // CHECK19-NEXT:    store i32 [[TMP4]], i32* [[B_CASTED]], align 4
11425 // CHECK19-NEXT:    [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4
11426 // CHECK19-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]])
11427 // CHECK19-NEXT:    ret void
11428 //
11429 //
11430 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..5
11431 // CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] {
11432 // CHECK19-NEXT:  entry:
11433 // CHECK19-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
11434 // CHECK19-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
11435 // CHECK19-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
11436 // CHECK19-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
11437 // CHECK19-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
11438 // CHECK19-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
11439 // CHECK19-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 4
11440 // CHECK19-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
11441 // CHECK19-NEXT:    [[TMP:%.*]] = alloca i32, align 4
11442 // CHECK19-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
11443 // CHECK19-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
11444 // CHECK19-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
11445 // CHECK19-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
11446 // CHECK19-NEXT:    [[I:%.*]] = alloca i32, align 4
11447 // CHECK19-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
11448 // CHECK19-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
11449 // CHECK19-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
11450 // CHECK19-NEXT:    store i32 [[B]], i32* [[B_ADDR]], align 4
11451 // CHECK19-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
11452 // CHECK19-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
11453 // CHECK19-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 4
11454 // CHECK19-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
11455 // CHECK19-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
11456 // CHECK19-NEXT:    [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
11457 // CHECK19-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
11458 // CHECK19-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
11459 // CHECK19-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
11460 // CHECK19-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
11461 // CHECK19-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
11462 // CHECK19-NEXT:    [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
11463 // CHECK19-NEXT:    [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
11464 // CHECK19-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
11465 // CHECK19-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
11466 // CHECK19-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 9
11467 // CHECK19-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
11468 // CHECK19:       cond.true:
11469 // CHECK19-NEXT:    br label [[COND_END:%.*]]
11470 // CHECK19:       cond.false:
11471 // CHECK19-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
11472 // CHECK19-NEXT:    br label [[COND_END]]
11473 // CHECK19:       cond.end:
11474 // CHECK19-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
11475 // CHECK19-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
11476 // CHECK19-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
11477 // CHECK19-NEXT:    store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
11478 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
11479 // CHECK19:       omp.inner.for.cond:
11480 // CHECK19-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !31
11481 // CHECK19-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !31
11482 // CHECK19-NEXT:    [[CMP3:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
11483 // CHECK19-NEXT:    br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
11484 // CHECK19:       omp.inner.for.body:
11485 // CHECK19-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !31
11486 // CHECK19-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
11487 // CHECK19-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
11488 // CHECK19-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !31
11489 // CHECK19-NEXT:    [[TMP12:%.*]] = load i32, i32* [[B_ADDR]], align 4, !llvm.access.group !31
11490 // CHECK19-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP12]] to double
11491 // CHECK19-NEXT:    [[ADD4:%.*]] = fadd double [[CONV]], 1.500000e+00
11492 // CHECK19-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
11493 // CHECK19-NEXT:    store double [[ADD4]], double* [[A]], align 4, !llvm.access.group !31
11494 // CHECK19-NEXT:    [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
11495 // CHECK19-NEXT:    [[TMP13:%.*]] = load double, double* [[A5]], align 4, !llvm.access.group !31
11496 // CHECK19-NEXT:    [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00
11497 // CHECK19-NEXT:    store double [[INC]], double* [[A5]], align 4, !llvm.access.group !31
11498 // CHECK19-NEXT:    [[CONV6:%.*]] = fptosi double [[INC]] to i16
11499 // CHECK19-NEXT:    [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]]
11500 // CHECK19-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP14]]
11501 // CHECK19-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
11502 // CHECK19-NEXT:    store i16 [[CONV6]], i16* [[ARRAYIDX7]], align 2, !llvm.access.group !31
11503 // CHECK19-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
11504 // CHECK19:       omp.body.continue:
11505 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
11506 // CHECK19:       omp.inner.for.inc:
11507 // CHECK19-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !31
11508 // CHECK19-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP15]], 1
11509 // CHECK19-NEXT:    store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !31
11510 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP32:![0-9]+]]
11511 // CHECK19:       omp.inner.for.end:
11512 // CHECK19-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
11513 // CHECK19:       omp.loop.exit:
11514 // CHECK19-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
11515 // CHECK19-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
11516 // CHECK19-NEXT:    [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0
11517 // CHECK19-NEXT:    br i1 [[TMP17]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
11518 // CHECK19:       .omp.final.then:
11519 // CHECK19-NEXT:    store i32 10, i32* [[I]], align 4
11520 // CHECK19-NEXT:    br label [[DOTOMP_FINAL_DONE]]
11521 // CHECK19:       .omp.final.done:
11522 // CHECK19-NEXT:    ret void
11523 //
11524 //
11525 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180
11526 // CHECK19-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
11527 // CHECK19-NEXT:  entry:
11528 // CHECK19-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
11529 // CHECK19-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
11530 // CHECK19-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
11531 // CHECK19-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
11532 // CHECK19-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
11533 // CHECK19-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
11534 // CHECK19-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
11535 // CHECK19-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
11536 // CHECK19-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
11537 // CHECK19-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
11538 // CHECK19-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
11539 // CHECK19-NEXT:    store i32 [[TMP1]], i32* [[A_CASTED]], align 4
11540 // CHECK19-NEXT:    [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
11541 // CHECK19-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
11542 // CHECK19-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
11543 // CHECK19-NEXT:    store i16 [[TMP3]], i16* [[CONV1]], align 2
11544 // CHECK19-NEXT:    [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
11545 // CHECK19-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]])
11546 // CHECK19-NEXT:    ret void
11547 //
11548 //
11549 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..6
11550 // CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {
11551 // CHECK19-NEXT:  entry:
11552 // CHECK19-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
11553 // CHECK19-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
11554 // CHECK19-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
11555 // CHECK19-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
11556 // CHECK19-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
11557 // CHECK19-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
11558 // CHECK19-NEXT:    [[TMP:%.*]] = alloca i32, align 4
11559 // CHECK19-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
11560 // CHECK19-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
11561 // CHECK19-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
11562 // CHECK19-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
11563 // CHECK19-NEXT:    [[I:%.*]] = alloca i32, align 4
11564 // CHECK19-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
11565 // CHECK19-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
11566 // CHECK19-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
11567 // CHECK19-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
11568 // CHECK19-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
11569 // CHECK19-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
11570 // CHECK19-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
11571 // CHECK19-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
11572 // CHECK19-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
11573 // CHECK19-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
11574 // CHECK19-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
11575 // CHECK19-NEXT:    [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
11576 // CHECK19-NEXT:    [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
11577 // CHECK19-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
11578 // CHECK19-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
11579 // CHECK19-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9
11580 // CHECK19-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
11581 // CHECK19:       cond.true:
11582 // CHECK19-NEXT:    br label [[COND_END:%.*]]
11583 // CHECK19:       cond.false:
11584 // CHECK19-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
11585 // CHECK19-NEXT:    br label [[COND_END]]
11586 // CHECK19:       cond.end:
11587 // CHECK19-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
11588 // CHECK19-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
11589 // CHECK19-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
11590 // CHECK19-NEXT:    store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
11591 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
11592 // CHECK19:       omp.inner.for.cond:
11593 // CHECK19-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !34
11594 // CHECK19-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !34
11595 // CHECK19-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
11596 // CHECK19-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
11597 // CHECK19:       omp.inner.for.body:
11598 // CHECK19-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !34
11599 // CHECK19-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
11600 // CHECK19-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
11601 // CHECK19-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !34
11602 // CHECK19-NEXT:    [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !34
11603 // CHECK19-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
11604 // CHECK19-NEXT:    store i32 [[ADD2]], i32* [[A_ADDR]], align 4, !llvm.access.group !34
11605 // CHECK19-NEXT:    [[TMP10:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !34
11606 // CHECK19-NEXT:    [[CONV3:%.*]] = sext i16 [[TMP10]] to i32
11607 // CHECK19-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
11608 // CHECK19-NEXT:    [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
11609 // CHECK19-NEXT:    store i16 [[CONV5]], i16* [[CONV]], align 2, !llvm.access.group !34
11610 // CHECK19-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
11611 // CHECK19-NEXT:    [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !34
11612 // CHECK19-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1
11613 // CHECK19-NEXT:    store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !34
11614 // CHECK19-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
11615 // CHECK19:       omp.body.continue:
11616 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
11617 // CHECK19:       omp.inner.for.inc:
11618 // CHECK19-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !34
11619 // CHECK19-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP12]], 1
11620 // CHECK19-NEXT:    store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !34
11621 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP35:![0-9]+]]
11622 // CHECK19:       omp.inner.for.end:
11623 // CHECK19-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
11624 // CHECK19:       omp.loop.exit:
11625 // CHECK19-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
11626 // CHECK19-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
11627 // CHECK19-NEXT:    [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
11628 // CHECK19-NEXT:    br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
11629 // CHECK19:       .omp.final.then:
11630 // CHECK19-NEXT:    store i32 10, i32* [[I]], align 4
11631 // CHECK19-NEXT:    br label [[DOTOMP_FINAL_DONE]]
11632 // CHECK19:       .omp.final.done:
11633 // CHECK19-NEXT:    ret void
11634 //
11635 //
11636 // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97
11637 // CHECK21-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] {
11638 // CHECK21-NEXT:  entry:
11639 // CHECK21-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
11640 // CHECK21-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
11641 // CHECK21-NEXT:    [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8
11642 // CHECK21-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
11643 // CHECK21-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]])
11644 // CHECK21-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
11645 // CHECK21-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
11646 // CHECK21-NEXT:    store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8
11647 // CHECK21-NEXT:    [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
11648 // CHECK21-NEXT:    [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
11649 // CHECK21-NEXT:    [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32*
11650 // CHECK21-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 4
11651 // CHECK21-NEXT:    [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 4
11652 // CHECK21-NEXT:    call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
11653 // CHECK21-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
11654 // CHECK21-NEXT:    [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
11655 // CHECK21-NEXT:    store i16 [[TMP3]], i16* [[CONV5]], align 2
11656 // CHECK21-NEXT:    [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
11657 // CHECK21-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]])
11658 // CHECK21-NEXT:    ret void
11659 //
11660 //
11661 // CHECK21-LABEL: define {{[^@]+}}@.omp_outlined.
11662 // CHECK21-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR1:[0-9]+]] {
11663 // CHECK21-NEXT:  entry:
11664 // CHECK21-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
11665 // CHECK21-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
11666 // CHECK21-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
11667 // CHECK21-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
11668 // CHECK21-NEXT:    [[TMP:%.*]] = alloca i32, align 4
11669 // CHECK21-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
11670 // CHECK21-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
11671 // CHECK21-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
11672 // CHECK21-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
11673 // CHECK21-NEXT:    [[I:%.*]] = alloca i32, align 4
11674 // CHECK21-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
11675 // CHECK21-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
11676 // CHECK21-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
11677 // CHECK21-NEXT:    [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
11678 // CHECK21-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
11679 // CHECK21-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
11680 // CHECK21-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
11681 // CHECK21-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
11682 // CHECK21-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
11683 // CHECK21-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
11684 // CHECK21-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
11685 // CHECK21-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
11686 // CHECK21-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
11687 // CHECK21-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
11688 // CHECK21:       cond.true:
11689 // CHECK21-NEXT:    br label [[COND_END:%.*]]
11690 // CHECK21:       cond.false:
11691 // CHECK21-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
11692 // CHECK21-NEXT:    br label [[COND_END]]
11693 // CHECK21:       cond.end:
11694 // CHECK21-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
11695 // CHECK21-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
11696 // CHECK21-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
11697 // CHECK21-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
11698 // CHECK21-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
11699 // CHECK21:       omp.inner.for.cond:
11700 // CHECK21-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
11701 // CHECK21-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !11
11702 // CHECK21-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
11703 // CHECK21-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
11704 // CHECK21:       omp.inner.for.body:
11705 // CHECK21-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
11706 // CHECK21-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
11707 // CHECK21-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
11708 // CHECK21-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11
11709 // CHECK21-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
11710 // CHECK21:       omp.body.continue:
11711 // CHECK21-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
11712 // CHECK21:       omp.inner.for.inc:
11713 // CHECK21-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
11714 // CHECK21-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
11715 // CHECK21-NEXT:    store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
11716 // CHECK21-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]
11717 // CHECK21:       omp.inner.for.end:
11718 // CHECK21-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
11719 // CHECK21:       omp.loop.exit:
11720 // CHECK21-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
11721 // CHECK21-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
11722 // CHECK21-NEXT:    [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0
11723 // CHECK21-NEXT:    br i1 [[TMP10]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
11724 // CHECK21:       .omp.final.then:
11725 // CHECK21-NEXT:    store i32 10, i32* [[I]], align 4
11726 // CHECK21-NEXT:    br label [[DOTOMP_FINAL_DONE]]
11727 // CHECK21:       .omp.final.done:
11728 // CHECK21-NEXT:    ret void
11729 //
11730 //
11731 // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111
11732 // CHECK21-SAME: (i64 noundef [[AA:%.*]]) #[[ATTR0]] {
11733 // CHECK21-NEXT:  entry:
11734 // CHECK21-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
11735 // CHECK21-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
11736 // CHECK21-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
11737 // CHECK21-NEXT:    [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
11738 // CHECK21-NEXT:    [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
11739 // CHECK21-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
11740 // CHECK21-NEXT:    store i16 [[TMP0]], i16* [[CONV1]], align 2
11741 // CHECK21-NEXT:    [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
11742 // CHECK21-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]])
11743 // CHECK21-NEXT:    ret void
11744 //
11745 //
11746 // CHECK21-LABEL: define {{[^@]+}}@.omp_outlined..1
11747 // CHECK21-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR1]] {
11748 // CHECK21-NEXT:  entry:
11749 // CHECK21-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
11750 // CHECK21-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
11751 // CHECK21-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
11752 // CHECK21-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
11753 // CHECK21-NEXT:    [[TMP:%.*]] = alloca i32, align 4
11754 // CHECK21-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
11755 // CHECK21-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
11756 // CHECK21-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
11757 // CHECK21-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
11758 // CHECK21-NEXT:    [[I:%.*]] = alloca i32, align 4
11759 // CHECK21-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
11760 // CHECK21-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
11761 // CHECK21-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
11762 // CHECK21-NEXT:    [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
11763 // CHECK21-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
11764 // CHECK21-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
11765 // CHECK21-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
11766 // CHECK21-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
11767 // CHECK21-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
11768 // CHECK21-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
11769 // CHECK21-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
11770 // CHECK21-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
11771 // CHECK21-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
11772 // CHECK21-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
11773 // CHECK21:       cond.true:
11774 // CHECK21-NEXT:    br label [[COND_END:%.*]]
11775 // CHECK21:       cond.false:
11776 // CHECK21-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
11777 // CHECK21-NEXT:    br label [[COND_END]]
11778 // CHECK21:       cond.end:
11779 // CHECK21-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
11780 // CHECK21-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
11781 // CHECK21-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
11782 // CHECK21-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
11783 // CHECK21-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
11784 // CHECK21:       omp.inner.for.cond:
11785 // CHECK21-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
11786 // CHECK21-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !18
11787 // CHECK21-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
11788 // CHECK21-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
11789 // CHECK21:       omp.inner.for.body:
11790 // CHECK21-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
11791 // CHECK21-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
11792 // CHECK21-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
11793 // CHECK21-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18
11794 // CHECK21-NEXT:    [[TMP8:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !18
11795 // CHECK21-NEXT:    [[CONV2:%.*]] = sext i16 [[TMP8]] to i32
11796 // CHECK21-NEXT:    [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
11797 // CHECK21-NEXT:    [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
11798 // CHECK21-NEXT:    store i16 [[CONV4]], i16* [[CONV]], align 2, !llvm.access.group !18
11799 // CHECK21-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
11800 // CHECK21:       omp.body.continue:
11801 // CHECK21-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
11802 // CHECK21:       omp.inner.for.inc:
11803 // CHECK21-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
11804 // CHECK21-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP9]], 1
11805 // CHECK21-NEXT:    store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
11806 // CHECK21-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]
11807 // CHECK21:       omp.inner.for.end:
11808 // CHECK21-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
11809 // CHECK21:       omp.loop.exit:
11810 // CHECK21-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
11811 // CHECK21-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
11812 // CHECK21-NEXT:    [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0
11813 // CHECK21-NEXT:    br i1 [[TMP11]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
11814 // CHECK21:       .omp.final.then:
11815 // CHECK21-NEXT:    store i32 10, i32* [[I]], align 4
11816 // CHECK21-NEXT:    br label [[DOTOMP_FINAL_DONE]]
11817 // CHECK21:       .omp.final.done:
11818 // CHECK21-NEXT:    ret void
11819 //
11820 //
11821 // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118
11822 // CHECK21-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] {
11823 // CHECK21-NEXT:  entry:
11824 // CHECK21-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
11825 // CHECK21-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
11826 // CHECK21-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
11827 // CHECK21-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
11828 // CHECK21-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
11829 // CHECK21-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
11830 // CHECK21-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
11831 // CHECK21-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
11832 // CHECK21-NEXT:    [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
11833 // CHECK21-NEXT:    [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
11834 // CHECK21-NEXT:    store i32 [[TMP0]], i32* [[CONV2]], align 4
11835 // CHECK21-NEXT:    [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
11836 // CHECK21-NEXT:    [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
11837 // CHECK21-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
11838 // CHECK21-NEXT:    store i16 [[TMP2]], i16* [[CONV3]], align 2
11839 // CHECK21-NEXT:    [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
11840 // CHECK21-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
11841 // CHECK21-NEXT:    ret void
11842 //
11843 //
11844 // CHECK21-LABEL: define {{[^@]+}}@.omp_outlined..2
11845 // CHECK21-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR1]] {
11846 // CHECK21-NEXT:  entry:
11847 // CHECK21-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
11848 // CHECK21-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
11849 // CHECK21-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
11850 // CHECK21-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
11851 // CHECK21-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
11852 // CHECK21-NEXT:    [[TMP:%.*]] = alloca i32, align 4
11853 // CHECK21-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
11854 // CHECK21-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
11855 // CHECK21-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
11856 // CHECK21-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
11857 // CHECK21-NEXT:    [[I:%.*]] = alloca i32, align 4
11858 // CHECK21-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
11859 // CHECK21-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
11860 // CHECK21-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
11861 // CHECK21-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
11862 // CHECK21-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
11863 // CHECK21-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
11864 // CHECK21-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
11865 // CHECK21-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
11866 // CHECK21-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
11867 // CHECK21-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
11868 // CHECK21-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
11869 // CHECK21-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
11870 // CHECK21-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
11871 // CHECK21-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
11872 // CHECK21-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
11873 // CHECK21-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
11874 // CHECK21:       cond.true:
11875 // CHECK21-NEXT:    br label [[COND_END:%.*]]
11876 // CHECK21:       cond.false:
11877 // CHECK21-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
11878 // CHECK21-NEXT:    br label [[COND_END]]
11879 // CHECK21:       cond.end:
11880 // CHECK21-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
11881 // CHECK21-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
11882 // CHECK21-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
11883 // CHECK21-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
11884 // CHECK21-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
11885 // CHECK21:       omp.inner.for.cond:
11886 // CHECK21-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
11887 // CHECK21-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !21
11888 // CHECK21-NEXT:    [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
11889 // CHECK21-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
11890 // CHECK21:       omp.inner.for.body:
11891 // CHECK21-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
11892 // CHECK21-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
11893 // CHECK21-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
11894 // CHECK21-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !21
11895 // CHECK21-NEXT:    [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !21
11896 // CHECK21-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
11897 // CHECK21-NEXT:    store i32 [[ADD3]], i32* [[CONV]], align 4, !llvm.access.group !21
11898 // CHECK21-NEXT:    [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 2, !llvm.access.group !21
11899 // CHECK21-NEXT:    [[CONV4:%.*]] = sext i16 [[TMP9]] to i32
11900 // CHECK21-NEXT:    [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
11901 // CHECK21-NEXT:    [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
11902 // CHECK21-NEXT:    store i16 [[CONV6]], i16* [[CONV1]], align 2, !llvm.access.group !21
11903 // CHECK21-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
11904 // CHECK21:       omp.body.continue:
11905 // CHECK21-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
11906 // CHECK21:       omp.inner.for.inc:
11907 // CHECK21-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
11908 // CHECK21-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1
11909 // CHECK21-NEXT:    store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
11910 // CHECK21-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]]
11911 // CHECK21:       omp.inner.for.end:
11912 // CHECK21-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
11913 // CHECK21:       omp.loop.exit:
11914 // CHECK21-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
11915 // CHECK21-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
11916 // CHECK21-NEXT:    [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
11917 // CHECK21-NEXT:    br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
11918 // CHECK21:       .omp.final.then:
11919 // CHECK21-NEXT:    store i32 10, i32* [[I]], align 4
11920 // CHECK21-NEXT:    br label [[DOTOMP_FINAL_DONE]]
11921 // CHECK21:       .omp.final.done:
11922 // CHECK21-NEXT:    ret void
11923 //
11924 //
11925 // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142
11926 // CHECK21-SAME: (i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] {
11927 // CHECK21-NEXT:  entry:
11928 // CHECK21-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
11929 // CHECK21-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
11930 // CHECK21-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
11931 // CHECK21-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 8
11932 // CHECK21-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
11933 // CHECK21-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
11934 // CHECK21-NEXT:    [[VLA_ADDR4:%.*]] = alloca i64, align 8
11935 // CHECK21-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 8
11936 // CHECK21-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
11937 // CHECK21-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
11938 // CHECK21-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
11939 // CHECK21-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
11940 // CHECK21-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
11941 // CHECK21-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 8
11942 // CHECK21-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
11943 // CHECK21-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
11944 // CHECK21-NEXT:    store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
11945 // CHECK21-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 8
11946 // CHECK21-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
11947 // CHECK21-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
11948 // CHECK21-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
11949 // CHECK21-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
11950 // CHECK21-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
11951 // CHECK21-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
11952 // CHECK21-NEXT:    [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
11953 // CHECK21-NEXT:    [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
11954 // CHECK21-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
11955 // CHECK21-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
11956 // CHECK21-NEXT:    [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
11957 // CHECK21-NEXT:    [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
11958 // CHECK21-NEXT:    store i32 [[TMP8]], i32* [[CONV5]], align 4
11959 // CHECK21-NEXT:    [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
11960 // CHECK21-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]])
11961 // CHECK21-NEXT:    ret void
11962 //
11963 //
11964 // CHECK21-LABEL: define {{[^@]+}}@.omp_outlined..3
11965 // CHECK21-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR1]] {
11966 // CHECK21-NEXT:  entry:
11967 // CHECK21-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
11968 // CHECK21-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
11969 // CHECK21-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
11970 // CHECK21-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
11971 // CHECK21-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
11972 // CHECK21-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 8
11973 // CHECK21-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
11974 // CHECK21-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
11975 // CHECK21-NEXT:    [[VLA_ADDR4:%.*]] = alloca i64, align 8
11976 // CHECK21-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 8
11977 // CHECK21-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
11978 // CHECK21-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
11979 // CHECK21-NEXT:    [[TMP:%.*]] = alloca i32, align 4
11980 // CHECK21-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
11981 // CHECK21-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
11982 // CHECK21-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
11983 // CHECK21-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
11984 // CHECK21-NEXT:    [[I:%.*]] = alloca i32, align 4
11985 // CHECK21-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
11986 // CHECK21-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
11987 // CHECK21-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
11988 // CHECK21-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
11989 // CHECK21-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
11990 // CHECK21-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 8
11991 // CHECK21-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
11992 // CHECK21-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
11993 // CHECK21-NEXT:    store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
11994 // CHECK21-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 8
11995 // CHECK21-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
11996 // CHECK21-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
11997 // CHECK21-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
11998 // CHECK21-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
11999 // CHECK21-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
12000 // CHECK21-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
12001 // CHECK21-NEXT:    [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
12002 // CHECK21-NEXT:    [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
12003 // CHECK21-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
12004 // CHECK21-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
12005 // CHECK21-NEXT:    [[ARRAYDECAY:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 0
12006 // CHECK21-NEXT:    call void @llvm.assume(i1 true) [ "align"(float* [[ARRAYDECAY]], i64 16) ]
12007 // CHECK21-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
12008 // CHECK21-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
12009 // CHECK21-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
12010 // CHECK21-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
12011 // CHECK21-NEXT:    [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
12012 // CHECK21-NEXT:    [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4
12013 // CHECK21-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
12014 // CHECK21-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
12015 // CHECK21-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP10]], 9
12016 // CHECK21-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
12017 // CHECK21:       cond.true:
12018 // CHECK21-NEXT:    br label [[COND_END:%.*]]
12019 // CHECK21:       cond.false:
12020 // CHECK21-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
12021 // CHECK21-NEXT:    br label [[COND_END]]
12022 // CHECK21:       cond.end:
12023 // CHECK21-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ]
12024 // CHECK21-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
12025 // CHECK21-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
12026 // CHECK21-NEXT:    store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4
12027 // CHECK21-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
12028 // CHECK21:       omp.inner.for.cond:
12029 // CHECK21-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
12030 // CHECK21-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !24
12031 // CHECK21-NEXT:    [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
12032 // CHECK21-NEXT:    br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
12033 // CHECK21:       omp.inner.for.body:
12034 // CHECK21-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
12035 // CHECK21-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1
12036 // CHECK21-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
12037 // CHECK21-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !24
12038 // CHECK21-NEXT:    [[TMP16:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !24
12039 // CHECK21-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP16]], 1
12040 // CHECK21-NEXT:    store i32 [[ADD6]], i32* [[CONV]], align 4, !llvm.access.group !24
12041 // CHECK21-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
12042 // CHECK21-NEXT:    [[TMP17:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !24
12043 // CHECK21-NEXT:    [[CONV7:%.*]] = fpext float [[TMP17]] to double
12044 // CHECK21-NEXT:    [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00
12045 // CHECK21-NEXT:    [[CONV9:%.*]] = fptrunc double [[ADD8]] to float
12046 // CHECK21-NEXT:    store float [[CONV9]], float* [[ARRAYIDX]], align 4, !llvm.access.group !24
12047 // CHECK21-NEXT:    [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3
12048 // CHECK21-NEXT:    [[TMP18:%.*]] = load float, float* [[ARRAYIDX10]], align 4, !llvm.access.group !24
12049 // CHECK21-NEXT:    [[CONV11:%.*]] = fpext float [[TMP18]] to double
12050 // CHECK21-NEXT:    [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00
12051 // CHECK21-NEXT:    [[CONV13:%.*]] = fptrunc double [[ADD12]] to float
12052 // CHECK21-NEXT:    store float [[CONV13]], float* [[ARRAYIDX10]], align 4, !llvm.access.group !24
12053 // CHECK21-NEXT:    [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1
12054 // CHECK21-NEXT:    [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX14]], i64 0, i64 2
12055 // CHECK21-NEXT:    [[TMP19:%.*]] = load double, double* [[ARRAYIDX15]], align 8, !llvm.access.group !24
12056 // CHECK21-NEXT:    [[ADD16:%.*]] = fadd double [[TMP19]], 1.000000e+00
12057 // CHECK21-NEXT:    store double [[ADD16]], double* [[ARRAYIDX15]], align 8, !llvm.access.group !24
12058 // CHECK21-NEXT:    [[TMP20:%.*]] = mul nsw i64 1, [[TMP5]]
12059 // CHECK21-NEXT:    [[ARRAYIDX17:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP20]]
12060 // CHECK21-NEXT:    [[ARRAYIDX18:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX17]], i64 3
12061 // CHECK21-NEXT:    [[TMP21:%.*]] = load double, double* [[ARRAYIDX18]], align 8, !llvm.access.group !24
12062 // CHECK21-NEXT:    [[ADD19:%.*]] = fadd double [[TMP21]], 1.000000e+00
12063 // CHECK21-NEXT:    store double [[ADD19]], double* [[ARRAYIDX18]], align 8, !llvm.access.group !24
12064 // CHECK21-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0
12065 // CHECK21-NEXT:    [[TMP22:%.*]] = load i64, i64* [[X]], align 8, !llvm.access.group !24
12066 // CHECK21-NEXT:    [[ADD20:%.*]] = add nsw i64 [[TMP22]], 1
12067 // CHECK21-NEXT:    store i64 [[ADD20]], i64* [[X]], align 8, !llvm.access.group !24
12068 // CHECK21-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1
12069 // CHECK21-NEXT:    [[TMP23:%.*]] = load i8, i8* [[Y]], align 8, !llvm.access.group !24
12070 // CHECK21-NEXT:    [[CONV21:%.*]] = sext i8 [[TMP23]] to i32
12071 // CHECK21-NEXT:    [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1
12072 // CHECK21-NEXT:    [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8
12073 // CHECK21-NEXT:    store i8 [[CONV23]], i8* [[Y]], align 8, !llvm.access.group !24
12074 // CHECK21-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
12075 // CHECK21:       omp.body.continue:
12076 // CHECK21-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
12077 // CHECK21:       omp.inner.for.inc:
12078 // CHECK21-NEXT:    [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
12079 // CHECK21-NEXT:    [[ADD24:%.*]] = add nsw i32 [[TMP24]], 1
12080 // CHECK21-NEXT:    store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
12081 // CHECK21-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]]
12082 // CHECK21:       omp.inner.for.end:
12083 // CHECK21-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
12084 // CHECK21:       omp.loop.exit:
12085 // CHECK21-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]])
12086 // CHECK21-NEXT:    [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
12087 // CHECK21-NEXT:    [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
12088 // CHECK21-NEXT:    br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
12089 // CHECK21:       .omp.final.then:
12090 // CHECK21-NEXT:    store i32 10, i32* [[I]], align 4
12091 // CHECK21-NEXT:    br label [[DOTOMP_FINAL_DONE]]
12092 // CHECK21:       .omp.final.done:
12093 // CHECK21-NEXT:    ret void
12094 //
12095 //
12096 // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197
12097 // CHECK21-SAME: (i64 noundef [[A:%.*]], i64 noundef [[N:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
12098 // CHECK21-NEXT:  entry:
12099 // CHECK21-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
12100 // CHECK21-NEXT:    [[N_ADDR:%.*]] = alloca i64, align 8
12101 // CHECK21-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
12102 // CHECK21-NEXT:    [[AAA_ADDR:%.*]] = alloca i64, align 8
12103 // CHECK21-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
12104 // CHECK21-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
12105 // CHECK21-NEXT:    [[N_CASTED:%.*]] = alloca i64, align 8
12106 // CHECK21-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
12107 // CHECK21-NEXT:    [[AAA_CASTED:%.*]] = alloca i64, align 8
12108 // CHECK21-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
12109 // CHECK21-NEXT:    store i64 [[N]], i64* [[N_ADDR]], align 8
12110 // CHECK21-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
12111 // CHECK21-NEXT:    store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
12112 // CHECK21-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
12113 // CHECK21-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
12114 // CHECK21-NEXT:    [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32*
12115 // CHECK21-NEXT:    [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
12116 // CHECK21-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
12117 // CHECK21-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
12118 // CHECK21-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
12119 // CHECK21-NEXT:    [[CONV4:%.*]] = bitcast i64* [[A_CASTED]] to i32*
12120 // CHECK21-NEXT:    store i32 [[TMP1]], i32* [[CONV4]], align 4
12121 // CHECK21-NEXT:    [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
12122 // CHECK21-NEXT:    [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 4
12123 // CHECK21-NEXT:    [[CONV5:%.*]] = bitcast i64* [[N_CASTED]] to i32*
12124 // CHECK21-NEXT:    store i32 [[TMP3]], i32* [[CONV5]], align 4
12125 // CHECK21-NEXT:    [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8
12126 // CHECK21-NEXT:    [[TMP5:%.*]] = load i16, i16* [[CONV2]], align 2
12127 // CHECK21-NEXT:    [[CONV6:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
12128 // CHECK21-NEXT:    store i16 [[TMP5]], i16* [[CONV6]], align 2
12129 // CHECK21-NEXT:    [[TMP6:%.*]] = load i64, i64* [[AA_CASTED]], align 8
12130 // CHECK21-NEXT:    [[TMP7:%.*]] = load i8, i8* [[CONV3]], align 1
12131 // CHECK21-NEXT:    [[CONV7:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
12132 // CHECK21-NEXT:    store i8 [[TMP7]], i8* [[CONV7]], align 1
12133 // CHECK21-NEXT:    [[TMP8:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
12134 // CHECK21-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]], [10 x i32]* [[TMP0]])
12135 // CHECK21-NEXT:    ret void
12136 //
12137 //
12138 // CHECK21-LABEL: define {{[^@]+}}@.omp_outlined..4
12139 // CHECK21-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[N:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {
12140 // CHECK21-NEXT:  entry:
12141 // CHECK21-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
12142 // CHECK21-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
12143 // CHECK21-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
12144 // CHECK21-NEXT:    [[N_ADDR:%.*]] = alloca i64, align 8
12145 // CHECK21-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
12146 // CHECK21-NEXT:    [[AAA_ADDR:%.*]] = alloca i64, align 8
12147 // CHECK21-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
12148 // CHECK21-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
12149 // CHECK21-NEXT:    [[TMP:%.*]] = alloca i32, align 4
12150 // CHECK21-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
12151 // CHECK21-NEXT:    [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4
12152 // CHECK21-NEXT:    [[DOTCAPTURE_EXPR_5:%.*]] = alloca i32, align 4
12153 // CHECK21-NEXT:    [[I:%.*]] = alloca i32, align 4
12154 // CHECK21-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
12155 // CHECK21-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
12156 // CHECK21-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
12157 // CHECK21-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
12158 // CHECK21-NEXT:    [[I8:%.*]] = alloca i32, align 4
12159 // CHECK21-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
12160 // CHECK21-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
12161 // CHECK21-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
12162 // CHECK21-NEXT:    store i64 [[N]], i64* [[N_ADDR]], align 8
12163 // CHECK21-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
12164 // CHECK21-NEXT:    store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
12165 // CHECK21-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
12166 // CHECK21-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
12167 // CHECK21-NEXT:    [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32*
12168 // CHECK21-NEXT:    [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
12169 // CHECK21-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
12170 // CHECK21-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
12171 // CHECK21-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
12172 // CHECK21-NEXT:    store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
12173 // CHECK21-NEXT:    [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4
12174 // CHECK21-NEXT:    store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_4]], align 4
12175 // CHECK21-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4
12176 // CHECK21-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
12177 // CHECK21-NEXT:    [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]]
12178 // CHECK21-NEXT:    [[SUB6:%.*]] = sub i32 [[SUB]], 1
12179 // CHECK21-NEXT:    [[ADD:%.*]] = add i32 [[SUB6]], 1
12180 // CHECK21-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], 1
12181 // CHECK21-NEXT:    [[SUB7:%.*]] = sub i32 [[DIV]], 1
12182 // CHECK21-NEXT:    store i32 [[SUB7]], i32* [[DOTCAPTURE_EXPR_5]], align 4
12183 // CHECK21-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
12184 // CHECK21-NEXT:    store i32 [[TMP5]], i32* [[I]], align 4
12185 // CHECK21-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
12186 // CHECK21-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4
12187 // CHECK21-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]]
12188 // CHECK21-NEXT:    br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
12189 // CHECK21:       omp.precond.then:
12190 // CHECK21-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
12191 // CHECK21-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4
12192 // CHECK21-NEXT:    store i32 [[TMP8]], i32* [[DOTOMP_UB]], align 4
12193 // CHECK21-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
12194 // CHECK21-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
12195 // CHECK21-NEXT:    [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
12196 // CHECK21-NEXT:    [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
12197 // CHECK21-NEXT:    call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
12198 // CHECK21-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
12199 // CHECK21-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4
12200 // CHECK21-NEXT:    [[CMP9:%.*]] = icmp ugt i32 [[TMP11]], [[TMP12]]
12201 // CHECK21-NEXT:    br i1 [[CMP9]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
12202 // CHECK21:       cond.true:
12203 // CHECK21-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4
12204 // CHECK21-NEXT:    br label [[COND_END:%.*]]
12205 // CHECK21:       cond.false:
12206 // CHECK21-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
12207 // CHECK21-NEXT:    br label [[COND_END]]
12208 // CHECK21:       cond.end:
12209 // CHECK21-NEXT:    [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ]
12210 // CHECK21-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
12211 // CHECK21-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
12212 // CHECK21-NEXT:    store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4
12213 // CHECK21-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
12214 // CHECK21:       omp.inner.for.cond:
12215 // CHECK21-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27
12216 // CHECK21-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !27
12217 // CHECK21-NEXT:    [[ADD10:%.*]] = add i32 [[TMP17]], 1
12218 // CHECK21-NEXT:    [[CMP11:%.*]] = icmp ult i32 [[TMP16]], [[ADD10]]
12219 // CHECK21-NEXT:    br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
12220 // CHECK21:       omp.inner.for.body:
12221 // CHECK21-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group !27
12222 // CHECK21-NEXT:    [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27
12223 // CHECK21-NEXT:    [[MUL:%.*]] = mul i32 [[TMP19]], 1
12224 // CHECK21-NEXT:    [[ADD12:%.*]] = add i32 [[TMP18]], [[MUL]]
12225 // CHECK21-NEXT:    store i32 [[ADD12]], i32* [[I8]], align 4, !llvm.access.group !27
12226 // CHECK21-NEXT:    [[TMP20:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !27
12227 // CHECK21-NEXT:    [[ADD13:%.*]] = add nsw i32 [[TMP20]], 1
12228 // CHECK21-NEXT:    store i32 [[ADD13]], i32* [[CONV]], align 4, !llvm.access.group !27
12229 // CHECK21-NEXT:    [[TMP21:%.*]] = load i16, i16* [[CONV2]], align 2, !llvm.access.group !27
12230 // CHECK21-NEXT:    [[CONV14:%.*]] = sext i16 [[TMP21]] to i32
12231 // CHECK21-NEXT:    [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1
12232 // CHECK21-NEXT:    [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16
12233 // CHECK21-NEXT:    store i16 [[CONV16]], i16* [[CONV2]], align 2, !llvm.access.group !27
12234 // CHECK21-NEXT:    [[TMP22:%.*]] = load i8, i8* [[CONV3]], align 1, !llvm.access.group !27
12235 // CHECK21-NEXT:    [[CONV17:%.*]] = sext i8 [[TMP22]] to i32
12236 // CHECK21-NEXT:    [[ADD18:%.*]] = add nsw i32 [[CONV17]], 1
12237 // CHECK21-NEXT:    [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8
12238 // CHECK21-NEXT:    store i8 [[CONV19]], i8* [[CONV3]], align 1, !llvm.access.group !27
12239 // CHECK21-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
12240 // CHECK21-NEXT:    [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !27
12241 // CHECK21-NEXT:    [[ADD20:%.*]] = add nsw i32 [[TMP23]], 1
12242 // CHECK21-NEXT:    store i32 [[ADD20]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !27
12243 // CHECK21-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
12244 // CHECK21:       omp.body.continue:
12245 // CHECK21-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
12246 // CHECK21:       omp.inner.for.inc:
12247 // CHECK21-NEXT:    [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27
12248 // CHECK21-NEXT:    [[ADD21:%.*]] = add i32 [[TMP24]], 1
12249 // CHECK21-NEXT:    store i32 [[ADD21]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27
12250 // CHECK21-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]]
12251 // CHECK21:       omp.inner.for.end:
12252 // CHECK21-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
12253 // CHECK21:       omp.loop.exit:
12254 // CHECK21-NEXT:    [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
12255 // CHECK21-NEXT:    [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4
12256 // CHECK21-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]])
12257 // CHECK21-NEXT:    [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
12258 // CHECK21-NEXT:    [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0
12259 // CHECK21-NEXT:    br i1 [[TMP28]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
12260 // CHECK21:       .omp.final.then:
12261 // CHECK21-NEXT:    [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
12262 // CHECK21-NEXT:    [[TMP30:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4
12263 // CHECK21-NEXT:    [[TMP31:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
12264 // CHECK21-NEXT:    [[SUB22:%.*]] = sub i32 [[TMP30]], [[TMP31]]
12265 // CHECK21-NEXT:    [[SUB23:%.*]] = sub i32 [[SUB22]], 1
12266 // CHECK21-NEXT:    [[ADD24:%.*]] = add i32 [[SUB23]], 1
12267 // CHECK21-NEXT:    [[DIV25:%.*]] = udiv i32 [[ADD24]], 1
12268 // CHECK21-NEXT:    [[MUL26:%.*]] = mul i32 [[DIV25]], 1
12269 // CHECK21-NEXT:    [[ADD27:%.*]] = add i32 [[TMP29]], [[MUL26]]
12270 // CHECK21-NEXT:    store i32 [[ADD27]], i32* [[I8]], align 4
12271 // CHECK21-NEXT:    br label [[DOTOMP_FINAL_DONE]]
12272 // CHECK21:       .omp.final.done:
12273 // CHECK21-NEXT:    br label [[OMP_PRECOND_END]]
12274 // CHECK21:       omp.precond.end:
12275 // CHECK21-NEXT:    ret void
12276 //
12277 //
12278 // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215
12279 // CHECK21-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
12280 // CHECK21-NEXT:  entry:
12281 // CHECK21-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
12282 // CHECK21-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
12283 // CHECK21-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
12284 // CHECK21-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
12285 // CHECK21-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 8
12286 // CHECK21-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
12287 // CHECK21-NEXT:    [[B_CASTED:%.*]] = alloca i64, align 8
12288 // CHECK21-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
12289 // CHECK21-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
12290 // CHECK21-NEXT:    store i64 [[B]], i64* [[B_ADDR]], align 8
12291 // CHECK21-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
12292 // CHECK21-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
12293 // CHECK21-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 8
12294 // CHECK21-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
12295 // CHECK21-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
12296 // CHECK21-NEXT:    [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
12297 // CHECK21-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
12298 // CHECK21-NEXT:    [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
12299 // CHECK21-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
12300 // CHECK21-NEXT:    [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
12301 // CHECK21-NEXT:    [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
12302 // CHECK21-NEXT:    [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i32*
12303 // CHECK21-NEXT:    store i32 [[TMP4]], i32* [[CONV4]], align 4
12304 // CHECK21-NEXT:    [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
12305 // CHECK21-NEXT:    [[TMP6:%.*]] = load i8, i8* [[CONV3]], align 1
12306 // CHECK21-NEXT:    [[TOBOOL:%.*]] = trunc i8 [[TMP6]] to i1
12307 // CHECK21-NEXT:    [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
12308 // CHECK21-NEXT:    [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
12309 // CHECK21-NEXT:    store i8 [[FROMBOOL]], i8* [[CONV5]], align 1
12310 // CHECK21-NEXT:    [[TMP7:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
12311 // CHECK21-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]], i64 [[TMP7]])
12312 // CHECK21-NEXT:    ret void
12313 //
12314 //
12315 // CHECK21-LABEL: define {{[^@]+}}@.omp_outlined..5
12316 // CHECK21-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
12317 // CHECK21-NEXT:  entry:
12318 // CHECK21-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
12319 // CHECK21-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
12320 // CHECK21-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
12321 // CHECK21-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
12322 // CHECK21-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
12323 // CHECK21-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
12324 // CHECK21-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 8
12325 // CHECK21-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
12326 // CHECK21-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
12327 // CHECK21-NEXT:    [[TMP:%.*]] = alloca i32, align 4
12328 // CHECK21-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
12329 // CHECK21-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
12330 // CHECK21-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
12331 // CHECK21-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
12332 // CHECK21-NEXT:    [[I:%.*]] = alloca i32, align 4
12333 // CHECK21-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
12334 // CHECK21-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
12335 // CHECK21-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
12336 // CHECK21-NEXT:    store i64 [[B]], i64* [[B_ADDR]], align 8
12337 // CHECK21-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
12338 // CHECK21-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
12339 // CHECK21-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 8
12340 // CHECK21-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
12341 // CHECK21-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
12342 // CHECK21-NEXT:    [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
12343 // CHECK21-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
12344 // CHECK21-NEXT:    [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
12345 // CHECK21-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
12346 // CHECK21-NEXT:    [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
12347 // CHECK21-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
12348 // CHECK21-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
12349 // CHECK21-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
12350 // CHECK21-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
12351 // CHECK21-NEXT:    [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
12352 // CHECK21-NEXT:    [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
12353 // CHECK21-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
12354 // CHECK21-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
12355 // CHECK21-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 9
12356 // CHECK21-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
12357 // CHECK21:       cond.true:
12358 // CHECK21-NEXT:    br label [[COND_END:%.*]]
12359 // CHECK21:       cond.false:
12360 // CHECK21-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
12361 // CHECK21-NEXT:    br label [[COND_END]]
12362 // CHECK21:       cond.end:
12363 // CHECK21-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
12364 // CHECK21-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
12365 // CHECK21-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
12366 // CHECK21-NEXT:    store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
12367 // CHECK21-NEXT:    [[TMP9:%.*]] = load i8, i8* [[CONV3]], align 1
12368 // CHECK21-NEXT:    [[TOBOOL:%.*]] = trunc i8 [[TMP9]] to i1
12369 // CHECK21-NEXT:    br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
12370 // CHECK21:       omp_if.then:
12371 // CHECK21-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
12372 // CHECK21:       omp.inner.for.cond:
12373 // CHECK21-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30
12374 // CHECK21-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !30
12375 // CHECK21-NEXT:    [[CMP4:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]
12376 // CHECK21-NEXT:    br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
12377 // CHECK21:       omp.inner.for.body:
12378 // CHECK21-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30
12379 // CHECK21-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1
12380 // CHECK21-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
12381 // CHECK21-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !30
12382 // CHECK21-NEXT:    [[TMP13:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !30
12383 // CHECK21-NEXT:    [[CONV5:%.*]] = sitofp i32 [[TMP13]] to double
12384 // CHECK21-NEXT:    [[ADD6:%.*]] = fadd double [[CONV5]], 1.500000e+00
12385 // CHECK21-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
12386 // CHECK21-NEXT:    store double [[ADD6]], double* [[A]], align 8, !llvm.access.group !30
12387 // CHECK21-NEXT:    [[A7:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
12388 // CHECK21-NEXT:    [[TMP14:%.*]] = load double, double* [[A7]], align 8, !llvm.access.group !30
12389 // CHECK21-NEXT:    [[INC:%.*]] = fadd double [[TMP14]], 1.000000e+00
12390 // CHECK21-NEXT:    store double [[INC]], double* [[A7]], align 8, !llvm.access.group !30
12391 // CHECK21-NEXT:    [[CONV8:%.*]] = fptosi double [[INC]] to i16
12392 // CHECK21-NEXT:    [[TMP15:%.*]] = mul nsw i64 1, [[TMP2]]
12393 // CHECK21-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP15]]
12394 // CHECK21-NEXT:    [[ARRAYIDX9:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
12395 // CHECK21-NEXT:    store i16 [[CONV8]], i16* [[ARRAYIDX9]], align 2, !llvm.access.group !30
12396 // CHECK21-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
12397 // CHECK21:       omp.body.continue:
12398 // CHECK21-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
12399 // CHECK21:       omp.inner.for.inc:
12400 // CHECK21-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30
12401 // CHECK21-NEXT:    [[ADD10:%.*]] = add nsw i32 [[TMP16]], 1
12402 // CHECK21-NEXT:    store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30
12403 // CHECK21-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP31:![0-9]+]]
12404 // CHECK21:       omp.inner.for.end:
12405 // CHECK21-NEXT:    br label [[OMP_IF_END:%.*]]
12406 // CHECK21:       omp_if.else:
12407 // CHECK21-NEXT:    br label [[OMP_INNER_FOR_COND11:%.*]]
12408 // CHECK21:       omp.inner.for.cond11:
12409 // CHECK21-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
12410 // CHECK21-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
12411 // CHECK21-NEXT:    [[CMP12:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]]
12412 // CHECK21-NEXT:    br i1 [[CMP12]], label [[OMP_INNER_FOR_BODY13:%.*]], label [[OMP_INNER_FOR_END27:%.*]]
12413 // CHECK21:       omp.inner.for.body13:
12414 // CHECK21-NEXT:    [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
12415 // CHECK21-NEXT:    [[MUL14:%.*]] = mul nsw i32 [[TMP19]], 1
12416 // CHECK21-NEXT:    [[ADD15:%.*]] = add nsw i32 0, [[MUL14]]
12417 // CHECK21-NEXT:    store i32 [[ADD15]], i32* [[I]], align 4
12418 // CHECK21-NEXT:    [[TMP20:%.*]] = load i32, i32* [[CONV]], align 4
12419 // CHECK21-NEXT:    [[CONV16:%.*]] = sitofp i32 [[TMP20]] to double
12420 // CHECK21-NEXT:    [[ADD17:%.*]] = fadd double [[CONV16]], 1.500000e+00
12421 // CHECK21-NEXT:    [[A18:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
12422 // CHECK21-NEXT:    store double [[ADD17]], double* [[A18]], align 8
12423 // CHECK21-NEXT:    [[A19:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
12424 // CHECK21-NEXT:    [[TMP21:%.*]] = load double, double* [[A19]], align 8
12425 // CHECK21-NEXT:    [[INC20:%.*]] = fadd double [[TMP21]], 1.000000e+00
12426 // CHECK21-NEXT:    store double [[INC20]], double* [[A19]], align 8
12427 // CHECK21-NEXT:    [[CONV21:%.*]] = fptosi double [[INC20]] to i16
12428 // CHECK21-NEXT:    [[TMP22:%.*]] = mul nsw i64 1, [[TMP2]]
12429 // CHECK21-NEXT:    [[ARRAYIDX22:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP22]]
12430 // CHECK21-NEXT:    [[ARRAYIDX23:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX22]], i64 1
12431 // CHECK21-NEXT:    store i16 [[CONV21]], i16* [[ARRAYIDX23]], align 2
12432 // CHECK21-NEXT:    br label [[OMP_BODY_CONTINUE24:%.*]]
12433 // CHECK21:       omp.body.continue24:
12434 // CHECK21-NEXT:    br label [[OMP_INNER_FOR_INC25:%.*]]
12435 // CHECK21:       omp.inner.for.inc25:
12436 // CHECK21-NEXT:    [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
12437 // CHECK21-NEXT:    [[ADD26:%.*]] = add nsw i32 [[TMP23]], 1
12438 // CHECK21-NEXT:    store i32 [[ADD26]], i32* [[DOTOMP_IV]], align 4
12439 // CHECK21-NEXT:    br label [[OMP_INNER_FOR_COND11]], !llvm.loop [[LOOP33:![0-9]+]]
12440 // CHECK21:       omp.inner.for.end27:
12441 // CHECK21-NEXT:    br label [[OMP_IF_END]]
12442 // CHECK21:       omp_if.end:
12443 // CHECK21-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
12444 // CHECK21:       omp.loop.exit:
12445 // CHECK21-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
12446 // CHECK21-NEXT:    [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
12447 // CHECK21-NEXT:    [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0
12448 // CHECK21-NEXT:    br i1 [[TMP25]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
12449 // CHECK21:       .omp.final.then:
12450 // CHECK21-NEXT:    store i32 10, i32* [[I]], align 4
12451 // CHECK21-NEXT:    br label [[DOTOMP_FINAL_DONE]]
12452 // CHECK21:       .omp.final.done:
12453 // CHECK21-NEXT:    ret void
12454 //
12455 //
12456 // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180
12457 // CHECK21-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
12458 // CHECK21-NEXT:  entry:
12459 // CHECK21-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
12460 // CHECK21-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
12461 // CHECK21-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
12462 // CHECK21-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
12463 // CHECK21-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
12464 // CHECK21-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
12465 // CHECK21-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
12466 // CHECK21-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
12467 // CHECK21-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
12468 // CHECK21-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
12469 // CHECK21-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
12470 // CHECK21-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
12471 // CHECK21-NEXT:    [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
12472 // CHECK21-NEXT:    store i32 [[TMP1]], i32* [[CONV2]], align 4
12473 // CHECK21-NEXT:    [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
12474 // CHECK21-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
12475 // CHECK21-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
12476 // CHECK21-NEXT:    store i16 [[TMP3]], i16* [[CONV3]], align 2
12477 // CHECK21-NEXT:    [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
12478 // CHECK21-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]])
12479 // CHECK21-NEXT:    ret void
12480 //
12481 //
12482 // CHECK21-LABEL: define {{[^@]+}}@.omp_outlined..6
12483 // CHECK21-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {
12484 // CHECK21-NEXT:  entry:
12485 // CHECK21-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
12486 // CHECK21-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
12487 // CHECK21-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
12488 // CHECK21-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
12489 // CHECK21-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
12490 // CHECK21-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
12491 // CHECK21-NEXT:    [[TMP:%.*]] = alloca i32, align 4
12492 // CHECK21-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
12493 // CHECK21-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
12494 // CHECK21-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
12495 // CHECK21-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
12496 // CHECK21-NEXT:    [[I:%.*]] = alloca i32, align 4
12497 // CHECK21-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
12498 // CHECK21-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
12499 // CHECK21-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
12500 // CHECK21-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
12501 // CHECK21-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
12502 // CHECK21-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
12503 // CHECK21-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
12504 // CHECK21-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
12505 // CHECK21-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
12506 // CHECK21-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
12507 // CHECK21-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
12508 // CHECK21-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
12509 // CHECK21-NEXT:    [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
12510 // CHECK21-NEXT:    [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
12511 // CHECK21-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
12512 // CHECK21-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
12513 // CHECK21-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9
12514 // CHECK21-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
12515 // CHECK21:       cond.true:
12516 // CHECK21-NEXT:    br label [[COND_END:%.*]]
12517 // CHECK21:       cond.false:
12518 // CHECK21-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
12519 // CHECK21-NEXT:    br label [[COND_END]]
12520 // CHECK21:       cond.end:
12521 // CHECK21-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
12522 // CHECK21-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
12523 // CHECK21-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
12524 // CHECK21-NEXT:    store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
12525 // CHECK21-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
12526 // CHECK21:       omp.inner.for.cond:
12527 // CHECK21-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !35
12528 // CHECK21-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !35
12529 // CHECK21-NEXT:    [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
12530 // CHECK21-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
12531 // CHECK21:       omp.inner.for.body:
12532 // CHECK21-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !35
12533 // CHECK21-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
12534 // CHECK21-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
12535 // CHECK21-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !35
12536 // CHECK21-NEXT:    [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !35
12537 // CHECK21-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1
12538 // CHECK21-NEXT:    store i32 [[ADD3]], i32* [[CONV]], align 4, !llvm.access.group !35
12539 // CHECK21-NEXT:    [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 2, !llvm.access.group !35
12540 // CHECK21-NEXT:    [[CONV4:%.*]] = sext i16 [[TMP10]] to i32
12541 // CHECK21-NEXT:    [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
12542 // CHECK21-NEXT:    [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
12543 // CHECK21-NEXT:    store i16 [[CONV6]], i16* [[CONV1]], align 2, !llvm.access.group !35
12544 // CHECK21-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
12545 // CHECK21-NEXT:    [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !35
12546 // CHECK21-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1
12547 // CHECK21-NEXT:    store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !35
12548 // CHECK21-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
12549 // CHECK21:       omp.body.continue:
12550 // CHECK21-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
12551 // CHECK21:       omp.inner.for.inc:
12552 // CHECK21-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !35
12553 // CHECK21-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP12]], 1
12554 // CHECK21-NEXT:    store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !35
12555 // CHECK21-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP36:![0-9]+]]
12556 // CHECK21:       omp.inner.for.end:
12557 // CHECK21-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
12558 // CHECK21:       omp.loop.exit:
12559 // CHECK21-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
12560 // CHECK21-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
12561 // CHECK21-NEXT:    [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
12562 // CHECK21-NEXT:    br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
12563 // CHECK21:       .omp.final.then:
12564 // CHECK21-NEXT:    store i32 10, i32* [[I]], align 4
12565 // CHECK21-NEXT:    br label [[DOTOMP_FINAL_DONE]]
12566 // CHECK21:       .omp.final.done:
12567 // CHECK21-NEXT:    ret void
12568 //
12569 //
12570 // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97
12571 // CHECK23-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]], i32 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] {
12572 // CHECK23-NEXT:  entry:
12573 // CHECK23-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
12574 // CHECK23-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
12575 // CHECK23-NEXT:    [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4
12576 // CHECK23-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
12577 // CHECK23-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]])
12578 // CHECK23-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
12579 // CHECK23-NEXT:    store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
12580 // CHECK23-NEXT:    store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4
12581 // CHECK23-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
12582 // CHECK23-NEXT:    [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
12583 // CHECK23-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4
12584 // CHECK23-NEXT:    call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
12585 // CHECK23-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
12586 // CHECK23-NEXT:    [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
12587 // CHECK23-NEXT:    store i16 [[TMP3]], i16* [[CONV3]], align 2
12588 // CHECK23-NEXT:    [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
12589 // CHECK23-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]])
12590 // CHECK23-NEXT:    ret void
12591 //
12592 //
12593 // CHECK23-LABEL: define {{[^@]+}}@.omp_outlined.
12594 // CHECK23-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR1:[0-9]+]] {
12595 // CHECK23-NEXT:  entry:
12596 // CHECK23-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
12597 // CHECK23-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
12598 // CHECK23-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
12599 // CHECK23-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
12600 // CHECK23-NEXT:    [[TMP:%.*]] = alloca i32, align 4
12601 // CHECK23-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
12602 // CHECK23-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
12603 // CHECK23-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
12604 // CHECK23-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
12605 // CHECK23-NEXT:    [[I:%.*]] = alloca i32, align 4
12606 // CHECK23-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
12607 // CHECK23-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
12608 // CHECK23-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
12609 // CHECK23-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
12610 // CHECK23-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
12611 // CHECK23-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
12612 // CHECK23-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
12613 // CHECK23-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
12614 // CHECK23-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
12615 // CHECK23-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
12616 // CHECK23-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
12617 // CHECK23-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
12618 // CHECK23-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
12619 // CHECK23-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
12620 // CHECK23:       cond.true:
12621 // CHECK23-NEXT:    br label [[COND_END:%.*]]
12622 // CHECK23:       cond.false:
12623 // CHECK23-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
12624 // CHECK23-NEXT:    br label [[COND_END]]
12625 // CHECK23:       cond.end:
12626 // CHECK23-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
12627 // CHECK23-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
12628 // CHECK23-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
12629 // CHECK23-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
12630 // CHECK23-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
12631 // CHECK23:       omp.inner.for.cond:
12632 // CHECK23-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
12633 // CHECK23-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !12
12634 // CHECK23-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
12635 // CHECK23-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
12636 // CHECK23:       omp.inner.for.body:
12637 // CHECK23-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
12638 // CHECK23-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
12639 // CHECK23-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
12640 // CHECK23-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !12
12641 // CHECK23-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
12642 // CHECK23:       omp.body.continue:
12643 // CHECK23-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
12644 // CHECK23:       omp.inner.for.inc:
12645 // CHECK23-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
12646 // CHECK23-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
12647 // CHECK23-NEXT:    store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
12648 // CHECK23-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]
12649 // CHECK23:       omp.inner.for.end:
12650 // CHECK23-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
12651 // CHECK23:       omp.loop.exit:
12652 // CHECK23-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
12653 // CHECK23-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
12654 // CHECK23-NEXT:    [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0
12655 // CHECK23-NEXT:    br i1 [[TMP10]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
12656 // CHECK23:       .omp.final.then:
12657 // CHECK23-NEXT:    store i32 10, i32* [[I]], align 4
12658 // CHECK23-NEXT:    br label [[DOTOMP_FINAL_DONE]]
12659 // CHECK23:       .omp.final.done:
12660 // CHECK23-NEXT:    ret void
12661 //
12662 //
12663 // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111
12664 // CHECK23-SAME: (i32 noundef [[AA:%.*]]) #[[ATTR0]] {
12665 // CHECK23-NEXT:  entry:
12666 // CHECK23-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
12667 // CHECK23-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
12668 // CHECK23-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
12669 // CHECK23-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
12670 // CHECK23-NEXT:    [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
12671 // CHECK23-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
12672 // CHECK23-NEXT:    store i16 [[TMP0]], i16* [[CONV1]], align 2
12673 // CHECK23-NEXT:    [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
12674 // CHECK23-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]])
12675 // CHECK23-NEXT:    ret void
12676 //
12677 //
12678 // CHECK23-LABEL: define {{[^@]+}}@.omp_outlined..1
12679 // CHECK23-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR1]] {
12680 // CHECK23-NEXT:  entry:
12681 // CHECK23-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
12682 // CHECK23-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
12683 // CHECK23-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
12684 // CHECK23-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
12685 // CHECK23-NEXT:    [[TMP:%.*]] = alloca i32, align 4
12686 // CHECK23-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
12687 // CHECK23-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
12688 // CHECK23-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
12689 // CHECK23-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
12690 // CHECK23-NEXT:    [[I:%.*]] = alloca i32, align 4
12691 // CHECK23-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
12692 // CHECK23-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
12693 // CHECK23-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
12694 // CHECK23-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
12695 // CHECK23-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
12696 // CHECK23-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
12697 // CHECK23-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
12698 // CHECK23-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
12699 // CHECK23-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
12700 // CHECK23-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
12701 // CHECK23-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
12702 // CHECK23-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
12703 // CHECK23-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
12704 // CHECK23-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
12705 // CHECK23:       cond.true:
12706 // CHECK23-NEXT:    br label [[COND_END:%.*]]
12707 // CHECK23:       cond.false:
12708 // CHECK23-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
12709 // CHECK23-NEXT:    br label [[COND_END]]
12710 // CHECK23:       cond.end:
12711 // CHECK23-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
12712 // CHECK23-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
12713 // CHECK23-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
12714 // CHECK23-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
12715 // CHECK23-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
12716 // CHECK23:       omp.inner.for.cond:
12717 // CHECK23-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
12718 // CHECK23-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !19
12719 // CHECK23-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
12720 // CHECK23-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
12721 // CHECK23:       omp.inner.for.body:
12722 // CHECK23-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
12723 // CHECK23-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
12724 // CHECK23-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
12725 // CHECK23-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !19
12726 // CHECK23-NEXT:    [[TMP8:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !19
12727 // CHECK23-NEXT:    [[CONV2:%.*]] = sext i16 [[TMP8]] to i32
12728 // CHECK23-NEXT:    [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
12729 // CHECK23-NEXT:    [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
12730 // CHECK23-NEXT:    store i16 [[CONV4]], i16* [[CONV]], align 2, !llvm.access.group !19
12731 // CHECK23-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
12732 // CHECK23:       omp.body.continue:
12733 // CHECK23-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
12734 // CHECK23:       omp.inner.for.inc:
12735 // CHECK23-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
12736 // CHECK23-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP9]], 1
12737 // CHECK23-NEXT:    store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
12738 // CHECK23-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]]
12739 // CHECK23:       omp.inner.for.end:
12740 // CHECK23-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
12741 // CHECK23:       omp.loop.exit:
12742 // CHECK23-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
12743 // CHECK23-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
12744 // CHECK23-NEXT:    [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0
12745 // CHECK23-NEXT:    br i1 [[TMP11]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
12746 // CHECK23:       .omp.final.then:
12747 // CHECK23-NEXT:    store i32 10, i32* [[I]], align 4
12748 // CHECK23-NEXT:    br label [[DOTOMP_FINAL_DONE]]
12749 // CHECK23:       .omp.final.done:
12750 // CHECK23-NEXT:    ret void
12751 //
12752 //
12753 // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118
12754 // CHECK23-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] {
12755 // CHECK23-NEXT:  entry:
12756 // CHECK23-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
12757 // CHECK23-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
12758 // CHECK23-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
12759 // CHECK23-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
12760 // CHECK23-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
12761 // CHECK23-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
12762 // CHECK23-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
12763 // CHECK23-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
12764 // CHECK23-NEXT:    store i32 [[TMP0]], i32* [[A_CASTED]], align 4
12765 // CHECK23-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
12766 // CHECK23-NEXT:    [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
12767 // CHECK23-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
12768 // CHECK23-NEXT:    store i16 [[TMP2]], i16* [[CONV1]], align 2
12769 // CHECK23-NEXT:    [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
12770 // CHECK23-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]])
12771 // CHECK23-NEXT:    ret void
12772 //
12773 //
12774 // CHECK23-LABEL: define {{[^@]+}}@.omp_outlined..2
12775 // CHECK23-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR1]] {
12776 // CHECK23-NEXT:  entry:
12777 // CHECK23-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
12778 // CHECK23-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
12779 // CHECK23-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
12780 // CHECK23-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
12781 // CHECK23-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
12782 // CHECK23-NEXT:    [[TMP:%.*]] = alloca i32, align 4
12783 // CHECK23-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
12784 // CHECK23-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
12785 // CHECK23-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
12786 // CHECK23-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
12787 // CHECK23-NEXT:    [[I:%.*]] = alloca i32, align 4
12788 // CHECK23-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
12789 // CHECK23-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
12790 // CHECK23-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
12791 // CHECK23-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
12792 // CHECK23-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
12793 // CHECK23-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
12794 // CHECK23-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
12795 // CHECK23-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
12796 // CHECK23-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
12797 // CHECK23-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
12798 // CHECK23-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
12799 // CHECK23-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
12800 // CHECK23-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
12801 // CHECK23-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
12802 // CHECK23-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
12803 // CHECK23:       cond.true:
12804 // CHECK23-NEXT:    br label [[COND_END:%.*]]
12805 // CHECK23:       cond.false:
12806 // CHECK23-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
12807 // CHECK23-NEXT:    br label [[COND_END]]
12808 // CHECK23:       cond.end:
12809 // CHECK23-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
12810 // CHECK23-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
12811 // CHECK23-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
12812 // CHECK23-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
12813 // CHECK23-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
12814 // CHECK23:       omp.inner.for.cond:
12815 // CHECK23-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
12816 // CHECK23-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !22
12817 // CHECK23-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
12818 // CHECK23-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
12819 // CHECK23:       omp.inner.for.body:
12820 // CHECK23-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
12821 // CHECK23-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
12822 // CHECK23-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
12823 // CHECK23-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !22
12824 // CHECK23-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !22
12825 // CHECK23-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
12826 // CHECK23-NEXT:    store i32 [[ADD2]], i32* [[A_ADDR]], align 4, !llvm.access.group !22
12827 // CHECK23-NEXT:    [[TMP9:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !22
12828 // CHECK23-NEXT:    [[CONV3:%.*]] = sext i16 [[TMP9]] to i32
12829 // CHECK23-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
12830 // CHECK23-NEXT:    [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
12831 // CHECK23-NEXT:    store i16 [[CONV5]], i16* [[CONV]], align 2, !llvm.access.group !22
12832 // CHECK23-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
12833 // CHECK23:       omp.body.continue:
12834 // CHECK23-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
12835 // CHECK23:       omp.inner.for.inc:
12836 // CHECK23-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
12837 // CHECK23-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP10]], 1
12838 // CHECK23-NEXT:    store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
12839 // CHECK23-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]]
12840 // CHECK23:       omp.inner.for.end:
12841 // CHECK23-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
12842 // CHECK23:       omp.loop.exit:
12843 // CHECK23-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
12844 // CHECK23-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
12845 // CHECK23-NEXT:    [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
12846 // CHECK23-NEXT:    br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
12847 // CHECK23:       .omp.final.then:
12848 // CHECK23-NEXT:    store i32 10, i32* [[I]], align 4
12849 // CHECK23-NEXT:    br label [[DOTOMP_FINAL_DONE]]
12850 // CHECK23:       .omp.final.done:
12851 // CHECK23-NEXT:    ret void
12852 //
12853 //
12854 // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142
12855 // CHECK23-SAME: (i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] {
12856 // CHECK23-NEXT:  entry:
12857 // CHECK23-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
12858 // CHECK23-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
12859 // CHECK23-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
12860 // CHECK23-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 4
12861 // CHECK23-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
12862 // CHECK23-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
12863 // CHECK23-NEXT:    [[VLA_ADDR4:%.*]] = alloca i32, align 4
12864 // CHECK23-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 4
12865 // CHECK23-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
12866 // CHECK23-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
12867 // CHECK23-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
12868 // CHECK23-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
12869 // CHECK23-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
12870 // CHECK23-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 4
12871 // CHECK23-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
12872 // CHECK23-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
12873 // CHECK23-NEXT:    store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
12874 // CHECK23-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 4
12875 // CHECK23-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
12876 // CHECK23-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
12877 // CHECK23-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
12878 // CHECK23-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
12879 // CHECK23-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
12880 // CHECK23-NEXT:    [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
12881 // CHECK23-NEXT:    [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
12882 // CHECK23-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
12883 // CHECK23-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
12884 // CHECK23-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
12885 // CHECK23-NEXT:    store i32 [[TMP8]], i32* [[A_CASTED]], align 4
12886 // CHECK23-NEXT:    [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4
12887 // CHECK23-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]])
12888 // CHECK23-NEXT:    ret void
12889 //
12890 //
12891 // CHECK23-LABEL: define {{[^@]+}}@.omp_outlined..3
12892 // CHECK23-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR1]] {
12893 // CHECK23-NEXT:  entry:
12894 // CHECK23-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
12895 // CHECK23-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
12896 // CHECK23-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
12897 // CHECK23-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
12898 // CHECK23-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
12899 // CHECK23-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 4
12900 // CHECK23-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
12901 // CHECK23-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
12902 // CHECK23-NEXT:    [[VLA_ADDR4:%.*]] = alloca i32, align 4
12903 // CHECK23-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 4
12904 // CHECK23-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
12905 // CHECK23-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
12906 // CHECK23-NEXT:    [[TMP:%.*]] = alloca i32, align 4
12907 // CHECK23-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
12908 // CHECK23-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
12909 // CHECK23-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
12910 // CHECK23-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
12911 // CHECK23-NEXT:    [[I:%.*]] = alloca i32, align 4
12912 // CHECK23-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
12913 // CHECK23-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
12914 // CHECK23-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
12915 // CHECK23-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
12916 // CHECK23-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
12917 // CHECK23-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 4
12918 // CHECK23-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
12919 // CHECK23-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
12920 // CHECK23-NEXT:    store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
12921 // CHECK23-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 4
12922 // CHECK23-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
12923 // CHECK23-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
12924 // CHECK23-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
12925 // CHECK23-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
12926 // CHECK23-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
12927 // CHECK23-NEXT:    [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
12928 // CHECK23-NEXT:    [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
12929 // CHECK23-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
12930 // CHECK23-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
12931 // CHECK23-NEXT:    [[ARRAYDECAY:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 0
12932 // CHECK23-NEXT:    call void @llvm.assume(i1 true) [ "align"(float* [[ARRAYDECAY]], i32 16) ]
12933 // CHECK23-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
12934 // CHECK23-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
12935 // CHECK23-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
12936 // CHECK23-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
12937 // CHECK23-NEXT:    [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
12938 // CHECK23-NEXT:    [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4
12939 // CHECK23-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
12940 // CHECK23-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
12941 // CHECK23-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP10]], 9
12942 // CHECK23-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
12943 // CHECK23:       cond.true:
12944 // CHECK23-NEXT:    br label [[COND_END:%.*]]
12945 // CHECK23:       cond.false:
12946 // CHECK23-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
12947 // CHECK23-NEXT:    br label [[COND_END]]
12948 // CHECK23:       cond.end:
12949 // CHECK23-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ]
12950 // CHECK23-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
12951 // CHECK23-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
12952 // CHECK23-NEXT:    store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4
12953 // CHECK23-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
12954 // CHECK23:       omp.inner.for.cond:
12955 // CHECK23-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25
12956 // CHECK23-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !25
12957 // CHECK23-NEXT:    [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
12958 // CHECK23-NEXT:    br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
12959 // CHECK23:       omp.inner.for.body:
12960 // CHECK23-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25
12961 // CHECK23-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1
12962 // CHECK23-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
12963 // CHECK23-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !25
12964 // CHECK23-NEXT:    [[TMP16:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !25
12965 // CHECK23-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP16]], 1
12966 // CHECK23-NEXT:    store i32 [[ADD6]], i32* [[A_ADDR]], align 4, !llvm.access.group !25
12967 // CHECK23-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2
12968 // CHECK23-NEXT:    [[TMP17:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !25
12969 // CHECK23-NEXT:    [[CONV:%.*]] = fpext float [[TMP17]] to double
12970 // CHECK23-NEXT:    [[ADD7:%.*]] = fadd double [[CONV]], 1.000000e+00
12971 // CHECK23-NEXT:    [[CONV8:%.*]] = fptrunc double [[ADD7]] to float
12972 // CHECK23-NEXT:    store float [[CONV8]], float* [[ARRAYIDX]], align 4, !llvm.access.group !25
12973 // CHECK23-NEXT:    [[ARRAYIDX9:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3
12974 // CHECK23-NEXT:    [[TMP18:%.*]] = load float, float* [[ARRAYIDX9]], align 4, !llvm.access.group !25
12975 // CHECK23-NEXT:    [[CONV10:%.*]] = fpext float [[TMP18]] to double
12976 // CHECK23-NEXT:    [[ADD11:%.*]] = fadd double [[CONV10]], 1.000000e+00
12977 // CHECK23-NEXT:    [[CONV12:%.*]] = fptrunc double [[ADD11]] to float
12978 // CHECK23-NEXT:    store float [[CONV12]], float* [[ARRAYIDX9]], align 4, !llvm.access.group !25
12979 // CHECK23-NEXT:    [[ARRAYIDX13:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1
12980 // CHECK23-NEXT:    [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX13]], i32 0, i32 2
12981 // CHECK23-NEXT:    [[TMP19:%.*]] = load double, double* [[ARRAYIDX14]], align 8, !llvm.access.group !25
12982 // CHECK23-NEXT:    [[ADD15:%.*]] = fadd double [[TMP19]], 1.000000e+00
12983 // CHECK23-NEXT:    store double [[ADD15]], double* [[ARRAYIDX14]], align 8, !llvm.access.group !25
12984 // CHECK23-NEXT:    [[TMP20:%.*]] = mul nsw i32 1, [[TMP5]]
12985 // CHECK23-NEXT:    [[ARRAYIDX16:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP20]]
12986 // CHECK23-NEXT:    [[ARRAYIDX17:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX16]], i32 3
12987 // CHECK23-NEXT:    [[TMP21:%.*]] = load double, double* [[ARRAYIDX17]], align 8, !llvm.access.group !25
12988 // CHECK23-NEXT:    [[ADD18:%.*]] = fadd double [[TMP21]], 1.000000e+00
12989 // CHECK23-NEXT:    store double [[ADD18]], double* [[ARRAYIDX17]], align 8, !llvm.access.group !25
12990 // CHECK23-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0
12991 // CHECK23-NEXT:    [[TMP22:%.*]] = load i64, i64* [[X]], align 4, !llvm.access.group !25
12992 // CHECK23-NEXT:    [[ADD19:%.*]] = add nsw i64 [[TMP22]], 1
12993 // CHECK23-NEXT:    store i64 [[ADD19]], i64* [[X]], align 4, !llvm.access.group !25
12994 // CHECK23-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1
12995 // CHECK23-NEXT:    [[TMP23:%.*]] = load i8, i8* [[Y]], align 4, !llvm.access.group !25
12996 // CHECK23-NEXT:    [[CONV20:%.*]] = sext i8 [[TMP23]] to i32
12997 // CHECK23-NEXT:    [[ADD21:%.*]] = add nsw i32 [[CONV20]], 1
12998 // CHECK23-NEXT:    [[CONV22:%.*]] = trunc i32 [[ADD21]] to i8
12999 // CHECK23-NEXT:    store i8 [[CONV22]], i8* [[Y]], align 4, !llvm.access.group !25
13000 // CHECK23-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
13001 // CHECK23:       omp.body.continue:
13002 // CHECK23-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
13003 // CHECK23:       omp.inner.for.inc:
13004 // CHECK23-NEXT:    [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25
13005 // CHECK23-NEXT:    [[ADD23:%.*]] = add nsw i32 [[TMP24]], 1
13006 // CHECK23-NEXT:    store i32 [[ADD23]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25
13007 // CHECK23-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP26:![0-9]+]]
13008 // CHECK23:       omp.inner.for.end:
13009 // CHECK23-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
13010 // CHECK23:       omp.loop.exit:
13011 // CHECK23-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]])
13012 // CHECK23-NEXT:    [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
13013 // CHECK23-NEXT:    [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
13014 // CHECK23-NEXT:    br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
13015 // CHECK23:       .omp.final.then:
13016 // CHECK23-NEXT:    store i32 10, i32* [[I]], align 4
13017 // CHECK23-NEXT:    br label [[DOTOMP_FINAL_DONE]]
13018 // CHECK23:       .omp.final.done:
13019 // CHECK23-NEXT:    ret void
13020 //
13021 //
13022 // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197
13023 // CHECK23-SAME: (i32 noundef [[A:%.*]], i32 noundef [[N:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
13024 // CHECK23-NEXT:  entry:
13025 // CHECK23-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
13026 // CHECK23-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
13027 // CHECK23-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
13028 // CHECK23-NEXT:    [[AAA_ADDR:%.*]] = alloca i32, align 4
13029 // CHECK23-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
13030 // CHECK23-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
13031 // CHECK23-NEXT:    [[N_CASTED:%.*]] = alloca i32, align 4
13032 // CHECK23-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
13033 // CHECK23-NEXT:    [[AAA_CASTED:%.*]] = alloca i32, align 4
13034 // CHECK23-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
13035 // CHECK23-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
13036 // CHECK23-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
13037 // CHECK23-NEXT:    store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
13038 // CHECK23-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
13039 // CHECK23-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
13040 // CHECK23-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
13041 // CHECK23-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
13042 // CHECK23-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
13043 // CHECK23-NEXT:    store i32 [[TMP1]], i32* [[A_CASTED]], align 4
13044 // CHECK23-NEXT:    [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
13045 // CHECK23-NEXT:    [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
13046 // CHECK23-NEXT:    store i32 [[TMP3]], i32* [[N_CASTED]], align 4
13047 // CHECK23-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_CASTED]], align 4
13048 // CHECK23-NEXT:    [[TMP5:%.*]] = load i16, i16* [[CONV]], align 2
13049 // CHECK23-NEXT:    [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
13050 // CHECK23-NEXT:    store i16 [[TMP5]], i16* [[CONV2]], align 2
13051 // CHECK23-NEXT:    [[TMP6:%.*]] = load i32, i32* [[AA_CASTED]], align 4
13052 // CHECK23-NEXT:    [[TMP7:%.*]] = load i8, i8* [[CONV1]], align 1
13053 // CHECK23-NEXT:    [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
13054 // CHECK23-NEXT:    store i8 [[TMP7]], i8* [[CONV3]], align 1
13055 // CHECK23-NEXT:    [[TMP8:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
13056 // CHECK23-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP8]], [10 x i32]* [[TMP0]])
13057 // CHECK23-NEXT:    ret void
13058 //
13059 //
13060 // CHECK23-LABEL: define {{[^@]+}}@.omp_outlined..4
13061 // CHECK23-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[N:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {
13062 // CHECK23-NEXT:  entry:
13063 // CHECK23-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
13064 // CHECK23-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
13065 // CHECK23-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
13066 // CHECK23-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
13067 // CHECK23-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
13068 // CHECK23-NEXT:    [[AAA_ADDR:%.*]] = alloca i32, align 4
13069 // CHECK23-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
13070 // CHECK23-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
13071 // CHECK23-NEXT:    [[TMP:%.*]] = alloca i32, align 4
13072 // CHECK23-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
13073 // CHECK23-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
13074 // CHECK23-NEXT:    [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4
13075 // CHECK23-NEXT:    [[I:%.*]] = alloca i32, align 4
13076 // CHECK23-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
13077 // CHECK23-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
13078 // CHECK23-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
13079 // CHECK23-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
13080 // CHECK23-NEXT:    [[I6:%.*]] = alloca i32, align 4
13081 // CHECK23-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
13082 // CHECK23-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
13083 // CHECK23-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
13084 // CHECK23-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
13085 // CHECK23-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
13086 // CHECK23-NEXT:    store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
13087 // CHECK23-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
13088 // CHECK23-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
13089 // CHECK23-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
13090 // CHECK23-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
13091 // CHECK23-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
13092 // CHECK23-NEXT:    store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
13093 // CHECK23-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
13094 // CHECK23-NEXT:    store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4
13095 // CHECK23-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
13096 // CHECK23-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
13097 // CHECK23-NEXT:    [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]]
13098 // CHECK23-NEXT:    [[SUB4:%.*]] = sub i32 [[SUB]], 1
13099 // CHECK23-NEXT:    [[ADD:%.*]] = add i32 [[SUB4]], 1
13100 // CHECK23-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], 1
13101 // CHECK23-NEXT:    [[SUB5:%.*]] = sub i32 [[DIV]], 1
13102 // CHECK23-NEXT:    store i32 [[SUB5]], i32* [[DOTCAPTURE_EXPR_3]], align 4
13103 // CHECK23-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
13104 // CHECK23-NEXT:    store i32 [[TMP5]], i32* [[I]], align 4
13105 // CHECK23-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
13106 // CHECK23-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
13107 // CHECK23-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]]
13108 // CHECK23-NEXT:    br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
13109 // CHECK23:       omp.precond.then:
13110 // CHECK23-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
13111 // CHECK23-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
13112 // CHECK23-NEXT:    store i32 [[TMP8]], i32* [[DOTOMP_UB]], align 4
13113 // CHECK23-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
13114 // CHECK23-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
13115 // CHECK23-NEXT:    [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
13116 // CHECK23-NEXT:    [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
13117 // CHECK23-NEXT:    call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
13118 // CHECK23-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
13119 // CHECK23-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
13120 // CHECK23-NEXT:    [[CMP7:%.*]] = icmp ugt i32 [[TMP11]], [[TMP12]]
13121 // CHECK23-NEXT:    br i1 [[CMP7]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
13122 // CHECK23:       cond.true:
13123 // CHECK23-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
13124 // CHECK23-NEXT:    br label [[COND_END:%.*]]
13125 // CHECK23:       cond.false:
13126 // CHECK23-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
13127 // CHECK23-NEXT:    br label [[COND_END]]
13128 // CHECK23:       cond.end:
13129 // CHECK23-NEXT:    [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ]
13130 // CHECK23-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
13131 // CHECK23-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
13132 // CHECK23-NEXT:    store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4
13133 // CHECK23-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
13134 // CHECK23:       omp.inner.for.cond:
13135 // CHECK23-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28
13136 // CHECK23-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !28
13137 // CHECK23-NEXT:    [[ADD8:%.*]] = add i32 [[TMP17]], 1
13138 // CHECK23-NEXT:    [[CMP9:%.*]] = icmp ult i32 [[TMP16]], [[ADD8]]
13139 // CHECK23-NEXT:    br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
13140 // CHECK23:       omp.inner.for.body:
13141 // CHECK23-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group !28
13142 // CHECK23-NEXT:    [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28
13143 // CHECK23-NEXT:    [[MUL:%.*]] = mul i32 [[TMP19]], 1
13144 // CHECK23-NEXT:    [[ADD10:%.*]] = add i32 [[TMP18]], [[MUL]]
13145 // CHECK23-NEXT:    store i32 [[ADD10]], i32* [[I6]], align 4, !llvm.access.group !28
13146 // CHECK23-NEXT:    [[TMP20:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !28
13147 // CHECK23-NEXT:    [[ADD11:%.*]] = add nsw i32 [[TMP20]], 1
13148 // CHECK23-NEXT:    store i32 [[ADD11]], i32* [[A_ADDR]], align 4, !llvm.access.group !28
13149 // CHECK23-NEXT:    [[TMP21:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !28
13150 // CHECK23-NEXT:    [[CONV12:%.*]] = sext i16 [[TMP21]] to i32
13151 // CHECK23-NEXT:    [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1
13152 // CHECK23-NEXT:    [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16
13153 // CHECK23-NEXT:    store i16 [[CONV14]], i16* [[CONV]], align 2, !llvm.access.group !28
13154 // CHECK23-NEXT:    [[TMP22:%.*]] = load i8, i8* [[CONV1]], align 1, !llvm.access.group !28
13155 // CHECK23-NEXT:    [[CONV15:%.*]] = sext i8 [[TMP22]] to i32
13156 // CHECK23-NEXT:    [[ADD16:%.*]] = add nsw i32 [[CONV15]], 1
13157 // CHECK23-NEXT:    [[CONV17:%.*]] = trunc i32 [[ADD16]] to i8
13158 // CHECK23-NEXT:    store i8 [[CONV17]], i8* [[CONV1]], align 1, !llvm.access.group !28
13159 // CHECK23-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
13160 // CHECK23-NEXT:    [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !28
13161 // CHECK23-NEXT:    [[ADD18:%.*]] = add nsw i32 [[TMP23]], 1
13162 // CHECK23-NEXT:    store i32 [[ADD18]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !28
13163 // CHECK23-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
13164 // CHECK23:       omp.body.continue:
13165 // CHECK23-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
13166 // CHECK23:       omp.inner.for.inc:
13167 // CHECK23-NEXT:    [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28
13168 // CHECK23-NEXT:    [[ADD19:%.*]] = add i32 [[TMP24]], 1
13169 // CHECK23-NEXT:    store i32 [[ADD19]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28
13170 // CHECK23-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP29:![0-9]+]]
13171 // CHECK23:       omp.inner.for.end:
13172 // CHECK23-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
13173 // CHECK23:       omp.loop.exit:
13174 // CHECK23-NEXT:    [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
13175 // CHECK23-NEXT:    [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4
13176 // CHECK23-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]])
13177 // CHECK23-NEXT:    [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
13178 // CHECK23-NEXT:    [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0
13179 // CHECK23-NEXT:    br i1 [[TMP28]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
13180 // CHECK23:       .omp.final.then:
13181 // CHECK23-NEXT:    [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
13182 // CHECK23-NEXT:    [[TMP30:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
13183 // CHECK23-NEXT:    [[TMP31:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
13184 // CHECK23-NEXT:    [[SUB20:%.*]] = sub i32 [[TMP30]], [[TMP31]]
13185 // CHECK23-NEXT:    [[SUB21:%.*]] = sub i32 [[SUB20]], 1
13186 // CHECK23-NEXT:    [[ADD22:%.*]] = add i32 [[SUB21]], 1
13187 // CHECK23-NEXT:    [[DIV23:%.*]] = udiv i32 [[ADD22]], 1
13188 // CHECK23-NEXT:    [[MUL24:%.*]] = mul i32 [[DIV23]], 1
13189 // CHECK23-NEXT:    [[ADD25:%.*]] = add i32 [[TMP29]], [[MUL24]]
13190 // CHECK23-NEXT:    store i32 [[ADD25]], i32* [[I6]], align 4
13191 // CHECK23-NEXT:    br label [[DOTOMP_FINAL_DONE]]
13192 // CHECK23:       .omp.final.done:
13193 // CHECK23-NEXT:    br label [[OMP_PRECOND_END]]
13194 // CHECK23:       omp.precond.end:
13195 // CHECK23-NEXT:    ret void
13196 //
13197 //
13198 // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215
13199 // CHECK23-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
13200 // CHECK23-NEXT:  entry:
13201 // CHECK23-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
13202 // CHECK23-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
13203 // CHECK23-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
13204 // CHECK23-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
13205 // CHECK23-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 4
13206 // CHECK23-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
13207 // CHECK23-NEXT:    [[B_CASTED:%.*]] = alloca i32, align 4
13208 // CHECK23-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
13209 // CHECK23-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
13210 // CHECK23-NEXT:    store i32 [[B]], i32* [[B_ADDR]], align 4
13211 // CHECK23-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
13212 // CHECK23-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
13213 // CHECK23-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 4
13214 // CHECK23-NEXT:    store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
13215 // CHECK23-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
13216 // CHECK23-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
13217 // CHECK23-NEXT:    [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
13218 // CHECK23-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
13219 // CHECK23-NEXT:    [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8*
13220 // CHECK23-NEXT:    [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4
13221 // CHECK23-NEXT:    store i32 [[TMP4]], i32* [[B_CASTED]], align 4
13222 // CHECK23-NEXT:    [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4
13223 // CHECK23-NEXT:    [[TMP6:%.*]] = load i8, i8* [[CONV]], align 1
13224 // CHECK23-NEXT:    [[TOBOOL:%.*]] = trunc i8 [[TMP6]] to i1
13225 // CHECK23-NEXT:    [[CONV3:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__CASTED]] to i8*
13226 // CHECK23-NEXT:    [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
13227 // CHECK23-NEXT:    store i8 [[FROMBOOL]], i8* [[CONV3]], align 1
13228 // CHECK23-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
13229 // CHECK23-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]], i32 [[TMP7]])
13230 // CHECK23-NEXT:    ret void
13231 //
13232 //
13233 // CHECK23-LABEL: define {{[^@]+}}@.omp_outlined..5
13234 // CHECK23-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
13235 // CHECK23-NEXT:  entry:
13236 // CHECK23-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
13237 // CHECK23-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
13238 // CHECK23-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
13239 // CHECK23-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
13240 // CHECK23-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
13241 // CHECK23-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
13242 // CHECK23-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 4
13243 // CHECK23-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
13244 // CHECK23-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
13245 // CHECK23-NEXT:    [[TMP:%.*]] = alloca i32, align 4
13246 // CHECK23-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
13247 // CHECK23-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
13248 // CHECK23-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
13249 // CHECK23-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
13250 // CHECK23-NEXT:    [[I:%.*]] = alloca i32, align 4
13251 // CHECK23-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
13252 // CHECK23-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
13253 // CHECK23-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
13254 // CHECK23-NEXT:    store i32 [[B]], i32* [[B_ADDR]], align 4
13255 // CHECK23-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
13256 // CHECK23-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
13257 // CHECK23-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 4
13258 // CHECK23-NEXT:    store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
13259 // CHECK23-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
13260 // CHECK23-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
13261 // CHECK23-NEXT:    [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
13262 // CHECK23-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
13263 // CHECK23-NEXT:    [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8*
13264 // CHECK23-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
13265 // CHECK23-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
13266 // CHECK23-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
13267 // CHECK23-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
13268 // CHECK23-NEXT:    [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
13269 // CHECK23-NEXT:    [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
13270 // CHECK23-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
13271 // CHECK23-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
13272 // CHECK23-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 9
13273 // CHECK23-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
13274 // CHECK23:       cond.true:
13275 // CHECK23-NEXT:    br label [[COND_END:%.*]]
13276 // CHECK23:       cond.false:
13277 // CHECK23-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
13278 // CHECK23-NEXT:    br label [[COND_END]]
13279 // CHECK23:       cond.end:
13280 // CHECK23-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
13281 // CHECK23-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
13282 // CHECK23-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
13283 // CHECK23-NEXT:    store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
13284 // CHECK23-NEXT:    [[TMP9:%.*]] = load i8, i8* [[CONV]], align 1
13285 // CHECK23-NEXT:    [[TOBOOL:%.*]] = trunc i8 [[TMP9]] to i1
13286 // CHECK23-NEXT:    br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
13287 // CHECK23:       omp_if.then:
13288 // CHECK23-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
13289 // CHECK23:       omp.inner.for.cond:
13290 // CHECK23-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !31
13291 // CHECK23-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !31
13292 // CHECK23-NEXT:    [[CMP3:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]
13293 // CHECK23-NEXT:    br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
13294 // CHECK23:       omp.inner.for.body:
13295 // CHECK23-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !31
13296 // CHECK23-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1
13297 // CHECK23-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
13298 // CHECK23-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !31
13299 // CHECK23-NEXT:    [[TMP13:%.*]] = load i32, i32* [[B_ADDR]], align 4, !llvm.access.group !31
13300 // CHECK23-NEXT:    [[CONV4:%.*]] = sitofp i32 [[TMP13]] to double
13301 // CHECK23-NEXT:    [[ADD5:%.*]] = fadd double [[CONV4]], 1.500000e+00
13302 // CHECK23-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
13303 // CHECK23-NEXT:    store double [[ADD5]], double* [[A]], align 4, !llvm.access.group !31
13304 // CHECK23-NEXT:    [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
13305 // CHECK23-NEXT:    [[TMP14:%.*]] = load double, double* [[A6]], align 4, !llvm.access.group !31
13306 // CHECK23-NEXT:    [[INC:%.*]] = fadd double [[TMP14]], 1.000000e+00
13307 // CHECK23-NEXT:    store double [[INC]], double* [[A6]], align 4, !llvm.access.group !31
13308 // CHECK23-NEXT:    [[CONV7:%.*]] = fptosi double [[INC]] to i16
13309 // CHECK23-NEXT:    [[TMP15:%.*]] = mul nsw i32 1, [[TMP2]]
13310 // CHECK23-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP15]]
13311 // CHECK23-NEXT:    [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
13312 // CHECK23-NEXT:    store i16 [[CONV7]], i16* [[ARRAYIDX8]], align 2, !llvm.access.group !31
13313 // CHECK23-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
13314 // CHECK23:       omp.body.continue:
13315 // CHECK23-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
13316 // CHECK23:       omp.inner.for.inc:
13317 // CHECK23-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !31
13318 // CHECK23-NEXT:    [[ADD9:%.*]] = add nsw i32 [[TMP16]], 1
13319 // CHECK23-NEXT:    store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !31
13320 // CHECK23-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP32:![0-9]+]]
13321 // CHECK23:       omp.inner.for.end:
13322 // CHECK23-NEXT:    br label [[OMP_IF_END:%.*]]
13323 // CHECK23:       omp_if.else:
13324 // CHECK23-NEXT:    br label [[OMP_INNER_FOR_COND10:%.*]]
13325 // CHECK23:       omp.inner.for.cond10:
13326 // CHECK23-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
13327 // CHECK23-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
13328 // CHECK23-NEXT:    [[CMP11:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]]
13329 // CHECK23-NEXT:    br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY12:%.*]], label [[OMP_INNER_FOR_END26:%.*]]
13330 // CHECK23:       omp.inner.for.body12:
13331 // CHECK23-NEXT:    [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
13332 // CHECK23-NEXT:    [[MUL13:%.*]] = mul nsw i32 [[TMP19]], 1
13333 // CHECK23-NEXT:    [[ADD14:%.*]] = add nsw i32 0, [[MUL13]]
13334 // CHECK23-NEXT:    store i32 [[ADD14]], i32* [[I]], align 4
13335 // CHECK23-NEXT:    [[TMP20:%.*]] = load i32, i32* [[B_ADDR]], align 4
13336 // CHECK23-NEXT:    [[CONV15:%.*]] = sitofp i32 [[TMP20]] to double
13337 // CHECK23-NEXT:    [[ADD16:%.*]] = fadd double [[CONV15]], 1.500000e+00
13338 // CHECK23-NEXT:    [[A17:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
13339 // CHECK23-NEXT:    store double [[ADD16]], double* [[A17]], align 4
13340 // CHECK23-NEXT:    [[A18:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
13341 // CHECK23-NEXT:    [[TMP21:%.*]] = load double, double* [[A18]], align 4
13342 // CHECK23-NEXT:    [[INC19:%.*]] = fadd double [[TMP21]], 1.000000e+00
13343 // CHECK23-NEXT:    store double [[INC19]], double* [[A18]], align 4
13344 // CHECK23-NEXT:    [[CONV20:%.*]] = fptosi double [[INC19]] to i16
13345 // CHECK23-NEXT:    [[TMP22:%.*]] = mul nsw i32 1, [[TMP2]]
13346 // CHECK23-NEXT:    [[ARRAYIDX21:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP22]]
13347 // CHECK23-NEXT:    [[ARRAYIDX22:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX21]], i32 1
13348 // CHECK23-NEXT:    store i16 [[CONV20]], i16* [[ARRAYIDX22]], align 2
13349 // CHECK23-NEXT:    br label [[OMP_BODY_CONTINUE23:%.*]]
13350 // CHECK23:       omp.body.continue23:
13351 // CHECK23-NEXT:    br label [[OMP_INNER_FOR_INC24:%.*]]
13352 // CHECK23:       omp.inner.for.inc24:
13353 // CHECK23-NEXT:    [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
13354 // CHECK23-NEXT:    [[ADD25:%.*]] = add nsw i32 [[TMP23]], 1
13355 // CHECK23-NEXT:    store i32 [[ADD25]], i32* [[DOTOMP_IV]], align 4
13356 // CHECK23-NEXT:    br label [[OMP_INNER_FOR_COND10]], !llvm.loop [[LOOP34:![0-9]+]]
13357 // CHECK23:       omp.inner.for.end26:
13358 // CHECK23-NEXT:    br label [[OMP_IF_END]]
13359 // CHECK23:       omp_if.end:
13360 // CHECK23-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
13361 // CHECK23:       omp.loop.exit:
13362 // CHECK23-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
13363 // CHECK23-NEXT:    [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
13364 // CHECK23-NEXT:    [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0
13365 // CHECK23-NEXT:    br i1 [[TMP25]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
13366 // CHECK23:       .omp.final.then:
13367 // CHECK23-NEXT:    store i32 10, i32* [[I]], align 4
13368 // CHECK23-NEXT:    br label [[DOTOMP_FINAL_DONE]]
13369 // CHECK23:       .omp.final.done:
13370 // CHECK23-NEXT:    ret void
13371 //
13372 //
13373 // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180
13374 // CHECK23-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
13375 // CHECK23-NEXT:  entry:
13376 // CHECK23-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
13377 // CHECK23-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
13378 // CHECK23-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
13379 // CHECK23-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
13380 // CHECK23-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
13381 // CHECK23-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
13382 // CHECK23-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
13383 // CHECK23-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
13384 // CHECK23-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
13385 // CHECK23-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
13386 // CHECK23-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
13387 // CHECK23-NEXT:    store i32 [[TMP1]], i32* [[A_CASTED]], align 4
13388 // CHECK23-NEXT:    [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
13389 // CHECK23-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
13390 // CHECK23-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
13391 // CHECK23-NEXT:    store i16 [[TMP3]], i16* [[CONV1]], align 2
13392 // CHECK23-NEXT:    [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
13393 // CHECK23-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]])
13394 // CHECK23-NEXT:    ret void
13395 //
13396 //
13397 // CHECK23-LABEL: define {{[^@]+}}@.omp_outlined..6
13398 // CHECK23-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {
13399 // CHECK23-NEXT:  entry:
13400 // CHECK23-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
13401 // CHECK23-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
13402 // CHECK23-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
13403 // CHECK23-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
13404 // CHECK23-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
13405 // CHECK23-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
13406 // CHECK23-NEXT:    [[TMP:%.*]] = alloca i32, align 4
13407 // CHECK23-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
13408 // CHECK23-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
13409 // CHECK23-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
13410 // CHECK23-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
13411 // CHECK23-NEXT:    [[I:%.*]] = alloca i32, align 4
13412 // CHECK23-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
13413 // CHECK23-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
13414 // CHECK23-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
13415 // CHECK23-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
13416 // CHECK23-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
13417 // CHECK23-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
13418 // CHECK23-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
13419 // CHECK23-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
13420 // CHECK23-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
13421 // CHECK23-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
13422 // CHECK23-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
13423 // CHECK23-NEXT:    [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
13424 // CHECK23-NEXT:    [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
13425 // CHECK23-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
13426 // CHECK23-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
13427 // CHECK23-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9
13428 // CHECK23-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
13429 // CHECK23:       cond.true:
13430 // CHECK23-NEXT:    br label [[COND_END:%.*]]
13431 // CHECK23:       cond.false:
13432 // CHECK23-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
13433 // CHECK23-NEXT:    br label [[COND_END]]
13434 // CHECK23:       cond.end:
13435 // CHECK23-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
13436 // CHECK23-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
13437 // CHECK23-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
13438 // CHECK23-NEXT:    store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
13439 // CHECK23-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
13440 // CHECK23:       omp.inner.for.cond:
13441 // CHECK23-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36
13442 // CHECK23-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !36
13443 // CHECK23-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
13444 // CHECK23-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
13445 // CHECK23:       omp.inner.for.body:
13446 // CHECK23-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36
13447 // CHECK23-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
13448 // CHECK23-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
13449 // CHECK23-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !36
13450 // CHECK23-NEXT:    [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !36
13451 // CHECK23-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
13452 // CHECK23-NEXT:    store i32 [[ADD2]], i32* [[A_ADDR]], align 4, !llvm.access.group !36
13453 // CHECK23-NEXT:    [[TMP10:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !36
13454 // CHECK23-NEXT:    [[CONV3:%.*]] = sext i16 [[TMP10]] to i32
13455 // CHECK23-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
13456 // CHECK23-NEXT:    [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
13457 // CHECK23-NEXT:    store i16 [[CONV5]], i16* [[CONV]], align 2, !llvm.access.group !36
13458 // CHECK23-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
13459 // CHECK23-NEXT:    [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !36
13460 // CHECK23-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1
13461 // CHECK23-NEXT:    store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !36
13462 // CHECK23-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
13463 // CHECK23:       omp.body.continue:
13464 // CHECK23-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
13465 // CHECK23:       omp.inner.for.inc:
13466 // CHECK23-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36
13467 // CHECK23-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP12]], 1
13468 // CHECK23-NEXT:    store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36
13469 // CHECK23-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP37:![0-9]+]]
13470 // CHECK23:       omp.inner.for.end:
13471 // CHECK23-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
13472 // CHECK23:       omp.loop.exit:
13473 // CHECK23-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
13474 // CHECK23-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
13475 // CHECK23-NEXT:    [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
13476 // CHECK23-NEXT:    br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
13477 // CHECK23:       .omp.final.then:
13478 // CHECK23-NEXT:    store i32 10, i32* [[I]], align 4
13479 // CHECK23-NEXT:    br label [[DOTOMP_FINAL_DONE]]
13480 // CHECK23:       .omp.final.done:
13481 // CHECK23-NEXT:    ret void
13482 //
13483