1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ 2 // Test host codegen. 3 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 4 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 5 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1 6 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 7 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 8 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK3 9 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=50 -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 10 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=50 -DOMP5 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 11 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=50 -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK5 12 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=50 -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 13 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=50 -DOMP5 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 14 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=50 -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK7 15 16 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 17 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 18 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK9 19 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11 20 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 21 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK11 22 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -fopenmp-version=50 -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK13 23 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=50 -DOMP5 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 24 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=50 -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK13 25 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -fopenmp-version=50 -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK15 26 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=50 -DOMP5 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 27 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=50 -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK15 28 29 // Test target codegen - host bc file has to be created first. 30 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc 31 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK17 32 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s 33 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK17 34 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc 35 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK19 36 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s 37 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK19 38 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=50 -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc 39 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=50 -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK21 40 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=50 -DOMP5 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s 41 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=50 -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK21 42 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=50 -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc 43 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=50 -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK23 44 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=50 -DOMP5 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s 45 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=50 -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK23 46 47 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc 48 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK9 49 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s 50 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK9 51 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc 52 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK11 53 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s 54 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK11 55 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -fopenmp-version=50 -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc 56 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -fopenmp-version=50 -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK13 57 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=50 -DOMP5 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s 58 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=50 -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK13 59 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -fopenmp-version=50 -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc 60 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -fopenmp-version=50 -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK15 61 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=50 -DOMP5 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s 62 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=50 -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK15 63 // expected-no-diagnostics 64 65 #ifndef HEADER 66 #define HEADER 67 68 69 70 71 // We have 8 target regions, but only 7 that actually will generate offloading 72 // code, only 6 will have mapped arguments, and only 4 have all-constant map 73 // sizes. 74 75 76 77 // Check target registration is registered as a Ctor. 78 79 80 template<typename tx, typename ty> 81 struct TT{ 82 tx X; 83 ty Y; 84 }; 85 86 int global; 87 88 int foo(int n) { 89 int a = 0; 90 short aa = 0; 91 float b[10]; 92 float bn[n]; 93 double c[5][10]; 94 double cn[5][n]; 95 TT<long long, char> d; 96 97 #pragma omp target teams distribute simd num_teams(a) thread_limit(a) firstprivate(aa) simdlen(16) nowait 98 for (int i = 0; i < 10; ++i) { 99 } 100 101 #ifdef OMP5 102 #pragma omp target teams distribute simd if(target: 0) safelen(32) linear(a) if(simd: 1) nontemporal(a) 103 #else 104 #pragma omp target teams distribute simd if(target: 0) safelen(32) linear(a) 105 #endif // OMP5 106 for (a = 0; a < 10; ++a) { 107 a += 1; 108 } 109 110 111 #pragma omp target teams distribute simd if(target: 1) 112 for (int i = 0; i < 10; ++i) { 113 aa += 1; 114 } 115 116 117 118 #pragma omp target teams distribute simd if(target: n>10) 119 for (int i = 0; i < 10; ++i) { 120 a += 1; 121 aa += 1; 122 } 123 124 // We capture 3 VLA sizes in this target region 125 126 127 128 129 130 // The names below are not necessarily consistent with the names used for the 131 // addresses above as some are repeated. 132 133 134 135 136 137 138 139 140 141 142 #pragma omp target teams distribute simd if(target: n>20) aligned(b) 143 for (int i = 0; i < 10; ++i) { 144 a += 1; 145 b[2] += 1.0; 146 bn[3] += 1.0; 147 c[1][2] += 1.0; 148 cn[1][3] += 1.0; 149 d.X += 1; 150 d.Y += 1; 151 } 152 153 return a; 154 } 155 156 // Check that the offloading functions are emitted and that the arguments are 157 // correct and loaded correctly for the target regions in foo(). 158 159 160 161 162 // Create stack storage and store argument in there. 163 164 // Create stack storage and store argument in there. 165 166 // Create stack storage and store argument in there. 167 168 // Create local storage for each capture. 169 170 171 172 // To reduce complexity, we're only going as far as validating the signature of the outlined parallel function. 173 174 template<typename tx> 175 tx ftemplate(int n) { 176 tx a = 0; 177 short aa = 0; 178 tx b[10]; 179 180 #pragma omp target teams distribute simd if(target: n>40) 181 for (int i = 0; i < 10; ++i) { 182 a += 1; 183 aa += 1; 184 b[2] += 1; 185 } 186 187 return a; 188 } 189 190 static 191 int fstatic(int n) { 192 int a = 0; 193 short aa = 0; 194 char aaa = 0; 195 int b[10]; 196 197 #pragma omp target teams distribute simd if(target: n>50) 198 for (int i = a; i < n; ++i) { 199 a += 1; 200 aa += 1; 201 aaa += 1; 202 b[2] += 1; 203 } 204 205 return a; 206 } 207 208 struct S1 { 209 double a; 210 211 int r1(int n){ 212 int b = n+1; 213 short int c[2][n]; 214 215 #pragma omp target teams distribute simd if(n>60) 216 for (int i = 0; i < 10; ++i) { 217 this->a = (double)b + 1.5; 218 c[1][1] = ++a; 219 } 220 221 return c[1][1] + (int)b; 222 } 223 }; 224 225 int bar(int n){ 226 int a = 0; 227 228 a += foo(n); 229 230 S1 S; 231 a += S.r1(n); 232 233 a += fstatic(n); 234 235 a += ftemplate<int>(n); 236 237 return a; 238 } 239 240 241 242 // We capture 2 VLA sizes in this target region 243 244 245 // The names below are not necessarily consistent with the names used for the 246 // addresses above as some are repeated. 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 // Check that the offloading functions are emitted and that the arguments are 270 // correct and loaded correctly for the target regions of the callees of bar(). 271 272 // Create local storage for each capture. 273 // Store captures in the context. 274 275 276 // To reduce complexity, we're only going as far as validating the signature of the outlined parallel function. 277 278 279 // Create local storage for each capture. 280 // Store captures in the context. 281 282 283 284 285 // To reduce complexity, we're only going as far as validating the signature of the outlined parallel function. 286 287 // Create local storage for each capture. 288 // Store captures in the context. 289 290 291 292 // To reduce complexity, we're only going as far as validating the signature of the outlined parallel function. 293 294 295 #endif 296 // CHECK1-LABEL: define {{[^@]+}}@_Z3fooi 297 // CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { 298 // CHECK1-NEXT: entry: 299 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 300 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4 301 // CHECK1-NEXT: [[AA:%.*]] = alloca i16, align 2 302 // CHECK1-NEXT: [[B:%.*]] = alloca [10 x float], align 4 303 // CHECK1-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 304 // CHECK1-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 305 // CHECK1-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 306 // CHECK1-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 307 // CHECK1-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 308 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 309 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 310 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 311 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 312 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED4:%.*]] = alloca i64, align 8 313 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 314 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 315 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 316 // CHECK1-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4 317 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 318 // CHECK1-NEXT: [[AA_CASTED7:%.*]] = alloca i64, align 8 319 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS9:%.*]] = alloca [1 x i8*], align 8 320 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS10:%.*]] = alloca [1 x i8*], align 8 321 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS11:%.*]] = alloca [1 x i8*], align 8 322 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 323 // CHECK1-NEXT: [[A_CASTED12:%.*]] = alloca i64, align 8 324 // CHECK1-NEXT: [[AA_CASTED14:%.*]] = alloca i64, align 8 325 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS16:%.*]] = alloca [2 x i8*], align 8 326 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS17:%.*]] = alloca [2 x i8*], align 8 327 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS18:%.*]] = alloca [2 x i8*], align 8 328 // CHECK1-NEXT: [[_TMP19:%.*]] = alloca i32, align 4 329 // CHECK1-NEXT: [[A_CASTED22:%.*]] = alloca i64, align 8 330 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS26:%.*]] = alloca [9 x i8*], align 8 331 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS27:%.*]] = alloca [9 x i8*], align 8 332 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS28:%.*]] = alloca [9 x i8*], align 8 333 // CHECK1-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [9 x i64], align 8 334 // CHECK1-NEXT: [[_TMP29:%.*]] = alloca i32, align 4 335 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) 336 // CHECK1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 337 // CHECK1-NEXT: store i32 0, i32* [[A]], align 4 338 // CHECK1-NEXT: store i16 0, i16* [[AA]], align 2 339 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 340 // CHECK1-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 341 // CHECK1-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() 342 // CHECK1-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 343 // CHECK1-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP2]], align 4 344 // CHECK1-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 345 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 346 // CHECK1-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64 347 // CHECK1-NEXT: [[TMP6:%.*]] = mul nuw i64 5, [[TMP5]] 348 // CHECK1-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP6]], align 8 349 // CHECK1-NEXT: store i64 [[TMP5]], i64* [[__VLA_EXPR1]], align 8 350 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 351 // CHECK1-NEXT: store i32 [[TMP7]], i32* [[DOTCAPTURE_EXPR_]], align 4 352 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 353 // CHECK1-NEXT: store i32 [[TMP8]], i32* [[DOTCAPTURE_EXPR_2]], align 4 354 // CHECK1-NEXT: [[TMP9:%.*]] = load i16, i16* [[AA]], align 2 355 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 356 // CHECK1-NEXT: store i16 [[TMP9]], i16* [[CONV]], align 2 357 // CHECK1-NEXT: [[TMP10:%.*]] = load i64, i64* [[AA_CASTED]], align 8 358 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 359 // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* 360 // CHECK1-NEXT: store i32 [[TMP11]], i32* [[CONV3]], align 4 361 // CHECK1-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 362 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 363 // CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED4]] to i32* 364 // CHECK1-NEXT: store i32 [[TMP13]], i32* [[CONV5]], align 4 365 // CHECK1-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED4]], align 8 366 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 367 // CHECK1-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i64* 368 // CHECK1-NEXT: store i64 [[TMP10]], i64* [[TMP16]], align 8 369 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 370 // CHECK1-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64* 371 // CHECK1-NEXT: store i64 [[TMP10]], i64* [[TMP18]], align 8 372 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 373 // CHECK1-NEXT: store i8* null, i8** [[TMP19]], align 8 374 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 375 // CHECK1-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i64* 376 // CHECK1-NEXT: store i64 [[TMP12]], i64* [[TMP21]], align 8 377 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 378 // CHECK1-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i64* 379 // CHECK1-NEXT: store i64 [[TMP12]], i64* [[TMP23]], align 8 380 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 381 // CHECK1-NEXT: store i8* null, i8** [[TMP24]], align 8 382 // CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 383 // CHECK1-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i64* 384 // CHECK1-NEXT: store i64 [[TMP14]], i64* [[TMP26]], align 8 385 // CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 386 // CHECK1-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i64* 387 // CHECK1-NEXT: store i64 [[TMP14]], i64* [[TMP28]], align 8 388 // CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 389 // CHECK1-NEXT: store i8* null, i8** [[TMP29]], align 8 390 // CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 391 // CHECK1-NEXT: [[TMP31:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 392 // CHECK1-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 0 393 // CHECK1-NEXT: [[TMP33:%.*]] = load i16, i16* [[AA]], align 2 394 // CHECK1-NEXT: store i16 [[TMP33]], i16* [[TMP32]], align 4 395 // CHECK1-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 1 396 // CHECK1-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 397 // CHECK1-NEXT: store i32 [[TMP35]], i32* [[TMP34]], align 4 398 // CHECK1-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 2 399 // CHECK1-NEXT: [[TMP37:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 400 // CHECK1-NEXT: store i32 [[TMP37]], i32* [[TMP36]], align 4 401 // CHECK1-NEXT: [[TMP38:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 1, i64 120, i64 12, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1) 402 // CHECK1-NEXT: [[TMP39:%.*]] = bitcast i8* [[TMP38]] to %struct.kmp_task_t_with_privates* 403 // CHECK1-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP39]], i32 0, i32 0 404 // CHECK1-NEXT: [[TMP41:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP40]], i32 0, i32 0 405 // CHECK1-NEXT: [[TMP42:%.*]] = load i8*, i8** [[TMP41]], align 8 406 // CHECK1-NEXT: [[TMP43:%.*]] = bitcast %struct.anon* [[AGG_CAPTURED]] to i8* 407 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP42]], i8* align 4 [[TMP43]], i64 12, i1 false) 408 // CHECK1-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP39]], i32 0, i32 1 409 // CHECK1-NEXT: [[TMP45:%.*]] = bitcast i8* [[TMP42]] to %struct.anon* 410 // CHECK1-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 0 411 // CHECK1-NEXT: [[TMP47:%.*]] = bitcast [3 x i8*]* [[TMP46]] to i8* 412 // CHECK1-NEXT: [[TMP48:%.*]] = bitcast i8** [[TMP30]] to i8* 413 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP47]], i8* align 8 [[TMP48]], i64 24, i1 false) 414 // CHECK1-NEXT: [[TMP49:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 1 415 // CHECK1-NEXT: [[TMP50:%.*]] = bitcast [3 x i8*]* [[TMP49]] to i8* 416 // CHECK1-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP31]] to i8* 417 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP50]], i8* align 8 [[TMP51]], i64 24, i1 false) 418 // CHECK1-NEXT: [[TMP52:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 2 419 // CHECK1-NEXT: [[TMP53:%.*]] = bitcast [3 x i64]* [[TMP52]] to i8* 420 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP53]], i8* align 8 bitcast ([3 x i64]* @.offload_sizes to i8*), i64 24, i1 false) 421 // CHECK1-NEXT: [[TMP54:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 3 422 // CHECK1-NEXT: [[TMP55:%.*]] = load i16, i16* [[AA]], align 2 423 // CHECK1-NEXT: store i16 [[TMP55]], i16* [[TMP54]], align 8 424 // CHECK1-NEXT: [[TMP56:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i8* [[TMP38]]) 425 // CHECK1-NEXT: [[TMP57:%.*]] = load i32, i32* [[A]], align 4 426 // CHECK1-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32* 427 // CHECK1-NEXT: store i32 [[TMP57]], i32* [[CONV6]], align 4 428 // CHECK1-NEXT: [[TMP58:%.*]] = load i64, i64* [[A_CASTED]], align 8 429 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104(i64 [[TMP58]]) #[[ATTR4:[0-9]+]] 430 // CHECK1-NEXT: [[TMP59:%.*]] = load i16, i16* [[AA]], align 2 431 // CHECK1-NEXT: [[CONV8:%.*]] = bitcast i64* [[AA_CASTED7]] to i16* 432 // CHECK1-NEXT: store i16 [[TMP59]], i16* [[CONV8]], align 2 433 // CHECK1-NEXT: [[TMP60:%.*]] = load i64, i64* [[AA_CASTED7]], align 8 434 // CHECK1-NEXT: [[TMP61:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS9]], i32 0, i32 0 435 // CHECK1-NEXT: [[TMP62:%.*]] = bitcast i8** [[TMP61]] to i64* 436 // CHECK1-NEXT: store i64 [[TMP60]], i64* [[TMP62]], align 8 437 // CHECK1-NEXT: [[TMP63:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS10]], i32 0, i32 0 438 // CHECK1-NEXT: [[TMP64:%.*]] = bitcast i8** [[TMP63]] to i64* 439 // CHECK1-NEXT: store i64 [[TMP60]], i64* [[TMP64]], align 8 440 // CHECK1-NEXT: [[TMP65:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS11]], i64 0, i64 0 441 // CHECK1-NEXT: store i8* null, i8** [[TMP65]], align 8 442 // CHECK1-NEXT: [[TMP66:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS9]], i32 0, i32 0 443 // CHECK1-NEXT: [[TMP67:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS10]], i32 0, i32 0 444 // CHECK1-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) 445 // CHECK1-NEXT: [[TMP68:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.region_id, i32 1, i8** [[TMP66]], i8** [[TMP67]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.4, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.5, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1) 446 // CHECK1-NEXT: [[TMP69:%.*]] = icmp ne i32 [[TMP68]], 0 447 // CHECK1-NEXT: br i1 [[TMP69]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 448 // CHECK1: omp_offload.failed: 449 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111(i64 [[TMP60]]) #[[ATTR4]] 450 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 451 // CHECK1: omp_offload.cont: 452 // CHECK1-NEXT: [[TMP70:%.*]] = load i32, i32* [[A]], align 4 453 // CHECK1-NEXT: [[CONV13:%.*]] = bitcast i64* [[A_CASTED12]] to i32* 454 // CHECK1-NEXT: store i32 [[TMP70]], i32* [[CONV13]], align 4 455 // CHECK1-NEXT: [[TMP71:%.*]] = load i64, i64* [[A_CASTED12]], align 8 456 // CHECK1-NEXT: [[TMP72:%.*]] = load i16, i16* [[AA]], align 2 457 // CHECK1-NEXT: [[CONV15:%.*]] = bitcast i64* [[AA_CASTED14]] to i16* 458 // CHECK1-NEXT: store i16 [[TMP72]], i16* [[CONV15]], align 2 459 // CHECK1-NEXT: [[TMP73:%.*]] = load i64, i64* [[AA_CASTED14]], align 8 460 // CHECK1-NEXT: [[TMP74:%.*]] = load i32, i32* [[N_ADDR]], align 4 461 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP74]], 10 462 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 463 // CHECK1: omp_if.then: 464 // CHECK1-NEXT: [[TMP75:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 0 465 // CHECK1-NEXT: [[TMP76:%.*]] = bitcast i8** [[TMP75]] to i64* 466 // CHECK1-NEXT: store i64 [[TMP71]], i64* [[TMP76]], align 8 467 // CHECK1-NEXT: [[TMP77:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 0 468 // CHECK1-NEXT: [[TMP78:%.*]] = bitcast i8** [[TMP77]] to i64* 469 // CHECK1-NEXT: store i64 [[TMP71]], i64* [[TMP78]], align 8 470 // CHECK1-NEXT: [[TMP79:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 0 471 // CHECK1-NEXT: store i8* null, i8** [[TMP79]], align 8 472 // CHECK1-NEXT: [[TMP80:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 1 473 // CHECK1-NEXT: [[TMP81:%.*]] = bitcast i8** [[TMP80]] to i64* 474 // CHECK1-NEXT: store i64 [[TMP73]], i64* [[TMP81]], align 8 475 // CHECK1-NEXT: [[TMP82:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 1 476 // CHECK1-NEXT: [[TMP83:%.*]] = bitcast i8** [[TMP82]] to i64* 477 // CHECK1-NEXT: store i64 [[TMP73]], i64* [[TMP83]], align 8 478 // CHECK1-NEXT: [[TMP84:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 1 479 // CHECK1-NEXT: store i8* null, i8** [[TMP84]], align 8 480 // CHECK1-NEXT: [[TMP85:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 0 481 // CHECK1-NEXT: [[TMP86:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 0 482 // CHECK1-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) 483 // CHECK1-NEXT: [[TMP87:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.region_id, i32 2, i8** [[TMP85]], i8** [[TMP86]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.7, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.8, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1) 484 // CHECK1-NEXT: [[TMP88:%.*]] = icmp ne i32 [[TMP87]], 0 485 // CHECK1-NEXT: br i1 [[TMP88]], label [[OMP_OFFLOAD_FAILED20:%.*]], label [[OMP_OFFLOAD_CONT21:%.*]] 486 // CHECK1: omp_offload.failed20: 487 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i64 [[TMP71]], i64 [[TMP73]]) #[[ATTR4]] 488 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT21]] 489 // CHECK1: omp_offload.cont21: 490 // CHECK1-NEXT: br label [[OMP_IF_END:%.*]] 491 // CHECK1: omp_if.else: 492 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i64 [[TMP71]], i64 [[TMP73]]) #[[ATTR4]] 493 // CHECK1-NEXT: br label [[OMP_IF_END]] 494 // CHECK1: omp_if.end: 495 // CHECK1-NEXT: [[TMP89:%.*]] = load i32, i32* [[A]], align 4 496 // CHECK1-NEXT: [[CONV23:%.*]] = bitcast i64* [[A_CASTED22]] to i32* 497 // CHECK1-NEXT: store i32 [[TMP89]], i32* [[CONV23]], align 4 498 // CHECK1-NEXT: [[TMP90:%.*]] = load i64, i64* [[A_CASTED22]], align 8 499 // CHECK1-NEXT: [[TMP91:%.*]] = load i32, i32* [[N_ADDR]], align 4 500 // CHECK1-NEXT: [[CMP24:%.*]] = icmp sgt i32 [[TMP91]], 20 501 // CHECK1-NEXT: br i1 [[CMP24]], label [[OMP_IF_THEN25:%.*]], label [[OMP_IF_ELSE32:%.*]] 502 // CHECK1: omp_if.then25: 503 // CHECK1-NEXT: [[TMP92:%.*]] = mul nuw i64 [[TMP2]], 4 504 // CHECK1-NEXT: [[TMP93:%.*]] = mul nuw i64 5, [[TMP5]] 505 // CHECK1-NEXT: [[TMP94:%.*]] = mul nuw i64 [[TMP93]], 8 506 // CHECK1-NEXT: [[TMP95:%.*]] = bitcast [9 x i64]* [[DOTOFFLOAD_SIZES]] to i8* 507 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP95]], i8* align 8 bitcast ([9 x i64]* @.offload_sizes.10 to i8*), i64 72, i1 false) 508 // CHECK1-NEXT: [[TMP96:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS26]], i32 0, i32 0 509 // CHECK1-NEXT: [[TMP97:%.*]] = bitcast i8** [[TMP96]] to i64* 510 // CHECK1-NEXT: store i64 [[TMP90]], i64* [[TMP97]], align 8 511 // CHECK1-NEXT: [[TMP98:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS27]], i32 0, i32 0 512 // CHECK1-NEXT: [[TMP99:%.*]] = bitcast i8** [[TMP98]] to i64* 513 // CHECK1-NEXT: store i64 [[TMP90]], i64* [[TMP99]], align 8 514 // CHECK1-NEXT: [[TMP100:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS28]], i64 0, i64 0 515 // CHECK1-NEXT: store i8* null, i8** [[TMP100]], align 8 516 // CHECK1-NEXT: [[TMP101:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS26]], i32 0, i32 1 517 // CHECK1-NEXT: [[TMP102:%.*]] = bitcast i8** [[TMP101]] to [10 x float]** 518 // CHECK1-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP102]], align 8 519 // CHECK1-NEXT: [[TMP103:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS27]], i32 0, i32 1 520 // CHECK1-NEXT: [[TMP104:%.*]] = bitcast i8** [[TMP103]] to [10 x float]** 521 // CHECK1-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP104]], align 8 522 // CHECK1-NEXT: [[TMP105:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS28]], i64 0, i64 1 523 // CHECK1-NEXT: store i8* null, i8** [[TMP105]], align 8 524 // CHECK1-NEXT: [[TMP106:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS26]], i32 0, i32 2 525 // CHECK1-NEXT: [[TMP107:%.*]] = bitcast i8** [[TMP106]] to i64* 526 // CHECK1-NEXT: store i64 [[TMP2]], i64* [[TMP107]], align 8 527 // CHECK1-NEXT: [[TMP108:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS27]], i32 0, i32 2 528 // CHECK1-NEXT: [[TMP109:%.*]] = bitcast i8** [[TMP108]] to i64* 529 // CHECK1-NEXT: store i64 [[TMP2]], i64* [[TMP109]], align 8 530 // CHECK1-NEXT: [[TMP110:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS28]], i64 0, i64 2 531 // CHECK1-NEXT: store i8* null, i8** [[TMP110]], align 8 532 // CHECK1-NEXT: [[TMP111:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS26]], i32 0, i32 3 533 // CHECK1-NEXT: [[TMP112:%.*]] = bitcast i8** [[TMP111]] to float** 534 // CHECK1-NEXT: store float* [[VLA]], float** [[TMP112]], align 8 535 // CHECK1-NEXT: [[TMP113:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS27]], i32 0, i32 3 536 // CHECK1-NEXT: [[TMP114:%.*]] = bitcast i8** [[TMP113]] to float** 537 // CHECK1-NEXT: store float* [[VLA]], float** [[TMP114]], align 8 538 // CHECK1-NEXT: [[TMP115:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 539 // CHECK1-NEXT: store i64 [[TMP92]], i64* [[TMP115]], align 8 540 // CHECK1-NEXT: [[TMP116:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS28]], i64 0, i64 3 541 // CHECK1-NEXT: store i8* null, i8** [[TMP116]], align 8 542 // CHECK1-NEXT: [[TMP117:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS26]], i32 0, i32 4 543 // CHECK1-NEXT: [[TMP118:%.*]] = bitcast i8** [[TMP117]] to [5 x [10 x double]]** 544 // CHECK1-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP118]], align 8 545 // CHECK1-NEXT: [[TMP119:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS27]], i32 0, i32 4 546 // CHECK1-NEXT: [[TMP120:%.*]] = bitcast i8** [[TMP119]] to [5 x [10 x double]]** 547 // CHECK1-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP120]], align 8 548 // CHECK1-NEXT: [[TMP121:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS28]], i64 0, i64 4 549 // CHECK1-NEXT: store i8* null, i8** [[TMP121]], align 8 550 // CHECK1-NEXT: [[TMP122:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS26]], i32 0, i32 5 551 // CHECK1-NEXT: [[TMP123:%.*]] = bitcast i8** [[TMP122]] to i64* 552 // CHECK1-NEXT: store i64 5, i64* [[TMP123]], align 8 553 // CHECK1-NEXT: [[TMP124:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS27]], i32 0, i32 5 554 // CHECK1-NEXT: [[TMP125:%.*]] = bitcast i8** [[TMP124]] to i64* 555 // CHECK1-NEXT: store i64 5, i64* [[TMP125]], align 8 556 // CHECK1-NEXT: [[TMP126:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS28]], i64 0, i64 5 557 // CHECK1-NEXT: store i8* null, i8** [[TMP126]], align 8 558 // CHECK1-NEXT: [[TMP127:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS26]], i32 0, i32 6 559 // CHECK1-NEXT: [[TMP128:%.*]] = bitcast i8** [[TMP127]] to i64* 560 // CHECK1-NEXT: store i64 [[TMP5]], i64* [[TMP128]], align 8 561 // CHECK1-NEXT: [[TMP129:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS27]], i32 0, i32 6 562 // CHECK1-NEXT: [[TMP130:%.*]] = bitcast i8** [[TMP129]] to i64* 563 // CHECK1-NEXT: store i64 [[TMP5]], i64* [[TMP130]], align 8 564 // CHECK1-NEXT: [[TMP131:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS28]], i64 0, i64 6 565 // CHECK1-NEXT: store i8* null, i8** [[TMP131]], align 8 566 // CHECK1-NEXT: [[TMP132:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS26]], i32 0, i32 7 567 // CHECK1-NEXT: [[TMP133:%.*]] = bitcast i8** [[TMP132]] to double** 568 // CHECK1-NEXT: store double* [[VLA1]], double** [[TMP133]], align 8 569 // CHECK1-NEXT: [[TMP134:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS27]], i32 0, i32 7 570 // CHECK1-NEXT: [[TMP135:%.*]] = bitcast i8** [[TMP134]] to double** 571 // CHECK1-NEXT: store double* [[VLA1]], double** [[TMP135]], align 8 572 // CHECK1-NEXT: [[TMP136:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 573 // CHECK1-NEXT: store i64 [[TMP94]], i64* [[TMP136]], align 8 574 // CHECK1-NEXT: [[TMP137:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS28]], i64 0, i64 7 575 // CHECK1-NEXT: store i8* null, i8** [[TMP137]], align 8 576 // CHECK1-NEXT: [[TMP138:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS26]], i32 0, i32 8 577 // CHECK1-NEXT: [[TMP139:%.*]] = bitcast i8** [[TMP138]] to %struct.TT** 578 // CHECK1-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP139]], align 8 579 // CHECK1-NEXT: [[TMP140:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS27]], i32 0, i32 8 580 // CHECK1-NEXT: [[TMP141:%.*]] = bitcast i8** [[TMP140]] to %struct.TT** 581 // CHECK1-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP141]], align 8 582 // CHECK1-NEXT: [[TMP142:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS28]], i64 0, i64 8 583 // CHECK1-NEXT: store i8* null, i8** [[TMP142]], align 8 584 // CHECK1-NEXT: [[TMP143:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS26]], i32 0, i32 0 585 // CHECK1-NEXT: [[TMP144:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS27]], i32 0, i32 0 586 // CHECK1-NEXT: [[TMP145:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 587 // CHECK1-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) 588 // CHECK1-NEXT: [[TMP146:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142.region_id, i32 9, i8** [[TMP143]], i8** [[TMP144]], i64* [[TMP145]], i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_maptypes.11, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1) 589 // CHECK1-NEXT: [[TMP147:%.*]] = icmp ne i32 [[TMP146]], 0 590 // CHECK1-NEXT: br i1 [[TMP147]], label [[OMP_OFFLOAD_FAILED30:%.*]], label [[OMP_OFFLOAD_CONT31:%.*]] 591 // CHECK1: omp_offload.failed30: 592 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i64 [[TMP90]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR4]] 593 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT31]] 594 // CHECK1: omp_offload.cont31: 595 // CHECK1-NEXT: br label [[OMP_IF_END33:%.*]] 596 // CHECK1: omp_if.else32: 597 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i64 [[TMP90]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR4]] 598 // CHECK1-NEXT: br label [[OMP_IF_END33]] 599 // CHECK1: omp_if.end33: 600 // CHECK1-NEXT: [[TMP148:%.*]] = load i32, i32* [[A]], align 4 601 // CHECK1-NEXT: [[TMP149:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 602 // CHECK1-NEXT: call void @llvm.stackrestore(i8* [[TMP149]]) 603 // CHECK1-NEXT: ret i32 [[TMP148]] 604 // 605 // 606 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97 607 // CHECK1-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] { 608 // CHECK1-NEXT: entry: 609 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 610 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 611 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8 612 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 613 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]]) 614 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 615 // CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 616 // CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8 617 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 618 // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* 619 // CHECK1-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32* 620 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 4 621 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 4 622 // CHECK1-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) 623 // CHECK1-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 624 // CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 625 // CHECK1-NEXT: store i16 [[TMP3]], i16* [[CONV5]], align 2 626 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 627 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]]) 628 // CHECK1-NEXT: ret void 629 // 630 // 631 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. 632 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR3:[0-9]+]] { 633 // CHECK1-NEXT: entry: 634 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 635 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 636 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 637 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 638 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 639 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 640 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 641 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 642 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 643 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 644 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 645 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 646 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 647 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 648 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 649 // CHECK1-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 650 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 651 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 652 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 653 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 654 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 655 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 656 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 657 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 658 // CHECK1: cond.true: 659 // CHECK1-NEXT: br label [[COND_END:%.*]] 660 // CHECK1: cond.false: 661 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 662 // CHECK1-NEXT: br label [[COND_END]] 663 // CHECK1: cond.end: 664 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 665 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 666 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 667 // CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 668 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 669 // CHECK1: omp.inner.for.cond: 670 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 671 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !10 672 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 673 // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 674 // CHECK1: omp.inner.for.body: 675 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 676 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 677 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 678 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10 679 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 680 // CHECK1: omp.body.continue: 681 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 682 // CHECK1: omp.inner.for.inc: 683 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 684 // CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 685 // CHECK1-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 686 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] 687 // CHECK1: omp.inner.for.end: 688 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 689 // CHECK1: omp.loop.exit: 690 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 691 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 692 // CHECK1-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 693 // CHECK1-NEXT: br i1 [[TMP10]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 694 // CHECK1: .omp.final.then: 695 // CHECK1-NEXT: store i32 10, i32* [[I]], align 4 696 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] 697 // CHECK1: .omp.final.done: 698 // CHECK1-NEXT: ret void 699 // 700 // 701 // CHECK1-LABEL: define {{[^@]+}}@.omp_task_privates_map. 702 // CHECK1-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], i16** noalias noundef [[TMP1:%.*]], [3 x i8*]** noalias noundef [[TMP2:%.*]], [3 x i8*]** noalias noundef [[TMP3:%.*]], [3 x i64]** noalias noundef [[TMP4:%.*]]) #[[ATTR5:[0-9]+]] { 703 // CHECK1-NEXT: entry: 704 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 8 705 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i16**, align 8 706 // CHECK1-NEXT: [[DOTADDR2:%.*]] = alloca [3 x i8*]**, align 8 707 // CHECK1-NEXT: [[DOTADDR3:%.*]] = alloca [3 x i8*]**, align 8 708 // CHECK1-NEXT: [[DOTADDR4:%.*]] = alloca [3 x i64]**, align 8 709 // CHECK1-NEXT: store %struct..kmp_privates.t* [[TMP0]], %struct..kmp_privates.t** [[DOTADDR]], align 8 710 // CHECK1-NEXT: store i16** [[TMP1]], i16*** [[DOTADDR1]], align 8 711 // CHECK1-NEXT: store [3 x i8*]** [[TMP2]], [3 x i8*]*** [[DOTADDR2]], align 8 712 // CHECK1-NEXT: store [3 x i8*]** [[TMP3]], [3 x i8*]*** [[DOTADDR3]], align 8 713 // CHECK1-NEXT: store [3 x i64]** [[TMP4]], [3 x i64]*** [[DOTADDR4]], align 8 714 // CHECK1-NEXT: [[TMP5:%.*]] = load %struct..kmp_privates.t*, %struct..kmp_privates.t** [[DOTADDR]], align 8 715 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 0 716 // CHECK1-NEXT: [[TMP7:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR2]], align 8 717 // CHECK1-NEXT: store [3 x i8*]* [[TMP6]], [3 x i8*]** [[TMP7]], align 8 718 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 1 719 // CHECK1-NEXT: [[TMP9:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR3]], align 8 720 // CHECK1-NEXT: store [3 x i8*]* [[TMP8]], [3 x i8*]** [[TMP9]], align 8 721 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 2 722 // CHECK1-NEXT: [[TMP11:%.*]] = load [3 x i64]**, [3 x i64]*** [[DOTADDR4]], align 8 723 // CHECK1-NEXT: store [3 x i64]* [[TMP10]], [3 x i64]** [[TMP11]], align 8 724 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 3 725 // CHECK1-NEXT: [[TMP13:%.*]] = load i16**, i16*** [[DOTADDR1]], align 8 726 // CHECK1-NEXT: store i16* [[TMP12]], i16** [[TMP13]], align 8 727 // CHECK1-NEXT: ret void 728 // 729 // 730 // CHECK1-LABEL: define {{[^@]+}}@.omp_task_entry. 731 // CHECK1-SAME: (i32 noundef signext [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] { 732 // CHECK1-NEXT: entry: 733 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 734 // CHECK1-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 735 // CHECK1-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8 736 // CHECK1-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8 737 // CHECK1-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8 738 // CHECK1-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 8 739 // CHECK1-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca i16*, align 8 740 // CHECK1-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca [3 x i8*]*, align 8 741 // CHECK1-NEXT: [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca [3 x i8*]*, align 8 742 // CHECK1-NEXT: [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca [3 x i64]*, align 8 743 // CHECK1-NEXT: [[AA_CASTED_I:%.*]] = alloca i64, align 8 744 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED_I:%.*]] = alloca i64, align 8 745 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED5_I:%.*]] = alloca i64, align 8 746 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 747 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8 748 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 749 // CHECK1-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 750 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 751 // CHECK1-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 752 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0 753 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 754 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 755 // CHECK1-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 756 // CHECK1-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon* 757 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1 758 // CHECK1-NEXT: [[TMP10:%.*]] = bitcast %struct..kmp_privates.t* [[TMP9]] to i8* 759 // CHECK1-NEXT: [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8* 760 // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META17:![0-9]+]]) 761 // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]]) 762 // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META22:![0-9]+]]) 763 // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META24:![0-9]+]]) 764 // CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !26 765 // CHECK1-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !26 766 // CHECK1-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !26 767 // CHECK1-NEXT: store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* @.omp_task_privates_map. to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !26 768 // CHECK1-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !26 769 // CHECK1-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !26 770 // CHECK1-NEXT: [[TMP12:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !26 771 // CHECK1-NEXT: [[TMP13:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !26 772 // CHECK1-NEXT: [[TMP14:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !26 773 // CHECK1-NEXT: [[TMP15:%.*]] = bitcast void (i8*, ...)* [[TMP13]] to void (i8*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* 774 // CHECK1-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR4]] 775 // CHECK1-NEXT: [[TMP16:%.*]] = load i16*, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !26 776 // CHECK1-NEXT: [[TMP17:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !26 777 // CHECK1-NEXT: [[TMP18:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 8, !noalias !26 778 // CHECK1-NEXT: [[TMP19:%.*]] = load [3 x i64]*, [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 8, !noalias !26 779 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP17]], i64 0, i64 0 780 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP18]], i64 0, i64 0 781 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[TMP19]], i64 0, i64 0 782 // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP12]], i32 0, i32 1 783 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[TMP12]], i32 0, i32 2 784 // CHECK1-NEXT: [[TMP25:%.*]] = load i32, i32* [[TMP23]], align 4 785 // CHECK1-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) #[[ATTR4]] 786 // CHECK1-NEXT: [[TMP26:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 [[TMP25]], i32 1, i32 0, i8* null, i32 0, i8* null) #[[ATTR4]] 787 // CHECK1-NEXT: [[TMP27:%.*]] = icmp ne i32 [[TMP26]], 0 788 // CHECK1-NEXT: br i1 [[TMP27]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]] 789 // CHECK1: omp_offload.failed.i: 790 // CHECK1-NEXT: [[TMP28:%.*]] = load i16, i16* [[TMP16]], align 2 791 // CHECK1-NEXT: [[CONV_I:%.*]] = bitcast i64* [[AA_CASTED_I]] to i16* 792 // CHECK1-NEXT: store i16 [[TMP28]], i16* [[CONV_I]], align 2, !noalias !26 793 // CHECK1-NEXT: [[TMP29:%.*]] = load i64, i64* [[AA_CASTED_I]], align 8, !noalias !26 794 // CHECK1-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP23]], align 4 795 // CHECK1-NEXT: [[CONV4_I:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED_I]] to i32* 796 // CHECK1-NEXT: store i32 [[TMP30]], i32* [[CONV4_I]], align 4, !noalias !26 797 // CHECK1-NEXT: [[TMP31:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED_I]], align 8, !noalias !26 798 // CHECK1-NEXT: [[TMP32:%.*]] = load i32, i32* [[TMP24]], align 4 799 // CHECK1-NEXT: [[CONV6_I:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED5_I]] to i32* 800 // CHECK1-NEXT: store i32 [[TMP32]], i32* [[CONV6_I]], align 4, !noalias !26 801 // CHECK1-NEXT: [[TMP33:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED5_I]], align 8, !noalias !26 802 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97(i64 [[TMP29]], i64 [[TMP31]], i64 [[TMP33]]) #[[ATTR4]] 803 // CHECK1-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]] 804 // CHECK1: .omp_outlined..1.exit: 805 // CHECK1-NEXT: ret i32 0 806 // 807 // 808 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104 809 // CHECK1-SAME: (i64 noundef [[A:%.*]]) #[[ATTR3]] { 810 // CHECK1-NEXT: entry: 811 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 812 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 813 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 814 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 815 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 816 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32* 817 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 818 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 819 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]]) 820 // CHECK1-NEXT: ret void 821 // 822 // 823 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..2 824 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]]) #[[ATTR3]] { 825 // CHECK1-NEXT: entry: 826 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 827 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 828 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 829 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 830 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 831 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 832 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 833 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 834 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 835 // CHECK1-NEXT: [[A1:%.*]] = alloca i32, align 4 836 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 837 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 838 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 839 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 840 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 841 // CHECK1-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 842 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 843 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 844 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 845 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 846 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 847 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 848 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 849 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 850 // CHECK1: cond.true: 851 // CHECK1-NEXT: br label [[COND_END:%.*]] 852 // CHECK1: cond.false: 853 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 854 // CHECK1-NEXT: br label [[COND_END]] 855 // CHECK1: cond.end: 856 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 857 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 858 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 859 // CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 860 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 861 // CHECK1: omp.inner.for.cond: 862 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 863 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 864 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 865 // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 866 // CHECK1: omp.inner.for.body: 867 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 868 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 869 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 870 // CHECK1-NEXT: store i32 [[ADD]], i32* [[A1]], align 4 871 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[A1]], align 4 872 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1 873 // CHECK1-NEXT: store i32 [[ADD3]], i32* [[A1]], align 4 874 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 875 // CHECK1: omp.body.continue: 876 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 877 // CHECK1: omp.inner.for.inc: 878 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 879 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP9]], 1 880 // CHECK1-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 881 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP27:![0-9]+]] 882 // CHECK1: omp.inner.for.end: 883 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 884 // CHECK1: omp.loop.exit: 885 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 886 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 887 // CHECK1-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0 888 // CHECK1-NEXT: br i1 [[TMP11]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 889 // CHECK1: .omp.final.then: 890 // CHECK1-NEXT: store i32 10, i32* [[CONV]], align 4 891 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] 892 // CHECK1: .omp.final.done: 893 // CHECK1-NEXT: ret void 894 // 895 // 896 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 897 // CHECK1-SAME: (i64 noundef [[AA:%.*]]) #[[ATTR2]] { 898 // CHECK1-NEXT: entry: 899 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 900 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 901 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 902 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 903 // CHECK1-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 904 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 905 // CHECK1-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 906 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 907 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP1]]) 908 // CHECK1-NEXT: ret void 909 // 910 // 911 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..3 912 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR3]] { 913 // CHECK1-NEXT: entry: 914 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 915 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 916 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 917 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 918 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 919 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 920 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 921 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 922 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 923 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 924 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 925 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 926 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 927 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 928 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 929 // CHECK1-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 930 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 931 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 932 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 933 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 934 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 935 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 936 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 937 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 938 // CHECK1: cond.true: 939 // CHECK1-NEXT: br label [[COND_END:%.*]] 940 // CHECK1: cond.false: 941 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 942 // CHECK1-NEXT: br label [[COND_END]] 943 // CHECK1: cond.end: 944 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 945 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 946 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 947 // CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 948 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 949 // CHECK1: omp.inner.for.cond: 950 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !29 951 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !29 952 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 953 // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 954 // CHECK1: omp.inner.for.body: 955 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !29 956 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 957 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 958 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !29 959 // CHECK1-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !29 960 // CHECK1-NEXT: [[CONV2:%.*]] = sext i16 [[TMP8]] to i32 961 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 962 // CHECK1-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 963 // CHECK1-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2, !llvm.access.group !29 964 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 965 // CHECK1: omp.body.continue: 966 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 967 // CHECK1: omp.inner.for.inc: 968 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !29 969 // CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP9]], 1 970 // CHECK1-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !29 971 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP30:![0-9]+]] 972 // CHECK1: omp.inner.for.end: 973 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 974 // CHECK1: omp.loop.exit: 975 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 976 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 977 // CHECK1-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0 978 // CHECK1-NEXT: br i1 [[TMP11]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 979 // CHECK1: .omp.final.then: 980 // CHECK1-NEXT: store i32 10, i32* [[I]], align 4 981 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] 982 // CHECK1: .omp.final.done: 983 // CHECK1-NEXT: ret void 984 // 985 // 986 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118 987 // CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { 988 // CHECK1-NEXT: entry: 989 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 990 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 991 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 992 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 993 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 994 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 995 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 996 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 997 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 998 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* 999 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 1000 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 1001 // CHECK1-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 1002 // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 1003 // CHECK1-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 1004 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 1005 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) 1006 // CHECK1-NEXT: ret void 1007 // 1008 // 1009 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..6 1010 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR3]] { 1011 // CHECK1-NEXT: entry: 1012 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1013 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1014 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1015 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 1016 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1017 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 1018 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1019 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1020 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1021 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1022 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 1023 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1024 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1025 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 1026 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 1027 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 1028 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 1029 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1030 // CHECK1-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 1031 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 1032 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1033 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 1034 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 1035 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 1036 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1037 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 1038 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1039 // CHECK1: cond.true: 1040 // CHECK1-NEXT: br label [[COND_END:%.*]] 1041 // CHECK1: cond.false: 1042 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1043 // CHECK1-NEXT: br label [[COND_END]] 1044 // CHECK1: cond.end: 1045 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 1046 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 1047 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1048 // CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 1049 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1050 // CHECK1: omp.inner.for.cond: 1051 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !32 1052 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !32 1053 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 1054 // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1055 // CHECK1: omp.inner.for.body: 1056 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !32 1057 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 1058 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1059 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !32 1060 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !32 1061 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1 1062 // CHECK1-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4, !llvm.access.group !32 1063 // CHECK1-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 2, !llvm.access.group !32 1064 // CHECK1-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32 1065 // CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 1066 // CHECK1-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 1067 // CHECK1-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2, !llvm.access.group !32 1068 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1069 // CHECK1: omp.body.continue: 1070 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1071 // CHECK1: omp.inner.for.inc: 1072 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !32 1073 // CHECK1-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1 1074 // CHECK1-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !32 1075 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP33:![0-9]+]] 1076 // CHECK1: omp.inner.for.end: 1077 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1078 // CHECK1: omp.loop.exit: 1079 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 1080 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 1081 // CHECK1-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 1082 // CHECK1-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 1083 // CHECK1: .omp.final.then: 1084 // CHECK1-NEXT: store i32 10, i32* [[I]], align 4 1085 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] 1086 // CHECK1: .omp.final.done: 1087 // CHECK1-NEXT: ret void 1088 // 1089 // 1090 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142 1091 // CHECK1-SAME: (i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] { 1092 // CHECK1-NEXT: entry: 1093 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1094 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 1095 // CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 1096 // CHECK1-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 1097 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 1098 // CHECK1-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 1099 // CHECK1-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 1100 // CHECK1-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 1101 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 1102 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 1103 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 1104 // CHECK1-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 1105 // CHECK1-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 1106 // CHECK1-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 1107 // CHECK1-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 1108 // CHECK1-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 1109 // CHECK1-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 1110 // CHECK1-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 1111 // CHECK1-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 1112 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 1113 // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 1114 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 1115 // CHECK1-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 1116 // CHECK1-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 1117 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 1118 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 1119 // CHECK1-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 1120 // CHECK1-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 1121 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 1122 // CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* 1123 // CHECK1-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4 1124 // CHECK1-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 1125 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) 1126 // CHECK1-NEXT: ret void 1127 // 1128 // 1129 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..9 1130 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR3]] { 1131 // CHECK1-NEXT: entry: 1132 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1133 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1134 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1135 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 1136 // CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 1137 // CHECK1-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 1138 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 1139 // CHECK1-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 1140 // CHECK1-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 1141 // CHECK1-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 1142 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 1143 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1144 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 1145 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1146 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1147 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1148 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1149 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 1150 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1151 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1152 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 1153 // CHECK1-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 1154 // CHECK1-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 1155 // CHECK1-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 1156 // CHECK1-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 1157 // CHECK1-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 1158 // CHECK1-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 1159 // CHECK1-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 1160 // CHECK1-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 1161 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 1162 // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 1163 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 1164 // CHECK1-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 1165 // CHECK1-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 1166 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 1167 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 1168 // CHECK1-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 1169 // CHECK1-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 1170 // CHECK1-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 0 1171 // CHECK1-NEXT: call void @llvm.assume(i1 true) [ "align"(float* [[ARRAYDECAY]], i64 16) ] 1172 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1173 // CHECK1-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 1174 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 1175 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1176 // CHECK1-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 1177 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 1178 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 1179 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1180 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP10]], 9 1181 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1182 // CHECK1: cond.true: 1183 // CHECK1-NEXT: br label [[COND_END:%.*]] 1184 // CHECK1: cond.false: 1185 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1186 // CHECK1-NEXT: br label [[COND_END]] 1187 // CHECK1: cond.end: 1188 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] 1189 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 1190 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1191 // CHECK1-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 1192 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1193 // CHECK1: omp.inner.for.cond: 1194 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !35 1195 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !35 1196 // CHECK1-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] 1197 // CHECK1-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1198 // CHECK1: omp.inner.for.body: 1199 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !35 1200 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 1201 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1202 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !35 1203 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !35 1204 // CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP16]], 1 1205 // CHECK1-NEXT: store i32 [[ADD6]], i32* [[CONV]], align 4, !llvm.access.group !35 1206 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 1207 // CHECK1-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !35 1208 // CHECK1-NEXT: [[CONV7:%.*]] = fpext float [[TMP17]] to double 1209 // CHECK1-NEXT: [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00 1210 // CHECK1-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float 1211 // CHECK1-NEXT: store float [[CONV9]], float* [[ARRAYIDX]], align 4, !llvm.access.group !35 1212 // CHECK1-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 1213 // CHECK1-NEXT: [[TMP18:%.*]] = load float, float* [[ARRAYIDX10]], align 4, !llvm.access.group !35 1214 // CHECK1-NEXT: [[CONV11:%.*]] = fpext float [[TMP18]] to double 1215 // CHECK1-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00 1216 // CHECK1-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float 1217 // CHECK1-NEXT: store float [[CONV13]], float* [[ARRAYIDX10]], align 4, !llvm.access.group !35 1218 // CHECK1-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1 1219 // CHECK1-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX14]], i64 0, i64 2 1220 // CHECK1-NEXT: [[TMP19:%.*]] = load double, double* [[ARRAYIDX15]], align 8, !llvm.access.group !35 1221 // CHECK1-NEXT: [[ADD16:%.*]] = fadd double [[TMP19]], 1.000000e+00 1222 // CHECK1-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8, !llvm.access.group !35 1223 // CHECK1-NEXT: [[TMP20:%.*]] = mul nsw i64 1, [[TMP5]] 1224 // CHECK1-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP20]] 1225 // CHECK1-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX17]], i64 3 1226 // CHECK1-NEXT: [[TMP21:%.*]] = load double, double* [[ARRAYIDX18]], align 8, !llvm.access.group !35 1227 // CHECK1-NEXT: [[ADD19:%.*]] = fadd double [[TMP21]], 1.000000e+00 1228 // CHECK1-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8, !llvm.access.group !35 1229 // CHECK1-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 1230 // CHECK1-NEXT: [[TMP22:%.*]] = load i64, i64* [[X]], align 8, !llvm.access.group !35 1231 // CHECK1-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP22]], 1 1232 // CHECK1-NEXT: store i64 [[ADD20]], i64* [[X]], align 8, !llvm.access.group !35 1233 // CHECK1-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 1234 // CHECK1-NEXT: [[TMP23:%.*]] = load i8, i8* [[Y]], align 8, !llvm.access.group !35 1235 // CHECK1-NEXT: [[CONV21:%.*]] = sext i8 [[TMP23]] to i32 1236 // CHECK1-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1 1237 // CHECK1-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8 1238 // CHECK1-NEXT: store i8 [[CONV23]], i8* [[Y]], align 8, !llvm.access.group !35 1239 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1240 // CHECK1: omp.body.continue: 1241 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1242 // CHECK1: omp.inner.for.inc: 1243 // CHECK1-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !35 1244 // CHECK1-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP24]], 1 1245 // CHECK1-NEXT: store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !35 1246 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP36:![0-9]+]] 1247 // CHECK1: omp.inner.for.end: 1248 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1249 // CHECK1: omp.loop.exit: 1250 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]]) 1251 // CHECK1-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 1252 // CHECK1-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0 1253 // CHECK1-NEXT: br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 1254 // CHECK1: .omp.final.then: 1255 // CHECK1-NEXT: store i32 10, i32* [[I]], align 4 1256 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] 1257 // CHECK1: .omp.final.done: 1258 // CHECK1-NEXT: ret void 1259 // 1260 // 1261 // CHECK1-LABEL: define {{[^@]+}}@_Z3bari 1262 // CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { 1263 // CHECK1-NEXT: entry: 1264 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 1265 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4 1266 // CHECK1-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 1267 // CHECK1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 1268 // CHECK1-NEXT: store i32 0, i32* [[A]], align 4 1269 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 1270 // CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]]) 1271 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 1272 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 1273 // CHECK1-NEXT: store i32 [[ADD]], i32* [[A]], align 4 1274 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 1275 // CHECK1-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP2]]) 1276 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 1277 // CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 1278 // CHECK1-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 1279 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 1280 // CHECK1-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]]) 1281 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 1282 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 1283 // CHECK1-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 1284 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 1285 // CHECK1-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]]) 1286 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 1287 // CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] 1288 // CHECK1-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 1289 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 1290 // CHECK1-NEXT: ret i32 [[TMP8]] 1291 // 1292 // 1293 // CHECK1-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 1294 // CHECK1-SAME: (%struct.S1* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { 1295 // CHECK1-NEXT: entry: 1296 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 1297 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 1298 // CHECK1-NEXT: [[B:%.*]] = alloca i32, align 4 1299 // CHECK1-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 1300 // CHECK1-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 1301 // CHECK1-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 1302 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8 1303 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8 1304 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8 1305 // CHECK1-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 8 1306 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 1307 // CHECK1-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 1308 // CHECK1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 1309 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 1310 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 1311 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 1312 // CHECK1-NEXT: store i32 [[ADD]], i32* [[B]], align 4 1313 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 1314 // CHECK1-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 1315 // CHECK1-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() 1316 // CHECK1-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 1317 // CHECK1-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] 1318 // CHECK1-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 1319 // CHECK1-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 1320 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 1321 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32* 1322 // CHECK1-NEXT: store i32 [[TMP5]], i32* [[CONV]], align 4 1323 // CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 1324 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4 1325 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 60 1326 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 1327 // CHECK1: omp_if.then: 1328 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 1329 // CHECK1-NEXT: [[TMP8:%.*]] = mul nuw i64 2, [[TMP2]] 1330 // CHECK1-NEXT: [[TMP9:%.*]] = mul nuw i64 [[TMP8]], 2 1331 // CHECK1-NEXT: [[TMP10:%.*]] = bitcast [5 x i64]* [[DOTOFFLOAD_SIZES]] to i8* 1332 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP10]], i8* align 8 bitcast ([5 x i64]* @.offload_sizes.13 to i8*), i64 40, i1 false) 1333 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1334 // CHECK1-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to %struct.S1** 1335 // CHECK1-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP12]], align 8 1336 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1337 // CHECK1-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to double** 1338 // CHECK1-NEXT: store double* [[A]], double** [[TMP14]], align 8 1339 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 1340 // CHECK1-NEXT: store i8* null, i8** [[TMP15]], align 8 1341 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1342 // CHECK1-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64* 1343 // CHECK1-NEXT: store i64 [[TMP6]], i64* [[TMP17]], align 8 1344 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1345 // CHECK1-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64* 1346 // CHECK1-NEXT: store i64 [[TMP6]], i64* [[TMP19]], align 8 1347 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 1348 // CHECK1-NEXT: store i8* null, i8** [[TMP20]], align 8 1349 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1350 // CHECK1-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i64* 1351 // CHECK1-NEXT: store i64 2, i64* [[TMP22]], align 8 1352 // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1353 // CHECK1-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i64* 1354 // CHECK1-NEXT: store i64 2, i64* [[TMP24]], align 8 1355 // CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 1356 // CHECK1-NEXT: store i8* null, i8** [[TMP25]], align 8 1357 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 1358 // CHECK1-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64* 1359 // CHECK1-NEXT: store i64 [[TMP2]], i64* [[TMP27]], align 8 1360 // CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 1361 // CHECK1-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i64* 1362 // CHECK1-NEXT: store i64 [[TMP2]], i64* [[TMP29]], align 8 1363 // CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 1364 // CHECK1-NEXT: store i8* null, i8** [[TMP30]], align 8 1365 // CHECK1-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 1366 // CHECK1-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i16** 1367 // CHECK1-NEXT: store i16* [[VLA]], i16** [[TMP32]], align 8 1368 // CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 1369 // CHECK1-NEXT: [[TMP34:%.*]] = bitcast i8** [[TMP33]] to i16** 1370 // CHECK1-NEXT: store i16* [[VLA]], i16** [[TMP34]], align 8 1371 // CHECK1-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 1372 // CHECK1-NEXT: store i64 [[TMP9]], i64* [[TMP35]], align 8 1373 // CHECK1-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 1374 // CHECK1-NEXT: store i8* null, i8** [[TMP36]], align 8 1375 // CHECK1-NEXT: [[TMP37:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1376 // CHECK1-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1377 // CHECK1-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 1378 // CHECK1-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) 1379 // CHECK1-NEXT: [[TMP40:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215.region_id, i32 5, i8** [[TMP37]], i8** [[TMP38]], i64* [[TMP39]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.14, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1) 1380 // CHECK1-NEXT: [[TMP41:%.*]] = icmp ne i32 [[TMP40]], 0 1381 // CHECK1-NEXT: br i1 [[TMP41]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1382 // CHECK1: omp_offload.failed: 1383 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR4]] 1384 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 1385 // CHECK1: omp_offload.cont: 1386 // CHECK1-NEXT: br label [[OMP_IF_END:%.*]] 1387 // CHECK1: omp_if.else: 1388 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR4]] 1389 // CHECK1-NEXT: br label [[OMP_IF_END]] 1390 // CHECK1: omp_if.end: 1391 // CHECK1-NEXT: [[TMP42:%.*]] = mul nsw i64 1, [[TMP2]] 1392 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP42]] 1393 // CHECK1-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 1394 // CHECK1-NEXT: [[TMP43:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2 1395 // CHECK1-NEXT: [[CONV3:%.*]] = sext i16 [[TMP43]] to i32 1396 // CHECK1-NEXT: [[TMP44:%.*]] = load i32, i32* [[B]], align 4 1397 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], [[TMP44]] 1398 // CHECK1-NEXT: [[TMP45:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 1399 // CHECK1-NEXT: call void @llvm.stackrestore(i8* [[TMP45]]) 1400 // CHECK1-NEXT: ret i32 [[ADD4]] 1401 // 1402 // 1403 // CHECK1-LABEL: define {{[^@]+}}@_ZL7fstatici 1404 // CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { 1405 // CHECK1-NEXT: entry: 1406 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 1407 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4 1408 // CHECK1-NEXT: [[AA:%.*]] = alloca i16, align 2 1409 // CHECK1-NEXT: [[AAA:%.*]] = alloca i8, align 1 1410 // CHECK1-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 1411 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 1412 // CHECK1-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 1413 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 1414 // CHECK1-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 1415 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8 1416 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8 1417 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8 1418 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 1419 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 1420 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4 1421 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i32, align 4 1422 // CHECK1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 1423 // CHECK1-NEXT: store i32 0, i32* [[A]], align 4 1424 // CHECK1-NEXT: store i16 0, i16* [[AA]], align 2 1425 // CHECK1-NEXT: store i8 0, i8* [[AAA]], align 1 1426 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 1427 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* 1428 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 1429 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 1430 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 1431 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32* 1432 // CHECK1-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4 1433 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8 1434 // CHECK1-NEXT: [[TMP4:%.*]] = load i16, i16* [[AA]], align 2 1435 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 1436 // CHECK1-NEXT: store i16 [[TMP4]], i16* [[CONV2]], align 2 1437 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[AA_CASTED]], align 8 1438 // CHECK1-NEXT: [[TMP6:%.*]] = load i8, i8* [[AAA]], align 1 1439 // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* 1440 // CHECK1-NEXT: store i8 [[TMP6]], i8* [[CONV3]], align 1 1441 // CHECK1-NEXT: [[TMP7:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 1442 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[N_ADDR]], align 4 1443 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP8]], 50 1444 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 1445 // CHECK1: omp_if.then: 1446 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1447 // CHECK1-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* 1448 // CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP10]], align 8 1449 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1450 // CHECK1-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64* 1451 // CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP12]], align 8 1452 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 1453 // CHECK1-NEXT: store i8* null, i8** [[TMP13]], align 8 1454 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1455 // CHECK1-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* 1456 // CHECK1-NEXT: store i64 [[TMP3]], i64* [[TMP15]], align 8 1457 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1458 // CHECK1-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64* 1459 // CHECK1-NEXT: store i64 [[TMP3]], i64* [[TMP17]], align 8 1460 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 1461 // CHECK1-NEXT: store i8* null, i8** [[TMP18]], align 8 1462 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1463 // CHECK1-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64* 1464 // CHECK1-NEXT: store i64 [[TMP5]], i64* [[TMP20]], align 8 1465 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1466 // CHECK1-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i64* 1467 // CHECK1-NEXT: store i64 [[TMP5]], i64* [[TMP22]], align 8 1468 // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 1469 // CHECK1-NEXT: store i8* null, i8** [[TMP23]], align 8 1470 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 1471 // CHECK1-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i64* 1472 // CHECK1-NEXT: store i64 [[TMP7]], i64* [[TMP25]], align 8 1473 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 1474 // CHECK1-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64* 1475 // CHECK1-NEXT: store i64 [[TMP7]], i64* [[TMP27]], align 8 1476 // CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 1477 // CHECK1-NEXT: store i8* null, i8** [[TMP28]], align 8 1478 // CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 1479 // CHECK1-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to [10 x i32]** 1480 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP30]], align 8 1481 // CHECK1-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 1482 // CHECK1-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to [10 x i32]** 1483 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP32]], align 8 1484 // CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 1485 // CHECK1-NEXT: store i8* null, i8** [[TMP33]], align 8 1486 // CHECK1-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1487 // CHECK1-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1488 // CHECK1-NEXT: [[TMP36:%.*]] = load i32, i32* [[A]], align 4 1489 // CHECK1-NEXT: store i32 [[TMP36]], i32* [[DOTCAPTURE_EXPR_]], align 4 1490 // CHECK1-NEXT: [[TMP37:%.*]] = load i32, i32* [[N_ADDR]], align 4 1491 // CHECK1-NEXT: store i32 [[TMP37]], i32* [[DOTCAPTURE_EXPR_4]], align 4 1492 // CHECK1-NEXT: [[TMP38:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 1493 // CHECK1-NEXT: [[TMP39:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 1494 // CHECK1-NEXT: [[SUB:%.*]] = sub i32 [[TMP38]], [[TMP39]] 1495 // CHECK1-NEXT: [[SUB6:%.*]] = sub i32 [[SUB]], 1 1496 // CHECK1-NEXT: [[ADD:%.*]] = add i32 [[SUB6]], 1 1497 // CHECK1-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 1498 // CHECK1-NEXT: [[SUB7:%.*]] = sub i32 [[DIV]], 1 1499 // CHECK1-NEXT: store i32 [[SUB7]], i32* [[DOTCAPTURE_EXPR_5]], align 4 1500 // CHECK1-NEXT: [[TMP40:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 1501 // CHECK1-NEXT: [[ADD8:%.*]] = add i32 [[TMP40]], 1 1502 // CHECK1-NEXT: [[TMP41:%.*]] = zext i32 [[ADD8]] to i64 1503 // CHECK1-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 [[TMP41]]) 1504 // CHECK1-NEXT: [[TMP42:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197.region_id, i32 5, i8** [[TMP34]], i8** [[TMP35]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes.16, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.17, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1) 1505 // CHECK1-NEXT: [[TMP43:%.*]] = icmp ne i32 [[TMP42]], 0 1506 // CHECK1-NEXT: br i1 [[TMP43]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1507 // CHECK1: omp_offload.failed: 1508 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], i64 [[TMP7]], [10 x i32]* [[B]]) #[[ATTR4]] 1509 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 1510 // CHECK1: omp_offload.cont: 1511 // CHECK1-NEXT: br label [[OMP_IF_END:%.*]] 1512 // CHECK1: omp_if.else: 1513 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], i64 [[TMP7]], [10 x i32]* [[B]]) #[[ATTR4]] 1514 // CHECK1-NEXT: br label [[OMP_IF_END]] 1515 // CHECK1: omp_if.end: 1516 // CHECK1-NEXT: [[TMP44:%.*]] = load i32, i32* [[A]], align 4 1517 // CHECK1-NEXT: ret i32 [[TMP44]] 1518 // 1519 // 1520 // CHECK1-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 1521 // CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat { 1522 // CHECK1-NEXT: entry: 1523 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 1524 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4 1525 // CHECK1-NEXT: [[AA:%.*]] = alloca i16, align 2 1526 // CHECK1-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 1527 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 1528 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 1529 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 1530 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 1531 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 1532 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 1533 // CHECK1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 1534 // CHECK1-NEXT: store i32 0, i32* [[A]], align 4 1535 // CHECK1-NEXT: store i16 0, i16* [[AA]], align 2 1536 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 1537 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* 1538 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 1539 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 1540 // CHECK1-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 1541 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 1542 // CHECK1-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 1543 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 1544 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 1545 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40 1546 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 1547 // CHECK1: omp_if.then: 1548 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1549 // CHECK1-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64* 1550 // CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP6]], align 8 1551 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1552 // CHECK1-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* 1553 // CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8 1554 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 1555 // CHECK1-NEXT: store i8* null, i8** [[TMP9]], align 8 1556 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1557 // CHECK1-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i64* 1558 // CHECK1-NEXT: store i64 [[TMP3]], i64* [[TMP11]], align 8 1559 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1560 // CHECK1-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* 1561 // CHECK1-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8 1562 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 1563 // CHECK1-NEXT: store i8* null, i8** [[TMP14]], align 8 1564 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1565 // CHECK1-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]** 1566 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 8 1567 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1568 // CHECK1-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]** 1569 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 8 1570 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 1571 // CHECK1-NEXT: store i8* null, i8** [[TMP19]], align 8 1572 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1573 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1574 // CHECK1-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) 1575 // CHECK1-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.19, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.20, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1) 1576 // CHECK1-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 1577 // CHECK1-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1578 // CHECK1: omp_offload.failed: 1579 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]] 1580 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 1581 // CHECK1: omp_offload.cont: 1582 // CHECK1-NEXT: br label [[OMP_IF_END:%.*]] 1583 // CHECK1: omp_if.else: 1584 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]] 1585 // CHECK1-NEXT: br label [[OMP_IF_END]] 1586 // CHECK1: omp_if.end: 1587 // CHECK1-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4 1588 // CHECK1-NEXT: ret i32 [[TMP24]] 1589 // 1590 // 1591 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215 1592 // CHECK1-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { 1593 // CHECK1-NEXT: entry: 1594 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 1595 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 1596 // CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 1597 // CHECK1-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 1598 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 1599 // CHECK1-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 1600 // CHECK1-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 1601 // CHECK1-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 1602 // CHECK1-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 1603 // CHECK1-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 1604 // CHECK1-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 1605 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 1606 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 1607 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 1608 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 1609 // CHECK1-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 1610 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4 1611 // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* 1612 // CHECK1-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 1613 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 1614 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..12 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) 1615 // CHECK1-NEXT: ret void 1616 // 1617 // 1618 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..12 1619 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] { 1620 // CHECK1-NEXT: entry: 1621 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1622 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1623 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 1624 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 1625 // CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 1626 // CHECK1-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 1627 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 1628 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1629 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 1630 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1631 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1632 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1633 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1634 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 1635 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1636 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1637 // CHECK1-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 1638 // CHECK1-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 1639 // CHECK1-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 1640 // CHECK1-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 1641 // CHECK1-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 1642 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 1643 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 1644 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 1645 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 1646 // CHECK1-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 1647 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1648 // CHECK1-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 1649 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 1650 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1651 // CHECK1-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 1652 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 1653 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 1654 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1655 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 9 1656 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1657 // CHECK1: cond.true: 1658 // CHECK1-NEXT: br label [[COND_END:%.*]] 1659 // CHECK1: cond.false: 1660 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1661 // CHECK1-NEXT: br label [[COND_END]] 1662 // CHECK1: cond.end: 1663 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 1664 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 1665 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1666 // CHECK1-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 1667 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1668 // CHECK1: omp.inner.for.cond: 1669 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !38 1670 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !38 1671 // CHECK1-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 1672 // CHECK1-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1673 // CHECK1: omp.inner.for.body: 1674 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !38 1675 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 1676 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1677 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !38 1678 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !38 1679 // CHECK1-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double 1680 // CHECK1-NEXT: [[ADD5:%.*]] = fadd double [[CONV4]], 1.500000e+00 1681 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 1682 // CHECK1-NEXT: store double [[ADD5]], double* [[A]], align 8, !llvm.access.group !38 1683 // CHECK1-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 1684 // CHECK1-NEXT: [[TMP13:%.*]] = load double, double* [[A6]], align 8, !llvm.access.group !38 1685 // CHECK1-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 1686 // CHECK1-NEXT: store double [[INC]], double* [[A6]], align 8, !llvm.access.group !38 1687 // CHECK1-NEXT: [[CONV7:%.*]] = fptosi double [[INC]] to i16 1688 // CHECK1-NEXT: [[TMP14:%.*]] = mul nsw i64 1, [[TMP2]] 1689 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP14]] 1690 // CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 1691 // CHECK1-NEXT: store i16 [[CONV7]], i16* [[ARRAYIDX8]], align 2, !llvm.access.group !38 1692 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1693 // CHECK1: omp.body.continue: 1694 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1695 // CHECK1: omp.inner.for.inc: 1696 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !38 1697 // CHECK1-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP15]], 1 1698 // CHECK1-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !38 1699 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP39:![0-9]+]] 1700 // CHECK1: omp.inner.for.end: 1701 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1702 // CHECK1: omp.loop.exit: 1703 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 1704 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 1705 // CHECK1-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0 1706 // CHECK1-NEXT: br i1 [[TMP17]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 1707 // CHECK1: .omp.final.then: 1708 // CHECK1-NEXT: store i32 10, i32* [[I]], align 4 1709 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] 1710 // CHECK1: .omp.final.done: 1711 // CHECK1-NEXT: ret void 1712 // 1713 // 1714 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197 1715 // CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[N:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 1716 // CHECK1-NEXT: entry: 1717 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1718 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 1719 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 1720 // CHECK1-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 1721 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 1722 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 1723 // CHECK1-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 1724 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 1725 // CHECK1-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 1726 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 1727 // CHECK1-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 1728 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 1729 // CHECK1-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 1730 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 1731 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 1732 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32* 1733 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 1734 // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 1735 // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 1736 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 1737 // CHECK1-NEXT: [[CONV4:%.*]] = bitcast i64* [[A_CASTED]] to i32* 1738 // CHECK1-NEXT: store i32 [[TMP1]], i32* [[CONV4]], align 4 1739 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 1740 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 4 1741 // CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[N_CASTED]] to i32* 1742 // CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV5]], align 4 1743 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8 1744 // CHECK1-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV2]], align 2 1745 // CHECK1-NEXT: [[CONV6:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 1746 // CHECK1-NEXT: store i16 [[TMP5]], i16* [[CONV6]], align 2 1747 // CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[AA_CASTED]], align 8 1748 // CHECK1-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV3]], align 1 1749 // CHECK1-NEXT: [[CONV7:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* 1750 // CHECK1-NEXT: store i8 [[TMP7]], i8* [[CONV7]], align 1 1751 // CHECK1-NEXT: [[TMP8:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 1752 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, [10 x i32]*)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]], [10 x i32]* [[TMP0]]) 1753 // CHECK1-NEXT: ret void 1754 // 1755 // 1756 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..15 1757 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[N:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { 1758 // CHECK1-NEXT: entry: 1759 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1760 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1761 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1762 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 1763 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 1764 // CHECK1-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 1765 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 1766 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1767 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 1768 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 1769 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4 1770 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i32, align 4 1771 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 1772 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1773 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1774 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1775 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1776 // CHECK1-NEXT: [[I8:%.*]] = alloca i32, align 4 1777 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1778 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1779 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 1780 // CHECK1-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 1781 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 1782 // CHECK1-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 1783 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 1784 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 1785 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32* 1786 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 1787 // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 1788 // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 1789 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 1790 // CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 1791 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4 1792 // CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_4]], align 4 1793 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 1794 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 1795 // CHECK1-NEXT: [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]] 1796 // CHECK1-NEXT: [[SUB6:%.*]] = sub i32 [[SUB]], 1 1797 // CHECK1-NEXT: [[ADD:%.*]] = add i32 [[SUB6]], 1 1798 // CHECK1-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 1799 // CHECK1-NEXT: [[SUB7:%.*]] = sub i32 [[DIV]], 1 1800 // CHECK1-NEXT: store i32 [[SUB7]], i32* [[DOTCAPTURE_EXPR_5]], align 4 1801 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 1802 // CHECK1-NEXT: store i32 [[TMP5]], i32* [[I]], align 4 1803 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 1804 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 1805 // CHECK1-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]] 1806 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] 1807 // CHECK1: omp.precond.then: 1808 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1809 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 1810 // CHECK1-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_UB]], align 4 1811 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 1812 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1813 // CHECK1-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 1814 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 1815 // CHECK1-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 1816 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1817 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 1818 // CHECK1-NEXT: [[CMP9:%.*]] = icmp ugt i32 [[TMP11]], [[TMP12]] 1819 // CHECK1-NEXT: br i1 [[CMP9]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1820 // CHECK1: cond.true: 1821 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 1822 // CHECK1-NEXT: br label [[COND_END:%.*]] 1823 // CHECK1: cond.false: 1824 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1825 // CHECK1-NEXT: br label [[COND_END]] 1826 // CHECK1: cond.end: 1827 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ] 1828 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 1829 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1830 // CHECK1-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4 1831 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1832 // CHECK1: omp.inner.for.cond: 1833 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !41 1834 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !41 1835 // CHECK1-NEXT: [[ADD10:%.*]] = add i32 [[TMP17]], 1 1836 // CHECK1-NEXT: [[CMP11:%.*]] = icmp ult i32 [[TMP16]], [[ADD10]] 1837 // CHECK1-NEXT: br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1838 // CHECK1: omp.inner.for.body: 1839 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group !41 1840 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !41 1841 // CHECK1-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 1 1842 // CHECK1-NEXT: [[ADD12:%.*]] = add i32 [[TMP18]], [[MUL]] 1843 // CHECK1-NEXT: store i32 [[ADD12]], i32* [[I8]], align 4, !llvm.access.group !41 1844 // CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !41 1845 // CHECK1-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP20]], 1 1846 // CHECK1-NEXT: store i32 [[ADD13]], i32* [[CONV]], align 4, !llvm.access.group !41 1847 // CHECK1-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV2]], align 2, !llvm.access.group !41 1848 // CHECK1-NEXT: [[CONV14:%.*]] = sext i16 [[TMP21]] to i32 1849 // CHECK1-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1 1850 // CHECK1-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16 1851 // CHECK1-NEXT: store i16 [[CONV16]], i16* [[CONV2]], align 2, !llvm.access.group !41 1852 // CHECK1-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV3]], align 1, !llvm.access.group !41 1853 // CHECK1-NEXT: [[CONV17:%.*]] = sext i8 [[TMP22]] to i32 1854 // CHECK1-NEXT: [[ADD18:%.*]] = add nsw i32 [[CONV17]], 1 1855 // CHECK1-NEXT: [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8 1856 // CHECK1-NEXT: store i8 [[CONV19]], i8* [[CONV3]], align 1, !llvm.access.group !41 1857 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 1858 // CHECK1-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !41 1859 // CHECK1-NEXT: [[ADD20:%.*]] = add nsw i32 [[TMP23]], 1 1860 // CHECK1-NEXT: store i32 [[ADD20]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !41 1861 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1862 // CHECK1: omp.body.continue: 1863 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1864 // CHECK1: omp.inner.for.inc: 1865 // CHECK1-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !41 1866 // CHECK1-NEXT: [[ADD21:%.*]] = add i32 [[TMP24]], 1 1867 // CHECK1-NEXT: store i32 [[ADD21]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !41 1868 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP42:![0-9]+]] 1869 // CHECK1: omp.inner.for.end: 1870 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1871 // CHECK1: omp.loop.exit: 1872 // CHECK1-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 1873 // CHECK1-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 1874 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) 1875 // CHECK1-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 1876 // CHECK1-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0 1877 // CHECK1-NEXT: br i1 [[TMP28]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 1878 // CHECK1: .omp.final.then: 1879 // CHECK1-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 1880 // CHECK1-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 1881 // CHECK1-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 1882 // CHECK1-NEXT: [[SUB22:%.*]] = sub i32 [[TMP30]], [[TMP31]] 1883 // CHECK1-NEXT: [[SUB23:%.*]] = sub i32 [[SUB22]], 1 1884 // CHECK1-NEXT: [[ADD24:%.*]] = add i32 [[SUB23]], 1 1885 // CHECK1-NEXT: [[DIV25:%.*]] = udiv i32 [[ADD24]], 1 1886 // CHECK1-NEXT: [[MUL26:%.*]] = mul i32 [[DIV25]], 1 1887 // CHECK1-NEXT: [[ADD27:%.*]] = add i32 [[TMP29]], [[MUL26]] 1888 // CHECK1-NEXT: store i32 [[ADD27]], i32* [[I8]], align 4 1889 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] 1890 // CHECK1: .omp.final.done: 1891 // CHECK1-NEXT: br label [[OMP_PRECOND_END]] 1892 // CHECK1: omp.precond.end: 1893 // CHECK1-NEXT: ret void 1894 // 1895 // 1896 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180 1897 // CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 1898 // CHECK1-NEXT: entry: 1899 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1900 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 1901 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 1902 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 1903 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 1904 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 1905 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 1906 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 1907 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 1908 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 1909 // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 1910 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 1911 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* 1912 // CHECK1-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 1913 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 1914 // CHECK1-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 1915 // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 1916 // CHECK1-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 1917 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 1918 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..18 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) 1919 // CHECK1-NEXT: ret void 1920 // 1921 // 1922 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..18 1923 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { 1924 // CHECK1-NEXT: entry: 1925 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1926 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1927 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1928 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 1929 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 1930 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1931 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 1932 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1933 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1934 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1935 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1936 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 1937 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1938 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1939 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 1940 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 1941 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 1942 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 1943 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 1944 // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 1945 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1946 // CHECK1-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 1947 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 1948 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1949 // CHECK1-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 1950 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 1951 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 1952 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1953 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 1954 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1955 // CHECK1: cond.true: 1956 // CHECK1-NEXT: br label [[COND_END:%.*]] 1957 // CHECK1: cond.false: 1958 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1959 // CHECK1-NEXT: br label [[COND_END]] 1960 // CHECK1: cond.end: 1961 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 1962 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 1963 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1964 // CHECK1-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 1965 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1966 // CHECK1: omp.inner.for.cond: 1967 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !44 1968 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !44 1969 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] 1970 // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1971 // CHECK1: omp.inner.for.body: 1972 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !44 1973 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 1974 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1975 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !44 1976 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !44 1977 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1 1978 // CHECK1-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4, !llvm.access.group !44 1979 // CHECK1-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 2, !llvm.access.group !44 1980 // CHECK1-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32 1981 // CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 1982 // CHECK1-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 1983 // CHECK1-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2, !llvm.access.group !44 1984 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 1985 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !44 1986 // CHECK1-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1 1987 // CHECK1-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !44 1988 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1989 // CHECK1: omp.body.continue: 1990 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1991 // CHECK1: omp.inner.for.inc: 1992 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !44 1993 // CHECK1-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP12]], 1 1994 // CHECK1-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !44 1995 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP45:![0-9]+]] 1996 // CHECK1: omp.inner.for.end: 1997 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1998 // CHECK1: omp.loop.exit: 1999 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) 2000 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 2001 // CHECK1-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 2002 // CHECK1-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 2003 // CHECK1: .omp.final.then: 2004 // CHECK1-NEXT: store i32 10, i32* [[I]], align 4 2005 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] 2006 // CHECK1: .omp.final.done: 2007 // CHECK1-NEXT: ret void 2008 // 2009 // 2010 // CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 2011 // CHECK1-SAME: () #[[ATTR5]] { 2012 // CHECK1-NEXT: entry: 2013 // CHECK1-NEXT: call void @__tgt_register_requires(i64 1) 2014 // CHECK1-NEXT: ret void 2015 // 2016 // 2017 // CHECK3-LABEL: define {{[^@]+}}@_Z3fooi 2018 // CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0:[0-9]+]] { 2019 // CHECK3-NEXT: entry: 2020 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 2021 // CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4 2022 // CHECK3-NEXT: [[AA:%.*]] = alloca i16, align 2 2023 // CHECK3-NEXT: [[B:%.*]] = alloca [10 x float], align 4 2024 // CHECK3-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 2025 // CHECK3-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 2026 // CHECK3-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 2027 // CHECK3-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 2028 // CHECK3-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 2029 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 2030 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 2031 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 2032 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 2033 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__CASTED3:%.*]] = alloca i32, align 4 2034 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 2035 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 2036 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 2037 // CHECK3-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4 2038 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 2039 // CHECK3-NEXT: [[AA_CASTED4:%.*]] = alloca i32, align 4 2040 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS6:%.*]] = alloca [1 x i8*], align 4 2041 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS7:%.*]] = alloca [1 x i8*], align 4 2042 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS8:%.*]] = alloca [1 x i8*], align 4 2043 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 2044 // CHECK3-NEXT: [[A_CASTED9:%.*]] = alloca i32, align 4 2045 // CHECK3-NEXT: [[AA_CASTED10:%.*]] = alloca i32, align 4 2046 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS12:%.*]] = alloca [2 x i8*], align 4 2047 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS13:%.*]] = alloca [2 x i8*], align 4 2048 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS14:%.*]] = alloca [2 x i8*], align 4 2049 // CHECK3-NEXT: [[_TMP15:%.*]] = alloca i32, align 4 2050 // CHECK3-NEXT: [[A_CASTED18:%.*]] = alloca i32, align 4 2051 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS21:%.*]] = alloca [9 x i8*], align 4 2052 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS22:%.*]] = alloca [9 x i8*], align 4 2053 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS23:%.*]] = alloca [9 x i8*], align 4 2054 // CHECK3-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [9 x i64], align 4 2055 // CHECK3-NEXT: [[_TMP24:%.*]] = alloca i32, align 4 2056 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) 2057 // CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 2058 // CHECK3-NEXT: store i32 0, i32* [[A]], align 4 2059 // CHECK3-NEXT: store i16 0, i16* [[AA]], align 2 2060 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 2061 // CHECK3-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() 2062 // CHECK3-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 2063 // CHECK3-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP1]], align 4 2064 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 2065 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 2066 // CHECK3-NEXT: [[TMP4:%.*]] = mul nuw i32 5, [[TMP3]] 2067 // CHECK3-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP4]], align 8 2068 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[__VLA_EXPR1]], align 4 2069 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 2070 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_]], align 4 2071 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 2072 // CHECK3-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_2]], align 4 2073 // CHECK3-NEXT: [[TMP7:%.*]] = load i16, i16* [[AA]], align 2 2074 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 2075 // CHECK3-NEXT: store i16 [[TMP7]], i16* [[CONV]], align 2 2076 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[AA_CASTED]], align 4 2077 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 2078 // CHECK3-NEXT: store i32 [[TMP9]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 2079 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 2080 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 2081 // CHECK3-NEXT: store i32 [[TMP11]], i32* [[DOTCAPTURE_EXPR__CASTED3]], align 4 2082 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED3]], align 4 2083 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2084 // CHECK3-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i32* 2085 // CHECK3-NEXT: store i32 [[TMP8]], i32* [[TMP14]], align 4 2086 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2087 // CHECK3-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i32* 2088 // CHECK3-NEXT: store i32 [[TMP8]], i32* [[TMP16]], align 4 2089 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 2090 // CHECK3-NEXT: store i8* null, i8** [[TMP17]], align 4 2091 // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 2092 // CHECK3-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32* 2093 // CHECK3-NEXT: store i32 [[TMP10]], i32* [[TMP19]], align 4 2094 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 2095 // CHECK3-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32* 2096 // CHECK3-NEXT: store i32 [[TMP10]], i32* [[TMP21]], align 4 2097 // CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 2098 // CHECK3-NEXT: store i8* null, i8** [[TMP22]], align 4 2099 // CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 2100 // CHECK3-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i32* 2101 // CHECK3-NEXT: store i32 [[TMP12]], i32* [[TMP24]], align 4 2102 // CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 2103 // CHECK3-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i32* 2104 // CHECK3-NEXT: store i32 [[TMP12]], i32* [[TMP26]], align 4 2105 // CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 2106 // CHECK3-NEXT: store i8* null, i8** [[TMP27]], align 4 2107 // CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2108 // CHECK3-NEXT: [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2109 // CHECK3-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 0 2110 // CHECK3-NEXT: [[TMP31:%.*]] = load i16, i16* [[AA]], align 2 2111 // CHECK3-NEXT: store i16 [[TMP31]], i16* [[TMP30]], align 4 2112 // CHECK3-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 1 2113 // CHECK3-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 2114 // CHECK3-NEXT: store i32 [[TMP33]], i32* [[TMP32]], align 4 2115 // CHECK3-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 2 2116 // CHECK3-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 2117 // CHECK3-NEXT: store i32 [[TMP35]], i32* [[TMP34]], align 4 2118 // CHECK3-NEXT: [[TMP36:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 1, i32 72, i32 12, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1) 2119 // CHECK3-NEXT: [[TMP37:%.*]] = bitcast i8* [[TMP36]] to %struct.kmp_task_t_with_privates* 2120 // CHECK3-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP37]], i32 0, i32 0 2121 // CHECK3-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP38]], i32 0, i32 0 2122 // CHECK3-NEXT: [[TMP40:%.*]] = load i8*, i8** [[TMP39]], align 4 2123 // CHECK3-NEXT: [[TMP41:%.*]] = bitcast %struct.anon* [[AGG_CAPTURED]] to i8* 2124 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP40]], i8* align 4 [[TMP41]], i32 12, i1 false) 2125 // CHECK3-NEXT: [[TMP42:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP37]], i32 0, i32 1 2126 // CHECK3-NEXT: [[TMP43:%.*]] = bitcast i8* [[TMP40]] to %struct.anon* 2127 // CHECK3-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 0 2128 // CHECK3-NEXT: [[TMP45:%.*]] = bitcast [3 x i64]* [[TMP44]] to i8* 2129 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP45]], i8* align 4 bitcast ([3 x i64]* @.offload_sizes to i8*), i32 24, i1 false) 2130 // CHECK3-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 1 2131 // CHECK3-NEXT: [[TMP47:%.*]] = bitcast [3 x i8*]* [[TMP46]] to i8* 2132 // CHECK3-NEXT: [[TMP48:%.*]] = bitcast i8** [[TMP28]] to i8* 2133 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP47]], i8* align 4 [[TMP48]], i32 12, i1 false) 2134 // CHECK3-NEXT: [[TMP49:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 2 2135 // CHECK3-NEXT: [[TMP50:%.*]] = bitcast [3 x i8*]* [[TMP49]] to i8* 2136 // CHECK3-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP29]] to i8* 2137 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP50]], i8* align 4 [[TMP51]], i32 12, i1 false) 2138 // CHECK3-NEXT: [[TMP52:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 3 2139 // CHECK3-NEXT: [[TMP53:%.*]] = load i16, i16* [[AA]], align 2 2140 // CHECK3-NEXT: store i16 [[TMP53]], i16* [[TMP52]], align 4 2141 // CHECK3-NEXT: [[TMP54:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i8* [[TMP36]]) 2142 // CHECK3-NEXT: [[TMP55:%.*]] = load i32, i32* [[A]], align 4 2143 // CHECK3-NEXT: store i32 [[TMP55]], i32* [[A_CASTED]], align 4 2144 // CHECK3-NEXT: [[TMP56:%.*]] = load i32, i32* [[A_CASTED]], align 4 2145 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104(i32 [[TMP56]]) #[[ATTR4:[0-9]+]] 2146 // CHECK3-NEXT: [[TMP57:%.*]] = load i16, i16* [[AA]], align 2 2147 // CHECK3-NEXT: [[CONV5:%.*]] = bitcast i32* [[AA_CASTED4]] to i16* 2148 // CHECK3-NEXT: store i16 [[TMP57]], i16* [[CONV5]], align 2 2149 // CHECK3-NEXT: [[TMP58:%.*]] = load i32, i32* [[AA_CASTED4]], align 4 2150 // CHECK3-NEXT: [[TMP59:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0 2151 // CHECK3-NEXT: [[TMP60:%.*]] = bitcast i8** [[TMP59]] to i32* 2152 // CHECK3-NEXT: store i32 [[TMP58]], i32* [[TMP60]], align 4 2153 // CHECK3-NEXT: [[TMP61:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0 2154 // CHECK3-NEXT: [[TMP62:%.*]] = bitcast i8** [[TMP61]] to i32* 2155 // CHECK3-NEXT: store i32 [[TMP58]], i32* [[TMP62]], align 4 2156 // CHECK3-NEXT: [[TMP63:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS8]], i32 0, i32 0 2157 // CHECK3-NEXT: store i8* null, i8** [[TMP63]], align 4 2158 // CHECK3-NEXT: [[TMP64:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0 2159 // CHECK3-NEXT: [[TMP65:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0 2160 // CHECK3-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) 2161 // CHECK3-NEXT: [[TMP66:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.region_id, i32 1, i8** [[TMP64]], i8** [[TMP65]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.4, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.5, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1) 2162 // CHECK3-NEXT: [[TMP67:%.*]] = icmp ne i32 [[TMP66]], 0 2163 // CHECK3-NEXT: br i1 [[TMP67]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 2164 // CHECK3: omp_offload.failed: 2165 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111(i32 [[TMP58]]) #[[ATTR4]] 2166 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 2167 // CHECK3: omp_offload.cont: 2168 // CHECK3-NEXT: [[TMP68:%.*]] = load i32, i32* [[A]], align 4 2169 // CHECK3-NEXT: store i32 [[TMP68]], i32* [[A_CASTED9]], align 4 2170 // CHECK3-NEXT: [[TMP69:%.*]] = load i32, i32* [[A_CASTED9]], align 4 2171 // CHECK3-NEXT: [[TMP70:%.*]] = load i16, i16* [[AA]], align 2 2172 // CHECK3-NEXT: [[CONV11:%.*]] = bitcast i32* [[AA_CASTED10]] to i16* 2173 // CHECK3-NEXT: store i16 [[TMP70]], i16* [[CONV11]], align 2 2174 // CHECK3-NEXT: [[TMP71:%.*]] = load i32, i32* [[AA_CASTED10]], align 4 2175 // CHECK3-NEXT: [[TMP72:%.*]] = load i32, i32* [[N_ADDR]], align 4 2176 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP72]], 10 2177 // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 2178 // CHECK3: omp_if.then: 2179 // CHECK3-NEXT: [[TMP73:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS12]], i32 0, i32 0 2180 // CHECK3-NEXT: [[TMP74:%.*]] = bitcast i8** [[TMP73]] to i32* 2181 // CHECK3-NEXT: store i32 [[TMP69]], i32* [[TMP74]], align 4 2182 // CHECK3-NEXT: [[TMP75:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS13]], i32 0, i32 0 2183 // CHECK3-NEXT: [[TMP76:%.*]] = bitcast i8** [[TMP75]] to i32* 2184 // CHECK3-NEXT: store i32 [[TMP69]], i32* [[TMP76]], align 4 2185 // CHECK3-NEXT: [[TMP77:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS14]], i32 0, i32 0 2186 // CHECK3-NEXT: store i8* null, i8** [[TMP77]], align 4 2187 // CHECK3-NEXT: [[TMP78:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS12]], i32 0, i32 1 2188 // CHECK3-NEXT: [[TMP79:%.*]] = bitcast i8** [[TMP78]] to i32* 2189 // CHECK3-NEXT: store i32 [[TMP71]], i32* [[TMP79]], align 4 2190 // CHECK3-NEXT: [[TMP80:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS13]], i32 0, i32 1 2191 // CHECK3-NEXT: [[TMP81:%.*]] = bitcast i8** [[TMP80]] to i32* 2192 // CHECK3-NEXT: store i32 [[TMP71]], i32* [[TMP81]], align 4 2193 // CHECK3-NEXT: [[TMP82:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS14]], i32 0, i32 1 2194 // CHECK3-NEXT: store i8* null, i8** [[TMP82]], align 4 2195 // CHECK3-NEXT: [[TMP83:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS12]], i32 0, i32 0 2196 // CHECK3-NEXT: [[TMP84:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS13]], i32 0, i32 0 2197 // CHECK3-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) 2198 // CHECK3-NEXT: [[TMP85:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.region_id, i32 2, i8** [[TMP83]], i8** [[TMP84]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.7, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.8, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1) 2199 // CHECK3-NEXT: [[TMP86:%.*]] = icmp ne i32 [[TMP85]], 0 2200 // CHECK3-NEXT: br i1 [[TMP86]], label [[OMP_OFFLOAD_FAILED16:%.*]], label [[OMP_OFFLOAD_CONT17:%.*]] 2201 // CHECK3: omp_offload.failed16: 2202 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i32 [[TMP69]], i32 [[TMP71]]) #[[ATTR4]] 2203 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT17]] 2204 // CHECK3: omp_offload.cont17: 2205 // CHECK3-NEXT: br label [[OMP_IF_END:%.*]] 2206 // CHECK3: omp_if.else: 2207 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i32 [[TMP69]], i32 [[TMP71]]) #[[ATTR4]] 2208 // CHECK3-NEXT: br label [[OMP_IF_END]] 2209 // CHECK3: omp_if.end: 2210 // CHECK3-NEXT: [[TMP87:%.*]] = load i32, i32* [[A]], align 4 2211 // CHECK3-NEXT: store i32 [[TMP87]], i32* [[A_CASTED18]], align 4 2212 // CHECK3-NEXT: [[TMP88:%.*]] = load i32, i32* [[A_CASTED18]], align 4 2213 // CHECK3-NEXT: [[TMP89:%.*]] = load i32, i32* [[N_ADDR]], align 4 2214 // CHECK3-NEXT: [[CMP19:%.*]] = icmp sgt i32 [[TMP89]], 20 2215 // CHECK3-NEXT: br i1 [[CMP19]], label [[OMP_IF_THEN20:%.*]], label [[OMP_IF_ELSE27:%.*]] 2216 // CHECK3: omp_if.then20: 2217 // CHECK3-NEXT: [[TMP90:%.*]] = mul nuw i32 [[TMP1]], 4 2218 // CHECK3-NEXT: [[TMP91:%.*]] = sext i32 [[TMP90]] to i64 2219 // CHECK3-NEXT: [[TMP92:%.*]] = mul nuw i32 5, [[TMP3]] 2220 // CHECK3-NEXT: [[TMP93:%.*]] = mul nuw i32 [[TMP92]], 8 2221 // CHECK3-NEXT: [[TMP94:%.*]] = sext i32 [[TMP93]] to i64 2222 // CHECK3-NEXT: [[TMP95:%.*]] = bitcast [9 x i64]* [[DOTOFFLOAD_SIZES]] to i8* 2223 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP95]], i8* align 4 bitcast ([9 x i64]* @.offload_sizes.10 to i8*), i32 72, i1 false) 2224 // CHECK3-NEXT: [[TMP96:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 0 2225 // CHECK3-NEXT: [[TMP97:%.*]] = bitcast i8** [[TMP96]] to i32* 2226 // CHECK3-NEXT: store i32 [[TMP88]], i32* [[TMP97]], align 4 2227 // CHECK3-NEXT: [[TMP98:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 0 2228 // CHECK3-NEXT: [[TMP99:%.*]] = bitcast i8** [[TMP98]] to i32* 2229 // CHECK3-NEXT: store i32 [[TMP88]], i32* [[TMP99]], align 4 2230 // CHECK3-NEXT: [[TMP100:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i32 0, i32 0 2231 // CHECK3-NEXT: store i8* null, i8** [[TMP100]], align 4 2232 // CHECK3-NEXT: [[TMP101:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 1 2233 // CHECK3-NEXT: [[TMP102:%.*]] = bitcast i8** [[TMP101]] to [10 x float]** 2234 // CHECK3-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP102]], align 4 2235 // CHECK3-NEXT: [[TMP103:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 1 2236 // CHECK3-NEXT: [[TMP104:%.*]] = bitcast i8** [[TMP103]] to [10 x float]** 2237 // CHECK3-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP104]], align 4 2238 // CHECK3-NEXT: [[TMP105:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i32 0, i32 1 2239 // CHECK3-NEXT: store i8* null, i8** [[TMP105]], align 4 2240 // CHECK3-NEXT: [[TMP106:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 2 2241 // CHECK3-NEXT: [[TMP107:%.*]] = bitcast i8** [[TMP106]] to i32* 2242 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP107]], align 4 2243 // CHECK3-NEXT: [[TMP108:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 2 2244 // CHECK3-NEXT: [[TMP109:%.*]] = bitcast i8** [[TMP108]] to i32* 2245 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP109]], align 4 2246 // CHECK3-NEXT: [[TMP110:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i32 0, i32 2 2247 // CHECK3-NEXT: store i8* null, i8** [[TMP110]], align 4 2248 // CHECK3-NEXT: [[TMP111:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 3 2249 // CHECK3-NEXT: [[TMP112:%.*]] = bitcast i8** [[TMP111]] to float** 2250 // CHECK3-NEXT: store float* [[VLA]], float** [[TMP112]], align 4 2251 // CHECK3-NEXT: [[TMP113:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 3 2252 // CHECK3-NEXT: [[TMP114:%.*]] = bitcast i8** [[TMP113]] to float** 2253 // CHECK3-NEXT: store float* [[VLA]], float** [[TMP114]], align 4 2254 // CHECK3-NEXT: [[TMP115:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 2255 // CHECK3-NEXT: store i64 [[TMP91]], i64* [[TMP115]], align 4 2256 // CHECK3-NEXT: [[TMP116:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i32 0, i32 3 2257 // CHECK3-NEXT: store i8* null, i8** [[TMP116]], align 4 2258 // CHECK3-NEXT: [[TMP117:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 4 2259 // CHECK3-NEXT: [[TMP118:%.*]] = bitcast i8** [[TMP117]] to [5 x [10 x double]]** 2260 // CHECK3-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP118]], align 4 2261 // CHECK3-NEXT: [[TMP119:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 4 2262 // CHECK3-NEXT: [[TMP120:%.*]] = bitcast i8** [[TMP119]] to [5 x [10 x double]]** 2263 // CHECK3-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP120]], align 4 2264 // CHECK3-NEXT: [[TMP121:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i32 0, i32 4 2265 // CHECK3-NEXT: store i8* null, i8** [[TMP121]], align 4 2266 // CHECK3-NEXT: [[TMP122:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 5 2267 // CHECK3-NEXT: [[TMP123:%.*]] = bitcast i8** [[TMP122]] to i32* 2268 // CHECK3-NEXT: store i32 5, i32* [[TMP123]], align 4 2269 // CHECK3-NEXT: [[TMP124:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 5 2270 // CHECK3-NEXT: [[TMP125:%.*]] = bitcast i8** [[TMP124]] to i32* 2271 // CHECK3-NEXT: store i32 5, i32* [[TMP125]], align 4 2272 // CHECK3-NEXT: [[TMP126:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i32 0, i32 5 2273 // CHECK3-NEXT: store i8* null, i8** [[TMP126]], align 4 2274 // CHECK3-NEXT: [[TMP127:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 6 2275 // CHECK3-NEXT: [[TMP128:%.*]] = bitcast i8** [[TMP127]] to i32* 2276 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP128]], align 4 2277 // CHECK3-NEXT: [[TMP129:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 6 2278 // CHECK3-NEXT: [[TMP130:%.*]] = bitcast i8** [[TMP129]] to i32* 2279 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP130]], align 4 2280 // CHECK3-NEXT: [[TMP131:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i32 0, i32 6 2281 // CHECK3-NEXT: store i8* null, i8** [[TMP131]], align 4 2282 // CHECK3-NEXT: [[TMP132:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 7 2283 // CHECK3-NEXT: [[TMP133:%.*]] = bitcast i8** [[TMP132]] to double** 2284 // CHECK3-NEXT: store double* [[VLA1]], double** [[TMP133]], align 4 2285 // CHECK3-NEXT: [[TMP134:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 7 2286 // CHECK3-NEXT: [[TMP135:%.*]] = bitcast i8** [[TMP134]] to double** 2287 // CHECK3-NEXT: store double* [[VLA1]], double** [[TMP135]], align 4 2288 // CHECK3-NEXT: [[TMP136:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 2289 // CHECK3-NEXT: store i64 [[TMP94]], i64* [[TMP136]], align 4 2290 // CHECK3-NEXT: [[TMP137:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i32 0, i32 7 2291 // CHECK3-NEXT: store i8* null, i8** [[TMP137]], align 4 2292 // CHECK3-NEXT: [[TMP138:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 8 2293 // CHECK3-NEXT: [[TMP139:%.*]] = bitcast i8** [[TMP138]] to %struct.TT** 2294 // CHECK3-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP139]], align 4 2295 // CHECK3-NEXT: [[TMP140:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 8 2296 // CHECK3-NEXT: [[TMP141:%.*]] = bitcast i8** [[TMP140]] to %struct.TT** 2297 // CHECK3-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP141]], align 4 2298 // CHECK3-NEXT: [[TMP142:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i32 0, i32 8 2299 // CHECK3-NEXT: store i8* null, i8** [[TMP142]], align 4 2300 // CHECK3-NEXT: [[TMP143:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 0 2301 // CHECK3-NEXT: [[TMP144:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 0 2302 // CHECK3-NEXT: [[TMP145:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 2303 // CHECK3-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) 2304 // CHECK3-NEXT: [[TMP146:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142.region_id, i32 9, i8** [[TMP143]], i8** [[TMP144]], i64* [[TMP145]], i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_maptypes.11, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1) 2305 // CHECK3-NEXT: [[TMP147:%.*]] = icmp ne i32 [[TMP146]], 0 2306 // CHECK3-NEXT: br i1 [[TMP147]], label [[OMP_OFFLOAD_FAILED25:%.*]], label [[OMP_OFFLOAD_CONT26:%.*]] 2307 // CHECK3: omp_offload.failed25: 2308 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i32 [[TMP88]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR4]] 2309 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT26]] 2310 // CHECK3: omp_offload.cont26: 2311 // CHECK3-NEXT: br label [[OMP_IF_END28:%.*]] 2312 // CHECK3: omp_if.else27: 2313 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i32 [[TMP88]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR4]] 2314 // CHECK3-NEXT: br label [[OMP_IF_END28]] 2315 // CHECK3: omp_if.end28: 2316 // CHECK3-NEXT: [[TMP148:%.*]] = load i32, i32* [[A]], align 4 2317 // CHECK3-NEXT: [[TMP149:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 2318 // CHECK3-NEXT: call void @llvm.stackrestore(i8* [[TMP149]]) 2319 // CHECK3-NEXT: ret i32 [[TMP148]] 2320 // 2321 // 2322 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97 2323 // CHECK3-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]], i32 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] { 2324 // CHECK3-NEXT: entry: 2325 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 2326 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 2327 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4 2328 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 2329 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]]) 2330 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 2331 // CHECK3-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 2332 // CHECK3-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 2333 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 2334 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 2335 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 2336 // CHECK3-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) 2337 // CHECK3-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 2338 // CHECK3-NEXT: [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 2339 // CHECK3-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 2340 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 2341 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]]) 2342 // CHECK3-NEXT: ret void 2343 // 2344 // 2345 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. 2346 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR3:[0-9]+]] { 2347 // CHECK3-NEXT: entry: 2348 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2349 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2350 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 2351 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2352 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 2353 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2354 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2355 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2356 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2357 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 2358 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2359 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2360 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 2361 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 2362 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 2363 // CHECK3-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 2364 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 2365 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 2366 // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 2367 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 2368 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 2369 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2370 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 2371 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2372 // CHECK3: cond.true: 2373 // CHECK3-NEXT: br label [[COND_END:%.*]] 2374 // CHECK3: cond.false: 2375 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2376 // CHECK3-NEXT: br label [[COND_END]] 2377 // CHECK3: cond.end: 2378 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 2379 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 2380 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 2381 // CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 2382 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2383 // CHECK3: omp.inner.for.cond: 2384 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 2385 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !11 2386 // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 2387 // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2388 // CHECK3: omp.inner.for.body: 2389 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 2390 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 2391 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 2392 // CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11 2393 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2394 // CHECK3: omp.body.continue: 2395 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2396 // CHECK3: omp.inner.for.inc: 2397 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 2398 // CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 2399 // CHECK3-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 2400 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] 2401 // CHECK3: omp.inner.for.end: 2402 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2403 // CHECK3: omp.loop.exit: 2404 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 2405 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 2406 // CHECK3-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 2407 // CHECK3-NEXT: br i1 [[TMP10]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 2408 // CHECK3: .omp.final.then: 2409 // CHECK3-NEXT: store i32 10, i32* [[I]], align 4 2410 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] 2411 // CHECK3: .omp.final.done: 2412 // CHECK3-NEXT: ret void 2413 // 2414 // 2415 // CHECK3-LABEL: define {{[^@]+}}@.omp_task_privates_map. 2416 // CHECK3-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], i16** noalias noundef [[TMP1:%.*]], [3 x i8*]** noalias noundef [[TMP2:%.*]], [3 x i8*]** noalias noundef [[TMP3:%.*]], [3 x i64]** noalias noundef [[TMP4:%.*]]) #[[ATTR5:[0-9]+]] { 2417 // CHECK3-NEXT: entry: 2418 // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 4 2419 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i16**, align 4 2420 // CHECK3-NEXT: [[DOTADDR2:%.*]] = alloca [3 x i8*]**, align 4 2421 // CHECK3-NEXT: [[DOTADDR3:%.*]] = alloca [3 x i8*]**, align 4 2422 // CHECK3-NEXT: [[DOTADDR4:%.*]] = alloca [3 x i64]**, align 4 2423 // CHECK3-NEXT: store %struct..kmp_privates.t* [[TMP0]], %struct..kmp_privates.t** [[DOTADDR]], align 4 2424 // CHECK3-NEXT: store i16** [[TMP1]], i16*** [[DOTADDR1]], align 4 2425 // CHECK3-NEXT: store [3 x i8*]** [[TMP2]], [3 x i8*]*** [[DOTADDR2]], align 4 2426 // CHECK3-NEXT: store [3 x i8*]** [[TMP3]], [3 x i8*]*** [[DOTADDR3]], align 4 2427 // CHECK3-NEXT: store [3 x i64]** [[TMP4]], [3 x i64]*** [[DOTADDR4]], align 4 2428 // CHECK3-NEXT: [[TMP5:%.*]] = load %struct..kmp_privates.t*, %struct..kmp_privates.t** [[DOTADDR]], align 4 2429 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 0 2430 // CHECK3-NEXT: [[TMP7:%.*]] = load [3 x i64]**, [3 x i64]*** [[DOTADDR4]], align 4 2431 // CHECK3-NEXT: store [3 x i64]* [[TMP6]], [3 x i64]** [[TMP7]], align 4 2432 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 1 2433 // CHECK3-NEXT: [[TMP9:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR2]], align 4 2434 // CHECK3-NEXT: store [3 x i8*]* [[TMP8]], [3 x i8*]** [[TMP9]], align 4 2435 // CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 2 2436 // CHECK3-NEXT: [[TMP11:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR3]], align 4 2437 // CHECK3-NEXT: store [3 x i8*]* [[TMP10]], [3 x i8*]** [[TMP11]], align 4 2438 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 3 2439 // CHECK3-NEXT: [[TMP13:%.*]] = load i16**, i16*** [[DOTADDR1]], align 4 2440 // CHECK3-NEXT: store i16* [[TMP12]], i16** [[TMP13]], align 4 2441 // CHECK3-NEXT: ret void 2442 // 2443 // 2444 // CHECK3-LABEL: define {{[^@]+}}@.omp_task_entry. 2445 // CHECK3-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] { 2446 // CHECK3-NEXT: entry: 2447 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 2448 // CHECK3-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 4 2449 // CHECK3-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 4 2450 // CHECK3-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 4 2451 // CHECK3-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 4 2452 // CHECK3-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 4 2453 // CHECK3-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca i16*, align 4 2454 // CHECK3-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca [3 x i8*]*, align 4 2455 // CHECK3-NEXT: [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca [3 x i8*]*, align 4 2456 // CHECK3-NEXT: [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca [3 x i64]*, align 4 2457 // CHECK3-NEXT: [[AA_CASTED_I:%.*]] = alloca i32, align 4 2458 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__CASTED_I:%.*]] = alloca i32, align 4 2459 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__CASTED4_I:%.*]] = alloca i32, align 4 2460 // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 2461 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 4 2462 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 2463 // CHECK3-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4 2464 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 2465 // CHECK3-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4 2466 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0 2467 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 2468 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 2469 // CHECK3-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 4 2470 // CHECK3-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon* 2471 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1 2472 // CHECK3-NEXT: [[TMP10:%.*]] = bitcast %struct..kmp_privates.t* [[TMP9]] to i8* 2473 // CHECK3-NEXT: [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8* 2474 // CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]]) 2475 // CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META21:![0-9]+]]) 2476 // CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META23:![0-9]+]]) 2477 // CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META25:![0-9]+]]) 2478 // CHECK3-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !27 2479 // CHECK3-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 4, !noalias !27 2480 // CHECK3-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !27 2481 // CHECK3-NEXT: store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* @.omp_task_privates_map. to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !27 2482 // CHECK3-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 4, !noalias !27 2483 // CHECK3-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !27 2484 // CHECK3-NEXT: [[TMP12:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !27 2485 // CHECK3-NEXT: [[TMP13:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !27 2486 // CHECK3-NEXT: [[TMP14:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !27 2487 // CHECK3-NEXT: [[TMP15:%.*]] = bitcast void (i8*, ...)* [[TMP13]] to void (i8*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* 2488 // CHECK3-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR4]] 2489 // CHECK3-NEXT: [[TMP16:%.*]] = load i16*, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 4, !noalias !27 2490 // CHECK3-NEXT: [[TMP17:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 4, !noalias !27 2491 // CHECK3-NEXT: [[TMP18:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 4, !noalias !27 2492 // CHECK3-NEXT: [[TMP19:%.*]] = load [3 x i64]*, [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 4, !noalias !27 2493 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP17]], i32 0, i32 0 2494 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP18]], i32 0, i32 0 2495 // CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[TMP19]], i32 0, i32 0 2496 // CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP12]], i32 0, i32 1 2497 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[TMP12]], i32 0, i32 2 2498 // CHECK3-NEXT: [[TMP25:%.*]] = load i32, i32* [[TMP23]], align 4 2499 // CHECK3-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) #[[ATTR4]] 2500 // CHECK3-NEXT: [[TMP26:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 [[TMP25]], i32 1, i32 0, i8* null, i32 0, i8* null) #[[ATTR4]] 2501 // CHECK3-NEXT: [[TMP27:%.*]] = icmp ne i32 [[TMP26]], 0 2502 // CHECK3-NEXT: br i1 [[TMP27]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]] 2503 // CHECK3: omp_offload.failed.i: 2504 // CHECK3-NEXT: [[TMP28:%.*]] = load i16, i16* [[TMP16]], align 2 2505 // CHECK3-NEXT: [[CONV_I:%.*]] = bitcast i32* [[AA_CASTED_I]] to i16* 2506 // CHECK3-NEXT: store i16 [[TMP28]], i16* [[CONV_I]], align 2, !noalias !27 2507 // CHECK3-NEXT: [[TMP29:%.*]] = load i32, i32* [[AA_CASTED_I]], align 4, !noalias !27 2508 // CHECK3-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP23]], align 4 2509 // CHECK3-NEXT: store i32 [[TMP30]], i32* [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias !27 2510 // CHECK3-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias !27 2511 // CHECK3-NEXT: [[TMP32:%.*]] = load i32, i32* [[TMP24]], align 4 2512 // CHECK3-NEXT: store i32 [[TMP32]], i32* [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias !27 2513 // CHECK3-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias !27 2514 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97(i32 [[TMP29]], i32 [[TMP31]], i32 [[TMP33]]) #[[ATTR4]] 2515 // CHECK3-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]] 2516 // CHECK3: .omp_outlined..1.exit: 2517 // CHECK3-NEXT: ret i32 0 2518 // 2519 // 2520 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104 2521 // CHECK3-SAME: (i32 noundef [[A:%.*]]) #[[ATTR3]] { 2522 // CHECK3-NEXT: entry: 2523 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2524 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 2525 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 2526 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 2527 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 2528 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 2529 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]]) 2530 // CHECK3-NEXT: ret void 2531 // 2532 // 2533 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..2 2534 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]]) #[[ATTR3]] { 2535 // CHECK3-NEXT: entry: 2536 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2537 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2538 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2539 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2540 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 2541 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2542 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2543 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2544 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2545 // CHECK3-NEXT: [[A1:%.*]] = alloca i32, align 4 2546 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2547 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2548 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 2549 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 2550 // CHECK3-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 2551 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 2552 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 2553 // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 2554 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 2555 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 2556 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2557 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 2558 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2559 // CHECK3: cond.true: 2560 // CHECK3-NEXT: br label [[COND_END:%.*]] 2561 // CHECK3: cond.false: 2562 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2563 // CHECK3-NEXT: br label [[COND_END]] 2564 // CHECK3: cond.end: 2565 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 2566 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 2567 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 2568 // CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 2569 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2570 // CHECK3: omp.inner.for.cond: 2571 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2572 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2573 // CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 2574 // CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2575 // CHECK3: omp.inner.for.body: 2576 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2577 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 2578 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 2579 // CHECK3-NEXT: store i32 [[ADD]], i32* [[A1]], align 4 2580 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[A1]], align 4 2581 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1 2582 // CHECK3-NEXT: store i32 [[ADD3]], i32* [[A1]], align 4 2583 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2584 // CHECK3: omp.body.continue: 2585 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2586 // CHECK3: omp.inner.for.inc: 2587 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2588 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP9]], 1 2589 // CHECK3-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 2590 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]] 2591 // CHECK3: omp.inner.for.end: 2592 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2593 // CHECK3: omp.loop.exit: 2594 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 2595 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 2596 // CHECK3-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0 2597 // CHECK3-NEXT: br i1 [[TMP11]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 2598 // CHECK3: .omp.final.then: 2599 // CHECK3-NEXT: store i32 10, i32* [[A_ADDR]], align 4 2600 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] 2601 // CHECK3: .omp.final.done: 2602 // CHECK3-NEXT: ret void 2603 // 2604 // 2605 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 2606 // CHECK3-SAME: (i32 noundef [[AA:%.*]]) #[[ATTR2]] { 2607 // CHECK3-NEXT: entry: 2608 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 2609 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 2610 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 2611 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 2612 // CHECK3-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 2613 // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 2614 // CHECK3-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 2615 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 2616 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP1]]) 2617 // CHECK3-NEXT: ret void 2618 // 2619 // 2620 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..3 2621 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR3]] { 2622 // CHECK3-NEXT: entry: 2623 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2624 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2625 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 2626 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2627 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 2628 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2629 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2630 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2631 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2632 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 2633 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2634 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2635 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 2636 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 2637 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 2638 // CHECK3-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 2639 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 2640 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 2641 // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 2642 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 2643 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 2644 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2645 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 2646 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2647 // CHECK3: cond.true: 2648 // CHECK3-NEXT: br label [[COND_END:%.*]] 2649 // CHECK3: cond.false: 2650 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2651 // CHECK3-NEXT: br label [[COND_END]] 2652 // CHECK3: cond.end: 2653 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 2654 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 2655 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 2656 // CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 2657 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2658 // CHECK3: omp.inner.for.cond: 2659 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30 2660 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !30 2661 // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 2662 // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2663 // CHECK3: omp.inner.for.body: 2664 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30 2665 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 2666 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 2667 // CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !30 2668 // CHECK3-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !30 2669 // CHECK3-NEXT: [[CONV2:%.*]] = sext i16 [[TMP8]] to i32 2670 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 2671 // CHECK3-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 2672 // CHECK3-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2, !llvm.access.group !30 2673 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2674 // CHECK3: omp.body.continue: 2675 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2676 // CHECK3: omp.inner.for.inc: 2677 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30 2678 // CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP9]], 1 2679 // CHECK3-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30 2680 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP31:![0-9]+]] 2681 // CHECK3: omp.inner.for.end: 2682 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2683 // CHECK3: omp.loop.exit: 2684 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 2685 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 2686 // CHECK3-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0 2687 // CHECK3-NEXT: br i1 [[TMP11]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 2688 // CHECK3: .omp.final.then: 2689 // CHECK3-NEXT: store i32 10, i32* [[I]], align 4 2690 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] 2691 // CHECK3: .omp.final.done: 2692 // CHECK3-NEXT: ret void 2693 // 2694 // 2695 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118 2696 // CHECK3-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { 2697 // CHECK3-NEXT: entry: 2698 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2699 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 2700 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 2701 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 2702 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 2703 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 2704 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 2705 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 2706 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 2707 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 2708 // CHECK3-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 2709 // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 2710 // CHECK3-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 2711 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 2712 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) 2713 // CHECK3-NEXT: ret void 2714 // 2715 // 2716 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..6 2717 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR3]] { 2718 // CHECK3-NEXT: entry: 2719 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2720 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2721 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2722 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 2723 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2724 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 2725 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2726 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2727 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2728 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2729 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 2730 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2731 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2732 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 2733 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 2734 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 2735 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 2736 // CHECK3-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 2737 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 2738 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 2739 // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 2740 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 2741 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 2742 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2743 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 2744 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2745 // CHECK3: cond.true: 2746 // CHECK3-NEXT: br label [[COND_END:%.*]] 2747 // CHECK3: cond.false: 2748 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2749 // CHECK3-NEXT: br label [[COND_END]] 2750 // CHECK3: cond.end: 2751 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 2752 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 2753 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 2754 // CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 2755 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2756 // CHECK3: omp.inner.for.cond: 2757 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33 2758 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !33 2759 // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 2760 // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2761 // CHECK3: omp.inner.for.body: 2762 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33 2763 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 2764 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 2765 // CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !33 2766 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !33 2767 // CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 2768 // CHECK3-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4, !llvm.access.group !33 2769 // CHECK3-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !33 2770 // CHECK3-NEXT: [[CONV3:%.*]] = sext i16 [[TMP9]] to i32 2771 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 2772 // CHECK3-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 2773 // CHECK3-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2, !llvm.access.group !33 2774 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2775 // CHECK3: omp.body.continue: 2776 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2777 // CHECK3: omp.inner.for.inc: 2778 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33 2779 // CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP10]], 1 2780 // CHECK3-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33 2781 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP34:![0-9]+]] 2782 // CHECK3: omp.inner.for.end: 2783 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2784 // CHECK3: omp.loop.exit: 2785 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 2786 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 2787 // CHECK3-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 2788 // CHECK3-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 2789 // CHECK3: .omp.final.then: 2790 // CHECK3-NEXT: store i32 10, i32* [[I]], align 4 2791 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] 2792 // CHECK3: .omp.final.done: 2793 // CHECK3-NEXT: ret void 2794 // 2795 // 2796 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142 2797 // CHECK3-SAME: (i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] { 2798 // CHECK3-NEXT: entry: 2799 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2800 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 2801 // CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 2802 // CHECK3-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 2803 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 2804 // CHECK3-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 2805 // CHECK3-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 2806 // CHECK3-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 2807 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 2808 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 2809 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 2810 // CHECK3-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 2811 // CHECK3-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 2812 // CHECK3-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 2813 // CHECK3-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 2814 // CHECK3-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 2815 // CHECK3-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 2816 // CHECK3-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 2817 // CHECK3-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 2818 // CHECK3-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 2819 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 2820 // CHECK3-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 2821 // CHECK3-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 2822 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 2823 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 2824 // CHECK3-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 2825 // CHECK3-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 2826 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 2827 // CHECK3-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4 2828 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4 2829 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) 2830 // CHECK3-NEXT: ret void 2831 // 2832 // 2833 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..9 2834 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR3]] { 2835 // CHECK3-NEXT: entry: 2836 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2837 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2838 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2839 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 2840 // CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 2841 // CHECK3-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 2842 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 2843 // CHECK3-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 2844 // CHECK3-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 2845 // CHECK3-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 2846 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 2847 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2848 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 2849 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2850 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2851 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2852 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2853 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 2854 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2855 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2856 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 2857 // CHECK3-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 2858 // CHECK3-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 2859 // CHECK3-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 2860 // CHECK3-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 2861 // CHECK3-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 2862 // CHECK3-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 2863 // CHECK3-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 2864 // CHECK3-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 2865 // CHECK3-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 2866 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 2867 // CHECK3-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 2868 // CHECK3-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 2869 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 2870 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 2871 // CHECK3-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 2872 // CHECK3-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 2873 // CHECK3-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 0 2874 // CHECK3-NEXT: call void @llvm.assume(i1 true) [ "align"(float* [[ARRAYDECAY]], i32 16) ] 2875 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 2876 // CHECK3-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 2877 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 2878 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 2879 // CHECK3-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 2880 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 2881 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 2882 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2883 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP10]], 9 2884 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2885 // CHECK3: cond.true: 2886 // CHECK3-NEXT: br label [[COND_END:%.*]] 2887 // CHECK3: cond.false: 2888 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2889 // CHECK3-NEXT: br label [[COND_END]] 2890 // CHECK3: cond.end: 2891 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] 2892 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 2893 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 2894 // CHECK3-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 2895 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2896 // CHECK3: omp.inner.for.cond: 2897 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36 2898 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !36 2899 // CHECK3-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] 2900 // CHECK3-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2901 // CHECK3: omp.inner.for.body: 2902 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36 2903 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 2904 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 2905 // CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !36 2906 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !36 2907 // CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP16]], 1 2908 // CHECK3-NEXT: store i32 [[ADD6]], i32* [[A_ADDR]], align 4, !llvm.access.group !36 2909 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2 2910 // CHECK3-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !36 2911 // CHECK3-NEXT: [[CONV:%.*]] = fpext float [[TMP17]] to double 2912 // CHECK3-NEXT: [[ADD7:%.*]] = fadd double [[CONV]], 1.000000e+00 2913 // CHECK3-NEXT: [[CONV8:%.*]] = fptrunc double [[ADD7]] to float 2914 // CHECK3-NEXT: store float [[CONV8]], float* [[ARRAYIDX]], align 4, !llvm.access.group !36 2915 // CHECK3-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3 2916 // CHECK3-NEXT: [[TMP18:%.*]] = load float, float* [[ARRAYIDX9]], align 4, !llvm.access.group !36 2917 // CHECK3-NEXT: [[CONV10:%.*]] = fpext float [[TMP18]] to double 2918 // CHECK3-NEXT: [[ADD11:%.*]] = fadd double [[CONV10]], 1.000000e+00 2919 // CHECK3-NEXT: [[CONV12:%.*]] = fptrunc double [[ADD11]] to float 2920 // CHECK3-NEXT: store float [[CONV12]], float* [[ARRAYIDX9]], align 4, !llvm.access.group !36 2921 // CHECK3-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1 2922 // CHECK3-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX13]], i32 0, i32 2 2923 // CHECK3-NEXT: [[TMP19:%.*]] = load double, double* [[ARRAYIDX14]], align 8, !llvm.access.group !36 2924 // CHECK3-NEXT: [[ADD15:%.*]] = fadd double [[TMP19]], 1.000000e+00 2925 // CHECK3-NEXT: store double [[ADD15]], double* [[ARRAYIDX14]], align 8, !llvm.access.group !36 2926 // CHECK3-NEXT: [[TMP20:%.*]] = mul nsw i32 1, [[TMP5]] 2927 // CHECK3-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP20]] 2928 // CHECK3-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX16]], i32 3 2929 // CHECK3-NEXT: [[TMP21:%.*]] = load double, double* [[ARRAYIDX17]], align 8, !llvm.access.group !36 2930 // CHECK3-NEXT: [[ADD18:%.*]] = fadd double [[TMP21]], 1.000000e+00 2931 // CHECK3-NEXT: store double [[ADD18]], double* [[ARRAYIDX17]], align 8, !llvm.access.group !36 2932 // CHECK3-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 2933 // CHECK3-NEXT: [[TMP22:%.*]] = load i64, i64* [[X]], align 4, !llvm.access.group !36 2934 // CHECK3-NEXT: [[ADD19:%.*]] = add nsw i64 [[TMP22]], 1 2935 // CHECK3-NEXT: store i64 [[ADD19]], i64* [[X]], align 4, !llvm.access.group !36 2936 // CHECK3-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 2937 // CHECK3-NEXT: [[TMP23:%.*]] = load i8, i8* [[Y]], align 4, !llvm.access.group !36 2938 // CHECK3-NEXT: [[CONV20:%.*]] = sext i8 [[TMP23]] to i32 2939 // CHECK3-NEXT: [[ADD21:%.*]] = add nsw i32 [[CONV20]], 1 2940 // CHECK3-NEXT: [[CONV22:%.*]] = trunc i32 [[ADD21]] to i8 2941 // CHECK3-NEXT: store i8 [[CONV22]], i8* [[Y]], align 4, !llvm.access.group !36 2942 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2943 // CHECK3: omp.body.continue: 2944 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2945 // CHECK3: omp.inner.for.inc: 2946 // CHECK3-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36 2947 // CHECK3-NEXT: [[ADD23:%.*]] = add nsw i32 [[TMP24]], 1 2948 // CHECK3-NEXT: store i32 [[ADD23]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36 2949 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP37:![0-9]+]] 2950 // CHECK3: omp.inner.for.end: 2951 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2952 // CHECK3: omp.loop.exit: 2953 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]]) 2954 // CHECK3-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 2955 // CHECK3-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0 2956 // CHECK3-NEXT: br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 2957 // CHECK3: .omp.final.then: 2958 // CHECK3-NEXT: store i32 10, i32* [[I]], align 4 2959 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] 2960 // CHECK3: .omp.final.done: 2961 // CHECK3-NEXT: ret void 2962 // 2963 // 2964 // CHECK3-LABEL: define {{[^@]+}}@_Z3bari 2965 // CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { 2966 // CHECK3-NEXT: entry: 2967 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 2968 // CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4 2969 // CHECK3-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 2970 // CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 2971 // CHECK3-NEXT: store i32 0, i32* [[A]], align 4 2972 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 2973 // CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]]) 2974 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 2975 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 2976 // CHECK3-NEXT: store i32 [[ADD]], i32* [[A]], align 4 2977 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 2978 // CHECK3-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP2]]) 2979 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 2980 // CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 2981 // CHECK3-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 2982 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 2983 // CHECK3-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]]) 2984 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 2985 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 2986 // CHECK3-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 2987 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 2988 // CHECK3-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]]) 2989 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 2990 // CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] 2991 // CHECK3-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 2992 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 2993 // CHECK3-NEXT: ret i32 [[TMP8]] 2994 // 2995 // 2996 // CHECK3-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 2997 // CHECK3-SAME: (%struct.S1* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 { 2998 // CHECK3-NEXT: entry: 2999 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 3000 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 3001 // CHECK3-NEXT: [[B:%.*]] = alloca i32, align 4 3002 // CHECK3-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 3003 // CHECK3-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 3004 // CHECK3-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 3005 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4 3006 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4 3007 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4 3008 // CHECK3-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 4 3009 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 3010 // CHECK3-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 3011 // CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 3012 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 3013 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 3014 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 3015 // CHECK3-NEXT: store i32 [[ADD]], i32* [[B]], align 4 3016 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 3017 // CHECK3-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() 3018 // CHECK3-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 3019 // CHECK3-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] 3020 // CHECK3-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 3021 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 3022 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[B]], align 4 3023 // CHECK3-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 3024 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 3025 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 3026 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 60 3027 // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 3028 // CHECK3: omp_if.then: 3029 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 3030 // CHECK3-NEXT: [[TMP7:%.*]] = mul nuw i32 2, [[TMP1]] 3031 // CHECK3-NEXT: [[TMP8:%.*]] = mul nuw i32 [[TMP7]], 2 3032 // CHECK3-NEXT: [[TMP9:%.*]] = sext i32 [[TMP8]] to i64 3033 // CHECK3-NEXT: [[TMP10:%.*]] = bitcast [5 x i64]* [[DOTOFFLOAD_SIZES]] to i8* 3034 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP10]], i8* align 4 bitcast ([5 x i64]* @.offload_sizes.13 to i8*), i32 40, i1 false) 3035 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3036 // CHECK3-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to %struct.S1** 3037 // CHECK3-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP12]], align 4 3038 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3039 // CHECK3-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to double** 3040 // CHECK3-NEXT: store double* [[A]], double** [[TMP14]], align 4 3041 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 3042 // CHECK3-NEXT: store i8* null, i8** [[TMP15]], align 4 3043 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 3044 // CHECK3-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32* 3045 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[TMP17]], align 4 3046 // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 3047 // CHECK3-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32* 3048 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[TMP19]], align 4 3049 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 3050 // CHECK3-NEXT: store i8* null, i8** [[TMP20]], align 4 3051 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 3052 // CHECK3-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i32* 3053 // CHECK3-NEXT: store i32 2, i32* [[TMP22]], align 4 3054 // CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 3055 // CHECK3-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i32* 3056 // CHECK3-NEXT: store i32 2, i32* [[TMP24]], align 4 3057 // CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 3058 // CHECK3-NEXT: store i8* null, i8** [[TMP25]], align 4 3059 // CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 3060 // CHECK3-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i32* 3061 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP27]], align 4 3062 // CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 3063 // CHECK3-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i32* 3064 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP29]], align 4 3065 // CHECK3-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 3066 // CHECK3-NEXT: store i8* null, i8** [[TMP30]], align 4 3067 // CHECK3-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 3068 // CHECK3-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i16** 3069 // CHECK3-NEXT: store i16* [[VLA]], i16** [[TMP32]], align 4 3070 // CHECK3-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 3071 // CHECK3-NEXT: [[TMP34:%.*]] = bitcast i8** [[TMP33]] to i16** 3072 // CHECK3-NEXT: store i16* [[VLA]], i16** [[TMP34]], align 4 3073 // CHECK3-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 3074 // CHECK3-NEXT: store i64 [[TMP9]], i64* [[TMP35]], align 4 3075 // CHECK3-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 3076 // CHECK3-NEXT: store i8* null, i8** [[TMP36]], align 4 3077 // CHECK3-NEXT: [[TMP37:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3078 // CHECK3-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3079 // CHECK3-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 3080 // CHECK3-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) 3081 // CHECK3-NEXT: [[TMP40:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215.region_id, i32 5, i8** [[TMP37]], i8** [[TMP38]], i64* [[TMP39]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.14, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1) 3082 // CHECK3-NEXT: [[TMP41:%.*]] = icmp ne i32 [[TMP40]], 0 3083 // CHECK3-NEXT: br i1 [[TMP41]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 3084 // CHECK3: omp_offload.failed: 3085 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR4]] 3086 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 3087 // CHECK3: omp_offload.cont: 3088 // CHECK3-NEXT: br label [[OMP_IF_END:%.*]] 3089 // CHECK3: omp_if.else: 3090 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR4]] 3091 // CHECK3-NEXT: br label [[OMP_IF_END]] 3092 // CHECK3: omp_if.end: 3093 // CHECK3-NEXT: [[TMP42:%.*]] = mul nsw i32 1, [[TMP1]] 3094 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP42]] 3095 // CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 3096 // CHECK3-NEXT: [[TMP43:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2 3097 // CHECK3-NEXT: [[CONV:%.*]] = sext i16 [[TMP43]] to i32 3098 // CHECK3-NEXT: [[TMP44:%.*]] = load i32, i32* [[B]], align 4 3099 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP44]] 3100 // CHECK3-NEXT: [[TMP45:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 3101 // CHECK3-NEXT: call void @llvm.stackrestore(i8* [[TMP45]]) 3102 // CHECK3-NEXT: ret i32 [[ADD3]] 3103 // 3104 // 3105 // CHECK3-LABEL: define {{[^@]+}}@_ZL7fstatici 3106 // CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { 3107 // CHECK3-NEXT: entry: 3108 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 3109 // CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4 3110 // CHECK3-NEXT: [[AA:%.*]] = alloca i16, align 2 3111 // CHECK3-NEXT: [[AAA:%.*]] = alloca i8, align 1 3112 // CHECK3-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 3113 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 3114 // CHECK3-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 3115 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 3116 // CHECK3-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 3117 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4 3118 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4 3119 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4 3120 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 3121 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 3122 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 3123 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4 3124 // CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 3125 // CHECK3-NEXT: store i32 0, i32* [[A]], align 4 3126 // CHECK3-NEXT: store i16 0, i16* [[AA]], align 2 3127 // CHECK3-NEXT: store i8 0, i8* [[AAA]], align 1 3128 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 3129 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 3130 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 3131 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 3132 // CHECK3-NEXT: store i32 [[TMP2]], i32* [[N_CASTED]], align 4 3133 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_CASTED]], align 4 3134 // CHECK3-NEXT: [[TMP4:%.*]] = load i16, i16* [[AA]], align 2 3135 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 3136 // CHECK3-NEXT: store i16 [[TMP4]], i16* [[CONV]], align 2 3137 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[AA_CASTED]], align 4 3138 // CHECK3-NEXT: [[TMP6:%.*]] = load i8, i8* [[AAA]], align 1 3139 // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* 3140 // CHECK3-NEXT: store i8 [[TMP6]], i8* [[CONV1]], align 1 3141 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 3142 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[N_ADDR]], align 4 3143 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP8]], 50 3144 // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 3145 // CHECK3: omp_if.then: 3146 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3147 // CHECK3-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* 3148 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP10]], align 4 3149 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3150 // CHECK3-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32* 3151 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP12]], align 4 3152 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 3153 // CHECK3-NEXT: store i8* null, i8** [[TMP13]], align 4 3154 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 3155 // CHECK3-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32* 3156 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP15]], align 4 3157 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 3158 // CHECK3-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32* 3159 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP17]], align 4 3160 // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 3161 // CHECK3-NEXT: store i8* null, i8** [[TMP18]], align 4 3162 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 3163 // CHECK3-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32* 3164 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[TMP20]], align 4 3165 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 3166 // CHECK3-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i32* 3167 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[TMP22]], align 4 3168 // CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 3169 // CHECK3-NEXT: store i8* null, i8** [[TMP23]], align 4 3170 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 3171 // CHECK3-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i32* 3172 // CHECK3-NEXT: store i32 [[TMP7]], i32* [[TMP25]], align 4 3173 // CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 3174 // CHECK3-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i32* 3175 // CHECK3-NEXT: store i32 [[TMP7]], i32* [[TMP27]], align 4 3176 // CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 3177 // CHECK3-NEXT: store i8* null, i8** [[TMP28]], align 4 3178 // CHECK3-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 3179 // CHECK3-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to [10 x i32]** 3180 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP30]], align 4 3181 // CHECK3-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 3182 // CHECK3-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to [10 x i32]** 3183 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP32]], align 4 3184 // CHECK3-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 3185 // CHECK3-NEXT: store i8* null, i8** [[TMP33]], align 4 3186 // CHECK3-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3187 // CHECK3-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3188 // CHECK3-NEXT: [[TMP36:%.*]] = load i32, i32* [[A]], align 4 3189 // CHECK3-NEXT: store i32 [[TMP36]], i32* [[DOTCAPTURE_EXPR_]], align 4 3190 // CHECK3-NEXT: [[TMP37:%.*]] = load i32, i32* [[N_ADDR]], align 4 3191 // CHECK3-NEXT: store i32 [[TMP37]], i32* [[DOTCAPTURE_EXPR_2]], align 4 3192 // CHECK3-NEXT: [[TMP38:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 3193 // CHECK3-NEXT: [[TMP39:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 3194 // CHECK3-NEXT: [[SUB:%.*]] = sub i32 [[TMP38]], [[TMP39]] 3195 // CHECK3-NEXT: [[SUB4:%.*]] = sub i32 [[SUB]], 1 3196 // CHECK3-NEXT: [[ADD:%.*]] = add i32 [[SUB4]], 1 3197 // CHECK3-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 3198 // CHECK3-NEXT: [[SUB5:%.*]] = sub i32 [[DIV]], 1 3199 // CHECK3-NEXT: store i32 [[SUB5]], i32* [[DOTCAPTURE_EXPR_3]], align 4 3200 // CHECK3-NEXT: [[TMP40:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 3201 // CHECK3-NEXT: [[ADD6:%.*]] = add i32 [[TMP40]], 1 3202 // CHECK3-NEXT: [[TMP41:%.*]] = zext i32 [[ADD6]] to i64 3203 // CHECK3-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 [[TMP41]]) 3204 // CHECK3-NEXT: [[TMP42:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197.region_id, i32 5, i8** [[TMP34]], i8** [[TMP35]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes.16, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.17, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1) 3205 // CHECK3-NEXT: [[TMP43:%.*]] = icmp ne i32 [[TMP42]], 0 3206 // CHECK3-NEXT: br i1 [[TMP43]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 3207 // CHECK3: omp_offload.failed: 3208 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], i32 [[TMP7]], [10 x i32]* [[B]]) #[[ATTR4]] 3209 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 3210 // CHECK3: omp_offload.cont: 3211 // CHECK3-NEXT: br label [[OMP_IF_END:%.*]] 3212 // CHECK3: omp_if.else: 3213 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], i32 [[TMP7]], [10 x i32]* [[B]]) #[[ATTR4]] 3214 // CHECK3-NEXT: br label [[OMP_IF_END]] 3215 // CHECK3: omp_if.end: 3216 // CHECK3-NEXT: [[TMP44:%.*]] = load i32, i32* [[A]], align 4 3217 // CHECK3-NEXT: ret i32 [[TMP44]] 3218 // 3219 // 3220 // CHECK3-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 3221 // CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat { 3222 // CHECK3-NEXT: entry: 3223 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 3224 // CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4 3225 // CHECK3-NEXT: [[AA:%.*]] = alloca i16, align 2 3226 // CHECK3-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 3227 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 3228 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 3229 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 3230 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 3231 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 3232 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 3233 // CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 3234 // CHECK3-NEXT: store i32 0, i32* [[A]], align 4 3235 // CHECK3-NEXT: store i16 0, i16* [[AA]], align 2 3236 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 3237 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 3238 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 3239 // CHECK3-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 3240 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 3241 // CHECK3-NEXT: store i16 [[TMP2]], i16* [[CONV]], align 2 3242 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 3243 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 3244 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40 3245 // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 3246 // CHECK3: omp_if.then: 3247 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3248 // CHECK3-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i32* 3249 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP6]], align 4 3250 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3251 // CHECK3-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* 3252 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4 3253 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 3254 // CHECK3-NEXT: store i8* null, i8** [[TMP9]], align 4 3255 // CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 3256 // CHECK3-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i32* 3257 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP11]], align 4 3258 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 3259 // CHECK3-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* 3260 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4 3261 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 3262 // CHECK3-NEXT: store i8* null, i8** [[TMP14]], align 4 3263 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 3264 // CHECK3-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]** 3265 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 4 3266 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 3267 // CHECK3-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]** 3268 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 4 3269 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 3270 // CHECK3-NEXT: store i8* null, i8** [[TMP19]], align 4 3271 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3272 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3273 // CHECK3-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) 3274 // CHECK3-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.19, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.20, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1) 3275 // CHECK3-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 3276 // CHECK3-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 3277 // CHECK3: omp_offload.failed: 3278 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]] 3279 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 3280 // CHECK3: omp_offload.cont: 3281 // CHECK3-NEXT: br label [[OMP_IF_END:%.*]] 3282 // CHECK3: omp_if.else: 3283 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]] 3284 // CHECK3-NEXT: br label [[OMP_IF_END]] 3285 // CHECK3: omp_if.end: 3286 // CHECK3-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4 3287 // CHECK3-NEXT: ret i32 [[TMP24]] 3288 // 3289 // 3290 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215 3291 // CHECK3-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { 3292 // CHECK3-NEXT: entry: 3293 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 3294 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 3295 // CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 3296 // CHECK3-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 3297 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 3298 // CHECK3-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 3299 // CHECK3-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 3300 // CHECK3-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 3301 // CHECK3-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 3302 // CHECK3-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 3303 // CHECK3-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 3304 // CHECK3-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 3305 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 3306 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 3307 // CHECK3-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 3308 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 3309 // CHECK3-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 3310 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 3311 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..12 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]]) 3312 // CHECK3-NEXT: ret void 3313 // 3314 // 3315 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..12 3316 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] { 3317 // CHECK3-NEXT: entry: 3318 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 3319 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 3320 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 3321 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 3322 // CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 3323 // CHECK3-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 3324 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 3325 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 3326 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 3327 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 3328 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 3329 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 3330 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 3331 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 3332 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 3333 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 3334 // CHECK3-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 3335 // CHECK3-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 3336 // CHECK3-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 3337 // CHECK3-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 3338 // CHECK3-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 3339 // CHECK3-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 3340 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 3341 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 3342 // CHECK3-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 3343 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 3344 // CHECK3-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 3345 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 3346 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 3347 // CHECK3-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 3348 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 3349 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 3350 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 3351 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 9 3352 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 3353 // CHECK3: cond.true: 3354 // CHECK3-NEXT: br label [[COND_END:%.*]] 3355 // CHECK3: cond.false: 3356 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 3357 // CHECK3-NEXT: br label [[COND_END]] 3358 // CHECK3: cond.end: 3359 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 3360 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 3361 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 3362 // CHECK3-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 3363 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 3364 // CHECK3: omp.inner.for.cond: 3365 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39 3366 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !39 3367 // CHECK3-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 3368 // CHECK3-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 3369 // CHECK3: omp.inner.for.body: 3370 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39 3371 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 3372 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 3373 // CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !39 3374 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[B_ADDR]], align 4, !llvm.access.group !39 3375 // CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP12]] to double 3376 // CHECK3-NEXT: [[ADD4:%.*]] = fadd double [[CONV]], 1.500000e+00 3377 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 3378 // CHECK3-NEXT: store double [[ADD4]], double* [[A]], align 4, !llvm.access.group !39 3379 // CHECK3-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 3380 // CHECK3-NEXT: [[TMP13:%.*]] = load double, double* [[A5]], align 4, !llvm.access.group !39 3381 // CHECK3-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 3382 // CHECK3-NEXT: store double [[INC]], double* [[A5]], align 4, !llvm.access.group !39 3383 // CHECK3-NEXT: [[CONV6:%.*]] = fptosi double [[INC]] to i16 3384 // CHECK3-NEXT: [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]] 3385 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP14]] 3386 // CHECK3-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 3387 // CHECK3-NEXT: store i16 [[CONV6]], i16* [[ARRAYIDX7]], align 2, !llvm.access.group !39 3388 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 3389 // CHECK3: omp.body.continue: 3390 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 3391 // CHECK3: omp.inner.for.inc: 3392 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39 3393 // CHECK3-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP15]], 1 3394 // CHECK3-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39 3395 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP40:![0-9]+]] 3396 // CHECK3: omp.inner.for.end: 3397 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 3398 // CHECK3: omp.loop.exit: 3399 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 3400 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 3401 // CHECK3-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0 3402 // CHECK3-NEXT: br i1 [[TMP17]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 3403 // CHECK3: .omp.final.then: 3404 // CHECK3-NEXT: store i32 10, i32* [[I]], align 4 3405 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] 3406 // CHECK3: .omp.final.done: 3407 // CHECK3-NEXT: ret void 3408 // 3409 // 3410 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197 3411 // CHECK3-SAME: (i32 noundef [[A:%.*]], i32 noundef [[N:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 3412 // CHECK3-NEXT: entry: 3413 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3414 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 3415 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 3416 // CHECK3-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 3417 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 3418 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 3419 // CHECK3-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 3420 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 3421 // CHECK3-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 3422 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 3423 // CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 3424 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 3425 // CHECK3-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 3426 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 3427 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 3428 // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 3429 // CHECK3-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 3430 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 3431 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 3432 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 3433 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 3434 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[N_CASTED]], align 4 3435 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_CASTED]], align 4 3436 // CHECK3-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 2 3437 // CHECK3-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 3438 // CHECK3-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2 3439 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[AA_CASTED]], align 4 3440 // CHECK3-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV1]], align 1 3441 // CHECK3-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* 3442 // CHECK3-NEXT: store i8 [[TMP7]], i8* [[CONV3]], align 1 3443 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 3444 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, [10 x i32]*)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP8]], [10 x i32]* [[TMP0]]) 3445 // CHECK3-NEXT: ret void 3446 // 3447 // 3448 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..15 3449 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[N:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { 3450 // CHECK3-NEXT: entry: 3451 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 3452 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 3453 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3454 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 3455 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 3456 // CHECK3-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 3457 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 3458 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 3459 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 3460 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 3461 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 3462 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4 3463 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 3464 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 3465 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 3466 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 3467 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 3468 // CHECK3-NEXT: [[I6:%.*]] = alloca i32, align 4 3469 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 3470 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 3471 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 3472 // CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 3473 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 3474 // CHECK3-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 3475 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 3476 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 3477 // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 3478 // CHECK3-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 3479 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 3480 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 3481 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 3482 // CHECK3-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4 3483 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 3484 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 3485 // CHECK3-NEXT: [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]] 3486 // CHECK3-NEXT: [[SUB4:%.*]] = sub i32 [[SUB]], 1 3487 // CHECK3-NEXT: [[ADD:%.*]] = add i32 [[SUB4]], 1 3488 // CHECK3-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 3489 // CHECK3-NEXT: [[SUB5:%.*]] = sub i32 [[DIV]], 1 3490 // CHECK3-NEXT: store i32 [[SUB5]], i32* [[DOTCAPTURE_EXPR_3]], align 4 3491 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 3492 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[I]], align 4 3493 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 3494 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 3495 // CHECK3-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]] 3496 // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] 3497 // CHECK3: omp.precond.then: 3498 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 3499 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 3500 // CHECK3-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_UB]], align 4 3501 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 3502 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 3503 // CHECK3-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 3504 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 3505 // CHECK3-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 3506 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 3507 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 3508 // CHECK3-NEXT: [[CMP7:%.*]] = icmp ugt i32 [[TMP11]], [[TMP12]] 3509 // CHECK3-NEXT: br i1 [[CMP7]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 3510 // CHECK3: cond.true: 3511 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 3512 // CHECK3-NEXT: br label [[COND_END:%.*]] 3513 // CHECK3: cond.false: 3514 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 3515 // CHECK3-NEXT: br label [[COND_END]] 3516 // CHECK3: cond.end: 3517 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ] 3518 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 3519 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 3520 // CHECK3-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4 3521 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 3522 // CHECK3: omp.inner.for.cond: 3523 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !42 3524 // CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !42 3525 // CHECK3-NEXT: [[ADD8:%.*]] = add i32 [[TMP17]], 1 3526 // CHECK3-NEXT: [[CMP9:%.*]] = icmp ult i32 [[TMP16]], [[ADD8]] 3527 // CHECK3-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 3528 // CHECK3: omp.inner.for.body: 3529 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group !42 3530 // CHECK3-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !42 3531 // CHECK3-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 1 3532 // CHECK3-NEXT: [[ADD10:%.*]] = add i32 [[TMP18]], [[MUL]] 3533 // CHECK3-NEXT: store i32 [[ADD10]], i32* [[I6]], align 4, !llvm.access.group !42 3534 // CHECK3-NEXT: [[TMP20:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !42 3535 // CHECK3-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP20]], 1 3536 // CHECK3-NEXT: store i32 [[ADD11]], i32* [[A_ADDR]], align 4, !llvm.access.group !42 3537 // CHECK3-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !42 3538 // CHECK3-NEXT: [[CONV12:%.*]] = sext i16 [[TMP21]] to i32 3539 // CHECK3-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1 3540 // CHECK3-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16 3541 // CHECK3-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 2, !llvm.access.group !42 3542 // CHECK3-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV1]], align 1, !llvm.access.group !42 3543 // CHECK3-NEXT: [[CONV15:%.*]] = sext i8 [[TMP22]] to i32 3544 // CHECK3-NEXT: [[ADD16:%.*]] = add nsw i32 [[CONV15]], 1 3545 // CHECK3-NEXT: [[CONV17:%.*]] = trunc i32 [[ADD16]] to i8 3546 // CHECK3-NEXT: store i8 [[CONV17]], i8* [[CONV1]], align 1, !llvm.access.group !42 3547 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 3548 // CHECK3-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !42 3549 // CHECK3-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP23]], 1 3550 // CHECK3-NEXT: store i32 [[ADD18]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !42 3551 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 3552 // CHECK3: omp.body.continue: 3553 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 3554 // CHECK3: omp.inner.for.inc: 3555 // CHECK3-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !42 3556 // CHECK3-NEXT: [[ADD19:%.*]] = add i32 [[TMP24]], 1 3557 // CHECK3-NEXT: store i32 [[ADD19]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !42 3558 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP43:![0-9]+]] 3559 // CHECK3: omp.inner.for.end: 3560 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 3561 // CHECK3: omp.loop.exit: 3562 // CHECK3-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 3563 // CHECK3-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 3564 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) 3565 // CHECK3-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 3566 // CHECK3-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0 3567 // CHECK3-NEXT: br i1 [[TMP28]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 3568 // CHECK3: .omp.final.then: 3569 // CHECK3-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 3570 // CHECK3-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 3571 // CHECK3-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 3572 // CHECK3-NEXT: [[SUB20:%.*]] = sub i32 [[TMP30]], [[TMP31]] 3573 // CHECK3-NEXT: [[SUB21:%.*]] = sub i32 [[SUB20]], 1 3574 // CHECK3-NEXT: [[ADD22:%.*]] = add i32 [[SUB21]], 1 3575 // CHECK3-NEXT: [[DIV23:%.*]] = udiv i32 [[ADD22]], 1 3576 // CHECK3-NEXT: [[MUL24:%.*]] = mul i32 [[DIV23]], 1 3577 // CHECK3-NEXT: [[ADD25:%.*]] = add i32 [[TMP29]], [[MUL24]] 3578 // CHECK3-NEXT: store i32 [[ADD25]], i32* [[I6]], align 4 3579 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] 3580 // CHECK3: .omp.final.done: 3581 // CHECK3-NEXT: br label [[OMP_PRECOND_END]] 3582 // CHECK3: omp.precond.end: 3583 // CHECK3-NEXT: ret void 3584 // 3585 // 3586 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180 3587 // CHECK3-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 3588 // CHECK3-NEXT: entry: 3589 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3590 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 3591 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 3592 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 3593 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 3594 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 3595 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 3596 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 3597 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 3598 // CHECK3-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 3599 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 3600 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 3601 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 3602 // CHECK3-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 3603 // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 3604 // CHECK3-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 3605 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 3606 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..18 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) 3607 // CHECK3-NEXT: ret void 3608 // 3609 // 3610 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..18 3611 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { 3612 // CHECK3-NEXT: entry: 3613 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 3614 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 3615 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3616 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 3617 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 3618 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 3619 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 3620 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 3621 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 3622 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 3623 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 3624 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 3625 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 3626 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 3627 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 3628 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 3629 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 3630 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 3631 // CHECK3-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 3632 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 3633 // CHECK3-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 3634 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 3635 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 3636 // CHECK3-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 3637 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 3638 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 3639 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 3640 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 3641 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 3642 // CHECK3: cond.true: 3643 // CHECK3-NEXT: br label [[COND_END:%.*]] 3644 // CHECK3: cond.false: 3645 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 3646 // CHECK3-NEXT: br label [[COND_END]] 3647 // CHECK3: cond.end: 3648 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 3649 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 3650 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 3651 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 3652 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 3653 // CHECK3: omp.inner.for.cond: 3654 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !45 3655 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !45 3656 // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] 3657 // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 3658 // CHECK3: omp.inner.for.body: 3659 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !45 3660 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 3661 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 3662 // CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !45 3663 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !45 3664 // CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 3665 // CHECK3-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4, !llvm.access.group !45 3666 // CHECK3-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !45 3667 // CHECK3-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32 3668 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 3669 // CHECK3-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 3670 // CHECK3-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2, !llvm.access.group !45 3671 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 3672 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !45 3673 // CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1 3674 // CHECK3-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !45 3675 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 3676 // CHECK3: omp.body.continue: 3677 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 3678 // CHECK3: omp.inner.for.inc: 3679 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !45 3680 // CHECK3-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP12]], 1 3681 // CHECK3-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !45 3682 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP46:![0-9]+]] 3683 // CHECK3: omp.inner.for.end: 3684 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 3685 // CHECK3: omp.loop.exit: 3686 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) 3687 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 3688 // CHECK3-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 3689 // CHECK3-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 3690 // CHECK3: .omp.final.then: 3691 // CHECK3-NEXT: store i32 10, i32* [[I]], align 4 3692 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] 3693 // CHECK3: .omp.final.done: 3694 // CHECK3-NEXT: ret void 3695 // 3696 // 3697 // CHECK3-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 3698 // CHECK3-SAME: () #[[ATTR5]] { 3699 // CHECK3-NEXT: entry: 3700 // CHECK3-NEXT: call void @__tgt_register_requires(i64 1) 3701 // CHECK3-NEXT: ret void 3702 // 3703 // 3704 // CHECK5-LABEL: define {{[^@]+}}@_Z3fooi 3705 // CHECK5-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { 3706 // CHECK5-NEXT: entry: 3707 // CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 3708 // CHECK5-NEXT: [[A:%.*]] = alloca i32, align 4 3709 // CHECK5-NEXT: [[AA:%.*]] = alloca i16, align 2 3710 // CHECK5-NEXT: [[B:%.*]] = alloca [10 x float], align 4 3711 // CHECK5-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 3712 // CHECK5-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 3713 // CHECK5-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 3714 // CHECK5-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 3715 // CHECK5-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 3716 // CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 3717 // CHECK5-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 3718 // CHECK5-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 3719 // CHECK5-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 3720 // CHECK5-NEXT: [[DOTCAPTURE_EXPR__CASTED4:%.*]] = alloca i64, align 8 3721 // CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 3722 // CHECK5-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 3723 // CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 3724 // CHECK5-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4 3725 // CHECK5-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 3726 // CHECK5-NEXT: [[AA_CASTED7:%.*]] = alloca i64, align 8 3727 // CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS9:%.*]] = alloca [1 x i8*], align 8 3728 // CHECK5-NEXT: [[DOTOFFLOAD_PTRS10:%.*]] = alloca [1 x i8*], align 8 3729 // CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS11:%.*]] = alloca [1 x i8*], align 8 3730 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 3731 // CHECK5-NEXT: [[A_CASTED12:%.*]] = alloca i64, align 8 3732 // CHECK5-NEXT: [[AA_CASTED14:%.*]] = alloca i64, align 8 3733 // CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS16:%.*]] = alloca [2 x i8*], align 8 3734 // CHECK5-NEXT: [[DOTOFFLOAD_PTRS17:%.*]] = alloca [2 x i8*], align 8 3735 // CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS18:%.*]] = alloca [2 x i8*], align 8 3736 // CHECK5-NEXT: [[_TMP19:%.*]] = alloca i32, align 4 3737 // CHECK5-NEXT: [[A_CASTED22:%.*]] = alloca i64, align 8 3738 // CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS26:%.*]] = alloca [9 x i8*], align 8 3739 // CHECK5-NEXT: [[DOTOFFLOAD_PTRS27:%.*]] = alloca [9 x i8*], align 8 3740 // CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS28:%.*]] = alloca [9 x i8*], align 8 3741 // CHECK5-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [9 x i64], align 8 3742 // CHECK5-NEXT: [[_TMP29:%.*]] = alloca i32, align 4 3743 // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) 3744 // CHECK5-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 3745 // CHECK5-NEXT: store i32 0, i32* [[A]], align 4 3746 // CHECK5-NEXT: store i16 0, i16* [[AA]], align 2 3747 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 3748 // CHECK5-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 3749 // CHECK5-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() 3750 // CHECK5-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 3751 // CHECK5-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP2]], align 4 3752 // CHECK5-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 3753 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 3754 // CHECK5-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64 3755 // CHECK5-NEXT: [[TMP6:%.*]] = mul nuw i64 5, [[TMP5]] 3756 // CHECK5-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP6]], align 8 3757 // CHECK5-NEXT: store i64 [[TMP5]], i64* [[__VLA_EXPR1]], align 8 3758 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 3759 // CHECK5-NEXT: store i32 [[TMP7]], i32* [[DOTCAPTURE_EXPR_]], align 4 3760 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 3761 // CHECK5-NEXT: store i32 [[TMP8]], i32* [[DOTCAPTURE_EXPR_2]], align 4 3762 // CHECK5-NEXT: [[TMP9:%.*]] = load i16, i16* [[AA]], align 2 3763 // CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 3764 // CHECK5-NEXT: store i16 [[TMP9]], i16* [[CONV]], align 2 3765 // CHECK5-NEXT: [[TMP10:%.*]] = load i64, i64* [[AA_CASTED]], align 8 3766 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 3767 // CHECK5-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* 3768 // CHECK5-NEXT: store i32 [[TMP11]], i32* [[CONV3]], align 4 3769 // CHECK5-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 3770 // CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 3771 // CHECK5-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED4]] to i32* 3772 // CHECK5-NEXT: store i32 [[TMP13]], i32* [[CONV5]], align 4 3773 // CHECK5-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED4]], align 8 3774 // CHECK5-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3775 // CHECK5-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i64* 3776 // CHECK5-NEXT: store i64 [[TMP10]], i64* [[TMP16]], align 8 3777 // CHECK5-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3778 // CHECK5-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64* 3779 // CHECK5-NEXT: store i64 [[TMP10]], i64* [[TMP18]], align 8 3780 // CHECK5-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 3781 // CHECK5-NEXT: store i8* null, i8** [[TMP19]], align 8 3782 // CHECK5-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 3783 // CHECK5-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i64* 3784 // CHECK5-NEXT: store i64 [[TMP12]], i64* [[TMP21]], align 8 3785 // CHECK5-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 3786 // CHECK5-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i64* 3787 // CHECK5-NEXT: store i64 [[TMP12]], i64* [[TMP23]], align 8 3788 // CHECK5-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 3789 // CHECK5-NEXT: store i8* null, i8** [[TMP24]], align 8 3790 // CHECK5-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 3791 // CHECK5-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i64* 3792 // CHECK5-NEXT: store i64 [[TMP14]], i64* [[TMP26]], align 8 3793 // CHECK5-NEXT: [[TMP27:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 3794 // CHECK5-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i64* 3795 // CHECK5-NEXT: store i64 [[TMP14]], i64* [[TMP28]], align 8 3796 // CHECK5-NEXT: [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 3797 // CHECK5-NEXT: store i8* null, i8** [[TMP29]], align 8 3798 // CHECK5-NEXT: [[TMP30:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3799 // CHECK5-NEXT: [[TMP31:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3800 // CHECK5-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 0 3801 // CHECK5-NEXT: [[TMP33:%.*]] = load i16, i16* [[AA]], align 2 3802 // CHECK5-NEXT: store i16 [[TMP33]], i16* [[TMP32]], align 4 3803 // CHECK5-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 1 3804 // CHECK5-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 3805 // CHECK5-NEXT: store i32 [[TMP35]], i32* [[TMP34]], align 4 3806 // CHECK5-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 2 3807 // CHECK5-NEXT: [[TMP37:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 3808 // CHECK5-NEXT: store i32 [[TMP37]], i32* [[TMP36]], align 4 3809 // CHECK5-NEXT: [[TMP38:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 1, i64 120, i64 12, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1) 3810 // CHECK5-NEXT: [[TMP39:%.*]] = bitcast i8* [[TMP38]] to %struct.kmp_task_t_with_privates* 3811 // CHECK5-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP39]], i32 0, i32 0 3812 // CHECK5-NEXT: [[TMP41:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP40]], i32 0, i32 0 3813 // CHECK5-NEXT: [[TMP42:%.*]] = load i8*, i8** [[TMP41]], align 8 3814 // CHECK5-NEXT: [[TMP43:%.*]] = bitcast %struct.anon* [[AGG_CAPTURED]] to i8* 3815 // CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP42]], i8* align 4 [[TMP43]], i64 12, i1 false) 3816 // CHECK5-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP39]], i32 0, i32 1 3817 // CHECK5-NEXT: [[TMP45:%.*]] = bitcast i8* [[TMP42]] to %struct.anon* 3818 // CHECK5-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 0 3819 // CHECK5-NEXT: [[TMP47:%.*]] = bitcast [3 x i8*]* [[TMP46]] to i8* 3820 // CHECK5-NEXT: [[TMP48:%.*]] = bitcast i8** [[TMP30]] to i8* 3821 // CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP47]], i8* align 8 [[TMP48]], i64 24, i1 false) 3822 // CHECK5-NEXT: [[TMP49:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 1 3823 // CHECK5-NEXT: [[TMP50:%.*]] = bitcast [3 x i8*]* [[TMP49]] to i8* 3824 // CHECK5-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP31]] to i8* 3825 // CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP50]], i8* align 8 [[TMP51]], i64 24, i1 false) 3826 // CHECK5-NEXT: [[TMP52:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 2 3827 // CHECK5-NEXT: [[TMP53:%.*]] = bitcast [3 x i64]* [[TMP52]] to i8* 3828 // CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP53]], i8* align 8 bitcast ([3 x i64]* @.offload_sizes to i8*), i64 24, i1 false) 3829 // CHECK5-NEXT: [[TMP54:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 3 3830 // CHECK5-NEXT: [[TMP55:%.*]] = load i16, i16* [[AA]], align 2 3831 // CHECK5-NEXT: store i16 [[TMP55]], i16* [[TMP54]], align 8 3832 // CHECK5-NEXT: [[TMP56:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i8* [[TMP38]]) 3833 // CHECK5-NEXT: [[TMP57:%.*]] = load i32, i32* [[A]], align 4 3834 // CHECK5-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32* 3835 // CHECK5-NEXT: store i32 [[TMP57]], i32* [[CONV6]], align 4 3836 // CHECK5-NEXT: [[TMP58:%.*]] = load i64, i64* [[A_CASTED]], align 8 3837 // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l102(i64 [[TMP58]]) #[[ATTR4:[0-9]+]] 3838 // CHECK5-NEXT: [[TMP59:%.*]] = load i16, i16* [[AA]], align 2 3839 // CHECK5-NEXT: [[CONV8:%.*]] = bitcast i64* [[AA_CASTED7]] to i16* 3840 // CHECK5-NEXT: store i16 [[TMP59]], i16* [[CONV8]], align 2 3841 // CHECK5-NEXT: [[TMP60:%.*]] = load i64, i64* [[AA_CASTED7]], align 8 3842 // CHECK5-NEXT: [[TMP61:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS9]], i32 0, i32 0 3843 // CHECK5-NEXT: [[TMP62:%.*]] = bitcast i8** [[TMP61]] to i64* 3844 // CHECK5-NEXT: store i64 [[TMP60]], i64* [[TMP62]], align 8 3845 // CHECK5-NEXT: [[TMP63:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS10]], i32 0, i32 0 3846 // CHECK5-NEXT: [[TMP64:%.*]] = bitcast i8** [[TMP63]] to i64* 3847 // CHECK5-NEXT: store i64 [[TMP60]], i64* [[TMP64]], align 8 3848 // CHECK5-NEXT: [[TMP65:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS11]], i64 0, i64 0 3849 // CHECK5-NEXT: store i8* null, i8** [[TMP65]], align 8 3850 // CHECK5-NEXT: [[TMP66:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS9]], i32 0, i32 0 3851 // CHECK5-NEXT: [[TMP67:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS10]], i32 0, i32 0 3852 // CHECK5-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) 3853 // CHECK5-NEXT: [[TMP68:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.region_id, i32 1, i8** [[TMP66]], i8** [[TMP67]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.4, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.5, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1) 3854 // CHECK5-NEXT: [[TMP69:%.*]] = icmp ne i32 [[TMP68]], 0 3855 // CHECK5-NEXT: br i1 [[TMP69]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 3856 // CHECK5: omp_offload.failed: 3857 // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111(i64 [[TMP60]]) #[[ATTR4]] 3858 // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]] 3859 // CHECK5: omp_offload.cont: 3860 // CHECK5-NEXT: [[TMP70:%.*]] = load i32, i32* [[A]], align 4 3861 // CHECK5-NEXT: [[CONV13:%.*]] = bitcast i64* [[A_CASTED12]] to i32* 3862 // CHECK5-NEXT: store i32 [[TMP70]], i32* [[CONV13]], align 4 3863 // CHECK5-NEXT: [[TMP71:%.*]] = load i64, i64* [[A_CASTED12]], align 8 3864 // CHECK5-NEXT: [[TMP72:%.*]] = load i16, i16* [[AA]], align 2 3865 // CHECK5-NEXT: [[CONV15:%.*]] = bitcast i64* [[AA_CASTED14]] to i16* 3866 // CHECK5-NEXT: store i16 [[TMP72]], i16* [[CONV15]], align 2 3867 // CHECK5-NEXT: [[TMP73:%.*]] = load i64, i64* [[AA_CASTED14]], align 8 3868 // CHECK5-NEXT: [[TMP74:%.*]] = load i32, i32* [[N_ADDR]], align 4 3869 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP74]], 10 3870 // CHECK5-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 3871 // CHECK5: omp_if.then: 3872 // CHECK5-NEXT: [[TMP75:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 0 3873 // CHECK5-NEXT: [[TMP76:%.*]] = bitcast i8** [[TMP75]] to i64* 3874 // CHECK5-NEXT: store i64 [[TMP71]], i64* [[TMP76]], align 8 3875 // CHECK5-NEXT: [[TMP77:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 0 3876 // CHECK5-NEXT: [[TMP78:%.*]] = bitcast i8** [[TMP77]] to i64* 3877 // CHECK5-NEXT: store i64 [[TMP71]], i64* [[TMP78]], align 8 3878 // CHECK5-NEXT: [[TMP79:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 0 3879 // CHECK5-NEXT: store i8* null, i8** [[TMP79]], align 8 3880 // CHECK5-NEXT: [[TMP80:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 1 3881 // CHECK5-NEXT: [[TMP81:%.*]] = bitcast i8** [[TMP80]] to i64* 3882 // CHECK5-NEXT: store i64 [[TMP73]], i64* [[TMP81]], align 8 3883 // CHECK5-NEXT: [[TMP82:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 1 3884 // CHECK5-NEXT: [[TMP83:%.*]] = bitcast i8** [[TMP82]] to i64* 3885 // CHECK5-NEXT: store i64 [[TMP73]], i64* [[TMP83]], align 8 3886 // CHECK5-NEXT: [[TMP84:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 1 3887 // CHECK5-NEXT: store i8* null, i8** [[TMP84]], align 8 3888 // CHECK5-NEXT: [[TMP85:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 0 3889 // CHECK5-NEXT: [[TMP86:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 0 3890 // CHECK5-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) 3891 // CHECK5-NEXT: [[TMP87:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.region_id, i32 2, i8** [[TMP85]], i8** [[TMP86]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.7, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.8, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1) 3892 // CHECK5-NEXT: [[TMP88:%.*]] = icmp ne i32 [[TMP87]], 0 3893 // CHECK5-NEXT: br i1 [[TMP88]], label [[OMP_OFFLOAD_FAILED20:%.*]], label [[OMP_OFFLOAD_CONT21:%.*]] 3894 // CHECK5: omp_offload.failed20: 3895 // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i64 [[TMP71]], i64 [[TMP73]]) #[[ATTR4]] 3896 // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT21]] 3897 // CHECK5: omp_offload.cont21: 3898 // CHECK5-NEXT: br label [[OMP_IF_END:%.*]] 3899 // CHECK5: omp_if.else: 3900 // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i64 [[TMP71]], i64 [[TMP73]]) #[[ATTR4]] 3901 // CHECK5-NEXT: br label [[OMP_IF_END]] 3902 // CHECK5: omp_if.end: 3903 // CHECK5-NEXT: [[TMP89:%.*]] = load i32, i32* [[A]], align 4 3904 // CHECK5-NEXT: [[CONV23:%.*]] = bitcast i64* [[A_CASTED22]] to i32* 3905 // CHECK5-NEXT: store i32 [[TMP89]], i32* [[CONV23]], align 4 3906 // CHECK5-NEXT: [[TMP90:%.*]] = load i64, i64* [[A_CASTED22]], align 8 3907 // CHECK5-NEXT: [[TMP91:%.*]] = load i32, i32* [[N_ADDR]], align 4 3908 // CHECK5-NEXT: [[CMP24:%.*]] = icmp sgt i32 [[TMP91]], 20 3909 // CHECK5-NEXT: br i1 [[CMP24]], label [[OMP_IF_THEN25:%.*]], label [[OMP_IF_ELSE32:%.*]] 3910 // CHECK5: omp_if.then25: 3911 // CHECK5-NEXT: [[TMP92:%.*]] = mul nuw i64 [[TMP2]], 4 3912 // CHECK5-NEXT: [[TMP93:%.*]] = mul nuw i64 5, [[TMP5]] 3913 // CHECK5-NEXT: [[TMP94:%.*]] = mul nuw i64 [[TMP93]], 8 3914 // CHECK5-NEXT: [[TMP95:%.*]] = bitcast [9 x i64]* [[DOTOFFLOAD_SIZES]] to i8* 3915 // CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP95]], i8* align 8 bitcast ([9 x i64]* @.offload_sizes.10 to i8*), i64 72, i1 false) 3916 // CHECK5-NEXT: [[TMP96:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS26]], i32 0, i32 0 3917 // CHECK5-NEXT: [[TMP97:%.*]] = bitcast i8** [[TMP96]] to i64* 3918 // CHECK5-NEXT: store i64 [[TMP90]], i64* [[TMP97]], align 8 3919 // CHECK5-NEXT: [[TMP98:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS27]], i32 0, i32 0 3920 // CHECK5-NEXT: [[TMP99:%.*]] = bitcast i8** [[TMP98]] to i64* 3921 // CHECK5-NEXT: store i64 [[TMP90]], i64* [[TMP99]], align 8 3922 // CHECK5-NEXT: [[TMP100:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS28]], i64 0, i64 0 3923 // CHECK5-NEXT: store i8* null, i8** [[TMP100]], align 8 3924 // CHECK5-NEXT: [[TMP101:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS26]], i32 0, i32 1 3925 // CHECK5-NEXT: [[TMP102:%.*]] = bitcast i8** [[TMP101]] to [10 x float]** 3926 // CHECK5-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP102]], align 8 3927 // CHECK5-NEXT: [[TMP103:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS27]], i32 0, i32 1 3928 // CHECK5-NEXT: [[TMP104:%.*]] = bitcast i8** [[TMP103]] to [10 x float]** 3929 // CHECK5-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP104]], align 8 3930 // CHECK5-NEXT: [[TMP105:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS28]], i64 0, i64 1 3931 // CHECK5-NEXT: store i8* null, i8** [[TMP105]], align 8 3932 // CHECK5-NEXT: [[TMP106:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS26]], i32 0, i32 2 3933 // CHECK5-NEXT: [[TMP107:%.*]] = bitcast i8** [[TMP106]] to i64* 3934 // CHECK5-NEXT: store i64 [[TMP2]], i64* [[TMP107]], align 8 3935 // CHECK5-NEXT: [[TMP108:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS27]], i32 0, i32 2 3936 // CHECK5-NEXT: [[TMP109:%.*]] = bitcast i8** [[TMP108]] to i64* 3937 // CHECK5-NEXT: store i64 [[TMP2]], i64* [[TMP109]], align 8 3938 // CHECK5-NEXT: [[TMP110:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS28]], i64 0, i64 2 3939 // CHECK5-NEXT: store i8* null, i8** [[TMP110]], align 8 3940 // CHECK5-NEXT: [[TMP111:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS26]], i32 0, i32 3 3941 // CHECK5-NEXT: [[TMP112:%.*]] = bitcast i8** [[TMP111]] to float** 3942 // CHECK5-NEXT: store float* [[VLA]], float** [[TMP112]], align 8 3943 // CHECK5-NEXT: [[TMP113:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS27]], i32 0, i32 3 3944 // CHECK5-NEXT: [[TMP114:%.*]] = bitcast i8** [[TMP113]] to float** 3945 // CHECK5-NEXT: store float* [[VLA]], float** [[TMP114]], align 8 3946 // CHECK5-NEXT: [[TMP115:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 3947 // CHECK5-NEXT: store i64 [[TMP92]], i64* [[TMP115]], align 8 3948 // CHECK5-NEXT: [[TMP116:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS28]], i64 0, i64 3 3949 // CHECK5-NEXT: store i8* null, i8** [[TMP116]], align 8 3950 // CHECK5-NEXT: [[TMP117:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS26]], i32 0, i32 4 3951 // CHECK5-NEXT: [[TMP118:%.*]] = bitcast i8** [[TMP117]] to [5 x [10 x double]]** 3952 // CHECK5-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP118]], align 8 3953 // CHECK5-NEXT: [[TMP119:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS27]], i32 0, i32 4 3954 // CHECK5-NEXT: [[TMP120:%.*]] = bitcast i8** [[TMP119]] to [5 x [10 x double]]** 3955 // CHECK5-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP120]], align 8 3956 // CHECK5-NEXT: [[TMP121:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS28]], i64 0, i64 4 3957 // CHECK5-NEXT: store i8* null, i8** [[TMP121]], align 8 3958 // CHECK5-NEXT: [[TMP122:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS26]], i32 0, i32 5 3959 // CHECK5-NEXT: [[TMP123:%.*]] = bitcast i8** [[TMP122]] to i64* 3960 // CHECK5-NEXT: store i64 5, i64* [[TMP123]], align 8 3961 // CHECK5-NEXT: [[TMP124:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS27]], i32 0, i32 5 3962 // CHECK5-NEXT: [[TMP125:%.*]] = bitcast i8** [[TMP124]] to i64* 3963 // CHECK5-NEXT: store i64 5, i64* [[TMP125]], align 8 3964 // CHECK5-NEXT: [[TMP126:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS28]], i64 0, i64 5 3965 // CHECK5-NEXT: store i8* null, i8** [[TMP126]], align 8 3966 // CHECK5-NEXT: [[TMP127:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS26]], i32 0, i32 6 3967 // CHECK5-NEXT: [[TMP128:%.*]] = bitcast i8** [[TMP127]] to i64* 3968 // CHECK5-NEXT: store i64 [[TMP5]], i64* [[TMP128]], align 8 3969 // CHECK5-NEXT: [[TMP129:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS27]], i32 0, i32 6 3970 // CHECK5-NEXT: [[TMP130:%.*]] = bitcast i8** [[TMP129]] to i64* 3971 // CHECK5-NEXT: store i64 [[TMP5]], i64* [[TMP130]], align 8 3972 // CHECK5-NEXT: [[TMP131:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS28]], i64 0, i64 6 3973 // CHECK5-NEXT: store i8* null, i8** [[TMP131]], align 8 3974 // CHECK5-NEXT: [[TMP132:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS26]], i32 0, i32 7 3975 // CHECK5-NEXT: [[TMP133:%.*]] = bitcast i8** [[TMP132]] to double** 3976 // CHECK5-NEXT: store double* [[VLA1]], double** [[TMP133]], align 8 3977 // CHECK5-NEXT: [[TMP134:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS27]], i32 0, i32 7 3978 // CHECK5-NEXT: [[TMP135:%.*]] = bitcast i8** [[TMP134]] to double** 3979 // CHECK5-NEXT: store double* [[VLA1]], double** [[TMP135]], align 8 3980 // CHECK5-NEXT: [[TMP136:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 3981 // CHECK5-NEXT: store i64 [[TMP94]], i64* [[TMP136]], align 8 3982 // CHECK5-NEXT: [[TMP137:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS28]], i64 0, i64 7 3983 // CHECK5-NEXT: store i8* null, i8** [[TMP137]], align 8 3984 // CHECK5-NEXT: [[TMP138:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS26]], i32 0, i32 8 3985 // CHECK5-NEXT: [[TMP139:%.*]] = bitcast i8** [[TMP138]] to %struct.TT** 3986 // CHECK5-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP139]], align 8 3987 // CHECK5-NEXT: [[TMP140:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS27]], i32 0, i32 8 3988 // CHECK5-NEXT: [[TMP141:%.*]] = bitcast i8** [[TMP140]] to %struct.TT** 3989 // CHECK5-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP141]], align 8 3990 // CHECK5-NEXT: [[TMP142:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS28]], i64 0, i64 8 3991 // CHECK5-NEXT: store i8* null, i8** [[TMP142]], align 8 3992 // CHECK5-NEXT: [[TMP143:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS26]], i32 0, i32 0 3993 // CHECK5-NEXT: [[TMP144:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS27]], i32 0, i32 0 3994 // CHECK5-NEXT: [[TMP145:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 3995 // CHECK5-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) 3996 // CHECK5-NEXT: [[TMP146:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142.region_id, i32 9, i8** [[TMP143]], i8** [[TMP144]], i64* [[TMP145]], i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_maptypes.11, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1) 3997 // CHECK5-NEXT: [[TMP147:%.*]] = icmp ne i32 [[TMP146]], 0 3998 // CHECK5-NEXT: br i1 [[TMP147]], label [[OMP_OFFLOAD_FAILED30:%.*]], label [[OMP_OFFLOAD_CONT31:%.*]] 3999 // CHECK5: omp_offload.failed30: 4000 // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i64 [[TMP90]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR4]] 4001 // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT31]] 4002 // CHECK5: omp_offload.cont31: 4003 // CHECK5-NEXT: br label [[OMP_IF_END33:%.*]] 4004 // CHECK5: omp_if.else32: 4005 // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i64 [[TMP90]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR4]] 4006 // CHECK5-NEXT: br label [[OMP_IF_END33]] 4007 // CHECK5: omp_if.end33: 4008 // CHECK5-NEXT: [[TMP148:%.*]] = load i32, i32* [[A]], align 4 4009 // CHECK5-NEXT: [[TMP149:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 4010 // CHECK5-NEXT: call void @llvm.stackrestore(i8* [[TMP149]]) 4011 // CHECK5-NEXT: ret i32 [[TMP148]] 4012 // 4013 // 4014 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97 4015 // CHECK5-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] { 4016 // CHECK5-NEXT: entry: 4017 // CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 4018 // CHECK5-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 4019 // CHECK5-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8 4020 // CHECK5-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 4021 // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]]) 4022 // CHECK5-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 4023 // CHECK5-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 4024 // CHECK5-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8 4025 // CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 4026 // CHECK5-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* 4027 // CHECK5-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32* 4028 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 4 4029 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 4 4030 // CHECK5-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) 4031 // CHECK5-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 4032 // CHECK5-NEXT: [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 4033 // CHECK5-NEXT: store i16 [[TMP3]], i16* [[CONV5]], align 2 4034 // CHECK5-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 4035 // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]]) 4036 // CHECK5-NEXT: ret void 4037 // 4038 // 4039 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined. 4040 // CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR3:[0-9]+]] { 4041 // CHECK5-NEXT: entry: 4042 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 4043 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 4044 // CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 4045 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 4046 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 4047 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 4048 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 4049 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 4050 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 4051 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 4052 // CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 4053 // CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 4054 // CHECK5-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 4055 // CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 4056 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 4057 // CHECK5-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 4058 // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 4059 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 4060 // CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 4061 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 4062 // CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 4063 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4064 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 4065 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 4066 // CHECK5: cond.true: 4067 // CHECK5-NEXT: br label [[COND_END:%.*]] 4068 // CHECK5: cond.false: 4069 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4070 // CHECK5-NEXT: br label [[COND_END]] 4071 // CHECK5: cond.end: 4072 // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 4073 // CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 4074 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 4075 // CHECK5-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 4076 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4077 // CHECK5: omp.inner.for.cond: 4078 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 4079 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !10 4080 // CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 4081 // CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 4082 // CHECK5: omp.inner.for.body: 4083 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 4084 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 4085 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 4086 // CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10 4087 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 4088 // CHECK5: omp.body.continue: 4089 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4090 // CHECK5: omp.inner.for.inc: 4091 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 4092 // CHECK5-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 4093 // CHECK5-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 4094 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] 4095 // CHECK5: omp.inner.for.end: 4096 // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 4097 // CHECK5: omp.loop.exit: 4098 // CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 4099 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 4100 // CHECK5-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 4101 // CHECK5-NEXT: br i1 [[TMP10]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 4102 // CHECK5: .omp.final.then: 4103 // CHECK5-NEXT: store i32 10, i32* [[I]], align 4 4104 // CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]] 4105 // CHECK5: .omp.final.done: 4106 // CHECK5-NEXT: ret void 4107 // 4108 // 4109 // CHECK5-LABEL: define {{[^@]+}}@.omp_task_privates_map. 4110 // CHECK5-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], i16** noalias noundef [[TMP1:%.*]], [3 x i8*]** noalias noundef [[TMP2:%.*]], [3 x i8*]** noalias noundef [[TMP3:%.*]], [3 x i64]** noalias noundef [[TMP4:%.*]]) #[[ATTR5:[0-9]+]] { 4111 // CHECK5-NEXT: entry: 4112 // CHECK5-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 8 4113 // CHECK5-NEXT: [[DOTADDR1:%.*]] = alloca i16**, align 8 4114 // CHECK5-NEXT: [[DOTADDR2:%.*]] = alloca [3 x i8*]**, align 8 4115 // CHECK5-NEXT: [[DOTADDR3:%.*]] = alloca [3 x i8*]**, align 8 4116 // CHECK5-NEXT: [[DOTADDR4:%.*]] = alloca [3 x i64]**, align 8 4117 // CHECK5-NEXT: store %struct..kmp_privates.t* [[TMP0]], %struct..kmp_privates.t** [[DOTADDR]], align 8 4118 // CHECK5-NEXT: store i16** [[TMP1]], i16*** [[DOTADDR1]], align 8 4119 // CHECK5-NEXT: store [3 x i8*]** [[TMP2]], [3 x i8*]*** [[DOTADDR2]], align 8 4120 // CHECK5-NEXT: store [3 x i8*]** [[TMP3]], [3 x i8*]*** [[DOTADDR3]], align 8 4121 // CHECK5-NEXT: store [3 x i64]** [[TMP4]], [3 x i64]*** [[DOTADDR4]], align 8 4122 // CHECK5-NEXT: [[TMP5:%.*]] = load %struct..kmp_privates.t*, %struct..kmp_privates.t** [[DOTADDR]], align 8 4123 // CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 0 4124 // CHECK5-NEXT: [[TMP7:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR2]], align 8 4125 // CHECK5-NEXT: store [3 x i8*]* [[TMP6]], [3 x i8*]** [[TMP7]], align 8 4126 // CHECK5-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 1 4127 // CHECK5-NEXT: [[TMP9:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR3]], align 8 4128 // CHECK5-NEXT: store [3 x i8*]* [[TMP8]], [3 x i8*]** [[TMP9]], align 8 4129 // CHECK5-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 2 4130 // CHECK5-NEXT: [[TMP11:%.*]] = load [3 x i64]**, [3 x i64]*** [[DOTADDR4]], align 8 4131 // CHECK5-NEXT: store [3 x i64]* [[TMP10]], [3 x i64]** [[TMP11]], align 8 4132 // CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 3 4133 // CHECK5-NEXT: [[TMP13:%.*]] = load i16**, i16*** [[DOTADDR1]], align 8 4134 // CHECK5-NEXT: store i16* [[TMP12]], i16** [[TMP13]], align 8 4135 // CHECK5-NEXT: ret void 4136 // 4137 // 4138 // CHECK5-LABEL: define {{[^@]+}}@.omp_task_entry. 4139 // CHECK5-SAME: (i32 noundef signext [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] { 4140 // CHECK5-NEXT: entry: 4141 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 4142 // CHECK5-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 4143 // CHECK5-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8 4144 // CHECK5-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8 4145 // CHECK5-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8 4146 // CHECK5-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 8 4147 // CHECK5-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca i16*, align 8 4148 // CHECK5-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca [3 x i8*]*, align 8 4149 // CHECK5-NEXT: [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca [3 x i8*]*, align 8 4150 // CHECK5-NEXT: [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca [3 x i64]*, align 8 4151 // CHECK5-NEXT: [[AA_CASTED_I:%.*]] = alloca i64, align 8 4152 // CHECK5-NEXT: [[DOTCAPTURE_EXPR__CASTED_I:%.*]] = alloca i64, align 8 4153 // CHECK5-NEXT: [[DOTCAPTURE_EXPR__CASTED5_I:%.*]] = alloca i64, align 8 4154 // CHECK5-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 4155 // CHECK5-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8 4156 // CHECK5-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 4157 // CHECK5-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 4158 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 4159 // CHECK5-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 4160 // CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0 4161 // CHECK5-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 4162 // CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 4163 // CHECK5-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 4164 // CHECK5-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon* 4165 // CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1 4166 // CHECK5-NEXT: [[TMP10:%.*]] = bitcast %struct..kmp_privates.t* [[TMP9]] to i8* 4167 // CHECK5-NEXT: [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8* 4168 // CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META17:![0-9]+]]) 4169 // CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]]) 4170 // CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META22:![0-9]+]]) 4171 // CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META24:![0-9]+]]) 4172 // CHECK5-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !26 4173 // CHECK5-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !26 4174 // CHECK5-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !26 4175 // CHECK5-NEXT: store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* @.omp_task_privates_map. to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !26 4176 // CHECK5-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !26 4177 // CHECK5-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !26 4178 // CHECK5-NEXT: [[TMP12:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !26 4179 // CHECK5-NEXT: [[TMP13:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !26 4180 // CHECK5-NEXT: [[TMP14:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !26 4181 // CHECK5-NEXT: [[TMP15:%.*]] = bitcast void (i8*, ...)* [[TMP13]] to void (i8*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* 4182 // CHECK5-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR4]] 4183 // CHECK5-NEXT: [[TMP16:%.*]] = load i16*, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !26 4184 // CHECK5-NEXT: [[TMP17:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !26 4185 // CHECK5-NEXT: [[TMP18:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 8, !noalias !26 4186 // CHECK5-NEXT: [[TMP19:%.*]] = load [3 x i64]*, [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 8, !noalias !26 4187 // CHECK5-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP17]], i64 0, i64 0 4188 // CHECK5-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP18]], i64 0, i64 0 4189 // CHECK5-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[TMP19]], i64 0, i64 0 4190 // CHECK5-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP12]], i32 0, i32 1 4191 // CHECK5-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[TMP12]], i32 0, i32 2 4192 // CHECK5-NEXT: [[TMP25:%.*]] = load i32, i32* [[TMP23]], align 4 4193 // CHECK5-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) #[[ATTR4]] 4194 // CHECK5-NEXT: [[TMP26:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 [[TMP25]], i32 1, i32 0, i8* null, i32 0, i8* null) #[[ATTR4]] 4195 // CHECK5-NEXT: [[TMP27:%.*]] = icmp ne i32 [[TMP26]], 0 4196 // CHECK5-NEXT: br i1 [[TMP27]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]] 4197 // CHECK5: omp_offload.failed.i: 4198 // CHECK5-NEXT: [[TMP28:%.*]] = load i16, i16* [[TMP16]], align 2 4199 // CHECK5-NEXT: [[CONV_I:%.*]] = bitcast i64* [[AA_CASTED_I]] to i16* 4200 // CHECK5-NEXT: store i16 [[TMP28]], i16* [[CONV_I]], align 2, !noalias !26 4201 // CHECK5-NEXT: [[TMP29:%.*]] = load i64, i64* [[AA_CASTED_I]], align 8, !noalias !26 4202 // CHECK5-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP23]], align 4 4203 // CHECK5-NEXT: [[CONV4_I:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED_I]] to i32* 4204 // CHECK5-NEXT: store i32 [[TMP30]], i32* [[CONV4_I]], align 4, !noalias !26 4205 // CHECK5-NEXT: [[TMP31:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED_I]], align 8, !noalias !26 4206 // CHECK5-NEXT: [[TMP32:%.*]] = load i32, i32* [[TMP24]], align 4 4207 // CHECK5-NEXT: [[CONV6_I:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED5_I]] to i32* 4208 // CHECK5-NEXT: store i32 [[TMP32]], i32* [[CONV6_I]], align 4, !noalias !26 4209 // CHECK5-NEXT: [[TMP33:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED5_I]], align 8, !noalias !26 4210 // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97(i64 [[TMP29]], i64 [[TMP31]], i64 [[TMP33]]) #[[ATTR4]] 4211 // CHECK5-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]] 4212 // CHECK5: .omp_outlined..1.exit: 4213 // CHECK5-NEXT: ret i32 0 4214 // 4215 // 4216 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l102 4217 // CHECK5-SAME: (i64 noundef [[A:%.*]]) #[[ATTR3]] { 4218 // CHECK5-NEXT: entry: 4219 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 4220 // CHECK5-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 4221 // CHECK5-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 4222 // CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 4223 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 4224 // CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32* 4225 // CHECK5-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 4226 // CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 4227 // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]]) 4228 // CHECK5-NEXT: ret void 4229 // 4230 // 4231 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..2 4232 // CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]]) #[[ATTR3]] { 4233 // CHECK5-NEXT: entry: 4234 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 4235 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 4236 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 4237 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 4238 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 4239 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 4240 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 4241 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 4242 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 4243 // CHECK5-NEXT: [[A1:%.*]] = alloca i32, align 4 4244 // CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 4245 // CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 4246 // CHECK5-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 4247 // CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 4248 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 4249 // CHECK5-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 4250 // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 4251 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 4252 // CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 4253 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 4254 // CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 4255 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4256 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 4257 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 4258 // CHECK5: cond.true: 4259 // CHECK5-NEXT: br label [[COND_END:%.*]] 4260 // CHECK5: cond.false: 4261 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4262 // CHECK5-NEXT: br label [[COND_END]] 4263 // CHECK5: cond.end: 4264 // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 4265 // CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 4266 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 4267 // CHECK5-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 4268 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4269 // CHECK5: omp.inner.for.cond: 4270 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4271 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4272 // CHECK5-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 4273 // CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 4274 // CHECK5: omp.inner.for.body: 4275 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4276 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 4277 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 4278 // CHECK5-NEXT: store i32 [[ADD]], i32* [[A1]], align 4, !nontemporal !27 4279 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[A1]], align 4, !nontemporal !27 4280 // CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1 4281 // CHECK5-NEXT: store i32 [[ADD3]], i32* [[A1]], align 4, !nontemporal !27 4282 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 4283 // CHECK5: omp.body.continue: 4284 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4285 // CHECK5: omp.inner.for.inc: 4286 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4287 // CHECK5-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP9]], 1 4288 // CHECK5-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 4289 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]] 4290 // CHECK5: omp.inner.for.end: 4291 // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 4292 // CHECK5: omp.loop.exit: 4293 // CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 4294 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 4295 // CHECK5-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0 4296 // CHECK5-NEXT: br i1 [[TMP11]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 4297 // CHECK5: .omp.final.then: 4298 // CHECK5-NEXT: store i32 10, i32* [[CONV]], align 4 4299 // CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]] 4300 // CHECK5: .omp.final.done: 4301 // CHECK5-NEXT: ret void 4302 // 4303 // 4304 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 4305 // CHECK5-SAME: (i64 noundef [[AA:%.*]]) #[[ATTR2]] { 4306 // CHECK5-NEXT: entry: 4307 // CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 4308 // CHECK5-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 4309 // CHECK5-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 4310 // CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 4311 // CHECK5-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 4312 // CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 4313 // CHECK5-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 4314 // CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 4315 // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP1]]) 4316 // CHECK5-NEXT: ret void 4317 // 4318 // 4319 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..3 4320 // CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR3]] { 4321 // CHECK5-NEXT: entry: 4322 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 4323 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 4324 // CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 4325 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 4326 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 4327 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 4328 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 4329 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 4330 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 4331 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 4332 // CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 4333 // CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 4334 // CHECK5-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 4335 // CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 4336 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 4337 // CHECK5-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 4338 // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 4339 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 4340 // CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 4341 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 4342 // CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 4343 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4344 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 4345 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 4346 // CHECK5: cond.true: 4347 // CHECK5-NEXT: br label [[COND_END:%.*]] 4348 // CHECK5: cond.false: 4349 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4350 // CHECK5-NEXT: br label [[COND_END]] 4351 // CHECK5: cond.end: 4352 // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 4353 // CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 4354 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 4355 // CHECK5-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 4356 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4357 // CHECK5: omp.inner.for.cond: 4358 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30 4359 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !30 4360 // CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 4361 // CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 4362 // CHECK5: omp.inner.for.body: 4363 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30 4364 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 4365 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 4366 // CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !30 4367 // CHECK5-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !30 4368 // CHECK5-NEXT: [[CONV2:%.*]] = sext i16 [[TMP8]] to i32 4369 // CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 4370 // CHECK5-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 4371 // CHECK5-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2, !llvm.access.group !30 4372 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 4373 // CHECK5: omp.body.continue: 4374 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4375 // CHECK5: omp.inner.for.inc: 4376 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30 4377 // CHECK5-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP9]], 1 4378 // CHECK5-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30 4379 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP31:![0-9]+]] 4380 // CHECK5: omp.inner.for.end: 4381 // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 4382 // CHECK5: omp.loop.exit: 4383 // CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 4384 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 4385 // CHECK5-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0 4386 // CHECK5-NEXT: br i1 [[TMP11]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 4387 // CHECK5: .omp.final.then: 4388 // CHECK5-NEXT: store i32 10, i32* [[I]], align 4 4389 // CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]] 4390 // CHECK5: .omp.final.done: 4391 // CHECK5-NEXT: ret void 4392 // 4393 // 4394 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118 4395 // CHECK5-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { 4396 // CHECK5-NEXT: entry: 4397 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 4398 // CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 4399 // CHECK5-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 4400 // CHECK5-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 4401 // CHECK5-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 4402 // CHECK5-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 4403 // CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 4404 // CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 4405 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 4406 // CHECK5-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* 4407 // CHECK5-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 4408 // CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 4409 // CHECK5-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 4410 // CHECK5-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 4411 // CHECK5-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 4412 // CHECK5-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 4413 // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) 4414 // CHECK5-NEXT: ret void 4415 // 4416 // 4417 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..6 4418 // CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR3]] { 4419 // CHECK5-NEXT: entry: 4420 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 4421 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 4422 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 4423 // CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 4424 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 4425 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 4426 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 4427 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 4428 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 4429 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 4430 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 4431 // CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 4432 // CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 4433 // CHECK5-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 4434 // CHECK5-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 4435 // CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 4436 // CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 4437 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 4438 // CHECK5-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 4439 // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 4440 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 4441 // CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 4442 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 4443 // CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 4444 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4445 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 4446 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 4447 // CHECK5: cond.true: 4448 // CHECK5-NEXT: br label [[COND_END:%.*]] 4449 // CHECK5: cond.false: 4450 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4451 // CHECK5-NEXT: br label [[COND_END]] 4452 // CHECK5: cond.end: 4453 // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 4454 // CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 4455 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 4456 // CHECK5-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 4457 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4458 // CHECK5: omp.inner.for.cond: 4459 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33 4460 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !33 4461 // CHECK5-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 4462 // CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 4463 // CHECK5: omp.inner.for.body: 4464 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33 4465 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 4466 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 4467 // CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !33 4468 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !33 4469 // CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1 4470 // CHECK5-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4, !llvm.access.group !33 4471 // CHECK5-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 2, !llvm.access.group !33 4472 // CHECK5-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32 4473 // CHECK5-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 4474 // CHECK5-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 4475 // CHECK5-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2, !llvm.access.group !33 4476 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 4477 // CHECK5: omp.body.continue: 4478 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4479 // CHECK5: omp.inner.for.inc: 4480 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33 4481 // CHECK5-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1 4482 // CHECK5-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33 4483 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP34:![0-9]+]] 4484 // CHECK5: omp.inner.for.end: 4485 // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 4486 // CHECK5: omp.loop.exit: 4487 // CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 4488 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 4489 // CHECK5-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 4490 // CHECK5-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 4491 // CHECK5: .omp.final.then: 4492 // CHECK5-NEXT: store i32 10, i32* [[I]], align 4 4493 // CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]] 4494 // CHECK5: .omp.final.done: 4495 // CHECK5-NEXT: ret void 4496 // 4497 // 4498 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142 4499 // CHECK5-SAME: (i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] { 4500 // CHECK5-NEXT: entry: 4501 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 4502 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 4503 // CHECK5-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 4504 // CHECK5-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 4505 // CHECK5-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 4506 // CHECK5-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 4507 // CHECK5-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 4508 // CHECK5-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 4509 // CHECK5-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 4510 // CHECK5-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 4511 // CHECK5-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 4512 // CHECK5-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 4513 // CHECK5-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 4514 // CHECK5-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 4515 // CHECK5-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 4516 // CHECK5-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 4517 // CHECK5-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 4518 // CHECK5-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 4519 // CHECK5-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 4520 // CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 4521 // CHECK5-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 4522 // CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 4523 // CHECK5-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 4524 // CHECK5-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 4525 // CHECK5-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 4526 // CHECK5-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 4527 // CHECK5-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 4528 // CHECK5-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 4529 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 4530 // CHECK5-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* 4531 // CHECK5-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4 4532 // CHECK5-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 4533 // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) 4534 // CHECK5-NEXT: ret void 4535 // 4536 // 4537 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..9 4538 // CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR3]] { 4539 // CHECK5-NEXT: entry: 4540 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 4541 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 4542 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 4543 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 4544 // CHECK5-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 4545 // CHECK5-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 4546 // CHECK5-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 4547 // CHECK5-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 4548 // CHECK5-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 4549 // CHECK5-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 4550 // CHECK5-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 4551 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 4552 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 4553 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 4554 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 4555 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 4556 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 4557 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 4558 // CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 4559 // CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 4560 // CHECK5-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 4561 // CHECK5-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 4562 // CHECK5-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 4563 // CHECK5-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 4564 // CHECK5-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 4565 // CHECK5-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 4566 // CHECK5-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 4567 // CHECK5-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 4568 // CHECK5-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 4569 // CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 4570 // CHECK5-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 4571 // CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 4572 // CHECK5-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 4573 // CHECK5-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 4574 // CHECK5-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 4575 // CHECK5-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 4576 // CHECK5-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 4577 // CHECK5-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 4578 // CHECK5-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 0 4579 // CHECK5-NEXT: call void @llvm.assume(i1 true) [ "align"(float* [[ARRAYDECAY]], i64 16) ] 4580 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 4581 // CHECK5-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 4582 // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 4583 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 4584 // CHECK5-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 4585 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 4586 // CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 4587 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4588 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP10]], 9 4589 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 4590 // CHECK5: cond.true: 4591 // CHECK5-NEXT: br label [[COND_END:%.*]] 4592 // CHECK5: cond.false: 4593 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4594 // CHECK5-NEXT: br label [[COND_END]] 4595 // CHECK5: cond.end: 4596 // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] 4597 // CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 4598 // CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 4599 // CHECK5-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 4600 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4601 // CHECK5: omp.inner.for.cond: 4602 // CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36 4603 // CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !36 4604 // CHECK5-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] 4605 // CHECK5-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 4606 // CHECK5: omp.inner.for.body: 4607 // CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36 4608 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 4609 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 4610 // CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !36 4611 // CHECK5-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !36 4612 // CHECK5-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP16]], 1 4613 // CHECK5-NEXT: store i32 [[ADD6]], i32* [[CONV]], align 4, !llvm.access.group !36 4614 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 4615 // CHECK5-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !36 4616 // CHECK5-NEXT: [[CONV7:%.*]] = fpext float [[TMP17]] to double 4617 // CHECK5-NEXT: [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00 4618 // CHECK5-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float 4619 // CHECK5-NEXT: store float [[CONV9]], float* [[ARRAYIDX]], align 4, !llvm.access.group !36 4620 // CHECK5-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 4621 // CHECK5-NEXT: [[TMP18:%.*]] = load float, float* [[ARRAYIDX10]], align 4, !llvm.access.group !36 4622 // CHECK5-NEXT: [[CONV11:%.*]] = fpext float [[TMP18]] to double 4623 // CHECK5-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00 4624 // CHECK5-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float 4625 // CHECK5-NEXT: store float [[CONV13]], float* [[ARRAYIDX10]], align 4, !llvm.access.group !36 4626 // CHECK5-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1 4627 // CHECK5-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX14]], i64 0, i64 2 4628 // CHECK5-NEXT: [[TMP19:%.*]] = load double, double* [[ARRAYIDX15]], align 8, !llvm.access.group !36 4629 // CHECK5-NEXT: [[ADD16:%.*]] = fadd double [[TMP19]], 1.000000e+00 4630 // CHECK5-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8, !llvm.access.group !36 4631 // CHECK5-NEXT: [[TMP20:%.*]] = mul nsw i64 1, [[TMP5]] 4632 // CHECK5-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP20]] 4633 // CHECK5-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX17]], i64 3 4634 // CHECK5-NEXT: [[TMP21:%.*]] = load double, double* [[ARRAYIDX18]], align 8, !llvm.access.group !36 4635 // CHECK5-NEXT: [[ADD19:%.*]] = fadd double [[TMP21]], 1.000000e+00 4636 // CHECK5-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8, !llvm.access.group !36 4637 // CHECK5-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 4638 // CHECK5-NEXT: [[TMP22:%.*]] = load i64, i64* [[X]], align 8, !llvm.access.group !36 4639 // CHECK5-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP22]], 1 4640 // CHECK5-NEXT: store i64 [[ADD20]], i64* [[X]], align 8, !llvm.access.group !36 4641 // CHECK5-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 4642 // CHECK5-NEXT: [[TMP23:%.*]] = load i8, i8* [[Y]], align 8, !llvm.access.group !36 4643 // CHECK5-NEXT: [[CONV21:%.*]] = sext i8 [[TMP23]] to i32 4644 // CHECK5-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1 4645 // CHECK5-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8 4646 // CHECK5-NEXT: store i8 [[CONV23]], i8* [[Y]], align 8, !llvm.access.group !36 4647 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 4648 // CHECK5: omp.body.continue: 4649 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4650 // CHECK5: omp.inner.for.inc: 4651 // CHECK5-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36 4652 // CHECK5-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP24]], 1 4653 // CHECK5-NEXT: store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36 4654 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP37:![0-9]+]] 4655 // CHECK5: omp.inner.for.end: 4656 // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 4657 // CHECK5: omp.loop.exit: 4658 // CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]]) 4659 // CHECK5-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 4660 // CHECK5-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0 4661 // CHECK5-NEXT: br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 4662 // CHECK5: .omp.final.then: 4663 // CHECK5-NEXT: store i32 10, i32* [[I]], align 4 4664 // CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]] 4665 // CHECK5: .omp.final.done: 4666 // CHECK5-NEXT: ret void 4667 // 4668 // 4669 // CHECK5-LABEL: define {{[^@]+}}@_Z3bari 4670 // CHECK5-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { 4671 // CHECK5-NEXT: entry: 4672 // CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 4673 // CHECK5-NEXT: [[A:%.*]] = alloca i32, align 4 4674 // CHECK5-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 4675 // CHECK5-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 4676 // CHECK5-NEXT: store i32 0, i32* [[A]], align 4 4677 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 4678 // CHECK5-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]]) 4679 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 4680 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 4681 // CHECK5-NEXT: store i32 [[ADD]], i32* [[A]], align 4 4682 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 4683 // CHECK5-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP2]]) 4684 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 4685 // CHECK5-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 4686 // CHECK5-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 4687 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 4688 // CHECK5-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]]) 4689 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 4690 // CHECK5-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 4691 // CHECK5-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 4692 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 4693 // CHECK5-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]]) 4694 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 4695 // CHECK5-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] 4696 // CHECK5-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 4697 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 4698 // CHECK5-NEXT: ret i32 [[TMP8]] 4699 // 4700 // 4701 // CHECK5-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 4702 // CHECK5-SAME: (%struct.S1* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { 4703 // CHECK5-NEXT: entry: 4704 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 4705 // CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 4706 // CHECK5-NEXT: [[B:%.*]] = alloca i32, align 4 4707 // CHECK5-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 4708 // CHECK5-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 4709 // CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 4710 // CHECK5-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 4711 // CHECK5-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 4712 // CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [6 x i8*], align 8 4713 // CHECK5-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [6 x i8*], align 8 4714 // CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [6 x i8*], align 8 4715 // CHECK5-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [6 x i64], align 8 4716 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 4717 // CHECK5-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 4718 // CHECK5-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 4719 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 4720 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 4721 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 4722 // CHECK5-NEXT: store i32 [[ADD]], i32* [[B]], align 4 4723 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 4724 // CHECK5-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 4725 // CHECK5-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() 4726 // CHECK5-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 4727 // CHECK5-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] 4728 // CHECK5-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 4729 // CHECK5-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 4730 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[N_ADDR]], align 4 4731 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 60 4732 // CHECK5-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8 4733 // CHECK5-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 4734 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[B]], align 4 4735 // CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32* 4736 // CHECK5-NEXT: store i32 [[TMP6]], i32* [[CONV]], align 4 4737 // CHECK5-NEXT: [[TMP7:%.*]] = load i64, i64* [[B_CASTED]], align 8 4738 // CHECK5-NEXT: [[TMP8:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 4739 // CHECK5-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP8]] to i1 4740 // CHECK5-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* 4741 // CHECK5-NEXT: [[FROMBOOL3:%.*]] = zext i1 [[TOBOOL]] to i8 4742 // CHECK5-NEXT: store i8 [[FROMBOOL3]], i8* [[CONV2]], align 1 4743 // CHECK5-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 4744 // CHECK5-NEXT: [[TMP10:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 4745 // CHECK5-NEXT: [[TOBOOL4:%.*]] = trunc i8 [[TMP10]] to i1 4746 // CHECK5-NEXT: br i1 [[TOBOOL4]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 4747 // CHECK5: omp_if.then: 4748 // CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 4749 // CHECK5-NEXT: [[TMP11:%.*]] = mul nuw i64 2, [[TMP2]] 4750 // CHECK5-NEXT: [[TMP12:%.*]] = mul nuw i64 [[TMP11]], 2 4751 // CHECK5-NEXT: [[TMP13:%.*]] = bitcast [6 x i64]* [[DOTOFFLOAD_SIZES]] to i8* 4752 // CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP13]], i8* align 8 bitcast ([6 x i64]* @.offload_sizes.13 to i8*), i64 48, i1 false) 4753 // CHECK5-NEXT: [[TMP14:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 4754 // CHECK5-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to %struct.S1** 4755 // CHECK5-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP15]], align 8 4756 // CHECK5-NEXT: [[TMP16:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 4757 // CHECK5-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to double** 4758 // CHECK5-NEXT: store double* [[A]], double** [[TMP17]], align 8 4759 // CHECK5-NEXT: [[TMP18:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 4760 // CHECK5-NEXT: store i8* null, i8** [[TMP18]], align 8 4761 // CHECK5-NEXT: [[TMP19:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 4762 // CHECK5-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64* 4763 // CHECK5-NEXT: store i64 [[TMP7]], i64* [[TMP20]], align 8 4764 // CHECK5-NEXT: [[TMP21:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 4765 // CHECK5-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i64* 4766 // CHECK5-NEXT: store i64 [[TMP7]], i64* [[TMP22]], align 8 4767 // CHECK5-NEXT: [[TMP23:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 4768 // CHECK5-NEXT: store i8* null, i8** [[TMP23]], align 8 4769 // CHECK5-NEXT: [[TMP24:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 4770 // CHECK5-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i64* 4771 // CHECK5-NEXT: store i64 2, i64* [[TMP25]], align 8 4772 // CHECK5-NEXT: [[TMP26:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 4773 // CHECK5-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64* 4774 // CHECK5-NEXT: store i64 2, i64* [[TMP27]], align 8 4775 // CHECK5-NEXT: [[TMP28:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 4776 // CHECK5-NEXT: store i8* null, i8** [[TMP28]], align 8 4777 // CHECK5-NEXT: [[TMP29:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 4778 // CHECK5-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i64* 4779 // CHECK5-NEXT: store i64 [[TMP2]], i64* [[TMP30]], align 8 4780 // CHECK5-NEXT: [[TMP31:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 4781 // CHECK5-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i64* 4782 // CHECK5-NEXT: store i64 [[TMP2]], i64* [[TMP32]], align 8 4783 // CHECK5-NEXT: [[TMP33:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 4784 // CHECK5-NEXT: store i8* null, i8** [[TMP33]], align 8 4785 // CHECK5-NEXT: [[TMP34:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 4786 // CHECK5-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i16** 4787 // CHECK5-NEXT: store i16* [[VLA]], i16** [[TMP35]], align 8 4788 // CHECK5-NEXT: [[TMP36:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 4789 // CHECK5-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i16** 4790 // CHECK5-NEXT: store i16* [[VLA]], i16** [[TMP37]], align 8 4791 // CHECK5-NEXT: [[TMP38:%.*]] = getelementptr inbounds [6 x i64], [6 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 4792 // CHECK5-NEXT: store i64 [[TMP12]], i64* [[TMP38]], align 8 4793 // CHECK5-NEXT: [[TMP39:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 4794 // CHECK5-NEXT: store i8* null, i8** [[TMP39]], align 8 4795 // CHECK5-NEXT: [[TMP40:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 5 4796 // CHECK5-NEXT: [[TMP41:%.*]] = bitcast i8** [[TMP40]] to i64* 4797 // CHECK5-NEXT: store i64 [[TMP9]], i64* [[TMP41]], align 8 4798 // CHECK5-NEXT: [[TMP42:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 5 4799 // CHECK5-NEXT: [[TMP43:%.*]] = bitcast i8** [[TMP42]] to i64* 4800 // CHECK5-NEXT: store i64 [[TMP9]], i64* [[TMP43]], align 8 4801 // CHECK5-NEXT: [[TMP44:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 5 4802 // CHECK5-NEXT: store i8* null, i8** [[TMP44]], align 8 4803 // CHECK5-NEXT: [[TMP45:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 4804 // CHECK5-NEXT: [[TMP46:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 4805 // CHECK5-NEXT: [[TMP47:%.*]] = getelementptr inbounds [6 x i64], [6 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 4806 // CHECK5-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) 4807 // CHECK5-NEXT: [[TMP48:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215.region_id, i32 6, i8** [[TMP45]], i8** [[TMP46]], i64* [[TMP47]], i64* getelementptr inbounds ([6 x i64], [6 x i64]* @.offload_maptypes.14, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1) 4808 // CHECK5-NEXT: [[TMP49:%.*]] = icmp ne i32 [[TMP48]], 0 4809 // CHECK5-NEXT: br i1 [[TMP49]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 4810 // CHECK5: omp_offload.failed: 4811 // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215(%struct.S1* [[THIS1]], i64 [[TMP7]], i64 2, i64 [[TMP2]], i16* [[VLA]], i64 [[TMP9]]) #[[ATTR4]] 4812 // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]] 4813 // CHECK5: omp_offload.cont: 4814 // CHECK5-NEXT: br label [[OMP_IF_END:%.*]] 4815 // CHECK5: omp_if.else: 4816 // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215(%struct.S1* [[THIS1]], i64 [[TMP7]], i64 2, i64 [[TMP2]], i16* [[VLA]], i64 [[TMP9]]) #[[ATTR4]] 4817 // CHECK5-NEXT: br label [[OMP_IF_END]] 4818 // CHECK5: omp_if.end: 4819 // CHECK5-NEXT: [[TMP50:%.*]] = mul nsw i64 1, [[TMP2]] 4820 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP50]] 4821 // CHECK5-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 4822 // CHECK5-NEXT: [[TMP51:%.*]] = load i16, i16* [[ARRAYIDX5]], align 2 4823 // CHECK5-NEXT: [[CONV6:%.*]] = sext i16 [[TMP51]] to i32 4824 // CHECK5-NEXT: [[TMP52:%.*]] = load i32, i32* [[B]], align 4 4825 // CHECK5-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], [[TMP52]] 4826 // CHECK5-NEXT: [[TMP53:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 4827 // CHECK5-NEXT: call void @llvm.stackrestore(i8* [[TMP53]]) 4828 // CHECK5-NEXT: ret i32 [[ADD7]] 4829 // 4830 // 4831 // CHECK5-LABEL: define {{[^@]+}}@_ZL7fstatici 4832 // CHECK5-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { 4833 // CHECK5-NEXT: entry: 4834 // CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 4835 // CHECK5-NEXT: [[A:%.*]] = alloca i32, align 4 4836 // CHECK5-NEXT: [[AA:%.*]] = alloca i16, align 2 4837 // CHECK5-NEXT: [[AAA:%.*]] = alloca i8, align 1 4838 // CHECK5-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 4839 // CHECK5-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 4840 // CHECK5-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 4841 // CHECK5-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 4842 // CHECK5-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 4843 // CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8 4844 // CHECK5-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8 4845 // CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8 4846 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 4847 // CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 4848 // CHECK5-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4 4849 // CHECK5-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i32, align 4 4850 // CHECK5-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 4851 // CHECK5-NEXT: store i32 0, i32* [[A]], align 4 4852 // CHECK5-NEXT: store i16 0, i16* [[AA]], align 2 4853 // CHECK5-NEXT: store i8 0, i8* [[AAA]], align 1 4854 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 4855 // CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* 4856 // CHECK5-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 4857 // CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 4858 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 4859 // CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32* 4860 // CHECK5-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4 4861 // CHECK5-NEXT: [[TMP3:%.*]] = load i64, i64* [[N_CASTED]], align 8 4862 // CHECK5-NEXT: [[TMP4:%.*]] = load i16, i16* [[AA]], align 2 4863 // CHECK5-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 4864 // CHECK5-NEXT: store i16 [[TMP4]], i16* [[CONV2]], align 2 4865 // CHECK5-NEXT: [[TMP5:%.*]] = load i64, i64* [[AA_CASTED]], align 8 4866 // CHECK5-NEXT: [[TMP6:%.*]] = load i8, i8* [[AAA]], align 1 4867 // CHECK5-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* 4868 // CHECK5-NEXT: store i8 [[TMP6]], i8* [[CONV3]], align 1 4869 // CHECK5-NEXT: [[TMP7:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 4870 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[N_ADDR]], align 4 4871 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP8]], 50 4872 // CHECK5-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 4873 // CHECK5: omp_if.then: 4874 // CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 4875 // CHECK5-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* 4876 // CHECK5-NEXT: store i64 [[TMP1]], i64* [[TMP10]], align 8 4877 // CHECK5-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 4878 // CHECK5-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64* 4879 // CHECK5-NEXT: store i64 [[TMP1]], i64* [[TMP12]], align 8 4880 // CHECK5-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 4881 // CHECK5-NEXT: store i8* null, i8** [[TMP13]], align 8 4882 // CHECK5-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 4883 // CHECK5-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* 4884 // CHECK5-NEXT: store i64 [[TMP3]], i64* [[TMP15]], align 8 4885 // CHECK5-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 4886 // CHECK5-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64* 4887 // CHECK5-NEXT: store i64 [[TMP3]], i64* [[TMP17]], align 8 4888 // CHECK5-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 4889 // CHECK5-NEXT: store i8* null, i8** [[TMP18]], align 8 4890 // CHECK5-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 4891 // CHECK5-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64* 4892 // CHECK5-NEXT: store i64 [[TMP5]], i64* [[TMP20]], align 8 4893 // CHECK5-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 4894 // CHECK5-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i64* 4895 // CHECK5-NEXT: store i64 [[TMP5]], i64* [[TMP22]], align 8 4896 // CHECK5-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 4897 // CHECK5-NEXT: store i8* null, i8** [[TMP23]], align 8 4898 // CHECK5-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 4899 // CHECK5-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i64* 4900 // CHECK5-NEXT: store i64 [[TMP7]], i64* [[TMP25]], align 8 4901 // CHECK5-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 4902 // CHECK5-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64* 4903 // CHECK5-NEXT: store i64 [[TMP7]], i64* [[TMP27]], align 8 4904 // CHECK5-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 4905 // CHECK5-NEXT: store i8* null, i8** [[TMP28]], align 8 4906 // CHECK5-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 4907 // CHECK5-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to [10 x i32]** 4908 // CHECK5-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP30]], align 8 4909 // CHECK5-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 4910 // CHECK5-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to [10 x i32]** 4911 // CHECK5-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP32]], align 8 4912 // CHECK5-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 4913 // CHECK5-NEXT: store i8* null, i8** [[TMP33]], align 8 4914 // CHECK5-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 4915 // CHECK5-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 4916 // CHECK5-NEXT: [[TMP36:%.*]] = load i32, i32* [[A]], align 4 4917 // CHECK5-NEXT: store i32 [[TMP36]], i32* [[DOTCAPTURE_EXPR_]], align 4 4918 // CHECK5-NEXT: [[TMP37:%.*]] = load i32, i32* [[N_ADDR]], align 4 4919 // CHECK5-NEXT: store i32 [[TMP37]], i32* [[DOTCAPTURE_EXPR_4]], align 4 4920 // CHECK5-NEXT: [[TMP38:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 4921 // CHECK5-NEXT: [[TMP39:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 4922 // CHECK5-NEXT: [[SUB:%.*]] = sub i32 [[TMP38]], [[TMP39]] 4923 // CHECK5-NEXT: [[SUB6:%.*]] = sub i32 [[SUB]], 1 4924 // CHECK5-NEXT: [[ADD:%.*]] = add i32 [[SUB6]], 1 4925 // CHECK5-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 4926 // CHECK5-NEXT: [[SUB7:%.*]] = sub i32 [[DIV]], 1 4927 // CHECK5-NEXT: store i32 [[SUB7]], i32* [[DOTCAPTURE_EXPR_5]], align 4 4928 // CHECK5-NEXT: [[TMP40:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 4929 // CHECK5-NEXT: [[ADD8:%.*]] = add i32 [[TMP40]], 1 4930 // CHECK5-NEXT: [[TMP41:%.*]] = zext i32 [[ADD8]] to i64 4931 // CHECK5-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 [[TMP41]]) 4932 // CHECK5-NEXT: [[TMP42:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197.region_id, i32 5, i8** [[TMP34]], i8** [[TMP35]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes.16, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.17, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1) 4933 // CHECK5-NEXT: [[TMP43:%.*]] = icmp ne i32 [[TMP42]], 0 4934 // CHECK5-NEXT: br i1 [[TMP43]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 4935 // CHECK5: omp_offload.failed: 4936 // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], i64 [[TMP7]], [10 x i32]* [[B]]) #[[ATTR4]] 4937 // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]] 4938 // CHECK5: omp_offload.cont: 4939 // CHECK5-NEXT: br label [[OMP_IF_END:%.*]] 4940 // CHECK5: omp_if.else: 4941 // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], i64 [[TMP7]], [10 x i32]* [[B]]) #[[ATTR4]] 4942 // CHECK5-NEXT: br label [[OMP_IF_END]] 4943 // CHECK5: omp_if.end: 4944 // CHECK5-NEXT: [[TMP44:%.*]] = load i32, i32* [[A]], align 4 4945 // CHECK5-NEXT: ret i32 [[TMP44]] 4946 // 4947 // 4948 // CHECK5-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 4949 // CHECK5-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat { 4950 // CHECK5-NEXT: entry: 4951 // CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 4952 // CHECK5-NEXT: [[A:%.*]] = alloca i32, align 4 4953 // CHECK5-NEXT: [[AA:%.*]] = alloca i16, align 2 4954 // CHECK5-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 4955 // CHECK5-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 4956 // CHECK5-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 4957 // CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 4958 // CHECK5-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 4959 // CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 4960 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 4961 // CHECK5-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 4962 // CHECK5-NEXT: store i32 0, i32* [[A]], align 4 4963 // CHECK5-NEXT: store i16 0, i16* [[AA]], align 2 4964 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 4965 // CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* 4966 // CHECK5-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 4967 // CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 4968 // CHECK5-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 4969 // CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 4970 // CHECK5-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 4971 // CHECK5-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 4972 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 4973 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40 4974 // CHECK5-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 4975 // CHECK5: omp_if.then: 4976 // CHECK5-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 4977 // CHECK5-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64* 4978 // CHECK5-NEXT: store i64 [[TMP1]], i64* [[TMP6]], align 8 4979 // CHECK5-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 4980 // CHECK5-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* 4981 // CHECK5-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8 4982 // CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 4983 // CHECK5-NEXT: store i8* null, i8** [[TMP9]], align 8 4984 // CHECK5-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 4985 // CHECK5-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i64* 4986 // CHECK5-NEXT: store i64 [[TMP3]], i64* [[TMP11]], align 8 4987 // CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 4988 // CHECK5-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* 4989 // CHECK5-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8 4990 // CHECK5-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 4991 // CHECK5-NEXT: store i8* null, i8** [[TMP14]], align 8 4992 // CHECK5-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 4993 // CHECK5-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]** 4994 // CHECK5-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 8 4995 // CHECK5-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 4996 // CHECK5-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]** 4997 // CHECK5-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 8 4998 // CHECK5-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 4999 // CHECK5-NEXT: store i8* null, i8** [[TMP19]], align 8 5000 // CHECK5-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 5001 // CHECK5-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 5002 // CHECK5-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) 5003 // CHECK5-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.19, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.20, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1) 5004 // CHECK5-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 5005 // CHECK5-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 5006 // CHECK5: omp_offload.failed: 5007 // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]] 5008 // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]] 5009 // CHECK5: omp_offload.cont: 5010 // CHECK5-NEXT: br label [[OMP_IF_END:%.*]] 5011 // CHECK5: omp_if.else: 5012 // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]] 5013 // CHECK5-NEXT: br label [[OMP_IF_END]] 5014 // CHECK5: omp_if.end: 5015 // CHECK5-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4 5016 // CHECK5-NEXT: ret i32 [[TMP24]] 5017 // 5018 // 5019 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215 5020 // CHECK5-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { 5021 // CHECK5-NEXT: entry: 5022 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 5023 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 5024 // CHECK5-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 5025 // CHECK5-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 5026 // CHECK5-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 5027 // CHECK5-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 5028 // CHECK5-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 5029 // CHECK5-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 5030 // CHECK5-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 5031 // CHECK5-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 5032 // CHECK5-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 5033 // CHECK5-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 5034 // CHECK5-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 5035 // CHECK5-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 5036 // CHECK5-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 5037 // CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 5038 // CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 5039 // CHECK5-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 5040 // CHECK5-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 5041 // CHECK5-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* 5042 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4 5043 // CHECK5-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i32* 5044 // CHECK5-NEXT: store i32 [[TMP4]], i32* [[CONV4]], align 4 5045 // CHECK5-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 5046 // CHECK5-NEXT: [[TMP6:%.*]] = load i8, i8* [[CONV3]], align 1 5047 // CHECK5-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP6]] to i1 5048 // CHECK5-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* 5049 // CHECK5-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 5050 // CHECK5-NEXT: store i8 [[FROMBOOL]], i8* [[CONV5]], align 1 5051 // CHECK5-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 5052 // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*, i64)* @.omp_outlined..12 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]], i64 [[TMP7]]) 5053 // CHECK5-NEXT: ret void 5054 // 5055 // 5056 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..12 5057 // CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { 5058 // CHECK5-NEXT: entry: 5059 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 5060 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 5061 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 5062 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 5063 // CHECK5-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 5064 // CHECK5-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 5065 // CHECK5-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 5066 // CHECK5-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 5067 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 5068 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 5069 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 5070 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 5071 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 5072 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 5073 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 5074 // CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 5075 // CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 5076 // CHECK5-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 5077 // CHECK5-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 5078 // CHECK5-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 5079 // CHECK5-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 5080 // CHECK5-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 5081 // CHECK5-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 5082 // CHECK5-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 5083 // CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 5084 // CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 5085 // CHECK5-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 5086 // CHECK5-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 5087 // CHECK5-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* 5088 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 5089 // CHECK5-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 5090 // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 5091 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 5092 // CHECK5-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 5093 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 5094 // CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 5095 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 5096 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 9 5097 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 5098 // CHECK5: cond.true: 5099 // CHECK5-NEXT: br label [[COND_END:%.*]] 5100 // CHECK5: cond.false: 5101 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 5102 // CHECK5-NEXT: br label [[COND_END]] 5103 // CHECK5: cond.end: 5104 // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 5105 // CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 5106 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 5107 // CHECK5-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 5108 // CHECK5-NEXT: [[TMP9:%.*]] = load i8, i8* [[CONV3]], align 1 5109 // CHECK5-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP9]] to i1 5110 // CHECK5-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 5111 // CHECK5: omp_if.then: 5112 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 5113 // CHECK5: omp.inner.for.cond: 5114 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39 5115 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !39 5116 // CHECK5-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]] 5117 // CHECK5-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 5118 // CHECK5: omp.inner.for.body: 5119 // CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39 5120 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1 5121 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 5122 // CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !39 5123 // CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !39 5124 // CHECK5-NEXT: [[CONV5:%.*]] = sitofp i32 [[TMP13]] to double 5125 // CHECK5-NEXT: [[ADD6:%.*]] = fadd double [[CONV5]], 1.500000e+00 5126 // CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 5127 // CHECK5-NEXT: store double [[ADD6]], double* [[A]], align 8, !llvm.access.group !39 5128 // CHECK5-NEXT: [[A7:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 5129 // CHECK5-NEXT: [[TMP14:%.*]] = load double, double* [[A7]], align 8, !llvm.access.group !39 5130 // CHECK5-NEXT: [[INC:%.*]] = fadd double [[TMP14]], 1.000000e+00 5131 // CHECK5-NEXT: store double [[INC]], double* [[A7]], align 8, !llvm.access.group !39 5132 // CHECK5-NEXT: [[CONV8:%.*]] = fptosi double [[INC]] to i16 5133 // CHECK5-NEXT: [[TMP15:%.*]] = mul nsw i64 1, [[TMP2]] 5134 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP15]] 5135 // CHECK5-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 5136 // CHECK5-NEXT: store i16 [[CONV8]], i16* [[ARRAYIDX9]], align 2, !llvm.access.group !39 5137 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 5138 // CHECK5: omp.body.continue: 5139 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 5140 // CHECK5: omp.inner.for.inc: 5141 // CHECK5-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39 5142 // CHECK5-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP16]], 1 5143 // CHECK5-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39 5144 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP40:![0-9]+]] 5145 // CHECK5: omp.inner.for.end: 5146 // CHECK5-NEXT: br label [[OMP_IF_END:%.*]] 5147 // CHECK5: omp_if.else: 5148 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND11:%.*]] 5149 // CHECK5: omp.inner.for.cond11: 5150 // CHECK5-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 5151 // CHECK5-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 5152 // CHECK5-NEXT: [[CMP12:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]] 5153 // CHECK5-NEXT: br i1 [[CMP12]], label [[OMP_INNER_FOR_BODY13:%.*]], label [[OMP_INNER_FOR_END27:%.*]] 5154 // CHECK5: omp.inner.for.body13: 5155 // CHECK5-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 5156 // CHECK5-NEXT: [[MUL14:%.*]] = mul nsw i32 [[TMP19]], 1 5157 // CHECK5-NEXT: [[ADD15:%.*]] = add nsw i32 0, [[MUL14]] 5158 // CHECK5-NEXT: store i32 [[ADD15]], i32* [[I]], align 4 5159 // CHECK5-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 4 5160 // CHECK5-NEXT: [[CONV16:%.*]] = sitofp i32 [[TMP20]] to double 5161 // CHECK5-NEXT: [[ADD17:%.*]] = fadd double [[CONV16]], 1.500000e+00 5162 // CHECK5-NEXT: [[A18:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 5163 // CHECK5-NEXT: store double [[ADD17]], double* [[A18]], align 8 5164 // CHECK5-NEXT: [[A19:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 5165 // CHECK5-NEXT: [[TMP21:%.*]] = load double, double* [[A19]], align 8 5166 // CHECK5-NEXT: [[INC20:%.*]] = fadd double [[TMP21]], 1.000000e+00 5167 // CHECK5-NEXT: store double [[INC20]], double* [[A19]], align 8 5168 // CHECK5-NEXT: [[CONV21:%.*]] = fptosi double [[INC20]] to i16 5169 // CHECK5-NEXT: [[TMP22:%.*]] = mul nsw i64 1, [[TMP2]] 5170 // CHECK5-NEXT: [[ARRAYIDX22:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP22]] 5171 // CHECK5-NEXT: [[ARRAYIDX23:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX22]], i64 1 5172 // CHECK5-NEXT: store i16 [[CONV21]], i16* [[ARRAYIDX23]], align 2 5173 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE24:%.*]] 5174 // CHECK5: omp.body.continue24: 5175 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC25:%.*]] 5176 // CHECK5: omp.inner.for.inc25: 5177 // CHECK5-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 5178 // CHECK5-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP23]], 1 5179 // CHECK5-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_IV]], align 4 5180 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND11]], !llvm.loop [[LOOP42:![0-9]+]] 5181 // CHECK5: omp.inner.for.end27: 5182 // CHECK5-NEXT: br label [[OMP_IF_END]] 5183 // CHECK5: omp_if.end: 5184 // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 5185 // CHECK5: omp.loop.exit: 5186 // CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 5187 // CHECK5-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 5188 // CHECK5-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 5189 // CHECK5-NEXT: br i1 [[TMP25]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 5190 // CHECK5: .omp.final.then: 5191 // CHECK5-NEXT: store i32 10, i32* [[I]], align 4 5192 // CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]] 5193 // CHECK5: .omp.final.done: 5194 // CHECK5-NEXT: ret void 5195 // 5196 // 5197 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197 5198 // CHECK5-SAME: (i64 noundef [[A:%.*]], i64 noundef [[N:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 5199 // CHECK5-NEXT: entry: 5200 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 5201 // CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 5202 // CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 5203 // CHECK5-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 5204 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 5205 // CHECK5-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 5206 // CHECK5-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 5207 // CHECK5-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 5208 // CHECK5-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 5209 // CHECK5-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 5210 // CHECK5-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 5211 // CHECK5-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 5212 // CHECK5-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 5213 // CHECK5-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 5214 // CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 5215 // CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32* 5216 // CHECK5-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 5217 // CHECK5-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 5218 // CHECK5-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 5219 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 5220 // CHECK5-NEXT: [[CONV4:%.*]] = bitcast i64* [[A_CASTED]] to i32* 5221 // CHECK5-NEXT: store i32 [[TMP1]], i32* [[CONV4]], align 4 5222 // CHECK5-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 5223 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 4 5224 // CHECK5-NEXT: [[CONV5:%.*]] = bitcast i64* [[N_CASTED]] to i32* 5225 // CHECK5-NEXT: store i32 [[TMP3]], i32* [[CONV5]], align 4 5226 // CHECK5-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8 5227 // CHECK5-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV2]], align 2 5228 // CHECK5-NEXT: [[CONV6:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 5229 // CHECK5-NEXT: store i16 [[TMP5]], i16* [[CONV6]], align 2 5230 // CHECK5-NEXT: [[TMP6:%.*]] = load i64, i64* [[AA_CASTED]], align 8 5231 // CHECK5-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV3]], align 1 5232 // CHECK5-NEXT: [[CONV7:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* 5233 // CHECK5-NEXT: store i8 [[TMP7]], i8* [[CONV7]], align 1 5234 // CHECK5-NEXT: [[TMP8:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 5235 // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, [10 x i32]*)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]], [10 x i32]* [[TMP0]]) 5236 // CHECK5-NEXT: ret void 5237 // 5238 // 5239 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..15 5240 // CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[N:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { 5241 // CHECK5-NEXT: entry: 5242 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 5243 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 5244 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 5245 // CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 5246 // CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 5247 // CHECK5-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 5248 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 5249 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 5250 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 5251 // CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 5252 // CHECK5-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4 5253 // CHECK5-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i32, align 4 5254 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 5255 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 5256 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 5257 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 5258 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 5259 // CHECK5-NEXT: [[I8:%.*]] = alloca i32, align 4 5260 // CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 5261 // CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 5262 // CHECK5-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 5263 // CHECK5-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 5264 // CHECK5-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 5265 // CHECK5-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 5266 // CHECK5-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 5267 // CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 5268 // CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32* 5269 // CHECK5-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 5270 // CHECK5-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 5271 // CHECK5-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 5272 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 5273 // CHECK5-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 5274 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4 5275 // CHECK5-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_4]], align 4 5276 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 5277 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 5278 // CHECK5-NEXT: [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]] 5279 // CHECK5-NEXT: [[SUB6:%.*]] = sub i32 [[SUB]], 1 5280 // CHECK5-NEXT: [[ADD:%.*]] = add i32 [[SUB6]], 1 5281 // CHECK5-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 5282 // CHECK5-NEXT: [[SUB7:%.*]] = sub i32 [[DIV]], 1 5283 // CHECK5-NEXT: store i32 [[SUB7]], i32* [[DOTCAPTURE_EXPR_5]], align 4 5284 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 5285 // CHECK5-NEXT: store i32 [[TMP5]], i32* [[I]], align 4 5286 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 5287 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 5288 // CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]] 5289 // CHECK5-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] 5290 // CHECK5: omp.precond.then: 5291 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 5292 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 5293 // CHECK5-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_UB]], align 4 5294 // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 5295 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 5296 // CHECK5-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 5297 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 5298 // CHECK5-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 5299 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 5300 // CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 5301 // CHECK5-NEXT: [[CMP9:%.*]] = icmp ugt i32 [[TMP11]], [[TMP12]] 5302 // CHECK5-NEXT: br i1 [[CMP9]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 5303 // CHECK5: cond.true: 5304 // CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 5305 // CHECK5-NEXT: br label [[COND_END:%.*]] 5306 // CHECK5: cond.false: 5307 // CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 5308 // CHECK5-NEXT: br label [[COND_END]] 5309 // CHECK5: cond.end: 5310 // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ] 5311 // CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 5312 // CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 5313 // CHECK5-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4 5314 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 5315 // CHECK5: omp.inner.for.cond: 5316 // CHECK5-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !44 5317 // CHECK5-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !44 5318 // CHECK5-NEXT: [[ADD10:%.*]] = add i32 [[TMP17]], 1 5319 // CHECK5-NEXT: [[CMP11:%.*]] = icmp ult i32 [[TMP16]], [[ADD10]] 5320 // CHECK5-NEXT: br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 5321 // CHECK5: omp.inner.for.body: 5322 // CHECK5-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group !44 5323 // CHECK5-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !44 5324 // CHECK5-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 1 5325 // CHECK5-NEXT: [[ADD12:%.*]] = add i32 [[TMP18]], [[MUL]] 5326 // CHECK5-NEXT: store i32 [[ADD12]], i32* [[I8]], align 4, !llvm.access.group !44 5327 // CHECK5-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !44 5328 // CHECK5-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP20]], 1 5329 // CHECK5-NEXT: store i32 [[ADD13]], i32* [[CONV]], align 4, !llvm.access.group !44 5330 // CHECK5-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV2]], align 2, !llvm.access.group !44 5331 // CHECK5-NEXT: [[CONV14:%.*]] = sext i16 [[TMP21]] to i32 5332 // CHECK5-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1 5333 // CHECK5-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16 5334 // CHECK5-NEXT: store i16 [[CONV16]], i16* [[CONV2]], align 2, !llvm.access.group !44 5335 // CHECK5-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV3]], align 1, !llvm.access.group !44 5336 // CHECK5-NEXT: [[CONV17:%.*]] = sext i8 [[TMP22]] to i32 5337 // CHECK5-NEXT: [[ADD18:%.*]] = add nsw i32 [[CONV17]], 1 5338 // CHECK5-NEXT: [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8 5339 // CHECK5-NEXT: store i8 [[CONV19]], i8* [[CONV3]], align 1, !llvm.access.group !44 5340 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 5341 // CHECK5-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !44 5342 // CHECK5-NEXT: [[ADD20:%.*]] = add nsw i32 [[TMP23]], 1 5343 // CHECK5-NEXT: store i32 [[ADD20]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !44 5344 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 5345 // CHECK5: omp.body.continue: 5346 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 5347 // CHECK5: omp.inner.for.inc: 5348 // CHECK5-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !44 5349 // CHECK5-NEXT: [[ADD21:%.*]] = add i32 [[TMP24]], 1 5350 // CHECK5-NEXT: store i32 [[ADD21]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !44 5351 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP45:![0-9]+]] 5352 // CHECK5: omp.inner.for.end: 5353 // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 5354 // CHECK5: omp.loop.exit: 5355 // CHECK5-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 5356 // CHECK5-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 5357 // CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) 5358 // CHECK5-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 5359 // CHECK5-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0 5360 // CHECK5-NEXT: br i1 [[TMP28]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 5361 // CHECK5: .omp.final.then: 5362 // CHECK5-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 5363 // CHECK5-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 5364 // CHECK5-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 5365 // CHECK5-NEXT: [[SUB22:%.*]] = sub i32 [[TMP30]], [[TMP31]] 5366 // CHECK5-NEXT: [[SUB23:%.*]] = sub i32 [[SUB22]], 1 5367 // CHECK5-NEXT: [[ADD24:%.*]] = add i32 [[SUB23]], 1 5368 // CHECK5-NEXT: [[DIV25:%.*]] = udiv i32 [[ADD24]], 1 5369 // CHECK5-NEXT: [[MUL26:%.*]] = mul i32 [[DIV25]], 1 5370 // CHECK5-NEXT: [[ADD27:%.*]] = add i32 [[TMP29]], [[MUL26]] 5371 // CHECK5-NEXT: store i32 [[ADD27]], i32* [[I8]], align 4 5372 // CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]] 5373 // CHECK5: .omp.final.done: 5374 // CHECK5-NEXT: br label [[OMP_PRECOND_END]] 5375 // CHECK5: omp.precond.end: 5376 // CHECK5-NEXT: ret void 5377 // 5378 // 5379 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180 5380 // CHECK5-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 5381 // CHECK5-NEXT: entry: 5382 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 5383 // CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 5384 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 5385 // CHECK5-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 5386 // CHECK5-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 5387 // CHECK5-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 5388 // CHECK5-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 5389 // CHECK5-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 5390 // CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 5391 // CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 5392 // CHECK5-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 5393 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 5394 // CHECK5-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* 5395 // CHECK5-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 5396 // CHECK5-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 5397 // CHECK5-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 5398 // CHECK5-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 5399 // CHECK5-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 5400 // CHECK5-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 5401 // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..18 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) 5402 // CHECK5-NEXT: ret void 5403 // 5404 // 5405 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..18 5406 // CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { 5407 // CHECK5-NEXT: entry: 5408 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 5409 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 5410 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 5411 // CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 5412 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 5413 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 5414 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 5415 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 5416 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 5417 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 5418 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 5419 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 5420 // CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 5421 // CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 5422 // CHECK5-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 5423 // CHECK5-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 5424 // CHECK5-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 5425 // CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 5426 // CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 5427 // CHECK5-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 5428 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 5429 // CHECK5-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 5430 // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 5431 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 5432 // CHECK5-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 5433 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 5434 // CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 5435 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 5436 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 5437 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 5438 // CHECK5: cond.true: 5439 // CHECK5-NEXT: br label [[COND_END:%.*]] 5440 // CHECK5: cond.false: 5441 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 5442 // CHECK5-NEXT: br label [[COND_END]] 5443 // CHECK5: cond.end: 5444 // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 5445 // CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 5446 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 5447 // CHECK5-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 5448 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 5449 // CHECK5: omp.inner.for.cond: 5450 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !47 5451 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !47 5452 // CHECK5-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] 5453 // CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 5454 // CHECK5: omp.inner.for.body: 5455 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !47 5456 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 5457 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 5458 // CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !47 5459 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !47 5460 // CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1 5461 // CHECK5-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4, !llvm.access.group !47 5462 // CHECK5-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 2, !llvm.access.group !47 5463 // CHECK5-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32 5464 // CHECK5-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 5465 // CHECK5-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 5466 // CHECK5-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2, !llvm.access.group !47 5467 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 5468 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !47 5469 // CHECK5-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1 5470 // CHECK5-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !47 5471 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 5472 // CHECK5: omp.body.continue: 5473 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 5474 // CHECK5: omp.inner.for.inc: 5475 // CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !47 5476 // CHECK5-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP12]], 1 5477 // CHECK5-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !47 5478 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP48:![0-9]+]] 5479 // CHECK5: omp.inner.for.end: 5480 // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 5481 // CHECK5: omp.loop.exit: 5482 // CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) 5483 // CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 5484 // CHECK5-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 5485 // CHECK5-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 5486 // CHECK5: .omp.final.then: 5487 // CHECK5-NEXT: store i32 10, i32* [[I]], align 4 5488 // CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]] 5489 // CHECK5: .omp.final.done: 5490 // CHECK5-NEXT: ret void 5491 // 5492 // 5493 // CHECK5-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 5494 // CHECK5-SAME: () #[[ATTR5]] { 5495 // CHECK5-NEXT: entry: 5496 // CHECK5-NEXT: call void @__tgt_register_requires(i64 1) 5497 // CHECK5-NEXT: ret void 5498 // 5499 // 5500 // CHECK7-LABEL: define {{[^@]+}}@_Z3fooi 5501 // CHECK7-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0:[0-9]+]] { 5502 // CHECK7-NEXT: entry: 5503 // CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 5504 // CHECK7-NEXT: [[A:%.*]] = alloca i32, align 4 5505 // CHECK7-NEXT: [[AA:%.*]] = alloca i16, align 2 5506 // CHECK7-NEXT: [[B:%.*]] = alloca [10 x float], align 4 5507 // CHECK7-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 5508 // CHECK7-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 5509 // CHECK7-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 5510 // CHECK7-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 5511 // CHECK7-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 5512 // CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 5513 // CHECK7-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 5514 // CHECK7-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 5515 // CHECK7-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 5516 // CHECK7-NEXT: [[DOTCAPTURE_EXPR__CASTED3:%.*]] = alloca i32, align 4 5517 // CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 5518 // CHECK7-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 5519 // CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 5520 // CHECK7-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4 5521 // CHECK7-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 5522 // CHECK7-NEXT: [[AA_CASTED4:%.*]] = alloca i32, align 4 5523 // CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS6:%.*]] = alloca [1 x i8*], align 4 5524 // CHECK7-NEXT: [[DOTOFFLOAD_PTRS7:%.*]] = alloca [1 x i8*], align 4 5525 // CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS8:%.*]] = alloca [1 x i8*], align 4 5526 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 5527 // CHECK7-NEXT: [[A_CASTED9:%.*]] = alloca i32, align 4 5528 // CHECK7-NEXT: [[AA_CASTED10:%.*]] = alloca i32, align 4 5529 // CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS12:%.*]] = alloca [2 x i8*], align 4 5530 // CHECK7-NEXT: [[DOTOFFLOAD_PTRS13:%.*]] = alloca [2 x i8*], align 4 5531 // CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS14:%.*]] = alloca [2 x i8*], align 4 5532 // CHECK7-NEXT: [[_TMP15:%.*]] = alloca i32, align 4 5533 // CHECK7-NEXT: [[A_CASTED18:%.*]] = alloca i32, align 4 5534 // CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS21:%.*]] = alloca [9 x i8*], align 4 5535 // CHECK7-NEXT: [[DOTOFFLOAD_PTRS22:%.*]] = alloca [9 x i8*], align 4 5536 // CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS23:%.*]] = alloca [9 x i8*], align 4 5537 // CHECK7-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [9 x i64], align 4 5538 // CHECK7-NEXT: [[_TMP24:%.*]] = alloca i32, align 4 5539 // CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) 5540 // CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 5541 // CHECK7-NEXT: store i32 0, i32* [[A]], align 4 5542 // CHECK7-NEXT: store i16 0, i16* [[AA]], align 2 5543 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 5544 // CHECK7-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() 5545 // CHECK7-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 5546 // CHECK7-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP1]], align 4 5547 // CHECK7-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 5548 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 5549 // CHECK7-NEXT: [[TMP4:%.*]] = mul nuw i32 5, [[TMP3]] 5550 // CHECK7-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP4]], align 8 5551 // CHECK7-NEXT: store i32 [[TMP3]], i32* [[__VLA_EXPR1]], align 4 5552 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 5553 // CHECK7-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_]], align 4 5554 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 5555 // CHECK7-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_2]], align 4 5556 // CHECK7-NEXT: [[TMP7:%.*]] = load i16, i16* [[AA]], align 2 5557 // CHECK7-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 5558 // CHECK7-NEXT: store i16 [[TMP7]], i16* [[CONV]], align 2 5559 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[AA_CASTED]], align 4 5560 // CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 5561 // CHECK7-NEXT: store i32 [[TMP9]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 5562 // CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 5563 // CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 5564 // CHECK7-NEXT: store i32 [[TMP11]], i32* [[DOTCAPTURE_EXPR__CASTED3]], align 4 5565 // CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED3]], align 4 5566 // CHECK7-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 5567 // CHECK7-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i32* 5568 // CHECK7-NEXT: store i32 [[TMP8]], i32* [[TMP14]], align 4 5569 // CHECK7-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 5570 // CHECK7-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i32* 5571 // CHECK7-NEXT: store i32 [[TMP8]], i32* [[TMP16]], align 4 5572 // CHECK7-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 5573 // CHECK7-NEXT: store i8* null, i8** [[TMP17]], align 4 5574 // CHECK7-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 5575 // CHECK7-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32* 5576 // CHECK7-NEXT: store i32 [[TMP10]], i32* [[TMP19]], align 4 5577 // CHECK7-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 5578 // CHECK7-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32* 5579 // CHECK7-NEXT: store i32 [[TMP10]], i32* [[TMP21]], align 4 5580 // CHECK7-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 5581 // CHECK7-NEXT: store i8* null, i8** [[TMP22]], align 4 5582 // CHECK7-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 5583 // CHECK7-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i32* 5584 // CHECK7-NEXT: store i32 [[TMP12]], i32* [[TMP24]], align 4 5585 // CHECK7-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 5586 // CHECK7-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i32* 5587 // CHECK7-NEXT: store i32 [[TMP12]], i32* [[TMP26]], align 4 5588 // CHECK7-NEXT: [[TMP27:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 5589 // CHECK7-NEXT: store i8* null, i8** [[TMP27]], align 4 5590 // CHECK7-NEXT: [[TMP28:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 5591 // CHECK7-NEXT: [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 5592 // CHECK7-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 0 5593 // CHECK7-NEXT: [[TMP31:%.*]] = load i16, i16* [[AA]], align 2 5594 // CHECK7-NEXT: store i16 [[TMP31]], i16* [[TMP30]], align 4 5595 // CHECK7-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 1 5596 // CHECK7-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 5597 // CHECK7-NEXT: store i32 [[TMP33]], i32* [[TMP32]], align 4 5598 // CHECK7-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 2 5599 // CHECK7-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 5600 // CHECK7-NEXT: store i32 [[TMP35]], i32* [[TMP34]], align 4 5601 // CHECK7-NEXT: [[TMP36:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 1, i32 72, i32 12, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1) 5602 // CHECK7-NEXT: [[TMP37:%.*]] = bitcast i8* [[TMP36]] to %struct.kmp_task_t_with_privates* 5603 // CHECK7-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP37]], i32 0, i32 0 5604 // CHECK7-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP38]], i32 0, i32 0 5605 // CHECK7-NEXT: [[TMP40:%.*]] = load i8*, i8** [[TMP39]], align 4 5606 // CHECK7-NEXT: [[TMP41:%.*]] = bitcast %struct.anon* [[AGG_CAPTURED]] to i8* 5607 // CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP40]], i8* align 4 [[TMP41]], i32 12, i1 false) 5608 // CHECK7-NEXT: [[TMP42:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP37]], i32 0, i32 1 5609 // CHECK7-NEXT: [[TMP43:%.*]] = bitcast i8* [[TMP40]] to %struct.anon* 5610 // CHECK7-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 0 5611 // CHECK7-NEXT: [[TMP45:%.*]] = bitcast [3 x i64]* [[TMP44]] to i8* 5612 // CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP45]], i8* align 4 bitcast ([3 x i64]* @.offload_sizes to i8*), i32 24, i1 false) 5613 // CHECK7-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 1 5614 // CHECK7-NEXT: [[TMP47:%.*]] = bitcast [3 x i8*]* [[TMP46]] to i8* 5615 // CHECK7-NEXT: [[TMP48:%.*]] = bitcast i8** [[TMP28]] to i8* 5616 // CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP47]], i8* align 4 [[TMP48]], i32 12, i1 false) 5617 // CHECK7-NEXT: [[TMP49:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 2 5618 // CHECK7-NEXT: [[TMP50:%.*]] = bitcast [3 x i8*]* [[TMP49]] to i8* 5619 // CHECK7-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP29]] to i8* 5620 // CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP50]], i8* align 4 [[TMP51]], i32 12, i1 false) 5621 // CHECK7-NEXT: [[TMP52:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 3 5622 // CHECK7-NEXT: [[TMP53:%.*]] = load i16, i16* [[AA]], align 2 5623 // CHECK7-NEXT: store i16 [[TMP53]], i16* [[TMP52]], align 4 5624 // CHECK7-NEXT: [[TMP54:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i8* [[TMP36]]) 5625 // CHECK7-NEXT: [[TMP55:%.*]] = load i32, i32* [[A]], align 4 5626 // CHECK7-NEXT: store i32 [[TMP55]], i32* [[A_CASTED]], align 4 5627 // CHECK7-NEXT: [[TMP56:%.*]] = load i32, i32* [[A_CASTED]], align 4 5628 // CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l102(i32 [[TMP56]]) #[[ATTR4:[0-9]+]] 5629 // CHECK7-NEXT: [[TMP57:%.*]] = load i16, i16* [[AA]], align 2 5630 // CHECK7-NEXT: [[CONV5:%.*]] = bitcast i32* [[AA_CASTED4]] to i16* 5631 // CHECK7-NEXT: store i16 [[TMP57]], i16* [[CONV5]], align 2 5632 // CHECK7-NEXT: [[TMP58:%.*]] = load i32, i32* [[AA_CASTED4]], align 4 5633 // CHECK7-NEXT: [[TMP59:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0 5634 // CHECK7-NEXT: [[TMP60:%.*]] = bitcast i8** [[TMP59]] to i32* 5635 // CHECK7-NEXT: store i32 [[TMP58]], i32* [[TMP60]], align 4 5636 // CHECK7-NEXT: [[TMP61:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0 5637 // CHECK7-NEXT: [[TMP62:%.*]] = bitcast i8** [[TMP61]] to i32* 5638 // CHECK7-NEXT: store i32 [[TMP58]], i32* [[TMP62]], align 4 5639 // CHECK7-NEXT: [[TMP63:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS8]], i32 0, i32 0 5640 // CHECK7-NEXT: store i8* null, i8** [[TMP63]], align 4 5641 // CHECK7-NEXT: [[TMP64:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0 5642 // CHECK7-NEXT: [[TMP65:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0 5643 // CHECK7-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) 5644 // CHECK7-NEXT: [[TMP66:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.region_id, i32 1, i8** [[TMP64]], i8** [[TMP65]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.4, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.5, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1) 5645 // CHECK7-NEXT: [[TMP67:%.*]] = icmp ne i32 [[TMP66]], 0 5646 // CHECK7-NEXT: br i1 [[TMP67]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 5647 // CHECK7: omp_offload.failed: 5648 // CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111(i32 [[TMP58]]) #[[ATTR4]] 5649 // CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT]] 5650 // CHECK7: omp_offload.cont: 5651 // CHECK7-NEXT: [[TMP68:%.*]] = load i32, i32* [[A]], align 4 5652 // CHECK7-NEXT: store i32 [[TMP68]], i32* [[A_CASTED9]], align 4 5653 // CHECK7-NEXT: [[TMP69:%.*]] = load i32, i32* [[A_CASTED9]], align 4 5654 // CHECK7-NEXT: [[TMP70:%.*]] = load i16, i16* [[AA]], align 2 5655 // CHECK7-NEXT: [[CONV11:%.*]] = bitcast i32* [[AA_CASTED10]] to i16* 5656 // CHECK7-NEXT: store i16 [[TMP70]], i16* [[CONV11]], align 2 5657 // CHECK7-NEXT: [[TMP71:%.*]] = load i32, i32* [[AA_CASTED10]], align 4 5658 // CHECK7-NEXT: [[TMP72:%.*]] = load i32, i32* [[N_ADDR]], align 4 5659 // CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP72]], 10 5660 // CHECK7-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 5661 // CHECK7: omp_if.then: 5662 // CHECK7-NEXT: [[TMP73:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS12]], i32 0, i32 0 5663 // CHECK7-NEXT: [[TMP74:%.*]] = bitcast i8** [[TMP73]] to i32* 5664 // CHECK7-NEXT: store i32 [[TMP69]], i32* [[TMP74]], align 4 5665 // CHECK7-NEXT: [[TMP75:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS13]], i32 0, i32 0 5666 // CHECK7-NEXT: [[TMP76:%.*]] = bitcast i8** [[TMP75]] to i32* 5667 // CHECK7-NEXT: store i32 [[TMP69]], i32* [[TMP76]], align 4 5668 // CHECK7-NEXT: [[TMP77:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS14]], i32 0, i32 0 5669 // CHECK7-NEXT: store i8* null, i8** [[TMP77]], align 4 5670 // CHECK7-NEXT: [[TMP78:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS12]], i32 0, i32 1 5671 // CHECK7-NEXT: [[TMP79:%.*]] = bitcast i8** [[TMP78]] to i32* 5672 // CHECK7-NEXT: store i32 [[TMP71]], i32* [[TMP79]], align 4 5673 // CHECK7-NEXT: [[TMP80:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS13]], i32 0, i32 1 5674 // CHECK7-NEXT: [[TMP81:%.*]] = bitcast i8** [[TMP80]] to i32* 5675 // CHECK7-NEXT: store i32 [[TMP71]], i32* [[TMP81]], align 4 5676 // CHECK7-NEXT: [[TMP82:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS14]], i32 0, i32 1 5677 // CHECK7-NEXT: store i8* null, i8** [[TMP82]], align 4 5678 // CHECK7-NEXT: [[TMP83:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS12]], i32 0, i32 0 5679 // CHECK7-NEXT: [[TMP84:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS13]], i32 0, i32 0 5680 // CHECK7-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) 5681 // CHECK7-NEXT: [[TMP85:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.region_id, i32 2, i8** [[TMP83]], i8** [[TMP84]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.7, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.8, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1) 5682 // CHECK7-NEXT: [[TMP86:%.*]] = icmp ne i32 [[TMP85]], 0 5683 // CHECK7-NEXT: br i1 [[TMP86]], label [[OMP_OFFLOAD_FAILED16:%.*]], label [[OMP_OFFLOAD_CONT17:%.*]] 5684 // CHECK7: omp_offload.failed16: 5685 // CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i32 [[TMP69]], i32 [[TMP71]]) #[[ATTR4]] 5686 // CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT17]] 5687 // CHECK7: omp_offload.cont17: 5688 // CHECK7-NEXT: br label [[OMP_IF_END:%.*]] 5689 // CHECK7: omp_if.else: 5690 // CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i32 [[TMP69]], i32 [[TMP71]]) #[[ATTR4]] 5691 // CHECK7-NEXT: br label [[OMP_IF_END]] 5692 // CHECK7: omp_if.end: 5693 // CHECK7-NEXT: [[TMP87:%.*]] = load i32, i32* [[A]], align 4 5694 // CHECK7-NEXT: store i32 [[TMP87]], i32* [[A_CASTED18]], align 4 5695 // CHECK7-NEXT: [[TMP88:%.*]] = load i32, i32* [[A_CASTED18]], align 4 5696 // CHECK7-NEXT: [[TMP89:%.*]] = load i32, i32* [[N_ADDR]], align 4 5697 // CHECK7-NEXT: [[CMP19:%.*]] = icmp sgt i32 [[TMP89]], 20 5698 // CHECK7-NEXT: br i1 [[CMP19]], label [[OMP_IF_THEN20:%.*]], label [[OMP_IF_ELSE27:%.*]] 5699 // CHECK7: omp_if.then20: 5700 // CHECK7-NEXT: [[TMP90:%.*]] = mul nuw i32 [[TMP1]], 4 5701 // CHECK7-NEXT: [[TMP91:%.*]] = sext i32 [[TMP90]] to i64 5702 // CHECK7-NEXT: [[TMP92:%.*]] = mul nuw i32 5, [[TMP3]] 5703 // CHECK7-NEXT: [[TMP93:%.*]] = mul nuw i32 [[TMP92]], 8 5704 // CHECK7-NEXT: [[TMP94:%.*]] = sext i32 [[TMP93]] to i64 5705 // CHECK7-NEXT: [[TMP95:%.*]] = bitcast [9 x i64]* [[DOTOFFLOAD_SIZES]] to i8* 5706 // CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP95]], i8* align 4 bitcast ([9 x i64]* @.offload_sizes.10 to i8*), i32 72, i1 false) 5707 // CHECK7-NEXT: [[TMP96:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 0 5708 // CHECK7-NEXT: [[TMP97:%.*]] = bitcast i8** [[TMP96]] to i32* 5709 // CHECK7-NEXT: store i32 [[TMP88]], i32* [[TMP97]], align 4 5710 // CHECK7-NEXT: [[TMP98:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 0 5711 // CHECK7-NEXT: [[TMP99:%.*]] = bitcast i8** [[TMP98]] to i32* 5712 // CHECK7-NEXT: store i32 [[TMP88]], i32* [[TMP99]], align 4 5713 // CHECK7-NEXT: [[TMP100:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i32 0, i32 0 5714 // CHECK7-NEXT: store i8* null, i8** [[TMP100]], align 4 5715 // CHECK7-NEXT: [[TMP101:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 1 5716 // CHECK7-NEXT: [[TMP102:%.*]] = bitcast i8** [[TMP101]] to [10 x float]** 5717 // CHECK7-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP102]], align 4 5718 // CHECK7-NEXT: [[TMP103:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 1 5719 // CHECK7-NEXT: [[TMP104:%.*]] = bitcast i8** [[TMP103]] to [10 x float]** 5720 // CHECK7-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP104]], align 4 5721 // CHECK7-NEXT: [[TMP105:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i32 0, i32 1 5722 // CHECK7-NEXT: store i8* null, i8** [[TMP105]], align 4 5723 // CHECK7-NEXT: [[TMP106:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 2 5724 // CHECK7-NEXT: [[TMP107:%.*]] = bitcast i8** [[TMP106]] to i32* 5725 // CHECK7-NEXT: store i32 [[TMP1]], i32* [[TMP107]], align 4 5726 // CHECK7-NEXT: [[TMP108:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 2 5727 // CHECK7-NEXT: [[TMP109:%.*]] = bitcast i8** [[TMP108]] to i32* 5728 // CHECK7-NEXT: store i32 [[TMP1]], i32* [[TMP109]], align 4 5729 // CHECK7-NEXT: [[TMP110:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i32 0, i32 2 5730 // CHECK7-NEXT: store i8* null, i8** [[TMP110]], align 4 5731 // CHECK7-NEXT: [[TMP111:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 3 5732 // CHECK7-NEXT: [[TMP112:%.*]] = bitcast i8** [[TMP111]] to float** 5733 // CHECK7-NEXT: store float* [[VLA]], float** [[TMP112]], align 4 5734 // CHECK7-NEXT: [[TMP113:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 3 5735 // CHECK7-NEXT: [[TMP114:%.*]] = bitcast i8** [[TMP113]] to float** 5736 // CHECK7-NEXT: store float* [[VLA]], float** [[TMP114]], align 4 5737 // CHECK7-NEXT: [[TMP115:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 5738 // CHECK7-NEXT: store i64 [[TMP91]], i64* [[TMP115]], align 4 5739 // CHECK7-NEXT: [[TMP116:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i32 0, i32 3 5740 // CHECK7-NEXT: store i8* null, i8** [[TMP116]], align 4 5741 // CHECK7-NEXT: [[TMP117:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 4 5742 // CHECK7-NEXT: [[TMP118:%.*]] = bitcast i8** [[TMP117]] to [5 x [10 x double]]** 5743 // CHECK7-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP118]], align 4 5744 // CHECK7-NEXT: [[TMP119:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 4 5745 // CHECK7-NEXT: [[TMP120:%.*]] = bitcast i8** [[TMP119]] to [5 x [10 x double]]** 5746 // CHECK7-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP120]], align 4 5747 // CHECK7-NEXT: [[TMP121:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i32 0, i32 4 5748 // CHECK7-NEXT: store i8* null, i8** [[TMP121]], align 4 5749 // CHECK7-NEXT: [[TMP122:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 5 5750 // CHECK7-NEXT: [[TMP123:%.*]] = bitcast i8** [[TMP122]] to i32* 5751 // CHECK7-NEXT: store i32 5, i32* [[TMP123]], align 4 5752 // CHECK7-NEXT: [[TMP124:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 5 5753 // CHECK7-NEXT: [[TMP125:%.*]] = bitcast i8** [[TMP124]] to i32* 5754 // CHECK7-NEXT: store i32 5, i32* [[TMP125]], align 4 5755 // CHECK7-NEXT: [[TMP126:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i32 0, i32 5 5756 // CHECK7-NEXT: store i8* null, i8** [[TMP126]], align 4 5757 // CHECK7-NEXT: [[TMP127:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 6 5758 // CHECK7-NEXT: [[TMP128:%.*]] = bitcast i8** [[TMP127]] to i32* 5759 // CHECK7-NEXT: store i32 [[TMP3]], i32* [[TMP128]], align 4 5760 // CHECK7-NEXT: [[TMP129:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 6 5761 // CHECK7-NEXT: [[TMP130:%.*]] = bitcast i8** [[TMP129]] to i32* 5762 // CHECK7-NEXT: store i32 [[TMP3]], i32* [[TMP130]], align 4 5763 // CHECK7-NEXT: [[TMP131:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i32 0, i32 6 5764 // CHECK7-NEXT: store i8* null, i8** [[TMP131]], align 4 5765 // CHECK7-NEXT: [[TMP132:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 7 5766 // CHECK7-NEXT: [[TMP133:%.*]] = bitcast i8** [[TMP132]] to double** 5767 // CHECK7-NEXT: store double* [[VLA1]], double** [[TMP133]], align 4 5768 // CHECK7-NEXT: [[TMP134:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 7 5769 // CHECK7-NEXT: [[TMP135:%.*]] = bitcast i8** [[TMP134]] to double** 5770 // CHECK7-NEXT: store double* [[VLA1]], double** [[TMP135]], align 4 5771 // CHECK7-NEXT: [[TMP136:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 5772 // CHECK7-NEXT: store i64 [[TMP94]], i64* [[TMP136]], align 4 5773 // CHECK7-NEXT: [[TMP137:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i32 0, i32 7 5774 // CHECK7-NEXT: store i8* null, i8** [[TMP137]], align 4 5775 // CHECK7-NEXT: [[TMP138:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 8 5776 // CHECK7-NEXT: [[TMP139:%.*]] = bitcast i8** [[TMP138]] to %struct.TT** 5777 // CHECK7-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP139]], align 4 5778 // CHECK7-NEXT: [[TMP140:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 8 5779 // CHECK7-NEXT: [[TMP141:%.*]] = bitcast i8** [[TMP140]] to %struct.TT** 5780 // CHECK7-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP141]], align 4 5781 // CHECK7-NEXT: [[TMP142:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i32 0, i32 8 5782 // CHECK7-NEXT: store i8* null, i8** [[TMP142]], align 4 5783 // CHECK7-NEXT: [[TMP143:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 0 5784 // CHECK7-NEXT: [[TMP144:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 0 5785 // CHECK7-NEXT: [[TMP145:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 5786 // CHECK7-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) 5787 // CHECK7-NEXT: [[TMP146:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142.region_id, i32 9, i8** [[TMP143]], i8** [[TMP144]], i64* [[TMP145]], i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_maptypes.11, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1) 5788 // CHECK7-NEXT: [[TMP147:%.*]] = icmp ne i32 [[TMP146]], 0 5789 // CHECK7-NEXT: br i1 [[TMP147]], label [[OMP_OFFLOAD_FAILED25:%.*]], label [[OMP_OFFLOAD_CONT26:%.*]] 5790 // CHECK7: omp_offload.failed25: 5791 // CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i32 [[TMP88]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR4]] 5792 // CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT26]] 5793 // CHECK7: omp_offload.cont26: 5794 // CHECK7-NEXT: br label [[OMP_IF_END28:%.*]] 5795 // CHECK7: omp_if.else27: 5796 // CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i32 [[TMP88]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR4]] 5797 // CHECK7-NEXT: br label [[OMP_IF_END28]] 5798 // CHECK7: omp_if.end28: 5799 // CHECK7-NEXT: [[TMP148:%.*]] = load i32, i32* [[A]], align 4 5800 // CHECK7-NEXT: [[TMP149:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 5801 // CHECK7-NEXT: call void @llvm.stackrestore(i8* [[TMP149]]) 5802 // CHECK7-NEXT: ret i32 [[TMP148]] 5803 // 5804 // 5805 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97 5806 // CHECK7-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]], i32 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] { 5807 // CHECK7-NEXT: entry: 5808 // CHECK7-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 5809 // CHECK7-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 5810 // CHECK7-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4 5811 // CHECK7-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 5812 // CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]]) 5813 // CHECK7-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 5814 // CHECK7-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 5815 // CHECK7-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 5816 // CHECK7-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 5817 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 5818 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 5819 // CHECK7-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) 5820 // CHECK7-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 5821 // CHECK7-NEXT: [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 5822 // CHECK7-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 5823 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 5824 // CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]]) 5825 // CHECK7-NEXT: ret void 5826 // 5827 // 5828 // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined. 5829 // CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR3:[0-9]+]] { 5830 // CHECK7-NEXT: entry: 5831 // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 5832 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 5833 // CHECK7-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 5834 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 5835 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 5836 // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 5837 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 5838 // CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 5839 // CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 5840 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 5841 // CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 5842 // CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 5843 // CHECK7-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 5844 // CHECK7-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 5845 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 5846 // CHECK7-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 5847 // CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 5848 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 5849 // CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 5850 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 5851 // CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 5852 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 5853 // CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 5854 // CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 5855 // CHECK7: cond.true: 5856 // CHECK7-NEXT: br label [[COND_END:%.*]] 5857 // CHECK7: cond.false: 5858 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 5859 // CHECK7-NEXT: br label [[COND_END]] 5860 // CHECK7: cond.end: 5861 // CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 5862 // CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 5863 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 5864 // CHECK7-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 5865 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 5866 // CHECK7: omp.inner.for.cond: 5867 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 5868 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !11 5869 // CHECK7-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 5870 // CHECK7-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 5871 // CHECK7: omp.inner.for.body: 5872 // CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 5873 // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 5874 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 5875 // CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11 5876 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 5877 // CHECK7: omp.body.continue: 5878 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 5879 // CHECK7: omp.inner.for.inc: 5880 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 5881 // CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 5882 // CHECK7-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 5883 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] 5884 // CHECK7: omp.inner.for.end: 5885 // CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 5886 // CHECK7: omp.loop.exit: 5887 // CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 5888 // CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 5889 // CHECK7-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 5890 // CHECK7-NEXT: br i1 [[TMP10]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 5891 // CHECK7: .omp.final.then: 5892 // CHECK7-NEXT: store i32 10, i32* [[I]], align 4 5893 // CHECK7-NEXT: br label [[DOTOMP_FINAL_DONE]] 5894 // CHECK7: .omp.final.done: 5895 // CHECK7-NEXT: ret void 5896 // 5897 // 5898 // CHECK7-LABEL: define {{[^@]+}}@.omp_task_privates_map. 5899 // CHECK7-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], i16** noalias noundef [[TMP1:%.*]], [3 x i8*]** noalias noundef [[TMP2:%.*]], [3 x i8*]** noalias noundef [[TMP3:%.*]], [3 x i64]** noalias noundef [[TMP4:%.*]]) #[[ATTR5:[0-9]+]] { 5900 // CHECK7-NEXT: entry: 5901 // CHECK7-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 4 5902 // CHECK7-NEXT: [[DOTADDR1:%.*]] = alloca i16**, align 4 5903 // CHECK7-NEXT: [[DOTADDR2:%.*]] = alloca [3 x i8*]**, align 4 5904 // CHECK7-NEXT: [[DOTADDR3:%.*]] = alloca [3 x i8*]**, align 4 5905 // CHECK7-NEXT: [[DOTADDR4:%.*]] = alloca [3 x i64]**, align 4 5906 // CHECK7-NEXT: store %struct..kmp_privates.t* [[TMP0]], %struct..kmp_privates.t** [[DOTADDR]], align 4 5907 // CHECK7-NEXT: store i16** [[TMP1]], i16*** [[DOTADDR1]], align 4 5908 // CHECK7-NEXT: store [3 x i8*]** [[TMP2]], [3 x i8*]*** [[DOTADDR2]], align 4 5909 // CHECK7-NEXT: store [3 x i8*]** [[TMP3]], [3 x i8*]*** [[DOTADDR3]], align 4 5910 // CHECK7-NEXT: store [3 x i64]** [[TMP4]], [3 x i64]*** [[DOTADDR4]], align 4 5911 // CHECK7-NEXT: [[TMP5:%.*]] = load %struct..kmp_privates.t*, %struct..kmp_privates.t** [[DOTADDR]], align 4 5912 // CHECK7-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 0 5913 // CHECK7-NEXT: [[TMP7:%.*]] = load [3 x i64]**, [3 x i64]*** [[DOTADDR4]], align 4 5914 // CHECK7-NEXT: store [3 x i64]* [[TMP6]], [3 x i64]** [[TMP7]], align 4 5915 // CHECK7-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 1 5916 // CHECK7-NEXT: [[TMP9:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR2]], align 4 5917 // CHECK7-NEXT: store [3 x i8*]* [[TMP8]], [3 x i8*]** [[TMP9]], align 4 5918 // CHECK7-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 2 5919 // CHECK7-NEXT: [[TMP11:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR3]], align 4 5920 // CHECK7-NEXT: store [3 x i8*]* [[TMP10]], [3 x i8*]** [[TMP11]], align 4 5921 // CHECK7-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 3 5922 // CHECK7-NEXT: [[TMP13:%.*]] = load i16**, i16*** [[DOTADDR1]], align 4 5923 // CHECK7-NEXT: store i16* [[TMP12]], i16** [[TMP13]], align 4 5924 // CHECK7-NEXT: ret void 5925 // 5926 // 5927 // CHECK7-LABEL: define {{[^@]+}}@.omp_task_entry. 5928 // CHECK7-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] { 5929 // CHECK7-NEXT: entry: 5930 // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 5931 // CHECK7-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 4 5932 // CHECK7-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 4 5933 // CHECK7-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 4 5934 // CHECK7-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 4 5935 // CHECK7-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 4 5936 // CHECK7-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca i16*, align 4 5937 // CHECK7-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca [3 x i8*]*, align 4 5938 // CHECK7-NEXT: [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca [3 x i8*]*, align 4 5939 // CHECK7-NEXT: [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca [3 x i64]*, align 4 5940 // CHECK7-NEXT: [[AA_CASTED_I:%.*]] = alloca i32, align 4 5941 // CHECK7-NEXT: [[DOTCAPTURE_EXPR__CASTED_I:%.*]] = alloca i32, align 4 5942 // CHECK7-NEXT: [[DOTCAPTURE_EXPR__CASTED4_I:%.*]] = alloca i32, align 4 5943 // CHECK7-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 5944 // CHECK7-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 4 5945 // CHECK7-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 5946 // CHECK7-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4 5947 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 5948 // CHECK7-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4 5949 // CHECK7-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0 5950 // CHECK7-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 5951 // CHECK7-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 5952 // CHECK7-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 4 5953 // CHECK7-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon* 5954 // CHECK7-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1 5955 // CHECK7-NEXT: [[TMP10:%.*]] = bitcast %struct..kmp_privates.t* [[TMP9]] to i8* 5956 // CHECK7-NEXT: [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8* 5957 // CHECK7-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]]) 5958 // CHECK7-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META21:![0-9]+]]) 5959 // CHECK7-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META23:![0-9]+]]) 5960 // CHECK7-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META25:![0-9]+]]) 5961 // CHECK7-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !27 5962 // CHECK7-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 4, !noalias !27 5963 // CHECK7-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !27 5964 // CHECK7-NEXT: store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* @.omp_task_privates_map. to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !27 5965 // CHECK7-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 4, !noalias !27 5966 // CHECK7-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !27 5967 // CHECK7-NEXT: [[TMP12:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !27 5968 // CHECK7-NEXT: [[TMP13:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !27 5969 // CHECK7-NEXT: [[TMP14:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !27 5970 // CHECK7-NEXT: [[TMP15:%.*]] = bitcast void (i8*, ...)* [[TMP13]] to void (i8*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* 5971 // CHECK7-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR4]] 5972 // CHECK7-NEXT: [[TMP16:%.*]] = load i16*, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 4, !noalias !27 5973 // CHECK7-NEXT: [[TMP17:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 4, !noalias !27 5974 // CHECK7-NEXT: [[TMP18:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 4, !noalias !27 5975 // CHECK7-NEXT: [[TMP19:%.*]] = load [3 x i64]*, [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 4, !noalias !27 5976 // CHECK7-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP17]], i32 0, i32 0 5977 // CHECK7-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP18]], i32 0, i32 0 5978 // CHECK7-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[TMP19]], i32 0, i32 0 5979 // CHECK7-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP12]], i32 0, i32 1 5980 // CHECK7-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[TMP12]], i32 0, i32 2 5981 // CHECK7-NEXT: [[TMP25:%.*]] = load i32, i32* [[TMP23]], align 4 5982 // CHECK7-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) #[[ATTR4]] 5983 // CHECK7-NEXT: [[TMP26:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 [[TMP25]], i32 1, i32 0, i8* null, i32 0, i8* null) #[[ATTR4]] 5984 // CHECK7-NEXT: [[TMP27:%.*]] = icmp ne i32 [[TMP26]], 0 5985 // CHECK7-NEXT: br i1 [[TMP27]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]] 5986 // CHECK7: omp_offload.failed.i: 5987 // CHECK7-NEXT: [[TMP28:%.*]] = load i16, i16* [[TMP16]], align 2 5988 // CHECK7-NEXT: [[CONV_I:%.*]] = bitcast i32* [[AA_CASTED_I]] to i16* 5989 // CHECK7-NEXT: store i16 [[TMP28]], i16* [[CONV_I]], align 2, !noalias !27 5990 // CHECK7-NEXT: [[TMP29:%.*]] = load i32, i32* [[AA_CASTED_I]], align 4, !noalias !27 5991 // CHECK7-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP23]], align 4 5992 // CHECK7-NEXT: store i32 [[TMP30]], i32* [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias !27 5993 // CHECK7-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias !27 5994 // CHECK7-NEXT: [[TMP32:%.*]] = load i32, i32* [[TMP24]], align 4 5995 // CHECK7-NEXT: store i32 [[TMP32]], i32* [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias !27 5996 // CHECK7-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias !27 5997 // CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97(i32 [[TMP29]], i32 [[TMP31]], i32 [[TMP33]]) #[[ATTR4]] 5998 // CHECK7-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]] 5999 // CHECK7: .omp_outlined..1.exit: 6000 // CHECK7-NEXT: ret i32 0 6001 // 6002 // 6003 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l102 6004 // CHECK7-SAME: (i32 noundef [[A:%.*]]) #[[ATTR3]] { 6005 // CHECK7-NEXT: entry: 6006 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 6007 // CHECK7-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 6008 // CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 6009 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 6010 // CHECK7-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 6011 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 6012 // CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]]) 6013 // CHECK7-NEXT: ret void 6014 // 6015 // 6016 // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..2 6017 // CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]]) #[[ATTR3]] { 6018 // CHECK7-NEXT: entry: 6019 // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 6020 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 6021 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 6022 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 6023 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 6024 // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 6025 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 6026 // CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 6027 // CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 6028 // CHECK7-NEXT: [[A1:%.*]] = alloca i32, align 4 6029 // CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 6030 // CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 6031 // CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 6032 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 6033 // CHECK7-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 6034 // CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 6035 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 6036 // CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 6037 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 6038 // CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 6039 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 6040 // CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 6041 // CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 6042 // CHECK7: cond.true: 6043 // CHECK7-NEXT: br label [[COND_END:%.*]] 6044 // CHECK7: cond.false: 6045 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 6046 // CHECK7-NEXT: br label [[COND_END]] 6047 // CHECK7: cond.end: 6048 // CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 6049 // CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 6050 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 6051 // CHECK7-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 6052 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 6053 // CHECK7: omp.inner.for.cond: 6054 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 6055 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 6056 // CHECK7-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 6057 // CHECK7-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 6058 // CHECK7: omp.inner.for.body: 6059 // CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 6060 // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 6061 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 6062 // CHECK7-NEXT: store i32 [[ADD]], i32* [[A1]], align 4, !nontemporal !28 6063 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[A1]], align 4, !nontemporal !28 6064 // CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1 6065 // CHECK7-NEXT: store i32 [[ADD3]], i32* [[A1]], align 4, !nontemporal !28 6066 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 6067 // CHECK7: omp.body.continue: 6068 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 6069 // CHECK7: omp.inner.for.inc: 6070 // CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 6071 // CHECK7-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP9]], 1 6072 // CHECK7-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 6073 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP29:![0-9]+]] 6074 // CHECK7: omp.inner.for.end: 6075 // CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 6076 // CHECK7: omp.loop.exit: 6077 // CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 6078 // CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 6079 // CHECK7-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0 6080 // CHECK7-NEXT: br i1 [[TMP11]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 6081 // CHECK7: .omp.final.then: 6082 // CHECK7-NEXT: store i32 10, i32* [[A_ADDR]], align 4 6083 // CHECK7-NEXT: br label [[DOTOMP_FINAL_DONE]] 6084 // CHECK7: .omp.final.done: 6085 // CHECK7-NEXT: ret void 6086 // 6087 // 6088 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 6089 // CHECK7-SAME: (i32 noundef [[AA:%.*]]) #[[ATTR2]] { 6090 // CHECK7-NEXT: entry: 6091 // CHECK7-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 6092 // CHECK7-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 6093 // CHECK7-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 6094 // CHECK7-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 6095 // CHECK7-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 6096 // CHECK7-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 6097 // CHECK7-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 6098 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 6099 // CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP1]]) 6100 // CHECK7-NEXT: ret void 6101 // 6102 // 6103 // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..3 6104 // CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR3]] { 6105 // CHECK7-NEXT: entry: 6106 // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 6107 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 6108 // CHECK7-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 6109 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 6110 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 6111 // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 6112 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 6113 // CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 6114 // CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 6115 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 6116 // CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 6117 // CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 6118 // CHECK7-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 6119 // CHECK7-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 6120 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 6121 // CHECK7-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 6122 // CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 6123 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 6124 // CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 6125 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 6126 // CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 6127 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 6128 // CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 6129 // CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 6130 // CHECK7: cond.true: 6131 // CHECK7-NEXT: br label [[COND_END:%.*]] 6132 // CHECK7: cond.false: 6133 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 6134 // CHECK7-NEXT: br label [[COND_END]] 6135 // CHECK7: cond.end: 6136 // CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 6137 // CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 6138 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 6139 // CHECK7-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 6140 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 6141 // CHECK7: omp.inner.for.cond: 6142 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !31 6143 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !31 6144 // CHECK7-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 6145 // CHECK7-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 6146 // CHECK7: omp.inner.for.body: 6147 // CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !31 6148 // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 6149 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 6150 // CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !31 6151 // CHECK7-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !31 6152 // CHECK7-NEXT: [[CONV2:%.*]] = sext i16 [[TMP8]] to i32 6153 // CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 6154 // CHECK7-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 6155 // CHECK7-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2, !llvm.access.group !31 6156 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 6157 // CHECK7: omp.body.continue: 6158 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 6159 // CHECK7: omp.inner.for.inc: 6160 // CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !31 6161 // CHECK7-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP9]], 1 6162 // CHECK7-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !31 6163 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP32:![0-9]+]] 6164 // CHECK7: omp.inner.for.end: 6165 // CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 6166 // CHECK7: omp.loop.exit: 6167 // CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 6168 // CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 6169 // CHECK7-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0 6170 // CHECK7-NEXT: br i1 [[TMP11]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 6171 // CHECK7: .omp.final.then: 6172 // CHECK7-NEXT: store i32 10, i32* [[I]], align 4 6173 // CHECK7-NEXT: br label [[DOTOMP_FINAL_DONE]] 6174 // CHECK7: .omp.final.done: 6175 // CHECK7-NEXT: ret void 6176 // 6177 // 6178 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118 6179 // CHECK7-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { 6180 // CHECK7-NEXT: entry: 6181 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 6182 // CHECK7-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 6183 // CHECK7-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 6184 // CHECK7-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 6185 // CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 6186 // CHECK7-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 6187 // CHECK7-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 6188 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 6189 // CHECK7-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 6190 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 6191 // CHECK7-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 6192 // CHECK7-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 6193 // CHECK7-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 6194 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 6195 // CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) 6196 // CHECK7-NEXT: ret void 6197 // 6198 // 6199 // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..6 6200 // CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR3]] { 6201 // CHECK7-NEXT: entry: 6202 // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 6203 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 6204 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 6205 // CHECK7-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 6206 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 6207 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 6208 // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 6209 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 6210 // CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 6211 // CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 6212 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 6213 // CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 6214 // CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 6215 // CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 6216 // CHECK7-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 6217 // CHECK7-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 6218 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 6219 // CHECK7-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 6220 // CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 6221 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 6222 // CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 6223 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 6224 // CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 6225 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 6226 // CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 6227 // CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 6228 // CHECK7: cond.true: 6229 // CHECK7-NEXT: br label [[COND_END:%.*]] 6230 // CHECK7: cond.false: 6231 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 6232 // CHECK7-NEXT: br label [[COND_END]] 6233 // CHECK7: cond.end: 6234 // CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 6235 // CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 6236 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 6237 // CHECK7-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 6238 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 6239 // CHECK7: omp.inner.for.cond: 6240 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !34 6241 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !34 6242 // CHECK7-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 6243 // CHECK7-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 6244 // CHECK7: omp.inner.for.body: 6245 // CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !34 6246 // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 6247 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 6248 // CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !34 6249 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !34 6250 // CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 6251 // CHECK7-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4, !llvm.access.group !34 6252 // CHECK7-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !34 6253 // CHECK7-NEXT: [[CONV3:%.*]] = sext i16 [[TMP9]] to i32 6254 // CHECK7-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 6255 // CHECK7-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 6256 // CHECK7-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2, !llvm.access.group !34 6257 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 6258 // CHECK7: omp.body.continue: 6259 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 6260 // CHECK7: omp.inner.for.inc: 6261 // CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !34 6262 // CHECK7-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP10]], 1 6263 // CHECK7-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !34 6264 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP35:![0-9]+]] 6265 // CHECK7: omp.inner.for.end: 6266 // CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 6267 // CHECK7: omp.loop.exit: 6268 // CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 6269 // CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 6270 // CHECK7-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 6271 // CHECK7-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 6272 // CHECK7: .omp.final.then: 6273 // CHECK7-NEXT: store i32 10, i32* [[I]], align 4 6274 // CHECK7-NEXT: br label [[DOTOMP_FINAL_DONE]] 6275 // CHECK7: .omp.final.done: 6276 // CHECK7-NEXT: ret void 6277 // 6278 // 6279 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142 6280 // CHECK7-SAME: (i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] { 6281 // CHECK7-NEXT: entry: 6282 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 6283 // CHECK7-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 6284 // CHECK7-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 6285 // CHECK7-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 6286 // CHECK7-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 6287 // CHECK7-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 6288 // CHECK7-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 6289 // CHECK7-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 6290 // CHECK7-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 6291 // CHECK7-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 6292 // CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 6293 // CHECK7-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 6294 // CHECK7-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 6295 // CHECK7-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 6296 // CHECK7-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 6297 // CHECK7-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 6298 // CHECK7-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 6299 // CHECK7-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 6300 // CHECK7-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 6301 // CHECK7-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 6302 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 6303 // CHECK7-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 6304 // CHECK7-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 6305 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 6306 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 6307 // CHECK7-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 6308 // CHECK7-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 6309 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 6310 // CHECK7-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4 6311 // CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4 6312 // CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) 6313 // CHECK7-NEXT: ret void 6314 // 6315 // 6316 // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..9 6317 // CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR3]] { 6318 // CHECK7-NEXT: entry: 6319 // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 6320 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 6321 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 6322 // CHECK7-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 6323 // CHECK7-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 6324 // CHECK7-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 6325 // CHECK7-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 6326 // CHECK7-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 6327 // CHECK7-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 6328 // CHECK7-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 6329 // CHECK7-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 6330 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 6331 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 6332 // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 6333 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 6334 // CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 6335 // CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 6336 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 6337 // CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 6338 // CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 6339 // CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 6340 // CHECK7-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 6341 // CHECK7-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 6342 // CHECK7-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 6343 // CHECK7-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 6344 // CHECK7-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 6345 // CHECK7-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 6346 // CHECK7-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 6347 // CHECK7-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 6348 // CHECK7-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 6349 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 6350 // CHECK7-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 6351 // CHECK7-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 6352 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 6353 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 6354 // CHECK7-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 6355 // CHECK7-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 6356 // CHECK7-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 0 6357 // CHECK7-NEXT: call void @llvm.assume(i1 true) [ "align"(float* [[ARRAYDECAY]], i32 16) ] 6358 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 6359 // CHECK7-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 6360 // CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 6361 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 6362 // CHECK7-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 6363 // CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 6364 // CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 6365 // CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 6366 // CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP10]], 9 6367 // CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 6368 // CHECK7: cond.true: 6369 // CHECK7-NEXT: br label [[COND_END:%.*]] 6370 // CHECK7: cond.false: 6371 // CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 6372 // CHECK7-NEXT: br label [[COND_END]] 6373 // CHECK7: cond.end: 6374 // CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] 6375 // CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 6376 // CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 6377 // CHECK7-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 6378 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 6379 // CHECK7: omp.inner.for.cond: 6380 // CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !37 6381 // CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !37 6382 // CHECK7-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] 6383 // CHECK7-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 6384 // CHECK7: omp.inner.for.body: 6385 // CHECK7-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !37 6386 // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 6387 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 6388 // CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !37 6389 // CHECK7-NEXT: [[TMP16:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !37 6390 // CHECK7-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP16]], 1 6391 // CHECK7-NEXT: store i32 [[ADD6]], i32* [[A_ADDR]], align 4, !llvm.access.group !37 6392 // CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2 6393 // CHECK7-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !37 6394 // CHECK7-NEXT: [[CONV:%.*]] = fpext float [[TMP17]] to double 6395 // CHECK7-NEXT: [[ADD7:%.*]] = fadd double [[CONV]], 1.000000e+00 6396 // CHECK7-NEXT: [[CONV8:%.*]] = fptrunc double [[ADD7]] to float 6397 // CHECK7-NEXT: store float [[CONV8]], float* [[ARRAYIDX]], align 4, !llvm.access.group !37 6398 // CHECK7-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3 6399 // CHECK7-NEXT: [[TMP18:%.*]] = load float, float* [[ARRAYIDX9]], align 4, !llvm.access.group !37 6400 // CHECK7-NEXT: [[CONV10:%.*]] = fpext float [[TMP18]] to double 6401 // CHECK7-NEXT: [[ADD11:%.*]] = fadd double [[CONV10]], 1.000000e+00 6402 // CHECK7-NEXT: [[CONV12:%.*]] = fptrunc double [[ADD11]] to float 6403 // CHECK7-NEXT: store float [[CONV12]], float* [[ARRAYIDX9]], align 4, !llvm.access.group !37 6404 // CHECK7-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1 6405 // CHECK7-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX13]], i32 0, i32 2 6406 // CHECK7-NEXT: [[TMP19:%.*]] = load double, double* [[ARRAYIDX14]], align 8, !llvm.access.group !37 6407 // CHECK7-NEXT: [[ADD15:%.*]] = fadd double [[TMP19]], 1.000000e+00 6408 // CHECK7-NEXT: store double [[ADD15]], double* [[ARRAYIDX14]], align 8, !llvm.access.group !37 6409 // CHECK7-NEXT: [[TMP20:%.*]] = mul nsw i32 1, [[TMP5]] 6410 // CHECK7-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP20]] 6411 // CHECK7-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX16]], i32 3 6412 // CHECK7-NEXT: [[TMP21:%.*]] = load double, double* [[ARRAYIDX17]], align 8, !llvm.access.group !37 6413 // CHECK7-NEXT: [[ADD18:%.*]] = fadd double [[TMP21]], 1.000000e+00 6414 // CHECK7-NEXT: store double [[ADD18]], double* [[ARRAYIDX17]], align 8, !llvm.access.group !37 6415 // CHECK7-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 6416 // CHECK7-NEXT: [[TMP22:%.*]] = load i64, i64* [[X]], align 4, !llvm.access.group !37 6417 // CHECK7-NEXT: [[ADD19:%.*]] = add nsw i64 [[TMP22]], 1 6418 // CHECK7-NEXT: store i64 [[ADD19]], i64* [[X]], align 4, !llvm.access.group !37 6419 // CHECK7-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 6420 // CHECK7-NEXT: [[TMP23:%.*]] = load i8, i8* [[Y]], align 4, !llvm.access.group !37 6421 // CHECK7-NEXT: [[CONV20:%.*]] = sext i8 [[TMP23]] to i32 6422 // CHECK7-NEXT: [[ADD21:%.*]] = add nsw i32 [[CONV20]], 1 6423 // CHECK7-NEXT: [[CONV22:%.*]] = trunc i32 [[ADD21]] to i8 6424 // CHECK7-NEXT: store i8 [[CONV22]], i8* [[Y]], align 4, !llvm.access.group !37 6425 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 6426 // CHECK7: omp.body.continue: 6427 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 6428 // CHECK7: omp.inner.for.inc: 6429 // CHECK7-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !37 6430 // CHECK7-NEXT: [[ADD23:%.*]] = add nsw i32 [[TMP24]], 1 6431 // CHECK7-NEXT: store i32 [[ADD23]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !37 6432 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP38:![0-9]+]] 6433 // CHECK7: omp.inner.for.end: 6434 // CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 6435 // CHECK7: omp.loop.exit: 6436 // CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]]) 6437 // CHECK7-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 6438 // CHECK7-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0 6439 // CHECK7-NEXT: br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 6440 // CHECK7: .omp.final.then: 6441 // CHECK7-NEXT: store i32 10, i32* [[I]], align 4 6442 // CHECK7-NEXT: br label [[DOTOMP_FINAL_DONE]] 6443 // CHECK7: .omp.final.done: 6444 // CHECK7-NEXT: ret void 6445 // 6446 // 6447 // CHECK7-LABEL: define {{[^@]+}}@_Z3bari 6448 // CHECK7-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { 6449 // CHECK7-NEXT: entry: 6450 // CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 6451 // CHECK7-NEXT: [[A:%.*]] = alloca i32, align 4 6452 // CHECK7-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 6453 // CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 6454 // CHECK7-NEXT: store i32 0, i32* [[A]], align 4 6455 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 6456 // CHECK7-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]]) 6457 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 6458 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 6459 // CHECK7-NEXT: store i32 [[ADD]], i32* [[A]], align 4 6460 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 6461 // CHECK7-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP2]]) 6462 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 6463 // CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 6464 // CHECK7-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 6465 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 6466 // CHECK7-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]]) 6467 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 6468 // CHECK7-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 6469 // CHECK7-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 6470 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 6471 // CHECK7-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]]) 6472 // CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 6473 // CHECK7-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] 6474 // CHECK7-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 6475 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 6476 // CHECK7-NEXT: ret i32 [[TMP8]] 6477 // 6478 // 6479 // CHECK7-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 6480 // CHECK7-SAME: (%struct.S1* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 { 6481 // CHECK7-NEXT: entry: 6482 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 6483 // CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 6484 // CHECK7-NEXT: [[B:%.*]] = alloca i32, align 4 6485 // CHECK7-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 6486 // CHECK7-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 6487 // CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 6488 // CHECK7-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 6489 // CHECK7-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 6490 // CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [6 x i8*], align 4 6491 // CHECK7-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [6 x i8*], align 4 6492 // CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [6 x i8*], align 4 6493 // CHECK7-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [6 x i64], align 4 6494 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 6495 // CHECK7-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 6496 // CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 6497 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 6498 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 6499 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 6500 // CHECK7-NEXT: store i32 [[ADD]], i32* [[B]], align 4 6501 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 6502 // CHECK7-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() 6503 // CHECK7-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 6504 // CHECK7-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] 6505 // CHECK7-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 6506 // CHECK7-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 6507 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 6508 // CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 60 6509 // CHECK7-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8 6510 // CHECK7-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 6511 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 6512 // CHECK7-NEXT: store i32 [[TMP5]], i32* [[B_CASTED]], align 4 6513 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4 6514 // CHECK7-NEXT: [[TMP7:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 6515 // CHECK7-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP7]] to i1 6516 // CHECK7-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__CASTED]] to i8* 6517 // CHECK7-NEXT: [[FROMBOOL2:%.*]] = zext i1 [[TOBOOL]] to i8 6518 // CHECK7-NEXT: store i8 [[FROMBOOL2]], i8* [[CONV]], align 1 6519 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 6520 // CHECK7-NEXT: [[TMP9:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 6521 // CHECK7-NEXT: [[TOBOOL3:%.*]] = trunc i8 [[TMP9]] to i1 6522 // CHECK7-NEXT: br i1 [[TOBOOL3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 6523 // CHECK7: omp_if.then: 6524 // CHECK7-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 6525 // CHECK7-NEXT: [[TMP10:%.*]] = mul nuw i32 2, [[TMP1]] 6526 // CHECK7-NEXT: [[TMP11:%.*]] = mul nuw i32 [[TMP10]], 2 6527 // CHECK7-NEXT: [[TMP12:%.*]] = sext i32 [[TMP11]] to i64 6528 // CHECK7-NEXT: [[TMP13:%.*]] = bitcast [6 x i64]* [[DOTOFFLOAD_SIZES]] to i8* 6529 // CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP13]], i8* align 4 bitcast ([6 x i64]* @.offload_sizes.13 to i8*), i32 48, i1 false) 6530 // CHECK7-NEXT: [[TMP14:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 6531 // CHECK7-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to %struct.S1** 6532 // CHECK7-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP15]], align 4 6533 // CHECK7-NEXT: [[TMP16:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 6534 // CHECK7-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to double** 6535 // CHECK7-NEXT: store double* [[A]], double** [[TMP17]], align 4 6536 // CHECK7-NEXT: [[TMP18:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 6537 // CHECK7-NEXT: store i8* null, i8** [[TMP18]], align 4 6538 // CHECK7-NEXT: [[TMP19:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 6539 // CHECK7-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32* 6540 // CHECK7-NEXT: store i32 [[TMP6]], i32* [[TMP20]], align 4 6541 // CHECK7-NEXT: [[TMP21:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 6542 // CHECK7-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i32* 6543 // CHECK7-NEXT: store i32 [[TMP6]], i32* [[TMP22]], align 4 6544 // CHECK7-NEXT: [[TMP23:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 6545 // CHECK7-NEXT: store i8* null, i8** [[TMP23]], align 4 6546 // CHECK7-NEXT: [[TMP24:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 6547 // CHECK7-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i32* 6548 // CHECK7-NEXT: store i32 2, i32* [[TMP25]], align 4 6549 // CHECK7-NEXT: [[TMP26:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 6550 // CHECK7-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i32* 6551 // CHECK7-NEXT: store i32 2, i32* [[TMP27]], align 4 6552 // CHECK7-NEXT: [[TMP28:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 6553 // CHECK7-NEXT: store i8* null, i8** [[TMP28]], align 4 6554 // CHECK7-NEXT: [[TMP29:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 6555 // CHECK7-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i32* 6556 // CHECK7-NEXT: store i32 [[TMP1]], i32* [[TMP30]], align 4 6557 // CHECK7-NEXT: [[TMP31:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 6558 // CHECK7-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i32* 6559 // CHECK7-NEXT: store i32 [[TMP1]], i32* [[TMP32]], align 4 6560 // CHECK7-NEXT: [[TMP33:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 6561 // CHECK7-NEXT: store i8* null, i8** [[TMP33]], align 4 6562 // CHECK7-NEXT: [[TMP34:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 6563 // CHECK7-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i16** 6564 // CHECK7-NEXT: store i16* [[VLA]], i16** [[TMP35]], align 4 6565 // CHECK7-NEXT: [[TMP36:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 6566 // CHECK7-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i16** 6567 // CHECK7-NEXT: store i16* [[VLA]], i16** [[TMP37]], align 4 6568 // CHECK7-NEXT: [[TMP38:%.*]] = getelementptr inbounds [6 x i64], [6 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 6569 // CHECK7-NEXT: store i64 [[TMP12]], i64* [[TMP38]], align 4 6570 // CHECK7-NEXT: [[TMP39:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 6571 // CHECK7-NEXT: store i8* null, i8** [[TMP39]], align 4 6572 // CHECK7-NEXT: [[TMP40:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 5 6573 // CHECK7-NEXT: [[TMP41:%.*]] = bitcast i8** [[TMP40]] to i32* 6574 // CHECK7-NEXT: store i32 [[TMP8]], i32* [[TMP41]], align 4 6575 // CHECK7-NEXT: [[TMP42:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 5 6576 // CHECK7-NEXT: [[TMP43:%.*]] = bitcast i8** [[TMP42]] to i32* 6577 // CHECK7-NEXT: store i32 [[TMP8]], i32* [[TMP43]], align 4 6578 // CHECK7-NEXT: [[TMP44:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 5 6579 // CHECK7-NEXT: store i8* null, i8** [[TMP44]], align 4 6580 // CHECK7-NEXT: [[TMP45:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 6581 // CHECK7-NEXT: [[TMP46:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 6582 // CHECK7-NEXT: [[TMP47:%.*]] = getelementptr inbounds [6 x i64], [6 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 6583 // CHECK7-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) 6584 // CHECK7-NEXT: [[TMP48:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215.region_id, i32 6, i8** [[TMP45]], i8** [[TMP46]], i64* [[TMP47]], i64* getelementptr inbounds ([6 x i64], [6 x i64]* @.offload_maptypes.14, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1) 6585 // CHECK7-NEXT: [[TMP49:%.*]] = icmp ne i32 [[TMP48]], 0 6586 // CHECK7-NEXT: br i1 [[TMP49]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 6587 // CHECK7: omp_offload.failed: 6588 // CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215(%struct.S1* [[THIS1]], i32 [[TMP6]], i32 2, i32 [[TMP1]], i16* [[VLA]], i32 [[TMP8]]) #[[ATTR4]] 6589 // CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT]] 6590 // CHECK7: omp_offload.cont: 6591 // CHECK7-NEXT: br label [[OMP_IF_END:%.*]] 6592 // CHECK7: omp_if.else: 6593 // CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215(%struct.S1* [[THIS1]], i32 [[TMP6]], i32 2, i32 [[TMP1]], i16* [[VLA]], i32 [[TMP8]]) #[[ATTR4]] 6594 // CHECK7-NEXT: br label [[OMP_IF_END]] 6595 // CHECK7: omp_if.end: 6596 // CHECK7-NEXT: [[TMP50:%.*]] = mul nsw i32 1, [[TMP1]] 6597 // CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP50]] 6598 // CHECK7-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 6599 // CHECK7-NEXT: [[TMP51:%.*]] = load i16, i16* [[ARRAYIDX4]], align 2 6600 // CHECK7-NEXT: [[CONV5:%.*]] = sext i16 [[TMP51]] to i32 6601 // CHECK7-NEXT: [[TMP52:%.*]] = load i32, i32* [[B]], align 4 6602 // CHECK7-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], [[TMP52]] 6603 // CHECK7-NEXT: [[TMP53:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 6604 // CHECK7-NEXT: call void @llvm.stackrestore(i8* [[TMP53]]) 6605 // CHECK7-NEXT: ret i32 [[ADD6]] 6606 // 6607 // 6608 // CHECK7-LABEL: define {{[^@]+}}@_ZL7fstatici 6609 // CHECK7-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { 6610 // CHECK7-NEXT: entry: 6611 // CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 6612 // CHECK7-NEXT: [[A:%.*]] = alloca i32, align 4 6613 // CHECK7-NEXT: [[AA:%.*]] = alloca i16, align 2 6614 // CHECK7-NEXT: [[AAA:%.*]] = alloca i8, align 1 6615 // CHECK7-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 6616 // CHECK7-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 6617 // CHECK7-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 6618 // CHECK7-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 6619 // CHECK7-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 6620 // CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4 6621 // CHECK7-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4 6622 // CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4 6623 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 6624 // CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 6625 // CHECK7-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 6626 // CHECK7-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4 6627 // CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 6628 // CHECK7-NEXT: store i32 0, i32* [[A]], align 4 6629 // CHECK7-NEXT: store i16 0, i16* [[AA]], align 2 6630 // CHECK7-NEXT: store i8 0, i8* [[AAA]], align 1 6631 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 6632 // CHECK7-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 6633 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 6634 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 6635 // CHECK7-NEXT: store i32 [[TMP2]], i32* [[N_CASTED]], align 4 6636 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_CASTED]], align 4 6637 // CHECK7-NEXT: [[TMP4:%.*]] = load i16, i16* [[AA]], align 2 6638 // CHECK7-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 6639 // CHECK7-NEXT: store i16 [[TMP4]], i16* [[CONV]], align 2 6640 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[AA_CASTED]], align 4 6641 // CHECK7-NEXT: [[TMP6:%.*]] = load i8, i8* [[AAA]], align 1 6642 // CHECK7-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* 6643 // CHECK7-NEXT: store i8 [[TMP6]], i8* [[CONV1]], align 1 6644 // CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 6645 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[N_ADDR]], align 4 6646 // CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP8]], 50 6647 // CHECK7-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 6648 // CHECK7: omp_if.then: 6649 // CHECK7-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 6650 // CHECK7-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* 6651 // CHECK7-NEXT: store i32 [[TMP1]], i32* [[TMP10]], align 4 6652 // CHECK7-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 6653 // CHECK7-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32* 6654 // CHECK7-NEXT: store i32 [[TMP1]], i32* [[TMP12]], align 4 6655 // CHECK7-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 6656 // CHECK7-NEXT: store i8* null, i8** [[TMP13]], align 4 6657 // CHECK7-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 6658 // CHECK7-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32* 6659 // CHECK7-NEXT: store i32 [[TMP3]], i32* [[TMP15]], align 4 6660 // CHECK7-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 6661 // CHECK7-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32* 6662 // CHECK7-NEXT: store i32 [[TMP3]], i32* [[TMP17]], align 4 6663 // CHECK7-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 6664 // CHECK7-NEXT: store i8* null, i8** [[TMP18]], align 4 6665 // CHECK7-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 6666 // CHECK7-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32* 6667 // CHECK7-NEXT: store i32 [[TMP5]], i32* [[TMP20]], align 4 6668 // CHECK7-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 6669 // CHECK7-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i32* 6670 // CHECK7-NEXT: store i32 [[TMP5]], i32* [[TMP22]], align 4 6671 // CHECK7-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 6672 // CHECK7-NEXT: store i8* null, i8** [[TMP23]], align 4 6673 // CHECK7-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 6674 // CHECK7-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i32* 6675 // CHECK7-NEXT: store i32 [[TMP7]], i32* [[TMP25]], align 4 6676 // CHECK7-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 6677 // CHECK7-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i32* 6678 // CHECK7-NEXT: store i32 [[TMP7]], i32* [[TMP27]], align 4 6679 // CHECK7-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 6680 // CHECK7-NEXT: store i8* null, i8** [[TMP28]], align 4 6681 // CHECK7-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 6682 // CHECK7-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to [10 x i32]** 6683 // CHECK7-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP30]], align 4 6684 // CHECK7-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 6685 // CHECK7-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to [10 x i32]** 6686 // CHECK7-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP32]], align 4 6687 // CHECK7-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 6688 // CHECK7-NEXT: store i8* null, i8** [[TMP33]], align 4 6689 // CHECK7-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 6690 // CHECK7-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 6691 // CHECK7-NEXT: [[TMP36:%.*]] = load i32, i32* [[A]], align 4 6692 // CHECK7-NEXT: store i32 [[TMP36]], i32* [[DOTCAPTURE_EXPR_]], align 4 6693 // CHECK7-NEXT: [[TMP37:%.*]] = load i32, i32* [[N_ADDR]], align 4 6694 // CHECK7-NEXT: store i32 [[TMP37]], i32* [[DOTCAPTURE_EXPR_2]], align 4 6695 // CHECK7-NEXT: [[TMP38:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 6696 // CHECK7-NEXT: [[TMP39:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 6697 // CHECK7-NEXT: [[SUB:%.*]] = sub i32 [[TMP38]], [[TMP39]] 6698 // CHECK7-NEXT: [[SUB4:%.*]] = sub i32 [[SUB]], 1 6699 // CHECK7-NEXT: [[ADD:%.*]] = add i32 [[SUB4]], 1 6700 // CHECK7-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 6701 // CHECK7-NEXT: [[SUB5:%.*]] = sub i32 [[DIV]], 1 6702 // CHECK7-NEXT: store i32 [[SUB5]], i32* [[DOTCAPTURE_EXPR_3]], align 4 6703 // CHECK7-NEXT: [[TMP40:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 6704 // CHECK7-NEXT: [[ADD6:%.*]] = add i32 [[TMP40]], 1 6705 // CHECK7-NEXT: [[TMP41:%.*]] = zext i32 [[ADD6]] to i64 6706 // CHECK7-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 [[TMP41]]) 6707 // CHECK7-NEXT: [[TMP42:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197.region_id, i32 5, i8** [[TMP34]], i8** [[TMP35]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes.16, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.17, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1) 6708 // CHECK7-NEXT: [[TMP43:%.*]] = icmp ne i32 [[TMP42]], 0 6709 // CHECK7-NEXT: br i1 [[TMP43]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 6710 // CHECK7: omp_offload.failed: 6711 // CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], i32 [[TMP7]], [10 x i32]* [[B]]) #[[ATTR4]] 6712 // CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT]] 6713 // CHECK7: omp_offload.cont: 6714 // CHECK7-NEXT: br label [[OMP_IF_END:%.*]] 6715 // CHECK7: omp_if.else: 6716 // CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], i32 [[TMP7]], [10 x i32]* [[B]]) #[[ATTR4]] 6717 // CHECK7-NEXT: br label [[OMP_IF_END]] 6718 // CHECK7: omp_if.end: 6719 // CHECK7-NEXT: [[TMP44:%.*]] = load i32, i32* [[A]], align 4 6720 // CHECK7-NEXT: ret i32 [[TMP44]] 6721 // 6722 // 6723 // CHECK7-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 6724 // CHECK7-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat { 6725 // CHECK7-NEXT: entry: 6726 // CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 6727 // CHECK7-NEXT: [[A:%.*]] = alloca i32, align 4 6728 // CHECK7-NEXT: [[AA:%.*]] = alloca i16, align 2 6729 // CHECK7-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 6730 // CHECK7-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 6731 // CHECK7-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 6732 // CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 6733 // CHECK7-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 6734 // CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 6735 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 6736 // CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 6737 // CHECK7-NEXT: store i32 0, i32* [[A]], align 4 6738 // CHECK7-NEXT: store i16 0, i16* [[AA]], align 2 6739 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 6740 // CHECK7-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 6741 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 6742 // CHECK7-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 6743 // CHECK7-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 6744 // CHECK7-NEXT: store i16 [[TMP2]], i16* [[CONV]], align 2 6745 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 6746 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 6747 // CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40 6748 // CHECK7-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 6749 // CHECK7: omp_if.then: 6750 // CHECK7-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 6751 // CHECK7-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i32* 6752 // CHECK7-NEXT: store i32 [[TMP1]], i32* [[TMP6]], align 4 6753 // CHECK7-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 6754 // CHECK7-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* 6755 // CHECK7-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4 6756 // CHECK7-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 6757 // CHECK7-NEXT: store i8* null, i8** [[TMP9]], align 4 6758 // CHECK7-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 6759 // CHECK7-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i32* 6760 // CHECK7-NEXT: store i32 [[TMP3]], i32* [[TMP11]], align 4 6761 // CHECK7-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 6762 // CHECK7-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* 6763 // CHECK7-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4 6764 // CHECK7-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 6765 // CHECK7-NEXT: store i8* null, i8** [[TMP14]], align 4 6766 // CHECK7-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 6767 // CHECK7-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]** 6768 // CHECK7-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 4 6769 // CHECK7-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 6770 // CHECK7-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]** 6771 // CHECK7-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 4 6772 // CHECK7-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 6773 // CHECK7-NEXT: store i8* null, i8** [[TMP19]], align 4 6774 // CHECK7-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 6775 // CHECK7-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 6776 // CHECK7-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) 6777 // CHECK7-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.19, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.20, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1) 6778 // CHECK7-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 6779 // CHECK7-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 6780 // CHECK7: omp_offload.failed: 6781 // CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]] 6782 // CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT]] 6783 // CHECK7: omp_offload.cont: 6784 // CHECK7-NEXT: br label [[OMP_IF_END:%.*]] 6785 // CHECK7: omp_if.else: 6786 // CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]] 6787 // CHECK7-NEXT: br label [[OMP_IF_END]] 6788 // CHECK7: omp_if.end: 6789 // CHECK7-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4 6790 // CHECK7-NEXT: ret i32 [[TMP24]] 6791 // 6792 // 6793 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215 6794 // CHECK7-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { 6795 // CHECK7-NEXT: entry: 6796 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 6797 // CHECK7-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 6798 // CHECK7-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 6799 // CHECK7-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 6800 // CHECK7-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 6801 // CHECK7-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 6802 // CHECK7-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 6803 // CHECK7-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 6804 // CHECK7-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 6805 // CHECK7-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 6806 // CHECK7-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 6807 // CHECK7-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 6808 // CHECK7-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 6809 // CHECK7-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 6810 // CHECK7-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 6811 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 6812 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 6813 // CHECK7-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 6814 // CHECK7-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8* 6815 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 6816 // CHECK7-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 6817 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 6818 // CHECK7-NEXT: [[TMP6:%.*]] = load i8, i8* [[CONV]], align 1 6819 // CHECK7-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP6]] to i1 6820 // CHECK7-NEXT: [[CONV3:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__CASTED]] to i8* 6821 // CHECK7-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 6822 // CHECK7-NEXT: store i8 [[FROMBOOL]], i8* [[CONV3]], align 1 6823 // CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 6824 // CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*, i32)* @.omp_outlined..12 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]], i32 [[TMP7]]) 6825 // CHECK7-NEXT: ret void 6826 // 6827 // 6828 // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..12 6829 // CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { 6830 // CHECK7-NEXT: entry: 6831 // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 6832 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 6833 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 6834 // CHECK7-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 6835 // CHECK7-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 6836 // CHECK7-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 6837 // CHECK7-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 6838 // CHECK7-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 6839 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 6840 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 6841 // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 6842 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 6843 // CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 6844 // CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 6845 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 6846 // CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 6847 // CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 6848 // CHECK7-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 6849 // CHECK7-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 6850 // CHECK7-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 6851 // CHECK7-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 6852 // CHECK7-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 6853 // CHECK7-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 6854 // CHECK7-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 6855 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 6856 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 6857 // CHECK7-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 6858 // CHECK7-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8* 6859 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 6860 // CHECK7-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 6861 // CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 6862 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 6863 // CHECK7-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 6864 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 6865 // CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 6866 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 6867 // CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 9 6868 // CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 6869 // CHECK7: cond.true: 6870 // CHECK7-NEXT: br label [[COND_END:%.*]] 6871 // CHECK7: cond.false: 6872 // CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 6873 // CHECK7-NEXT: br label [[COND_END]] 6874 // CHECK7: cond.end: 6875 // CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 6876 // CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 6877 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 6878 // CHECK7-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 6879 // CHECK7-NEXT: [[TMP9:%.*]] = load i8, i8* [[CONV]], align 1 6880 // CHECK7-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP9]] to i1 6881 // CHECK7-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 6882 // CHECK7: omp_if.then: 6883 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 6884 // CHECK7: omp.inner.for.cond: 6885 // CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !40 6886 // CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !40 6887 // CHECK7-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]] 6888 // CHECK7-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 6889 // CHECK7: omp.inner.for.body: 6890 // CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !40 6891 // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1 6892 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 6893 // CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !40 6894 // CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[B_ADDR]], align 4, !llvm.access.group !40 6895 // CHECK7-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP13]] to double 6896 // CHECK7-NEXT: [[ADD5:%.*]] = fadd double [[CONV4]], 1.500000e+00 6897 // CHECK7-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 6898 // CHECK7-NEXT: store double [[ADD5]], double* [[A]], align 4, !llvm.access.group !40 6899 // CHECK7-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 6900 // CHECK7-NEXT: [[TMP14:%.*]] = load double, double* [[A6]], align 4, !llvm.access.group !40 6901 // CHECK7-NEXT: [[INC:%.*]] = fadd double [[TMP14]], 1.000000e+00 6902 // CHECK7-NEXT: store double [[INC]], double* [[A6]], align 4, !llvm.access.group !40 6903 // CHECK7-NEXT: [[CONV7:%.*]] = fptosi double [[INC]] to i16 6904 // CHECK7-NEXT: [[TMP15:%.*]] = mul nsw i32 1, [[TMP2]] 6905 // CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP15]] 6906 // CHECK7-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 6907 // CHECK7-NEXT: store i16 [[CONV7]], i16* [[ARRAYIDX8]], align 2, !llvm.access.group !40 6908 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 6909 // CHECK7: omp.body.continue: 6910 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 6911 // CHECK7: omp.inner.for.inc: 6912 // CHECK7-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !40 6913 // CHECK7-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP16]], 1 6914 // CHECK7-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !40 6915 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP41:![0-9]+]] 6916 // CHECK7: omp.inner.for.end: 6917 // CHECK7-NEXT: br label [[OMP_IF_END:%.*]] 6918 // CHECK7: omp_if.else: 6919 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND10:%.*]] 6920 // CHECK7: omp.inner.for.cond10: 6921 // CHECK7-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 6922 // CHECK7-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 6923 // CHECK7-NEXT: [[CMP11:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]] 6924 // CHECK7-NEXT: br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY12:%.*]], label [[OMP_INNER_FOR_END26:%.*]] 6925 // CHECK7: omp.inner.for.body12: 6926 // CHECK7-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 6927 // CHECK7-NEXT: [[MUL13:%.*]] = mul nsw i32 [[TMP19]], 1 6928 // CHECK7-NEXT: [[ADD14:%.*]] = add nsw i32 0, [[MUL13]] 6929 // CHECK7-NEXT: store i32 [[ADD14]], i32* [[I]], align 4 6930 // CHECK7-NEXT: [[TMP20:%.*]] = load i32, i32* [[B_ADDR]], align 4 6931 // CHECK7-NEXT: [[CONV15:%.*]] = sitofp i32 [[TMP20]] to double 6932 // CHECK7-NEXT: [[ADD16:%.*]] = fadd double [[CONV15]], 1.500000e+00 6933 // CHECK7-NEXT: [[A17:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 6934 // CHECK7-NEXT: store double [[ADD16]], double* [[A17]], align 4 6935 // CHECK7-NEXT: [[A18:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 6936 // CHECK7-NEXT: [[TMP21:%.*]] = load double, double* [[A18]], align 4 6937 // CHECK7-NEXT: [[INC19:%.*]] = fadd double [[TMP21]], 1.000000e+00 6938 // CHECK7-NEXT: store double [[INC19]], double* [[A18]], align 4 6939 // CHECK7-NEXT: [[CONV20:%.*]] = fptosi double [[INC19]] to i16 6940 // CHECK7-NEXT: [[TMP22:%.*]] = mul nsw i32 1, [[TMP2]] 6941 // CHECK7-NEXT: [[ARRAYIDX21:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP22]] 6942 // CHECK7-NEXT: [[ARRAYIDX22:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX21]], i32 1 6943 // CHECK7-NEXT: store i16 [[CONV20]], i16* [[ARRAYIDX22]], align 2 6944 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE23:%.*]] 6945 // CHECK7: omp.body.continue23: 6946 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC24:%.*]] 6947 // CHECK7: omp.inner.for.inc24: 6948 // CHECK7-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 6949 // CHECK7-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP23]], 1 6950 // CHECK7-NEXT: store i32 [[ADD25]], i32* [[DOTOMP_IV]], align 4 6951 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND10]], !llvm.loop [[LOOP43:![0-9]+]] 6952 // CHECK7: omp.inner.for.end26: 6953 // CHECK7-NEXT: br label [[OMP_IF_END]] 6954 // CHECK7: omp_if.end: 6955 // CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 6956 // CHECK7: omp.loop.exit: 6957 // CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 6958 // CHECK7-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 6959 // CHECK7-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 6960 // CHECK7-NEXT: br i1 [[TMP25]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 6961 // CHECK7: .omp.final.then: 6962 // CHECK7-NEXT: store i32 10, i32* [[I]], align 4 6963 // CHECK7-NEXT: br label [[DOTOMP_FINAL_DONE]] 6964 // CHECK7: .omp.final.done: 6965 // CHECK7-NEXT: ret void 6966 // 6967 // 6968 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197 6969 // CHECK7-SAME: (i32 noundef [[A:%.*]], i32 noundef [[N:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 6970 // CHECK7-NEXT: entry: 6971 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 6972 // CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 6973 // CHECK7-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 6974 // CHECK7-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 6975 // CHECK7-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 6976 // CHECK7-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 6977 // CHECK7-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 6978 // CHECK7-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 6979 // CHECK7-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 6980 // CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 6981 // CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 6982 // CHECK7-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 6983 // CHECK7-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 6984 // CHECK7-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 6985 // CHECK7-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 6986 // CHECK7-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 6987 // CHECK7-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 6988 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 6989 // CHECK7-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 6990 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 6991 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 6992 // CHECK7-NEXT: store i32 [[TMP3]], i32* [[N_CASTED]], align 4 6993 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_CASTED]], align 4 6994 // CHECK7-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 2 6995 // CHECK7-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 6996 // CHECK7-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2 6997 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[AA_CASTED]], align 4 6998 // CHECK7-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV1]], align 1 6999 // CHECK7-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* 7000 // CHECK7-NEXT: store i8 [[TMP7]], i8* [[CONV3]], align 1 7001 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 7002 // CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, [10 x i32]*)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP8]], [10 x i32]* [[TMP0]]) 7003 // CHECK7-NEXT: ret void 7004 // 7005 // 7006 // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..15 7007 // CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[N:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { 7008 // CHECK7-NEXT: entry: 7009 // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 7010 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 7011 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 7012 // CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 7013 // CHECK7-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 7014 // CHECK7-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 7015 // CHECK7-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 7016 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 7017 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 7018 // CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 7019 // CHECK7-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 7020 // CHECK7-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4 7021 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 7022 // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 7023 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 7024 // CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 7025 // CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 7026 // CHECK7-NEXT: [[I6:%.*]] = alloca i32, align 4 7027 // CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 7028 // CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 7029 // CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 7030 // CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 7031 // CHECK7-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 7032 // CHECK7-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 7033 // CHECK7-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 7034 // CHECK7-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 7035 // CHECK7-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 7036 // CHECK7-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 7037 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 7038 // CHECK7-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 7039 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 7040 // CHECK7-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4 7041 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 7042 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 7043 // CHECK7-NEXT: [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]] 7044 // CHECK7-NEXT: [[SUB4:%.*]] = sub i32 [[SUB]], 1 7045 // CHECK7-NEXT: [[ADD:%.*]] = add i32 [[SUB4]], 1 7046 // CHECK7-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 7047 // CHECK7-NEXT: [[SUB5:%.*]] = sub i32 [[DIV]], 1 7048 // CHECK7-NEXT: store i32 [[SUB5]], i32* [[DOTCAPTURE_EXPR_3]], align 4 7049 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 7050 // CHECK7-NEXT: store i32 [[TMP5]], i32* [[I]], align 4 7051 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 7052 // CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 7053 // CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]] 7054 // CHECK7-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] 7055 // CHECK7: omp.precond.then: 7056 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 7057 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 7058 // CHECK7-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_UB]], align 4 7059 // CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 7060 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 7061 // CHECK7-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 7062 // CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 7063 // CHECK7-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 7064 // CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 7065 // CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 7066 // CHECK7-NEXT: [[CMP7:%.*]] = icmp ugt i32 [[TMP11]], [[TMP12]] 7067 // CHECK7-NEXT: br i1 [[CMP7]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 7068 // CHECK7: cond.true: 7069 // CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 7070 // CHECK7-NEXT: br label [[COND_END:%.*]] 7071 // CHECK7: cond.false: 7072 // CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 7073 // CHECK7-NEXT: br label [[COND_END]] 7074 // CHECK7: cond.end: 7075 // CHECK7-NEXT: [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ] 7076 // CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 7077 // CHECK7-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 7078 // CHECK7-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4 7079 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 7080 // CHECK7: omp.inner.for.cond: 7081 // CHECK7-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !45 7082 // CHECK7-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !45 7083 // CHECK7-NEXT: [[ADD8:%.*]] = add i32 [[TMP17]], 1 7084 // CHECK7-NEXT: [[CMP9:%.*]] = icmp ult i32 [[TMP16]], [[ADD8]] 7085 // CHECK7-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 7086 // CHECK7: omp.inner.for.body: 7087 // CHECK7-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group !45 7088 // CHECK7-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !45 7089 // CHECK7-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 1 7090 // CHECK7-NEXT: [[ADD10:%.*]] = add i32 [[TMP18]], [[MUL]] 7091 // CHECK7-NEXT: store i32 [[ADD10]], i32* [[I6]], align 4, !llvm.access.group !45 7092 // CHECK7-NEXT: [[TMP20:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !45 7093 // CHECK7-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP20]], 1 7094 // CHECK7-NEXT: store i32 [[ADD11]], i32* [[A_ADDR]], align 4, !llvm.access.group !45 7095 // CHECK7-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !45 7096 // CHECK7-NEXT: [[CONV12:%.*]] = sext i16 [[TMP21]] to i32 7097 // CHECK7-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1 7098 // CHECK7-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16 7099 // CHECK7-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 2, !llvm.access.group !45 7100 // CHECK7-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV1]], align 1, !llvm.access.group !45 7101 // CHECK7-NEXT: [[CONV15:%.*]] = sext i8 [[TMP22]] to i32 7102 // CHECK7-NEXT: [[ADD16:%.*]] = add nsw i32 [[CONV15]], 1 7103 // CHECK7-NEXT: [[CONV17:%.*]] = trunc i32 [[ADD16]] to i8 7104 // CHECK7-NEXT: store i8 [[CONV17]], i8* [[CONV1]], align 1, !llvm.access.group !45 7105 // CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 7106 // CHECK7-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !45 7107 // CHECK7-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP23]], 1 7108 // CHECK7-NEXT: store i32 [[ADD18]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !45 7109 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 7110 // CHECK7: omp.body.continue: 7111 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 7112 // CHECK7: omp.inner.for.inc: 7113 // CHECK7-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !45 7114 // CHECK7-NEXT: [[ADD19:%.*]] = add i32 [[TMP24]], 1 7115 // CHECK7-NEXT: store i32 [[ADD19]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !45 7116 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP46:![0-9]+]] 7117 // CHECK7: omp.inner.for.end: 7118 // CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 7119 // CHECK7: omp.loop.exit: 7120 // CHECK7-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 7121 // CHECK7-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 7122 // CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) 7123 // CHECK7-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 7124 // CHECK7-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0 7125 // CHECK7-NEXT: br i1 [[TMP28]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 7126 // CHECK7: .omp.final.then: 7127 // CHECK7-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 7128 // CHECK7-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 7129 // CHECK7-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 7130 // CHECK7-NEXT: [[SUB20:%.*]] = sub i32 [[TMP30]], [[TMP31]] 7131 // CHECK7-NEXT: [[SUB21:%.*]] = sub i32 [[SUB20]], 1 7132 // CHECK7-NEXT: [[ADD22:%.*]] = add i32 [[SUB21]], 1 7133 // CHECK7-NEXT: [[DIV23:%.*]] = udiv i32 [[ADD22]], 1 7134 // CHECK7-NEXT: [[MUL24:%.*]] = mul i32 [[DIV23]], 1 7135 // CHECK7-NEXT: [[ADD25:%.*]] = add i32 [[TMP29]], [[MUL24]] 7136 // CHECK7-NEXT: store i32 [[ADD25]], i32* [[I6]], align 4 7137 // CHECK7-NEXT: br label [[DOTOMP_FINAL_DONE]] 7138 // CHECK7: .omp.final.done: 7139 // CHECK7-NEXT: br label [[OMP_PRECOND_END]] 7140 // CHECK7: omp.precond.end: 7141 // CHECK7-NEXT: ret void 7142 // 7143 // 7144 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180 7145 // CHECK7-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 7146 // CHECK7-NEXT: entry: 7147 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 7148 // CHECK7-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 7149 // CHECK7-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 7150 // CHECK7-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 7151 // CHECK7-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 7152 // CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 7153 // CHECK7-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 7154 // CHECK7-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 7155 // CHECK7-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 7156 // CHECK7-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 7157 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 7158 // CHECK7-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 7159 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 7160 // CHECK7-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 7161 // CHECK7-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 7162 // CHECK7-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 7163 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 7164 // CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..18 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) 7165 // CHECK7-NEXT: ret void 7166 // 7167 // 7168 // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..18 7169 // CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { 7170 // CHECK7-NEXT: entry: 7171 // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 7172 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 7173 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 7174 // CHECK7-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 7175 // CHECK7-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 7176 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 7177 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 7178 // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 7179 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 7180 // CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 7181 // CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 7182 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 7183 // CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 7184 // CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 7185 // CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 7186 // CHECK7-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 7187 // CHECK7-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 7188 // CHECK7-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 7189 // CHECK7-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 7190 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 7191 // CHECK7-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 7192 // CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 7193 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 7194 // CHECK7-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 7195 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 7196 // CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 7197 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 7198 // CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 7199 // CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 7200 // CHECK7: cond.true: 7201 // CHECK7-NEXT: br label [[COND_END:%.*]] 7202 // CHECK7: cond.false: 7203 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 7204 // CHECK7-NEXT: br label [[COND_END]] 7205 // CHECK7: cond.end: 7206 // CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 7207 // CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 7208 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 7209 // CHECK7-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 7210 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 7211 // CHECK7: omp.inner.for.cond: 7212 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !48 7213 // CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !48 7214 // CHECK7-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] 7215 // CHECK7-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 7216 // CHECK7: omp.inner.for.body: 7217 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !48 7218 // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 7219 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 7220 // CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !48 7221 // CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !48 7222 // CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 7223 // CHECK7-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4, !llvm.access.group !48 7224 // CHECK7-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !48 7225 // CHECK7-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32 7226 // CHECK7-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 7227 // CHECK7-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 7228 // CHECK7-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2, !llvm.access.group !48 7229 // CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 7230 // CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !48 7231 // CHECK7-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1 7232 // CHECK7-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !48 7233 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 7234 // CHECK7: omp.body.continue: 7235 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 7236 // CHECK7: omp.inner.for.inc: 7237 // CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !48 7238 // CHECK7-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP12]], 1 7239 // CHECK7-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !48 7240 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP49:![0-9]+]] 7241 // CHECK7: omp.inner.for.end: 7242 // CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 7243 // CHECK7: omp.loop.exit: 7244 // CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) 7245 // CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 7246 // CHECK7-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 7247 // CHECK7-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 7248 // CHECK7: .omp.final.then: 7249 // CHECK7-NEXT: store i32 10, i32* [[I]], align 4 7250 // CHECK7-NEXT: br label [[DOTOMP_FINAL_DONE]] 7251 // CHECK7: .omp.final.done: 7252 // CHECK7-NEXT: ret void 7253 // 7254 // 7255 // CHECK7-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 7256 // CHECK7-SAME: () #[[ATTR5]] { 7257 // CHECK7-NEXT: entry: 7258 // CHECK7-NEXT: call void @__tgt_register_requires(i64 1) 7259 // CHECK7-NEXT: ret void 7260 // 7261 // 7262 // CHECK9-LABEL: define {{[^@]+}}@_Z3fooi 7263 // CHECK9-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { 7264 // CHECK9-NEXT: entry: 7265 // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 7266 // CHECK9-NEXT: [[A:%.*]] = alloca i32, align 4 7267 // CHECK9-NEXT: [[AA:%.*]] = alloca i16, align 2 7268 // CHECK9-NEXT: [[B:%.*]] = alloca [10 x float], align 4 7269 // CHECK9-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 7270 // CHECK9-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 7271 // CHECK9-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 7272 // CHECK9-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 7273 // CHECK9-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 7274 // CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 7275 // CHECK9-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 7276 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 7277 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 7278 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 7279 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 7280 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 7281 // CHECK9-NEXT: [[_TMP4:%.*]] = alloca i32, align 4 7282 // CHECK9-NEXT: [[DOTOMP_LB5:%.*]] = alloca i32, align 4 7283 // CHECK9-NEXT: [[DOTOMP_UB6:%.*]] = alloca i32, align 4 7284 // CHECK9-NEXT: [[DOTOMP_IV7:%.*]] = alloca i32, align 4 7285 // CHECK9-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4 7286 // CHECK9-NEXT: [[A8:%.*]] = alloca i32, align 4 7287 // CHECK9-NEXT: [[A9:%.*]] = alloca i32, align 4 7288 // CHECK9-NEXT: [[_TMP20:%.*]] = alloca i32, align 4 7289 // CHECK9-NEXT: [[DOTOMP_LB21:%.*]] = alloca i32, align 4 7290 // CHECK9-NEXT: [[DOTOMP_UB22:%.*]] = alloca i32, align 4 7291 // CHECK9-NEXT: [[DOTOMP_IV23:%.*]] = alloca i32, align 4 7292 // CHECK9-NEXT: [[I24:%.*]] = alloca i32, align 4 7293 // CHECK9-NEXT: [[_TMP36:%.*]] = alloca i32, align 4 7294 // CHECK9-NEXT: [[DOTOMP_LB37:%.*]] = alloca i32, align 4 7295 // CHECK9-NEXT: [[DOTOMP_UB38:%.*]] = alloca i32, align 4 7296 // CHECK9-NEXT: [[DOTOMP_IV39:%.*]] = alloca i32, align 4 7297 // CHECK9-NEXT: [[I40:%.*]] = alloca i32, align 4 7298 // CHECK9-NEXT: [[_TMP54:%.*]] = alloca i32, align 4 7299 // CHECK9-NEXT: [[DOTOMP_LB55:%.*]] = alloca i32, align 4 7300 // CHECK9-NEXT: [[DOTOMP_UB56:%.*]] = alloca i32, align 4 7301 // CHECK9-NEXT: [[DOTOMP_IV57:%.*]] = alloca i32, align 4 7302 // CHECK9-NEXT: [[I58:%.*]] = alloca i32, align 4 7303 // CHECK9-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 7304 // CHECK9-NEXT: store i32 0, i32* [[A]], align 4 7305 // CHECK9-NEXT: store i16 0, i16* [[AA]], align 2 7306 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 7307 // CHECK9-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 7308 // CHECK9-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() 7309 // CHECK9-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 7310 // CHECK9-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4 7311 // CHECK9-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 7312 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 7313 // CHECK9-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64 7314 // CHECK9-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]] 7315 // CHECK9-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8 7316 // CHECK9-NEXT: store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8 7317 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 7318 // CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_]], align 4 7319 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 7320 // CHECK9-NEXT: store i32 [[TMP7]], i32* [[DOTCAPTURE_EXPR_2]], align 4 7321 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 7322 // CHECK9-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 7323 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 7324 // CHECK9-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 7325 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 7326 // CHECK9: omp.inner.for.cond: 7327 // CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 7328 // CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !2 7329 // CHECK9-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 7330 // CHECK9-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 7331 // CHECK9: omp.inner.for.body: 7332 // CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 7333 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 7334 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 7335 // CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !2 7336 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 7337 // CHECK9: omp.body.continue: 7338 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 7339 // CHECK9: omp.inner.for.inc: 7340 // CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 7341 // CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 7342 // CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 7343 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] 7344 // CHECK9: omp.inner.for.end: 7345 // CHECK9-NEXT: store i32 10, i32* [[I]], align 4 7346 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB5]], align 4 7347 // CHECK9-NEXT: store i32 9, i32* [[DOTOMP_UB6]], align 4 7348 // CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB5]], align 4 7349 // CHECK9-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV7]], align 4 7350 // CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[A]], align 4 7351 // CHECK9-NEXT: store i32 [[TMP14]], i32* [[DOTLINEAR_START]], align 4 7352 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND10:%.*]] 7353 // CHECK9: omp.inner.for.cond10: 7354 // CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV7]], align 4 7355 // CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB6]], align 4 7356 // CHECK9-NEXT: [[CMP11:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] 7357 // CHECK9-NEXT: br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY12:%.*]], label [[OMP_INNER_FOR_END19:%.*]] 7358 // CHECK9: omp.inner.for.body12: 7359 // CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV7]], align 4 7360 // CHECK9-NEXT: [[MUL13:%.*]] = mul nsw i32 [[TMP17]], 1 7361 // CHECK9-NEXT: [[ADD14:%.*]] = add nsw i32 0, [[MUL13]] 7362 // CHECK9-NEXT: store i32 [[ADD14]], i32* [[A8]], align 4 7363 // CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[A8]], align 4 7364 // CHECK9-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP18]], 1 7365 // CHECK9-NEXT: store i32 [[ADD15]], i32* [[A8]], align 4 7366 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE16:%.*]] 7367 // CHECK9: omp.body.continue16: 7368 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC17:%.*]] 7369 // CHECK9: omp.inner.for.inc17: 7370 // CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV7]], align 4 7371 // CHECK9-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP19]], 1 7372 // CHECK9-NEXT: store i32 [[ADD18]], i32* [[DOTOMP_IV7]], align 4 7373 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND10]], !llvm.loop [[LOOP7:![0-9]+]] 7374 // CHECK9: omp.inner.for.end19: 7375 // CHECK9-NEXT: store i32 10, i32* [[A]], align 4 7376 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB21]], align 4 7377 // CHECK9-NEXT: store i32 9, i32* [[DOTOMP_UB22]], align 4 7378 // CHECK9-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_LB21]], align 4 7379 // CHECK9-NEXT: store i32 [[TMP20]], i32* [[DOTOMP_IV23]], align 4 7380 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND25:%.*]] 7381 // CHECK9: omp.inner.for.cond25: 7382 // CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV23]], align 4, !llvm.access.group !9 7383 // CHECK9-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_UB22]], align 4, !llvm.access.group !9 7384 // CHECK9-NEXT: [[CMP26:%.*]] = icmp sle i32 [[TMP21]], [[TMP22]] 7385 // CHECK9-NEXT: br i1 [[CMP26]], label [[OMP_INNER_FOR_BODY27:%.*]], label [[OMP_INNER_FOR_END35:%.*]] 7386 // CHECK9: omp.inner.for.body27: 7387 // CHECK9-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV23]], align 4, !llvm.access.group !9 7388 // CHECK9-NEXT: [[MUL28:%.*]] = mul nsw i32 [[TMP23]], 1 7389 // CHECK9-NEXT: [[ADD29:%.*]] = add nsw i32 0, [[MUL28]] 7390 // CHECK9-NEXT: store i32 [[ADD29]], i32* [[I24]], align 4, !llvm.access.group !9 7391 // CHECK9-NEXT: [[TMP24:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !9 7392 // CHECK9-NEXT: [[CONV:%.*]] = sext i16 [[TMP24]] to i32 7393 // CHECK9-NEXT: [[ADD30:%.*]] = add nsw i32 [[CONV]], 1 7394 // CHECK9-NEXT: [[CONV31:%.*]] = trunc i32 [[ADD30]] to i16 7395 // CHECK9-NEXT: store i16 [[CONV31]], i16* [[AA]], align 2, !llvm.access.group !9 7396 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE32:%.*]] 7397 // CHECK9: omp.body.continue32: 7398 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC33:%.*]] 7399 // CHECK9: omp.inner.for.inc33: 7400 // CHECK9-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IV23]], align 4, !llvm.access.group !9 7401 // CHECK9-NEXT: [[ADD34:%.*]] = add nsw i32 [[TMP25]], 1 7402 // CHECK9-NEXT: store i32 [[ADD34]], i32* [[DOTOMP_IV23]], align 4, !llvm.access.group !9 7403 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND25]], !llvm.loop [[LOOP10:![0-9]+]] 7404 // CHECK9: omp.inner.for.end35: 7405 // CHECK9-NEXT: store i32 10, i32* [[I24]], align 4 7406 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB37]], align 4 7407 // CHECK9-NEXT: store i32 9, i32* [[DOTOMP_UB38]], align 4 7408 // CHECK9-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_LB37]], align 4 7409 // CHECK9-NEXT: store i32 [[TMP26]], i32* [[DOTOMP_IV39]], align 4 7410 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND41:%.*]] 7411 // CHECK9: omp.inner.for.cond41: 7412 // CHECK9-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV39]], align 4, !llvm.access.group !12 7413 // CHECK9-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_UB38]], align 4, !llvm.access.group !12 7414 // CHECK9-NEXT: [[CMP42:%.*]] = icmp sle i32 [[TMP27]], [[TMP28]] 7415 // CHECK9-NEXT: br i1 [[CMP42]], label [[OMP_INNER_FOR_BODY43:%.*]], label [[OMP_INNER_FOR_END53:%.*]] 7416 // CHECK9: omp.inner.for.body43: 7417 // CHECK9-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_IV39]], align 4, !llvm.access.group !12 7418 // CHECK9-NEXT: [[MUL44:%.*]] = mul nsw i32 [[TMP29]], 1 7419 // CHECK9-NEXT: [[ADD45:%.*]] = add nsw i32 0, [[MUL44]] 7420 // CHECK9-NEXT: store i32 [[ADD45]], i32* [[I40]], align 4, !llvm.access.group !12 7421 // CHECK9-NEXT: [[TMP30:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !12 7422 // CHECK9-NEXT: [[ADD46:%.*]] = add nsw i32 [[TMP30]], 1 7423 // CHECK9-NEXT: store i32 [[ADD46]], i32* [[A]], align 4, !llvm.access.group !12 7424 // CHECK9-NEXT: [[TMP31:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !12 7425 // CHECK9-NEXT: [[CONV47:%.*]] = sext i16 [[TMP31]] to i32 7426 // CHECK9-NEXT: [[ADD48:%.*]] = add nsw i32 [[CONV47]], 1 7427 // CHECK9-NEXT: [[CONV49:%.*]] = trunc i32 [[ADD48]] to i16 7428 // CHECK9-NEXT: store i16 [[CONV49]], i16* [[AA]], align 2, !llvm.access.group !12 7429 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE50:%.*]] 7430 // CHECK9: omp.body.continue50: 7431 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC51:%.*]] 7432 // CHECK9: omp.inner.for.inc51: 7433 // CHECK9-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTOMP_IV39]], align 4, !llvm.access.group !12 7434 // CHECK9-NEXT: [[ADD52:%.*]] = add nsw i32 [[TMP32]], 1 7435 // CHECK9-NEXT: store i32 [[ADD52]], i32* [[DOTOMP_IV39]], align 4, !llvm.access.group !12 7436 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND41]], !llvm.loop [[LOOP13:![0-9]+]] 7437 // CHECK9: omp.inner.for.end53: 7438 // CHECK9-NEXT: store i32 10, i32* [[I40]], align 4 7439 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB55]], align 4 7440 // CHECK9-NEXT: store i32 9, i32* [[DOTOMP_UB56]], align 4 7441 // CHECK9-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTOMP_LB55]], align 4 7442 // CHECK9-NEXT: store i32 [[TMP33]], i32* [[DOTOMP_IV57]], align 4 7443 // CHECK9-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 0 7444 // CHECK9-NEXT: call void @llvm.assume(i1 true) [ "align"(float* [[ARRAYDECAY]], i64 16) ] 7445 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND59:%.*]] 7446 // CHECK9: omp.inner.for.cond59: 7447 // CHECK9-NEXT: [[TMP34:%.*]] = load i32, i32* [[DOTOMP_IV57]], align 4, !llvm.access.group !15 7448 // CHECK9-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTOMP_UB56]], align 4, !llvm.access.group !15 7449 // CHECK9-NEXT: [[CMP60:%.*]] = icmp sle i32 [[TMP34]], [[TMP35]] 7450 // CHECK9-NEXT: br i1 [[CMP60]], label [[OMP_INNER_FOR_BODY61:%.*]], label [[OMP_INNER_FOR_END85:%.*]] 7451 // CHECK9: omp.inner.for.body61: 7452 // CHECK9-NEXT: [[TMP36:%.*]] = load i32, i32* [[DOTOMP_IV57]], align 4, !llvm.access.group !15 7453 // CHECK9-NEXT: [[MUL62:%.*]] = mul nsw i32 [[TMP36]], 1 7454 // CHECK9-NEXT: [[ADD63:%.*]] = add nsw i32 0, [[MUL62]] 7455 // CHECK9-NEXT: store i32 [[ADD63]], i32* [[I58]], align 4, !llvm.access.group !15 7456 // CHECK9-NEXT: [[TMP37:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !15 7457 // CHECK9-NEXT: [[ADD64:%.*]] = add nsw i32 [[TMP37]], 1 7458 // CHECK9-NEXT: store i32 [[ADD64]], i32* [[A]], align 4, !llvm.access.group !15 7459 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2 7460 // CHECK9-NEXT: [[TMP38:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !15 7461 // CHECK9-NEXT: [[CONV65:%.*]] = fpext float [[TMP38]] to double 7462 // CHECK9-NEXT: [[ADD66:%.*]] = fadd double [[CONV65]], 1.000000e+00 7463 // CHECK9-NEXT: [[CONV67:%.*]] = fptrunc double [[ADD66]] to float 7464 // CHECK9-NEXT: store float [[CONV67]], float* [[ARRAYIDX]], align 4, !llvm.access.group !15 7465 // CHECK9-NEXT: [[ARRAYIDX68:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3 7466 // CHECK9-NEXT: [[TMP39:%.*]] = load float, float* [[ARRAYIDX68]], align 4, !llvm.access.group !15 7467 // CHECK9-NEXT: [[CONV69:%.*]] = fpext float [[TMP39]] to double 7468 // CHECK9-NEXT: [[ADD70:%.*]] = fadd double [[CONV69]], 1.000000e+00 7469 // CHECK9-NEXT: [[CONV71:%.*]] = fptrunc double [[ADD70]] to float 7470 // CHECK9-NEXT: store float [[CONV71]], float* [[ARRAYIDX68]], align 4, !llvm.access.group !15 7471 // CHECK9-NEXT: [[ARRAYIDX72:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1 7472 // CHECK9-NEXT: [[ARRAYIDX73:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX72]], i64 0, i64 2 7473 // CHECK9-NEXT: [[TMP40:%.*]] = load double, double* [[ARRAYIDX73]], align 8, !llvm.access.group !15 7474 // CHECK9-NEXT: [[ADD74:%.*]] = fadd double [[TMP40]], 1.000000e+00 7475 // CHECK9-NEXT: store double [[ADD74]], double* [[ARRAYIDX73]], align 8, !llvm.access.group !15 7476 // CHECK9-NEXT: [[TMP41:%.*]] = mul nsw i64 1, [[TMP4]] 7477 // CHECK9-NEXT: [[ARRAYIDX75:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP41]] 7478 // CHECK9-NEXT: [[ARRAYIDX76:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX75]], i64 3 7479 // CHECK9-NEXT: [[TMP42:%.*]] = load double, double* [[ARRAYIDX76]], align 8, !llvm.access.group !15 7480 // CHECK9-NEXT: [[ADD77:%.*]] = fadd double [[TMP42]], 1.000000e+00 7481 // CHECK9-NEXT: store double [[ADD77]], double* [[ARRAYIDX76]], align 8, !llvm.access.group !15 7482 // CHECK9-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 7483 // CHECK9-NEXT: [[TMP43:%.*]] = load i64, i64* [[X]], align 8, !llvm.access.group !15 7484 // CHECK9-NEXT: [[ADD78:%.*]] = add nsw i64 [[TMP43]], 1 7485 // CHECK9-NEXT: store i64 [[ADD78]], i64* [[X]], align 8, !llvm.access.group !15 7486 // CHECK9-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 7487 // CHECK9-NEXT: [[TMP44:%.*]] = load i8, i8* [[Y]], align 8, !llvm.access.group !15 7488 // CHECK9-NEXT: [[CONV79:%.*]] = sext i8 [[TMP44]] to i32 7489 // CHECK9-NEXT: [[ADD80:%.*]] = add nsw i32 [[CONV79]], 1 7490 // CHECK9-NEXT: [[CONV81:%.*]] = trunc i32 [[ADD80]] to i8 7491 // CHECK9-NEXT: store i8 [[CONV81]], i8* [[Y]], align 8, !llvm.access.group !15 7492 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE82:%.*]] 7493 // CHECK9: omp.body.continue82: 7494 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC83:%.*]] 7495 // CHECK9: omp.inner.for.inc83: 7496 // CHECK9-NEXT: [[TMP45:%.*]] = load i32, i32* [[DOTOMP_IV57]], align 4, !llvm.access.group !15 7497 // CHECK9-NEXT: [[ADD84:%.*]] = add nsw i32 [[TMP45]], 1 7498 // CHECK9-NEXT: store i32 [[ADD84]], i32* [[DOTOMP_IV57]], align 4, !llvm.access.group !15 7499 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND59]], !llvm.loop [[LOOP16:![0-9]+]] 7500 // CHECK9: omp.inner.for.end85: 7501 // CHECK9-NEXT: store i32 10, i32* [[I58]], align 4 7502 // CHECK9-NEXT: [[TMP46:%.*]] = load i32, i32* [[A]], align 4 7503 // CHECK9-NEXT: [[TMP47:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 7504 // CHECK9-NEXT: call void @llvm.stackrestore(i8* [[TMP47]]) 7505 // CHECK9-NEXT: ret i32 [[TMP46]] 7506 // 7507 // 7508 // CHECK9-LABEL: define {{[^@]+}}@_Z3bari 7509 // CHECK9-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { 7510 // CHECK9-NEXT: entry: 7511 // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 7512 // CHECK9-NEXT: [[A:%.*]] = alloca i32, align 4 7513 // CHECK9-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 7514 // CHECK9-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 7515 // CHECK9-NEXT: store i32 0, i32* [[A]], align 4 7516 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 7517 // CHECK9-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]]) 7518 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 7519 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 7520 // CHECK9-NEXT: store i32 [[ADD]], i32* [[A]], align 4 7521 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 7522 // CHECK9-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP2]]) 7523 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 7524 // CHECK9-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 7525 // CHECK9-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 7526 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 7527 // CHECK9-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]]) 7528 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 7529 // CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 7530 // CHECK9-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 7531 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 7532 // CHECK9-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]]) 7533 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 7534 // CHECK9-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] 7535 // CHECK9-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 7536 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 7537 // CHECK9-NEXT: ret i32 [[TMP8]] 7538 // 7539 // 7540 // CHECK9-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 7541 // CHECK9-SAME: (%struct.S1* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { 7542 // CHECK9-NEXT: entry: 7543 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 7544 // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 7545 // CHECK9-NEXT: [[B:%.*]] = alloca i32, align 4 7546 // CHECK9-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 7547 // CHECK9-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 7548 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 7549 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 7550 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 7551 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 7552 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 7553 // CHECK9-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 7554 // CHECK9-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 7555 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 7556 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 7557 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 7558 // CHECK9-NEXT: store i32 [[ADD]], i32* [[B]], align 4 7559 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 7560 // CHECK9-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 7561 // CHECK9-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() 7562 // CHECK9-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 7563 // CHECK9-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] 7564 // CHECK9-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 7565 // CHECK9-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 7566 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 7567 // CHECK9-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 7568 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 7569 // CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 7570 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 7571 // CHECK9: omp.inner.for.cond: 7572 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 7573 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !18 7574 // CHECK9-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] 7575 // CHECK9-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 7576 // CHECK9: omp.inner.for.body: 7577 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 7578 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 7579 // CHECK9-NEXT: [[ADD2:%.*]] = add nsw i32 0, [[MUL]] 7580 // CHECK9-NEXT: store i32 [[ADD2]], i32* [[I]], align 4, !llvm.access.group !18 7581 // CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[B]], align 4, !llvm.access.group !18 7582 // CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP9]] to double 7583 // CHECK9-NEXT: [[ADD3:%.*]] = fadd double [[CONV]], 1.500000e+00 7584 // CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 7585 // CHECK9-NEXT: store double [[ADD3]], double* [[A]], align 8, !llvm.access.group !18 7586 // CHECK9-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 7587 // CHECK9-NEXT: [[TMP10:%.*]] = load double, double* [[A4]], align 8, !llvm.access.group !18 7588 // CHECK9-NEXT: [[INC:%.*]] = fadd double [[TMP10]], 1.000000e+00 7589 // CHECK9-NEXT: store double [[INC]], double* [[A4]], align 8, !llvm.access.group !18 7590 // CHECK9-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 7591 // CHECK9-NEXT: [[TMP11:%.*]] = mul nsw i64 1, [[TMP2]] 7592 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP11]] 7593 // CHECK9-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 7594 // CHECK9-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2, !llvm.access.group !18 7595 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 7596 // CHECK9: omp.body.continue: 7597 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 7598 // CHECK9: omp.inner.for.inc: 7599 // CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 7600 // CHECK9-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP12]], 1 7601 // CHECK9-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 7602 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] 7603 // CHECK9: omp.inner.for.end: 7604 // CHECK9-NEXT: store i32 10, i32* [[I]], align 4 7605 // CHECK9-NEXT: [[TMP13:%.*]] = mul nsw i64 1, [[TMP2]] 7606 // CHECK9-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP13]] 7607 // CHECK9-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX8]], i64 1 7608 // CHECK9-NEXT: [[TMP14:%.*]] = load i16, i16* [[ARRAYIDX9]], align 2 7609 // CHECK9-NEXT: [[CONV10:%.*]] = sext i16 [[TMP14]] to i32 7610 // CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[B]], align 4 7611 // CHECK9-NEXT: [[ADD11:%.*]] = add nsw i32 [[CONV10]], [[TMP15]] 7612 // CHECK9-NEXT: [[TMP16:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 7613 // CHECK9-NEXT: call void @llvm.stackrestore(i8* [[TMP16]]) 7614 // CHECK9-NEXT: ret i32 [[ADD11]] 7615 // 7616 // 7617 // CHECK9-LABEL: define {{[^@]+}}@_ZL7fstatici 7618 // CHECK9-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { 7619 // CHECK9-NEXT: entry: 7620 // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 7621 // CHECK9-NEXT: [[A:%.*]] = alloca i32, align 4 7622 // CHECK9-NEXT: [[AA:%.*]] = alloca i16, align 2 7623 // CHECK9-NEXT: [[AAA:%.*]] = alloca i8, align 1 7624 // CHECK9-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 7625 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 7626 // CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 7627 // CHECK9-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 7628 // CHECK9-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 7629 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 7630 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 7631 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 7632 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 7633 // CHECK9-NEXT: [[I5:%.*]] = alloca i32, align 4 7634 // CHECK9-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 7635 // CHECK9-NEXT: store i32 0, i32* [[A]], align 4 7636 // CHECK9-NEXT: store i16 0, i16* [[AA]], align 2 7637 // CHECK9-NEXT: store i8 0, i8* [[AAA]], align 1 7638 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 7639 // CHECK9-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 7640 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 7641 // CHECK9-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_1]], align 4 7642 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 7643 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 7644 // CHECK9-NEXT: [[SUB:%.*]] = sub i32 [[TMP2]], [[TMP3]] 7645 // CHECK9-NEXT: [[SUB3:%.*]] = sub i32 [[SUB]], 1 7646 // CHECK9-NEXT: [[ADD:%.*]] = add i32 [[SUB3]], 1 7647 // CHECK9-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 7648 // CHECK9-NEXT: [[SUB4:%.*]] = sub i32 [[DIV]], 1 7649 // CHECK9-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_2]], align 4 7650 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 7651 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 7652 // CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_UB]], align 4 7653 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 7654 // CHECK9-NEXT: store i32 [[TMP5]], i32* [[I]], align 4 7655 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 7656 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 7657 // CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]] 7658 // CHECK9-NEXT: br i1 [[CMP]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END:%.*]] 7659 // CHECK9: simd.if.then: 7660 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 7661 // CHECK9-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 7662 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 7663 // CHECK9: omp.inner.for.cond: 7664 // CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 7665 // CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !21 7666 // CHECK9-NEXT: [[ADD6:%.*]] = add i32 [[TMP10]], 1 7667 // CHECK9-NEXT: [[CMP7:%.*]] = icmp ult i32 [[TMP9]], [[ADD6]] 7668 // CHECK9-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 7669 // CHECK9: omp.inner.for.body: 7670 // CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group !21 7671 // CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 7672 // CHECK9-NEXT: [[MUL:%.*]] = mul i32 [[TMP12]], 1 7673 // CHECK9-NEXT: [[ADD8:%.*]] = add i32 [[TMP11]], [[MUL]] 7674 // CHECK9-NEXT: store i32 [[ADD8]], i32* [[I5]], align 4, !llvm.access.group !21 7675 // CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !21 7676 // CHECK9-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP13]], 1 7677 // CHECK9-NEXT: store i32 [[ADD9]], i32* [[A]], align 4, !llvm.access.group !21 7678 // CHECK9-NEXT: [[TMP14:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !21 7679 // CHECK9-NEXT: [[CONV:%.*]] = sext i16 [[TMP14]] to i32 7680 // CHECK9-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV]], 1 7681 // CHECK9-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD10]] to i16 7682 // CHECK9-NEXT: store i16 [[CONV11]], i16* [[AA]], align 2, !llvm.access.group !21 7683 // CHECK9-NEXT: [[TMP15:%.*]] = load i8, i8* [[AAA]], align 1, !llvm.access.group !21 7684 // CHECK9-NEXT: [[CONV12:%.*]] = sext i8 [[TMP15]] to i32 7685 // CHECK9-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1 7686 // CHECK9-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i8 7687 // CHECK9-NEXT: store i8 [[CONV14]], i8* [[AAA]], align 1, !llvm.access.group !21 7688 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 7689 // CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !21 7690 // CHECK9-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP16]], 1 7691 // CHECK9-NEXT: store i32 [[ADD15]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !21 7692 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 7693 // CHECK9: omp.body.continue: 7694 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 7695 // CHECK9: omp.inner.for.inc: 7696 // CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 7697 // CHECK9-NEXT: [[ADD16:%.*]] = add i32 [[TMP17]], 1 7698 // CHECK9-NEXT: store i32 [[ADD16]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 7699 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]] 7700 // CHECK9: omp.inner.for.end: 7701 // CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 7702 // CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 7703 // CHECK9-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 7704 // CHECK9-NEXT: [[SUB17:%.*]] = sub i32 [[TMP19]], [[TMP20]] 7705 // CHECK9-NEXT: [[SUB18:%.*]] = sub i32 [[SUB17]], 1 7706 // CHECK9-NEXT: [[ADD19:%.*]] = add i32 [[SUB18]], 1 7707 // CHECK9-NEXT: [[DIV20:%.*]] = udiv i32 [[ADD19]], 1 7708 // CHECK9-NEXT: [[MUL21:%.*]] = mul i32 [[DIV20]], 1 7709 // CHECK9-NEXT: [[ADD22:%.*]] = add i32 [[TMP18]], [[MUL21]] 7710 // CHECK9-NEXT: store i32 [[ADD22]], i32* [[I5]], align 4 7711 // CHECK9-NEXT: br label [[SIMD_IF_END]] 7712 // CHECK9: simd.if.end: 7713 // CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[A]], align 4 7714 // CHECK9-NEXT: ret i32 [[TMP21]] 7715 // 7716 // 7717 // CHECK9-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 7718 // CHECK9-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat { 7719 // CHECK9-NEXT: entry: 7720 // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 7721 // CHECK9-NEXT: [[A:%.*]] = alloca i32, align 4 7722 // CHECK9-NEXT: [[AA:%.*]] = alloca i16, align 2 7723 // CHECK9-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 7724 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 7725 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 7726 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 7727 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 7728 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 7729 // CHECK9-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 7730 // CHECK9-NEXT: store i32 0, i32* [[A]], align 4 7731 // CHECK9-NEXT: store i16 0, i16* [[AA]], align 2 7732 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 7733 // CHECK9-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 7734 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 7735 // CHECK9-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 7736 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 7737 // CHECK9: omp.inner.for.cond: 7738 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 7739 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !24 7740 // CHECK9-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] 7741 // CHECK9-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 7742 // CHECK9: omp.inner.for.body: 7743 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 7744 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 7745 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 7746 // CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !24 7747 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !24 7748 // CHECK9-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1 7749 // CHECK9-NEXT: store i32 [[ADD1]], i32* [[A]], align 4, !llvm.access.group !24 7750 // CHECK9-NEXT: [[TMP5:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !24 7751 // CHECK9-NEXT: [[CONV:%.*]] = sext i16 [[TMP5]] to i32 7752 // CHECK9-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 1 7753 // CHECK9-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 7754 // CHECK9-NEXT: store i16 [[CONV3]], i16* [[AA]], align 2, !llvm.access.group !24 7755 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 7756 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !24 7757 // CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP6]], 1 7758 // CHECK9-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !24 7759 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 7760 // CHECK9: omp.body.continue: 7761 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 7762 // CHECK9: omp.inner.for.inc: 7763 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 7764 // CHECK9-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP7]], 1 7765 // CHECK9-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 7766 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]] 7767 // CHECK9: omp.inner.for.end: 7768 // CHECK9-NEXT: store i32 10, i32* [[I]], align 4 7769 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 7770 // CHECK9-NEXT: ret i32 [[TMP8]] 7771 // 7772 // 7773 // CHECK11-LABEL: define {{[^@]+}}@_Z3fooi 7774 // CHECK11-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0:[0-9]+]] { 7775 // CHECK11-NEXT: entry: 7776 // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 7777 // CHECK11-NEXT: [[A:%.*]] = alloca i32, align 4 7778 // CHECK11-NEXT: [[AA:%.*]] = alloca i16, align 2 7779 // CHECK11-NEXT: [[B:%.*]] = alloca [10 x float], align 4 7780 // CHECK11-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 7781 // CHECK11-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 7782 // CHECK11-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 7783 // CHECK11-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 7784 // CHECK11-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 7785 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 7786 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 7787 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 7788 // CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 7789 // CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 7790 // CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 7791 // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 7792 // CHECK11-NEXT: [[_TMP4:%.*]] = alloca i32, align 4 7793 // CHECK11-NEXT: [[DOTOMP_LB5:%.*]] = alloca i32, align 4 7794 // CHECK11-NEXT: [[DOTOMP_UB6:%.*]] = alloca i32, align 4 7795 // CHECK11-NEXT: [[DOTOMP_IV7:%.*]] = alloca i32, align 4 7796 // CHECK11-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4 7797 // CHECK11-NEXT: [[A8:%.*]] = alloca i32, align 4 7798 // CHECK11-NEXT: [[A9:%.*]] = alloca i32, align 4 7799 // CHECK11-NEXT: [[_TMP20:%.*]] = alloca i32, align 4 7800 // CHECK11-NEXT: [[DOTOMP_LB21:%.*]] = alloca i32, align 4 7801 // CHECK11-NEXT: [[DOTOMP_UB22:%.*]] = alloca i32, align 4 7802 // CHECK11-NEXT: [[DOTOMP_IV23:%.*]] = alloca i32, align 4 7803 // CHECK11-NEXT: [[I24:%.*]] = alloca i32, align 4 7804 // CHECK11-NEXT: [[_TMP36:%.*]] = alloca i32, align 4 7805 // CHECK11-NEXT: [[DOTOMP_LB37:%.*]] = alloca i32, align 4 7806 // CHECK11-NEXT: [[DOTOMP_UB38:%.*]] = alloca i32, align 4 7807 // CHECK11-NEXT: [[DOTOMP_IV39:%.*]] = alloca i32, align 4 7808 // CHECK11-NEXT: [[I40:%.*]] = alloca i32, align 4 7809 // CHECK11-NEXT: [[_TMP54:%.*]] = alloca i32, align 4 7810 // CHECK11-NEXT: [[DOTOMP_LB55:%.*]] = alloca i32, align 4 7811 // CHECK11-NEXT: [[DOTOMP_UB56:%.*]] = alloca i32, align 4 7812 // CHECK11-NEXT: [[DOTOMP_IV57:%.*]] = alloca i32, align 4 7813 // CHECK11-NEXT: [[I58:%.*]] = alloca i32, align 4 7814 // CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 7815 // CHECK11-NEXT: store i32 0, i32* [[A]], align 4 7816 // CHECK11-NEXT: store i16 0, i16* [[AA]], align 2 7817 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 7818 // CHECK11-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() 7819 // CHECK11-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 7820 // CHECK11-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4 7821 // CHECK11-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 7822 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 7823 // CHECK11-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]] 7824 // CHECK11-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8 7825 // CHECK11-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4 7826 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 7827 // CHECK11-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 7828 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 7829 // CHECK11-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_2]], align 4 7830 // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 7831 // CHECK11-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 7832 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 7833 // CHECK11-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 7834 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 7835 // CHECK11: omp.inner.for.cond: 7836 // CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 7837 // CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !3 7838 // CHECK11-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] 7839 // CHECK11-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 7840 // CHECK11: omp.inner.for.body: 7841 // CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 7842 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 7843 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 7844 // CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !3 7845 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 7846 // CHECK11: omp.body.continue: 7847 // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 7848 // CHECK11: omp.inner.for.inc: 7849 // CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 7850 // CHECK11-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 7851 // CHECK11-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 7852 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] 7853 // CHECK11: omp.inner.for.end: 7854 // CHECK11-NEXT: store i32 10, i32* [[I]], align 4 7855 // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB5]], align 4 7856 // CHECK11-NEXT: store i32 9, i32* [[DOTOMP_UB6]], align 4 7857 // CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_LB5]], align 4 7858 // CHECK11-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV7]], align 4 7859 // CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[A]], align 4 7860 // CHECK11-NEXT: store i32 [[TMP12]], i32* [[DOTLINEAR_START]], align 4 7861 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND10:%.*]] 7862 // CHECK11: omp.inner.for.cond10: 7863 // CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV7]], align 4 7864 // CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB6]], align 4 7865 // CHECK11-NEXT: [[CMP11:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] 7866 // CHECK11-NEXT: br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY12:%.*]], label [[OMP_INNER_FOR_END19:%.*]] 7867 // CHECK11: omp.inner.for.body12: 7868 // CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV7]], align 4 7869 // CHECK11-NEXT: [[MUL13:%.*]] = mul nsw i32 [[TMP15]], 1 7870 // CHECK11-NEXT: [[ADD14:%.*]] = add nsw i32 0, [[MUL13]] 7871 // CHECK11-NEXT: store i32 [[ADD14]], i32* [[A8]], align 4 7872 // CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[A8]], align 4 7873 // CHECK11-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP16]], 1 7874 // CHECK11-NEXT: store i32 [[ADD15]], i32* [[A8]], align 4 7875 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE16:%.*]] 7876 // CHECK11: omp.body.continue16: 7877 // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC17:%.*]] 7878 // CHECK11: omp.inner.for.inc17: 7879 // CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV7]], align 4 7880 // CHECK11-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP17]], 1 7881 // CHECK11-NEXT: store i32 [[ADD18]], i32* [[DOTOMP_IV7]], align 4 7882 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND10]], !llvm.loop [[LOOP8:![0-9]+]] 7883 // CHECK11: omp.inner.for.end19: 7884 // CHECK11-NEXT: store i32 10, i32* [[A]], align 4 7885 // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB21]], align 4 7886 // CHECK11-NEXT: store i32 9, i32* [[DOTOMP_UB22]], align 4 7887 // CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_LB21]], align 4 7888 // CHECK11-NEXT: store i32 [[TMP18]], i32* [[DOTOMP_IV23]], align 4 7889 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND25:%.*]] 7890 // CHECK11: omp.inner.for.cond25: 7891 // CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV23]], align 4, !llvm.access.group !10 7892 // CHECK11-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_UB22]], align 4, !llvm.access.group !10 7893 // CHECK11-NEXT: [[CMP26:%.*]] = icmp sle i32 [[TMP19]], [[TMP20]] 7894 // CHECK11-NEXT: br i1 [[CMP26]], label [[OMP_INNER_FOR_BODY27:%.*]], label [[OMP_INNER_FOR_END35:%.*]] 7895 // CHECK11: omp.inner.for.body27: 7896 // CHECK11-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV23]], align 4, !llvm.access.group !10 7897 // CHECK11-NEXT: [[MUL28:%.*]] = mul nsw i32 [[TMP21]], 1 7898 // CHECK11-NEXT: [[ADD29:%.*]] = add nsw i32 0, [[MUL28]] 7899 // CHECK11-NEXT: store i32 [[ADD29]], i32* [[I24]], align 4, !llvm.access.group !10 7900 // CHECK11-NEXT: [[TMP22:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !10 7901 // CHECK11-NEXT: [[CONV:%.*]] = sext i16 [[TMP22]] to i32 7902 // CHECK11-NEXT: [[ADD30:%.*]] = add nsw i32 [[CONV]], 1 7903 // CHECK11-NEXT: [[CONV31:%.*]] = trunc i32 [[ADD30]] to i16 7904 // CHECK11-NEXT: store i16 [[CONV31]], i16* [[AA]], align 2, !llvm.access.group !10 7905 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE32:%.*]] 7906 // CHECK11: omp.body.continue32: 7907 // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC33:%.*]] 7908 // CHECK11: omp.inner.for.inc33: 7909 // CHECK11-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV23]], align 4, !llvm.access.group !10 7910 // CHECK11-NEXT: [[ADD34:%.*]] = add nsw i32 [[TMP23]], 1 7911 // CHECK11-NEXT: store i32 [[ADD34]], i32* [[DOTOMP_IV23]], align 4, !llvm.access.group !10 7912 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND25]], !llvm.loop [[LOOP11:![0-9]+]] 7913 // CHECK11: omp.inner.for.end35: 7914 // CHECK11-NEXT: store i32 10, i32* [[I24]], align 4 7915 // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB37]], align 4 7916 // CHECK11-NEXT: store i32 9, i32* [[DOTOMP_UB38]], align 4 7917 // CHECK11-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_LB37]], align 4 7918 // CHECK11-NEXT: store i32 [[TMP24]], i32* [[DOTOMP_IV39]], align 4 7919 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND41:%.*]] 7920 // CHECK11: omp.inner.for.cond41: 7921 // CHECK11-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IV39]], align 4, !llvm.access.group !13 7922 // CHECK11-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_UB38]], align 4, !llvm.access.group !13 7923 // CHECK11-NEXT: [[CMP42:%.*]] = icmp sle i32 [[TMP25]], [[TMP26]] 7924 // CHECK11-NEXT: br i1 [[CMP42]], label [[OMP_INNER_FOR_BODY43:%.*]], label [[OMP_INNER_FOR_END53:%.*]] 7925 // CHECK11: omp.inner.for.body43: 7926 // CHECK11-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV39]], align 4, !llvm.access.group !13 7927 // CHECK11-NEXT: [[MUL44:%.*]] = mul nsw i32 [[TMP27]], 1 7928 // CHECK11-NEXT: [[ADD45:%.*]] = add nsw i32 0, [[MUL44]] 7929 // CHECK11-NEXT: store i32 [[ADD45]], i32* [[I40]], align 4, !llvm.access.group !13 7930 // CHECK11-NEXT: [[TMP28:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !13 7931 // CHECK11-NEXT: [[ADD46:%.*]] = add nsw i32 [[TMP28]], 1 7932 // CHECK11-NEXT: store i32 [[ADD46]], i32* [[A]], align 4, !llvm.access.group !13 7933 // CHECK11-NEXT: [[TMP29:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !13 7934 // CHECK11-NEXT: [[CONV47:%.*]] = sext i16 [[TMP29]] to i32 7935 // CHECK11-NEXT: [[ADD48:%.*]] = add nsw i32 [[CONV47]], 1 7936 // CHECK11-NEXT: [[CONV49:%.*]] = trunc i32 [[ADD48]] to i16 7937 // CHECK11-NEXT: store i16 [[CONV49]], i16* [[AA]], align 2, !llvm.access.group !13 7938 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE50:%.*]] 7939 // CHECK11: omp.body.continue50: 7940 // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC51:%.*]] 7941 // CHECK11: omp.inner.for.inc51: 7942 // CHECK11-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_IV39]], align 4, !llvm.access.group !13 7943 // CHECK11-NEXT: [[ADD52:%.*]] = add nsw i32 [[TMP30]], 1 7944 // CHECK11-NEXT: store i32 [[ADD52]], i32* [[DOTOMP_IV39]], align 4, !llvm.access.group !13 7945 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND41]], !llvm.loop [[LOOP14:![0-9]+]] 7946 // CHECK11: omp.inner.for.end53: 7947 // CHECK11-NEXT: store i32 10, i32* [[I40]], align 4 7948 // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB55]], align 4 7949 // CHECK11-NEXT: store i32 9, i32* [[DOTOMP_UB56]], align 4 7950 // CHECK11-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_LB55]], align 4 7951 // CHECK11-NEXT: store i32 [[TMP31]], i32* [[DOTOMP_IV57]], align 4 7952 // CHECK11-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 0 7953 // CHECK11-NEXT: call void @llvm.assume(i1 true) [ "align"(float* [[ARRAYDECAY]], i32 16) ] 7954 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND59:%.*]] 7955 // CHECK11: omp.inner.for.cond59: 7956 // CHECK11-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTOMP_IV57]], align 4, !llvm.access.group !16 7957 // CHECK11-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTOMP_UB56]], align 4, !llvm.access.group !16 7958 // CHECK11-NEXT: [[CMP60:%.*]] = icmp sle i32 [[TMP32]], [[TMP33]] 7959 // CHECK11-NEXT: br i1 [[CMP60]], label [[OMP_INNER_FOR_BODY61:%.*]], label [[OMP_INNER_FOR_END85:%.*]] 7960 // CHECK11: omp.inner.for.body61: 7961 // CHECK11-NEXT: [[TMP34:%.*]] = load i32, i32* [[DOTOMP_IV57]], align 4, !llvm.access.group !16 7962 // CHECK11-NEXT: [[MUL62:%.*]] = mul nsw i32 [[TMP34]], 1 7963 // CHECK11-NEXT: [[ADD63:%.*]] = add nsw i32 0, [[MUL62]] 7964 // CHECK11-NEXT: store i32 [[ADD63]], i32* [[I58]], align 4, !llvm.access.group !16 7965 // CHECK11-NEXT: [[TMP35:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !16 7966 // CHECK11-NEXT: [[ADD64:%.*]] = add nsw i32 [[TMP35]], 1 7967 // CHECK11-NEXT: store i32 [[ADD64]], i32* [[A]], align 4, !llvm.access.group !16 7968 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2 7969 // CHECK11-NEXT: [[TMP36:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !16 7970 // CHECK11-NEXT: [[CONV65:%.*]] = fpext float [[TMP36]] to double 7971 // CHECK11-NEXT: [[ADD66:%.*]] = fadd double [[CONV65]], 1.000000e+00 7972 // CHECK11-NEXT: [[CONV67:%.*]] = fptrunc double [[ADD66]] to float 7973 // CHECK11-NEXT: store float [[CONV67]], float* [[ARRAYIDX]], align 4, !llvm.access.group !16 7974 // CHECK11-NEXT: [[ARRAYIDX68:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3 7975 // CHECK11-NEXT: [[TMP37:%.*]] = load float, float* [[ARRAYIDX68]], align 4, !llvm.access.group !16 7976 // CHECK11-NEXT: [[CONV69:%.*]] = fpext float [[TMP37]] to double 7977 // CHECK11-NEXT: [[ADD70:%.*]] = fadd double [[CONV69]], 1.000000e+00 7978 // CHECK11-NEXT: [[CONV71:%.*]] = fptrunc double [[ADD70]] to float 7979 // CHECK11-NEXT: store float [[CONV71]], float* [[ARRAYIDX68]], align 4, !llvm.access.group !16 7980 // CHECK11-NEXT: [[ARRAYIDX72:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1 7981 // CHECK11-NEXT: [[ARRAYIDX73:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX72]], i32 0, i32 2 7982 // CHECK11-NEXT: [[TMP38:%.*]] = load double, double* [[ARRAYIDX73]], align 8, !llvm.access.group !16 7983 // CHECK11-NEXT: [[ADD74:%.*]] = fadd double [[TMP38]], 1.000000e+00 7984 // CHECK11-NEXT: store double [[ADD74]], double* [[ARRAYIDX73]], align 8, !llvm.access.group !16 7985 // CHECK11-NEXT: [[TMP39:%.*]] = mul nsw i32 1, [[TMP2]] 7986 // CHECK11-NEXT: [[ARRAYIDX75:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP39]] 7987 // CHECK11-NEXT: [[ARRAYIDX76:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX75]], i32 3 7988 // CHECK11-NEXT: [[TMP40:%.*]] = load double, double* [[ARRAYIDX76]], align 8, !llvm.access.group !16 7989 // CHECK11-NEXT: [[ADD77:%.*]] = fadd double [[TMP40]], 1.000000e+00 7990 // CHECK11-NEXT: store double [[ADD77]], double* [[ARRAYIDX76]], align 8, !llvm.access.group !16 7991 // CHECK11-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 7992 // CHECK11-NEXT: [[TMP41:%.*]] = load i64, i64* [[X]], align 4, !llvm.access.group !16 7993 // CHECK11-NEXT: [[ADD78:%.*]] = add nsw i64 [[TMP41]], 1 7994 // CHECK11-NEXT: store i64 [[ADD78]], i64* [[X]], align 4, !llvm.access.group !16 7995 // CHECK11-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 7996 // CHECK11-NEXT: [[TMP42:%.*]] = load i8, i8* [[Y]], align 4, !llvm.access.group !16 7997 // CHECK11-NEXT: [[CONV79:%.*]] = sext i8 [[TMP42]] to i32 7998 // CHECK11-NEXT: [[ADD80:%.*]] = add nsw i32 [[CONV79]], 1 7999 // CHECK11-NEXT: [[CONV81:%.*]] = trunc i32 [[ADD80]] to i8 8000 // CHECK11-NEXT: store i8 [[CONV81]], i8* [[Y]], align 4, !llvm.access.group !16 8001 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE82:%.*]] 8002 // CHECK11: omp.body.continue82: 8003 // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC83:%.*]] 8004 // CHECK11: omp.inner.for.inc83: 8005 // CHECK11-NEXT: [[TMP43:%.*]] = load i32, i32* [[DOTOMP_IV57]], align 4, !llvm.access.group !16 8006 // CHECK11-NEXT: [[ADD84:%.*]] = add nsw i32 [[TMP43]], 1 8007 // CHECK11-NEXT: store i32 [[ADD84]], i32* [[DOTOMP_IV57]], align 4, !llvm.access.group !16 8008 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND59]], !llvm.loop [[LOOP17:![0-9]+]] 8009 // CHECK11: omp.inner.for.end85: 8010 // CHECK11-NEXT: store i32 10, i32* [[I58]], align 4 8011 // CHECK11-NEXT: [[TMP44:%.*]] = load i32, i32* [[A]], align 4 8012 // CHECK11-NEXT: [[TMP45:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 8013 // CHECK11-NEXT: call void @llvm.stackrestore(i8* [[TMP45]]) 8014 // CHECK11-NEXT: ret i32 [[TMP44]] 8015 // 8016 // 8017 // CHECK11-LABEL: define {{[^@]+}}@_Z3bari 8018 // CHECK11-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { 8019 // CHECK11-NEXT: entry: 8020 // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 8021 // CHECK11-NEXT: [[A:%.*]] = alloca i32, align 4 8022 // CHECK11-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 8023 // CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 8024 // CHECK11-NEXT: store i32 0, i32* [[A]], align 4 8025 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 8026 // CHECK11-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]]) 8027 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 8028 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 8029 // CHECK11-NEXT: store i32 [[ADD]], i32* [[A]], align 4 8030 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 8031 // CHECK11-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP2]]) 8032 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 8033 // CHECK11-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 8034 // CHECK11-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 8035 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 8036 // CHECK11-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]]) 8037 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 8038 // CHECK11-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 8039 // CHECK11-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 8040 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 8041 // CHECK11-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]]) 8042 // CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 8043 // CHECK11-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] 8044 // CHECK11-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 8045 // CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 8046 // CHECK11-NEXT: ret i32 [[TMP8]] 8047 // 8048 // 8049 // CHECK11-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 8050 // CHECK11-SAME: (%struct.S1* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 { 8051 // CHECK11-NEXT: entry: 8052 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 8053 // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 8054 // CHECK11-NEXT: [[B:%.*]] = alloca i32, align 4 8055 // CHECK11-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 8056 // CHECK11-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 8057 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 8058 // CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 8059 // CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 8060 // CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 8061 // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 8062 // CHECK11-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 8063 // CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 8064 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 8065 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 8066 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 8067 // CHECK11-NEXT: store i32 [[ADD]], i32* [[B]], align 4 8068 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 8069 // CHECK11-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() 8070 // CHECK11-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 8071 // CHECK11-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] 8072 // CHECK11-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 8073 // CHECK11-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 8074 // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 8075 // CHECK11-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 8076 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 8077 // CHECK11-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 8078 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 8079 // CHECK11: omp.inner.for.cond: 8080 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 8081 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !19 8082 // CHECK11-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 8083 // CHECK11-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 8084 // CHECK11: omp.inner.for.body: 8085 // CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 8086 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 8087 // CHECK11-NEXT: [[ADD2:%.*]] = add nsw i32 0, [[MUL]] 8088 // CHECK11-NEXT: store i32 [[ADD2]], i32* [[I]], align 4, !llvm.access.group !19 8089 // CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[B]], align 4, !llvm.access.group !19 8090 // CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP8]] to double 8091 // CHECK11-NEXT: [[ADD3:%.*]] = fadd double [[CONV]], 1.500000e+00 8092 // CHECK11-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 8093 // CHECK11-NEXT: store double [[ADD3]], double* [[A]], align 4, !llvm.access.group !19 8094 // CHECK11-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 8095 // CHECK11-NEXT: [[TMP9:%.*]] = load double, double* [[A4]], align 4, !llvm.access.group !19 8096 // CHECK11-NEXT: [[INC:%.*]] = fadd double [[TMP9]], 1.000000e+00 8097 // CHECK11-NEXT: store double [[INC]], double* [[A4]], align 4, !llvm.access.group !19 8098 // CHECK11-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 8099 // CHECK11-NEXT: [[TMP10:%.*]] = mul nsw i32 1, [[TMP1]] 8100 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP10]] 8101 // CHECK11-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 8102 // CHECK11-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2, !llvm.access.group !19 8103 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 8104 // CHECK11: omp.body.continue: 8105 // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 8106 // CHECK11: omp.inner.for.inc: 8107 // CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 8108 // CHECK11-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1 8109 // CHECK11-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 8110 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]] 8111 // CHECK11: omp.inner.for.end: 8112 // CHECK11-NEXT: store i32 10, i32* [[I]], align 4 8113 // CHECK11-NEXT: [[TMP12:%.*]] = mul nsw i32 1, [[TMP1]] 8114 // CHECK11-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP12]] 8115 // CHECK11-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX8]], i32 1 8116 // CHECK11-NEXT: [[TMP13:%.*]] = load i16, i16* [[ARRAYIDX9]], align 2 8117 // CHECK11-NEXT: [[CONV10:%.*]] = sext i16 [[TMP13]] to i32 8118 // CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[B]], align 4 8119 // CHECK11-NEXT: [[ADD11:%.*]] = add nsw i32 [[CONV10]], [[TMP14]] 8120 // CHECK11-NEXT: [[TMP15:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 8121 // CHECK11-NEXT: call void @llvm.stackrestore(i8* [[TMP15]]) 8122 // CHECK11-NEXT: ret i32 [[ADD11]] 8123 // 8124 // 8125 // CHECK11-LABEL: define {{[^@]+}}@_ZL7fstatici 8126 // CHECK11-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { 8127 // CHECK11-NEXT: entry: 8128 // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 8129 // CHECK11-NEXT: [[A:%.*]] = alloca i32, align 4 8130 // CHECK11-NEXT: [[AA:%.*]] = alloca i16, align 2 8131 // CHECK11-NEXT: [[AAA:%.*]] = alloca i8, align 1 8132 // CHECK11-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 8133 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 8134 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 8135 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 8136 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 8137 // CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 8138 // CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 8139 // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 8140 // CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 8141 // CHECK11-NEXT: [[I5:%.*]] = alloca i32, align 4 8142 // CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 8143 // CHECK11-NEXT: store i32 0, i32* [[A]], align 4 8144 // CHECK11-NEXT: store i16 0, i16* [[AA]], align 2 8145 // CHECK11-NEXT: store i8 0, i8* [[AAA]], align 1 8146 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 8147 // CHECK11-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 8148 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 8149 // CHECK11-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_1]], align 4 8150 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 8151 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 8152 // CHECK11-NEXT: [[SUB:%.*]] = sub i32 [[TMP2]], [[TMP3]] 8153 // CHECK11-NEXT: [[SUB3:%.*]] = sub i32 [[SUB]], 1 8154 // CHECK11-NEXT: [[ADD:%.*]] = add i32 [[SUB3]], 1 8155 // CHECK11-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 8156 // CHECK11-NEXT: [[SUB4:%.*]] = sub i32 [[DIV]], 1 8157 // CHECK11-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_2]], align 4 8158 // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 8159 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 8160 // CHECK11-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_UB]], align 4 8161 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 8162 // CHECK11-NEXT: store i32 [[TMP5]], i32* [[I]], align 4 8163 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 8164 // CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 8165 // CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]] 8166 // CHECK11-NEXT: br i1 [[CMP]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END:%.*]] 8167 // CHECK11: simd.if.then: 8168 // CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 8169 // CHECK11-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 8170 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 8171 // CHECK11: omp.inner.for.cond: 8172 // CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 8173 // CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !22 8174 // CHECK11-NEXT: [[ADD6:%.*]] = add i32 [[TMP10]], 1 8175 // CHECK11-NEXT: [[CMP7:%.*]] = icmp ult i32 [[TMP9]], [[ADD6]] 8176 // CHECK11-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 8177 // CHECK11: omp.inner.for.body: 8178 // CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group !22 8179 // CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 8180 // CHECK11-NEXT: [[MUL:%.*]] = mul i32 [[TMP12]], 1 8181 // CHECK11-NEXT: [[ADD8:%.*]] = add i32 [[TMP11]], [[MUL]] 8182 // CHECK11-NEXT: store i32 [[ADD8]], i32* [[I5]], align 4, !llvm.access.group !22 8183 // CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !22 8184 // CHECK11-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP13]], 1 8185 // CHECK11-NEXT: store i32 [[ADD9]], i32* [[A]], align 4, !llvm.access.group !22 8186 // CHECK11-NEXT: [[TMP14:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !22 8187 // CHECK11-NEXT: [[CONV:%.*]] = sext i16 [[TMP14]] to i32 8188 // CHECK11-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV]], 1 8189 // CHECK11-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD10]] to i16 8190 // CHECK11-NEXT: store i16 [[CONV11]], i16* [[AA]], align 2, !llvm.access.group !22 8191 // CHECK11-NEXT: [[TMP15:%.*]] = load i8, i8* [[AAA]], align 1, !llvm.access.group !22 8192 // CHECK11-NEXT: [[CONV12:%.*]] = sext i8 [[TMP15]] to i32 8193 // CHECK11-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1 8194 // CHECK11-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i8 8195 // CHECK11-NEXT: store i8 [[CONV14]], i8* [[AAA]], align 1, !llvm.access.group !22 8196 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 8197 // CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !22 8198 // CHECK11-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP16]], 1 8199 // CHECK11-NEXT: store i32 [[ADD15]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !22 8200 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 8201 // CHECK11: omp.body.continue: 8202 // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 8203 // CHECK11: omp.inner.for.inc: 8204 // CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 8205 // CHECK11-NEXT: [[ADD16:%.*]] = add i32 [[TMP17]], 1 8206 // CHECK11-NEXT: store i32 [[ADD16]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 8207 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]] 8208 // CHECK11: omp.inner.for.end: 8209 // CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 8210 // CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 8211 // CHECK11-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 8212 // CHECK11-NEXT: [[SUB17:%.*]] = sub i32 [[TMP19]], [[TMP20]] 8213 // CHECK11-NEXT: [[SUB18:%.*]] = sub i32 [[SUB17]], 1 8214 // CHECK11-NEXT: [[ADD19:%.*]] = add i32 [[SUB18]], 1 8215 // CHECK11-NEXT: [[DIV20:%.*]] = udiv i32 [[ADD19]], 1 8216 // CHECK11-NEXT: [[MUL21:%.*]] = mul i32 [[DIV20]], 1 8217 // CHECK11-NEXT: [[ADD22:%.*]] = add i32 [[TMP18]], [[MUL21]] 8218 // CHECK11-NEXT: store i32 [[ADD22]], i32* [[I5]], align 4 8219 // CHECK11-NEXT: br label [[SIMD_IF_END]] 8220 // CHECK11: simd.if.end: 8221 // CHECK11-NEXT: [[TMP21:%.*]] = load i32, i32* [[A]], align 4 8222 // CHECK11-NEXT: ret i32 [[TMP21]] 8223 // 8224 // 8225 // CHECK11-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 8226 // CHECK11-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat { 8227 // CHECK11-NEXT: entry: 8228 // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 8229 // CHECK11-NEXT: [[A:%.*]] = alloca i32, align 4 8230 // CHECK11-NEXT: [[AA:%.*]] = alloca i16, align 2 8231 // CHECK11-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 8232 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 8233 // CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 8234 // CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 8235 // CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 8236 // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 8237 // CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 8238 // CHECK11-NEXT: store i32 0, i32* [[A]], align 4 8239 // CHECK11-NEXT: store i16 0, i16* [[AA]], align 2 8240 // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 8241 // CHECK11-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 8242 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 8243 // CHECK11-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 8244 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 8245 // CHECK11: omp.inner.for.cond: 8246 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25 8247 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !25 8248 // CHECK11-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] 8249 // CHECK11-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 8250 // CHECK11: omp.inner.for.body: 8251 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25 8252 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 8253 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 8254 // CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !25 8255 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !25 8256 // CHECK11-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1 8257 // CHECK11-NEXT: store i32 [[ADD1]], i32* [[A]], align 4, !llvm.access.group !25 8258 // CHECK11-NEXT: [[TMP5:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !25 8259 // CHECK11-NEXT: [[CONV:%.*]] = sext i16 [[TMP5]] to i32 8260 // CHECK11-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 1 8261 // CHECK11-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 8262 // CHECK11-NEXT: store i16 [[CONV3]], i16* [[AA]], align 2, !llvm.access.group !25 8263 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 8264 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !25 8265 // CHECK11-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP6]], 1 8266 // CHECK11-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !25 8267 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 8268 // CHECK11: omp.body.continue: 8269 // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 8270 // CHECK11: omp.inner.for.inc: 8271 // CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25 8272 // CHECK11-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP7]], 1 8273 // CHECK11-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25 8274 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP26:![0-9]+]] 8275 // CHECK11: omp.inner.for.end: 8276 // CHECK11-NEXT: store i32 10, i32* [[I]], align 4 8277 // CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 8278 // CHECK11-NEXT: ret i32 [[TMP8]] 8279 // 8280 // 8281 // CHECK13-LABEL: define {{[^@]+}}@_Z3fooi 8282 // CHECK13-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { 8283 // CHECK13-NEXT: entry: 8284 // CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 8285 // CHECK13-NEXT: [[A:%.*]] = alloca i32, align 4 8286 // CHECK13-NEXT: [[AA:%.*]] = alloca i16, align 2 8287 // CHECK13-NEXT: [[B:%.*]] = alloca [10 x float], align 4 8288 // CHECK13-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 8289 // CHECK13-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 8290 // CHECK13-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 8291 // CHECK13-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 8292 // CHECK13-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 8293 // CHECK13-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 8294 // CHECK13-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 8295 // CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 8296 // CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 8297 // CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 8298 // CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 8299 // CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 8300 // CHECK13-NEXT: [[_TMP4:%.*]] = alloca i32, align 4 8301 // CHECK13-NEXT: [[DOTOMP_LB5:%.*]] = alloca i32, align 4 8302 // CHECK13-NEXT: [[DOTOMP_UB6:%.*]] = alloca i32, align 4 8303 // CHECK13-NEXT: [[DOTOMP_IV7:%.*]] = alloca i32, align 4 8304 // CHECK13-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4 8305 // CHECK13-NEXT: [[A8:%.*]] = alloca i32, align 4 8306 // CHECK13-NEXT: [[A9:%.*]] = alloca i32, align 4 8307 // CHECK13-NEXT: [[_TMP20:%.*]] = alloca i32, align 4 8308 // CHECK13-NEXT: [[DOTOMP_LB21:%.*]] = alloca i32, align 4 8309 // CHECK13-NEXT: [[DOTOMP_UB22:%.*]] = alloca i32, align 4 8310 // CHECK13-NEXT: [[DOTOMP_IV23:%.*]] = alloca i32, align 4 8311 // CHECK13-NEXT: [[I24:%.*]] = alloca i32, align 4 8312 // CHECK13-NEXT: [[_TMP36:%.*]] = alloca i32, align 4 8313 // CHECK13-NEXT: [[DOTOMP_LB37:%.*]] = alloca i32, align 4 8314 // CHECK13-NEXT: [[DOTOMP_UB38:%.*]] = alloca i32, align 4 8315 // CHECK13-NEXT: [[DOTOMP_IV39:%.*]] = alloca i32, align 4 8316 // CHECK13-NEXT: [[I40:%.*]] = alloca i32, align 4 8317 // CHECK13-NEXT: [[_TMP54:%.*]] = alloca i32, align 4 8318 // CHECK13-NEXT: [[DOTOMP_LB55:%.*]] = alloca i32, align 4 8319 // CHECK13-NEXT: [[DOTOMP_UB56:%.*]] = alloca i32, align 4 8320 // CHECK13-NEXT: [[DOTOMP_IV57:%.*]] = alloca i32, align 4 8321 // CHECK13-NEXT: [[I58:%.*]] = alloca i32, align 4 8322 // CHECK13-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 8323 // CHECK13-NEXT: store i32 0, i32* [[A]], align 4 8324 // CHECK13-NEXT: store i16 0, i16* [[AA]], align 2 8325 // CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 8326 // CHECK13-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 8327 // CHECK13-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() 8328 // CHECK13-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 8329 // CHECK13-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4 8330 // CHECK13-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 8331 // CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 8332 // CHECK13-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64 8333 // CHECK13-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]] 8334 // CHECK13-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8 8335 // CHECK13-NEXT: store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8 8336 // CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 8337 // CHECK13-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_]], align 4 8338 // CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 8339 // CHECK13-NEXT: store i32 [[TMP7]], i32* [[DOTCAPTURE_EXPR_2]], align 4 8340 // CHECK13-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 8341 // CHECK13-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 8342 // CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 8343 // CHECK13-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 8344 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 8345 // CHECK13: omp.inner.for.cond: 8346 // CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 8347 // CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !2 8348 // CHECK13-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 8349 // CHECK13-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 8350 // CHECK13: omp.inner.for.body: 8351 // CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 8352 // CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 8353 // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 8354 // CHECK13-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !2 8355 // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 8356 // CHECK13: omp.body.continue: 8357 // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 8358 // CHECK13: omp.inner.for.inc: 8359 // CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 8360 // CHECK13-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 8361 // CHECK13-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 8362 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] 8363 // CHECK13: omp.inner.for.end: 8364 // CHECK13-NEXT: store i32 10, i32* [[I]], align 4 8365 // CHECK13-NEXT: store i32 0, i32* [[DOTOMP_LB5]], align 4 8366 // CHECK13-NEXT: store i32 9, i32* [[DOTOMP_UB6]], align 4 8367 // CHECK13-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB5]], align 4 8368 // CHECK13-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV7]], align 4 8369 // CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[A]], align 4 8370 // CHECK13-NEXT: store i32 [[TMP14]], i32* [[DOTLINEAR_START]], align 4 8371 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND10:%.*]] 8372 // CHECK13: omp.inner.for.cond10: 8373 // CHECK13-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV7]], align 4 8374 // CHECK13-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB6]], align 4 8375 // CHECK13-NEXT: [[CMP11:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] 8376 // CHECK13-NEXT: br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY12:%.*]], label [[OMP_INNER_FOR_END19:%.*]] 8377 // CHECK13: omp.inner.for.body12: 8378 // CHECK13-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV7]], align 4 8379 // CHECK13-NEXT: [[MUL13:%.*]] = mul nsw i32 [[TMP17]], 1 8380 // CHECK13-NEXT: [[ADD14:%.*]] = add nsw i32 0, [[MUL13]] 8381 // CHECK13-NEXT: store i32 [[ADD14]], i32* [[A8]], align 4, !nontemporal !7 8382 // CHECK13-NEXT: [[TMP18:%.*]] = load i32, i32* [[A8]], align 4, !nontemporal !7 8383 // CHECK13-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP18]], 1 8384 // CHECK13-NEXT: store i32 [[ADD15]], i32* [[A8]], align 4, !nontemporal !7 8385 // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE16:%.*]] 8386 // CHECK13: omp.body.continue16: 8387 // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC17:%.*]] 8388 // CHECK13: omp.inner.for.inc17: 8389 // CHECK13-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV7]], align 4 8390 // CHECK13-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP19]], 1 8391 // CHECK13-NEXT: store i32 [[ADD18]], i32* [[DOTOMP_IV7]], align 4 8392 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND10]], !llvm.loop [[LOOP8:![0-9]+]] 8393 // CHECK13: omp.inner.for.end19: 8394 // CHECK13-NEXT: store i32 10, i32* [[A]], align 4 8395 // CHECK13-NEXT: store i32 0, i32* [[DOTOMP_LB21]], align 4 8396 // CHECK13-NEXT: store i32 9, i32* [[DOTOMP_UB22]], align 4 8397 // CHECK13-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_LB21]], align 4 8398 // CHECK13-NEXT: store i32 [[TMP20]], i32* [[DOTOMP_IV23]], align 4 8399 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND25:%.*]] 8400 // CHECK13: omp.inner.for.cond25: 8401 // CHECK13-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV23]], align 4, !llvm.access.group !10 8402 // CHECK13-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_UB22]], align 4, !llvm.access.group !10 8403 // CHECK13-NEXT: [[CMP26:%.*]] = icmp sle i32 [[TMP21]], [[TMP22]] 8404 // CHECK13-NEXT: br i1 [[CMP26]], label [[OMP_INNER_FOR_BODY27:%.*]], label [[OMP_INNER_FOR_END35:%.*]] 8405 // CHECK13: omp.inner.for.body27: 8406 // CHECK13-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV23]], align 4, !llvm.access.group !10 8407 // CHECK13-NEXT: [[MUL28:%.*]] = mul nsw i32 [[TMP23]], 1 8408 // CHECK13-NEXT: [[ADD29:%.*]] = add nsw i32 0, [[MUL28]] 8409 // CHECK13-NEXT: store i32 [[ADD29]], i32* [[I24]], align 4, !llvm.access.group !10 8410 // CHECK13-NEXT: [[TMP24:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !10 8411 // CHECK13-NEXT: [[CONV:%.*]] = sext i16 [[TMP24]] to i32 8412 // CHECK13-NEXT: [[ADD30:%.*]] = add nsw i32 [[CONV]], 1 8413 // CHECK13-NEXT: [[CONV31:%.*]] = trunc i32 [[ADD30]] to i16 8414 // CHECK13-NEXT: store i16 [[CONV31]], i16* [[AA]], align 2, !llvm.access.group !10 8415 // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE32:%.*]] 8416 // CHECK13: omp.body.continue32: 8417 // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC33:%.*]] 8418 // CHECK13: omp.inner.for.inc33: 8419 // CHECK13-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IV23]], align 4, !llvm.access.group !10 8420 // CHECK13-NEXT: [[ADD34:%.*]] = add nsw i32 [[TMP25]], 1 8421 // CHECK13-NEXT: store i32 [[ADD34]], i32* [[DOTOMP_IV23]], align 4, !llvm.access.group !10 8422 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND25]], !llvm.loop [[LOOP11:![0-9]+]] 8423 // CHECK13: omp.inner.for.end35: 8424 // CHECK13-NEXT: store i32 10, i32* [[I24]], align 4 8425 // CHECK13-NEXT: store i32 0, i32* [[DOTOMP_LB37]], align 4 8426 // CHECK13-NEXT: store i32 9, i32* [[DOTOMP_UB38]], align 4 8427 // CHECK13-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_LB37]], align 4 8428 // CHECK13-NEXT: store i32 [[TMP26]], i32* [[DOTOMP_IV39]], align 4 8429 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND41:%.*]] 8430 // CHECK13: omp.inner.for.cond41: 8431 // CHECK13-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV39]], align 4, !llvm.access.group !13 8432 // CHECK13-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_UB38]], align 4, !llvm.access.group !13 8433 // CHECK13-NEXT: [[CMP42:%.*]] = icmp sle i32 [[TMP27]], [[TMP28]] 8434 // CHECK13-NEXT: br i1 [[CMP42]], label [[OMP_INNER_FOR_BODY43:%.*]], label [[OMP_INNER_FOR_END53:%.*]] 8435 // CHECK13: omp.inner.for.body43: 8436 // CHECK13-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_IV39]], align 4, !llvm.access.group !13 8437 // CHECK13-NEXT: [[MUL44:%.*]] = mul nsw i32 [[TMP29]], 1 8438 // CHECK13-NEXT: [[ADD45:%.*]] = add nsw i32 0, [[MUL44]] 8439 // CHECK13-NEXT: store i32 [[ADD45]], i32* [[I40]], align 4, !llvm.access.group !13 8440 // CHECK13-NEXT: [[TMP30:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !13 8441 // CHECK13-NEXT: [[ADD46:%.*]] = add nsw i32 [[TMP30]], 1 8442 // CHECK13-NEXT: store i32 [[ADD46]], i32* [[A]], align 4, !llvm.access.group !13 8443 // CHECK13-NEXT: [[TMP31:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !13 8444 // CHECK13-NEXT: [[CONV47:%.*]] = sext i16 [[TMP31]] to i32 8445 // CHECK13-NEXT: [[ADD48:%.*]] = add nsw i32 [[CONV47]], 1 8446 // CHECK13-NEXT: [[CONV49:%.*]] = trunc i32 [[ADD48]] to i16 8447 // CHECK13-NEXT: store i16 [[CONV49]], i16* [[AA]], align 2, !llvm.access.group !13 8448 // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE50:%.*]] 8449 // CHECK13: omp.body.continue50: 8450 // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC51:%.*]] 8451 // CHECK13: omp.inner.for.inc51: 8452 // CHECK13-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTOMP_IV39]], align 4, !llvm.access.group !13 8453 // CHECK13-NEXT: [[ADD52:%.*]] = add nsw i32 [[TMP32]], 1 8454 // CHECK13-NEXT: store i32 [[ADD52]], i32* [[DOTOMP_IV39]], align 4, !llvm.access.group !13 8455 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND41]], !llvm.loop [[LOOP14:![0-9]+]] 8456 // CHECK13: omp.inner.for.end53: 8457 // CHECK13-NEXT: store i32 10, i32* [[I40]], align 4 8458 // CHECK13-NEXT: store i32 0, i32* [[DOTOMP_LB55]], align 4 8459 // CHECK13-NEXT: store i32 9, i32* [[DOTOMP_UB56]], align 4 8460 // CHECK13-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTOMP_LB55]], align 4 8461 // CHECK13-NEXT: store i32 [[TMP33]], i32* [[DOTOMP_IV57]], align 4 8462 // CHECK13-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 0 8463 // CHECK13-NEXT: call void @llvm.assume(i1 true) [ "align"(float* [[ARRAYDECAY]], i64 16) ] 8464 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND59:%.*]] 8465 // CHECK13: omp.inner.for.cond59: 8466 // CHECK13-NEXT: [[TMP34:%.*]] = load i32, i32* [[DOTOMP_IV57]], align 4, !llvm.access.group !16 8467 // CHECK13-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTOMP_UB56]], align 4, !llvm.access.group !16 8468 // CHECK13-NEXT: [[CMP60:%.*]] = icmp sle i32 [[TMP34]], [[TMP35]] 8469 // CHECK13-NEXT: br i1 [[CMP60]], label [[OMP_INNER_FOR_BODY61:%.*]], label [[OMP_INNER_FOR_END85:%.*]] 8470 // CHECK13: omp.inner.for.body61: 8471 // CHECK13-NEXT: [[TMP36:%.*]] = load i32, i32* [[DOTOMP_IV57]], align 4, !llvm.access.group !16 8472 // CHECK13-NEXT: [[MUL62:%.*]] = mul nsw i32 [[TMP36]], 1 8473 // CHECK13-NEXT: [[ADD63:%.*]] = add nsw i32 0, [[MUL62]] 8474 // CHECK13-NEXT: store i32 [[ADD63]], i32* [[I58]], align 4, !llvm.access.group !16 8475 // CHECK13-NEXT: [[TMP37:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !16 8476 // CHECK13-NEXT: [[ADD64:%.*]] = add nsw i32 [[TMP37]], 1 8477 // CHECK13-NEXT: store i32 [[ADD64]], i32* [[A]], align 4, !llvm.access.group !16 8478 // CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2 8479 // CHECK13-NEXT: [[TMP38:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !16 8480 // CHECK13-NEXT: [[CONV65:%.*]] = fpext float [[TMP38]] to double 8481 // CHECK13-NEXT: [[ADD66:%.*]] = fadd double [[CONV65]], 1.000000e+00 8482 // CHECK13-NEXT: [[CONV67:%.*]] = fptrunc double [[ADD66]] to float 8483 // CHECK13-NEXT: store float [[CONV67]], float* [[ARRAYIDX]], align 4, !llvm.access.group !16 8484 // CHECK13-NEXT: [[ARRAYIDX68:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3 8485 // CHECK13-NEXT: [[TMP39:%.*]] = load float, float* [[ARRAYIDX68]], align 4, !llvm.access.group !16 8486 // CHECK13-NEXT: [[CONV69:%.*]] = fpext float [[TMP39]] to double 8487 // CHECK13-NEXT: [[ADD70:%.*]] = fadd double [[CONV69]], 1.000000e+00 8488 // CHECK13-NEXT: [[CONV71:%.*]] = fptrunc double [[ADD70]] to float 8489 // CHECK13-NEXT: store float [[CONV71]], float* [[ARRAYIDX68]], align 4, !llvm.access.group !16 8490 // CHECK13-NEXT: [[ARRAYIDX72:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1 8491 // CHECK13-NEXT: [[ARRAYIDX73:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX72]], i64 0, i64 2 8492 // CHECK13-NEXT: [[TMP40:%.*]] = load double, double* [[ARRAYIDX73]], align 8, !llvm.access.group !16 8493 // CHECK13-NEXT: [[ADD74:%.*]] = fadd double [[TMP40]], 1.000000e+00 8494 // CHECK13-NEXT: store double [[ADD74]], double* [[ARRAYIDX73]], align 8, !llvm.access.group !16 8495 // CHECK13-NEXT: [[TMP41:%.*]] = mul nsw i64 1, [[TMP4]] 8496 // CHECK13-NEXT: [[ARRAYIDX75:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP41]] 8497 // CHECK13-NEXT: [[ARRAYIDX76:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX75]], i64 3 8498 // CHECK13-NEXT: [[TMP42:%.*]] = load double, double* [[ARRAYIDX76]], align 8, !llvm.access.group !16 8499 // CHECK13-NEXT: [[ADD77:%.*]] = fadd double [[TMP42]], 1.000000e+00 8500 // CHECK13-NEXT: store double [[ADD77]], double* [[ARRAYIDX76]], align 8, !llvm.access.group !16 8501 // CHECK13-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 8502 // CHECK13-NEXT: [[TMP43:%.*]] = load i64, i64* [[X]], align 8, !llvm.access.group !16 8503 // CHECK13-NEXT: [[ADD78:%.*]] = add nsw i64 [[TMP43]], 1 8504 // CHECK13-NEXT: store i64 [[ADD78]], i64* [[X]], align 8, !llvm.access.group !16 8505 // CHECK13-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 8506 // CHECK13-NEXT: [[TMP44:%.*]] = load i8, i8* [[Y]], align 8, !llvm.access.group !16 8507 // CHECK13-NEXT: [[CONV79:%.*]] = sext i8 [[TMP44]] to i32 8508 // CHECK13-NEXT: [[ADD80:%.*]] = add nsw i32 [[CONV79]], 1 8509 // CHECK13-NEXT: [[CONV81:%.*]] = trunc i32 [[ADD80]] to i8 8510 // CHECK13-NEXT: store i8 [[CONV81]], i8* [[Y]], align 8, !llvm.access.group !16 8511 // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE82:%.*]] 8512 // CHECK13: omp.body.continue82: 8513 // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC83:%.*]] 8514 // CHECK13: omp.inner.for.inc83: 8515 // CHECK13-NEXT: [[TMP45:%.*]] = load i32, i32* [[DOTOMP_IV57]], align 4, !llvm.access.group !16 8516 // CHECK13-NEXT: [[ADD84:%.*]] = add nsw i32 [[TMP45]], 1 8517 // CHECK13-NEXT: store i32 [[ADD84]], i32* [[DOTOMP_IV57]], align 4, !llvm.access.group !16 8518 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND59]], !llvm.loop [[LOOP17:![0-9]+]] 8519 // CHECK13: omp.inner.for.end85: 8520 // CHECK13-NEXT: store i32 10, i32* [[I58]], align 4 8521 // CHECK13-NEXT: [[TMP46:%.*]] = load i32, i32* [[A]], align 4 8522 // CHECK13-NEXT: [[TMP47:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 8523 // CHECK13-NEXT: call void @llvm.stackrestore(i8* [[TMP47]]) 8524 // CHECK13-NEXT: ret i32 [[TMP46]] 8525 // 8526 // 8527 // CHECK13-LABEL: define {{[^@]+}}@_Z3bari 8528 // CHECK13-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { 8529 // CHECK13-NEXT: entry: 8530 // CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 8531 // CHECK13-NEXT: [[A:%.*]] = alloca i32, align 4 8532 // CHECK13-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 8533 // CHECK13-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 8534 // CHECK13-NEXT: store i32 0, i32* [[A]], align 4 8535 // CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 8536 // CHECK13-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]]) 8537 // CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 8538 // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 8539 // CHECK13-NEXT: store i32 [[ADD]], i32* [[A]], align 4 8540 // CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 8541 // CHECK13-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP2]]) 8542 // CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 8543 // CHECK13-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 8544 // CHECK13-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 8545 // CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 8546 // CHECK13-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]]) 8547 // CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 8548 // CHECK13-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 8549 // CHECK13-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 8550 // CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 8551 // CHECK13-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]]) 8552 // CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 8553 // CHECK13-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] 8554 // CHECK13-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 8555 // CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 8556 // CHECK13-NEXT: ret i32 [[TMP8]] 8557 // 8558 // 8559 // CHECK13-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 8560 // CHECK13-SAME: (%struct.S1* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { 8561 // CHECK13-NEXT: entry: 8562 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 8563 // CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 8564 // CHECK13-NEXT: [[B:%.*]] = alloca i32, align 4 8565 // CHECK13-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 8566 // CHECK13-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 8567 // CHECK13-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 8568 // CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 8569 // CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 8570 // CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 8571 // CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 8572 // CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 8573 // CHECK13-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 8574 // CHECK13-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 8575 // CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 8576 // CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 8577 // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 8578 // CHECK13-NEXT: store i32 [[ADD]], i32* [[B]], align 4 8579 // CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 8580 // CHECK13-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 8581 // CHECK13-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() 8582 // CHECK13-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 8583 // CHECK13-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] 8584 // CHECK13-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 8585 // CHECK13-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 8586 // CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[N_ADDR]], align 4 8587 // CHECK13-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 60 8588 // CHECK13-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8 8589 // CHECK13-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 8590 // CHECK13-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 8591 // CHECK13-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 8592 // CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 8593 // CHECK13-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 8594 // CHECK13-NEXT: [[TMP7:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 8595 // CHECK13-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP7]] to i1 8596 // CHECK13-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 8597 // CHECK13: omp_if.then: 8598 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 8599 // CHECK13: omp.inner.for.cond: 8600 // CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 8601 // CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !19 8602 // CHECK13-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] 8603 // CHECK13-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 8604 // CHECK13: omp.inner.for.body: 8605 // CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 8606 // CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 8607 // CHECK13-NEXT: [[ADD3:%.*]] = add nsw i32 0, [[MUL]] 8608 // CHECK13-NEXT: store i32 [[ADD3]], i32* [[I]], align 4, !llvm.access.group !19 8609 // CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[B]], align 4, !llvm.access.group !19 8610 // CHECK13-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP11]] to double 8611 // CHECK13-NEXT: [[ADD4:%.*]] = fadd double [[CONV]], 1.500000e+00 8612 // CHECK13-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 8613 // CHECK13-NEXT: store double [[ADD4]], double* [[A]], align 8, !llvm.access.group !19 8614 // CHECK13-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 8615 // CHECK13-NEXT: [[TMP12:%.*]] = load double, double* [[A5]], align 8, !llvm.access.group !19 8616 // CHECK13-NEXT: [[INC:%.*]] = fadd double [[TMP12]], 1.000000e+00 8617 // CHECK13-NEXT: store double [[INC]], double* [[A5]], align 8, !llvm.access.group !19 8618 // CHECK13-NEXT: [[CONV6:%.*]] = fptosi double [[INC]] to i16 8619 // CHECK13-NEXT: [[TMP13:%.*]] = mul nsw i64 1, [[TMP2]] 8620 // CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP13]] 8621 // CHECK13-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 8622 // CHECK13-NEXT: store i16 [[CONV6]], i16* [[ARRAYIDX7]], align 2, !llvm.access.group !19 8623 // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 8624 // CHECK13: omp.body.continue: 8625 // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 8626 // CHECK13: omp.inner.for.inc: 8627 // CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 8628 // CHECK13-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP14]], 1 8629 // CHECK13-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 8630 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]] 8631 // CHECK13: omp.inner.for.end: 8632 // CHECK13-NEXT: br label [[OMP_IF_END:%.*]] 8633 // CHECK13: omp_if.else: 8634 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND9:%.*]] 8635 // CHECK13: omp.inner.for.cond9: 8636 // CHECK13-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 8637 // CHECK13-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 8638 // CHECK13-NEXT: [[CMP10:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] 8639 // CHECK13-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY11:%.*]], label [[OMP_INNER_FOR_END25:%.*]] 8640 // CHECK13: omp.inner.for.body11: 8641 // CHECK13-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 8642 // CHECK13-NEXT: [[MUL12:%.*]] = mul nsw i32 [[TMP17]], 1 8643 // CHECK13-NEXT: [[ADD13:%.*]] = add nsw i32 0, [[MUL12]] 8644 // CHECK13-NEXT: store i32 [[ADD13]], i32* [[I]], align 4 8645 // CHECK13-NEXT: [[TMP18:%.*]] = load i32, i32* [[B]], align 4 8646 // CHECK13-NEXT: [[CONV14:%.*]] = sitofp i32 [[TMP18]] to double 8647 // CHECK13-NEXT: [[ADD15:%.*]] = fadd double [[CONV14]], 1.500000e+00 8648 // CHECK13-NEXT: [[A16:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 8649 // CHECK13-NEXT: store double [[ADD15]], double* [[A16]], align 8 8650 // CHECK13-NEXT: [[A17:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 8651 // CHECK13-NEXT: [[TMP19:%.*]] = load double, double* [[A17]], align 8 8652 // CHECK13-NEXT: [[INC18:%.*]] = fadd double [[TMP19]], 1.000000e+00 8653 // CHECK13-NEXT: store double [[INC18]], double* [[A17]], align 8 8654 // CHECK13-NEXT: [[CONV19:%.*]] = fptosi double [[INC18]] to i16 8655 // CHECK13-NEXT: [[TMP20:%.*]] = mul nsw i64 1, [[TMP2]] 8656 // CHECK13-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP20]] 8657 // CHECK13-NEXT: [[ARRAYIDX21:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX20]], i64 1 8658 // CHECK13-NEXT: store i16 [[CONV19]], i16* [[ARRAYIDX21]], align 2 8659 // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE22:%.*]] 8660 // CHECK13: omp.body.continue22: 8661 // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC23:%.*]] 8662 // CHECK13: omp.inner.for.inc23: 8663 // CHECK13-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 8664 // CHECK13-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP21]], 1 8665 // CHECK13-NEXT: store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4 8666 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND9]], !llvm.loop [[LOOP22:![0-9]+]] 8667 // CHECK13: omp.inner.for.end25: 8668 // CHECK13-NEXT: br label [[OMP_IF_END]] 8669 // CHECK13: omp_if.end: 8670 // CHECK13-NEXT: store i32 10, i32* [[I]], align 4 8671 // CHECK13-NEXT: [[TMP22:%.*]] = mul nsw i64 1, [[TMP2]] 8672 // CHECK13-NEXT: [[ARRAYIDX26:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP22]] 8673 // CHECK13-NEXT: [[ARRAYIDX27:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX26]], i64 1 8674 // CHECK13-NEXT: [[TMP23:%.*]] = load i16, i16* [[ARRAYIDX27]], align 2 8675 // CHECK13-NEXT: [[CONV28:%.*]] = sext i16 [[TMP23]] to i32 8676 // CHECK13-NEXT: [[TMP24:%.*]] = load i32, i32* [[B]], align 4 8677 // CHECK13-NEXT: [[ADD29:%.*]] = add nsw i32 [[CONV28]], [[TMP24]] 8678 // CHECK13-NEXT: [[TMP25:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 8679 // CHECK13-NEXT: call void @llvm.stackrestore(i8* [[TMP25]]) 8680 // CHECK13-NEXT: ret i32 [[ADD29]] 8681 // 8682 // 8683 // CHECK13-LABEL: define {{[^@]+}}@_ZL7fstatici 8684 // CHECK13-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { 8685 // CHECK13-NEXT: entry: 8686 // CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 8687 // CHECK13-NEXT: [[A:%.*]] = alloca i32, align 4 8688 // CHECK13-NEXT: [[AA:%.*]] = alloca i16, align 2 8689 // CHECK13-NEXT: [[AAA:%.*]] = alloca i8, align 1 8690 // CHECK13-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 8691 // CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 8692 // CHECK13-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 8693 // CHECK13-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 8694 // CHECK13-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 8695 // CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 8696 // CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 8697 // CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 8698 // CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 8699 // CHECK13-NEXT: [[I5:%.*]] = alloca i32, align 4 8700 // CHECK13-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 8701 // CHECK13-NEXT: store i32 0, i32* [[A]], align 4 8702 // CHECK13-NEXT: store i16 0, i16* [[AA]], align 2 8703 // CHECK13-NEXT: store i8 0, i8* [[AAA]], align 1 8704 // CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 8705 // CHECK13-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 8706 // CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 8707 // CHECK13-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_1]], align 4 8708 // CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 8709 // CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 8710 // CHECK13-NEXT: [[SUB:%.*]] = sub i32 [[TMP2]], [[TMP3]] 8711 // CHECK13-NEXT: [[SUB3:%.*]] = sub i32 [[SUB]], 1 8712 // CHECK13-NEXT: [[ADD:%.*]] = add i32 [[SUB3]], 1 8713 // CHECK13-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 8714 // CHECK13-NEXT: [[SUB4:%.*]] = sub i32 [[DIV]], 1 8715 // CHECK13-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_2]], align 4 8716 // CHECK13-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 8717 // CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 8718 // CHECK13-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_UB]], align 4 8719 // CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 8720 // CHECK13-NEXT: store i32 [[TMP5]], i32* [[I]], align 4 8721 // CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 8722 // CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 8723 // CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]] 8724 // CHECK13-NEXT: br i1 [[CMP]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END:%.*]] 8725 // CHECK13: simd.if.then: 8726 // CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 8727 // CHECK13-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 8728 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 8729 // CHECK13: omp.inner.for.cond: 8730 // CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 8731 // CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !24 8732 // CHECK13-NEXT: [[ADD6:%.*]] = add i32 [[TMP10]], 1 8733 // CHECK13-NEXT: [[CMP7:%.*]] = icmp ult i32 [[TMP9]], [[ADD6]] 8734 // CHECK13-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 8735 // CHECK13: omp.inner.for.body: 8736 // CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group !24 8737 // CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 8738 // CHECK13-NEXT: [[MUL:%.*]] = mul i32 [[TMP12]], 1 8739 // CHECK13-NEXT: [[ADD8:%.*]] = add i32 [[TMP11]], [[MUL]] 8740 // CHECK13-NEXT: store i32 [[ADD8]], i32* [[I5]], align 4, !llvm.access.group !24 8741 // CHECK13-NEXT: [[TMP13:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !24 8742 // CHECK13-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP13]], 1 8743 // CHECK13-NEXT: store i32 [[ADD9]], i32* [[A]], align 4, !llvm.access.group !24 8744 // CHECK13-NEXT: [[TMP14:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !24 8745 // CHECK13-NEXT: [[CONV:%.*]] = sext i16 [[TMP14]] to i32 8746 // CHECK13-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV]], 1 8747 // CHECK13-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD10]] to i16 8748 // CHECK13-NEXT: store i16 [[CONV11]], i16* [[AA]], align 2, !llvm.access.group !24 8749 // CHECK13-NEXT: [[TMP15:%.*]] = load i8, i8* [[AAA]], align 1, !llvm.access.group !24 8750 // CHECK13-NEXT: [[CONV12:%.*]] = sext i8 [[TMP15]] to i32 8751 // CHECK13-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1 8752 // CHECK13-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i8 8753 // CHECK13-NEXT: store i8 [[CONV14]], i8* [[AAA]], align 1, !llvm.access.group !24 8754 // CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 8755 // CHECK13-NEXT: [[TMP16:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !24 8756 // CHECK13-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP16]], 1 8757 // CHECK13-NEXT: store i32 [[ADD15]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !24 8758 // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 8759 // CHECK13: omp.body.continue: 8760 // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 8761 // CHECK13: omp.inner.for.inc: 8762 // CHECK13-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 8763 // CHECK13-NEXT: [[ADD16:%.*]] = add i32 [[TMP17]], 1 8764 // CHECK13-NEXT: store i32 [[ADD16]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 8765 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]] 8766 // CHECK13: omp.inner.for.end: 8767 // CHECK13-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 8768 // CHECK13-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 8769 // CHECK13-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 8770 // CHECK13-NEXT: [[SUB17:%.*]] = sub i32 [[TMP19]], [[TMP20]] 8771 // CHECK13-NEXT: [[SUB18:%.*]] = sub i32 [[SUB17]], 1 8772 // CHECK13-NEXT: [[ADD19:%.*]] = add i32 [[SUB18]], 1 8773 // CHECK13-NEXT: [[DIV20:%.*]] = udiv i32 [[ADD19]], 1 8774 // CHECK13-NEXT: [[MUL21:%.*]] = mul i32 [[DIV20]], 1 8775 // CHECK13-NEXT: [[ADD22:%.*]] = add i32 [[TMP18]], [[MUL21]] 8776 // CHECK13-NEXT: store i32 [[ADD22]], i32* [[I5]], align 4 8777 // CHECK13-NEXT: br label [[SIMD_IF_END]] 8778 // CHECK13: simd.if.end: 8779 // CHECK13-NEXT: [[TMP21:%.*]] = load i32, i32* [[A]], align 4 8780 // CHECK13-NEXT: ret i32 [[TMP21]] 8781 // 8782 // 8783 // CHECK13-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 8784 // CHECK13-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat { 8785 // CHECK13-NEXT: entry: 8786 // CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 8787 // CHECK13-NEXT: [[A:%.*]] = alloca i32, align 4 8788 // CHECK13-NEXT: [[AA:%.*]] = alloca i16, align 2 8789 // CHECK13-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 8790 // CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 8791 // CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 8792 // CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 8793 // CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 8794 // CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 8795 // CHECK13-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 8796 // CHECK13-NEXT: store i32 0, i32* [[A]], align 4 8797 // CHECK13-NEXT: store i16 0, i16* [[AA]], align 2 8798 // CHECK13-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 8799 // CHECK13-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 8800 // CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 8801 // CHECK13-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 8802 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 8803 // CHECK13: omp.inner.for.cond: 8804 // CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 8805 // CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !27 8806 // CHECK13-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] 8807 // CHECK13-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 8808 // CHECK13: omp.inner.for.body: 8809 // CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 8810 // CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 8811 // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 8812 // CHECK13-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !27 8813 // CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !27 8814 // CHECK13-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1 8815 // CHECK13-NEXT: store i32 [[ADD1]], i32* [[A]], align 4, !llvm.access.group !27 8816 // CHECK13-NEXT: [[TMP5:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !27 8817 // CHECK13-NEXT: [[CONV:%.*]] = sext i16 [[TMP5]] to i32 8818 // CHECK13-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 1 8819 // CHECK13-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 8820 // CHECK13-NEXT: store i16 [[CONV3]], i16* [[AA]], align 2, !llvm.access.group !27 8821 // CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 8822 // CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !27 8823 // CHECK13-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP6]], 1 8824 // CHECK13-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !27 8825 // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 8826 // CHECK13: omp.body.continue: 8827 // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 8828 // CHECK13: omp.inner.for.inc: 8829 // CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 8830 // CHECK13-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP7]], 1 8831 // CHECK13-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 8832 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]] 8833 // CHECK13: omp.inner.for.end: 8834 // CHECK13-NEXT: store i32 10, i32* [[I]], align 4 8835 // CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 8836 // CHECK13-NEXT: ret i32 [[TMP8]] 8837 // 8838 // 8839 // CHECK15-LABEL: define {{[^@]+}}@_Z3fooi 8840 // CHECK15-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0:[0-9]+]] { 8841 // CHECK15-NEXT: entry: 8842 // CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 8843 // CHECK15-NEXT: [[A:%.*]] = alloca i32, align 4 8844 // CHECK15-NEXT: [[AA:%.*]] = alloca i16, align 2 8845 // CHECK15-NEXT: [[B:%.*]] = alloca [10 x float], align 4 8846 // CHECK15-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 8847 // CHECK15-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 8848 // CHECK15-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 8849 // CHECK15-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 8850 // CHECK15-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 8851 // CHECK15-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 8852 // CHECK15-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 8853 // CHECK15-NEXT: [[TMP:%.*]] = alloca i32, align 4 8854 // CHECK15-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 8855 // CHECK15-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 8856 // CHECK15-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 8857 // CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 8858 // CHECK15-NEXT: [[_TMP4:%.*]] = alloca i32, align 4 8859 // CHECK15-NEXT: [[DOTOMP_LB5:%.*]] = alloca i32, align 4 8860 // CHECK15-NEXT: [[DOTOMP_UB6:%.*]] = alloca i32, align 4 8861 // CHECK15-NEXT: [[DOTOMP_IV7:%.*]] = alloca i32, align 4 8862 // CHECK15-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4 8863 // CHECK15-NEXT: [[A8:%.*]] = alloca i32, align 4 8864 // CHECK15-NEXT: [[A9:%.*]] = alloca i32, align 4 8865 // CHECK15-NEXT: [[_TMP20:%.*]] = alloca i32, align 4 8866 // CHECK15-NEXT: [[DOTOMP_LB21:%.*]] = alloca i32, align 4 8867 // CHECK15-NEXT: [[DOTOMP_UB22:%.*]] = alloca i32, align 4 8868 // CHECK15-NEXT: [[DOTOMP_IV23:%.*]] = alloca i32, align 4 8869 // CHECK15-NEXT: [[I24:%.*]] = alloca i32, align 4 8870 // CHECK15-NEXT: [[_TMP36:%.*]] = alloca i32, align 4 8871 // CHECK15-NEXT: [[DOTOMP_LB37:%.*]] = alloca i32, align 4 8872 // CHECK15-NEXT: [[DOTOMP_UB38:%.*]] = alloca i32, align 4 8873 // CHECK15-NEXT: [[DOTOMP_IV39:%.*]] = alloca i32, align 4 8874 // CHECK15-NEXT: [[I40:%.*]] = alloca i32, align 4 8875 // CHECK15-NEXT: [[_TMP54:%.*]] = alloca i32, align 4 8876 // CHECK15-NEXT: [[DOTOMP_LB55:%.*]] = alloca i32, align 4 8877 // CHECK15-NEXT: [[DOTOMP_UB56:%.*]] = alloca i32, align 4 8878 // CHECK15-NEXT: [[DOTOMP_IV57:%.*]] = alloca i32, align 4 8879 // CHECK15-NEXT: [[I58:%.*]] = alloca i32, align 4 8880 // CHECK15-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 8881 // CHECK15-NEXT: store i32 0, i32* [[A]], align 4 8882 // CHECK15-NEXT: store i16 0, i16* [[AA]], align 2 8883 // CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 8884 // CHECK15-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() 8885 // CHECK15-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 8886 // CHECK15-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4 8887 // CHECK15-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 8888 // CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 8889 // CHECK15-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]] 8890 // CHECK15-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8 8891 // CHECK15-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4 8892 // CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 8893 // CHECK15-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 8894 // CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 8895 // CHECK15-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_2]], align 4 8896 // CHECK15-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 8897 // CHECK15-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 8898 // CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 8899 // CHECK15-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 8900 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 8901 // CHECK15: omp.inner.for.cond: 8902 // CHECK15-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 8903 // CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !3 8904 // CHECK15-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] 8905 // CHECK15-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 8906 // CHECK15: omp.inner.for.body: 8907 // CHECK15-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 8908 // CHECK15-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 8909 // CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 8910 // CHECK15-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !3 8911 // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 8912 // CHECK15: omp.body.continue: 8913 // CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 8914 // CHECK15: omp.inner.for.inc: 8915 // CHECK15-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 8916 // CHECK15-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 8917 // CHECK15-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 8918 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] 8919 // CHECK15: omp.inner.for.end: 8920 // CHECK15-NEXT: store i32 10, i32* [[I]], align 4 8921 // CHECK15-NEXT: store i32 0, i32* [[DOTOMP_LB5]], align 4 8922 // CHECK15-NEXT: store i32 9, i32* [[DOTOMP_UB6]], align 4 8923 // CHECK15-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_LB5]], align 4 8924 // CHECK15-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV7]], align 4 8925 // CHECK15-NEXT: [[TMP12:%.*]] = load i32, i32* [[A]], align 4 8926 // CHECK15-NEXT: store i32 [[TMP12]], i32* [[DOTLINEAR_START]], align 4 8927 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND10:%.*]] 8928 // CHECK15: omp.inner.for.cond10: 8929 // CHECK15-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV7]], align 4 8930 // CHECK15-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB6]], align 4 8931 // CHECK15-NEXT: [[CMP11:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] 8932 // CHECK15-NEXT: br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY12:%.*]], label [[OMP_INNER_FOR_END19:%.*]] 8933 // CHECK15: omp.inner.for.body12: 8934 // CHECK15-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV7]], align 4 8935 // CHECK15-NEXT: [[MUL13:%.*]] = mul nsw i32 [[TMP15]], 1 8936 // CHECK15-NEXT: [[ADD14:%.*]] = add nsw i32 0, [[MUL13]] 8937 // CHECK15-NEXT: store i32 [[ADD14]], i32* [[A8]], align 4, !nontemporal !8 8938 // CHECK15-NEXT: [[TMP16:%.*]] = load i32, i32* [[A8]], align 4, !nontemporal !8 8939 // CHECK15-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP16]], 1 8940 // CHECK15-NEXT: store i32 [[ADD15]], i32* [[A8]], align 4, !nontemporal !8 8941 // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE16:%.*]] 8942 // CHECK15: omp.body.continue16: 8943 // CHECK15-NEXT: br label [[OMP_INNER_FOR_INC17:%.*]] 8944 // CHECK15: omp.inner.for.inc17: 8945 // CHECK15-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV7]], align 4 8946 // CHECK15-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP17]], 1 8947 // CHECK15-NEXT: store i32 [[ADD18]], i32* [[DOTOMP_IV7]], align 4 8948 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND10]], !llvm.loop [[LOOP9:![0-9]+]] 8949 // CHECK15: omp.inner.for.end19: 8950 // CHECK15-NEXT: store i32 10, i32* [[A]], align 4 8951 // CHECK15-NEXT: store i32 0, i32* [[DOTOMP_LB21]], align 4 8952 // CHECK15-NEXT: store i32 9, i32* [[DOTOMP_UB22]], align 4 8953 // CHECK15-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_LB21]], align 4 8954 // CHECK15-NEXT: store i32 [[TMP18]], i32* [[DOTOMP_IV23]], align 4 8955 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND25:%.*]] 8956 // CHECK15: omp.inner.for.cond25: 8957 // CHECK15-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV23]], align 4, !llvm.access.group !11 8958 // CHECK15-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_UB22]], align 4, !llvm.access.group !11 8959 // CHECK15-NEXT: [[CMP26:%.*]] = icmp sle i32 [[TMP19]], [[TMP20]] 8960 // CHECK15-NEXT: br i1 [[CMP26]], label [[OMP_INNER_FOR_BODY27:%.*]], label [[OMP_INNER_FOR_END35:%.*]] 8961 // CHECK15: omp.inner.for.body27: 8962 // CHECK15-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV23]], align 4, !llvm.access.group !11 8963 // CHECK15-NEXT: [[MUL28:%.*]] = mul nsw i32 [[TMP21]], 1 8964 // CHECK15-NEXT: [[ADD29:%.*]] = add nsw i32 0, [[MUL28]] 8965 // CHECK15-NEXT: store i32 [[ADD29]], i32* [[I24]], align 4, !llvm.access.group !11 8966 // CHECK15-NEXT: [[TMP22:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !11 8967 // CHECK15-NEXT: [[CONV:%.*]] = sext i16 [[TMP22]] to i32 8968 // CHECK15-NEXT: [[ADD30:%.*]] = add nsw i32 [[CONV]], 1 8969 // CHECK15-NEXT: [[CONV31:%.*]] = trunc i32 [[ADD30]] to i16 8970 // CHECK15-NEXT: store i16 [[CONV31]], i16* [[AA]], align 2, !llvm.access.group !11 8971 // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE32:%.*]] 8972 // CHECK15: omp.body.continue32: 8973 // CHECK15-NEXT: br label [[OMP_INNER_FOR_INC33:%.*]] 8974 // CHECK15: omp.inner.for.inc33: 8975 // CHECK15-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV23]], align 4, !llvm.access.group !11 8976 // CHECK15-NEXT: [[ADD34:%.*]] = add nsw i32 [[TMP23]], 1 8977 // CHECK15-NEXT: store i32 [[ADD34]], i32* [[DOTOMP_IV23]], align 4, !llvm.access.group !11 8978 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND25]], !llvm.loop [[LOOP12:![0-9]+]] 8979 // CHECK15: omp.inner.for.end35: 8980 // CHECK15-NEXT: store i32 10, i32* [[I24]], align 4 8981 // CHECK15-NEXT: store i32 0, i32* [[DOTOMP_LB37]], align 4 8982 // CHECK15-NEXT: store i32 9, i32* [[DOTOMP_UB38]], align 4 8983 // CHECK15-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_LB37]], align 4 8984 // CHECK15-NEXT: store i32 [[TMP24]], i32* [[DOTOMP_IV39]], align 4 8985 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND41:%.*]] 8986 // CHECK15: omp.inner.for.cond41: 8987 // CHECK15-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IV39]], align 4, !llvm.access.group !14 8988 // CHECK15-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_UB38]], align 4, !llvm.access.group !14 8989 // CHECK15-NEXT: [[CMP42:%.*]] = icmp sle i32 [[TMP25]], [[TMP26]] 8990 // CHECK15-NEXT: br i1 [[CMP42]], label [[OMP_INNER_FOR_BODY43:%.*]], label [[OMP_INNER_FOR_END53:%.*]] 8991 // CHECK15: omp.inner.for.body43: 8992 // CHECK15-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV39]], align 4, !llvm.access.group !14 8993 // CHECK15-NEXT: [[MUL44:%.*]] = mul nsw i32 [[TMP27]], 1 8994 // CHECK15-NEXT: [[ADD45:%.*]] = add nsw i32 0, [[MUL44]] 8995 // CHECK15-NEXT: store i32 [[ADD45]], i32* [[I40]], align 4, !llvm.access.group !14 8996 // CHECK15-NEXT: [[TMP28:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !14 8997 // CHECK15-NEXT: [[ADD46:%.*]] = add nsw i32 [[TMP28]], 1 8998 // CHECK15-NEXT: store i32 [[ADD46]], i32* [[A]], align 4, !llvm.access.group !14 8999 // CHECK15-NEXT: [[TMP29:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !14 9000 // CHECK15-NEXT: [[CONV47:%.*]] = sext i16 [[TMP29]] to i32 9001 // CHECK15-NEXT: [[ADD48:%.*]] = add nsw i32 [[CONV47]], 1 9002 // CHECK15-NEXT: [[CONV49:%.*]] = trunc i32 [[ADD48]] to i16 9003 // CHECK15-NEXT: store i16 [[CONV49]], i16* [[AA]], align 2, !llvm.access.group !14 9004 // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE50:%.*]] 9005 // CHECK15: omp.body.continue50: 9006 // CHECK15-NEXT: br label [[OMP_INNER_FOR_INC51:%.*]] 9007 // CHECK15: omp.inner.for.inc51: 9008 // CHECK15-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_IV39]], align 4, !llvm.access.group !14 9009 // CHECK15-NEXT: [[ADD52:%.*]] = add nsw i32 [[TMP30]], 1 9010 // CHECK15-NEXT: store i32 [[ADD52]], i32* [[DOTOMP_IV39]], align 4, !llvm.access.group !14 9011 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND41]], !llvm.loop [[LOOP15:![0-9]+]] 9012 // CHECK15: omp.inner.for.end53: 9013 // CHECK15-NEXT: store i32 10, i32* [[I40]], align 4 9014 // CHECK15-NEXT: store i32 0, i32* [[DOTOMP_LB55]], align 4 9015 // CHECK15-NEXT: store i32 9, i32* [[DOTOMP_UB56]], align 4 9016 // CHECK15-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_LB55]], align 4 9017 // CHECK15-NEXT: store i32 [[TMP31]], i32* [[DOTOMP_IV57]], align 4 9018 // CHECK15-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 0 9019 // CHECK15-NEXT: call void @llvm.assume(i1 true) [ "align"(float* [[ARRAYDECAY]], i32 16) ] 9020 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND59:%.*]] 9021 // CHECK15: omp.inner.for.cond59: 9022 // CHECK15-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTOMP_IV57]], align 4, !llvm.access.group !17 9023 // CHECK15-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTOMP_UB56]], align 4, !llvm.access.group !17 9024 // CHECK15-NEXT: [[CMP60:%.*]] = icmp sle i32 [[TMP32]], [[TMP33]] 9025 // CHECK15-NEXT: br i1 [[CMP60]], label [[OMP_INNER_FOR_BODY61:%.*]], label [[OMP_INNER_FOR_END85:%.*]] 9026 // CHECK15: omp.inner.for.body61: 9027 // CHECK15-NEXT: [[TMP34:%.*]] = load i32, i32* [[DOTOMP_IV57]], align 4, !llvm.access.group !17 9028 // CHECK15-NEXT: [[MUL62:%.*]] = mul nsw i32 [[TMP34]], 1 9029 // CHECK15-NEXT: [[ADD63:%.*]] = add nsw i32 0, [[MUL62]] 9030 // CHECK15-NEXT: store i32 [[ADD63]], i32* [[I58]], align 4, !llvm.access.group !17 9031 // CHECK15-NEXT: [[TMP35:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !17 9032 // CHECK15-NEXT: [[ADD64:%.*]] = add nsw i32 [[TMP35]], 1 9033 // CHECK15-NEXT: store i32 [[ADD64]], i32* [[A]], align 4, !llvm.access.group !17 9034 // CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2 9035 // CHECK15-NEXT: [[TMP36:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !17 9036 // CHECK15-NEXT: [[CONV65:%.*]] = fpext float [[TMP36]] to double 9037 // CHECK15-NEXT: [[ADD66:%.*]] = fadd double [[CONV65]], 1.000000e+00 9038 // CHECK15-NEXT: [[CONV67:%.*]] = fptrunc double [[ADD66]] to float 9039 // CHECK15-NEXT: store float [[CONV67]], float* [[ARRAYIDX]], align 4, !llvm.access.group !17 9040 // CHECK15-NEXT: [[ARRAYIDX68:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3 9041 // CHECK15-NEXT: [[TMP37:%.*]] = load float, float* [[ARRAYIDX68]], align 4, !llvm.access.group !17 9042 // CHECK15-NEXT: [[CONV69:%.*]] = fpext float [[TMP37]] to double 9043 // CHECK15-NEXT: [[ADD70:%.*]] = fadd double [[CONV69]], 1.000000e+00 9044 // CHECK15-NEXT: [[CONV71:%.*]] = fptrunc double [[ADD70]] to float 9045 // CHECK15-NEXT: store float [[CONV71]], float* [[ARRAYIDX68]], align 4, !llvm.access.group !17 9046 // CHECK15-NEXT: [[ARRAYIDX72:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1 9047 // CHECK15-NEXT: [[ARRAYIDX73:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX72]], i32 0, i32 2 9048 // CHECK15-NEXT: [[TMP38:%.*]] = load double, double* [[ARRAYIDX73]], align 8, !llvm.access.group !17 9049 // CHECK15-NEXT: [[ADD74:%.*]] = fadd double [[TMP38]], 1.000000e+00 9050 // CHECK15-NEXT: store double [[ADD74]], double* [[ARRAYIDX73]], align 8, !llvm.access.group !17 9051 // CHECK15-NEXT: [[TMP39:%.*]] = mul nsw i32 1, [[TMP2]] 9052 // CHECK15-NEXT: [[ARRAYIDX75:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP39]] 9053 // CHECK15-NEXT: [[ARRAYIDX76:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX75]], i32 3 9054 // CHECK15-NEXT: [[TMP40:%.*]] = load double, double* [[ARRAYIDX76]], align 8, !llvm.access.group !17 9055 // CHECK15-NEXT: [[ADD77:%.*]] = fadd double [[TMP40]], 1.000000e+00 9056 // CHECK15-NEXT: store double [[ADD77]], double* [[ARRAYIDX76]], align 8, !llvm.access.group !17 9057 // CHECK15-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 9058 // CHECK15-NEXT: [[TMP41:%.*]] = load i64, i64* [[X]], align 4, !llvm.access.group !17 9059 // CHECK15-NEXT: [[ADD78:%.*]] = add nsw i64 [[TMP41]], 1 9060 // CHECK15-NEXT: store i64 [[ADD78]], i64* [[X]], align 4, !llvm.access.group !17 9061 // CHECK15-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 9062 // CHECK15-NEXT: [[TMP42:%.*]] = load i8, i8* [[Y]], align 4, !llvm.access.group !17 9063 // CHECK15-NEXT: [[CONV79:%.*]] = sext i8 [[TMP42]] to i32 9064 // CHECK15-NEXT: [[ADD80:%.*]] = add nsw i32 [[CONV79]], 1 9065 // CHECK15-NEXT: [[CONV81:%.*]] = trunc i32 [[ADD80]] to i8 9066 // CHECK15-NEXT: store i8 [[CONV81]], i8* [[Y]], align 4, !llvm.access.group !17 9067 // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE82:%.*]] 9068 // CHECK15: omp.body.continue82: 9069 // CHECK15-NEXT: br label [[OMP_INNER_FOR_INC83:%.*]] 9070 // CHECK15: omp.inner.for.inc83: 9071 // CHECK15-NEXT: [[TMP43:%.*]] = load i32, i32* [[DOTOMP_IV57]], align 4, !llvm.access.group !17 9072 // CHECK15-NEXT: [[ADD84:%.*]] = add nsw i32 [[TMP43]], 1 9073 // CHECK15-NEXT: store i32 [[ADD84]], i32* [[DOTOMP_IV57]], align 4, !llvm.access.group !17 9074 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND59]], !llvm.loop [[LOOP18:![0-9]+]] 9075 // CHECK15: omp.inner.for.end85: 9076 // CHECK15-NEXT: store i32 10, i32* [[I58]], align 4 9077 // CHECK15-NEXT: [[TMP44:%.*]] = load i32, i32* [[A]], align 4 9078 // CHECK15-NEXT: [[TMP45:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 9079 // CHECK15-NEXT: call void @llvm.stackrestore(i8* [[TMP45]]) 9080 // CHECK15-NEXT: ret i32 [[TMP44]] 9081 // 9082 // 9083 // CHECK15-LABEL: define {{[^@]+}}@_Z3bari 9084 // CHECK15-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { 9085 // CHECK15-NEXT: entry: 9086 // CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 9087 // CHECK15-NEXT: [[A:%.*]] = alloca i32, align 4 9088 // CHECK15-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 9089 // CHECK15-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 9090 // CHECK15-NEXT: store i32 0, i32* [[A]], align 4 9091 // CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 9092 // CHECK15-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]]) 9093 // CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 9094 // CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 9095 // CHECK15-NEXT: store i32 [[ADD]], i32* [[A]], align 4 9096 // CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 9097 // CHECK15-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP2]]) 9098 // CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 9099 // CHECK15-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 9100 // CHECK15-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 9101 // CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 9102 // CHECK15-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]]) 9103 // CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 9104 // CHECK15-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 9105 // CHECK15-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 9106 // CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 9107 // CHECK15-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]]) 9108 // CHECK15-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 9109 // CHECK15-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] 9110 // CHECK15-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 9111 // CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 9112 // CHECK15-NEXT: ret i32 [[TMP8]] 9113 // 9114 // 9115 // CHECK15-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 9116 // CHECK15-SAME: (%struct.S1* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 { 9117 // CHECK15-NEXT: entry: 9118 // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 9119 // CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 9120 // CHECK15-NEXT: [[B:%.*]] = alloca i32, align 4 9121 // CHECK15-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 9122 // CHECK15-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 9123 // CHECK15-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 9124 // CHECK15-NEXT: [[TMP:%.*]] = alloca i32, align 4 9125 // CHECK15-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 9126 // CHECK15-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 9127 // CHECK15-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 9128 // CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 9129 // CHECK15-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 9130 // CHECK15-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 9131 // CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 9132 // CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 9133 // CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 9134 // CHECK15-NEXT: store i32 [[ADD]], i32* [[B]], align 4 9135 // CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 9136 // CHECK15-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() 9137 // CHECK15-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 9138 // CHECK15-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] 9139 // CHECK15-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 9140 // CHECK15-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 9141 // CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 9142 // CHECK15-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 60 9143 // CHECK15-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8 9144 // CHECK15-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 9145 // CHECK15-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 9146 // CHECK15-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 9147 // CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 9148 // CHECK15-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 9149 // CHECK15-NEXT: [[TMP6:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 9150 // CHECK15-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP6]] to i1 9151 // CHECK15-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 9152 // CHECK15: omp_if.then: 9153 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 9154 // CHECK15: omp.inner.for.cond: 9155 // CHECK15-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20 9156 // CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !20 9157 // CHECK15-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] 9158 // CHECK15-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 9159 // CHECK15: omp.inner.for.body: 9160 // CHECK15-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20 9161 // CHECK15-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 9162 // CHECK15-NEXT: [[ADD3:%.*]] = add nsw i32 0, [[MUL]] 9163 // CHECK15-NEXT: store i32 [[ADD3]], i32* [[I]], align 4, !llvm.access.group !20 9164 // CHECK15-NEXT: [[TMP10:%.*]] = load i32, i32* [[B]], align 4, !llvm.access.group !20 9165 // CHECK15-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP10]] to double 9166 // CHECK15-NEXT: [[ADD4:%.*]] = fadd double [[CONV]], 1.500000e+00 9167 // CHECK15-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 9168 // CHECK15-NEXT: store double [[ADD4]], double* [[A]], align 4, !llvm.access.group !20 9169 // CHECK15-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 9170 // CHECK15-NEXT: [[TMP11:%.*]] = load double, double* [[A5]], align 4, !llvm.access.group !20 9171 // CHECK15-NEXT: [[INC:%.*]] = fadd double [[TMP11]], 1.000000e+00 9172 // CHECK15-NEXT: store double [[INC]], double* [[A5]], align 4, !llvm.access.group !20 9173 // CHECK15-NEXT: [[CONV6:%.*]] = fptosi double [[INC]] to i16 9174 // CHECK15-NEXT: [[TMP12:%.*]] = mul nsw i32 1, [[TMP1]] 9175 // CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP12]] 9176 // CHECK15-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 9177 // CHECK15-NEXT: store i16 [[CONV6]], i16* [[ARRAYIDX7]], align 2, !llvm.access.group !20 9178 // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 9179 // CHECK15: omp.body.continue: 9180 // CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 9181 // CHECK15: omp.inner.for.inc: 9182 // CHECK15-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20 9183 // CHECK15-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP13]], 1 9184 // CHECK15-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20 9185 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]] 9186 // CHECK15: omp.inner.for.end: 9187 // CHECK15-NEXT: br label [[OMP_IF_END:%.*]] 9188 // CHECK15: omp_if.else: 9189 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND9:%.*]] 9190 // CHECK15: omp.inner.for.cond9: 9191 // CHECK15-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 9192 // CHECK15-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 9193 // CHECK15-NEXT: [[CMP10:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] 9194 // CHECK15-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY11:%.*]], label [[OMP_INNER_FOR_END25:%.*]] 9195 // CHECK15: omp.inner.for.body11: 9196 // CHECK15-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 9197 // CHECK15-NEXT: [[MUL12:%.*]] = mul nsw i32 [[TMP16]], 1 9198 // CHECK15-NEXT: [[ADD13:%.*]] = add nsw i32 0, [[MUL12]] 9199 // CHECK15-NEXT: store i32 [[ADD13]], i32* [[I]], align 4 9200 // CHECK15-NEXT: [[TMP17:%.*]] = load i32, i32* [[B]], align 4 9201 // CHECK15-NEXT: [[CONV14:%.*]] = sitofp i32 [[TMP17]] to double 9202 // CHECK15-NEXT: [[ADD15:%.*]] = fadd double [[CONV14]], 1.500000e+00 9203 // CHECK15-NEXT: [[A16:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 9204 // CHECK15-NEXT: store double [[ADD15]], double* [[A16]], align 4 9205 // CHECK15-NEXT: [[A17:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 9206 // CHECK15-NEXT: [[TMP18:%.*]] = load double, double* [[A17]], align 4 9207 // CHECK15-NEXT: [[INC18:%.*]] = fadd double [[TMP18]], 1.000000e+00 9208 // CHECK15-NEXT: store double [[INC18]], double* [[A17]], align 4 9209 // CHECK15-NEXT: [[CONV19:%.*]] = fptosi double [[INC18]] to i16 9210 // CHECK15-NEXT: [[TMP19:%.*]] = mul nsw i32 1, [[TMP1]] 9211 // CHECK15-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP19]] 9212 // CHECK15-NEXT: [[ARRAYIDX21:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX20]], i32 1 9213 // CHECK15-NEXT: store i16 [[CONV19]], i16* [[ARRAYIDX21]], align 2 9214 // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE22:%.*]] 9215 // CHECK15: omp.body.continue22: 9216 // CHECK15-NEXT: br label [[OMP_INNER_FOR_INC23:%.*]] 9217 // CHECK15: omp.inner.for.inc23: 9218 // CHECK15-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 9219 // CHECK15-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP20]], 1 9220 // CHECK15-NEXT: store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4 9221 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND9]], !llvm.loop [[LOOP23:![0-9]+]] 9222 // CHECK15: omp.inner.for.end25: 9223 // CHECK15-NEXT: br label [[OMP_IF_END]] 9224 // CHECK15: omp_if.end: 9225 // CHECK15-NEXT: store i32 10, i32* [[I]], align 4 9226 // CHECK15-NEXT: [[TMP21:%.*]] = mul nsw i32 1, [[TMP1]] 9227 // CHECK15-NEXT: [[ARRAYIDX26:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP21]] 9228 // CHECK15-NEXT: [[ARRAYIDX27:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX26]], i32 1 9229 // CHECK15-NEXT: [[TMP22:%.*]] = load i16, i16* [[ARRAYIDX27]], align 2 9230 // CHECK15-NEXT: [[CONV28:%.*]] = sext i16 [[TMP22]] to i32 9231 // CHECK15-NEXT: [[TMP23:%.*]] = load i32, i32* [[B]], align 4 9232 // CHECK15-NEXT: [[ADD29:%.*]] = add nsw i32 [[CONV28]], [[TMP23]] 9233 // CHECK15-NEXT: [[TMP24:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 9234 // CHECK15-NEXT: call void @llvm.stackrestore(i8* [[TMP24]]) 9235 // CHECK15-NEXT: ret i32 [[ADD29]] 9236 // 9237 // 9238 // CHECK15-LABEL: define {{[^@]+}}@_ZL7fstatici 9239 // CHECK15-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { 9240 // CHECK15-NEXT: entry: 9241 // CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 9242 // CHECK15-NEXT: [[A:%.*]] = alloca i32, align 4 9243 // CHECK15-NEXT: [[AA:%.*]] = alloca i16, align 2 9244 // CHECK15-NEXT: [[AAA:%.*]] = alloca i8, align 1 9245 // CHECK15-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 9246 // CHECK15-NEXT: [[TMP:%.*]] = alloca i32, align 4 9247 // CHECK15-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 9248 // CHECK15-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 9249 // CHECK15-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 9250 // CHECK15-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 9251 // CHECK15-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 9252 // CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 9253 // CHECK15-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 9254 // CHECK15-NEXT: [[I5:%.*]] = alloca i32, align 4 9255 // CHECK15-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 9256 // CHECK15-NEXT: store i32 0, i32* [[A]], align 4 9257 // CHECK15-NEXT: store i16 0, i16* [[AA]], align 2 9258 // CHECK15-NEXT: store i8 0, i8* [[AAA]], align 1 9259 // CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 9260 // CHECK15-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 9261 // CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 9262 // CHECK15-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_1]], align 4 9263 // CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 9264 // CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 9265 // CHECK15-NEXT: [[SUB:%.*]] = sub i32 [[TMP2]], [[TMP3]] 9266 // CHECK15-NEXT: [[SUB3:%.*]] = sub i32 [[SUB]], 1 9267 // CHECK15-NEXT: [[ADD:%.*]] = add i32 [[SUB3]], 1 9268 // CHECK15-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 9269 // CHECK15-NEXT: [[SUB4:%.*]] = sub i32 [[DIV]], 1 9270 // CHECK15-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_2]], align 4 9271 // CHECK15-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 9272 // CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 9273 // CHECK15-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_UB]], align 4 9274 // CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 9275 // CHECK15-NEXT: store i32 [[TMP5]], i32* [[I]], align 4 9276 // CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 9277 // CHECK15-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 9278 // CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]] 9279 // CHECK15-NEXT: br i1 [[CMP]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END:%.*]] 9280 // CHECK15: simd.if.then: 9281 // CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 9282 // CHECK15-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 9283 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 9284 // CHECK15: omp.inner.for.cond: 9285 // CHECK15-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25 9286 // CHECK15-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !25 9287 // CHECK15-NEXT: [[ADD6:%.*]] = add i32 [[TMP10]], 1 9288 // CHECK15-NEXT: [[CMP7:%.*]] = icmp ult i32 [[TMP9]], [[ADD6]] 9289 // CHECK15-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 9290 // CHECK15: omp.inner.for.body: 9291 // CHECK15-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group !25 9292 // CHECK15-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25 9293 // CHECK15-NEXT: [[MUL:%.*]] = mul i32 [[TMP12]], 1 9294 // CHECK15-NEXT: [[ADD8:%.*]] = add i32 [[TMP11]], [[MUL]] 9295 // CHECK15-NEXT: store i32 [[ADD8]], i32* [[I5]], align 4, !llvm.access.group !25 9296 // CHECK15-NEXT: [[TMP13:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !25 9297 // CHECK15-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP13]], 1 9298 // CHECK15-NEXT: store i32 [[ADD9]], i32* [[A]], align 4, !llvm.access.group !25 9299 // CHECK15-NEXT: [[TMP14:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !25 9300 // CHECK15-NEXT: [[CONV:%.*]] = sext i16 [[TMP14]] to i32 9301 // CHECK15-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV]], 1 9302 // CHECK15-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD10]] to i16 9303 // CHECK15-NEXT: store i16 [[CONV11]], i16* [[AA]], align 2, !llvm.access.group !25 9304 // CHECK15-NEXT: [[TMP15:%.*]] = load i8, i8* [[AAA]], align 1, !llvm.access.group !25 9305 // CHECK15-NEXT: [[CONV12:%.*]] = sext i8 [[TMP15]] to i32 9306 // CHECK15-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1 9307 // CHECK15-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i8 9308 // CHECK15-NEXT: store i8 [[CONV14]], i8* [[AAA]], align 1, !llvm.access.group !25 9309 // CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 9310 // CHECK15-NEXT: [[TMP16:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !25 9311 // CHECK15-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP16]], 1 9312 // CHECK15-NEXT: store i32 [[ADD15]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !25 9313 // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 9314 // CHECK15: omp.body.continue: 9315 // CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 9316 // CHECK15: omp.inner.for.inc: 9317 // CHECK15-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25 9318 // CHECK15-NEXT: [[ADD16:%.*]] = add i32 [[TMP17]], 1 9319 // CHECK15-NEXT: store i32 [[ADD16]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25 9320 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP26:![0-9]+]] 9321 // CHECK15: omp.inner.for.end: 9322 // CHECK15-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 9323 // CHECK15-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 9324 // CHECK15-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 9325 // CHECK15-NEXT: [[SUB17:%.*]] = sub i32 [[TMP19]], [[TMP20]] 9326 // CHECK15-NEXT: [[SUB18:%.*]] = sub i32 [[SUB17]], 1 9327 // CHECK15-NEXT: [[ADD19:%.*]] = add i32 [[SUB18]], 1 9328 // CHECK15-NEXT: [[DIV20:%.*]] = udiv i32 [[ADD19]], 1 9329 // CHECK15-NEXT: [[MUL21:%.*]] = mul i32 [[DIV20]], 1 9330 // CHECK15-NEXT: [[ADD22:%.*]] = add i32 [[TMP18]], [[MUL21]] 9331 // CHECK15-NEXT: store i32 [[ADD22]], i32* [[I5]], align 4 9332 // CHECK15-NEXT: br label [[SIMD_IF_END]] 9333 // CHECK15: simd.if.end: 9334 // CHECK15-NEXT: [[TMP21:%.*]] = load i32, i32* [[A]], align 4 9335 // CHECK15-NEXT: ret i32 [[TMP21]] 9336 // 9337 // 9338 // CHECK15-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 9339 // CHECK15-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat { 9340 // CHECK15-NEXT: entry: 9341 // CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 9342 // CHECK15-NEXT: [[A:%.*]] = alloca i32, align 4 9343 // CHECK15-NEXT: [[AA:%.*]] = alloca i16, align 2 9344 // CHECK15-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 9345 // CHECK15-NEXT: [[TMP:%.*]] = alloca i32, align 4 9346 // CHECK15-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 9347 // CHECK15-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 9348 // CHECK15-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 9349 // CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 9350 // CHECK15-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 9351 // CHECK15-NEXT: store i32 0, i32* [[A]], align 4 9352 // CHECK15-NEXT: store i16 0, i16* [[AA]], align 2 9353 // CHECK15-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 9354 // CHECK15-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 9355 // CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 9356 // CHECK15-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 9357 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 9358 // CHECK15: omp.inner.for.cond: 9359 // CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28 9360 // CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !28 9361 // CHECK15-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] 9362 // CHECK15-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 9363 // CHECK15: omp.inner.for.body: 9364 // CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28 9365 // CHECK15-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 9366 // CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 9367 // CHECK15-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !28 9368 // CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !28 9369 // CHECK15-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1 9370 // CHECK15-NEXT: store i32 [[ADD1]], i32* [[A]], align 4, !llvm.access.group !28 9371 // CHECK15-NEXT: [[TMP5:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !28 9372 // CHECK15-NEXT: [[CONV:%.*]] = sext i16 [[TMP5]] to i32 9373 // CHECK15-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 1 9374 // CHECK15-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 9375 // CHECK15-NEXT: store i16 [[CONV3]], i16* [[AA]], align 2, !llvm.access.group !28 9376 // CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 9377 // CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !28 9378 // CHECK15-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP6]], 1 9379 // CHECK15-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !28 9380 // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 9381 // CHECK15: omp.body.continue: 9382 // CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 9383 // CHECK15: omp.inner.for.inc: 9384 // CHECK15-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28 9385 // CHECK15-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP7]], 1 9386 // CHECK15-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28 9387 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP29:![0-9]+]] 9388 // CHECK15: omp.inner.for.end: 9389 // CHECK15-NEXT: store i32 10, i32* [[I]], align 4 9390 // CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 9391 // CHECK15-NEXT: ret i32 [[TMP8]] 9392 // 9393 // 9394 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97 9395 // CHECK17-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { 9396 // CHECK17-NEXT: entry: 9397 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 9398 // CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 9399 // CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8 9400 // CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 9401 // CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) 9402 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 9403 // CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 9404 // CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8 9405 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 9406 // CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* 9407 // CHECK17-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32* 9408 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 4 9409 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 4 9410 // CHECK17-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) 9411 // CHECK17-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 9412 // CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 9413 // CHECK17-NEXT: store i16 [[TMP3]], i16* [[CONV5]], align 2 9414 // CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 9415 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]]) 9416 // CHECK17-NEXT: ret void 9417 // 9418 // 9419 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined. 9420 // CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR1:[0-9]+]] { 9421 // CHECK17-NEXT: entry: 9422 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 9423 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 9424 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 9425 // CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 9426 // CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4 9427 // CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 9428 // CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 9429 // CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 9430 // CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 9431 // CHECK17-NEXT: [[I:%.*]] = alloca i32, align 4 9432 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 9433 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 9434 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 9435 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 9436 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 9437 // CHECK17-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 9438 // CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 9439 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 9440 // CHECK17-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 9441 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 9442 // CHECK17-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 9443 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 9444 // CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 9445 // CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 9446 // CHECK17: cond.true: 9447 // CHECK17-NEXT: br label [[COND_END:%.*]] 9448 // CHECK17: cond.false: 9449 // CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 9450 // CHECK17-NEXT: br label [[COND_END]] 9451 // CHECK17: cond.end: 9452 // CHECK17-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 9453 // CHECK17-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 9454 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 9455 // CHECK17-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 9456 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 9457 // CHECK17: omp.inner.for.cond: 9458 // CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 9459 // CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !11 9460 // CHECK17-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 9461 // CHECK17-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 9462 // CHECK17: omp.inner.for.body: 9463 // CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 9464 // CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 9465 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 9466 // CHECK17-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11 9467 // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 9468 // CHECK17: omp.body.continue: 9469 // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 9470 // CHECK17: omp.inner.for.inc: 9471 // CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 9472 // CHECK17-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 9473 // CHECK17-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 9474 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] 9475 // CHECK17: omp.inner.for.end: 9476 // CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 9477 // CHECK17: omp.loop.exit: 9478 // CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 9479 // CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 9480 // CHECK17-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 9481 // CHECK17-NEXT: br i1 [[TMP10]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 9482 // CHECK17: .omp.final.then: 9483 // CHECK17-NEXT: store i32 10, i32* [[I]], align 4 9484 // CHECK17-NEXT: br label [[DOTOMP_FINAL_DONE]] 9485 // CHECK17: .omp.final.done: 9486 // CHECK17-NEXT: ret void 9487 // 9488 // 9489 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 9490 // CHECK17-SAME: (i64 noundef [[AA:%.*]]) #[[ATTR0]] { 9491 // CHECK17-NEXT: entry: 9492 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 9493 // CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 9494 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 9495 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 9496 // CHECK17-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 9497 // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 9498 // CHECK17-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 9499 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 9500 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]]) 9501 // CHECK17-NEXT: ret void 9502 // 9503 // 9504 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..1 9505 // CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR1]] { 9506 // CHECK17-NEXT: entry: 9507 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 9508 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 9509 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 9510 // CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 9511 // CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4 9512 // CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 9513 // CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 9514 // CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 9515 // CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 9516 // CHECK17-NEXT: [[I:%.*]] = alloca i32, align 4 9517 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 9518 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 9519 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 9520 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 9521 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 9522 // CHECK17-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 9523 // CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 9524 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 9525 // CHECK17-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 9526 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 9527 // CHECK17-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 9528 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 9529 // CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 9530 // CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 9531 // CHECK17: cond.true: 9532 // CHECK17-NEXT: br label [[COND_END:%.*]] 9533 // CHECK17: cond.false: 9534 // CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 9535 // CHECK17-NEXT: br label [[COND_END]] 9536 // CHECK17: cond.end: 9537 // CHECK17-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 9538 // CHECK17-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 9539 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 9540 // CHECK17-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 9541 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 9542 // CHECK17: omp.inner.for.cond: 9543 // CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 9544 // CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !18 9545 // CHECK17-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 9546 // CHECK17-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 9547 // CHECK17: omp.inner.for.body: 9548 // CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 9549 // CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 9550 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 9551 // CHECK17-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18 9552 // CHECK17-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !18 9553 // CHECK17-NEXT: [[CONV2:%.*]] = sext i16 [[TMP8]] to i32 9554 // CHECK17-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 9555 // CHECK17-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 9556 // CHECK17-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2, !llvm.access.group !18 9557 // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 9558 // CHECK17: omp.body.continue: 9559 // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 9560 // CHECK17: omp.inner.for.inc: 9561 // CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 9562 // CHECK17-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP9]], 1 9563 // CHECK17-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 9564 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] 9565 // CHECK17: omp.inner.for.end: 9566 // CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 9567 // CHECK17: omp.loop.exit: 9568 // CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 9569 // CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 9570 // CHECK17-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0 9571 // CHECK17-NEXT: br i1 [[TMP11]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 9572 // CHECK17: .omp.final.then: 9573 // CHECK17-NEXT: store i32 10, i32* [[I]], align 4 9574 // CHECK17-NEXT: br label [[DOTOMP_FINAL_DONE]] 9575 // CHECK17: .omp.final.done: 9576 // CHECK17-NEXT: ret void 9577 // 9578 // 9579 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118 9580 // CHECK17-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { 9581 // CHECK17-NEXT: entry: 9582 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 9583 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 9584 // CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 9585 // CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 9586 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 9587 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 9588 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 9589 // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 9590 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 9591 // CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* 9592 // CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 9593 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 9594 // CHECK17-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 9595 // CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 9596 // CHECK17-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 9597 // CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 9598 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) 9599 // CHECK17-NEXT: ret void 9600 // 9601 // 9602 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..2 9603 // CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR1]] { 9604 // CHECK17-NEXT: entry: 9605 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 9606 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 9607 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 9608 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 9609 // CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 9610 // CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4 9611 // CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 9612 // CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 9613 // CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 9614 // CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 9615 // CHECK17-NEXT: [[I:%.*]] = alloca i32, align 4 9616 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 9617 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 9618 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 9619 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 9620 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 9621 // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 9622 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 9623 // CHECK17-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 9624 // CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 9625 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 9626 // CHECK17-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 9627 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 9628 // CHECK17-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 9629 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 9630 // CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 9631 // CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 9632 // CHECK17: cond.true: 9633 // CHECK17-NEXT: br label [[COND_END:%.*]] 9634 // CHECK17: cond.false: 9635 // CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 9636 // CHECK17-NEXT: br label [[COND_END]] 9637 // CHECK17: cond.end: 9638 // CHECK17-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 9639 // CHECK17-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 9640 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 9641 // CHECK17-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 9642 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 9643 // CHECK17: omp.inner.for.cond: 9644 // CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 9645 // CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !21 9646 // CHECK17-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 9647 // CHECK17-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 9648 // CHECK17: omp.inner.for.body: 9649 // CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 9650 // CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 9651 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 9652 // CHECK17-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !21 9653 // CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !21 9654 // CHECK17-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1 9655 // CHECK17-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4, !llvm.access.group !21 9656 // CHECK17-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 2, !llvm.access.group !21 9657 // CHECK17-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32 9658 // CHECK17-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 9659 // CHECK17-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 9660 // CHECK17-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2, !llvm.access.group !21 9661 // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 9662 // CHECK17: omp.body.continue: 9663 // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 9664 // CHECK17: omp.inner.for.inc: 9665 // CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 9666 // CHECK17-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1 9667 // CHECK17-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 9668 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]] 9669 // CHECK17: omp.inner.for.end: 9670 // CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 9671 // CHECK17: omp.loop.exit: 9672 // CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 9673 // CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 9674 // CHECK17-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 9675 // CHECK17-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 9676 // CHECK17: .omp.final.then: 9677 // CHECK17-NEXT: store i32 10, i32* [[I]], align 4 9678 // CHECK17-NEXT: br label [[DOTOMP_FINAL_DONE]] 9679 // CHECK17: .omp.final.done: 9680 // CHECK17-NEXT: ret void 9681 // 9682 // 9683 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142 9684 // CHECK17-SAME: (i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] { 9685 // CHECK17-NEXT: entry: 9686 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 9687 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 9688 // CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 9689 // CHECK17-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 9690 // CHECK17-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 9691 // CHECK17-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 9692 // CHECK17-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 9693 // CHECK17-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 9694 // CHECK17-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 9695 // CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 9696 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 9697 // CHECK17-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 9698 // CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 9699 // CHECK17-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 9700 // CHECK17-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 9701 // CHECK17-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 9702 // CHECK17-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 9703 // CHECK17-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 9704 // CHECK17-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 9705 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 9706 // CHECK17-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 9707 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 9708 // CHECK17-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 9709 // CHECK17-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 9710 // CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 9711 // CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 9712 // CHECK17-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 9713 // CHECK17-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 9714 // CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 9715 // CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* 9716 // CHECK17-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4 9717 // CHECK17-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 9718 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) 9719 // CHECK17-NEXT: ret void 9720 // 9721 // 9722 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..3 9723 // CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR1]] { 9724 // CHECK17-NEXT: entry: 9725 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 9726 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 9727 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 9728 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 9729 // CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 9730 // CHECK17-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 9731 // CHECK17-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 9732 // CHECK17-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 9733 // CHECK17-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 9734 // CHECK17-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 9735 // CHECK17-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 9736 // CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 9737 // CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4 9738 // CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 9739 // CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 9740 // CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 9741 // CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 9742 // CHECK17-NEXT: [[I:%.*]] = alloca i32, align 4 9743 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 9744 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 9745 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 9746 // CHECK17-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 9747 // CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 9748 // CHECK17-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 9749 // CHECK17-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 9750 // CHECK17-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 9751 // CHECK17-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 9752 // CHECK17-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 9753 // CHECK17-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 9754 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 9755 // CHECK17-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 9756 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 9757 // CHECK17-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 9758 // CHECK17-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 9759 // CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 9760 // CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 9761 // CHECK17-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 9762 // CHECK17-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 9763 // CHECK17-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 0 9764 // CHECK17-NEXT: call void @llvm.assume(i1 true) [ "align"(float* [[ARRAYDECAY]], i64 16) ] 9765 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 9766 // CHECK17-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 9767 // CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 9768 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 9769 // CHECK17-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 9770 // CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 9771 // CHECK17-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 9772 // CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 9773 // CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP10]], 9 9774 // CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 9775 // CHECK17: cond.true: 9776 // CHECK17-NEXT: br label [[COND_END:%.*]] 9777 // CHECK17: cond.false: 9778 // CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 9779 // CHECK17-NEXT: br label [[COND_END]] 9780 // CHECK17: cond.end: 9781 // CHECK17-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] 9782 // CHECK17-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 9783 // CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 9784 // CHECK17-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 9785 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 9786 // CHECK17: omp.inner.for.cond: 9787 // CHECK17-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 9788 // CHECK17-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !24 9789 // CHECK17-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] 9790 // CHECK17-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 9791 // CHECK17: omp.inner.for.body: 9792 // CHECK17-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 9793 // CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 9794 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 9795 // CHECK17-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !24 9796 // CHECK17-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !24 9797 // CHECK17-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP16]], 1 9798 // CHECK17-NEXT: store i32 [[ADD6]], i32* [[CONV]], align 4, !llvm.access.group !24 9799 // CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 9800 // CHECK17-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !24 9801 // CHECK17-NEXT: [[CONV7:%.*]] = fpext float [[TMP17]] to double 9802 // CHECK17-NEXT: [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00 9803 // CHECK17-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float 9804 // CHECK17-NEXT: store float [[CONV9]], float* [[ARRAYIDX]], align 4, !llvm.access.group !24 9805 // CHECK17-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 9806 // CHECK17-NEXT: [[TMP18:%.*]] = load float, float* [[ARRAYIDX10]], align 4, !llvm.access.group !24 9807 // CHECK17-NEXT: [[CONV11:%.*]] = fpext float [[TMP18]] to double 9808 // CHECK17-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00 9809 // CHECK17-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float 9810 // CHECK17-NEXT: store float [[CONV13]], float* [[ARRAYIDX10]], align 4, !llvm.access.group !24 9811 // CHECK17-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1 9812 // CHECK17-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX14]], i64 0, i64 2 9813 // CHECK17-NEXT: [[TMP19:%.*]] = load double, double* [[ARRAYIDX15]], align 8, !llvm.access.group !24 9814 // CHECK17-NEXT: [[ADD16:%.*]] = fadd double [[TMP19]], 1.000000e+00 9815 // CHECK17-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8, !llvm.access.group !24 9816 // CHECK17-NEXT: [[TMP20:%.*]] = mul nsw i64 1, [[TMP5]] 9817 // CHECK17-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP20]] 9818 // CHECK17-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX17]], i64 3 9819 // CHECK17-NEXT: [[TMP21:%.*]] = load double, double* [[ARRAYIDX18]], align 8, !llvm.access.group !24 9820 // CHECK17-NEXT: [[ADD19:%.*]] = fadd double [[TMP21]], 1.000000e+00 9821 // CHECK17-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8, !llvm.access.group !24 9822 // CHECK17-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 9823 // CHECK17-NEXT: [[TMP22:%.*]] = load i64, i64* [[X]], align 8, !llvm.access.group !24 9824 // CHECK17-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP22]], 1 9825 // CHECK17-NEXT: store i64 [[ADD20]], i64* [[X]], align 8, !llvm.access.group !24 9826 // CHECK17-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 9827 // CHECK17-NEXT: [[TMP23:%.*]] = load i8, i8* [[Y]], align 8, !llvm.access.group !24 9828 // CHECK17-NEXT: [[CONV21:%.*]] = sext i8 [[TMP23]] to i32 9829 // CHECK17-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1 9830 // CHECK17-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8 9831 // CHECK17-NEXT: store i8 [[CONV23]], i8* [[Y]], align 8, !llvm.access.group !24 9832 // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 9833 // CHECK17: omp.body.continue: 9834 // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 9835 // CHECK17: omp.inner.for.inc: 9836 // CHECK17-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 9837 // CHECK17-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP24]], 1 9838 // CHECK17-NEXT: store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 9839 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]] 9840 // CHECK17: omp.inner.for.end: 9841 // CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 9842 // CHECK17: omp.loop.exit: 9843 // CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]]) 9844 // CHECK17-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 9845 // CHECK17-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0 9846 // CHECK17-NEXT: br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 9847 // CHECK17: .omp.final.then: 9848 // CHECK17-NEXT: store i32 10, i32* [[I]], align 4 9849 // CHECK17-NEXT: br label [[DOTOMP_FINAL_DONE]] 9850 // CHECK17: .omp.final.done: 9851 // CHECK17-NEXT: ret void 9852 // 9853 // 9854 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197 9855 // CHECK17-SAME: (i64 noundef [[A:%.*]], i64 noundef [[N:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 9856 // CHECK17-NEXT: entry: 9857 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 9858 // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 9859 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 9860 // CHECK17-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 9861 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 9862 // CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 9863 // CHECK17-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 9864 // CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 9865 // CHECK17-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 9866 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 9867 // CHECK17-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 9868 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 9869 // CHECK17-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 9870 // CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 9871 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 9872 // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32* 9873 // CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 9874 // CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 9875 // CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 9876 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 9877 // CHECK17-NEXT: [[CONV4:%.*]] = bitcast i64* [[A_CASTED]] to i32* 9878 // CHECK17-NEXT: store i32 [[TMP1]], i32* [[CONV4]], align 4 9879 // CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 9880 // CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 4 9881 // CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[N_CASTED]] to i32* 9882 // CHECK17-NEXT: store i32 [[TMP3]], i32* [[CONV5]], align 4 9883 // CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8 9884 // CHECK17-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV2]], align 2 9885 // CHECK17-NEXT: [[CONV6:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 9886 // CHECK17-NEXT: store i16 [[TMP5]], i16* [[CONV6]], align 2 9887 // CHECK17-NEXT: [[TMP6:%.*]] = load i64, i64* [[AA_CASTED]], align 8 9888 // CHECK17-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV3]], align 1 9889 // CHECK17-NEXT: [[CONV7:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* 9890 // CHECK17-NEXT: store i8 [[TMP7]], i8* [[CONV7]], align 1 9891 // CHECK17-NEXT: [[TMP8:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 9892 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]], [10 x i32]* [[TMP0]]) 9893 // CHECK17-NEXT: ret void 9894 // 9895 // 9896 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..4 9897 // CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[N:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { 9898 // CHECK17-NEXT: entry: 9899 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 9900 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 9901 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 9902 // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 9903 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 9904 // CHECK17-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 9905 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 9906 // CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 9907 // CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4 9908 // CHECK17-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 9909 // CHECK17-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4 9910 // CHECK17-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i32, align 4 9911 // CHECK17-NEXT: [[I:%.*]] = alloca i32, align 4 9912 // CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 9913 // CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 9914 // CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 9915 // CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 9916 // CHECK17-NEXT: [[I8:%.*]] = alloca i32, align 4 9917 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 9918 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 9919 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 9920 // CHECK17-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 9921 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 9922 // CHECK17-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 9923 // CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 9924 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 9925 // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32* 9926 // CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 9927 // CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 9928 // CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 9929 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 9930 // CHECK17-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 9931 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4 9932 // CHECK17-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_4]], align 4 9933 // CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 9934 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 9935 // CHECK17-NEXT: [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]] 9936 // CHECK17-NEXT: [[SUB6:%.*]] = sub i32 [[SUB]], 1 9937 // CHECK17-NEXT: [[ADD:%.*]] = add i32 [[SUB6]], 1 9938 // CHECK17-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 9939 // CHECK17-NEXT: [[SUB7:%.*]] = sub i32 [[DIV]], 1 9940 // CHECK17-NEXT: store i32 [[SUB7]], i32* [[DOTCAPTURE_EXPR_5]], align 4 9941 // CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 9942 // CHECK17-NEXT: store i32 [[TMP5]], i32* [[I]], align 4 9943 // CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 9944 // CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 9945 // CHECK17-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]] 9946 // CHECK17-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] 9947 // CHECK17: omp.precond.then: 9948 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 9949 // CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 9950 // CHECK17-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_UB]], align 4 9951 // CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 9952 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 9953 // CHECK17-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 9954 // CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 9955 // CHECK17-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 9956 // CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 9957 // CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 9958 // CHECK17-NEXT: [[CMP9:%.*]] = icmp ugt i32 [[TMP11]], [[TMP12]] 9959 // CHECK17-NEXT: br i1 [[CMP9]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 9960 // CHECK17: cond.true: 9961 // CHECK17-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 9962 // CHECK17-NEXT: br label [[COND_END:%.*]] 9963 // CHECK17: cond.false: 9964 // CHECK17-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 9965 // CHECK17-NEXT: br label [[COND_END]] 9966 // CHECK17: cond.end: 9967 // CHECK17-NEXT: [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ] 9968 // CHECK17-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 9969 // CHECK17-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 9970 // CHECK17-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4 9971 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 9972 // CHECK17: omp.inner.for.cond: 9973 // CHECK17-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 9974 // CHECK17-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !27 9975 // CHECK17-NEXT: [[ADD10:%.*]] = add i32 [[TMP17]], 1 9976 // CHECK17-NEXT: [[CMP11:%.*]] = icmp ult i32 [[TMP16]], [[ADD10]] 9977 // CHECK17-NEXT: br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 9978 // CHECK17: omp.inner.for.body: 9979 // CHECK17-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group !27 9980 // CHECK17-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 9981 // CHECK17-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 1 9982 // CHECK17-NEXT: [[ADD12:%.*]] = add i32 [[TMP18]], [[MUL]] 9983 // CHECK17-NEXT: store i32 [[ADD12]], i32* [[I8]], align 4, !llvm.access.group !27 9984 // CHECK17-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !27 9985 // CHECK17-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP20]], 1 9986 // CHECK17-NEXT: store i32 [[ADD13]], i32* [[CONV]], align 4, !llvm.access.group !27 9987 // CHECK17-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV2]], align 2, !llvm.access.group !27 9988 // CHECK17-NEXT: [[CONV14:%.*]] = sext i16 [[TMP21]] to i32 9989 // CHECK17-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1 9990 // CHECK17-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16 9991 // CHECK17-NEXT: store i16 [[CONV16]], i16* [[CONV2]], align 2, !llvm.access.group !27 9992 // CHECK17-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV3]], align 1, !llvm.access.group !27 9993 // CHECK17-NEXT: [[CONV17:%.*]] = sext i8 [[TMP22]] to i32 9994 // CHECK17-NEXT: [[ADD18:%.*]] = add nsw i32 [[CONV17]], 1 9995 // CHECK17-NEXT: [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8 9996 // CHECK17-NEXT: store i8 [[CONV19]], i8* [[CONV3]], align 1, !llvm.access.group !27 9997 // CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 9998 // CHECK17-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !27 9999 // CHECK17-NEXT: [[ADD20:%.*]] = add nsw i32 [[TMP23]], 1 10000 // CHECK17-NEXT: store i32 [[ADD20]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !27 10001 // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 10002 // CHECK17: omp.body.continue: 10003 // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 10004 // CHECK17: omp.inner.for.inc: 10005 // CHECK17-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 10006 // CHECK17-NEXT: [[ADD21:%.*]] = add i32 [[TMP24]], 1 10007 // CHECK17-NEXT: store i32 [[ADD21]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 10008 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]] 10009 // CHECK17: omp.inner.for.end: 10010 // CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 10011 // CHECK17: omp.loop.exit: 10012 // CHECK17-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 10013 // CHECK17-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 10014 // CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) 10015 // CHECK17-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 10016 // CHECK17-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0 10017 // CHECK17-NEXT: br i1 [[TMP28]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 10018 // CHECK17: .omp.final.then: 10019 // CHECK17-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 10020 // CHECK17-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 10021 // CHECK17-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 10022 // CHECK17-NEXT: [[SUB22:%.*]] = sub i32 [[TMP30]], [[TMP31]] 10023 // CHECK17-NEXT: [[SUB23:%.*]] = sub i32 [[SUB22]], 1 10024 // CHECK17-NEXT: [[ADD24:%.*]] = add i32 [[SUB23]], 1 10025 // CHECK17-NEXT: [[DIV25:%.*]] = udiv i32 [[ADD24]], 1 10026 // CHECK17-NEXT: [[MUL26:%.*]] = mul i32 [[DIV25]], 1 10027 // CHECK17-NEXT: [[ADD27:%.*]] = add i32 [[TMP29]], [[MUL26]] 10028 // CHECK17-NEXT: store i32 [[ADD27]], i32* [[I8]], align 4 10029 // CHECK17-NEXT: br label [[DOTOMP_FINAL_DONE]] 10030 // CHECK17: .omp.final.done: 10031 // CHECK17-NEXT: br label [[OMP_PRECOND_END]] 10032 // CHECK17: omp.precond.end: 10033 // CHECK17-NEXT: ret void 10034 // 10035 // 10036 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215 10037 // CHECK17-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { 10038 // CHECK17-NEXT: entry: 10039 // CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 10040 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 10041 // CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 10042 // CHECK17-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 10043 // CHECK17-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 10044 // CHECK17-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 10045 // CHECK17-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 10046 // CHECK17-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 10047 // CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 10048 // CHECK17-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 10049 // CHECK17-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 10050 // CHECK17-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 10051 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 10052 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 10053 // CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 10054 // CHECK17-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 10055 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4 10056 // CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* 10057 // CHECK17-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 10058 // CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 10059 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) 10060 // CHECK17-NEXT: ret void 10061 // 10062 // 10063 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..5 10064 // CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] { 10065 // CHECK17-NEXT: entry: 10066 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 10067 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 10068 // CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 10069 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 10070 // CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 10071 // CHECK17-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 10072 // CHECK17-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 10073 // CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 10074 // CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4 10075 // CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 10076 // CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 10077 // CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 10078 // CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 10079 // CHECK17-NEXT: [[I:%.*]] = alloca i32, align 4 10080 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 10081 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 10082 // CHECK17-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 10083 // CHECK17-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 10084 // CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 10085 // CHECK17-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 10086 // CHECK17-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 10087 // CHECK17-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 10088 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 10089 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 10090 // CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 10091 // CHECK17-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 10092 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 10093 // CHECK17-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 10094 // CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 10095 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 10096 // CHECK17-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 10097 // CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 10098 // CHECK17-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 10099 // CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 10100 // CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 9 10101 // CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 10102 // CHECK17: cond.true: 10103 // CHECK17-NEXT: br label [[COND_END:%.*]] 10104 // CHECK17: cond.false: 10105 // CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 10106 // CHECK17-NEXT: br label [[COND_END]] 10107 // CHECK17: cond.end: 10108 // CHECK17-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 10109 // CHECK17-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 10110 // CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 10111 // CHECK17-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 10112 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 10113 // CHECK17: omp.inner.for.cond: 10114 // CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30 10115 // CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !30 10116 // CHECK17-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 10117 // CHECK17-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 10118 // CHECK17: omp.inner.for.body: 10119 // CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30 10120 // CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 10121 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 10122 // CHECK17-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !30 10123 // CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !30 10124 // CHECK17-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double 10125 // CHECK17-NEXT: [[ADD5:%.*]] = fadd double [[CONV4]], 1.500000e+00 10126 // CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 10127 // CHECK17-NEXT: store double [[ADD5]], double* [[A]], align 8, !llvm.access.group !30 10128 // CHECK17-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 10129 // CHECK17-NEXT: [[TMP13:%.*]] = load double, double* [[A6]], align 8, !llvm.access.group !30 10130 // CHECK17-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 10131 // CHECK17-NEXT: store double [[INC]], double* [[A6]], align 8, !llvm.access.group !30 10132 // CHECK17-NEXT: [[CONV7:%.*]] = fptosi double [[INC]] to i16 10133 // CHECK17-NEXT: [[TMP14:%.*]] = mul nsw i64 1, [[TMP2]] 10134 // CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP14]] 10135 // CHECK17-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 10136 // CHECK17-NEXT: store i16 [[CONV7]], i16* [[ARRAYIDX8]], align 2, !llvm.access.group !30 10137 // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 10138 // CHECK17: omp.body.continue: 10139 // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 10140 // CHECK17: omp.inner.for.inc: 10141 // CHECK17-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30 10142 // CHECK17-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP15]], 1 10143 // CHECK17-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30 10144 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP31:![0-9]+]] 10145 // CHECK17: omp.inner.for.end: 10146 // CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 10147 // CHECK17: omp.loop.exit: 10148 // CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 10149 // CHECK17-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 10150 // CHECK17-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0 10151 // CHECK17-NEXT: br i1 [[TMP17]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 10152 // CHECK17: .omp.final.then: 10153 // CHECK17-NEXT: store i32 10, i32* [[I]], align 4 10154 // CHECK17-NEXT: br label [[DOTOMP_FINAL_DONE]] 10155 // CHECK17: .omp.final.done: 10156 // CHECK17-NEXT: ret void 10157 // 10158 // 10159 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180 10160 // CHECK17-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 10161 // CHECK17-NEXT: entry: 10162 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 10163 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 10164 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 10165 // CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 10166 // CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 10167 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 10168 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 10169 // CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 10170 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 10171 // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 10172 // CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 10173 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 10174 // CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* 10175 // CHECK17-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 10176 // CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 10177 // CHECK17-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 10178 // CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 10179 // CHECK17-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 10180 // CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 10181 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) 10182 // CHECK17-NEXT: ret void 10183 // 10184 // 10185 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..6 10186 // CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { 10187 // CHECK17-NEXT: entry: 10188 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 10189 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 10190 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 10191 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 10192 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 10193 // CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 10194 // CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4 10195 // CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 10196 // CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 10197 // CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 10198 // CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 10199 // CHECK17-NEXT: [[I:%.*]] = alloca i32, align 4 10200 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 10201 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 10202 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 10203 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 10204 // CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 10205 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 10206 // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 10207 // CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 10208 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 10209 // CHECK17-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 10210 // CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 10211 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 10212 // CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 10213 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 10214 // CHECK17-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 10215 // CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 10216 // CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 10217 // CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 10218 // CHECK17: cond.true: 10219 // CHECK17-NEXT: br label [[COND_END:%.*]] 10220 // CHECK17: cond.false: 10221 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 10222 // CHECK17-NEXT: br label [[COND_END]] 10223 // CHECK17: cond.end: 10224 // CHECK17-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 10225 // CHECK17-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 10226 // CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 10227 // CHECK17-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 10228 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 10229 // CHECK17: omp.inner.for.cond: 10230 // CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33 10231 // CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !33 10232 // CHECK17-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] 10233 // CHECK17-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 10234 // CHECK17: omp.inner.for.body: 10235 // CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33 10236 // CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 10237 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 10238 // CHECK17-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !33 10239 // CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !33 10240 // CHECK17-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1 10241 // CHECK17-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4, !llvm.access.group !33 10242 // CHECK17-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 2, !llvm.access.group !33 10243 // CHECK17-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32 10244 // CHECK17-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 10245 // CHECK17-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 10246 // CHECK17-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2, !llvm.access.group !33 10247 // CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 10248 // CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !33 10249 // CHECK17-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1 10250 // CHECK17-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !33 10251 // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 10252 // CHECK17: omp.body.continue: 10253 // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 10254 // CHECK17: omp.inner.for.inc: 10255 // CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33 10256 // CHECK17-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP12]], 1 10257 // CHECK17-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33 10258 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP34:![0-9]+]] 10259 // CHECK17: omp.inner.for.end: 10260 // CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 10261 // CHECK17: omp.loop.exit: 10262 // CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) 10263 // CHECK17-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 10264 // CHECK17-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 10265 // CHECK17-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 10266 // CHECK17: .omp.final.then: 10267 // CHECK17-NEXT: store i32 10, i32* [[I]], align 4 10268 // CHECK17-NEXT: br label [[DOTOMP_FINAL_DONE]] 10269 // CHECK17: .omp.final.done: 10270 // CHECK17-NEXT: ret void 10271 // 10272 // 10273 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97 10274 // CHECK19-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]], i32 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { 10275 // CHECK19-NEXT: entry: 10276 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 10277 // CHECK19-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 10278 // CHECK19-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4 10279 // CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 10280 // CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) 10281 // CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 10282 // CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 10283 // CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 10284 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 10285 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 10286 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 10287 // CHECK19-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) 10288 // CHECK19-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 10289 // CHECK19-NEXT: [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 10290 // CHECK19-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 10291 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 10292 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]]) 10293 // CHECK19-NEXT: ret void 10294 // 10295 // 10296 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined. 10297 // CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR1:[0-9]+]] { 10298 // CHECK19-NEXT: entry: 10299 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 10300 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 10301 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 10302 // CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 10303 // CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4 10304 // CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 10305 // CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 10306 // CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 10307 // CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 10308 // CHECK19-NEXT: [[I:%.*]] = alloca i32, align 4 10309 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 10310 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 10311 // CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 10312 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 10313 // CHECK19-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 10314 // CHECK19-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 10315 // CHECK19-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 10316 // CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 10317 // CHECK19-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 10318 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 10319 // CHECK19-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 10320 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 10321 // CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 10322 // CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 10323 // CHECK19: cond.true: 10324 // CHECK19-NEXT: br label [[COND_END:%.*]] 10325 // CHECK19: cond.false: 10326 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 10327 // CHECK19-NEXT: br label [[COND_END]] 10328 // CHECK19: cond.end: 10329 // CHECK19-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 10330 // CHECK19-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 10331 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 10332 // CHECK19-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 10333 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 10334 // CHECK19: omp.inner.for.cond: 10335 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 10336 // CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !12 10337 // CHECK19-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 10338 // CHECK19-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 10339 // CHECK19: omp.inner.for.body: 10340 // CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 10341 // CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 10342 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 10343 // CHECK19-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !12 10344 // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 10345 // CHECK19: omp.body.continue: 10346 // CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 10347 // CHECK19: omp.inner.for.inc: 10348 // CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 10349 // CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 10350 // CHECK19-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 10351 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] 10352 // CHECK19: omp.inner.for.end: 10353 // CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 10354 // CHECK19: omp.loop.exit: 10355 // CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 10356 // CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 10357 // CHECK19-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 10358 // CHECK19-NEXT: br i1 [[TMP10]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 10359 // CHECK19: .omp.final.then: 10360 // CHECK19-NEXT: store i32 10, i32* [[I]], align 4 10361 // CHECK19-NEXT: br label [[DOTOMP_FINAL_DONE]] 10362 // CHECK19: .omp.final.done: 10363 // CHECK19-NEXT: ret void 10364 // 10365 // 10366 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 10367 // CHECK19-SAME: (i32 noundef [[AA:%.*]]) #[[ATTR0]] { 10368 // CHECK19-NEXT: entry: 10369 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 10370 // CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 10371 // CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 10372 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 10373 // CHECK19-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 10374 // CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 10375 // CHECK19-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 10376 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 10377 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]]) 10378 // CHECK19-NEXT: ret void 10379 // 10380 // 10381 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..1 10382 // CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR1]] { 10383 // CHECK19-NEXT: entry: 10384 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 10385 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 10386 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 10387 // CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 10388 // CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4 10389 // CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 10390 // CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 10391 // CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 10392 // CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 10393 // CHECK19-NEXT: [[I:%.*]] = alloca i32, align 4 10394 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 10395 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 10396 // CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 10397 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 10398 // CHECK19-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 10399 // CHECK19-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 10400 // CHECK19-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 10401 // CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 10402 // CHECK19-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 10403 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 10404 // CHECK19-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 10405 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 10406 // CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 10407 // CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 10408 // CHECK19: cond.true: 10409 // CHECK19-NEXT: br label [[COND_END:%.*]] 10410 // CHECK19: cond.false: 10411 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 10412 // CHECK19-NEXT: br label [[COND_END]] 10413 // CHECK19: cond.end: 10414 // CHECK19-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 10415 // CHECK19-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 10416 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 10417 // CHECK19-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 10418 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 10419 // CHECK19: omp.inner.for.cond: 10420 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 10421 // CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !19 10422 // CHECK19-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 10423 // CHECK19-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 10424 // CHECK19: omp.inner.for.body: 10425 // CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 10426 // CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 10427 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 10428 // CHECK19-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !19 10429 // CHECK19-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !19 10430 // CHECK19-NEXT: [[CONV2:%.*]] = sext i16 [[TMP8]] to i32 10431 // CHECK19-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 10432 // CHECK19-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 10433 // CHECK19-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2, !llvm.access.group !19 10434 // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 10435 // CHECK19: omp.body.continue: 10436 // CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 10437 // CHECK19: omp.inner.for.inc: 10438 // CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 10439 // CHECK19-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP9]], 1 10440 // CHECK19-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 10441 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]] 10442 // CHECK19: omp.inner.for.end: 10443 // CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 10444 // CHECK19: omp.loop.exit: 10445 // CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 10446 // CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 10447 // CHECK19-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0 10448 // CHECK19-NEXT: br i1 [[TMP11]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 10449 // CHECK19: .omp.final.then: 10450 // CHECK19-NEXT: store i32 10, i32* [[I]], align 4 10451 // CHECK19-NEXT: br label [[DOTOMP_FINAL_DONE]] 10452 // CHECK19: .omp.final.done: 10453 // CHECK19-NEXT: ret void 10454 // 10455 // 10456 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118 10457 // CHECK19-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { 10458 // CHECK19-NEXT: entry: 10459 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 10460 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 10461 // CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 10462 // CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 10463 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 10464 // CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 10465 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 10466 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 10467 // CHECK19-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 10468 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 10469 // CHECK19-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 10470 // CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 10471 // CHECK19-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 10472 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 10473 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) 10474 // CHECK19-NEXT: ret void 10475 // 10476 // 10477 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..2 10478 // CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR1]] { 10479 // CHECK19-NEXT: entry: 10480 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 10481 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 10482 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 10483 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 10484 // CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 10485 // CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4 10486 // CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 10487 // CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 10488 // CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 10489 // CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 10490 // CHECK19-NEXT: [[I:%.*]] = alloca i32, align 4 10491 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 10492 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 10493 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 10494 // CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 10495 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 10496 // CHECK19-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 10497 // CHECK19-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 10498 // CHECK19-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 10499 // CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 10500 // CHECK19-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 10501 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 10502 // CHECK19-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 10503 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 10504 // CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 10505 // CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 10506 // CHECK19: cond.true: 10507 // CHECK19-NEXT: br label [[COND_END:%.*]] 10508 // CHECK19: cond.false: 10509 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 10510 // CHECK19-NEXT: br label [[COND_END]] 10511 // CHECK19: cond.end: 10512 // CHECK19-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 10513 // CHECK19-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 10514 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 10515 // CHECK19-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 10516 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 10517 // CHECK19: omp.inner.for.cond: 10518 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 10519 // CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !22 10520 // CHECK19-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 10521 // CHECK19-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 10522 // CHECK19: omp.inner.for.body: 10523 // CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 10524 // CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 10525 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 10526 // CHECK19-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !22 10527 // CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !22 10528 // CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 10529 // CHECK19-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4, !llvm.access.group !22 10530 // CHECK19-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !22 10531 // CHECK19-NEXT: [[CONV3:%.*]] = sext i16 [[TMP9]] to i32 10532 // CHECK19-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 10533 // CHECK19-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 10534 // CHECK19-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2, !llvm.access.group !22 10535 // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 10536 // CHECK19: omp.body.continue: 10537 // CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 10538 // CHECK19: omp.inner.for.inc: 10539 // CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 10540 // CHECK19-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP10]], 1 10541 // CHECK19-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 10542 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]] 10543 // CHECK19: omp.inner.for.end: 10544 // CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 10545 // CHECK19: omp.loop.exit: 10546 // CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 10547 // CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 10548 // CHECK19-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 10549 // CHECK19-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 10550 // CHECK19: .omp.final.then: 10551 // CHECK19-NEXT: store i32 10, i32* [[I]], align 4 10552 // CHECK19-NEXT: br label [[DOTOMP_FINAL_DONE]] 10553 // CHECK19: .omp.final.done: 10554 // CHECK19-NEXT: ret void 10555 // 10556 // 10557 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142 10558 // CHECK19-SAME: (i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] { 10559 // CHECK19-NEXT: entry: 10560 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 10561 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 10562 // CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 10563 // CHECK19-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 10564 // CHECK19-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 10565 // CHECK19-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 10566 // CHECK19-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 10567 // CHECK19-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 10568 // CHECK19-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 10569 // CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 10570 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 10571 // CHECK19-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 10572 // CHECK19-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 10573 // CHECK19-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 10574 // CHECK19-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 10575 // CHECK19-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 10576 // CHECK19-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 10577 // CHECK19-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 10578 // CHECK19-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 10579 // CHECK19-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 10580 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 10581 // CHECK19-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 10582 // CHECK19-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 10583 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 10584 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 10585 // CHECK19-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 10586 // CHECK19-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 10587 // CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 10588 // CHECK19-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4 10589 // CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4 10590 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) 10591 // CHECK19-NEXT: ret void 10592 // 10593 // 10594 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..3 10595 // CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR1]] { 10596 // CHECK19-NEXT: entry: 10597 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 10598 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 10599 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 10600 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 10601 // CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 10602 // CHECK19-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 10603 // CHECK19-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 10604 // CHECK19-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 10605 // CHECK19-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 10606 // CHECK19-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 10607 // CHECK19-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 10608 // CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 10609 // CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4 10610 // CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 10611 // CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 10612 // CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 10613 // CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 10614 // CHECK19-NEXT: [[I:%.*]] = alloca i32, align 4 10615 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 10616 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 10617 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 10618 // CHECK19-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 10619 // CHECK19-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 10620 // CHECK19-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 10621 // CHECK19-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 10622 // CHECK19-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 10623 // CHECK19-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 10624 // CHECK19-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 10625 // CHECK19-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 10626 // CHECK19-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 10627 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 10628 // CHECK19-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 10629 // CHECK19-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 10630 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 10631 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 10632 // CHECK19-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 10633 // CHECK19-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 10634 // CHECK19-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 0 10635 // CHECK19-NEXT: call void @llvm.assume(i1 true) [ "align"(float* [[ARRAYDECAY]], i32 16) ] 10636 // CHECK19-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 10637 // CHECK19-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 10638 // CHECK19-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 10639 // CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 10640 // CHECK19-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 10641 // CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 10642 // CHECK19-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 10643 // CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 10644 // CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP10]], 9 10645 // CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 10646 // CHECK19: cond.true: 10647 // CHECK19-NEXT: br label [[COND_END:%.*]] 10648 // CHECK19: cond.false: 10649 // CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 10650 // CHECK19-NEXT: br label [[COND_END]] 10651 // CHECK19: cond.end: 10652 // CHECK19-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] 10653 // CHECK19-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 10654 // CHECK19-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 10655 // CHECK19-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 10656 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 10657 // CHECK19: omp.inner.for.cond: 10658 // CHECK19-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25 10659 // CHECK19-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !25 10660 // CHECK19-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] 10661 // CHECK19-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 10662 // CHECK19: omp.inner.for.body: 10663 // CHECK19-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25 10664 // CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 10665 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 10666 // CHECK19-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !25 10667 // CHECK19-NEXT: [[TMP16:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !25 10668 // CHECK19-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP16]], 1 10669 // CHECK19-NEXT: store i32 [[ADD6]], i32* [[A_ADDR]], align 4, !llvm.access.group !25 10670 // CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2 10671 // CHECK19-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !25 10672 // CHECK19-NEXT: [[CONV:%.*]] = fpext float [[TMP17]] to double 10673 // CHECK19-NEXT: [[ADD7:%.*]] = fadd double [[CONV]], 1.000000e+00 10674 // CHECK19-NEXT: [[CONV8:%.*]] = fptrunc double [[ADD7]] to float 10675 // CHECK19-NEXT: store float [[CONV8]], float* [[ARRAYIDX]], align 4, !llvm.access.group !25 10676 // CHECK19-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3 10677 // CHECK19-NEXT: [[TMP18:%.*]] = load float, float* [[ARRAYIDX9]], align 4, !llvm.access.group !25 10678 // CHECK19-NEXT: [[CONV10:%.*]] = fpext float [[TMP18]] to double 10679 // CHECK19-NEXT: [[ADD11:%.*]] = fadd double [[CONV10]], 1.000000e+00 10680 // CHECK19-NEXT: [[CONV12:%.*]] = fptrunc double [[ADD11]] to float 10681 // CHECK19-NEXT: store float [[CONV12]], float* [[ARRAYIDX9]], align 4, !llvm.access.group !25 10682 // CHECK19-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1 10683 // CHECK19-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX13]], i32 0, i32 2 10684 // CHECK19-NEXT: [[TMP19:%.*]] = load double, double* [[ARRAYIDX14]], align 8, !llvm.access.group !25 10685 // CHECK19-NEXT: [[ADD15:%.*]] = fadd double [[TMP19]], 1.000000e+00 10686 // CHECK19-NEXT: store double [[ADD15]], double* [[ARRAYIDX14]], align 8, !llvm.access.group !25 10687 // CHECK19-NEXT: [[TMP20:%.*]] = mul nsw i32 1, [[TMP5]] 10688 // CHECK19-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP20]] 10689 // CHECK19-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX16]], i32 3 10690 // CHECK19-NEXT: [[TMP21:%.*]] = load double, double* [[ARRAYIDX17]], align 8, !llvm.access.group !25 10691 // CHECK19-NEXT: [[ADD18:%.*]] = fadd double [[TMP21]], 1.000000e+00 10692 // CHECK19-NEXT: store double [[ADD18]], double* [[ARRAYIDX17]], align 8, !llvm.access.group !25 10693 // CHECK19-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 10694 // CHECK19-NEXT: [[TMP22:%.*]] = load i64, i64* [[X]], align 4, !llvm.access.group !25 10695 // CHECK19-NEXT: [[ADD19:%.*]] = add nsw i64 [[TMP22]], 1 10696 // CHECK19-NEXT: store i64 [[ADD19]], i64* [[X]], align 4, !llvm.access.group !25 10697 // CHECK19-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 10698 // CHECK19-NEXT: [[TMP23:%.*]] = load i8, i8* [[Y]], align 4, !llvm.access.group !25 10699 // CHECK19-NEXT: [[CONV20:%.*]] = sext i8 [[TMP23]] to i32 10700 // CHECK19-NEXT: [[ADD21:%.*]] = add nsw i32 [[CONV20]], 1 10701 // CHECK19-NEXT: [[CONV22:%.*]] = trunc i32 [[ADD21]] to i8 10702 // CHECK19-NEXT: store i8 [[CONV22]], i8* [[Y]], align 4, !llvm.access.group !25 10703 // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 10704 // CHECK19: omp.body.continue: 10705 // CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 10706 // CHECK19: omp.inner.for.inc: 10707 // CHECK19-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25 10708 // CHECK19-NEXT: [[ADD23:%.*]] = add nsw i32 [[TMP24]], 1 10709 // CHECK19-NEXT: store i32 [[ADD23]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25 10710 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP26:![0-9]+]] 10711 // CHECK19: omp.inner.for.end: 10712 // CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 10713 // CHECK19: omp.loop.exit: 10714 // CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]]) 10715 // CHECK19-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 10716 // CHECK19-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0 10717 // CHECK19-NEXT: br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 10718 // CHECK19: .omp.final.then: 10719 // CHECK19-NEXT: store i32 10, i32* [[I]], align 4 10720 // CHECK19-NEXT: br label [[DOTOMP_FINAL_DONE]] 10721 // CHECK19: .omp.final.done: 10722 // CHECK19-NEXT: ret void 10723 // 10724 // 10725 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197 10726 // CHECK19-SAME: (i32 noundef [[A:%.*]], i32 noundef [[N:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 10727 // CHECK19-NEXT: entry: 10728 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 10729 // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 10730 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 10731 // CHECK19-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 10732 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 10733 // CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 10734 // CHECK19-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 10735 // CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 10736 // CHECK19-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 10737 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 10738 // CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 10739 // CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 10740 // CHECK19-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 10741 // CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 10742 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 10743 // CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 10744 // CHECK19-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 10745 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 10746 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 10747 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 10748 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 10749 // CHECK19-NEXT: store i32 [[TMP3]], i32* [[N_CASTED]], align 4 10750 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_CASTED]], align 4 10751 // CHECK19-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 2 10752 // CHECK19-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 10753 // CHECK19-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2 10754 // CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[AA_CASTED]], align 4 10755 // CHECK19-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV1]], align 1 10756 // CHECK19-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* 10757 // CHECK19-NEXT: store i8 [[TMP7]], i8* [[CONV3]], align 1 10758 // CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 10759 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP8]], [10 x i32]* [[TMP0]]) 10760 // CHECK19-NEXT: ret void 10761 // 10762 // 10763 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..4 10764 // CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[N:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { 10765 // CHECK19-NEXT: entry: 10766 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 10767 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 10768 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 10769 // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 10770 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 10771 // CHECK19-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 10772 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 10773 // CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 10774 // CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4 10775 // CHECK19-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 10776 // CHECK19-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 10777 // CHECK19-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4 10778 // CHECK19-NEXT: [[I:%.*]] = alloca i32, align 4 10779 // CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 10780 // CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 10781 // CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 10782 // CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 10783 // CHECK19-NEXT: [[I6:%.*]] = alloca i32, align 4 10784 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 10785 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 10786 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 10787 // CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 10788 // CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 10789 // CHECK19-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 10790 // CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 10791 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 10792 // CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 10793 // CHECK19-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 10794 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 10795 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 10796 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 10797 // CHECK19-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4 10798 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 10799 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 10800 // CHECK19-NEXT: [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]] 10801 // CHECK19-NEXT: [[SUB4:%.*]] = sub i32 [[SUB]], 1 10802 // CHECK19-NEXT: [[ADD:%.*]] = add i32 [[SUB4]], 1 10803 // CHECK19-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 10804 // CHECK19-NEXT: [[SUB5:%.*]] = sub i32 [[DIV]], 1 10805 // CHECK19-NEXT: store i32 [[SUB5]], i32* [[DOTCAPTURE_EXPR_3]], align 4 10806 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 10807 // CHECK19-NEXT: store i32 [[TMP5]], i32* [[I]], align 4 10808 // CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 10809 // CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 10810 // CHECK19-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]] 10811 // CHECK19-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] 10812 // CHECK19: omp.precond.then: 10813 // CHECK19-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 10814 // CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 10815 // CHECK19-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_UB]], align 4 10816 // CHECK19-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 10817 // CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 10818 // CHECK19-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 10819 // CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 10820 // CHECK19-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 10821 // CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 10822 // CHECK19-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 10823 // CHECK19-NEXT: [[CMP7:%.*]] = icmp ugt i32 [[TMP11]], [[TMP12]] 10824 // CHECK19-NEXT: br i1 [[CMP7]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 10825 // CHECK19: cond.true: 10826 // CHECK19-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 10827 // CHECK19-NEXT: br label [[COND_END:%.*]] 10828 // CHECK19: cond.false: 10829 // CHECK19-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 10830 // CHECK19-NEXT: br label [[COND_END]] 10831 // CHECK19: cond.end: 10832 // CHECK19-NEXT: [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ] 10833 // CHECK19-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 10834 // CHECK19-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 10835 // CHECK19-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4 10836 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 10837 // CHECK19: omp.inner.for.cond: 10838 // CHECK19-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28 10839 // CHECK19-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !28 10840 // CHECK19-NEXT: [[ADD8:%.*]] = add i32 [[TMP17]], 1 10841 // CHECK19-NEXT: [[CMP9:%.*]] = icmp ult i32 [[TMP16]], [[ADD8]] 10842 // CHECK19-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 10843 // CHECK19: omp.inner.for.body: 10844 // CHECK19-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group !28 10845 // CHECK19-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28 10846 // CHECK19-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 1 10847 // CHECK19-NEXT: [[ADD10:%.*]] = add i32 [[TMP18]], [[MUL]] 10848 // CHECK19-NEXT: store i32 [[ADD10]], i32* [[I6]], align 4, !llvm.access.group !28 10849 // CHECK19-NEXT: [[TMP20:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !28 10850 // CHECK19-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP20]], 1 10851 // CHECK19-NEXT: store i32 [[ADD11]], i32* [[A_ADDR]], align 4, !llvm.access.group !28 10852 // CHECK19-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !28 10853 // CHECK19-NEXT: [[CONV12:%.*]] = sext i16 [[TMP21]] to i32 10854 // CHECK19-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1 10855 // CHECK19-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16 10856 // CHECK19-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 2, !llvm.access.group !28 10857 // CHECK19-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV1]], align 1, !llvm.access.group !28 10858 // CHECK19-NEXT: [[CONV15:%.*]] = sext i8 [[TMP22]] to i32 10859 // CHECK19-NEXT: [[ADD16:%.*]] = add nsw i32 [[CONV15]], 1 10860 // CHECK19-NEXT: [[CONV17:%.*]] = trunc i32 [[ADD16]] to i8 10861 // CHECK19-NEXT: store i8 [[CONV17]], i8* [[CONV1]], align 1, !llvm.access.group !28 10862 // CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 10863 // CHECK19-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !28 10864 // CHECK19-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP23]], 1 10865 // CHECK19-NEXT: store i32 [[ADD18]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !28 10866 // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 10867 // CHECK19: omp.body.continue: 10868 // CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 10869 // CHECK19: omp.inner.for.inc: 10870 // CHECK19-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28 10871 // CHECK19-NEXT: [[ADD19:%.*]] = add i32 [[TMP24]], 1 10872 // CHECK19-NEXT: store i32 [[ADD19]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28 10873 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP29:![0-9]+]] 10874 // CHECK19: omp.inner.for.end: 10875 // CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 10876 // CHECK19: omp.loop.exit: 10877 // CHECK19-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 10878 // CHECK19-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 10879 // CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) 10880 // CHECK19-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 10881 // CHECK19-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0 10882 // CHECK19-NEXT: br i1 [[TMP28]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 10883 // CHECK19: .omp.final.then: 10884 // CHECK19-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 10885 // CHECK19-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 10886 // CHECK19-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 10887 // CHECK19-NEXT: [[SUB20:%.*]] = sub i32 [[TMP30]], [[TMP31]] 10888 // CHECK19-NEXT: [[SUB21:%.*]] = sub i32 [[SUB20]], 1 10889 // CHECK19-NEXT: [[ADD22:%.*]] = add i32 [[SUB21]], 1 10890 // CHECK19-NEXT: [[DIV23:%.*]] = udiv i32 [[ADD22]], 1 10891 // CHECK19-NEXT: [[MUL24:%.*]] = mul i32 [[DIV23]], 1 10892 // CHECK19-NEXT: [[ADD25:%.*]] = add i32 [[TMP29]], [[MUL24]] 10893 // CHECK19-NEXT: store i32 [[ADD25]], i32* [[I6]], align 4 10894 // CHECK19-NEXT: br label [[DOTOMP_FINAL_DONE]] 10895 // CHECK19: .omp.final.done: 10896 // CHECK19-NEXT: br label [[OMP_PRECOND_END]] 10897 // CHECK19: omp.precond.end: 10898 // CHECK19-NEXT: ret void 10899 // 10900 // 10901 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215 10902 // CHECK19-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { 10903 // CHECK19-NEXT: entry: 10904 // CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 10905 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 10906 // CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 10907 // CHECK19-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 10908 // CHECK19-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 10909 // CHECK19-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 10910 // CHECK19-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 10911 // CHECK19-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 10912 // CHECK19-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 10913 // CHECK19-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 10914 // CHECK19-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 10915 // CHECK19-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 10916 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 10917 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 10918 // CHECK19-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 10919 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 10920 // CHECK19-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 10921 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 10922 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]]) 10923 // CHECK19-NEXT: ret void 10924 // 10925 // 10926 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..5 10927 // CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] { 10928 // CHECK19-NEXT: entry: 10929 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 10930 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 10931 // CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 10932 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 10933 // CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 10934 // CHECK19-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 10935 // CHECK19-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 10936 // CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 10937 // CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4 10938 // CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 10939 // CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 10940 // CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 10941 // CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 10942 // CHECK19-NEXT: [[I:%.*]] = alloca i32, align 4 10943 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 10944 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 10945 // CHECK19-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 10946 // CHECK19-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 10947 // CHECK19-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 10948 // CHECK19-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 10949 // CHECK19-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 10950 // CHECK19-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 10951 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 10952 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 10953 // CHECK19-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 10954 // CHECK19-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 10955 // CHECK19-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 10956 // CHECK19-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 10957 // CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 10958 // CHECK19-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 10959 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 10960 // CHECK19-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 10961 // CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 10962 // CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 9 10963 // CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 10964 // CHECK19: cond.true: 10965 // CHECK19-NEXT: br label [[COND_END:%.*]] 10966 // CHECK19: cond.false: 10967 // CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 10968 // CHECK19-NEXT: br label [[COND_END]] 10969 // CHECK19: cond.end: 10970 // CHECK19-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 10971 // CHECK19-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 10972 // CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 10973 // CHECK19-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 10974 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 10975 // CHECK19: omp.inner.for.cond: 10976 // CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !31 10977 // CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !31 10978 // CHECK19-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 10979 // CHECK19-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 10980 // CHECK19: omp.inner.for.body: 10981 // CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !31 10982 // CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 10983 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 10984 // CHECK19-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !31 10985 // CHECK19-NEXT: [[TMP12:%.*]] = load i32, i32* [[B_ADDR]], align 4, !llvm.access.group !31 10986 // CHECK19-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP12]] to double 10987 // CHECK19-NEXT: [[ADD4:%.*]] = fadd double [[CONV]], 1.500000e+00 10988 // CHECK19-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 10989 // CHECK19-NEXT: store double [[ADD4]], double* [[A]], align 4, !llvm.access.group !31 10990 // CHECK19-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 10991 // CHECK19-NEXT: [[TMP13:%.*]] = load double, double* [[A5]], align 4, !llvm.access.group !31 10992 // CHECK19-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 10993 // CHECK19-NEXT: store double [[INC]], double* [[A5]], align 4, !llvm.access.group !31 10994 // CHECK19-NEXT: [[CONV6:%.*]] = fptosi double [[INC]] to i16 10995 // CHECK19-NEXT: [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]] 10996 // CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP14]] 10997 // CHECK19-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 10998 // CHECK19-NEXT: store i16 [[CONV6]], i16* [[ARRAYIDX7]], align 2, !llvm.access.group !31 10999 // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 11000 // CHECK19: omp.body.continue: 11001 // CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 11002 // CHECK19: omp.inner.for.inc: 11003 // CHECK19-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !31 11004 // CHECK19-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP15]], 1 11005 // CHECK19-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !31 11006 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP32:![0-9]+]] 11007 // CHECK19: omp.inner.for.end: 11008 // CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 11009 // CHECK19: omp.loop.exit: 11010 // CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 11011 // CHECK19-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 11012 // CHECK19-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0 11013 // CHECK19-NEXT: br i1 [[TMP17]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 11014 // CHECK19: .omp.final.then: 11015 // CHECK19-NEXT: store i32 10, i32* [[I]], align 4 11016 // CHECK19-NEXT: br label [[DOTOMP_FINAL_DONE]] 11017 // CHECK19: .omp.final.done: 11018 // CHECK19-NEXT: ret void 11019 // 11020 // 11021 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180 11022 // CHECK19-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 11023 // CHECK19-NEXT: entry: 11024 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 11025 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 11026 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 11027 // CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 11028 // CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 11029 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 11030 // CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 11031 // CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 11032 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 11033 // CHECK19-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 11034 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 11035 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 11036 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 11037 // CHECK19-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 11038 // CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 11039 // CHECK19-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 11040 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 11041 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) 11042 // CHECK19-NEXT: ret void 11043 // 11044 // 11045 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..6 11046 // CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { 11047 // CHECK19-NEXT: entry: 11048 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 11049 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 11050 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 11051 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 11052 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 11053 // CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 11054 // CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4 11055 // CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 11056 // CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 11057 // CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 11058 // CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 11059 // CHECK19-NEXT: [[I:%.*]] = alloca i32, align 4 11060 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 11061 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 11062 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 11063 // CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 11064 // CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 11065 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 11066 // CHECK19-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 11067 // CHECK19-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 11068 // CHECK19-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 11069 // CHECK19-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 11070 // CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 11071 // CHECK19-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 11072 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 11073 // CHECK19-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 11074 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 11075 // CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 11076 // CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 11077 // CHECK19: cond.true: 11078 // CHECK19-NEXT: br label [[COND_END:%.*]] 11079 // CHECK19: cond.false: 11080 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 11081 // CHECK19-NEXT: br label [[COND_END]] 11082 // CHECK19: cond.end: 11083 // CHECK19-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 11084 // CHECK19-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 11085 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 11086 // CHECK19-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 11087 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 11088 // CHECK19: omp.inner.for.cond: 11089 // CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !34 11090 // CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !34 11091 // CHECK19-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] 11092 // CHECK19-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 11093 // CHECK19: omp.inner.for.body: 11094 // CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !34 11095 // CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 11096 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 11097 // CHECK19-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !34 11098 // CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !34 11099 // CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 11100 // CHECK19-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4, !llvm.access.group !34 11101 // CHECK19-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !34 11102 // CHECK19-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32 11103 // CHECK19-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 11104 // CHECK19-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 11105 // CHECK19-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2, !llvm.access.group !34 11106 // CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 11107 // CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !34 11108 // CHECK19-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1 11109 // CHECK19-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !34 11110 // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 11111 // CHECK19: omp.body.continue: 11112 // CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 11113 // CHECK19: omp.inner.for.inc: 11114 // CHECK19-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !34 11115 // CHECK19-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP12]], 1 11116 // CHECK19-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !34 11117 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP35:![0-9]+]] 11118 // CHECK19: omp.inner.for.end: 11119 // CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 11120 // CHECK19: omp.loop.exit: 11121 // CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) 11122 // CHECK19-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 11123 // CHECK19-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 11124 // CHECK19-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 11125 // CHECK19: .omp.final.then: 11126 // CHECK19-NEXT: store i32 10, i32* [[I]], align 4 11127 // CHECK19-NEXT: br label [[DOTOMP_FINAL_DONE]] 11128 // CHECK19: .omp.final.done: 11129 // CHECK19-NEXT: ret void 11130 // 11131 // 11132 // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97 11133 // CHECK21-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { 11134 // CHECK21-NEXT: entry: 11135 // CHECK21-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 11136 // CHECK21-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 11137 // CHECK21-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8 11138 // CHECK21-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 11139 // CHECK21-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) 11140 // CHECK21-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 11141 // CHECK21-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 11142 // CHECK21-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8 11143 // CHECK21-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 11144 // CHECK21-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* 11145 // CHECK21-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32* 11146 // CHECK21-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 4 11147 // CHECK21-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 4 11148 // CHECK21-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) 11149 // CHECK21-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 11150 // CHECK21-NEXT: [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 11151 // CHECK21-NEXT: store i16 [[TMP3]], i16* [[CONV5]], align 2 11152 // CHECK21-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 11153 // CHECK21-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]]) 11154 // CHECK21-NEXT: ret void 11155 // 11156 // 11157 // CHECK21-LABEL: define {{[^@]+}}@.omp_outlined. 11158 // CHECK21-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR1:[0-9]+]] { 11159 // CHECK21-NEXT: entry: 11160 // CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 11161 // CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 11162 // CHECK21-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 11163 // CHECK21-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 11164 // CHECK21-NEXT: [[TMP:%.*]] = alloca i32, align 4 11165 // CHECK21-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 11166 // CHECK21-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 11167 // CHECK21-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 11168 // CHECK21-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 11169 // CHECK21-NEXT: [[I:%.*]] = alloca i32, align 4 11170 // CHECK21-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 11171 // CHECK21-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 11172 // CHECK21-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 11173 // CHECK21-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 11174 // CHECK21-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 11175 // CHECK21-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 11176 // CHECK21-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 11177 // CHECK21-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 11178 // CHECK21-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 11179 // CHECK21-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 11180 // CHECK21-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 11181 // CHECK21-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 11182 // CHECK21-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 11183 // CHECK21-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 11184 // CHECK21: cond.true: 11185 // CHECK21-NEXT: br label [[COND_END:%.*]] 11186 // CHECK21: cond.false: 11187 // CHECK21-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 11188 // CHECK21-NEXT: br label [[COND_END]] 11189 // CHECK21: cond.end: 11190 // CHECK21-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 11191 // CHECK21-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 11192 // CHECK21-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 11193 // CHECK21-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 11194 // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 11195 // CHECK21: omp.inner.for.cond: 11196 // CHECK21-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 11197 // CHECK21-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !11 11198 // CHECK21-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 11199 // CHECK21-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 11200 // CHECK21: omp.inner.for.body: 11201 // CHECK21-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 11202 // CHECK21-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 11203 // CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 11204 // CHECK21-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11 11205 // CHECK21-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 11206 // CHECK21: omp.body.continue: 11207 // CHECK21-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 11208 // CHECK21: omp.inner.for.inc: 11209 // CHECK21-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 11210 // CHECK21-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 11211 // CHECK21-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 11212 // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] 11213 // CHECK21: omp.inner.for.end: 11214 // CHECK21-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 11215 // CHECK21: omp.loop.exit: 11216 // CHECK21-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 11217 // CHECK21-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 11218 // CHECK21-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 11219 // CHECK21-NEXT: br i1 [[TMP10]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 11220 // CHECK21: .omp.final.then: 11221 // CHECK21-NEXT: store i32 10, i32* [[I]], align 4 11222 // CHECK21-NEXT: br label [[DOTOMP_FINAL_DONE]] 11223 // CHECK21: .omp.final.done: 11224 // CHECK21-NEXT: ret void 11225 // 11226 // 11227 // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 11228 // CHECK21-SAME: (i64 noundef [[AA:%.*]]) #[[ATTR0]] { 11229 // CHECK21-NEXT: entry: 11230 // CHECK21-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 11231 // CHECK21-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 11232 // CHECK21-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 11233 // CHECK21-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 11234 // CHECK21-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 11235 // CHECK21-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 11236 // CHECK21-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 11237 // CHECK21-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 11238 // CHECK21-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]]) 11239 // CHECK21-NEXT: ret void 11240 // 11241 // 11242 // CHECK21-LABEL: define {{[^@]+}}@.omp_outlined..1 11243 // CHECK21-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR1]] { 11244 // CHECK21-NEXT: entry: 11245 // CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 11246 // CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 11247 // CHECK21-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 11248 // CHECK21-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 11249 // CHECK21-NEXT: [[TMP:%.*]] = alloca i32, align 4 11250 // CHECK21-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 11251 // CHECK21-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 11252 // CHECK21-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 11253 // CHECK21-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 11254 // CHECK21-NEXT: [[I:%.*]] = alloca i32, align 4 11255 // CHECK21-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 11256 // CHECK21-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 11257 // CHECK21-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 11258 // CHECK21-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 11259 // CHECK21-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 11260 // CHECK21-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 11261 // CHECK21-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 11262 // CHECK21-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 11263 // CHECK21-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 11264 // CHECK21-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 11265 // CHECK21-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 11266 // CHECK21-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 11267 // CHECK21-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 11268 // CHECK21-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 11269 // CHECK21: cond.true: 11270 // CHECK21-NEXT: br label [[COND_END:%.*]] 11271 // CHECK21: cond.false: 11272 // CHECK21-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 11273 // CHECK21-NEXT: br label [[COND_END]] 11274 // CHECK21: cond.end: 11275 // CHECK21-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 11276 // CHECK21-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 11277 // CHECK21-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 11278 // CHECK21-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 11279 // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 11280 // CHECK21: omp.inner.for.cond: 11281 // CHECK21-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 11282 // CHECK21-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !18 11283 // CHECK21-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 11284 // CHECK21-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 11285 // CHECK21: omp.inner.for.body: 11286 // CHECK21-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 11287 // CHECK21-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 11288 // CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 11289 // CHECK21-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18 11290 // CHECK21-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !18 11291 // CHECK21-NEXT: [[CONV2:%.*]] = sext i16 [[TMP8]] to i32 11292 // CHECK21-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 11293 // CHECK21-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 11294 // CHECK21-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2, !llvm.access.group !18 11295 // CHECK21-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 11296 // CHECK21: omp.body.continue: 11297 // CHECK21-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 11298 // CHECK21: omp.inner.for.inc: 11299 // CHECK21-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 11300 // CHECK21-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP9]], 1 11301 // CHECK21-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18 11302 // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] 11303 // CHECK21: omp.inner.for.end: 11304 // CHECK21-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 11305 // CHECK21: omp.loop.exit: 11306 // CHECK21-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 11307 // CHECK21-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 11308 // CHECK21-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0 11309 // CHECK21-NEXT: br i1 [[TMP11]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 11310 // CHECK21: .omp.final.then: 11311 // CHECK21-NEXT: store i32 10, i32* [[I]], align 4 11312 // CHECK21-NEXT: br label [[DOTOMP_FINAL_DONE]] 11313 // CHECK21: .omp.final.done: 11314 // CHECK21-NEXT: ret void 11315 // 11316 // 11317 // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118 11318 // CHECK21-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { 11319 // CHECK21-NEXT: entry: 11320 // CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 11321 // CHECK21-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 11322 // CHECK21-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 11323 // CHECK21-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 11324 // CHECK21-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 11325 // CHECK21-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 11326 // CHECK21-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 11327 // CHECK21-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 11328 // CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 11329 // CHECK21-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* 11330 // CHECK21-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 11331 // CHECK21-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 11332 // CHECK21-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 11333 // CHECK21-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 11334 // CHECK21-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 11335 // CHECK21-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 11336 // CHECK21-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) 11337 // CHECK21-NEXT: ret void 11338 // 11339 // 11340 // CHECK21-LABEL: define {{[^@]+}}@.omp_outlined..2 11341 // CHECK21-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR1]] { 11342 // CHECK21-NEXT: entry: 11343 // CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 11344 // CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 11345 // CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 11346 // CHECK21-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 11347 // CHECK21-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 11348 // CHECK21-NEXT: [[TMP:%.*]] = alloca i32, align 4 11349 // CHECK21-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 11350 // CHECK21-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 11351 // CHECK21-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 11352 // CHECK21-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 11353 // CHECK21-NEXT: [[I:%.*]] = alloca i32, align 4 11354 // CHECK21-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 11355 // CHECK21-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 11356 // CHECK21-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 11357 // CHECK21-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 11358 // CHECK21-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 11359 // CHECK21-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 11360 // CHECK21-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 11361 // CHECK21-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 11362 // CHECK21-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 11363 // CHECK21-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 11364 // CHECK21-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 11365 // CHECK21-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 11366 // CHECK21-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 11367 // CHECK21-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 11368 // CHECK21-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 11369 // CHECK21-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 11370 // CHECK21: cond.true: 11371 // CHECK21-NEXT: br label [[COND_END:%.*]] 11372 // CHECK21: cond.false: 11373 // CHECK21-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 11374 // CHECK21-NEXT: br label [[COND_END]] 11375 // CHECK21: cond.end: 11376 // CHECK21-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 11377 // CHECK21-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 11378 // CHECK21-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 11379 // CHECK21-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 11380 // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 11381 // CHECK21: omp.inner.for.cond: 11382 // CHECK21-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 11383 // CHECK21-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !21 11384 // CHECK21-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 11385 // CHECK21-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 11386 // CHECK21: omp.inner.for.body: 11387 // CHECK21-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 11388 // CHECK21-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 11389 // CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 11390 // CHECK21-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !21 11391 // CHECK21-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !21 11392 // CHECK21-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1 11393 // CHECK21-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4, !llvm.access.group !21 11394 // CHECK21-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 2, !llvm.access.group !21 11395 // CHECK21-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32 11396 // CHECK21-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 11397 // CHECK21-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 11398 // CHECK21-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2, !llvm.access.group !21 11399 // CHECK21-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 11400 // CHECK21: omp.body.continue: 11401 // CHECK21-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 11402 // CHECK21: omp.inner.for.inc: 11403 // CHECK21-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 11404 // CHECK21-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1 11405 // CHECK21-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 11406 // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]] 11407 // CHECK21: omp.inner.for.end: 11408 // CHECK21-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 11409 // CHECK21: omp.loop.exit: 11410 // CHECK21-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 11411 // CHECK21-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 11412 // CHECK21-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 11413 // CHECK21-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 11414 // CHECK21: .omp.final.then: 11415 // CHECK21-NEXT: store i32 10, i32* [[I]], align 4 11416 // CHECK21-NEXT: br label [[DOTOMP_FINAL_DONE]] 11417 // CHECK21: .omp.final.done: 11418 // CHECK21-NEXT: ret void 11419 // 11420 // 11421 // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142 11422 // CHECK21-SAME: (i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] { 11423 // CHECK21-NEXT: entry: 11424 // CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 11425 // CHECK21-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 11426 // CHECK21-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 11427 // CHECK21-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 11428 // CHECK21-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 11429 // CHECK21-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 11430 // CHECK21-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 11431 // CHECK21-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 11432 // CHECK21-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 11433 // CHECK21-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 11434 // CHECK21-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 11435 // CHECK21-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 11436 // CHECK21-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 11437 // CHECK21-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 11438 // CHECK21-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 11439 // CHECK21-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 11440 // CHECK21-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 11441 // CHECK21-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 11442 // CHECK21-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 11443 // CHECK21-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 11444 // CHECK21-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 11445 // CHECK21-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 11446 // CHECK21-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 11447 // CHECK21-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 11448 // CHECK21-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 11449 // CHECK21-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 11450 // CHECK21-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 11451 // CHECK21-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 11452 // CHECK21-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 11453 // CHECK21-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* 11454 // CHECK21-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4 11455 // CHECK21-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 11456 // CHECK21-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) 11457 // CHECK21-NEXT: ret void 11458 // 11459 // 11460 // CHECK21-LABEL: define {{[^@]+}}@.omp_outlined..3 11461 // CHECK21-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR1]] { 11462 // CHECK21-NEXT: entry: 11463 // CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 11464 // CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 11465 // CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 11466 // CHECK21-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 11467 // CHECK21-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 11468 // CHECK21-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 11469 // CHECK21-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 11470 // CHECK21-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 11471 // CHECK21-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 11472 // CHECK21-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 11473 // CHECK21-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 11474 // CHECK21-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 11475 // CHECK21-NEXT: [[TMP:%.*]] = alloca i32, align 4 11476 // CHECK21-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 11477 // CHECK21-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 11478 // CHECK21-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 11479 // CHECK21-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 11480 // CHECK21-NEXT: [[I:%.*]] = alloca i32, align 4 11481 // CHECK21-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 11482 // CHECK21-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 11483 // CHECK21-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 11484 // CHECK21-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 11485 // CHECK21-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 11486 // CHECK21-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 11487 // CHECK21-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 11488 // CHECK21-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 11489 // CHECK21-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 11490 // CHECK21-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 11491 // CHECK21-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 11492 // CHECK21-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 11493 // CHECK21-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 11494 // CHECK21-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 11495 // CHECK21-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 11496 // CHECK21-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 11497 // CHECK21-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 11498 // CHECK21-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 11499 // CHECK21-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 11500 // CHECK21-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 11501 // CHECK21-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 0 11502 // CHECK21-NEXT: call void @llvm.assume(i1 true) [ "align"(float* [[ARRAYDECAY]], i64 16) ] 11503 // CHECK21-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 11504 // CHECK21-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 11505 // CHECK21-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 11506 // CHECK21-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 11507 // CHECK21-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 11508 // CHECK21-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 11509 // CHECK21-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 11510 // CHECK21-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 11511 // CHECK21-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP10]], 9 11512 // CHECK21-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 11513 // CHECK21: cond.true: 11514 // CHECK21-NEXT: br label [[COND_END:%.*]] 11515 // CHECK21: cond.false: 11516 // CHECK21-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 11517 // CHECK21-NEXT: br label [[COND_END]] 11518 // CHECK21: cond.end: 11519 // CHECK21-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] 11520 // CHECK21-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 11521 // CHECK21-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 11522 // CHECK21-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 11523 // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 11524 // CHECK21: omp.inner.for.cond: 11525 // CHECK21-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 11526 // CHECK21-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !24 11527 // CHECK21-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] 11528 // CHECK21-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 11529 // CHECK21: omp.inner.for.body: 11530 // CHECK21-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 11531 // CHECK21-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 11532 // CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 11533 // CHECK21-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !24 11534 // CHECK21-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !24 11535 // CHECK21-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP16]], 1 11536 // CHECK21-NEXT: store i32 [[ADD6]], i32* [[CONV]], align 4, !llvm.access.group !24 11537 // CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 11538 // CHECK21-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !24 11539 // CHECK21-NEXT: [[CONV7:%.*]] = fpext float [[TMP17]] to double 11540 // CHECK21-NEXT: [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00 11541 // CHECK21-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float 11542 // CHECK21-NEXT: store float [[CONV9]], float* [[ARRAYIDX]], align 4, !llvm.access.group !24 11543 // CHECK21-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 11544 // CHECK21-NEXT: [[TMP18:%.*]] = load float, float* [[ARRAYIDX10]], align 4, !llvm.access.group !24 11545 // CHECK21-NEXT: [[CONV11:%.*]] = fpext float [[TMP18]] to double 11546 // CHECK21-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00 11547 // CHECK21-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float 11548 // CHECK21-NEXT: store float [[CONV13]], float* [[ARRAYIDX10]], align 4, !llvm.access.group !24 11549 // CHECK21-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1 11550 // CHECK21-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX14]], i64 0, i64 2 11551 // CHECK21-NEXT: [[TMP19:%.*]] = load double, double* [[ARRAYIDX15]], align 8, !llvm.access.group !24 11552 // CHECK21-NEXT: [[ADD16:%.*]] = fadd double [[TMP19]], 1.000000e+00 11553 // CHECK21-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8, !llvm.access.group !24 11554 // CHECK21-NEXT: [[TMP20:%.*]] = mul nsw i64 1, [[TMP5]] 11555 // CHECK21-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP20]] 11556 // CHECK21-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX17]], i64 3 11557 // CHECK21-NEXT: [[TMP21:%.*]] = load double, double* [[ARRAYIDX18]], align 8, !llvm.access.group !24 11558 // CHECK21-NEXT: [[ADD19:%.*]] = fadd double [[TMP21]], 1.000000e+00 11559 // CHECK21-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8, !llvm.access.group !24 11560 // CHECK21-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 11561 // CHECK21-NEXT: [[TMP22:%.*]] = load i64, i64* [[X]], align 8, !llvm.access.group !24 11562 // CHECK21-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP22]], 1 11563 // CHECK21-NEXT: store i64 [[ADD20]], i64* [[X]], align 8, !llvm.access.group !24 11564 // CHECK21-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 11565 // CHECK21-NEXT: [[TMP23:%.*]] = load i8, i8* [[Y]], align 8, !llvm.access.group !24 11566 // CHECK21-NEXT: [[CONV21:%.*]] = sext i8 [[TMP23]] to i32 11567 // CHECK21-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1 11568 // CHECK21-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8 11569 // CHECK21-NEXT: store i8 [[CONV23]], i8* [[Y]], align 8, !llvm.access.group !24 11570 // CHECK21-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 11571 // CHECK21: omp.body.continue: 11572 // CHECK21-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 11573 // CHECK21: omp.inner.for.inc: 11574 // CHECK21-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 11575 // CHECK21-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP24]], 1 11576 // CHECK21-NEXT: store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 11577 // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]] 11578 // CHECK21: omp.inner.for.end: 11579 // CHECK21-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 11580 // CHECK21: omp.loop.exit: 11581 // CHECK21-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]]) 11582 // CHECK21-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 11583 // CHECK21-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0 11584 // CHECK21-NEXT: br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 11585 // CHECK21: .omp.final.then: 11586 // CHECK21-NEXT: store i32 10, i32* [[I]], align 4 11587 // CHECK21-NEXT: br label [[DOTOMP_FINAL_DONE]] 11588 // CHECK21: .omp.final.done: 11589 // CHECK21-NEXT: ret void 11590 // 11591 // 11592 // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197 11593 // CHECK21-SAME: (i64 noundef [[A:%.*]], i64 noundef [[N:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 11594 // CHECK21-NEXT: entry: 11595 // CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 11596 // CHECK21-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 11597 // CHECK21-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 11598 // CHECK21-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 11599 // CHECK21-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 11600 // CHECK21-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 11601 // CHECK21-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 11602 // CHECK21-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 11603 // CHECK21-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 11604 // CHECK21-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 11605 // CHECK21-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 11606 // CHECK21-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 11607 // CHECK21-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 11608 // CHECK21-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 11609 // CHECK21-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 11610 // CHECK21-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32* 11611 // CHECK21-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 11612 // CHECK21-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 11613 // CHECK21-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 11614 // CHECK21-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 11615 // CHECK21-NEXT: [[CONV4:%.*]] = bitcast i64* [[A_CASTED]] to i32* 11616 // CHECK21-NEXT: store i32 [[TMP1]], i32* [[CONV4]], align 4 11617 // CHECK21-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 11618 // CHECK21-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 4 11619 // CHECK21-NEXT: [[CONV5:%.*]] = bitcast i64* [[N_CASTED]] to i32* 11620 // CHECK21-NEXT: store i32 [[TMP3]], i32* [[CONV5]], align 4 11621 // CHECK21-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8 11622 // CHECK21-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV2]], align 2 11623 // CHECK21-NEXT: [[CONV6:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 11624 // CHECK21-NEXT: store i16 [[TMP5]], i16* [[CONV6]], align 2 11625 // CHECK21-NEXT: [[TMP6:%.*]] = load i64, i64* [[AA_CASTED]], align 8 11626 // CHECK21-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV3]], align 1 11627 // CHECK21-NEXT: [[CONV7:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* 11628 // CHECK21-NEXT: store i8 [[TMP7]], i8* [[CONV7]], align 1 11629 // CHECK21-NEXT: [[TMP8:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 11630 // CHECK21-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]], [10 x i32]* [[TMP0]]) 11631 // CHECK21-NEXT: ret void 11632 // 11633 // 11634 // CHECK21-LABEL: define {{[^@]+}}@.omp_outlined..4 11635 // CHECK21-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[N:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { 11636 // CHECK21-NEXT: entry: 11637 // CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 11638 // CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 11639 // CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 11640 // CHECK21-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 11641 // CHECK21-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 11642 // CHECK21-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 11643 // CHECK21-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 11644 // CHECK21-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 11645 // CHECK21-NEXT: [[TMP:%.*]] = alloca i32, align 4 11646 // CHECK21-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 11647 // CHECK21-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4 11648 // CHECK21-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i32, align 4 11649 // CHECK21-NEXT: [[I:%.*]] = alloca i32, align 4 11650 // CHECK21-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 11651 // CHECK21-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 11652 // CHECK21-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 11653 // CHECK21-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 11654 // CHECK21-NEXT: [[I8:%.*]] = alloca i32, align 4 11655 // CHECK21-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 11656 // CHECK21-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 11657 // CHECK21-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 11658 // CHECK21-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 11659 // CHECK21-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 11660 // CHECK21-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 11661 // CHECK21-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 11662 // CHECK21-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 11663 // CHECK21-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_ADDR]] to i32* 11664 // CHECK21-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 11665 // CHECK21-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 11666 // CHECK21-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 11667 // CHECK21-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 11668 // CHECK21-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 11669 // CHECK21-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4 11670 // CHECK21-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_4]], align 4 11671 // CHECK21-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 11672 // CHECK21-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 11673 // CHECK21-NEXT: [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]] 11674 // CHECK21-NEXT: [[SUB6:%.*]] = sub i32 [[SUB]], 1 11675 // CHECK21-NEXT: [[ADD:%.*]] = add i32 [[SUB6]], 1 11676 // CHECK21-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 11677 // CHECK21-NEXT: [[SUB7:%.*]] = sub i32 [[DIV]], 1 11678 // CHECK21-NEXT: store i32 [[SUB7]], i32* [[DOTCAPTURE_EXPR_5]], align 4 11679 // CHECK21-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 11680 // CHECK21-NEXT: store i32 [[TMP5]], i32* [[I]], align 4 11681 // CHECK21-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 11682 // CHECK21-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 11683 // CHECK21-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]] 11684 // CHECK21-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] 11685 // CHECK21: omp.precond.then: 11686 // CHECK21-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 11687 // CHECK21-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 11688 // CHECK21-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_UB]], align 4 11689 // CHECK21-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 11690 // CHECK21-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 11691 // CHECK21-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 11692 // CHECK21-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 11693 // CHECK21-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 11694 // CHECK21-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 11695 // CHECK21-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 11696 // CHECK21-NEXT: [[CMP9:%.*]] = icmp ugt i32 [[TMP11]], [[TMP12]] 11697 // CHECK21-NEXT: br i1 [[CMP9]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 11698 // CHECK21: cond.true: 11699 // CHECK21-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 11700 // CHECK21-NEXT: br label [[COND_END:%.*]] 11701 // CHECK21: cond.false: 11702 // CHECK21-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 11703 // CHECK21-NEXT: br label [[COND_END]] 11704 // CHECK21: cond.end: 11705 // CHECK21-NEXT: [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ] 11706 // CHECK21-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 11707 // CHECK21-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 11708 // CHECK21-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4 11709 // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 11710 // CHECK21: omp.inner.for.cond: 11711 // CHECK21-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 11712 // CHECK21-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !27 11713 // CHECK21-NEXT: [[ADD10:%.*]] = add i32 [[TMP17]], 1 11714 // CHECK21-NEXT: [[CMP11:%.*]] = icmp ult i32 [[TMP16]], [[ADD10]] 11715 // CHECK21-NEXT: br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 11716 // CHECK21: omp.inner.for.body: 11717 // CHECK21-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group !27 11718 // CHECK21-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 11719 // CHECK21-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 1 11720 // CHECK21-NEXT: [[ADD12:%.*]] = add i32 [[TMP18]], [[MUL]] 11721 // CHECK21-NEXT: store i32 [[ADD12]], i32* [[I8]], align 4, !llvm.access.group !27 11722 // CHECK21-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !27 11723 // CHECK21-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP20]], 1 11724 // CHECK21-NEXT: store i32 [[ADD13]], i32* [[CONV]], align 4, !llvm.access.group !27 11725 // CHECK21-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV2]], align 2, !llvm.access.group !27 11726 // CHECK21-NEXT: [[CONV14:%.*]] = sext i16 [[TMP21]] to i32 11727 // CHECK21-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1 11728 // CHECK21-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16 11729 // CHECK21-NEXT: store i16 [[CONV16]], i16* [[CONV2]], align 2, !llvm.access.group !27 11730 // CHECK21-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV3]], align 1, !llvm.access.group !27 11731 // CHECK21-NEXT: [[CONV17:%.*]] = sext i8 [[TMP22]] to i32 11732 // CHECK21-NEXT: [[ADD18:%.*]] = add nsw i32 [[CONV17]], 1 11733 // CHECK21-NEXT: [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8 11734 // CHECK21-NEXT: store i8 [[CONV19]], i8* [[CONV3]], align 1, !llvm.access.group !27 11735 // CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 11736 // CHECK21-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !27 11737 // CHECK21-NEXT: [[ADD20:%.*]] = add nsw i32 [[TMP23]], 1 11738 // CHECK21-NEXT: store i32 [[ADD20]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !27 11739 // CHECK21-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 11740 // CHECK21: omp.body.continue: 11741 // CHECK21-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 11742 // CHECK21: omp.inner.for.inc: 11743 // CHECK21-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 11744 // CHECK21-NEXT: [[ADD21:%.*]] = add i32 [[TMP24]], 1 11745 // CHECK21-NEXT: store i32 [[ADD21]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 11746 // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]] 11747 // CHECK21: omp.inner.for.end: 11748 // CHECK21-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 11749 // CHECK21: omp.loop.exit: 11750 // CHECK21-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 11751 // CHECK21-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 11752 // CHECK21-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) 11753 // CHECK21-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 11754 // CHECK21-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0 11755 // CHECK21-NEXT: br i1 [[TMP28]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 11756 // CHECK21: .omp.final.then: 11757 // CHECK21-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 11758 // CHECK21-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 11759 // CHECK21-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 11760 // CHECK21-NEXT: [[SUB22:%.*]] = sub i32 [[TMP30]], [[TMP31]] 11761 // CHECK21-NEXT: [[SUB23:%.*]] = sub i32 [[SUB22]], 1 11762 // CHECK21-NEXT: [[ADD24:%.*]] = add i32 [[SUB23]], 1 11763 // CHECK21-NEXT: [[DIV25:%.*]] = udiv i32 [[ADD24]], 1 11764 // CHECK21-NEXT: [[MUL26:%.*]] = mul i32 [[DIV25]], 1 11765 // CHECK21-NEXT: [[ADD27:%.*]] = add i32 [[TMP29]], [[MUL26]] 11766 // CHECK21-NEXT: store i32 [[ADD27]], i32* [[I8]], align 4 11767 // CHECK21-NEXT: br label [[DOTOMP_FINAL_DONE]] 11768 // CHECK21: .omp.final.done: 11769 // CHECK21-NEXT: br label [[OMP_PRECOND_END]] 11770 // CHECK21: omp.precond.end: 11771 // CHECK21-NEXT: ret void 11772 // 11773 // 11774 // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215 11775 // CHECK21-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { 11776 // CHECK21-NEXT: entry: 11777 // CHECK21-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 11778 // CHECK21-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 11779 // CHECK21-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 11780 // CHECK21-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 11781 // CHECK21-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 11782 // CHECK21-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 11783 // CHECK21-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 11784 // CHECK21-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 11785 // CHECK21-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 11786 // CHECK21-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 11787 // CHECK21-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 11788 // CHECK21-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 11789 // CHECK21-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 11790 // CHECK21-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 11791 // CHECK21-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 11792 // CHECK21-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 11793 // CHECK21-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 11794 // CHECK21-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 11795 // CHECK21-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 11796 // CHECK21-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* 11797 // CHECK21-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4 11798 // CHECK21-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i32* 11799 // CHECK21-NEXT: store i32 [[TMP4]], i32* [[CONV4]], align 4 11800 // CHECK21-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 11801 // CHECK21-NEXT: [[TMP6:%.*]] = load i8, i8* [[CONV3]], align 1 11802 // CHECK21-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP6]] to i1 11803 // CHECK21-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* 11804 // CHECK21-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 11805 // CHECK21-NEXT: store i8 [[FROMBOOL]], i8* [[CONV5]], align 1 11806 // CHECK21-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 11807 // CHECK21-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]], i64 [[TMP7]]) 11808 // CHECK21-NEXT: ret void 11809 // 11810 // 11811 // CHECK21-LABEL: define {{[^@]+}}@.omp_outlined..5 11812 // CHECK21-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { 11813 // CHECK21-NEXT: entry: 11814 // CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 11815 // CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 11816 // CHECK21-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 11817 // CHECK21-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 11818 // CHECK21-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 11819 // CHECK21-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 11820 // CHECK21-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 11821 // CHECK21-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 11822 // CHECK21-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 11823 // CHECK21-NEXT: [[TMP:%.*]] = alloca i32, align 4 11824 // CHECK21-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 11825 // CHECK21-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 11826 // CHECK21-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 11827 // CHECK21-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 11828 // CHECK21-NEXT: [[I:%.*]] = alloca i32, align 4 11829 // CHECK21-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 11830 // CHECK21-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 11831 // CHECK21-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 11832 // CHECK21-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 11833 // CHECK21-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 11834 // CHECK21-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 11835 // CHECK21-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 11836 // CHECK21-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 11837 // CHECK21-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 11838 // CHECK21-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 11839 // CHECK21-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 11840 // CHECK21-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 11841 // CHECK21-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 11842 // CHECK21-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* 11843 // CHECK21-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 11844 // CHECK21-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 11845 // CHECK21-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 11846 // CHECK21-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 11847 // CHECK21-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 11848 // CHECK21-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 11849 // CHECK21-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 11850 // CHECK21-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 11851 // CHECK21-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 9 11852 // CHECK21-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 11853 // CHECK21: cond.true: 11854 // CHECK21-NEXT: br label [[COND_END:%.*]] 11855 // CHECK21: cond.false: 11856 // CHECK21-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 11857 // CHECK21-NEXT: br label [[COND_END]] 11858 // CHECK21: cond.end: 11859 // CHECK21-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 11860 // CHECK21-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 11861 // CHECK21-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 11862 // CHECK21-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 11863 // CHECK21-NEXT: [[TMP9:%.*]] = load i8, i8* [[CONV3]], align 1 11864 // CHECK21-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP9]] to i1 11865 // CHECK21-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 11866 // CHECK21: omp_if.then: 11867 // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 11868 // CHECK21: omp.inner.for.cond: 11869 // CHECK21-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30 11870 // CHECK21-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !30 11871 // CHECK21-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]] 11872 // CHECK21-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 11873 // CHECK21: omp.inner.for.body: 11874 // CHECK21-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30 11875 // CHECK21-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1 11876 // CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 11877 // CHECK21-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !30 11878 // CHECK21-NEXT: [[TMP13:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !30 11879 // CHECK21-NEXT: [[CONV5:%.*]] = sitofp i32 [[TMP13]] to double 11880 // CHECK21-NEXT: [[ADD6:%.*]] = fadd double [[CONV5]], 1.500000e+00 11881 // CHECK21-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 11882 // CHECK21-NEXT: store double [[ADD6]], double* [[A]], align 8, !llvm.access.group !30 11883 // CHECK21-NEXT: [[A7:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 11884 // CHECK21-NEXT: [[TMP14:%.*]] = load double, double* [[A7]], align 8, !llvm.access.group !30 11885 // CHECK21-NEXT: [[INC:%.*]] = fadd double [[TMP14]], 1.000000e+00 11886 // CHECK21-NEXT: store double [[INC]], double* [[A7]], align 8, !llvm.access.group !30 11887 // CHECK21-NEXT: [[CONV8:%.*]] = fptosi double [[INC]] to i16 11888 // CHECK21-NEXT: [[TMP15:%.*]] = mul nsw i64 1, [[TMP2]] 11889 // CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP15]] 11890 // CHECK21-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 11891 // CHECK21-NEXT: store i16 [[CONV8]], i16* [[ARRAYIDX9]], align 2, !llvm.access.group !30 11892 // CHECK21-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 11893 // CHECK21: omp.body.continue: 11894 // CHECK21-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 11895 // CHECK21: omp.inner.for.inc: 11896 // CHECK21-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30 11897 // CHECK21-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP16]], 1 11898 // CHECK21-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30 11899 // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP31:![0-9]+]] 11900 // CHECK21: omp.inner.for.end: 11901 // CHECK21-NEXT: br label [[OMP_IF_END:%.*]] 11902 // CHECK21: omp_if.else: 11903 // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND11:%.*]] 11904 // CHECK21: omp.inner.for.cond11: 11905 // CHECK21-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 11906 // CHECK21-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 11907 // CHECK21-NEXT: [[CMP12:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]] 11908 // CHECK21-NEXT: br i1 [[CMP12]], label [[OMP_INNER_FOR_BODY13:%.*]], label [[OMP_INNER_FOR_END27:%.*]] 11909 // CHECK21: omp.inner.for.body13: 11910 // CHECK21-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 11911 // CHECK21-NEXT: [[MUL14:%.*]] = mul nsw i32 [[TMP19]], 1 11912 // CHECK21-NEXT: [[ADD15:%.*]] = add nsw i32 0, [[MUL14]] 11913 // CHECK21-NEXT: store i32 [[ADD15]], i32* [[I]], align 4 11914 // CHECK21-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV]], align 4 11915 // CHECK21-NEXT: [[CONV16:%.*]] = sitofp i32 [[TMP20]] to double 11916 // CHECK21-NEXT: [[ADD17:%.*]] = fadd double [[CONV16]], 1.500000e+00 11917 // CHECK21-NEXT: [[A18:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 11918 // CHECK21-NEXT: store double [[ADD17]], double* [[A18]], align 8 11919 // CHECK21-NEXT: [[A19:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 11920 // CHECK21-NEXT: [[TMP21:%.*]] = load double, double* [[A19]], align 8 11921 // CHECK21-NEXT: [[INC20:%.*]] = fadd double [[TMP21]], 1.000000e+00 11922 // CHECK21-NEXT: store double [[INC20]], double* [[A19]], align 8 11923 // CHECK21-NEXT: [[CONV21:%.*]] = fptosi double [[INC20]] to i16 11924 // CHECK21-NEXT: [[TMP22:%.*]] = mul nsw i64 1, [[TMP2]] 11925 // CHECK21-NEXT: [[ARRAYIDX22:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP22]] 11926 // CHECK21-NEXT: [[ARRAYIDX23:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX22]], i64 1 11927 // CHECK21-NEXT: store i16 [[CONV21]], i16* [[ARRAYIDX23]], align 2 11928 // CHECK21-NEXT: br label [[OMP_BODY_CONTINUE24:%.*]] 11929 // CHECK21: omp.body.continue24: 11930 // CHECK21-NEXT: br label [[OMP_INNER_FOR_INC25:%.*]] 11931 // CHECK21: omp.inner.for.inc25: 11932 // CHECK21-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 11933 // CHECK21-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP23]], 1 11934 // CHECK21-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_IV]], align 4 11935 // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND11]], !llvm.loop [[LOOP33:![0-9]+]] 11936 // CHECK21: omp.inner.for.end27: 11937 // CHECK21-NEXT: br label [[OMP_IF_END]] 11938 // CHECK21: omp_if.end: 11939 // CHECK21-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 11940 // CHECK21: omp.loop.exit: 11941 // CHECK21-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 11942 // CHECK21-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 11943 // CHECK21-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 11944 // CHECK21-NEXT: br i1 [[TMP25]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 11945 // CHECK21: .omp.final.then: 11946 // CHECK21-NEXT: store i32 10, i32* [[I]], align 4 11947 // CHECK21-NEXT: br label [[DOTOMP_FINAL_DONE]] 11948 // CHECK21: .omp.final.done: 11949 // CHECK21-NEXT: ret void 11950 // 11951 // 11952 // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180 11953 // CHECK21-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 11954 // CHECK21-NEXT: entry: 11955 // CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 11956 // CHECK21-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 11957 // CHECK21-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 11958 // CHECK21-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 11959 // CHECK21-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 11960 // CHECK21-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 11961 // CHECK21-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 11962 // CHECK21-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 11963 // CHECK21-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 11964 // CHECK21-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 11965 // CHECK21-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 11966 // CHECK21-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 11967 // CHECK21-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* 11968 // CHECK21-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 11969 // CHECK21-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 11970 // CHECK21-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 11971 // CHECK21-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 11972 // CHECK21-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 11973 // CHECK21-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 11974 // CHECK21-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) 11975 // CHECK21-NEXT: ret void 11976 // 11977 // 11978 // CHECK21-LABEL: define {{[^@]+}}@.omp_outlined..6 11979 // CHECK21-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { 11980 // CHECK21-NEXT: entry: 11981 // CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 11982 // CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 11983 // CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 11984 // CHECK21-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 11985 // CHECK21-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 11986 // CHECK21-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 11987 // CHECK21-NEXT: [[TMP:%.*]] = alloca i32, align 4 11988 // CHECK21-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 11989 // CHECK21-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 11990 // CHECK21-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 11991 // CHECK21-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 11992 // CHECK21-NEXT: [[I:%.*]] = alloca i32, align 4 11993 // CHECK21-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 11994 // CHECK21-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 11995 // CHECK21-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 11996 // CHECK21-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 11997 // CHECK21-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 11998 // CHECK21-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 11999 // CHECK21-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 12000 // CHECK21-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 12001 // CHECK21-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 12002 // CHECK21-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 12003 // CHECK21-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 12004 // CHECK21-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 12005 // CHECK21-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 12006 // CHECK21-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 12007 // CHECK21-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 12008 // CHECK21-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 12009 // CHECK21-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 12010 // CHECK21-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 12011 // CHECK21: cond.true: 12012 // CHECK21-NEXT: br label [[COND_END:%.*]] 12013 // CHECK21: cond.false: 12014 // CHECK21-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 12015 // CHECK21-NEXT: br label [[COND_END]] 12016 // CHECK21: cond.end: 12017 // CHECK21-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 12018 // CHECK21-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 12019 // CHECK21-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 12020 // CHECK21-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 12021 // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 12022 // CHECK21: omp.inner.for.cond: 12023 // CHECK21-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !35 12024 // CHECK21-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !35 12025 // CHECK21-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] 12026 // CHECK21-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 12027 // CHECK21: omp.inner.for.body: 12028 // CHECK21-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !35 12029 // CHECK21-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 12030 // CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 12031 // CHECK21-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !35 12032 // CHECK21-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !35 12033 // CHECK21-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1 12034 // CHECK21-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4, !llvm.access.group !35 12035 // CHECK21-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 2, !llvm.access.group !35 12036 // CHECK21-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32 12037 // CHECK21-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 12038 // CHECK21-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 12039 // CHECK21-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2, !llvm.access.group !35 12040 // CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 12041 // CHECK21-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !35 12042 // CHECK21-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1 12043 // CHECK21-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !35 12044 // CHECK21-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 12045 // CHECK21: omp.body.continue: 12046 // CHECK21-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 12047 // CHECK21: omp.inner.for.inc: 12048 // CHECK21-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !35 12049 // CHECK21-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP12]], 1 12050 // CHECK21-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !35 12051 // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP36:![0-9]+]] 12052 // CHECK21: omp.inner.for.end: 12053 // CHECK21-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 12054 // CHECK21: omp.loop.exit: 12055 // CHECK21-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) 12056 // CHECK21-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 12057 // CHECK21-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 12058 // CHECK21-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 12059 // CHECK21: .omp.final.then: 12060 // CHECK21-NEXT: store i32 10, i32* [[I]], align 4 12061 // CHECK21-NEXT: br label [[DOTOMP_FINAL_DONE]] 12062 // CHECK21: .omp.final.done: 12063 // CHECK21-NEXT: ret void 12064 // 12065 // 12066 // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97 12067 // CHECK23-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]], i32 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { 12068 // CHECK23-NEXT: entry: 12069 // CHECK23-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 12070 // CHECK23-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 12071 // CHECK23-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4 12072 // CHECK23-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 12073 // CHECK23-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) 12074 // CHECK23-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 12075 // CHECK23-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 12076 // CHECK23-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 12077 // CHECK23-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 12078 // CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 12079 // CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 12080 // CHECK23-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) 12081 // CHECK23-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 12082 // CHECK23-NEXT: [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 12083 // CHECK23-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 12084 // CHECK23-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 12085 // CHECK23-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]]) 12086 // CHECK23-NEXT: ret void 12087 // 12088 // 12089 // CHECK23-LABEL: define {{[^@]+}}@.omp_outlined. 12090 // CHECK23-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR1:[0-9]+]] { 12091 // CHECK23-NEXT: entry: 12092 // CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 12093 // CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 12094 // CHECK23-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 12095 // CHECK23-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 12096 // CHECK23-NEXT: [[TMP:%.*]] = alloca i32, align 4 12097 // CHECK23-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 12098 // CHECK23-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 12099 // CHECK23-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 12100 // CHECK23-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 12101 // CHECK23-NEXT: [[I:%.*]] = alloca i32, align 4 12102 // CHECK23-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 12103 // CHECK23-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 12104 // CHECK23-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 12105 // CHECK23-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 12106 // CHECK23-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 12107 // CHECK23-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 12108 // CHECK23-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 12109 // CHECK23-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 12110 // CHECK23-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 12111 // CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 12112 // CHECK23-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 12113 // CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 12114 // CHECK23-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 12115 // CHECK23-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 12116 // CHECK23: cond.true: 12117 // CHECK23-NEXT: br label [[COND_END:%.*]] 12118 // CHECK23: cond.false: 12119 // CHECK23-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 12120 // CHECK23-NEXT: br label [[COND_END]] 12121 // CHECK23: cond.end: 12122 // CHECK23-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 12123 // CHECK23-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 12124 // CHECK23-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 12125 // CHECK23-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 12126 // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 12127 // CHECK23: omp.inner.for.cond: 12128 // CHECK23-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 12129 // CHECK23-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !12 12130 // CHECK23-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 12131 // CHECK23-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 12132 // CHECK23: omp.inner.for.body: 12133 // CHECK23-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 12134 // CHECK23-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 12135 // CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 12136 // CHECK23-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !12 12137 // CHECK23-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 12138 // CHECK23: omp.body.continue: 12139 // CHECK23-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 12140 // CHECK23: omp.inner.for.inc: 12141 // CHECK23-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 12142 // CHECK23-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 12143 // CHECK23-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 12144 // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] 12145 // CHECK23: omp.inner.for.end: 12146 // CHECK23-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 12147 // CHECK23: omp.loop.exit: 12148 // CHECK23-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 12149 // CHECK23-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 12150 // CHECK23-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 12151 // CHECK23-NEXT: br i1 [[TMP10]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 12152 // CHECK23: .omp.final.then: 12153 // CHECK23-NEXT: store i32 10, i32* [[I]], align 4 12154 // CHECK23-NEXT: br label [[DOTOMP_FINAL_DONE]] 12155 // CHECK23: .omp.final.done: 12156 // CHECK23-NEXT: ret void 12157 // 12158 // 12159 // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 12160 // CHECK23-SAME: (i32 noundef [[AA:%.*]]) #[[ATTR0]] { 12161 // CHECK23-NEXT: entry: 12162 // CHECK23-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 12163 // CHECK23-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 12164 // CHECK23-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 12165 // CHECK23-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 12166 // CHECK23-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 12167 // CHECK23-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 12168 // CHECK23-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 12169 // CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 12170 // CHECK23-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]]) 12171 // CHECK23-NEXT: ret void 12172 // 12173 // 12174 // CHECK23-LABEL: define {{[^@]+}}@.omp_outlined..1 12175 // CHECK23-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR1]] { 12176 // CHECK23-NEXT: entry: 12177 // CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 12178 // CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 12179 // CHECK23-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 12180 // CHECK23-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 12181 // CHECK23-NEXT: [[TMP:%.*]] = alloca i32, align 4 12182 // CHECK23-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 12183 // CHECK23-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 12184 // CHECK23-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 12185 // CHECK23-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 12186 // CHECK23-NEXT: [[I:%.*]] = alloca i32, align 4 12187 // CHECK23-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 12188 // CHECK23-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 12189 // CHECK23-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 12190 // CHECK23-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 12191 // CHECK23-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 12192 // CHECK23-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 12193 // CHECK23-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 12194 // CHECK23-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 12195 // CHECK23-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 12196 // CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 12197 // CHECK23-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 12198 // CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 12199 // CHECK23-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 12200 // CHECK23-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 12201 // CHECK23: cond.true: 12202 // CHECK23-NEXT: br label [[COND_END:%.*]] 12203 // CHECK23: cond.false: 12204 // CHECK23-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 12205 // CHECK23-NEXT: br label [[COND_END]] 12206 // CHECK23: cond.end: 12207 // CHECK23-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 12208 // CHECK23-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 12209 // CHECK23-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 12210 // CHECK23-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 12211 // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 12212 // CHECK23: omp.inner.for.cond: 12213 // CHECK23-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 12214 // CHECK23-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !19 12215 // CHECK23-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 12216 // CHECK23-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 12217 // CHECK23: omp.inner.for.body: 12218 // CHECK23-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 12219 // CHECK23-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 12220 // CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 12221 // CHECK23-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !19 12222 // CHECK23-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !19 12223 // CHECK23-NEXT: [[CONV2:%.*]] = sext i16 [[TMP8]] to i32 12224 // CHECK23-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 12225 // CHECK23-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 12226 // CHECK23-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2, !llvm.access.group !19 12227 // CHECK23-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 12228 // CHECK23: omp.body.continue: 12229 // CHECK23-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 12230 // CHECK23: omp.inner.for.inc: 12231 // CHECK23-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 12232 // CHECK23-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP9]], 1 12233 // CHECK23-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19 12234 // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]] 12235 // CHECK23: omp.inner.for.end: 12236 // CHECK23-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 12237 // CHECK23: omp.loop.exit: 12238 // CHECK23-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 12239 // CHECK23-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 12240 // CHECK23-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0 12241 // CHECK23-NEXT: br i1 [[TMP11]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 12242 // CHECK23: .omp.final.then: 12243 // CHECK23-NEXT: store i32 10, i32* [[I]], align 4 12244 // CHECK23-NEXT: br label [[DOTOMP_FINAL_DONE]] 12245 // CHECK23: .omp.final.done: 12246 // CHECK23-NEXT: ret void 12247 // 12248 // 12249 // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118 12250 // CHECK23-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { 12251 // CHECK23-NEXT: entry: 12252 // CHECK23-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 12253 // CHECK23-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 12254 // CHECK23-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 12255 // CHECK23-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 12256 // CHECK23-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 12257 // CHECK23-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 12258 // CHECK23-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 12259 // CHECK23-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 12260 // CHECK23-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 12261 // CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 12262 // CHECK23-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 12263 // CHECK23-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 12264 // CHECK23-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 12265 // CHECK23-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 12266 // CHECK23-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) 12267 // CHECK23-NEXT: ret void 12268 // 12269 // 12270 // CHECK23-LABEL: define {{[^@]+}}@.omp_outlined..2 12271 // CHECK23-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR1]] { 12272 // CHECK23-NEXT: entry: 12273 // CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 12274 // CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 12275 // CHECK23-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 12276 // CHECK23-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 12277 // CHECK23-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 12278 // CHECK23-NEXT: [[TMP:%.*]] = alloca i32, align 4 12279 // CHECK23-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 12280 // CHECK23-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 12281 // CHECK23-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 12282 // CHECK23-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 12283 // CHECK23-NEXT: [[I:%.*]] = alloca i32, align 4 12284 // CHECK23-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 12285 // CHECK23-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 12286 // CHECK23-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 12287 // CHECK23-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 12288 // CHECK23-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 12289 // CHECK23-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 12290 // CHECK23-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 12291 // CHECK23-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 12292 // CHECK23-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 12293 // CHECK23-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 12294 // CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 12295 // CHECK23-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 12296 // CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 12297 // CHECK23-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 12298 // CHECK23-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 12299 // CHECK23: cond.true: 12300 // CHECK23-NEXT: br label [[COND_END:%.*]] 12301 // CHECK23: cond.false: 12302 // CHECK23-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 12303 // CHECK23-NEXT: br label [[COND_END]] 12304 // CHECK23: cond.end: 12305 // CHECK23-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 12306 // CHECK23-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 12307 // CHECK23-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 12308 // CHECK23-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 12309 // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 12310 // CHECK23: omp.inner.for.cond: 12311 // CHECK23-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 12312 // CHECK23-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !22 12313 // CHECK23-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 12314 // CHECK23-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 12315 // CHECK23: omp.inner.for.body: 12316 // CHECK23-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 12317 // CHECK23-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 12318 // CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 12319 // CHECK23-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !22 12320 // CHECK23-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !22 12321 // CHECK23-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 12322 // CHECK23-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4, !llvm.access.group !22 12323 // CHECK23-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !22 12324 // CHECK23-NEXT: [[CONV3:%.*]] = sext i16 [[TMP9]] to i32 12325 // CHECK23-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 12326 // CHECK23-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 12327 // CHECK23-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2, !llvm.access.group !22 12328 // CHECK23-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 12329 // CHECK23: omp.body.continue: 12330 // CHECK23-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 12331 // CHECK23: omp.inner.for.inc: 12332 // CHECK23-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 12333 // CHECK23-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP10]], 1 12334 // CHECK23-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 12335 // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]] 12336 // CHECK23: omp.inner.for.end: 12337 // CHECK23-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 12338 // CHECK23: omp.loop.exit: 12339 // CHECK23-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 12340 // CHECK23-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 12341 // CHECK23-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 12342 // CHECK23-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 12343 // CHECK23: .omp.final.then: 12344 // CHECK23-NEXT: store i32 10, i32* [[I]], align 4 12345 // CHECK23-NEXT: br label [[DOTOMP_FINAL_DONE]] 12346 // CHECK23: .omp.final.done: 12347 // CHECK23-NEXT: ret void 12348 // 12349 // 12350 // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142 12351 // CHECK23-SAME: (i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] { 12352 // CHECK23-NEXT: entry: 12353 // CHECK23-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 12354 // CHECK23-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 12355 // CHECK23-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 12356 // CHECK23-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 12357 // CHECK23-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 12358 // CHECK23-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 12359 // CHECK23-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 12360 // CHECK23-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 12361 // CHECK23-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 12362 // CHECK23-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 12363 // CHECK23-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 12364 // CHECK23-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 12365 // CHECK23-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 12366 // CHECK23-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 12367 // CHECK23-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 12368 // CHECK23-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 12369 // CHECK23-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 12370 // CHECK23-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 12371 // CHECK23-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 12372 // CHECK23-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 12373 // CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 12374 // CHECK23-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 12375 // CHECK23-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 12376 // CHECK23-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 12377 // CHECK23-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 12378 // CHECK23-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 12379 // CHECK23-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 12380 // CHECK23-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 12381 // CHECK23-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4 12382 // CHECK23-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4 12383 // CHECK23-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) 12384 // CHECK23-NEXT: ret void 12385 // 12386 // 12387 // CHECK23-LABEL: define {{[^@]+}}@.omp_outlined..3 12388 // CHECK23-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR1]] { 12389 // CHECK23-NEXT: entry: 12390 // CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 12391 // CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 12392 // CHECK23-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 12393 // CHECK23-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 12394 // CHECK23-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 12395 // CHECK23-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 12396 // CHECK23-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 12397 // CHECK23-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 12398 // CHECK23-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 12399 // CHECK23-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 12400 // CHECK23-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 12401 // CHECK23-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 12402 // CHECK23-NEXT: [[TMP:%.*]] = alloca i32, align 4 12403 // CHECK23-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 12404 // CHECK23-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 12405 // CHECK23-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 12406 // CHECK23-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 12407 // CHECK23-NEXT: [[I:%.*]] = alloca i32, align 4 12408 // CHECK23-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 12409 // CHECK23-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 12410 // CHECK23-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 12411 // CHECK23-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 12412 // CHECK23-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 12413 // CHECK23-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 12414 // CHECK23-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 12415 // CHECK23-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 12416 // CHECK23-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 12417 // CHECK23-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 12418 // CHECK23-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 12419 // CHECK23-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 12420 // CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 12421 // CHECK23-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 12422 // CHECK23-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 12423 // CHECK23-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 12424 // CHECK23-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 12425 // CHECK23-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 12426 // CHECK23-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 12427 // CHECK23-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 0 12428 // CHECK23-NEXT: call void @llvm.assume(i1 true) [ "align"(float* [[ARRAYDECAY]], i32 16) ] 12429 // CHECK23-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 12430 // CHECK23-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 12431 // CHECK23-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 12432 // CHECK23-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 12433 // CHECK23-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 12434 // CHECK23-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 12435 // CHECK23-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 12436 // CHECK23-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 12437 // CHECK23-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP10]], 9 12438 // CHECK23-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 12439 // CHECK23: cond.true: 12440 // CHECK23-NEXT: br label [[COND_END:%.*]] 12441 // CHECK23: cond.false: 12442 // CHECK23-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 12443 // CHECK23-NEXT: br label [[COND_END]] 12444 // CHECK23: cond.end: 12445 // CHECK23-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] 12446 // CHECK23-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 12447 // CHECK23-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 12448 // CHECK23-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 12449 // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 12450 // CHECK23: omp.inner.for.cond: 12451 // CHECK23-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25 12452 // CHECK23-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !25 12453 // CHECK23-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] 12454 // CHECK23-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 12455 // CHECK23: omp.inner.for.body: 12456 // CHECK23-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25 12457 // CHECK23-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 12458 // CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 12459 // CHECK23-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !25 12460 // CHECK23-NEXT: [[TMP16:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !25 12461 // CHECK23-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP16]], 1 12462 // CHECK23-NEXT: store i32 [[ADD6]], i32* [[A_ADDR]], align 4, !llvm.access.group !25 12463 // CHECK23-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2 12464 // CHECK23-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !25 12465 // CHECK23-NEXT: [[CONV:%.*]] = fpext float [[TMP17]] to double 12466 // CHECK23-NEXT: [[ADD7:%.*]] = fadd double [[CONV]], 1.000000e+00 12467 // CHECK23-NEXT: [[CONV8:%.*]] = fptrunc double [[ADD7]] to float 12468 // CHECK23-NEXT: store float [[CONV8]], float* [[ARRAYIDX]], align 4, !llvm.access.group !25 12469 // CHECK23-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3 12470 // CHECK23-NEXT: [[TMP18:%.*]] = load float, float* [[ARRAYIDX9]], align 4, !llvm.access.group !25 12471 // CHECK23-NEXT: [[CONV10:%.*]] = fpext float [[TMP18]] to double 12472 // CHECK23-NEXT: [[ADD11:%.*]] = fadd double [[CONV10]], 1.000000e+00 12473 // CHECK23-NEXT: [[CONV12:%.*]] = fptrunc double [[ADD11]] to float 12474 // CHECK23-NEXT: store float [[CONV12]], float* [[ARRAYIDX9]], align 4, !llvm.access.group !25 12475 // CHECK23-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1 12476 // CHECK23-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX13]], i32 0, i32 2 12477 // CHECK23-NEXT: [[TMP19:%.*]] = load double, double* [[ARRAYIDX14]], align 8, !llvm.access.group !25 12478 // CHECK23-NEXT: [[ADD15:%.*]] = fadd double [[TMP19]], 1.000000e+00 12479 // CHECK23-NEXT: store double [[ADD15]], double* [[ARRAYIDX14]], align 8, !llvm.access.group !25 12480 // CHECK23-NEXT: [[TMP20:%.*]] = mul nsw i32 1, [[TMP5]] 12481 // CHECK23-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP20]] 12482 // CHECK23-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX16]], i32 3 12483 // CHECK23-NEXT: [[TMP21:%.*]] = load double, double* [[ARRAYIDX17]], align 8, !llvm.access.group !25 12484 // CHECK23-NEXT: [[ADD18:%.*]] = fadd double [[TMP21]], 1.000000e+00 12485 // CHECK23-NEXT: store double [[ADD18]], double* [[ARRAYIDX17]], align 8, !llvm.access.group !25 12486 // CHECK23-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 12487 // CHECK23-NEXT: [[TMP22:%.*]] = load i64, i64* [[X]], align 4, !llvm.access.group !25 12488 // CHECK23-NEXT: [[ADD19:%.*]] = add nsw i64 [[TMP22]], 1 12489 // CHECK23-NEXT: store i64 [[ADD19]], i64* [[X]], align 4, !llvm.access.group !25 12490 // CHECK23-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 12491 // CHECK23-NEXT: [[TMP23:%.*]] = load i8, i8* [[Y]], align 4, !llvm.access.group !25 12492 // CHECK23-NEXT: [[CONV20:%.*]] = sext i8 [[TMP23]] to i32 12493 // CHECK23-NEXT: [[ADD21:%.*]] = add nsw i32 [[CONV20]], 1 12494 // CHECK23-NEXT: [[CONV22:%.*]] = trunc i32 [[ADD21]] to i8 12495 // CHECK23-NEXT: store i8 [[CONV22]], i8* [[Y]], align 4, !llvm.access.group !25 12496 // CHECK23-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 12497 // CHECK23: omp.body.continue: 12498 // CHECK23-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 12499 // CHECK23: omp.inner.for.inc: 12500 // CHECK23-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25 12501 // CHECK23-NEXT: [[ADD23:%.*]] = add nsw i32 [[TMP24]], 1 12502 // CHECK23-NEXT: store i32 [[ADD23]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25 12503 // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP26:![0-9]+]] 12504 // CHECK23: omp.inner.for.end: 12505 // CHECK23-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 12506 // CHECK23: omp.loop.exit: 12507 // CHECK23-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]]) 12508 // CHECK23-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 12509 // CHECK23-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0 12510 // CHECK23-NEXT: br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 12511 // CHECK23: .omp.final.then: 12512 // CHECK23-NEXT: store i32 10, i32* [[I]], align 4 12513 // CHECK23-NEXT: br label [[DOTOMP_FINAL_DONE]] 12514 // CHECK23: .omp.final.done: 12515 // CHECK23-NEXT: ret void 12516 // 12517 // 12518 // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197 12519 // CHECK23-SAME: (i32 noundef [[A:%.*]], i32 noundef [[N:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 12520 // CHECK23-NEXT: entry: 12521 // CHECK23-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 12522 // CHECK23-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 12523 // CHECK23-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 12524 // CHECK23-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 12525 // CHECK23-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 12526 // CHECK23-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 12527 // CHECK23-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 12528 // CHECK23-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 12529 // CHECK23-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 12530 // CHECK23-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 12531 // CHECK23-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 12532 // CHECK23-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 12533 // CHECK23-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 12534 // CHECK23-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 12535 // CHECK23-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 12536 // CHECK23-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 12537 // CHECK23-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 12538 // CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 12539 // CHECK23-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 12540 // CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 12541 // CHECK23-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 12542 // CHECK23-NEXT: store i32 [[TMP3]], i32* [[N_CASTED]], align 4 12543 // CHECK23-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_CASTED]], align 4 12544 // CHECK23-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 2 12545 // CHECK23-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 12546 // CHECK23-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2 12547 // CHECK23-NEXT: [[TMP6:%.*]] = load i32, i32* [[AA_CASTED]], align 4 12548 // CHECK23-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV1]], align 1 12549 // CHECK23-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* 12550 // CHECK23-NEXT: store i8 [[TMP7]], i8* [[CONV3]], align 1 12551 // CHECK23-NEXT: [[TMP8:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 12552 // CHECK23-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP8]], [10 x i32]* [[TMP0]]) 12553 // CHECK23-NEXT: ret void 12554 // 12555 // 12556 // CHECK23-LABEL: define {{[^@]+}}@.omp_outlined..4 12557 // CHECK23-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[N:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { 12558 // CHECK23-NEXT: entry: 12559 // CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 12560 // CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 12561 // CHECK23-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 12562 // CHECK23-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 12563 // CHECK23-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 12564 // CHECK23-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 12565 // CHECK23-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 12566 // CHECK23-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 12567 // CHECK23-NEXT: [[TMP:%.*]] = alloca i32, align 4 12568 // CHECK23-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 12569 // CHECK23-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 12570 // CHECK23-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4 12571 // CHECK23-NEXT: [[I:%.*]] = alloca i32, align 4 12572 // CHECK23-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 12573 // CHECK23-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 12574 // CHECK23-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 12575 // CHECK23-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 12576 // CHECK23-NEXT: [[I6:%.*]] = alloca i32, align 4 12577 // CHECK23-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 12578 // CHECK23-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 12579 // CHECK23-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 12580 // CHECK23-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 12581 // CHECK23-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 12582 // CHECK23-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 12583 // CHECK23-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 12584 // CHECK23-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 12585 // CHECK23-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 12586 // CHECK23-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 12587 // CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 12588 // CHECK23-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 12589 // CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 12590 // CHECK23-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4 12591 // CHECK23-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 12592 // CHECK23-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 12593 // CHECK23-NEXT: [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]] 12594 // CHECK23-NEXT: [[SUB4:%.*]] = sub i32 [[SUB]], 1 12595 // CHECK23-NEXT: [[ADD:%.*]] = add i32 [[SUB4]], 1 12596 // CHECK23-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 12597 // CHECK23-NEXT: [[SUB5:%.*]] = sub i32 [[DIV]], 1 12598 // CHECK23-NEXT: store i32 [[SUB5]], i32* [[DOTCAPTURE_EXPR_3]], align 4 12599 // CHECK23-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 12600 // CHECK23-NEXT: store i32 [[TMP5]], i32* [[I]], align 4 12601 // CHECK23-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 12602 // CHECK23-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 12603 // CHECK23-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]] 12604 // CHECK23-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] 12605 // CHECK23: omp.precond.then: 12606 // CHECK23-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 12607 // CHECK23-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 12608 // CHECK23-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_UB]], align 4 12609 // CHECK23-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 12610 // CHECK23-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 12611 // CHECK23-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 12612 // CHECK23-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 12613 // CHECK23-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 12614 // CHECK23-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 12615 // CHECK23-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 12616 // CHECK23-NEXT: [[CMP7:%.*]] = icmp ugt i32 [[TMP11]], [[TMP12]] 12617 // CHECK23-NEXT: br i1 [[CMP7]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 12618 // CHECK23: cond.true: 12619 // CHECK23-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 12620 // CHECK23-NEXT: br label [[COND_END:%.*]] 12621 // CHECK23: cond.false: 12622 // CHECK23-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 12623 // CHECK23-NEXT: br label [[COND_END]] 12624 // CHECK23: cond.end: 12625 // CHECK23-NEXT: [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ] 12626 // CHECK23-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 12627 // CHECK23-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 12628 // CHECK23-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4 12629 // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 12630 // CHECK23: omp.inner.for.cond: 12631 // CHECK23-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28 12632 // CHECK23-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !28 12633 // CHECK23-NEXT: [[ADD8:%.*]] = add i32 [[TMP17]], 1 12634 // CHECK23-NEXT: [[CMP9:%.*]] = icmp ult i32 [[TMP16]], [[ADD8]] 12635 // CHECK23-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 12636 // CHECK23: omp.inner.for.body: 12637 // CHECK23-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group !28 12638 // CHECK23-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28 12639 // CHECK23-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 1 12640 // CHECK23-NEXT: [[ADD10:%.*]] = add i32 [[TMP18]], [[MUL]] 12641 // CHECK23-NEXT: store i32 [[ADD10]], i32* [[I6]], align 4, !llvm.access.group !28 12642 // CHECK23-NEXT: [[TMP20:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !28 12643 // CHECK23-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP20]], 1 12644 // CHECK23-NEXT: store i32 [[ADD11]], i32* [[A_ADDR]], align 4, !llvm.access.group !28 12645 // CHECK23-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !28 12646 // CHECK23-NEXT: [[CONV12:%.*]] = sext i16 [[TMP21]] to i32 12647 // CHECK23-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1 12648 // CHECK23-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16 12649 // CHECK23-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 2, !llvm.access.group !28 12650 // CHECK23-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV1]], align 1, !llvm.access.group !28 12651 // CHECK23-NEXT: [[CONV15:%.*]] = sext i8 [[TMP22]] to i32 12652 // CHECK23-NEXT: [[ADD16:%.*]] = add nsw i32 [[CONV15]], 1 12653 // CHECK23-NEXT: [[CONV17:%.*]] = trunc i32 [[ADD16]] to i8 12654 // CHECK23-NEXT: store i8 [[CONV17]], i8* [[CONV1]], align 1, !llvm.access.group !28 12655 // CHECK23-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 12656 // CHECK23-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !28 12657 // CHECK23-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP23]], 1 12658 // CHECK23-NEXT: store i32 [[ADD18]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !28 12659 // CHECK23-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 12660 // CHECK23: omp.body.continue: 12661 // CHECK23-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 12662 // CHECK23: omp.inner.for.inc: 12663 // CHECK23-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28 12664 // CHECK23-NEXT: [[ADD19:%.*]] = add i32 [[TMP24]], 1 12665 // CHECK23-NEXT: store i32 [[ADD19]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28 12666 // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP29:![0-9]+]] 12667 // CHECK23: omp.inner.for.end: 12668 // CHECK23-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 12669 // CHECK23: omp.loop.exit: 12670 // CHECK23-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 12671 // CHECK23-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 12672 // CHECK23-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) 12673 // CHECK23-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 12674 // CHECK23-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0 12675 // CHECK23-NEXT: br i1 [[TMP28]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 12676 // CHECK23: .omp.final.then: 12677 // CHECK23-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 12678 // CHECK23-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 12679 // CHECK23-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 12680 // CHECK23-NEXT: [[SUB20:%.*]] = sub i32 [[TMP30]], [[TMP31]] 12681 // CHECK23-NEXT: [[SUB21:%.*]] = sub i32 [[SUB20]], 1 12682 // CHECK23-NEXT: [[ADD22:%.*]] = add i32 [[SUB21]], 1 12683 // CHECK23-NEXT: [[DIV23:%.*]] = udiv i32 [[ADD22]], 1 12684 // CHECK23-NEXT: [[MUL24:%.*]] = mul i32 [[DIV23]], 1 12685 // CHECK23-NEXT: [[ADD25:%.*]] = add i32 [[TMP29]], [[MUL24]] 12686 // CHECK23-NEXT: store i32 [[ADD25]], i32* [[I6]], align 4 12687 // CHECK23-NEXT: br label [[DOTOMP_FINAL_DONE]] 12688 // CHECK23: .omp.final.done: 12689 // CHECK23-NEXT: br label [[OMP_PRECOND_END]] 12690 // CHECK23: omp.precond.end: 12691 // CHECK23-NEXT: ret void 12692 // 12693 // 12694 // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215 12695 // CHECK23-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { 12696 // CHECK23-NEXT: entry: 12697 // CHECK23-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 12698 // CHECK23-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 12699 // CHECK23-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 12700 // CHECK23-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 12701 // CHECK23-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 12702 // CHECK23-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 12703 // CHECK23-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 12704 // CHECK23-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 12705 // CHECK23-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 12706 // CHECK23-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 12707 // CHECK23-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 12708 // CHECK23-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 12709 // CHECK23-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 12710 // CHECK23-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 12711 // CHECK23-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 12712 // CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 12713 // CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 12714 // CHECK23-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 12715 // CHECK23-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8* 12716 // CHECK23-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 12717 // CHECK23-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 12718 // CHECK23-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 12719 // CHECK23-NEXT: [[TMP6:%.*]] = load i8, i8* [[CONV]], align 1 12720 // CHECK23-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP6]] to i1 12721 // CHECK23-NEXT: [[CONV3:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__CASTED]] to i8* 12722 // CHECK23-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 12723 // CHECK23-NEXT: store i8 [[FROMBOOL]], i8* [[CONV3]], align 1 12724 // CHECK23-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 12725 // CHECK23-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]], i32 [[TMP7]]) 12726 // CHECK23-NEXT: ret void 12727 // 12728 // 12729 // CHECK23-LABEL: define {{[^@]+}}@.omp_outlined..5 12730 // CHECK23-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { 12731 // CHECK23-NEXT: entry: 12732 // CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 12733 // CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 12734 // CHECK23-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 12735 // CHECK23-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 12736 // CHECK23-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 12737 // CHECK23-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 12738 // CHECK23-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 12739 // CHECK23-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 12740 // CHECK23-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 12741 // CHECK23-NEXT: [[TMP:%.*]] = alloca i32, align 4 12742 // CHECK23-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 12743 // CHECK23-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 12744 // CHECK23-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 12745 // CHECK23-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 12746 // CHECK23-NEXT: [[I:%.*]] = alloca i32, align 4 12747 // CHECK23-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 12748 // CHECK23-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 12749 // CHECK23-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 12750 // CHECK23-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 12751 // CHECK23-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 12752 // CHECK23-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 12753 // CHECK23-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 12754 // CHECK23-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 12755 // CHECK23-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 12756 // CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 12757 // CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 12758 // CHECK23-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 12759 // CHECK23-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8* 12760 // CHECK23-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 12761 // CHECK23-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 12762 // CHECK23-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 12763 // CHECK23-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 12764 // CHECK23-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 12765 // CHECK23-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 12766 // CHECK23-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 12767 // CHECK23-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 12768 // CHECK23-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 9 12769 // CHECK23-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 12770 // CHECK23: cond.true: 12771 // CHECK23-NEXT: br label [[COND_END:%.*]] 12772 // CHECK23: cond.false: 12773 // CHECK23-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 12774 // CHECK23-NEXT: br label [[COND_END]] 12775 // CHECK23: cond.end: 12776 // CHECK23-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 12777 // CHECK23-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 12778 // CHECK23-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 12779 // CHECK23-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 12780 // CHECK23-NEXT: [[TMP9:%.*]] = load i8, i8* [[CONV]], align 1 12781 // CHECK23-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP9]] to i1 12782 // CHECK23-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 12783 // CHECK23: omp_if.then: 12784 // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 12785 // CHECK23: omp.inner.for.cond: 12786 // CHECK23-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !31 12787 // CHECK23-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !31 12788 // CHECK23-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]] 12789 // CHECK23-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 12790 // CHECK23: omp.inner.for.body: 12791 // CHECK23-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !31 12792 // CHECK23-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1 12793 // CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 12794 // CHECK23-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !31 12795 // CHECK23-NEXT: [[TMP13:%.*]] = load i32, i32* [[B_ADDR]], align 4, !llvm.access.group !31 12796 // CHECK23-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP13]] to double 12797 // CHECK23-NEXT: [[ADD5:%.*]] = fadd double [[CONV4]], 1.500000e+00 12798 // CHECK23-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 12799 // CHECK23-NEXT: store double [[ADD5]], double* [[A]], align 4, !llvm.access.group !31 12800 // CHECK23-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 12801 // CHECK23-NEXT: [[TMP14:%.*]] = load double, double* [[A6]], align 4, !llvm.access.group !31 12802 // CHECK23-NEXT: [[INC:%.*]] = fadd double [[TMP14]], 1.000000e+00 12803 // CHECK23-NEXT: store double [[INC]], double* [[A6]], align 4, !llvm.access.group !31 12804 // CHECK23-NEXT: [[CONV7:%.*]] = fptosi double [[INC]] to i16 12805 // CHECK23-NEXT: [[TMP15:%.*]] = mul nsw i32 1, [[TMP2]] 12806 // CHECK23-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP15]] 12807 // CHECK23-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 12808 // CHECK23-NEXT: store i16 [[CONV7]], i16* [[ARRAYIDX8]], align 2, !llvm.access.group !31 12809 // CHECK23-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 12810 // CHECK23: omp.body.continue: 12811 // CHECK23-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 12812 // CHECK23: omp.inner.for.inc: 12813 // CHECK23-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !31 12814 // CHECK23-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP16]], 1 12815 // CHECK23-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !31 12816 // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP32:![0-9]+]] 12817 // CHECK23: omp.inner.for.end: 12818 // CHECK23-NEXT: br label [[OMP_IF_END:%.*]] 12819 // CHECK23: omp_if.else: 12820 // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND10:%.*]] 12821 // CHECK23: omp.inner.for.cond10: 12822 // CHECK23-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 12823 // CHECK23-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 12824 // CHECK23-NEXT: [[CMP11:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]] 12825 // CHECK23-NEXT: br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY12:%.*]], label [[OMP_INNER_FOR_END26:%.*]] 12826 // CHECK23: omp.inner.for.body12: 12827 // CHECK23-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 12828 // CHECK23-NEXT: [[MUL13:%.*]] = mul nsw i32 [[TMP19]], 1 12829 // CHECK23-NEXT: [[ADD14:%.*]] = add nsw i32 0, [[MUL13]] 12830 // CHECK23-NEXT: store i32 [[ADD14]], i32* [[I]], align 4 12831 // CHECK23-NEXT: [[TMP20:%.*]] = load i32, i32* [[B_ADDR]], align 4 12832 // CHECK23-NEXT: [[CONV15:%.*]] = sitofp i32 [[TMP20]] to double 12833 // CHECK23-NEXT: [[ADD16:%.*]] = fadd double [[CONV15]], 1.500000e+00 12834 // CHECK23-NEXT: [[A17:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 12835 // CHECK23-NEXT: store double [[ADD16]], double* [[A17]], align 4 12836 // CHECK23-NEXT: [[A18:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 12837 // CHECK23-NEXT: [[TMP21:%.*]] = load double, double* [[A18]], align 4 12838 // CHECK23-NEXT: [[INC19:%.*]] = fadd double [[TMP21]], 1.000000e+00 12839 // CHECK23-NEXT: store double [[INC19]], double* [[A18]], align 4 12840 // CHECK23-NEXT: [[CONV20:%.*]] = fptosi double [[INC19]] to i16 12841 // CHECK23-NEXT: [[TMP22:%.*]] = mul nsw i32 1, [[TMP2]] 12842 // CHECK23-NEXT: [[ARRAYIDX21:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP22]] 12843 // CHECK23-NEXT: [[ARRAYIDX22:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX21]], i32 1 12844 // CHECK23-NEXT: store i16 [[CONV20]], i16* [[ARRAYIDX22]], align 2 12845 // CHECK23-NEXT: br label [[OMP_BODY_CONTINUE23:%.*]] 12846 // CHECK23: omp.body.continue23: 12847 // CHECK23-NEXT: br label [[OMP_INNER_FOR_INC24:%.*]] 12848 // CHECK23: omp.inner.for.inc24: 12849 // CHECK23-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 12850 // CHECK23-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP23]], 1 12851 // CHECK23-NEXT: store i32 [[ADD25]], i32* [[DOTOMP_IV]], align 4 12852 // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND10]], !llvm.loop [[LOOP34:![0-9]+]] 12853 // CHECK23: omp.inner.for.end26: 12854 // CHECK23-NEXT: br label [[OMP_IF_END]] 12855 // CHECK23: omp_if.end: 12856 // CHECK23-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 12857 // CHECK23: omp.loop.exit: 12858 // CHECK23-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 12859 // CHECK23-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 12860 // CHECK23-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 12861 // CHECK23-NEXT: br i1 [[TMP25]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 12862 // CHECK23: .omp.final.then: 12863 // CHECK23-NEXT: store i32 10, i32* [[I]], align 4 12864 // CHECK23-NEXT: br label [[DOTOMP_FINAL_DONE]] 12865 // CHECK23: .omp.final.done: 12866 // CHECK23-NEXT: ret void 12867 // 12868 // 12869 // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180 12870 // CHECK23-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 12871 // CHECK23-NEXT: entry: 12872 // CHECK23-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 12873 // CHECK23-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 12874 // CHECK23-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 12875 // CHECK23-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 12876 // CHECK23-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 12877 // CHECK23-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 12878 // CHECK23-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 12879 // CHECK23-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 12880 // CHECK23-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 12881 // CHECK23-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 12882 // CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 12883 // CHECK23-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 12884 // CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 12885 // CHECK23-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 12886 // CHECK23-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 12887 // CHECK23-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 12888 // CHECK23-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 12889 // CHECK23-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) 12890 // CHECK23-NEXT: ret void 12891 // 12892 // 12893 // CHECK23-LABEL: define {{[^@]+}}@.omp_outlined..6 12894 // CHECK23-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { 12895 // CHECK23-NEXT: entry: 12896 // CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 12897 // CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 12898 // CHECK23-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 12899 // CHECK23-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 12900 // CHECK23-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 12901 // CHECK23-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 12902 // CHECK23-NEXT: [[TMP:%.*]] = alloca i32, align 4 12903 // CHECK23-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 12904 // CHECK23-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 12905 // CHECK23-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 12906 // CHECK23-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 12907 // CHECK23-NEXT: [[I:%.*]] = alloca i32, align 4 12908 // CHECK23-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 12909 // CHECK23-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 12910 // CHECK23-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 12911 // CHECK23-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 12912 // CHECK23-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 12913 // CHECK23-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 12914 // CHECK23-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 12915 // CHECK23-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 12916 // CHECK23-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 12917 // CHECK23-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 12918 // CHECK23-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 12919 // CHECK23-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 12920 // CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 12921 // CHECK23-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 12922 // CHECK23-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 12923 // CHECK23-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 12924 // CHECK23-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 12925 // CHECK23: cond.true: 12926 // CHECK23-NEXT: br label [[COND_END:%.*]] 12927 // CHECK23: cond.false: 12928 // CHECK23-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 12929 // CHECK23-NEXT: br label [[COND_END]] 12930 // CHECK23: cond.end: 12931 // CHECK23-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 12932 // CHECK23-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 12933 // CHECK23-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 12934 // CHECK23-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 12935 // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 12936 // CHECK23: omp.inner.for.cond: 12937 // CHECK23-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36 12938 // CHECK23-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !36 12939 // CHECK23-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] 12940 // CHECK23-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 12941 // CHECK23: omp.inner.for.body: 12942 // CHECK23-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36 12943 // CHECK23-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 12944 // CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 12945 // CHECK23-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !36 12946 // CHECK23-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !36 12947 // CHECK23-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 12948 // CHECK23-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4, !llvm.access.group !36 12949 // CHECK23-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !36 12950 // CHECK23-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32 12951 // CHECK23-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 12952 // CHECK23-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 12953 // CHECK23-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2, !llvm.access.group !36 12954 // CHECK23-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 12955 // CHECK23-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !36 12956 // CHECK23-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1 12957 // CHECK23-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !36 12958 // CHECK23-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 12959 // CHECK23: omp.body.continue: 12960 // CHECK23-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 12961 // CHECK23: omp.inner.for.inc: 12962 // CHECK23-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36 12963 // CHECK23-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP12]], 1 12964 // CHECK23-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36 12965 // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP37:![0-9]+]] 12966 // CHECK23: omp.inner.for.end: 12967 // CHECK23-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 12968 // CHECK23: omp.loop.exit: 12969 // CHECK23-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) 12970 // CHECK23-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 12971 // CHECK23-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 12972 // CHECK23-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 12973 // CHECK23: .omp.final.then: 12974 // CHECK23-NEXT: store i32 10, i32* [[I]], align 4 12975 // CHECK23-NEXT: br label [[DOTOMP_FINAL_DONE]] 12976 // CHECK23: .omp.final.done: 12977 // CHECK23-NEXT: ret void 12978 // 12979