1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ 2 // RUN: %clang_cc1 -DCHECK -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1 3 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 4 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK2 5 // RUN: %clang_cc1 -DCHECK -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK3 6 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 7 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK4 8 9 // RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK5 10 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 11 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK6 12 // RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK7 13 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 14 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK8 15 16 // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9 17 // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 18 // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK10 19 20 // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11 21 // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 22 // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK12 23 24 // expected-no-diagnostics 25 #ifndef HEADER 26 #define HEADER 27 28 struct St { 29 int a, b; 30 St() : a(0), b(0) {} 31 St(const St &st) : a(st.a + st.b), b(0) {} 32 ~St() {} 33 }; 34 35 volatile int g = 1212; 36 volatile int &g1 = g; 37 38 template <class T> 39 struct S { 40 T f; 41 S(T a) : f(a + g) {} 42 S() : f(g) {} 43 S(const S &s, St t = St()) : f(s.f + t.a) {} 44 operator T() { return T(); } 45 ~S() {} 46 }; 47 48 49 template <typename T> 50 T tmain() { 51 S<T> test; 52 T t_var = T(); 53 T vec[] = {1, 2}; 54 S<T> s_arr[] = {1, 2}; 55 S<T> &var = test; 56 #pragma omp target teams distribute firstprivate(t_var, vec, s_arr, var) 57 for (int i = 0; i < 2; ++i) { 58 vec[i] = t_var; 59 s_arr[i] = var; 60 } 61 return T(); 62 } 63 64 S<float> test; 65 int t_var = 333; 66 int vec[] = {1, 2}; 67 S<float> s_arr[] = {1, 2}; 68 S<float> var(3); 69 70 int main() { 71 static int sivar; 72 #ifdef LAMBDA 73 [&]() { 74 #pragma omp target teams distribute firstprivate(g, g1, sivar) 75 for (int i = 0; i < 2; ++i) { 76 77 // Skip global and bound tid vars 78 // skip loop vars 79 g = 1; 80 g1 = 1; 81 sivar = 2; 82 [&]() { 83 g = 2; 84 g1 = 2; 85 sivar = 4; 86 87 }(); 88 } 89 }(); 90 return 0; 91 #else 92 #pragma omp target teams distribute firstprivate(t_var, vec, s_arr, var, sivar) 93 for (int i = 0; i < 2; ++i) { 94 vec[i] = t_var; 95 s_arr[i] = var; 96 sivar += i; 97 } 98 return tmain<int>(); 99 #endif 100 } 101 102 103 104 105 106 // Skip global and bound tid vars 107 // Skip temp vars for loop 108 109 // param copy 110 111 // T_VAR and SIVAR 112 113 // preparation vars 114 115 // firstprivate vec(vec): copy from *_addr into priv1 and then from priv1 into priv2 116 117 // firstprivate(s_arr) 118 119 // firstprivate(var) 120 121 122 123 124 125 126 // Skip global and bound tid vars 127 // Skip temp vars for loop 128 129 // param copy 130 131 // T_VAR and preparation variables 132 133 134 // firstprivate vec(vec): copy from *_addr into priv1 and then from priv1 into priv2 135 136 // firstprivate(s_arr) 137 138 // firstprivate(var) 139 140 141 #endif 142 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init 143 // CHECK1-SAME: () #[[ATTR0:[0-9]+]] { 144 // CHECK1-NEXT: entry: 145 // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) 146 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] 147 // CHECK1-NEXT: ret void 148 // 149 // 150 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 151 // CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 152 // CHECK1-NEXT: entry: 153 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 154 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 155 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 156 // CHECK1-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) 157 // CHECK1-NEXT: ret void 158 // 159 // 160 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 161 // CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 162 // CHECK1-NEXT: entry: 163 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 164 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 165 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 166 // CHECK1-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 167 // CHECK1-NEXT: ret void 168 // 169 // 170 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 171 // CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 172 // CHECK1-NEXT: entry: 173 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 174 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 175 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 176 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 177 // CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 178 // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 179 // CHECK1-NEXT: store float [[CONV]], float* [[F]], align 4 180 // CHECK1-NEXT: ret void 181 // 182 // 183 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 184 // CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 185 // CHECK1-NEXT: entry: 186 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 187 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 188 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 189 // CHECK1-NEXT: ret void 190 // 191 // 192 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 193 // CHECK1-SAME: () #[[ATTR0]] { 194 // CHECK1-NEXT: entry: 195 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) 196 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) 197 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] 198 // CHECK1-NEXT: ret void 199 // 200 // 201 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 202 // CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 203 // CHECK1-NEXT: entry: 204 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 205 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 206 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 207 // CHECK1-NEXT: store float [[A]], float* [[A_ADDR]], align 4 208 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 209 // CHECK1-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 210 // CHECK1-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) 211 // CHECK1-NEXT: ret void 212 // 213 // 214 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 215 // CHECK1-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { 216 // CHECK1-NEXT: entry: 217 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 218 // CHECK1-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 219 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 220 // CHECK1: arraydestroy.body: 221 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 222 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 223 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 224 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) 225 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 226 // CHECK1: arraydestroy.done1: 227 // CHECK1-NEXT: ret void 228 // 229 // 230 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 231 // CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 232 // CHECK1-NEXT: entry: 233 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 234 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 235 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 236 // CHECK1-NEXT: store float [[A]], float* [[A_ADDR]], align 4 237 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 238 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 239 // CHECK1-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 240 // CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 241 // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 242 // CHECK1-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 243 // CHECK1-NEXT: store float [[ADD]], float* [[F]], align 4 244 // CHECK1-NEXT: ret void 245 // 246 // 247 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 248 // CHECK1-SAME: () #[[ATTR0]] { 249 // CHECK1-NEXT: entry: 250 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) 251 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] 252 // CHECK1-NEXT: ret void 253 // 254 // 255 // CHECK1-LABEL: define {{[^@]+}}@main 256 // CHECK1-SAME: () #[[ATTR3:[0-9]+]] { 257 // CHECK1-NEXT: entry: 258 // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 259 // CHECK1-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 260 // CHECK1-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 261 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8 262 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8 263 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8 264 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 265 // CHECK1-NEXT: store i32 0, i32* [[RETVAL]], align 4 266 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* @t_var, align 4 267 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* 268 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 269 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 270 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 271 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* 272 // CHECK1-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4 273 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 274 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 275 // CHECK1-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to [2 x i32]** 276 // CHECK1-NEXT: store [2 x i32]* @vec, [2 x i32]** [[TMP5]], align 8 277 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 278 // CHECK1-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to [2 x i32]** 279 // CHECK1-NEXT: store [2 x i32]* @vec, [2 x i32]** [[TMP7]], align 8 280 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 281 // CHECK1-NEXT: store i8* null, i8** [[TMP8]], align 8 282 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 283 // CHECK1-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* 284 // CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP10]], align 8 285 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 286 // CHECK1-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64* 287 // CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP12]], align 8 288 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 289 // CHECK1-NEXT: store i8* null, i8** [[TMP13]], align 8 290 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 291 // CHECK1-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x %struct.S]** 292 // CHECK1-NEXT: store [2 x %struct.S]* @s_arr, [2 x %struct.S]** [[TMP15]], align 8 293 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 294 // CHECK1-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to [2 x %struct.S]** 295 // CHECK1-NEXT: store [2 x %struct.S]* @s_arr, [2 x %struct.S]** [[TMP17]], align 8 296 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 297 // CHECK1-NEXT: store i8* null, i8** [[TMP18]], align 8 298 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 299 // CHECK1-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to %struct.S** 300 // CHECK1-NEXT: store %struct.S* @var, %struct.S** [[TMP20]], align 8 301 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 302 // CHECK1-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to %struct.S** 303 // CHECK1-NEXT: store %struct.S* @var, %struct.S** [[TMP22]], align 8 304 // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 305 // CHECK1-NEXT: store i8* null, i8** [[TMP23]], align 8 306 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 307 // CHECK1-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i64* 308 // CHECK1-NEXT: store i64 [[TMP3]], i64* [[TMP25]], align 8 309 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 310 // CHECK1-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64* 311 // CHECK1-NEXT: store i64 [[TMP3]], i64* [[TMP27]], align 8 312 // CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 313 // CHECK1-NEXT: store i8* null, i8** [[TMP28]], align 8 314 // CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 315 // CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 316 // CHECK1-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 2) 317 // CHECK1-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92.region_id, i32 5, i8** [[TMP29]], i8** [[TMP30]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 318 // CHECK1-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 319 // CHECK1-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 320 // CHECK1: omp_offload.failed: 321 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92([2 x i32]* @vec, i64 [[TMP1]], [2 x %struct.S]* @s_arr, %struct.S* @var, i64 [[TMP3]]) #[[ATTR2]] 322 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 323 // CHECK1: omp_offload.cont: 324 // CHECK1-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() 325 // CHECK1-NEXT: ret i32 [[CALL]] 326 // 327 // 328 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92 329 // CHECK1-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR4:[0-9]+]] { 330 // CHECK1-NEXT: entry: 331 // CHECK1-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 332 // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 333 // CHECK1-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8 334 // CHECK1-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8 335 // CHECK1-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 336 // CHECK1-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 337 // CHECK1-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 338 // CHECK1-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 339 // CHECK1-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 340 // CHECK1-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 341 // CHECK1-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 342 // CHECK1-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 343 // CHECK1-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 344 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* 345 // CHECK1-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 346 // CHECK1-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 347 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* 348 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 349 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* 350 // CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 351 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 352 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 8 353 // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* 354 // CHECK1-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4 355 // CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 356 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP2]], i64 [[TMP6]]) 357 // CHECK1-NEXT: ret void 358 // 359 // 360 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. 361 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR4]] { 362 // CHECK1-NEXT: entry: 363 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 364 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 365 // CHECK1-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 366 // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 367 // CHECK1-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8 368 // CHECK1-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8 369 // CHECK1-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 370 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 371 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 372 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 373 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 374 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 375 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 376 // CHECK1-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 377 // CHECK1-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S], align 4 378 // CHECK1-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 379 // CHECK1-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S:%.*]], align 4 380 // CHECK1-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 381 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 382 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 383 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 384 // CHECK1-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 385 // CHECK1-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 386 // CHECK1-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 387 // CHECK1-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 388 // CHECK1-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 389 // CHECK1-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 390 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* 391 // CHECK1-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 392 // CHECK1-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 393 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* 394 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 395 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 396 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 397 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 398 // CHECK1-NEXT: [[TMP3:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8* 399 // CHECK1-NEXT: [[TMP4:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* 400 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i64 8, i1 false) 401 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 402 // CHECK1-NEXT: [[TMP5:%.*]] = bitcast [2 x %struct.S]* [[TMP1]] to %struct.S* 403 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 404 // CHECK1-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP6]] 405 // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 406 // CHECK1: omp.arraycpy.body: 407 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 408 // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 409 // CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) 410 // CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) 411 // CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] 412 // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 413 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 414 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] 415 // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] 416 // CHECK1: omp.arraycpy.done4: 417 // CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) 418 // CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP6]]) 419 // CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] 420 // CHECK1-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 421 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 422 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 423 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 424 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP9]], 1 425 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 426 // CHECK1: cond.true: 427 // CHECK1-NEXT: br label [[COND_END:%.*]] 428 // CHECK1: cond.false: 429 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 430 // CHECK1-NEXT: br label [[COND_END]] 431 // CHECK1: cond.end: 432 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ] 433 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 434 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 435 // CHECK1-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 436 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 437 // CHECK1: omp.inner.for.cond: 438 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 439 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 440 // CHECK1-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] 441 // CHECK1-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 442 // CHECK1: omp.inner.for.cond.cleanup: 443 // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 444 // CHECK1: omp.inner.for.body: 445 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 446 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1 447 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 448 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4 449 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[CONV]], align 8 450 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 451 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64 452 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 [[IDXPROM]] 453 // CHECK1-NEXT: store i32 [[TMP15]], i32* [[ARRAYIDX]], align 4 454 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4 455 // CHECK1-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP17]] to i64 456 // CHECK1-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i64 0, i64 [[IDXPROM8]] 457 // CHECK1-NEXT: [[TMP18:%.*]] = bitcast %struct.S* [[ARRAYIDX9]] to i8* 458 // CHECK1-NEXT: [[TMP19:%.*]] = bitcast %struct.S* [[VAR5]] to i8* 459 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP18]], i8* align 4 [[TMP19]], i64 4, i1 false) 460 // CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[I]], align 4 461 // CHECK1-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV1]], align 8 462 // CHECK1-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP21]], [[TMP20]] 463 // CHECK1-NEXT: store i32 [[ADD10]], i32* [[CONV1]], align 8 464 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 465 // CHECK1: omp.body.continue: 466 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 467 // CHECK1: omp.inner.for.inc: 468 // CHECK1-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 469 // CHECK1-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP22]], 1 470 // CHECK1-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4 471 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 472 // CHECK1: omp.inner.for.end: 473 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 474 // CHECK1: omp.loop.exit: 475 // CHECK1-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 476 // CHECK1-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 477 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) 478 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] 479 // CHECK1-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 480 // CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN12]], i64 2 481 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 482 // CHECK1: arraydestroy.body: 483 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP25]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 484 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 485 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 486 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] 487 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] 488 // CHECK1: arraydestroy.done13: 489 // CHECK1-NEXT: ret void 490 // 491 // 492 // CHECK1-LABEL: define {{[^@]+}}@_ZN2StC1Ev 493 // CHECK1-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 494 // CHECK1-NEXT: entry: 495 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 496 // CHECK1-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 497 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 498 // CHECK1-NEXT: call void @_ZN2StC2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) 499 // CHECK1-NEXT: ret void 500 // 501 // 502 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St 503 // CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 504 // CHECK1-NEXT: entry: 505 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 506 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8 507 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 508 // CHECK1-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8 509 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 510 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8 511 // CHECK1-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) 512 // CHECK1-NEXT: ret void 513 // 514 // 515 // CHECK1-LABEL: define {{[^@]+}}@_ZN2StD1Ev 516 // CHECK1-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 517 // CHECK1-NEXT: entry: 518 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 519 // CHECK1-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 520 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 521 // CHECK1-NEXT: call void @_ZN2StD2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR2]] 522 // CHECK1-NEXT: ret void 523 // 524 // 525 // CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 526 // CHECK1-SAME: () #[[ATTR6:[0-9]+]] comdat { 527 // CHECK1-NEXT: entry: 528 // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 529 // CHECK1-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 530 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 531 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 532 // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 533 // CHECK1-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 534 // CHECK1-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 535 // CHECK1-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 536 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8 537 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 538 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 539 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 540 // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) 541 // CHECK1-NEXT: store i32 0, i32* [[T_VAR]], align 4 542 // CHECK1-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 543 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) 544 // CHECK1-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 545 // CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) 546 // CHECK1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 547 // CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) 548 // CHECK1-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 549 // CHECK1-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 550 // CHECK1-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 551 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 552 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* 553 // CHECK1-NEXT: store i32 [[TMP2]], i32* [[CONV]], align 4 554 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 555 // CHECK1-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 556 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 557 // CHECK1-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to [2 x i32]** 558 // CHECK1-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP6]], align 8 559 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 560 // CHECK1-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to [2 x i32]** 561 // CHECK1-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP8]], align 8 562 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 563 // CHECK1-NEXT: store i8* null, i8** [[TMP9]], align 8 564 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 565 // CHECK1-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i64* 566 // CHECK1-NEXT: store i64 [[TMP3]], i64* [[TMP11]], align 8 567 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 568 // CHECK1-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* 569 // CHECK1-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8 570 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 571 // CHECK1-NEXT: store i8* null, i8** [[TMP14]], align 8 572 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 573 // CHECK1-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [2 x %struct.S.0]** 574 // CHECK1-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP16]], align 8 575 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 576 // CHECK1-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [2 x %struct.S.0]** 577 // CHECK1-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP18]], align 8 578 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 579 // CHECK1-NEXT: store i8* null, i8** [[TMP19]], align 8 580 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 581 // CHECK1-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to %struct.S.0** 582 // CHECK1-NEXT: store %struct.S.0* [[TMP4]], %struct.S.0** [[TMP21]], align 8 583 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 584 // CHECK1-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.S.0** 585 // CHECK1-NEXT: store %struct.S.0* [[TMP4]], %struct.S.0** [[TMP23]], align 8 586 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 587 // CHECK1-NEXT: store i8* null, i8** [[TMP24]], align 8 588 // CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 589 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 590 // CHECK1-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 2) 591 // CHECK1-NEXT: [[TMP27:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.region_id, i32 4, i8** [[TMP25]], i8** [[TMP26]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.4, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.5, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 592 // CHECK1-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0 593 // CHECK1-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 594 // CHECK1: omp_offload.failed: 595 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56([2 x i32]* [[VEC]], i64 [[TMP3]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[TMP4]]) #[[ATTR2]] 596 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 597 // CHECK1: omp_offload.cont: 598 // CHECK1-NEXT: store i32 0, i32* [[RETVAL]], align 4 599 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 600 // CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 601 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 602 // CHECK1: arraydestroy.body: 603 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP29]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 604 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 605 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 606 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 607 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] 608 // CHECK1: arraydestroy.done2: 609 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] 610 // CHECK1-NEXT: [[TMP30:%.*]] = load i32, i32* [[RETVAL]], align 4 611 // CHECK1-NEXT: ret i32 [[TMP30]] 612 // 613 // 614 // CHECK1-LABEL: define {{[^@]+}}@_ZN2StC2Ev 615 // CHECK1-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 616 // CHECK1-NEXT: entry: 617 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 618 // CHECK1-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 619 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 620 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[THIS1]], i32 0, i32 0 621 // CHECK1-NEXT: store i32 0, i32* [[A]], align 4 622 // CHECK1-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1 623 // CHECK1-NEXT: store i32 0, i32* [[B]], align 4 624 // CHECK1-NEXT: ret void 625 // 626 // 627 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St 628 // CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 629 // CHECK1-NEXT: entry: 630 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 631 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8 632 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 633 // CHECK1-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8 634 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 635 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 636 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8 637 // CHECK1-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[TMP0]], i32 0, i32 0 638 // CHECK1-NEXT: [[TMP1:%.*]] = load float, float* [[F2]], align 4 639 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0 640 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 641 // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to float 642 // CHECK1-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]] 643 // CHECK1-NEXT: store float [[ADD]], float* [[F]], align 4 644 // CHECK1-NEXT: ret void 645 // 646 // 647 // CHECK1-LABEL: define {{[^@]+}}@_ZN2StD2Ev 648 // CHECK1-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 649 // CHECK1-NEXT: entry: 650 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 651 // CHECK1-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 652 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 653 // CHECK1-NEXT: ret void 654 // 655 // 656 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 657 // CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 658 // CHECK1-NEXT: entry: 659 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 660 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 661 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 662 // CHECK1-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) 663 // CHECK1-NEXT: ret void 664 // 665 // 666 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 667 // CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 668 // CHECK1-NEXT: entry: 669 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 670 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 671 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 672 // CHECK1-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 673 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 674 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 675 // CHECK1-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) 676 // CHECK1-NEXT: ret void 677 // 678 // 679 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56 680 // CHECK1-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { 681 // CHECK1-NEXT: entry: 682 // CHECK1-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 683 // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 684 // CHECK1-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8 685 // CHECK1-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8 686 // CHECK1-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 687 // CHECK1-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 688 // CHECK1-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 689 // CHECK1-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 690 // CHECK1-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 691 // CHECK1-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 692 // CHECK1-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 693 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* 694 // CHECK1-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 695 // CHECK1-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 696 // CHECK1-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8 697 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 698 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* 699 // CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4 700 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 701 // CHECK1-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 702 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP5]]) 703 // CHECK1-NEXT: ret void 704 // 705 // 706 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..3 707 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { 708 // CHECK1-NEXT: entry: 709 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 710 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 711 // CHECK1-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 712 // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 713 // CHECK1-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8 714 // CHECK1-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8 715 // CHECK1-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 716 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 717 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 718 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 719 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 720 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 721 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 722 // CHECK1-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 723 // CHECK1-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 724 // CHECK1-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 725 // CHECK1-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 726 // CHECK1-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 727 // CHECK1-NEXT: [[_TMP7:%.*]] = alloca %struct.S.0*, align 8 728 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 729 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 730 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 731 // CHECK1-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 732 // CHECK1-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 733 // CHECK1-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 734 // CHECK1-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 735 // CHECK1-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 736 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* 737 // CHECK1-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 738 // CHECK1-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 739 // CHECK1-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8 740 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 741 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 742 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 743 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 744 // CHECK1-NEXT: [[TMP3:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8* 745 // CHECK1-NEXT: [[TMP4:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* 746 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i64 8, i1 false) 747 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 748 // CHECK1-NEXT: [[TMP5:%.*]] = bitcast [2 x %struct.S.0]* [[TMP1]] to %struct.S.0* 749 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 750 // CHECK1-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP6]] 751 // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 752 // CHECK1: omp.arraycpy.body: 753 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 754 // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 755 // CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) 756 // CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) 757 // CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] 758 // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 759 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 760 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] 761 // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] 762 // CHECK1: omp.arraycpy.done4: 763 // CHECK1-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 764 // CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) 765 // CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP7]], %struct.St* [[AGG_TMP6]]) 766 // CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] 767 // CHECK1-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP7]], align 8 768 // CHECK1-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 769 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 770 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 771 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 772 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP10]], 1 773 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 774 // CHECK1: cond.true: 775 // CHECK1-NEXT: br label [[COND_END:%.*]] 776 // CHECK1: cond.false: 777 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 778 // CHECK1-NEXT: br label [[COND_END]] 779 // CHECK1: cond.end: 780 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] 781 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 782 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 783 // CHECK1-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 784 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 785 // CHECK1: omp.inner.for.cond: 786 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 787 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 788 // CHECK1-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] 789 // CHECK1-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 790 // CHECK1: omp.inner.for.cond.cleanup: 791 // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 792 // CHECK1: omp.inner.for.body: 793 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 794 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 795 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 796 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4 797 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV]], align 8 798 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4 799 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64 800 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 [[IDXPROM]] 801 // CHECK1-NEXT: store i32 [[TMP16]], i32* [[ARRAYIDX]], align 4 802 // CHECK1-NEXT: [[TMP18:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 8 803 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 804 // CHECK1-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP19]] to i64 805 // CHECK1-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i64 0, i64 [[IDXPROM9]] 806 // CHECK1-NEXT: [[TMP20:%.*]] = bitcast %struct.S.0* [[ARRAYIDX10]] to i8* 807 // CHECK1-NEXT: [[TMP21:%.*]] = bitcast %struct.S.0* [[TMP18]] to i8* 808 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i64 4, i1 false) 809 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 810 // CHECK1: omp.body.continue: 811 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 812 // CHECK1: omp.inner.for.inc: 813 // CHECK1-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 814 // CHECK1-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP22]], 1 815 // CHECK1-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4 816 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 817 // CHECK1: omp.inner.for.end: 818 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 819 // CHECK1: omp.loop.exit: 820 // CHECK1-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 821 // CHECK1-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 822 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) 823 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] 824 // CHECK1-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 825 // CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN12]], i64 2 826 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 827 // CHECK1: arraydestroy.body: 828 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP25]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 829 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 830 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 831 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] 832 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] 833 // CHECK1: arraydestroy.done13: 834 // CHECK1-NEXT: ret void 835 // 836 // 837 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St 838 // CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 839 // CHECK1-NEXT: entry: 840 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 841 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8 842 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 843 // CHECK1-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8 844 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 845 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8 846 // CHECK1-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) 847 // CHECK1-NEXT: ret void 848 // 849 // 850 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 851 // CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 852 // CHECK1-NEXT: entry: 853 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 854 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 855 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 856 // CHECK1-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 857 // CHECK1-NEXT: ret void 858 // 859 // 860 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 861 // CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 862 // CHECK1-NEXT: entry: 863 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 864 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 865 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 866 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 867 // CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 868 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 869 // CHECK1-NEXT: ret void 870 // 871 // 872 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 873 // CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 874 // CHECK1-NEXT: entry: 875 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 876 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 877 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 878 // CHECK1-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 879 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 880 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 881 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 882 // CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 883 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] 884 // CHECK1-NEXT: store i32 [[ADD]], i32* [[F]], align 4 885 // CHECK1-NEXT: ret void 886 // 887 // 888 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St 889 // CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 890 // CHECK1-NEXT: entry: 891 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 892 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8 893 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 894 // CHECK1-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8 895 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 896 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 897 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8 898 // CHECK1-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[TMP0]], i32 0, i32 0 899 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[F2]], align 4 900 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0 901 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 902 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]] 903 // CHECK1-NEXT: store i32 [[ADD]], i32* [[F]], align 4 904 // CHECK1-NEXT: ret void 905 // 906 // 907 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 908 // CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 909 // CHECK1-NEXT: entry: 910 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 911 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 912 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 913 // CHECK1-NEXT: ret void 914 // 915 // 916 // CHECK1-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_firstprivate_codegen.cpp 917 // CHECK1-SAME: () #[[ATTR0]] { 918 // CHECK1-NEXT: entry: 919 // CHECK1-NEXT: call void @__cxx_global_var_init() 920 // CHECK1-NEXT: call void @__cxx_global_var_init.1() 921 // CHECK1-NEXT: call void @__cxx_global_var_init.2() 922 // CHECK1-NEXT: ret void 923 // 924 // 925 // CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 926 // CHECK1-SAME: () #[[ATTR0]] { 927 // CHECK1-NEXT: entry: 928 // CHECK1-NEXT: call void @__tgt_register_requires(i64 1) 929 // CHECK1-NEXT: ret void 930 // 931 // 932 // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_var_init 933 // CHECK2-SAME: () #[[ATTR0:[0-9]+]] { 934 // CHECK2-NEXT: entry: 935 // CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) 936 // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] 937 // CHECK2-NEXT: ret void 938 // 939 // 940 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 941 // CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 942 // CHECK2-NEXT: entry: 943 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 944 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 945 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 946 // CHECK2-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) 947 // CHECK2-NEXT: ret void 948 // 949 // 950 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 951 // CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 952 // CHECK2-NEXT: entry: 953 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 954 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 955 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 956 // CHECK2-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 957 // CHECK2-NEXT: ret void 958 // 959 // 960 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 961 // CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 962 // CHECK2-NEXT: entry: 963 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 964 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 965 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 966 // CHECK2-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 967 // CHECK2-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 968 // CHECK2-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 969 // CHECK2-NEXT: store float [[CONV]], float* [[F]], align 4 970 // CHECK2-NEXT: ret void 971 // 972 // 973 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 974 // CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 975 // CHECK2-NEXT: entry: 976 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 977 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 978 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 979 // CHECK2-NEXT: ret void 980 // 981 // 982 // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 983 // CHECK2-SAME: () #[[ATTR0]] { 984 // CHECK2-NEXT: entry: 985 // CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) 986 // CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) 987 // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] 988 // CHECK2-NEXT: ret void 989 // 990 // 991 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 992 // CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 993 // CHECK2-NEXT: entry: 994 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 995 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 996 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 997 // CHECK2-NEXT: store float [[A]], float* [[A_ADDR]], align 4 998 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 999 // CHECK2-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 1000 // CHECK2-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) 1001 // CHECK2-NEXT: ret void 1002 // 1003 // 1004 // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 1005 // CHECK2-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { 1006 // CHECK2-NEXT: entry: 1007 // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 1008 // CHECK2-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 1009 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1010 // CHECK2: arraydestroy.body: 1011 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1012 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 1013 // CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1014 // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) 1015 // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 1016 // CHECK2: arraydestroy.done1: 1017 // CHECK2-NEXT: ret void 1018 // 1019 // 1020 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 1021 // CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1022 // CHECK2-NEXT: entry: 1023 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 1024 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 1025 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 1026 // CHECK2-NEXT: store float [[A]], float* [[A_ADDR]], align 4 1027 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 1028 // CHECK2-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 1029 // CHECK2-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 1030 // CHECK2-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 1031 // CHECK2-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 1032 // CHECK2-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 1033 // CHECK2-NEXT: store float [[ADD]], float* [[F]], align 4 1034 // CHECK2-NEXT: ret void 1035 // 1036 // 1037 // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 1038 // CHECK2-SAME: () #[[ATTR0]] { 1039 // CHECK2-NEXT: entry: 1040 // CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) 1041 // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] 1042 // CHECK2-NEXT: ret void 1043 // 1044 // 1045 // CHECK2-LABEL: define {{[^@]+}}@main 1046 // CHECK2-SAME: () #[[ATTR3:[0-9]+]] { 1047 // CHECK2-NEXT: entry: 1048 // CHECK2-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1049 // CHECK2-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 1050 // CHECK2-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 1051 // CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8 1052 // CHECK2-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8 1053 // CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8 1054 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4 1055 // CHECK2-NEXT: store i32 0, i32* [[RETVAL]], align 4 1056 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* @t_var, align 4 1057 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* 1058 // CHECK2-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 1059 // CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 1060 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 1061 // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* 1062 // CHECK2-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4 1063 // CHECK2-NEXT: [[TMP3:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 1064 // CHECK2-NEXT: [[TMP4:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1065 // CHECK2-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to [2 x i32]** 1066 // CHECK2-NEXT: store [2 x i32]* @vec, [2 x i32]** [[TMP5]], align 8 1067 // CHECK2-NEXT: [[TMP6:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1068 // CHECK2-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to [2 x i32]** 1069 // CHECK2-NEXT: store [2 x i32]* @vec, [2 x i32]** [[TMP7]], align 8 1070 // CHECK2-NEXT: [[TMP8:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 1071 // CHECK2-NEXT: store i8* null, i8** [[TMP8]], align 8 1072 // CHECK2-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1073 // CHECK2-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* 1074 // CHECK2-NEXT: store i64 [[TMP1]], i64* [[TMP10]], align 8 1075 // CHECK2-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1076 // CHECK2-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64* 1077 // CHECK2-NEXT: store i64 [[TMP1]], i64* [[TMP12]], align 8 1078 // CHECK2-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 1079 // CHECK2-NEXT: store i8* null, i8** [[TMP13]], align 8 1080 // CHECK2-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1081 // CHECK2-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x %struct.S]** 1082 // CHECK2-NEXT: store [2 x %struct.S]* @s_arr, [2 x %struct.S]** [[TMP15]], align 8 1083 // CHECK2-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1084 // CHECK2-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to [2 x %struct.S]** 1085 // CHECK2-NEXT: store [2 x %struct.S]* @s_arr, [2 x %struct.S]** [[TMP17]], align 8 1086 // CHECK2-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 1087 // CHECK2-NEXT: store i8* null, i8** [[TMP18]], align 8 1088 // CHECK2-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 1089 // CHECK2-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to %struct.S** 1090 // CHECK2-NEXT: store %struct.S* @var, %struct.S** [[TMP20]], align 8 1091 // CHECK2-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 1092 // CHECK2-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to %struct.S** 1093 // CHECK2-NEXT: store %struct.S* @var, %struct.S** [[TMP22]], align 8 1094 // CHECK2-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 1095 // CHECK2-NEXT: store i8* null, i8** [[TMP23]], align 8 1096 // CHECK2-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 1097 // CHECK2-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i64* 1098 // CHECK2-NEXT: store i64 [[TMP3]], i64* [[TMP25]], align 8 1099 // CHECK2-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 1100 // CHECK2-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64* 1101 // CHECK2-NEXT: store i64 [[TMP3]], i64* [[TMP27]], align 8 1102 // CHECK2-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 1103 // CHECK2-NEXT: store i8* null, i8** [[TMP28]], align 8 1104 // CHECK2-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1105 // CHECK2-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1106 // CHECK2-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 2) 1107 // CHECK2-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92.region_id, i32 5, i8** [[TMP29]], i8** [[TMP30]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 1108 // CHECK2-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 1109 // CHECK2-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1110 // CHECK2: omp_offload.failed: 1111 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92([2 x i32]* @vec, i64 [[TMP1]], [2 x %struct.S]* @s_arr, %struct.S* @var, i64 [[TMP3]]) #[[ATTR2]] 1112 // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]] 1113 // CHECK2: omp_offload.cont: 1114 // CHECK2-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() 1115 // CHECK2-NEXT: ret i32 [[CALL]] 1116 // 1117 // 1118 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92 1119 // CHECK2-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR4:[0-9]+]] { 1120 // CHECK2-NEXT: entry: 1121 // CHECK2-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 1122 // CHECK2-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 1123 // CHECK2-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8 1124 // CHECK2-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8 1125 // CHECK2-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 1126 // CHECK2-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 1127 // CHECK2-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 1128 // CHECK2-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 1129 // CHECK2-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 1130 // CHECK2-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 1131 // CHECK2-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 1132 // CHECK2-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 1133 // CHECK2-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 1134 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* 1135 // CHECK2-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 1136 // CHECK2-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 1137 // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* 1138 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 1139 // CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* 1140 // CHECK2-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 1141 // CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 1142 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 8 1143 // CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* 1144 // CHECK2-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4 1145 // CHECK2-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 1146 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP2]], i64 [[TMP6]]) 1147 // CHECK2-NEXT: ret void 1148 // 1149 // 1150 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. 1151 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR4]] { 1152 // CHECK2-NEXT: entry: 1153 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1154 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1155 // CHECK2-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 1156 // CHECK2-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 1157 // CHECK2-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8 1158 // CHECK2-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8 1159 // CHECK2-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 1160 // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1161 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4 1162 // CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1163 // CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1164 // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1165 // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1166 // CHECK2-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 1167 // CHECK2-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S], align 4 1168 // CHECK2-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 1169 // CHECK2-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S:%.*]], align 4 1170 // CHECK2-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 1171 // CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4 1172 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1173 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1174 // CHECK2-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 1175 // CHECK2-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 1176 // CHECK2-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 1177 // CHECK2-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 1178 // CHECK2-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 1179 // CHECK2-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 1180 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* 1181 // CHECK2-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 1182 // CHECK2-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 1183 // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* 1184 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1185 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 1186 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 1187 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1188 // CHECK2-NEXT: [[TMP3:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8* 1189 // CHECK2-NEXT: [[TMP4:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* 1190 // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i64 8, i1 false) 1191 // CHECK2-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 1192 // CHECK2-NEXT: [[TMP5:%.*]] = bitcast [2 x %struct.S]* [[TMP1]] to %struct.S* 1193 // CHECK2-NEXT: [[TMP6:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 1194 // CHECK2-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP6]] 1195 // CHECK2-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 1196 // CHECK2: omp.arraycpy.body: 1197 // CHECK2-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 1198 // CHECK2-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 1199 // CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) 1200 // CHECK2-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) 1201 // CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] 1202 // CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 1203 // CHECK2-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 1204 // CHECK2-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] 1205 // CHECK2-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] 1206 // CHECK2: omp.arraycpy.done4: 1207 // CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) 1208 // CHECK2-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP6]]) 1209 // CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] 1210 // CHECK2-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 1211 // CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 1212 // CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 1213 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1214 // CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP9]], 1 1215 // CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1216 // CHECK2: cond.true: 1217 // CHECK2-NEXT: br label [[COND_END:%.*]] 1218 // CHECK2: cond.false: 1219 // CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1220 // CHECK2-NEXT: br label [[COND_END]] 1221 // CHECK2: cond.end: 1222 // CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ] 1223 // CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 1224 // CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1225 // CHECK2-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 1226 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1227 // CHECK2: omp.inner.for.cond: 1228 // CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1229 // CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1230 // CHECK2-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] 1231 // CHECK2-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 1232 // CHECK2: omp.inner.for.cond.cleanup: 1233 // CHECK2-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 1234 // CHECK2: omp.inner.for.body: 1235 // CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1236 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1 1237 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1238 // CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4 1239 // CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[CONV]], align 8 1240 // CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 1241 // CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64 1242 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 [[IDXPROM]] 1243 // CHECK2-NEXT: store i32 [[TMP15]], i32* [[ARRAYIDX]], align 4 1244 // CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4 1245 // CHECK2-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP17]] to i64 1246 // CHECK2-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i64 0, i64 [[IDXPROM8]] 1247 // CHECK2-NEXT: [[TMP18:%.*]] = bitcast %struct.S* [[ARRAYIDX9]] to i8* 1248 // CHECK2-NEXT: [[TMP19:%.*]] = bitcast %struct.S* [[VAR5]] to i8* 1249 // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP18]], i8* align 4 [[TMP19]], i64 4, i1 false) 1250 // CHECK2-NEXT: [[TMP20:%.*]] = load i32, i32* [[I]], align 4 1251 // CHECK2-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV1]], align 8 1252 // CHECK2-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP21]], [[TMP20]] 1253 // CHECK2-NEXT: store i32 [[ADD10]], i32* [[CONV1]], align 8 1254 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1255 // CHECK2: omp.body.continue: 1256 // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1257 // CHECK2: omp.inner.for.inc: 1258 // CHECK2-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1259 // CHECK2-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP22]], 1 1260 // CHECK2-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4 1261 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]] 1262 // CHECK2: omp.inner.for.end: 1263 // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1264 // CHECK2: omp.loop.exit: 1265 // CHECK2-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 1266 // CHECK2-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 1267 // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) 1268 // CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] 1269 // CHECK2-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 1270 // CHECK2-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN12]], i64 2 1271 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1272 // CHECK2: arraydestroy.body: 1273 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP25]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1274 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 1275 // CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1276 // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] 1277 // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] 1278 // CHECK2: arraydestroy.done13: 1279 // CHECK2-NEXT: ret void 1280 // 1281 // 1282 // CHECK2-LABEL: define {{[^@]+}}@_ZN2StC1Ev 1283 // CHECK2-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1284 // CHECK2-NEXT: entry: 1285 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 1286 // CHECK2-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 1287 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 1288 // CHECK2-NEXT: call void @_ZN2StC2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) 1289 // CHECK2-NEXT: ret void 1290 // 1291 // 1292 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St 1293 // CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1294 // CHECK2-NEXT: entry: 1295 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 1296 // CHECK2-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8 1297 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 1298 // CHECK2-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8 1299 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 1300 // CHECK2-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8 1301 // CHECK2-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) 1302 // CHECK2-NEXT: ret void 1303 // 1304 // 1305 // CHECK2-LABEL: define {{[^@]+}}@_ZN2StD1Ev 1306 // CHECK2-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1307 // CHECK2-NEXT: entry: 1308 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 1309 // CHECK2-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 1310 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 1311 // CHECK2-NEXT: call void @_ZN2StD2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR2]] 1312 // CHECK2-NEXT: ret void 1313 // 1314 // 1315 // CHECK2-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 1316 // CHECK2-SAME: () #[[ATTR6:[0-9]+]] comdat { 1317 // CHECK2-NEXT: entry: 1318 // CHECK2-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1319 // CHECK2-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 1320 // CHECK2-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 1321 // CHECK2-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 1322 // CHECK2-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 1323 // CHECK2-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 1324 // CHECK2-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 1325 // CHECK2-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 1326 // CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8 1327 // CHECK2-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 1328 // CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 1329 // CHECK2-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 1330 // CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) 1331 // CHECK2-NEXT: store i32 0, i32* [[T_VAR]], align 4 1332 // CHECK2-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 1333 // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) 1334 // CHECK2-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 1335 // CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) 1336 // CHECK2-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 1337 // CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) 1338 // CHECK2-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 1339 // CHECK2-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 1340 // CHECK2-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 1341 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 1342 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* 1343 // CHECK2-NEXT: store i32 [[TMP2]], i32* [[CONV]], align 4 1344 // CHECK2-NEXT: [[TMP3:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 1345 // CHECK2-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 1346 // CHECK2-NEXT: [[TMP5:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1347 // CHECK2-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to [2 x i32]** 1348 // CHECK2-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP6]], align 8 1349 // CHECK2-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1350 // CHECK2-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to [2 x i32]** 1351 // CHECK2-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP8]], align 8 1352 // CHECK2-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 1353 // CHECK2-NEXT: store i8* null, i8** [[TMP9]], align 8 1354 // CHECK2-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1355 // CHECK2-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i64* 1356 // CHECK2-NEXT: store i64 [[TMP3]], i64* [[TMP11]], align 8 1357 // CHECK2-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1358 // CHECK2-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* 1359 // CHECK2-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8 1360 // CHECK2-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 1361 // CHECK2-NEXT: store i8* null, i8** [[TMP14]], align 8 1362 // CHECK2-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1363 // CHECK2-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [2 x %struct.S.0]** 1364 // CHECK2-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP16]], align 8 1365 // CHECK2-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1366 // CHECK2-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [2 x %struct.S.0]** 1367 // CHECK2-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP18]], align 8 1368 // CHECK2-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 1369 // CHECK2-NEXT: store i8* null, i8** [[TMP19]], align 8 1370 // CHECK2-NEXT: [[TMP20:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 1371 // CHECK2-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to %struct.S.0** 1372 // CHECK2-NEXT: store %struct.S.0* [[TMP4]], %struct.S.0** [[TMP21]], align 8 1373 // CHECK2-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 1374 // CHECK2-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.S.0** 1375 // CHECK2-NEXT: store %struct.S.0* [[TMP4]], %struct.S.0** [[TMP23]], align 8 1376 // CHECK2-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 1377 // CHECK2-NEXT: store i8* null, i8** [[TMP24]], align 8 1378 // CHECK2-NEXT: [[TMP25:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1379 // CHECK2-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1380 // CHECK2-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 2) 1381 // CHECK2-NEXT: [[TMP27:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.region_id, i32 4, i8** [[TMP25]], i8** [[TMP26]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.4, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.5, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 1382 // CHECK2-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0 1383 // CHECK2-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1384 // CHECK2: omp_offload.failed: 1385 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56([2 x i32]* [[VEC]], i64 [[TMP3]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[TMP4]]) #[[ATTR2]] 1386 // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]] 1387 // CHECK2: omp_offload.cont: 1388 // CHECK2-NEXT: store i32 0, i32* [[RETVAL]], align 4 1389 // CHECK2-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 1390 // CHECK2-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 1391 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1392 // CHECK2: arraydestroy.body: 1393 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP29]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1394 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 1395 // CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1396 // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 1397 // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] 1398 // CHECK2: arraydestroy.done2: 1399 // CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] 1400 // CHECK2-NEXT: [[TMP30:%.*]] = load i32, i32* [[RETVAL]], align 4 1401 // CHECK2-NEXT: ret i32 [[TMP30]] 1402 // 1403 // 1404 // CHECK2-LABEL: define {{[^@]+}}@_ZN2StC2Ev 1405 // CHECK2-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1406 // CHECK2-NEXT: entry: 1407 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 1408 // CHECK2-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 1409 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 1410 // CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[THIS1]], i32 0, i32 0 1411 // CHECK2-NEXT: store i32 0, i32* [[A]], align 4 1412 // CHECK2-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1 1413 // CHECK2-NEXT: store i32 0, i32* [[B]], align 4 1414 // CHECK2-NEXT: ret void 1415 // 1416 // 1417 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St 1418 // CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1419 // CHECK2-NEXT: entry: 1420 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 1421 // CHECK2-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8 1422 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 1423 // CHECK2-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8 1424 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 1425 // CHECK2-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 1426 // CHECK2-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8 1427 // CHECK2-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[TMP0]], i32 0, i32 0 1428 // CHECK2-NEXT: [[TMP1:%.*]] = load float, float* [[F2]], align 4 1429 // CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0 1430 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 1431 // CHECK2-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to float 1432 // CHECK2-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]] 1433 // CHECK2-NEXT: store float [[ADD]], float* [[F]], align 4 1434 // CHECK2-NEXT: ret void 1435 // 1436 // 1437 // CHECK2-LABEL: define {{[^@]+}}@_ZN2StD2Ev 1438 // CHECK2-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1439 // CHECK2-NEXT: entry: 1440 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 1441 // CHECK2-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 1442 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 1443 // CHECK2-NEXT: ret void 1444 // 1445 // 1446 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 1447 // CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1448 // CHECK2-NEXT: entry: 1449 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 1450 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 1451 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 1452 // CHECK2-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) 1453 // CHECK2-NEXT: ret void 1454 // 1455 // 1456 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 1457 // CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1458 // CHECK2-NEXT: entry: 1459 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 1460 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 1461 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 1462 // CHECK2-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 1463 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 1464 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 1465 // CHECK2-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) 1466 // CHECK2-NEXT: ret void 1467 // 1468 // 1469 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56 1470 // CHECK2-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { 1471 // CHECK2-NEXT: entry: 1472 // CHECK2-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 1473 // CHECK2-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 1474 // CHECK2-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8 1475 // CHECK2-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8 1476 // CHECK2-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 1477 // CHECK2-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 1478 // CHECK2-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 1479 // CHECK2-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 1480 // CHECK2-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 1481 // CHECK2-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 1482 // CHECK2-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 1483 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* 1484 // CHECK2-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 1485 // CHECK2-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 1486 // CHECK2-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8 1487 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 1488 // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* 1489 // CHECK2-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4 1490 // CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 1491 // CHECK2-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 1492 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP5]]) 1493 // CHECK2-NEXT: ret void 1494 // 1495 // 1496 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..3 1497 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { 1498 // CHECK2-NEXT: entry: 1499 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1500 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1501 // CHECK2-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 1502 // CHECK2-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 1503 // CHECK2-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8 1504 // CHECK2-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8 1505 // CHECK2-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 1506 // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1507 // CHECK2-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 1508 // CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1509 // CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1510 // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1511 // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1512 // CHECK2-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 1513 // CHECK2-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 1514 // CHECK2-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 1515 // CHECK2-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 1516 // CHECK2-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 1517 // CHECK2-NEXT: [[_TMP7:%.*]] = alloca %struct.S.0*, align 8 1518 // CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4 1519 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1520 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1521 // CHECK2-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 1522 // CHECK2-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 1523 // CHECK2-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 1524 // CHECK2-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 1525 // CHECK2-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 1526 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* 1527 // CHECK2-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 1528 // CHECK2-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 1529 // CHECK2-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8 1530 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1531 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 1532 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 1533 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1534 // CHECK2-NEXT: [[TMP3:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8* 1535 // CHECK2-NEXT: [[TMP4:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* 1536 // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i64 8, i1 false) 1537 // CHECK2-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 1538 // CHECK2-NEXT: [[TMP5:%.*]] = bitcast [2 x %struct.S.0]* [[TMP1]] to %struct.S.0* 1539 // CHECK2-NEXT: [[TMP6:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 1540 // CHECK2-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP6]] 1541 // CHECK2-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 1542 // CHECK2: omp.arraycpy.body: 1543 // CHECK2-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 1544 // CHECK2-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 1545 // CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) 1546 // CHECK2-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) 1547 // CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] 1548 // CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 1549 // CHECK2-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 1550 // CHECK2-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] 1551 // CHECK2-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] 1552 // CHECK2: omp.arraycpy.done4: 1553 // CHECK2-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 1554 // CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) 1555 // CHECK2-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP7]], %struct.St* [[AGG_TMP6]]) 1556 // CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] 1557 // CHECK2-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP7]], align 8 1558 // CHECK2-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 1559 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 1560 // CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 1561 // CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1562 // CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP10]], 1 1563 // CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1564 // CHECK2: cond.true: 1565 // CHECK2-NEXT: br label [[COND_END:%.*]] 1566 // CHECK2: cond.false: 1567 // CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1568 // CHECK2-NEXT: br label [[COND_END]] 1569 // CHECK2: cond.end: 1570 // CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] 1571 // CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 1572 // CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1573 // CHECK2-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 1574 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1575 // CHECK2: omp.inner.for.cond: 1576 // CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1577 // CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1578 // CHECK2-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] 1579 // CHECK2-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 1580 // CHECK2: omp.inner.for.cond.cleanup: 1581 // CHECK2-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 1582 // CHECK2: omp.inner.for.body: 1583 // CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1584 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 1585 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1586 // CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4 1587 // CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV]], align 8 1588 // CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4 1589 // CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64 1590 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 [[IDXPROM]] 1591 // CHECK2-NEXT: store i32 [[TMP16]], i32* [[ARRAYIDX]], align 4 1592 // CHECK2-NEXT: [[TMP18:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 8 1593 // CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 1594 // CHECK2-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP19]] to i64 1595 // CHECK2-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i64 0, i64 [[IDXPROM9]] 1596 // CHECK2-NEXT: [[TMP20:%.*]] = bitcast %struct.S.0* [[ARRAYIDX10]] to i8* 1597 // CHECK2-NEXT: [[TMP21:%.*]] = bitcast %struct.S.0* [[TMP18]] to i8* 1598 // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i64 4, i1 false) 1599 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1600 // CHECK2: omp.body.continue: 1601 // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1602 // CHECK2: omp.inner.for.inc: 1603 // CHECK2-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1604 // CHECK2-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP22]], 1 1605 // CHECK2-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4 1606 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]] 1607 // CHECK2: omp.inner.for.end: 1608 // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1609 // CHECK2: omp.loop.exit: 1610 // CHECK2-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 1611 // CHECK2-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 1612 // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) 1613 // CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] 1614 // CHECK2-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 1615 // CHECK2-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN12]], i64 2 1616 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1617 // CHECK2: arraydestroy.body: 1618 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP25]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1619 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 1620 // CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1621 // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] 1622 // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] 1623 // CHECK2: arraydestroy.done13: 1624 // CHECK2-NEXT: ret void 1625 // 1626 // 1627 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St 1628 // CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1629 // CHECK2-NEXT: entry: 1630 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 1631 // CHECK2-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8 1632 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 1633 // CHECK2-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8 1634 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 1635 // CHECK2-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8 1636 // CHECK2-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) 1637 // CHECK2-NEXT: ret void 1638 // 1639 // 1640 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 1641 // CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1642 // CHECK2-NEXT: entry: 1643 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 1644 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 1645 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 1646 // CHECK2-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 1647 // CHECK2-NEXT: ret void 1648 // 1649 // 1650 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 1651 // CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1652 // CHECK2-NEXT: entry: 1653 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 1654 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 1655 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 1656 // CHECK2-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 1657 // CHECK2-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 1658 // CHECK2-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 1659 // CHECK2-NEXT: ret void 1660 // 1661 // 1662 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 1663 // CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1664 // CHECK2-NEXT: entry: 1665 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 1666 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 1667 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 1668 // CHECK2-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 1669 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 1670 // CHECK2-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 1671 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 1672 // CHECK2-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 1673 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] 1674 // CHECK2-NEXT: store i32 [[ADD]], i32* [[F]], align 4 1675 // CHECK2-NEXT: ret void 1676 // 1677 // 1678 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St 1679 // CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1680 // CHECK2-NEXT: entry: 1681 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 1682 // CHECK2-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8 1683 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 1684 // CHECK2-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8 1685 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 1686 // CHECK2-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 1687 // CHECK2-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8 1688 // CHECK2-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[TMP0]], i32 0, i32 0 1689 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[F2]], align 4 1690 // CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0 1691 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 1692 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]] 1693 // CHECK2-NEXT: store i32 [[ADD]], i32* [[F]], align 4 1694 // CHECK2-NEXT: ret void 1695 // 1696 // 1697 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 1698 // CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1699 // CHECK2-NEXT: entry: 1700 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 1701 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 1702 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 1703 // CHECK2-NEXT: ret void 1704 // 1705 // 1706 // CHECK2-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_firstprivate_codegen.cpp 1707 // CHECK2-SAME: () #[[ATTR0]] { 1708 // CHECK2-NEXT: entry: 1709 // CHECK2-NEXT: call void @__cxx_global_var_init() 1710 // CHECK2-NEXT: call void @__cxx_global_var_init.1() 1711 // CHECK2-NEXT: call void @__cxx_global_var_init.2() 1712 // CHECK2-NEXT: ret void 1713 // 1714 // 1715 // CHECK2-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 1716 // CHECK2-SAME: () #[[ATTR0]] { 1717 // CHECK2-NEXT: entry: 1718 // CHECK2-NEXT: call void @__tgt_register_requires(i64 1) 1719 // CHECK2-NEXT: ret void 1720 // 1721 // 1722 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init 1723 // CHECK3-SAME: () #[[ATTR0:[0-9]+]] { 1724 // CHECK3-NEXT: entry: 1725 // CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) 1726 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] 1727 // CHECK3-NEXT: ret void 1728 // 1729 // 1730 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 1731 // CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 1732 // CHECK3-NEXT: entry: 1733 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 1734 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 1735 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 1736 // CHECK3-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) 1737 // CHECK3-NEXT: ret void 1738 // 1739 // 1740 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 1741 // CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1742 // CHECK3-NEXT: entry: 1743 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 1744 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 1745 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 1746 // CHECK3-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 1747 // CHECK3-NEXT: ret void 1748 // 1749 // 1750 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 1751 // CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1752 // CHECK3-NEXT: entry: 1753 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 1754 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 1755 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 1756 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 1757 // CHECK3-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 1758 // CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 1759 // CHECK3-NEXT: store float [[CONV]], float* [[F]], align 4 1760 // CHECK3-NEXT: ret void 1761 // 1762 // 1763 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 1764 // CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1765 // CHECK3-NEXT: entry: 1766 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 1767 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 1768 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 1769 // CHECK3-NEXT: ret void 1770 // 1771 // 1772 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 1773 // CHECK3-SAME: () #[[ATTR0]] { 1774 // CHECK3-NEXT: entry: 1775 // CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float 1.000000e+00) 1776 // CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float 2.000000e+00) 1777 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] 1778 // CHECK3-NEXT: ret void 1779 // 1780 // 1781 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 1782 // CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1783 // CHECK3-NEXT: entry: 1784 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 1785 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 1786 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 1787 // CHECK3-NEXT: store float [[A]], float* [[A_ADDR]], align 4 1788 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 1789 // CHECK3-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 1790 // CHECK3-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) 1791 // CHECK3-NEXT: ret void 1792 // 1793 // 1794 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 1795 // CHECK3-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { 1796 // CHECK3-NEXT: entry: 1797 // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 1798 // CHECK3-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4 1799 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1800 // CHECK3: arraydestroy.body: 1801 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1802 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 1803 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1804 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) 1805 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 1806 // CHECK3: arraydestroy.done1: 1807 // CHECK3-NEXT: ret void 1808 // 1809 // 1810 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 1811 // CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1812 // CHECK3-NEXT: entry: 1813 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 1814 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 1815 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 1816 // CHECK3-NEXT: store float [[A]], float* [[A_ADDR]], align 4 1817 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 1818 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 1819 // CHECK3-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 1820 // CHECK3-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 1821 // CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 1822 // CHECK3-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 1823 // CHECK3-NEXT: store float [[ADD]], float* [[F]], align 4 1824 // CHECK3-NEXT: ret void 1825 // 1826 // 1827 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 1828 // CHECK3-SAME: () #[[ATTR0]] { 1829 // CHECK3-NEXT: entry: 1830 // CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) 1831 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] 1832 // CHECK3-NEXT: ret void 1833 // 1834 // 1835 // CHECK3-LABEL: define {{[^@]+}}@main 1836 // CHECK3-SAME: () #[[ATTR3:[0-9]+]] { 1837 // CHECK3-NEXT: entry: 1838 // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1839 // CHECK3-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 1840 // CHECK3-NEXT: [[SIVAR_CASTED:%.*]] = alloca i32, align 4 1841 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4 1842 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4 1843 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4 1844 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 1845 // CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4 1846 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* @t_var, align 4 1847 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[T_VAR_CASTED]], align 4 1848 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 1849 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 1850 // CHECK3-NEXT: store i32 [[TMP2]], i32* [[SIVAR_CASTED]], align 4 1851 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[SIVAR_CASTED]], align 4 1852 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1853 // CHECK3-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to [2 x i32]** 1854 // CHECK3-NEXT: store [2 x i32]* @vec, [2 x i32]** [[TMP5]], align 4 1855 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1856 // CHECK3-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to [2 x i32]** 1857 // CHECK3-NEXT: store [2 x i32]* @vec, [2 x i32]** [[TMP7]], align 4 1858 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 1859 // CHECK3-NEXT: store i8* null, i8** [[TMP8]], align 4 1860 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1861 // CHECK3-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* 1862 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP10]], align 4 1863 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1864 // CHECK3-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32* 1865 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP12]], align 4 1866 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 1867 // CHECK3-NEXT: store i8* null, i8** [[TMP13]], align 4 1868 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1869 // CHECK3-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x %struct.S]** 1870 // CHECK3-NEXT: store [2 x %struct.S]* @s_arr, [2 x %struct.S]** [[TMP15]], align 4 1871 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1872 // CHECK3-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to [2 x %struct.S]** 1873 // CHECK3-NEXT: store [2 x %struct.S]* @s_arr, [2 x %struct.S]** [[TMP17]], align 4 1874 // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 1875 // CHECK3-NEXT: store i8* null, i8** [[TMP18]], align 4 1876 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 1877 // CHECK3-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to %struct.S** 1878 // CHECK3-NEXT: store %struct.S* @var, %struct.S** [[TMP20]], align 4 1879 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 1880 // CHECK3-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to %struct.S** 1881 // CHECK3-NEXT: store %struct.S* @var, %struct.S** [[TMP22]], align 4 1882 // CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 1883 // CHECK3-NEXT: store i8* null, i8** [[TMP23]], align 4 1884 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 1885 // CHECK3-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i32* 1886 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP25]], align 4 1887 // CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 1888 // CHECK3-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i32* 1889 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP27]], align 4 1890 // CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 1891 // CHECK3-NEXT: store i8* null, i8** [[TMP28]], align 4 1892 // CHECK3-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1893 // CHECK3-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1894 // CHECK3-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 2) 1895 // CHECK3-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92.region_id, i32 5, i8** [[TMP29]], i8** [[TMP30]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 1896 // CHECK3-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 1897 // CHECK3-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1898 // CHECK3: omp_offload.failed: 1899 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92([2 x i32]* @vec, i32 [[TMP1]], [2 x %struct.S]* @s_arr, %struct.S* @var, i32 [[TMP3]]) #[[ATTR2]] 1900 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 1901 // CHECK3: omp_offload.cont: 1902 // CHECK3-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() 1903 // CHECK3-NEXT: ret i32 [[CALL]] 1904 // 1905 // 1906 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92 1907 // CHECK3-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR4:[0-9]+]] { 1908 // CHECK3-NEXT: entry: 1909 // CHECK3-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 1910 // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 1911 // CHECK3-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4 1912 // CHECK3-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4 1913 // CHECK3-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4 1914 // CHECK3-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 1915 // CHECK3-NEXT: [[SIVAR_CASTED:%.*]] = alloca i32, align 4 1916 // CHECK3-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 1917 // CHECK3-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 1918 // CHECK3-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4 1919 // CHECK3-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4 1920 // CHECK3-NEXT: store i32 [[SIVAR]], i32* [[SIVAR_ADDR]], align 4 1921 // CHECK3-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 1922 // CHECK3-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4 1923 // CHECK3-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4 1924 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 1925 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[T_VAR_CASTED]], align 4 1926 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 1927 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[SIVAR_ADDR]], align 4 1928 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[SIVAR_CASTED]], align 4 1929 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[SIVAR_CASTED]], align 4 1930 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32, [2 x %struct.S]*, %struct.S*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i32 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP2]], i32 [[TMP6]]) 1931 // CHECK3-NEXT: ret void 1932 // 1933 // 1934 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. 1935 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR4]] { 1936 // CHECK3-NEXT: entry: 1937 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 1938 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 1939 // CHECK3-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 1940 // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 1941 // CHECK3-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4 1942 // CHECK3-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4 1943 // CHECK3-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4 1944 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1945 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 1946 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1947 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1948 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1949 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1950 // CHECK3-NEXT: [[VEC1:%.*]] = alloca [2 x i32], align 4 1951 // CHECK3-NEXT: [[S_ARR2:%.*]] = alloca [2 x %struct.S], align 4 1952 // CHECK3-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 1953 // CHECK3-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S:%.*]], align 4 1954 // CHECK3-NEXT: [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 4 1955 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 1956 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 1957 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 1958 // CHECK3-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 1959 // CHECK3-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 1960 // CHECK3-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4 1961 // CHECK3-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4 1962 // CHECK3-NEXT: store i32 [[SIVAR]], i32* [[SIVAR_ADDR]], align 4 1963 // CHECK3-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 1964 // CHECK3-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4 1965 // CHECK3-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4 1966 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1967 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 1968 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 1969 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1970 // CHECK3-NEXT: [[TMP3:%.*]] = bitcast [2 x i32]* [[VEC1]] to i8* 1971 // CHECK3-NEXT: [[TMP4:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* 1972 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i32 8, i1 false) 1973 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0 1974 // CHECK3-NEXT: [[TMP5:%.*]] = bitcast [2 x %struct.S]* [[TMP1]] to %struct.S* 1975 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 1976 // CHECK3-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP6]] 1977 // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 1978 // CHECK3: omp.arraycpy.body: 1979 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 1980 // CHECK3-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 1981 // CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) 1982 // CHECK3-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) 1983 // CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] 1984 // CHECK3-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 1985 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 1986 // CHECK3-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] 1987 // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]] 1988 // CHECK3: omp.arraycpy.done3: 1989 // CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) 1990 // CHECK3-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP5]]) 1991 // CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR2]] 1992 // CHECK3-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 1993 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 1994 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 1995 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1996 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP9]], 1 1997 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1998 // CHECK3: cond.true: 1999 // CHECK3-NEXT: br label [[COND_END:%.*]] 2000 // CHECK3: cond.false: 2001 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2002 // CHECK3-NEXT: br label [[COND_END]] 2003 // CHECK3: cond.end: 2004 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ] 2005 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 2006 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 2007 // CHECK3-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 2008 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2009 // CHECK3: omp.inner.for.cond: 2010 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2011 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2012 // CHECK3-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] 2013 // CHECK3-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 2014 // CHECK3: omp.inner.for.cond.cleanup: 2015 // CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 2016 // CHECK3: omp.inner.for.body: 2017 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2018 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1 2019 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 2020 // CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4 2021 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 2022 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 2023 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC1]], i32 0, i32 [[TMP16]] 2024 // CHECK3-NEXT: store i32 [[TMP15]], i32* [[ARRAYIDX]], align 4 2025 // CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4 2026 // CHECK3-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 [[TMP17]] 2027 // CHECK3-NEXT: [[TMP18:%.*]] = bitcast %struct.S* [[ARRAYIDX7]] to i8* 2028 // CHECK3-NEXT: [[TMP19:%.*]] = bitcast %struct.S* [[VAR4]] to i8* 2029 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP18]], i8* align 4 [[TMP19]], i32 4, i1 false) 2030 // CHECK3-NEXT: [[TMP20:%.*]] = load i32, i32* [[I]], align 4 2031 // CHECK3-NEXT: [[TMP21:%.*]] = load i32, i32* [[SIVAR_ADDR]], align 4 2032 // CHECK3-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP21]], [[TMP20]] 2033 // CHECK3-NEXT: store i32 [[ADD8]], i32* [[SIVAR_ADDR]], align 4 2034 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2035 // CHECK3: omp.body.continue: 2036 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2037 // CHECK3: omp.inner.for.inc: 2038 // CHECK3-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2039 // CHECK3-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP22]], 1 2040 // CHECK3-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 2041 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] 2042 // CHECK3: omp.inner.for.end: 2043 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2044 // CHECK3: omp.loop.exit: 2045 // CHECK3-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 2046 // CHECK3-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 2047 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) 2048 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR2]] 2049 // CHECK3-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0 2050 // CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN10]], i32 2 2051 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 2052 // CHECK3: arraydestroy.body: 2053 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP25]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 2054 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 2055 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 2056 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] 2057 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] 2058 // CHECK3: arraydestroy.done11: 2059 // CHECK3-NEXT: ret void 2060 // 2061 // 2062 // CHECK3-LABEL: define {{[^@]+}}@_ZN2StC1Ev 2063 // CHECK3-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2064 // CHECK3-NEXT: entry: 2065 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 2066 // CHECK3-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 2067 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 2068 // CHECK3-NEXT: call void @_ZN2StC2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) 2069 // CHECK3-NEXT: ret void 2070 // 2071 // 2072 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St 2073 // CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2074 // CHECK3-NEXT: entry: 2075 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 2076 // CHECK3-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 4 2077 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 2078 // CHECK3-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 4 2079 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 2080 // CHECK3-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 4 2081 // CHECK3-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) 2082 // CHECK3-NEXT: ret void 2083 // 2084 // 2085 // CHECK3-LABEL: define {{[^@]+}}@_ZN2StD1Ev 2086 // CHECK3-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2087 // CHECK3-NEXT: entry: 2088 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 2089 // CHECK3-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 2090 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 2091 // CHECK3-NEXT: call void @_ZN2StD2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR2]] 2092 // CHECK3-NEXT: ret void 2093 // 2094 // 2095 // CHECK3-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 2096 // CHECK3-SAME: () #[[ATTR6:[0-9]+]] comdat { 2097 // CHECK3-NEXT: entry: 2098 // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 2099 // CHECK3-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 2100 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 2101 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 2102 // CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 2103 // CHECK3-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 2104 // CHECK3-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 2105 // CHECK3-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 2106 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4 2107 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 2108 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 2109 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 2110 // CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) 2111 // CHECK3-NEXT: store i32 0, i32* [[T_VAR]], align 4 2112 // CHECK3-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 2113 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) 2114 // CHECK3-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 2115 // CHECK3-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) 2116 // CHECK3-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 2117 // CHECK3-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) 2118 // CHECK3-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 2119 // CHECK3-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 2120 // CHECK3-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 2121 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 2122 // CHECK3-NEXT: store i32 [[TMP2]], i32* [[T_VAR_CASTED]], align 4 2123 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 2124 // CHECK3-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 2125 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2126 // CHECK3-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to [2 x i32]** 2127 // CHECK3-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP6]], align 4 2128 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2129 // CHECK3-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to [2 x i32]** 2130 // CHECK3-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP8]], align 4 2131 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 2132 // CHECK3-NEXT: store i8* null, i8** [[TMP9]], align 4 2133 // CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 2134 // CHECK3-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i32* 2135 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP11]], align 4 2136 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 2137 // CHECK3-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* 2138 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4 2139 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 2140 // CHECK3-NEXT: store i8* null, i8** [[TMP14]], align 4 2141 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 2142 // CHECK3-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [2 x %struct.S.0]** 2143 // CHECK3-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP16]], align 4 2144 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 2145 // CHECK3-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [2 x %struct.S.0]** 2146 // CHECK3-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP18]], align 4 2147 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 2148 // CHECK3-NEXT: store i8* null, i8** [[TMP19]], align 4 2149 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 2150 // CHECK3-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to %struct.S.0** 2151 // CHECK3-NEXT: store %struct.S.0* [[TMP4]], %struct.S.0** [[TMP21]], align 4 2152 // CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 2153 // CHECK3-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.S.0** 2154 // CHECK3-NEXT: store %struct.S.0* [[TMP4]], %struct.S.0** [[TMP23]], align 4 2155 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 2156 // CHECK3-NEXT: store i8* null, i8** [[TMP24]], align 4 2157 // CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2158 // CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2159 // CHECK3-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 2) 2160 // CHECK3-NEXT: [[TMP27:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.region_id, i32 4, i8** [[TMP25]], i8** [[TMP26]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.4, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.5, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 2161 // CHECK3-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0 2162 // CHECK3-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 2163 // CHECK3: omp_offload.failed: 2164 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56([2 x i32]* [[VEC]], i32 [[TMP3]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[TMP4]]) #[[ATTR2]] 2165 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 2166 // CHECK3: omp_offload.cont: 2167 // CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4 2168 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 2169 // CHECK3-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 2170 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 2171 // CHECK3: arraydestroy.body: 2172 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP29]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 2173 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 2174 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 2175 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 2176 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] 2177 // CHECK3: arraydestroy.done2: 2178 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] 2179 // CHECK3-NEXT: [[TMP30:%.*]] = load i32, i32* [[RETVAL]], align 4 2180 // CHECK3-NEXT: ret i32 [[TMP30]] 2181 // 2182 // 2183 // CHECK3-LABEL: define {{[^@]+}}@_ZN2StC2Ev 2184 // CHECK3-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2185 // CHECK3-NEXT: entry: 2186 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 2187 // CHECK3-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 2188 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 2189 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[THIS1]], i32 0, i32 0 2190 // CHECK3-NEXT: store i32 0, i32* [[A]], align 4 2191 // CHECK3-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1 2192 // CHECK3-NEXT: store i32 0, i32* [[B]], align 4 2193 // CHECK3-NEXT: ret void 2194 // 2195 // 2196 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St 2197 // CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2198 // CHECK3-NEXT: entry: 2199 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 2200 // CHECK3-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 4 2201 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 2202 // CHECK3-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 4 2203 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 2204 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 2205 // CHECK3-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 4 2206 // CHECK3-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[TMP0]], i32 0, i32 0 2207 // CHECK3-NEXT: [[TMP1:%.*]] = load float, float* [[F2]], align 4 2208 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0 2209 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 2210 // CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to float 2211 // CHECK3-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]] 2212 // CHECK3-NEXT: store float [[ADD]], float* [[F]], align 4 2213 // CHECK3-NEXT: ret void 2214 // 2215 // 2216 // CHECK3-LABEL: define {{[^@]+}}@_ZN2StD2Ev 2217 // CHECK3-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2218 // CHECK3-NEXT: entry: 2219 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 2220 // CHECK3-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 2221 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 2222 // CHECK3-NEXT: ret void 2223 // 2224 // 2225 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 2226 // CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2227 // CHECK3-NEXT: entry: 2228 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 2229 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 2230 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 2231 // CHECK3-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) 2232 // CHECK3-NEXT: ret void 2233 // 2234 // 2235 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 2236 // CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2237 // CHECK3-NEXT: entry: 2238 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 2239 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2240 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 2241 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 2242 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 2243 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 2244 // CHECK3-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) 2245 // CHECK3-NEXT: ret void 2246 // 2247 // 2248 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56 2249 // CHECK3-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { 2250 // CHECK3-NEXT: entry: 2251 // CHECK3-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 2252 // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 2253 // CHECK3-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4 2254 // CHECK3-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4 2255 // CHECK3-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 2256 // CHECK3-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 2257 // CHECK3-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 2258 // CHECK3-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 2259 // CHECK3-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 2260 // CHECK3-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4 2261 // CHECK3-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 2262 // CHECK3-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 2263 // CHECK3-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4 2264 // CHECK3-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 4 2265 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 2266 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[T_VAR_CASTED]], align 4 2267 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 2268 // CHECK3-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 2269 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i32 [[TMP4]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP5]]) 2270 // CHECK3-NEXT: ret void 2271 // 2272 // 2273 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..3 2274 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { 2275 // CHECK3-NEXT: entry: 2276 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2277 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2278 // CHECK3-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 2279 // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 2280 // CHECK3-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4 2281 // CHECK3-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4 2282 // CHECK3-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 2283 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2284 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 2285 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2286 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2287 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2288 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2289 // CHECK3-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 2290 // CHECK3-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 2291 // CHECK3-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 2292 // CHECK3-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 2293 // CHECK3-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 2294 // CHECK3-NEXT: [[_TMP7:%.*]] = alloca %struct.S.0*, align 4 2295 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 2296 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2297 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2298 // CHECK3-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 2299 // CHECK3-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 2300 // CHECK3-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 2301 // CHECK3-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4 2302 // CHECK3-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 2303 // CHECK3-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 2304 // CHECK3-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4 2305 // CHECK3-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 4 2306 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 2307 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 2308 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 2309 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 2310 // CHECK3-NEXT: [[TMP3:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8* 2311 // CHECK3-NEXT: [[TMP4:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* 2312 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i32 8, i1 false) 2313 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 2314 // CHECK3-NEXT: [[TMP5:%.*]] = bitcast [2 x %struct.S.0]* [[TMP1]] to %struct.S.0* 2315 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 2316 // CHECK3-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP6]] 2317 // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 2318 // CHECK3: omp.arraycpy.body: 2319 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 2320 // CHECK3-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 2321 // CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) 2322 // CHECK3-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) 2323 // CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] 2324 // CHECK3-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 2325 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 2326 // CHECK3-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] 2327 // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] 2328 // CHECK3: omp.arraycpy.done4: 2329 // CHECK3-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 2330 // CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) 2331 // CHECK3-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP7]], %struct.St* [[AGG_TMP6]]) 2332 // CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] 2333 // CHECK3-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP7]], align 4 2334 // CHECK3-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 2335 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 2336 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 2337 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2338 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP10]], 1 2339 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2340 // CHECK3: cond.true: 2341 // CHECK3-NEXT: br label [[COND_END:%.*]] 2342 // CHECK3: cond.false: 2343 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2344 // CHECK3-NEXT: br label [[COND_END]] 2345 // CHECK3: cond.end: 2346 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] 2347 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 2348 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 2349 // CHECK3-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 2350 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2351 // CHECK3: omp.inner.for.cond: 2352 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2353 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2354 // CHECK3-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] 2355 // CHECK3-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 2356 // CHECK3: omp.inner.for.cond.cleanup: 2357 // CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 2358 // CHECK3: omp.inner.for.body: 2359 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2360 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 2361 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 2362 // CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4 2363 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 2364 // CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4 2365 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i32 0, i32 [[TMP17]] 2366 // CHECK3-NEXT: store i32 [[TMP16]], i32* [[ARRAYIDX]], align 4 2367 // CHECK3-NEXT: [[TMP18:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 4 2368 // CHECK3-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 2369 // CHECK3-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 [[TMP19]] 2370 // CHECK3-NEXT: [[TMP20:%.*]] = bitcast %struct.S.0* [[ARRAYIDX9]] to i8* 2371 // CHECK3-NEXT: [[TMP21:%.*]] = bitcast %struct.S.0* [[TMP18]] to i8* 2372 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i32 4, i1 false) 2373 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2374 // CHECK3: omp.body.continue: 2375 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2376 // CHECK3: omp.inner.for.inc: 2377 // CHECK3-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2378 // CHECK3-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP22]], 1 2379 // CHECK3-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4 2380 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] 2381 // CHECK3: omp.inner.for.end: 2382 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2383 // CHECK3: omp.loop.exit: 2384 // CHECK3-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 2385 // CHECK3-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 2386 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) 2387 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] 2388 // CHECK3-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 2389 // CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN11]], i32 2 2390 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 2391 // CHECK3: arraydestroy.body: 2392 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP25]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 2393 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 2394 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 2395 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] 2396 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] 2397 // CHECK3: arraydestroy.done12: 2398 // CHECK3-NEXT: ret void 2399 // 2400 // 2401 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St 2402 // CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2403 // CHECK3-NEXT: entry: 2404 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 2405 // CHECK3-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 4 2406 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 2407 // CHECK3-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 4 2408 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 2409 // CHECK3-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 4 2410 // CHECK3-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) 2411 // CHECK3-NEXT: ret void 2412 // 2413 // 2414 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 2415 // CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2416 // CHECK3-NEXT: entry: 2417 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 2418 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 2419 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 2420 // CHECK3-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 2421 // CHECK3-NEXT: ret void 2422 // 2423 // 2424 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 2425 // CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2426 // CHECK3-NEXT: entry: 2427 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 2428 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 2429 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 2430 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 2431 // CHECK3-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 2432 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 2433 // CHECK3-NEXT: ret void 2434 // 2435 // 2436 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 2437 // CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2438 // CHECK3-NEXT: entry: 2439 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 2440 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2441 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 2442 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 2443 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 2444 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 2445 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 2446 // CHECK3-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 2447 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] 2448 // CHECK3-NEXT: store i32 [[ADD]], i32* [[F]], align 4 2449 // CHECK3-NEXT: ret void 2450 // 2451 // 2452 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St 2453 // CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2454 // CHECK3-NEXT: entry: 2455 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 2456 // CHECK3-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 4 2457 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 2458 // CHECK3-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 4 2459 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 2460 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 2461 // CHECK3-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 4 2462 // CHECK3-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[TMP0]], i32 0, i32 0 2463 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[F2]], align 4 2464 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0 2465 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 2466 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]] 2467 // CHECK3-NEXT: store i32 [[ADD]], i32* [[F]], align 4 2468 // CHECK3-NEXT: ret void 2469 // 2470 // 2471 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 2472 // CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2473 // CHECK3-NEXT: entry: 2474 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 2475 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 2476 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 2477 // CHECK3-NEXT: ret void 2478 // 2479 // 2480 // CHECK3-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_firstprivate_codegen.cpp 2481 // CHECK3-SAME: () #[[ATTR0]] { 2482 // CHECK3-NEXT: entry: 2483 // CHECK3-NEXT: call void @__cxx_global_var_init() 2484 // CHECK3-NEXT: call void @__cxx_global_var_init.1() 2485 // CHECK3-NEXT: call void @__cxx_global_var_init.2() 2486 // CHECK3-NEXT: ret void 2487 // 2488 // 2489 // CHECK3-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 2490 // CHECK3-SAME: () #[[ATTR0]] { 2491 // CHECK3-NEXT: entry: 2492 // CHECK3-NEXT: call void @__tgt_register_requires(i64 1) 2493 // CHECK3-NEXT: ret void 2494 // 2495 // 2496 // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_var_init 2497 // CHECK4-SAME: () #[[ATTR0:[0-9]+]] { 2498 // CHECK4-NEXT: entry: 2499 // CHECK4-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) 2500 // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] 2501 // CHECK4-NEXT: ret void 2502 // 2503 // 2504 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 2505 // CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 2506 // CHECK4-NEXT: entry: 2507 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 2508 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 2509 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 2510 // CHECK4-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) 2511 // CHECK4-NEXT: ret void 2512 // 2513 // 2514 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 2515 // CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2516 // CHECK4-NEXT: entry: 2517 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 2518 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 2519 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 2520 // CHECK4-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 2521 // CHECK4-NEXT: ret void 2522 // 2523 // 2524 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 2525 // CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2526 // CHECK4-NEXT: entry: 2527 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 2528 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 2529 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 2530 // CHECK4-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 2531 // CHECK4-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 2532 // CHECK4-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 2533 // CHECK4-NEXT: store float [[CONV]], float* [[F]], align 4 2534 // CHECK4-NEXT: ret void 2535 // 2536 // 2537 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 2538 // CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2539 // CHECK4-NEXT: entry: 2540 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 2541 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 2542 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 2543 // CHECK4-NEXT: ret void 2544 // 2545 // 2546 // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 2547 // CHECK4-SAME: () #[[ATTR0]] { 2548 // CHECK4-NEXT: entry: 2549 // CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float 1.000000e+00) 2550 // CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float 2.000000e+00) 2551 // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] 2552 // CHECK4-NEXT: ret void 2553 // 2554 // 2555 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 2556 // CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2557 // CHECK4-NEXT: entry: 2558 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 2559 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 2560 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 2561 // CHECK4-NEXT: store float [[A]], float* [[A_ADDR]], align 4 2562 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 2563 // CHECK4-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 2564 // CHECK4-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) 2565 // CHECK4-NEXT: ret void 2566 // 2567 // 2568 // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 2569 // CHECK4-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { 2570 // CHECK4-NEXT: entry: 2571 // CHECK4-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 2572 // CHECK4-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4 2573 // CHECK4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 2574 // CHECK4: arraydestroy.body: 2575 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 2576 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 2577 // CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 2578 // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) 2579 // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 2580 // CHECK4: arraydestroy.done1: 2581 // CHECK4-NEXT: ret void 2582 // 2583 // 2584 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 2585 // CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2586 // CHECK4-NEXT: entry: 2587 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 2588 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 2589 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 2590 // CHECK4-NEXT: store float [[A]], float* [[A_ADDR]], align 4 2591 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 2592 // CHECK4-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 2593 // CHECK4-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 2594 // CHECK4-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 2595 // CHECK4-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 2596 // CHECK4-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 2597 // CHECK4-NEXT: store float [[ADD]], float* [[F]], align 4 2598 // CHECK4-NEXT: ret void 2599 // 2600 // 2601 // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 2602 // CHECK4-SAME: () #[[ATTR0]] { 2603 // CHECK4-NEXT: entry: 2604 // CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) 2605 // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] 2606 // CHECK4-NEXT: ret void 2607 // 2608 // 2609 // CHECK4-LABEL: define {{[^@]+}}@main 2610 // CHECK4-SAME: () #[[ATTR3:[0-9]+]] { 2611 // CHECK4-NEXT: entry: 2612 // CHECK4-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 2613 // CHECK4-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 2614 // CHECK4-NEXT: [[SIVAR_CASTED:%.*]] = alloca i32, align 4 2615 // CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4 2616 // CHECK4-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4 2617 // CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4 2618 // CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 2619 // CHECK4-NEXT: store i32 0, i32* [[RETVAL]], align 4 2620 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* @t_var, align 4 2621 // CHECK4-NEXT: store i32 [[TMP0]], i32* [[T_VAR_CASTED]], align 4 2622 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 2623 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 2624 // CHECK4-NEXT: store i32 [[TMP2]], i32* [[SIVAR_CASTED]], align 4 2625 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[SIVAR_CASTED]], align 4 2626 // CHECK4-NEXT: [[TMP4:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2627 // CHECK4-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to [2 x i32]** 2628 // CHECK4-NEXT: store [2 x i32]* @vec, [2 x i32]** [[TMP5]], align 4 2629 // CHECK4-NEXT: [[TMP6:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2630 // CHECK4-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to [2 x i32]** 2631 // CHECK4-NEXT: store [2 x i32]* @vec, [2 x i32]** [[TMP7]], align 4 2632 // CHECK4-NEXT: [[TMP8:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 2633 // CHECK4-NEXT: store i8* null, i8** [[TMP8]], align 4 2634 // CHECK4-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 2635 // CHECK4-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* 2636 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[TMP10]], align 4 2637 // CHECK4-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 2638 // CHECK4-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32* 2639 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[TMP12]], align 4 2640 // CHECK4-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 2641 // CHECK4-NEXT: store i8* null, i8** [[TMP13]], align 4 2642 // CHECK4-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 2643 // CHECK4-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x %struct.S]** 2644 // CHECK4-NEXT: store [2 x %struct.S]* @s_arr, [2 x %struct.S]** [[TMP15]], align 4 2645 // CHECK4-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 2646 // CHECK4-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to [2 x %struct.S]** 2647 // CHECK4-NEXT: store [2 x %struct.S]* @s_arr, [2 x %struct.S]** [[TMP17]], align 4 2648 // CHECK4-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 2649 // CHECK4-NEXT: store i8* null, i8** [[TMP18]], align 4 2650 // CHECK4-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 2651 // CHECK4-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to %struct.S** 2652 // CHECK4-NEXT: store %struct.S* @var, %struct.S** [[TMP20]], align 4 2653 // CHECK4-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 2654 // CHECK4-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to %struct.S** 2655 // CHECK4-NEXT: store %struct.S* @var, %struct.S** [[TMP22]], align 4 2656 // CHECK4-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 2657 // CHECK4-NEXT: store i8* null, i8** [[TMP23]], align 4 2658 // CHECK4-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 2659 // CHECK4-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i32* 2660 // CHECK4-NEXT: store i32 [[TMP3]], i32* [[TMP25]], align 4 2661 // CHECK4-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 2662 // CHECK4-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i32* 2663 // CHECK4-NEXT: store i32 [[TMP3]], i32* [[TMP27]], align 4 2664 // CHECK4-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 2665 // CHECK4-NEXT: store i8* null, i8** [[TMP28]], align 4 2666 // CHECK4-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2667 // CHECK4-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2668 // CHECK4-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 2) 2669 // CHECK4-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92.region_id, i32 5, i8** [[TMP29]], i8** [[TMP30]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 2670 // CHECK4-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 2671 // CHECK4-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 2672 // CHECK4: omp_offload.failed: 2673 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92([2 x i32]* @vec, i32 [[TMP1]], [2 x %struct.S]* @s_arr, %struct.S* @var, i32 [[TMP3]]) #[[ATTR2]] 2674 // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]] 2675 // CHECK4: omp_offload.cont: 2676 // CHECK4-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() 2677 // CHECK4-NEXT: ret i32 [[CALL]] 2678 // 2679 // 2680 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92 2681 // CHECK4-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR4:[0-9]+]] { 2682 // CHECK4-NEXT: entry: 2683 // CHECK4-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 2684 // CHECK4-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 2685 // CHECK4-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4 2686 // CHECK4-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4 2687 // CHECK4-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4 2688 // CHECK4-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 2689 // CHECK4-NEXT: [[SIVAR_CASTED:%.*]] = alloca i32, align 4 2690 // CHECK4-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 2691 // CHECK4-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 2692 // CHECK4-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4 2693 // CHECK4-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4 2694 // CHECK4-NEXT: store i32 [[SIVAR]], i32* [[SIVAR_ADDR]], align 4 2695 // CHECK4-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 2696 // CHECK4-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4 2697 // CHECK4-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4 2698 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 2699 // CHECK4-NEXT: store i32 [[TMP3]], i32* [[T_VAR_CASTED]], align 4 2700 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 2701 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[SIVAR_ADDR]], align 4 2702 // CHECK4-NEXT: store i32 [[TMP5]], i32* [[SIVAR_CASTED]], align 4 2703 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[SIVAR_CASTED]], align 4 2704 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32, [2 x %struct.S]*, %struct.S*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i32 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP2]], i32 [[TMP6]]) 2705 // CHECK4-NEXT: ret void 2706 // 2707 // 2708 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. 2709 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR4]] { 2710 // CHECK4-NEXT: entry: 2711 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2712 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2713 // CHECK4-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 2714 // CHECK4-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 2715 // CHECK4-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4 2716 // CHECK4-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4 2717 // CHECK4-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4 2718 // CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2719 // CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 2720 // CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2721 // CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2722 // CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2723 // CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2724 // CHECK4-NEXT: [[VEC1:%.*]] = alloca [2 x i32], align 4 2725 // CHECK4-NEXT: [[S_ARR2:%.*]] = alloca [2 x %struct.S], align 4 2726 // CHECK4-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 2727 // CHECK4-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S:%.*]], align 4 2728 // CHECK4-NEXT: [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 4 2729 // CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 2730 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2731 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2732 // CHECK4-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 2733 // CHECK4-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 2734 // CHECK4-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4 2735 // CHECK4-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4 2736 // CHECK4-NEXT: store i32 [[SIVAR]], i32* [[SIVAR_ADDR]], align 4 2737 // CHECK4-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 2738 // CHECK4-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4 2739 // CHECK4-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4 2740 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 2741 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 2742 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 2743 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 2744 // CHECK4-NEXT: [[TMP3:%.*]] = bitcast [2 x i32]* [[VEC1]] to i8* 2745 // CHECK4-NEXT: [[TMP4:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* 2746 // CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i32 8, i1 false) 2747 // CHECK4-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0 2748 // CHECK4-NEXT: [[TMP5:%.*]] = bitcast [2 x %struct.S]* [[TMP1]] to %struct.S* 2749 // CHECK4-NEXT: [[TMP6:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 2750 // CHECK4-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP6]] 2751 // CHECK4-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 2752 // CHECK4: omp.arraycpy.body: 2753 // CHECK4-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 2754 // CHECK4-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 2755 // CHECK4-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) 2756 // CHECK4-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) 2757 // CHECK4-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] 2758 // CHECK4-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 2759 // CHECK4-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 2760 // CHECK4-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] 2761 // CHECK4-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]] 2762 // CHECK4: omp.arraycpy.done3: 2763 // CHECK4-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) 2764 // CHECK4-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP5]]) 2765 // CHECK4-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR2]] 2766 // CHECK4-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 2767 // CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 2768 // CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 2769 // CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2770 // CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP9]], 1 2771 // CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2772 // CHECK4: cond.true: 2773 // CHECK4-NEXT: br label [[COND_END:%.*]] 2774 // CHECK4: cond.false: 2775 // CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2776 // CHECK4-NEXT: br label [[COND_END]] 2777 // CHECK4: cond.end: 2778 // CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ] 2779 // CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 2780 // CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 2781 // CHECK4-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 2782 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2783 // CHECK4: omp.inner.for.cond: 2784 // CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2785 // CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2786 // CHECK4-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] 2787 // CHECK4-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 2788 // CHECK4: omp.inner.for.cond.cleanup: 2789 // CHECK4-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 2790 // CHECK4: omp.inner.for.body: 2791 // CHECK4-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2792 // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1 2793 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 2794 // CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4 2795 // CHECK4-NEXT: [[TMP15:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 2796 // CHECK4-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 2797 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC1]], i32 0, i32 [[TMP16]] 2798 // CHECK4-NEXT: store i32 [[TMP15]], i32* [[ARRAYIDX]], align 4 2799 // CHECK4-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4 2800 // CHECK4-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 [[TMP17]] 2801 // CHECK4-NEXT: [[TMP18:%.*]] = bitcast %struct.S* [[ARRAYIDX7]] to i8* 2802 // CHECK4-NEXT: [[TMP19:%.*]] = bitcast %struct.S* [[VAR4]] to i8* 2803 // CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP18]], i8* align 4 [[TMP19]], i32 4, i1 false) 2804 // CHECK4-NEXT: [[TMP20:%.*]] = load i32, i32* [[I]], align 4 2805 // CHECK4-NEXT: [[TMP21:%.*]] = load i32, i32* [[SIVAR_ADDR]], align 4 2806 // CHECK4-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP21]], [[TMP20]] 2807 // CHECK4-NEXT: store i32 [[ADD8]], i32* [[SIVAR_ADDR]], align 4 2808 // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2809 // CHECK4: omp.body.continue: 2810 // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2811 // CHECK4: omp.inner.for.inc: 2812 // CHECK4-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2813 // CHECK4-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP22]], 1 2814 // CHECK4-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 2815 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] 2816 // CHECK4: omp.inner.for.end: 2817 // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2818 // CHECK4: omp.loop.exit: 2819 // CHECK4-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 2820 // CHECK4-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 2821 // CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) 2822 // CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR2]] 2823 // CHECK4-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0 2824 // CHECK4-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN10]], i32 2 2825 // CHECK4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 2826 // CHECK4: arraydestroy.body: 2827 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP25]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 2828 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 2829 // CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 2830 // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] 2831 // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] 2832 // CHECK4: arraydestroy.done11: 2833 // CHECK4-NEXT: ret void 2834 // 2835 // 2836 // CHECK4-LABEL: define {{[^@]+}}@_ZN2StC1Ev 2837 // CHECK4-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2838 // CHECK4-NEXT: entry: 2839 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 2840 // CHECK4-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 2841 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 2842 // CHECK4-NEXT: call void @_ZN2StC2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) 2843 // CHECK4-NEXT: ret void 2844 // 2845 // 2846 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St 2847 // CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2848 // CHECK4-NEXT: entry: 2849 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 2850 // CHECK4-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 4 2851 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 2852 // CHECK4-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 4 2853 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 2854 // CHECK4-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 4 2855 // CHECK4-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) 2856 // CHECK4-NEXT: ret void 2857 // 2858 // 2859 // CHECK4-LABEL: define {{[^@]+}}@_ZN2StD1Ev 2860 // CHECK4-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2861 // CHECK4-NEXT: entry: 2862 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 2863 // CHECK4-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 2864 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 2865 // CHECK4-NEXT: call void @_ZN2StD2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR2]] 2866 // CHECK4-NEXT: ret void 2867 // 2868 // 2869 // CHECK4-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 2870 // CHECK4-SAME: () #[[ATTR6:[0-9]+]] comdat { 2871 // CHECK4-NEXT: entry: 2872 // CHECK4-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 2873 // CHECK4-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 2874 // CHECK4-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 2875 // CHECK4-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 2876 // CHECK4-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 2877 // CHECK4-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 2878 // CHECK4-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 2879 // CHECK4-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 2880 // CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4 2881 // CHECK4-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 2882 // CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 2883 // CHECK4-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 2884 // CHECK4-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) 2885 // CHECK4-NEXT: store i32 0, i32* [[T_VAR]], align 4 2886 // CHECK4-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 2887 // CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) 2888 // CHECK4-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 2889 // CHECK4-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) 2890 // CHECK4-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 2891 // CHECK4-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) 2892 // CHECK4-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 2893 // CHECK4-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 2894 // CHECK4-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 2895 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 2896 // CHECK4-NEXT: store i32 [[TMP2]], i32* [[T_VAR_CASTED]], align 4 2897 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 2898 // CHECK4-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 2899 // CHECK4-NEXT: [[TMP5:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2900 // CHECK4-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to [2 x i32]** 2901 // CHECK4-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP6]], align 4 2902 // CHECK4-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2903 // CHECK4-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to [2 x i32]** 2904 // CHECK4-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP8]], align 4 2905 // CHECK4-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 2906 // CHECK4-NEXT: store i8* null, i8** [[TMP9]], align 4 2907 // CHECK4-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 2908 // CHECK4-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i32* 2909 // CHECK4-NEXT: store i32 [[TMP3]], i32* [[TMP11]], align 4 2910 // CHECK4-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 2911 // CHECK4-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* 2912 // CHECK4-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4 2913 // CHECK4-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 2914 // CHECK4-NEXT: store i8* null, i8** [[TMP14]], align 4 2915 // CHECK4-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 2916 // CHECK4-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [2 x %struct.S.0]** 2917 // CHECK4-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP16]], align 4 2918 // CHECK4-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 2919 // CHECK4-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [2 x %struct.S.0]** 2920 // CHECK4-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP18]], align 4 2921 // CHECK4-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 2922 // CHECK4-NEXT: store i8* null, i8** [[TMP19]], align 4 2923 // CHECK4-NEXT: [[TMP20:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 2924 // CHECK4-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to %struct.S.0** 2925 // CHECK4-NEXT: store %struct.S.0* [[TMP4]], %struct.S.0** [[TMP21]], align 4 2926 // CHECK4-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 2927 // CHECK4-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.S.0** 2928 // CHECK4-NEXT: store %struct.S.0* [[TMP4]], %struct.S.0** [[TMP23]], align 4 2929 // CHECK4-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 2930 // CHECK4-NEXT: store i8* null, i8** [[TMP24]], align 4 2931 // CHECK4-NEXT: [[TMP25:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2932 // CHECK4-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2933 // CHECK4-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 2) 2934 // CHECK4-NEXT: [[TMP27:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.region_id, i32 4, i8** [[TMP25]], i8** [[TMP26]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.4, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.5, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 2935 // CHECK4-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0 2936 // CHECK4-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 2937 // CHECK4: omp_offload.failed: 2938 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56([2 x i32]* [[VEC]], i32 [[TMP3]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[TMP4]]) #[[ATTR2]] 2939 // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]] 2940 // CHECK4: omp_offload.cont: 2941 // CHECK4-NEXT: store i32 0, i32* [[RETVAL]], align 4 2942 // CHECK4-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 2943 // CHECK4-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 2944 // CHECK4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 2945 // CHECK4: arraydestroy.body: 2946 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP29]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 2947 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 2948 // CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 2949 // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 2950 // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] 2951 // CHECK4: arraydestroy.done2: 2952 // CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] 2953 // CHECK4-NEXT: [[TMP30:%.*]] = load i32, i32* [[RETVAL]], align 4 2954 // CHECK4-NEXT: ret i32 [[TMP30]] 2955 // 2956 // 2957 // CHECK4-LABEL: define {{[^@]+}}@_ZN2StC2Ev 2958 // CHECK4-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2959 // CHECK4-NEXT: entry: 2960 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 2961 // CHECK4-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 2962 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 2963 // CHECK4-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[THIS1]], i32 0, i32 0 2964 // CHECK4-NEXT: store i32 0, i32* [[A]], align 4 2965 // CHECK4-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1 2966 // CHECK4-NEXT: store i32 0, i32* [[B]], align 4 2967 // CHECK4-NEXT: ret void 2968 // 2969 // 2970 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St 2971 // CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2972 // CHECK4-NEXT: entry: 2973 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 2974 // CHECK4-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 4 2975 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 2976 // CHECK4-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 4 2977 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 2978 // CHECK4-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 2979 // CHECK4-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 4 2980 // CHECK4-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[TMP0]], i32 0, i32 0 2981 // CHECK4-NEXT: [[TMP1:%.*]] = load float, float* [[F2]], align 4 2982 // CHECK4-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0 2983 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 2984 // CHECK4-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to float 2985 // CHECK4-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]] 2986 // CHECK4-NEXT: store float [[ADD]], float* [[F]], align 4 2987 // CHECK4-NEXT: ret void 2988 // 2989 // 2990 // CHECK4-LABEL: define {{[^@]+}}@_ZN2StD2Ev 2991 // CHECK4-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2992 // CHECK4-NEXT: entry: 2993 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 2994 // CHECK4-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 2995 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 2996 // CHECK4-NEXT: ret void 2997 // 2998 // 2999 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 3000 // CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3001 // CHECK4-NEXT: entry: 3002 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 3003 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 3004 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 3005 // CHECK4-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) 3006 // CHECK4-NEXT: ret void 3007 // 3008 // 3009 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 3010 // CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3011 // CHECK4-NEXT: entry: 3012 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 3013 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3014 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 3015 // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 3016 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 3017 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 3018 // CHECK4-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) 3019 // CHECK4-NEXT: ret void 3020 // 3021 // 3022 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56 3023 // CHECK4-SAME: ([2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { 3024 // CHECK4-NEXT: entry: 3025 // CHECK4-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 3026 // CHECK4-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 3027 // CHECK4-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4 3028 // CHECK4-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4 3029 // CHECK4-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 3030 // CHECK4-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 3031 // CHECK4-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 3032 // CHECK4-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 3033 // CHECK4-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 3034 // CHECK4-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4 3035 // CHECK4-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 3036 // CHECK4-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 3037 // CHECK4-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4 3038 // CHECK4-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 4 3039 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 3040 // CHECK4-NEXT: store i32 [[TMP3]], i32* [[T_VAR_CASTED]], align 4 3041 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 3042 // CHECK4-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 3043 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i32 [[TMP4]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP5]]) 3044 // CHECK4-NEXT: ret void 3045 // 3046 // 3047 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..3 3048 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { 3049 // CHECK4-NEXT: entry: 3050 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 3051 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 3052 // CHECK4-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 3053 // CHECK4-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 3054 // CHECK4-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4 3055 // CHECK4-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4 3056 // CHECK4-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 3057 // CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 3058 // CHECK4-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 3059 // CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 3060 // CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 3061 // CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 3062 // CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 3063 // CHECK4-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 3064 // CHECK4-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 3065 // CHECK4-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 3066 // CHECK4-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 3067 // CHECK4-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 3068 // CHECK4-NEXT: [[_TMP7:%.*]] = alloca %struct.S.0*, align 4 3069 // CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 3070 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 3071 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 3072 // CHECK4-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 3073 // CHECK4-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 3074 // CHECK4-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 3075 // CHECK4-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4 3076 // CHECK4-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 3077 // CHECK4-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 3078 // CHECK4-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4 3079 // CHECK4-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 4 3080 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 3081 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 3082 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 3083 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 3084 // CHECK4-NEXT: [[TMP3:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8* 3085 // CHECK4-NEXT: [[TMP4:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* 3086 // CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i32 8, i1 false) 3087 // CHECK4-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 3088 // CHECK4-NEXT: [[TMP5:%.*]] = bitcast [2 x %struct.S.0]* [[TMP1]] to %struct.S.0* 3089 // CHECK4-NEXT: [[TMP6:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 3090 // CHECK4-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP6]] 3091 // CHECK4-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 3092 // CHECK4: omp.arraycpy.body: 3093 // CHECK4-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 3094 // CHECK4-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 3095 // CHECK4-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) 3096 // CHECK4-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) 3097 // CHECK4-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] 3098 // CHECK4-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 3099 // CHECK4-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 3100 // CHECK4-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] 3101 // CHECK4-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] 3102 // CHECK4: omp.arraycpy.done4: 3103 // CHECK4-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 3104 // CHECK4-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) 3105 // CHECK4-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP7]], %struct.St* [[AGG_TMP6]]) 3106 // CHECK4-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] 3107 // CHECK4-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP7]], align 4 3108 // CHECK4-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 3109 // CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 3110 // CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 3111 // CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 3112 // CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP10]], 1 3113 // CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 3114 // CHECK4: cond.true: 3115 // CHECK4-NEXT: br label [[COND_END:%.*]] 3116 // CHECK4: cond.false: 3117 // CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 3118 // CHECK4-NEXT: br label [[COND_END]] 3119 // CHECK4: cond.end: 3120 // CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] 3121 // CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 3122 // CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 3123 // CHECK4-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 3124 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 3125 // CHECK4: omp.inner.for.cond: 3126 // CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 3127 // CHECK4-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 3128 // CHECK4-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] 3129 // CHECK4-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 3130 // CHECK4: omp.inner.for.cond.cleanup: 3131 // CHECK4-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 3132 // CHECK4: omp.inner.for.body: 3133 // CHECK4-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 3134 // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 3135 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 3136 // CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4 3137 // CHECK4-NEXT: [[TMP16:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 3138 // CHECK4-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4 3139 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i32 0, i32 [[TMP17]] 3140 // CHECK4-NEXT: store i32 [[TMP16]], i32* [[ARRAYIDX]], align 4 3141 // CHECK4-NEXT: [[TMP18:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 4 3142 // CHECK4-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 3143 // CHECK4-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 [[TMP19]] 3144 // CHECK4-NEXT: [[TMP20:%.*]] = bitcast %struct.S.0* [[ARRAYIDX9]] to i8* 3145 // CHECK4-NEXT: [[TMP21:%.*]] = bitcast %struct.S.0* [[TMP18]] to i8* 3146 // CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i32 4, i1 false) 3147 // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 3148 // CHECK4: omp.body.continue: 3149 // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 3150 // CHECK4: omp.inner.for.inc: 3151 // CHECK4-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 3152 // CHECK4-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP22]], 1 3153 // CHECK4-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4 3154 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] 3155 // CHECK4: omp.inner.for.end: 3156 // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 3157 // CHECK4: omp.loop.exit: 3158 // CHECK4-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 3159 // CHECK4-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 3160 // CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) 3161 // CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] 3162 // CHECK4-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 3163 // CHECK4-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN11]], i32 2 3164 // CHECK4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 3165 // CHECK4: arraydestroy.body: 3166 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP25]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 3167 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 3168 // CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 3169 // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] 3170 // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] 3171 // CHECK4: arraydestroy.done12: 3172 // CHECK4-NEXT: ret void 3173 // 3174 // 3175 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St 3176 // CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3177 // CHECK4-NEXT: entry: 3178 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 3179 // CHECK4-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 4 3180 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 3181 // CHECK4-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 4 3182 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 3183 // CHECK4-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 4 3184 // CHECK4-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) 3185 // CHECK4-NEXT: ret void 3186 // 3187 // 3188 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 3189 // CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3190 // CHECK4-NEXT: entry: 3191 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 3192 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 3193 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 3194 // CHECK4-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 3195 // CHECK4-NEXT: ret void 3196 // 3197 // 3198 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 3199 // CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3200 // CHECK4-NEXT: entry: 3201 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 3202 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 3203 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 3204 // CHECK4-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 3205 // CHECK4-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 3206 // CHECK4-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 3207 // CHECK4-NEXT: ret void 3208 // 3209 // 3210 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 3211 // CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3212 // CHECK4-NEXT: entry: 3213 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 3214 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3215 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 3216 // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 3217 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 3218 // CHECK4-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 3219 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 3220 // CHECK4-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 3221 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] 3222 // CHECK4-NEXT: store i32 [[ADD]], i32* [[F]], align 4 3223 // CHECK4-NEXT: ret void 3224 // 3225 // 3226 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St 3227 // CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3228 // CHECK4-NEXT: entry: 3229 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 3230 // CHECK4-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 4 3231 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 3232 // CHECK4-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 4 3233 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 3234 // CHECK4-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 3235 // CHECK4-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 4 3236 // CHECK4-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[TMP0]], i32 0, i32 0 3237 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[F2]], align 4 3238 // CHECK4-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0 3239 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 3240 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]] 3241 // CHECK4-NEXT: store i32 [[ADD]], i32* [[F]], align 4 3242 // CHECK4-NEXT: ret void 3243 // 3244 // 3245 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 3246 // CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3247 // CHECK4-NEXT: entry: 3248 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 3249 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 3250 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 3251 // CHECK4-NEXT: ret void 3252 // 3253 // 3254 // CHECK4-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_firstprivate_codegen.cpp 3255 // CHECK4-SAME: () #[[ATTR0]] { 3256 // CHECK4-NEXT: entry: 3257 // CHECK4-NEXT: call void @__cxx_global_var_init() 3258 // CHECK4-NEXT: call void @__cxx_global_var_init.1() 3259 // CHECK4-NEXT: call void @__cxx_global_var_init.2() 3260 // CHECK4-NEXT: ret void 3261 // 3262 // 3263 // CHECK4-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 3264 // CHECK4-SAME: () #[[ATTR0]] { 3265 // CHECK4-NEXT: entry: 3266 // CHECK4-NEXT: call void @__tgt_register_requires(i64 1) 3267 // CHECK4-NEXT: ret void 3268 // 3269 // 3270 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init 3271 // CHECK5-SAME: () #[[ATTR0:[0-9]+]] { 3272 // CHECK5-NEXT: entry: 3273 // CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) 3274 // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] 3275 // CHECK5-NEXT: ret void 3276 // 3277 // 3278 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 3279 // CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 3280 // CHECK5-NEXT: entry: 3281 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 3282 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 3283 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 3284 // CHECK5-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) 3285 // CHECK5-NEXT: ret void 3286 // 3287 // 3288 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 3289 // CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3290 // CHECK5-NEXT: entry: 3291 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 3292 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 3293 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 3294 // CHECK5-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 3295 // CHECK5-NEXT: ret void 3296 // 3297 // 3298 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 3299 // CHECK5-SAME: () #[[ATTR0]] { 3300 // CHECK5-NEXT: entry: 3301 // CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) 3302 // CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) 3303 // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] 3304 // CHECK5-NEXT: ret void 3305 // 3306 // 3307 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 3308 // CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3309 // CHECK5-NEXT: entry: 3310 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 3311 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 3312 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 3313 // CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 4 3314 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 3315 // CHECK5-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 3316 // CHECK5-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) 3317 // CHECK5-NEXT: ret void 3318 // 3319 // 3320 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 3321 // CHECK5-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { 3322 // CHECK5-NEXT: entry: 3323 // CHECK5-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 3324 // CHECK5-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 3325 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 3326 // CHECK5: arraydestroy.body: 3327 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 3328 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 3329 // CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 3330 // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) 3331 // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 3332 // CHECK5: arraydestroy.done1: 3333 // CHECK5-NEXT: ret void 3334 // 3335 // 3336 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 3337 // CHECK5-SAME: () #[[ATTR0]] { 3338 // CHECK5-NEXT: entry: 3339 // CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) 3340 // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] 3341 // CHECK5-NEXT: ret void 3342 // 3343 // 3344 // CHECK5-LABEL: define {{[^@]+}}@main 3345 // CHECK5-SAME: () #[[ATTR3:[0-9]+]] { 3346 // CHECK5-NEXT: entry: 3347 // CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 3348 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 3349 // CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 3350 // CHECK5-NEXT: store i32 0, i32* [[I]], align 4 3351 // CHECK5-NEXT: br label [[FOR_COND:%.*]] 3352 // CHECK5: for.cond: 3353 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 3354 // CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 3355 // CHECK5-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 3356 // CHECK5: for.body: 3357 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* @t_var, align 4 3358 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 3359 // CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 3360 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* @vec, i64 0, i64 [[IDXPROM]] 3361 // CHECK5-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 3362 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 3363 // CHECK5-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP3]] to i64 3364 // CHECK5-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 [[IDXPROM1]] 3365 // CHECK5-NEXT: [[TMP4:%.*]] = bitcast %struct.S* [[ARRAYIDX2]] to i8* 3366 // CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP4]], i8* align 4 bitcast (%struct.S* @var to i8*), i64 4, i1 false) 3367 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 3368 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 3369 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], [[TMP5]] 3370 // CHECK5-NEXT: store i32 [[ADD]], i32* @_ZZ4mainE5sivar, align 4 3371 // CHECK5-NEXT: br label [[FOR_INC:%.*]] 3372 // CHECK5: for.inc: 3373 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 3374 // CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 3375 // CHECK5-NEXT: store i32 [[INC]], i32* [[I]], align 4 3376 // CHECK5-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] 3377 // CHECK5: for.end: 3378 // CHECK5-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() 3379 // CHECK5-NEXT: ret i32 [[CALL]] 3380 // 3381 // 3382 // CHECK5-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 3383 // CHECK5-SAME: () #[[ATTR5:[0-9]+]] comdat { 3384 // CHECK5-NEXT: entry: 3385 // CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 3386 // CHECK5-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 3387 // CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 3388 // CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 3389 // CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 3390 // CHECK5-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 3391 // CHECK5-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 3392 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 3393 // CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) 3394 // CHECK5-NEXT: store i32 0, i32* [[T_VAR]], align 4 3395 // CHECK5-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 3396 // CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) 3397 // CHECK5-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 3398 // CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) 3399 // CHECK5-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 3400 // CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) 3401 // CHECK5-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 3402 // CHECK5-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 3403 // CHECK5-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 3404 // CHECK5-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 3405 // CHECK5-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 3406 // CHECK5-NEXT: store i32 0, i32* [[I]], align 4 3407 // CHECK5-NEXT: br label [[FOR_COND:%.*]] 3408 // CHECK5: for.cond: 3409 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 3410 // CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP4]], 2 3411 // CHECK5-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 3412 // CHECK5: for.body: 3413 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[T_VAR]], align 4 3414 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 3415 // CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP6]] to i64 3416 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] 3417 // CHECK5-NEXT: store i32 [[TMP5]], i32* [[ARRAYIDX]], align 4 3418 // CHECK5-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 3419 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 3420 // CHECK5-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP8]] to i64 3421 // CHECK5-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 [[IDXPROM1]] 3422 // CHECK5-NEXT: [[TMP9:%.*]] = bitcast %struct.S.0* [[ARRAYIDX2]] to i8* 3423 // CHECK5-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[TMP7]] to i8* 3424 // CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP9]], i8* align 4 [[TMP10]], i64 4, i1 false) 3425 // CHECK5-NEXT: br label [[FOR_INC:%.*]] 3426 // CHECK5: for.inc: 3427 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 3428 // CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP11]], 1 3429 // CHECK5-NEXT: store i32 [[INC]], i32* [[I]], align 4 3430 // CHECK5-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] 3431 // CHECK5: for.end: 3432 // CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 3433 // CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 3434 // CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 3435 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 3436 // CHECK5: arraydestroy.body: 3437 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP12]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 3438 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 3439 // CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 3440 // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 3441 // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] 3442 // CHECK5: arraydestroy.done3: 3443 // CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] 3444 // CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[RETVAL]], align 4 3445 // CHECK5-NEXT: ret i32 [[TMP13]] 3446 // 3447 // 3448 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 3449 // CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3450 // CHECK5-NEXT: entry: 3451 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 3452 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 3453 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 3454 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 3455 // CHECK5-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 3456 // CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 3457 // CHECK5-NEXT: store float [[CONV]], float* [[F]], align 4 3458 // CHECK5-NEXT: ret void 3459 // 3460 // 3461 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 3462 // CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3463 // CHECK5-NEXT: entry: 3464 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 3465 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 3466 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 3467 // CHECK5-NEXT: ret void 3468 // 3469 // 3470 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 3471 // CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3472 // CHECK5-NEXT: entry: 3473 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 3474 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 3475 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 3476 // CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 4 3477 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 3478 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 3479 // CHECK5-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 3480 // CHECK5-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 3481 // CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 3482 // CHECK5-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 3483 // CHECK5-NEXT: store float [[ADD]], float* [[F]], align 4 3484 // CHECK5-NEXT: ret void 3485 // 3486 // 3487 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 3488 // CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3489 // CHECK5-NEXT: entry: 3490 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 3491 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 3492 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 3493 // CHECK5-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) 3494 // CHECK5-NEXT: ret void 3495 // 3496 // 3497 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 3498 // CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3499 // CHECK5-NEXT: entry: 3500 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 3501 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3502 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 3503 // CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 3504 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 3505 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 3506 // CHECK5-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) 3507 // CHECK5-NEXT: ret void 3508 // 3509 // 3510 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 3511 // CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3512 // CHECK5-NEXT: entry: 3513 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 3514 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 3515 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 3516 // CHECK5-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 3517 // CHECK5-NEXT: ret void 3518 // 3519 // 3520 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 3521 // CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3522 // CHECK5-NEXT: entry: 3523 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 3524 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 3525 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 3526 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 3527 // CHECK5-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 3528 // CHECK5-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 3529 // CHECK5-NEXT: ret void 3530 // 3531 // 3532 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 3533 // CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3534 // CHECK5-NEXT: entry: 3535 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 3536 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3537 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 3538 // CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 3539 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 3540 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 3541 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 3542 // CHECK5-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 3543 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] 3544 // CHECK5-NEXT: store i32 [[ADD]], i32* [[F]], align 4 3545 // CHECK5-NEXT: ret void 3546 // 3547 // 3548 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 3549 // CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3550 // CHECK5-NEXT: entry: 3551 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 3552 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 3553 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 3554 // CHECK5-NEXT: ret void 3555 // 3556 // 3557 // CHECK5-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_firstprivate_codegen.cpp 3558 // CHECK5-SAME: () #[[ATTR0]] { 3559 // CHECK5-NEXT: entry: 3560 // CHECK5-NEXT: call void @__cxx_global_var_init() 3561 // CHECK5-NEXT: call void @__cxx_global_var_init.1() 3562 // CHECK5-NEXT: call void @__cxx_global_var_init.2() 3563 // CHECK5-NEXT: ret void 3564 // 3565 // 3566 // CHECK6-LABEL: define {{[^@]+}}@__cxx_global_var_init 3567 // CHECK6-SAME: () #[[ATTR0:[0-9]+]] { 3568 // CHECK6-NEXT: entry: 3569 // CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) 3570 // CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] 3571 // CHECK6-NEXT: ret void 3572 // 3573 // 3574 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 3575 // CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 3576 // CHECK6-NEXT: entry: 3577 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 3578 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 3579 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 3580 // CHECK6-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) 3581 // CHECK6-NEXT: ret void 3582 // 3583 // 3584 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 3585 // CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3586 // CHECK6-NEXT: entry: 3587 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 3588 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 3589 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 3590 // CHECK6-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 3591 // CHECK6-NEXT: ret void 3592 // 3593 // 3594 // CHECK6-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 3595 // CHECK6-SAME: () #[[ATTR0]] { 3596 // CHECK6-NEXT: entry: 3597 // CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) 3598 // CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) 3599 // CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] 3600 // CHECK6-NEXT: ret void 3601 // 3602 // 3603 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 3604 // CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3605 // CHECK6-NEXT: entry: 3606 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 3607 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 3608 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 3609 // CHECK6-NEXT: store float [[A]], float* [[A_ADDR]], align 4 3610 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 3611 // CHECK6-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 3612 // CHECK6-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) 3613 // CHECK6-NEXT: ret void 3614 // 3615 // 3616 // CHECK6-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 3617 // CHECK6-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { 3618 // CHECK6-NEXT: entry: 3619 // CHECK6-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 3620 // CHECK6-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 3621 // CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 3622 // CHECK6: arraydestroy.body: 3623 // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 3624 // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 3625 // CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 3626 // CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) 3627 // CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 3628 // CHECK6: arraydestroy.done1: 3629 // CHECK6-NEXT: ret void 3630 // 3631 // 3632 // CHECK6-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 3633 // CHECK6-SAME: () #[[ATTR0]] { 3634 // CHECK6-NEXT: entry: 3635 // CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) 3636 // CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] 3637 // CHECK6-NEXT: ret void 3638 // 3639 // 3640 // CHECK6-LABEL: define {{[^@]+}}@main 3641 // CHECK6-SAME: () #[[ATTR3:[0-9]+]] { 3642 // CHECK6-NEXT: entry: 3643 // CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 3644 // CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 3645 // CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 3646 // CHECK6-NEXT: store i32 0, i32* [[I]], align 4 3647 // CHECK6-NEXT: br label [[FOR_COND:%.*]] 3648 // CHECK6: for.cond: 3649 // CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 3650 // CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 3651 // CHECK6-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 3652 // CHECK6: for.body: 3653 // CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* @t_var, align 4 3654 // CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 3655 // CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 3656 // CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* @vec, i64 0, i64 [[IDXPROM]] 3657 // CHECK6-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 3658 // CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 3659 // CHECK6-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP3]] to i64 3660 // CHECK6-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 [[IDXPROM1]] 3661 // CHECK6-NEXT: [[TMP4:%.*]] = bitcast %struct.S* [[ARRAYIDX2]] to i8* 3662 // CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP4]], i8* align 4 bitcast (%struct.S* @var to i8*), i64 4, i1 false) 3663 // CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 3664 // CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 3665 // CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], [[TMP5]] 3666 // CHECK6-NEXT: store i32 [[ADD]], i32* @_ZZ4mainE5sivar, align 4 3667 // CHECK6-NEXT: br label [[FOR_INC:%.*]] 3668 // CHECK6: for.inc: 3669 // CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 3670 // CHECK6-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 3671 // CHECK6-NEXT: store i32 [[INC]], i32* [[I]], align 4 3672 // CHECK6-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] 3673 // CHECK6: for.end: 3674 // CHECK6-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() 3675 // CHECK6-NEXT: ret i32 [[CALL]] 3676 // 3677 // 3678 // CHECK6-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 3679 // CHECK6-SAME: () #[[ATTR5:[0-9]+]] comdat { 3680 // CHECK6-NEXT: entry: 3681 // CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 3682 // CHECK6-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 3683 // CHECK6-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 3684 // CHECK6-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 3685 // CHECK6-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 3686 // CHECK6-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 3687 // CHECK6-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 3688 // CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 3689 // CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) 3690 // CHECK6-NEXT: store i32 0, i32* [[T_VAR]], align 4 3691 // CHECK6-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 3692 // CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) 3693 // CHECK6-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 3694 // CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) 3695 // CHECK6-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 3696 // CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) 3697 // CHECK6-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 3698 // CHECK6-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 3699 // CHECK6-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 3700 // CHECK6-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 3701 // CHECK6-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 3702 // CHECK6-NEXT: store i32 0, i32* [[I]], align 4 3703 // CHECK6-NEXT: br label [[FOR_COND:%.*]] 3704 // CHECK6: for.cond: 3705 // CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 3706 // CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP4]], 2 3707 // CHECK6-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 3708 // CHECK6: for.body: 3709 // CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[T_VAR]], align 4 3710 // CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 3711 // CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP6]] to i64 3712 // CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] 3713 // CHECK6-NEXT: store i32 [[TMP5]], i32* [[ARRAYIDX]], align 4 3714 // CHECK6-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 3715 // CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 3716 // CHECK6-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP8]] to i64 3717 // CHECK6-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 [[IDXPROM1]] 3718 // CHECK6-NEXT: [[TMP9:%.*]] = bitcast %struct.S.0* [[ARRAYIDX2]] to i8* 3719 // CHECK6-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[TMP7]] to i8* 3720 // CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP9]], i8* align 4 [[TMP10]], i64 4, i1 false) 3721 // CHECK6-NEXT: br label [[FOR_INC:%.*]] 3722 // CHECK6: for.inc: 3723 // CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 3724 // CHECK6-NEXT: [[INC:%.*]] = add nsw i32 [[TMP11]], 1 3725 // CHECK6-NEXT: store i32 [[INC]], i32* [[I]], align 4 3726 // CHECK6-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] 3727 // CHECK6: for.end: 3728 // CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 3729 // CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 3730 // CHECK6-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 3731 // CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 3732 // CHECK6: arraydestroy.body: 3733 // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP12]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 3734 // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 3735 // CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 3736 // CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 3737 // CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] 3738 // CHECK6: arraydestroy.done3: 3739 // CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] 3740 // CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[RETVAL]], align 4 3741 // CHECK6-NEXT: ret i32 [[TMP13]] 3742 // 3743 // 3744 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 3745 // CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3746 // CHECK6-NEXT: entry: 3747 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 3748 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 3749 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 3750 // CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 3751 // CHECK6-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 3752 // CHECK6-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 3753 // CHECK6-NEXT: store float [[CONV]], float* [[F]], align 4 3754 // CHECK6-NEXT: ret void 3755 // 3756 // 3757 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 3758 // CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3759 // CHECK6-NEXT: entry: 3760 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 3761 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 3762 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 3763 // CHECK6-NEXT: ret void 3764 // 3765 // 3766 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 3767 // CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3768 // CHECK6-NEXT: entry: 3769 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 3770 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 3771 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 3772 // CHECK6-NEXT: store float [[A]], float* [[A_ADDR]], align 4 3773 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 3774 // CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 3775 // CHECK6-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 3776 // CHECK6-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 3777 // CHECK6-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 3778 // CHECK6-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 3779 // CHECK6-NEXT: store float [[ADD]], float* [[F]], align 4 3780 // CHECK6-NEXT: ret void 3781 // 3782 // 3783 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 3784 // CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3785 // CHECK6-NEXT: entry: 3786 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 3787 // CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 3788 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 3789 // CHECK6-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) 3790 // CHECK6-NEXT: ret void 3791 // 3792 // 3793 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 3794 // CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3795 // CHECK6-NEXT: entry: 3796 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 3797 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3798 // CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 3799 // CHECK6-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 3800 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 3801 // CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 3802 // CHECK6-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) 3803 // CHECK6-NEXT: ret void 3804 // 3805 // 3806 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 3807 // CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3808 // CHECK6-NEXT: entry: 3809 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 3810 // CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 3811 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 3812 // CHECK6-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 3813 // CHECK6-NEXT: ret void 3814 // 3815 // 3816 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 3817 // CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3818 // CHECK6-NEXT: entry: 3819 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 3820 // CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 3821 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 3822 // CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 3823 // CHECK6-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 3824 // CHECK6-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 3825 // CHECK6-NEXT: ret void 3826 // 3827 // 3828 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 3829 // CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3830 // CHECK6-NEXT: entry: 3831 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 3832 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3833 // CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 3834 // CHECK6-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 3835 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 3836 // CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 3837 // CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 3838 // CHECK6-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 3839 // CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] 3840 // CHECK6-NEXT: store i32 [[ADD]], i32* [[F]], align 4 3841 // CHECK6-NEXT: ret void 3842 // 3843 // 3844 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 3845 // CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3846 // CHECK6-NEXT: entry: 3847 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 3848 // CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 3849 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 3850 // CHECK6-NEXT: ret void 3851 // 3852 // 3853 // CHECK6-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_firstprivate_codegen.cpp 3854 // CHECK6-SAME: () #[[ATTR0]] { 3855 // CHECK6-NEXT: entry: 3856 // CHECK6-NEXT: call void @__cxx_global_var_init() 3857 // CHECK6-NEXT: call void @__cxx_global_var_init.1() 3858 // CHECK6-NEXT: call void @__cxx_global_var_init.2() 3859 // CHECK6-NEXT: ret void 3860 // 3861 // 3862 // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init 3863 // CHECK7-SAME: () #[[ATTR0:[0-9]+]] { 3864 // CHECK7-NEXT: entry: 3865 // CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) 3866 // CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] 3867 // CHECK7-NEXT: ret void 3868 // 3869 // 3870 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 3871 // CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 3872 // CHECK7-NEXT: entry: 3873 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 3874 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 3875 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 3876 // CHECK7-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) 3877 // CHECK7-NEXT: ret void 3878 // 3879 // 3880 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 3881 // CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3882 // CHECK7-NEXT: entry: 3883 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 3884 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 3885 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 3886 // CHECK7-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 3887 // CHECK7-NEXT: ret void 3888 // 3889 // 3890 // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 3891 // CHECK7-SAME: () #[[ATTR0]] { 3892 // CHECK7-NEXT: entry: 3893 // CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float 1.000000e+00) 3894 // CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float 2.000000e+00) 3895 // CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] 3896 // CHECK7-NEXT: ret void 3897 // 3898 // 3899 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 3900 // CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3901 // CHECK7-NEXT: entry: 3902 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 3903 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 3904 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 3905 // CHECK7-NEXT: store float [[A]], float* [[A_ADDR]], align 4 3906 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 3907 // CHECK7-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 3908 // CHECK7-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) 3909 // CHECK7-NEXT: ret void 3910 // 3911 // 3912 // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 3913 // CHECK7-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { 3914 // CHECK7-NEXT: entry: 3915 // CHECK7-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 3916 // CHECK7-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4 3917 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 3918 // CHECK7: arraydestroy.body: 3919 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 3920 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 3921 // CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 3922 // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) 3923 // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 3924 // CHECK7: arraydestroy.done1: 3925 // CHECK7-NEXT: ret void 3926 // 3927 // 3928 // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 3929 // CHECK7-SAME: () #[[ATTR0]] { 3930 // CHECK7-NEXT: entry: 3931 // CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) 3932 // CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] 3933 // CHECK7-NEXT: ret void 3934 // 3935 // 3936 // CHECK7-LABEL: define {{[^@]+}}@main 3937 // CHECK7-SAME: () #[[ATTR3:[0-9]+]] { 3938 // CHECK7-NEXT: entry: 3939 // CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 3940 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 3941 // CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 3942 // CHECK7-NEXT: store i32 0, i32* [[I]], align 4 3943 // CHECK7-NEXT: br label [[FOR_COND:%.*]] 3944 // CHECK7: for.cond: 3945 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 3946 // CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 3947 // CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 3948 // CHECK7: for.body: 3949 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* @t_var, align 4 3950 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 3951 // CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* @vec, i32 0, i32 [[TMP2]] 3952 // CHECK7-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 3953 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 3954 // CHECK7-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 [[TMP3]] 3955 // CHECK7-NEXT: [[TMP4:%.*]] = bitcast %struct.S* [[ARRAYIDX1]] to i8* 3956 // CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP4]], i8* align 4 bitcast (%struct.S* @var to i8*), i32 4, i1 false) 3957 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 3958 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 3959 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], [[TMP5]] 3960 // CHECK7-NEXT: store i32 [[ADD]], i32* @_ZZ4mainE5sivar, align 4 3961 // CHECK7-NEXT: br label [[FOR_INC:%.*]] 3962 // CHECK7: for.inc: 3963 // CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 3964 // CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 3965 // CHECK7-NEXT: store i32 [[INC]], i32* [[I]], align 4 3966 // CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] 3967 // CHECK7: for.end: 3968 // CHECK7-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() 3969 // CHECK7-NEXT: ret i32 [[CALL]] 3970 // 3971 // 3972 // CHECK7-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 3973 // CHECK7-SAME: () #[[ATTR5:[0-9]+]] comdat { 3974 // CHECK7-NEXT: entry: 3975 // CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 3976 // CHECK7-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 3977 // CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 3978 // CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 3979 // CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 3980 // CHECK7-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 3981 // CHECK7-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 3982 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 3983 // CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) 3984 // CHECK7-NEXT: store i32 0, i32* [[T_VAR]], align 4 3985 // CHECK7-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 3986 // CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) 3987 // CHECK7-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 3988 // CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) 3989 // CHECK7-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 3990 // CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) 3991 // CHECK7-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 3992 // CHECK7-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 3993 // CHECK7-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 3994 // CHECK7-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 3995 // CHECK7-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 3996 // CHECK7-NEXT: store i32 0, i32* [[I]], align 4 3997 // CHECK7-NEXT: br label [[FOR_COND:%.*]] 3998 // CHECK7: for.cond: 3999 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 4000 // CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP4]], 2 4001 // CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 4002 // CHECK7: for.body: 4003 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[T_VAR]], align 4 4004 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 4005 // CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP6]] 4006 // CHECK7-NEXT: store i32 [[TMP5]], i32* [[ARRAYIDX]], align 4 4007 // CHECK7-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 4008 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 4009 // CHECK7-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 [[TMP8]] 4010 // CHECK7-NEXT: [[TMP9:%.*]] = bitcast %struct.S.0* [[ARRAYIDX1]] to i8* 4011 // CHECK7-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[TMP7]] to i8* 4012 // CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP9]], i8* align 4 [[TMP10]], i32 4, i1 false) 4013 // CHECK7-NEXT: br label [[FOR_INC:%.*]] 4014 // CHECK7: for.inc: 4015 // CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 4016 // CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP11]], 1 4017 // CHECK7-NEXT: store i32 [[INC]], i32* [[I]], align 4 4018 // CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] 4019 // CHECK7: for.end: 4020 // CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 4021 // CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 4022 // CHECK7-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 4023 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 4024 // CHECK7: arraydestroy.body: 4025 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP12]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 4026 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 4027 // CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 4028 // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 4029 // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] 4030 // CHECK7: arraydestroy.done2: 4031 // CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] 4032 // CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[RETVAL]], align 4 4033 // CHECK7-NEXT: ret i32 [[TMP13]] 4034 // 4035 // 4036 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 4037 // CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4038 // CHECK7-NEXT: entry: 4039 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 4040 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 4041 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 4042 // CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 4043 // CHECK7-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 4044 // CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 4045 // CHECK7-NEXT: store float [[CONV]], float* [[F]], align 4 4046 // CHECK7-NEXT: ret void 4047 // 4048 // 4049 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 4050 // CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4051 // CHECK7-NEXT: entry: 4052 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 4053 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 4054 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 4055 // CHECK7-NEXT: ret void 4056 // 4057 // 4058 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 4059 // CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4060 // CHECK7-NEXT: entry: 4061 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 4062 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 4063 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 4064 // CHECK7-NEXT: store float [[A]], float* [[A_ADDR]], align 4 4065 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 4066 // CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 4067 // CHECK7-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 4068 // CHECK7-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 4069 // CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 4070 // CHECK7-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 4071 // CHECK7-NEXT: store float [[ADD]], float* [[F]], align 4 4072 // CHECK7-NEXT: ret void 4073 // 4074 // 4075 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 4076 // CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4077 // CHECK7-NEXT: entry: 4078 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 4079 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 4080 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 4081 // CHECK7-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) 4082 // CHECK7-NEXT: ret void 4083 // 4084 // 4085 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 4086 // CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4087 // CHECK7-NEXT: entry: 4088 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 4089 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 4090 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 4091 // CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 4092 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 4093 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 4094 // CHECK7-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) 4095 // CHECK7-NEXT: ret void 4096 // 4097 // 4098 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 4099 // CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4100 // CHECK7-NEXT: entry: 4101 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 4102 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 4103 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 4104 // CHECK7-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 4105 // CHECK7-NEXT: ret void 4106 // 4107 // 4108 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 4109 // CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4110 // CHECK7-NEXT: entry: 4111 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 4112 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 4113 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 4114 // CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 4115 // CHECK7-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 4116 // CHECK7-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 4117 // CHECK7-NEXT: ret void 4118 // 4119 // 4120 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 4121 // CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4122 // CHECK7-NEXT: entry: 4123 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 4124 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 4125 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 4126 // CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 4127 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 4128 // CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 4129 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 4130 // CHECK7-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 4131 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] 4132 // CHECK7-NEXT: store i32 [[ADD]], i32* [[F]], align 4 4133 // CHECK7-NEXT: ret void 4134 // 4135 // 4136 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 4137 // CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4138 // CHECK7-NEXT: entry: 4139 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 4140 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 4141 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 4142 // CHECK7-NEXT: ret void 4143 // 4144 // 4145 // CHECK7-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_firstprivate_codegen.cpp 4146 // CHECK7-SAME: () #[[ATTR0]] { 4147 // CHECK7-NEXT: entry: 4148 // CHECK7-NEXT: call void @__cxx_global_var_init() 4149 // CHECK7-NEXT: call void @__cxx_global_var_init.1() 4150 // CHECK7-NEXT: call void @__cxx_global_var_init.2() 4151 // CHECK7-NEXT: ret void 4152 // 4153 // 4154 // CHECK8-LABEL: define {{[^@]+}}@__cxx_global_var_init 4155 // CHECK8-SAME: () #[[ATTR0:[0-9]+]] { 4156 // CHECK8-NEXT: entry: 4157 // CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) 4158 // CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] 4159 // CHECK8-NEXT: ret void 4160 // 4161 // 4162 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 4163 // CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 4164 // CHECK8-NEXT: entry: 4165 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 4166 // CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 4167 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 4168 // CHECK8-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) 4169 // CHECK8-NEXT: ret void 4170 // 4171 // 4172 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 4173 // CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4174 // CHECK8-NEXT: entry: 4175 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 4176 // CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 4177 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 4178 // CHECK8-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 4179 // CHECK8-NEXT: ret void 4180 // 4181 // 4182 // CHECK8-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 4183 // CHECK8-SAME: () #[[ATTR0]] { 4184 // CHECK8-NEXT: entry: 4185 // CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float 1.000000e+00) 4186 // CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float 2.000000e+00) 4187 // CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] 4188 // CHECK8-NEXT: ret void 4189 // 4190 // 4191 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 4192 // CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4193 // CHECK8-NEXT: entry: 4194 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 4195 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 4196 // CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 4197 // CHECK8-NEXT: store float [[A]], float* [[A_ADDR]], align 4 4198 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 4199 // CHECK8-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 4200 // CHECK8-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) 4201 // CHECK8-NEXT: ret void 4202 // 4203 // 4204 // CHECK8-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 4205 // CHECK8-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { 4206 // CHECK8-NEXT: entry: 4207 // CHECK8-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 4208 // CHECK8-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4 4209 // CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 4210 // CHECK8: arraydestroy.body: 4211 // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 4212 // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 4213 // CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 4214 // CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) 4215 // CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 4216 // CHECK8: arraydestroy.done1: 4217 // CHECK8-NEXT: ret void 4218 // 4219 // 4220 // CHECK8-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 4221 // CHECK8-SAME: () #[[ATTR0]] { 4222 // CHECK8-NEXT: entry: 4223 // CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) 4224 // CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] 4225 // CHECK8-NEXT: ret void 4226 // 4227 // 4228 // CHECK8-LABEL: define {{[^@]+}}@main 4229 // CHECK8-SAME: () #[[ATTR3:[0-9]+]] { 4230 // CHECK8-NEXT: entry: 4231 // CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 4232 // CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 4233 // CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 4234 // CHECK8-NEXT: store i32 0, i32* [[I]], align 4 4235 // CHECK8-NEXT: br label [[FOR_COND:%.*]] 4236 // CHECK8: for.cond: 4237 // CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 4238 // CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 4239 // CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 4240 // CHECK8: for.body: 4241 // CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* @t_var, align 4 4242 // CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 4243 // CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* @vec, i32 0, i32 [[TMP2]] 4244 // CHECK8-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 4245 // CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 4246 // CHECK8-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 [[TMP3]] 4247 // CHECK8-NEXT: [[TMP4:%.*]] = bitcast %struct.S* [[ARRAYIDX1]] to i8* 4248 // CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP4]], i8* align 4 bitcast (%struct.S* @var to i8*), i32 4, i1 false) 4249 // CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 4250 // CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 4251 // CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], [[TMP5]] 4252 // CHECK8-NEXT: store i32 [[ADD]], i32* @_ZZ4mainE5sivar, align 4 4253 // CHECK8-NEXT: br label [[FOR_INC:%.*]] 4254 // CHECK8: for.inc: 4255 // CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 4256 // CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 4257 // CHECK8-NEXT: store i32 [[INC]], i32* [[I]], align 4 4258 // CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] 4259 // CHECK8: for.end: 4260 // CHECK8-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() 4261 // CHECK8-NEXT: ret i32 [[CALL]] 4262 // 4263 // 4264 // CHECK8-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 4265 // CHECK8-SAME: () #[[ATTR5:[0-9]+]] comdat { 4266 // CHECK8-NEXT: entry: 4267 // CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 4268 // CHECK8-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 4269 // CHECK8-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 4270 // CHECK8-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 4271 // CHECK8-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 4272 // CHECK8-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 4273 // CHECK8-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 4274 // CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 4275 // CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) 4276 // CHECK8-NEXT: store i32 0, i32* [[T_VAR]], align 4 4277 // CHECK8-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 4278 // CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) 4279 // CHECK8-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 4280 // CHECK8-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) 4281 // CHECK8-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 4282 // CHECK8-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) 4283 // CHECK8-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 4284 // CHECK8-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 4285 // CHECK8-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 4286 // CHECK8-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 4287 // CHECK8-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 4288 // CHECK8-NEXT: store i32 0, i32* [[I]], align 4 4289 // CHECK8-NEXT: br label [[FOR_COND:%.*]] 4290 // CHECK8: for.cond: 4291 // CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 4292 // CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP4]], 2 4293 // CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 4294 // CHECK8: for.body: 4295 // CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[T_VAR]], align 4 4296 // CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 4297 // CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP6]] 4298 // CHECK8-NEXT: store i32 [[TMP5]], i32* [[ARRAYIDX]], align 4 4299 // CHECK8-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 4300 // CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 4301 // CHECK8-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 [[TMP8]] 4302 // CHECK8-NEXT: [[TMP9:%.*]] = bitcast %struct.S.0* [[ARRAYIDX1]] to i8* 4303 // CHECK8-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[TMP7]] to i8* 4304 // CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP9]], i8* align 4 [[TMP10]], i32 4, i1 false) 4305 // CHECK8-NEXT: br label [[FOR_INC:%.*]] 4306 // CHECK8: for.inc: 4307 // CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 4308 // CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP11]], 1 4309 // CHECK8-NEXT: store i32 [[INC]], i32* [[I]], align 4 4310 // CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] 4311 // CHECK8: for.end: 4312 // CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 4313 // CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 4314 // CHECK8-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 4315 // CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 4316 // CHECK8: arraydestroy.body: 4317 // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP12]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 4318 // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 4319 // CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 4320 // CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 4321 // CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] 4322 // CHECK8: arraydestroy.done2: 4323 // CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] 4324 // CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[RETVAL]], align 4 4325 // CHECK8-NEXT: ret i32 [[TMP13]] 4326 // 4327 // 4328 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 4329 // CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4330 // CHECK8-NEXT: entry: 4331 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 4332 // CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 4333 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 4334 // CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 4335 // CHECK8-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 4336 // CHECK8-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 4337 // CHECK8-NEXT: store float [[CONV]], float* [[F]], align 4 4338 // CHECK8-NEXT: ret void 4339 // 4340 // 4341 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 4342 // CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4343 // CHECK8-NEXT: entry: 4344 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 4345 // CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 4346 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 4347 // CHECK8-NEXT: ret void 4348 // 4349 // 4350 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 4351 // CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4352 // CHECK8-NEXT: entry: 4353 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 4354 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 4355 // CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 4356 // CHECK8-NEXT: store float [[A]], float* [[A_ADDR]], align 4 4357 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 4358 // CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 4359 // CHECK8-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 4360 // CHECK8-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 4361 // CHECK8-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 4362 // CHECK8-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 4363 // CHECK8-NEXT: store float [[ADD]], float* [[F]], align 4 4364 // CHECK8-NEXT: ret void 4365 // 4366 // 4367 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 4368 // CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4369 // CHECK8-NEXT: entry: 4370 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 4371 // CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 4372 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 4373 // CHECK8-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) 4374 // CHECK8-NEXT: ret void 4375 // 4376 // 4377 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 4378 // CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4379 // CHECK8-NEXT: entry: 4380 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 4381 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 4382 // CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 4383 // CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 4384 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 4385 // CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 4386 // CHECK8-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) 4387 // CHECK8-NEXT: ret void 4388 // 4389 // 4390 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 4391 // CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4392 // CHECK8-NEXT: entry: 4393 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 4394 // CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 4395 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 4396 // CHECK8-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 4397 // CHECK8-NEXT: ret void 4398 // 4399 // 4400 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 4401 // CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4402 // CHECK8-NEXT: entry: 4403 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 4404 // CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 4405 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 4406 // CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 4407 // CHECK8-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 4408 // CHECK8-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 4409 // CHECK8-NEXT: ret void 4410 // 4411 // 4412 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 4413 // CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4414 // CHECK8-NEXT: entry: 4415 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 4416 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 4417 // CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 4418 // CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 4419 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 4420 // CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 4421 // CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 4422 // CHECK8-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 4423 // CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] 4424 // CHECK8-NEXT: store i32 [[ADD]], i32* [[F]], align 4 4425 // CHECK8-NEXT: ret void 4426 // 4427 // 4428 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 4429 // CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4430 // CHECK8-NEXT: entry: 4431 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 4432 // CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 4433 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 4434 // CHECK8-NEXT: ret void 4435 // 4436 // 4437 // CHECK8-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_firstprivate_codegen.cpp 4438 // CHECK8-SAME: () #[[ATTR0]] { 4439 // CHECK8-NEXT: entry: 4440 // CHECK8-NEXT: call void @__cxx_global_var_init() 4441 // CHECK8-NEXT: call void @__cxx_global_var_init.1() 4442 // CHECK8-NEXT: call void @__cxx_global_var_init.2() 4443 // CHECK8-NEXT: ret void 4444 // 4445 // 4446 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init 4447 // CHECK9-SAME: () #[[ATTR0:[0-9]+]] { 4448 // CHECK9-NEXT: entry: 4449 // CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) 4450 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] 4451 // CHECK9-NEXT: ret void 4452 // 4453 // 4454 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 4455 // CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 4456 // CHECK9-NEXT: entry: 4457 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 4458 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 4459 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 4460 // CHECK9-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) 4461 // CHECK9-NEXT: ret void 4462 // 4463 // 4464 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 4465 // CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4466 // CHECK9-NEXT: entry: 4467 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 4468 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 4469 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 4470 // CHECK9-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 4471 // CHECK9-NEXT: ret void 4472 // 4473 // 4474 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 4475 // CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4476 // CHECK9-NEXT: entry: 4477 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 4478 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 4479 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 4480 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 4481 // CHECK9-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 4482 // CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 4483 // CHECK9-NEXT: store float [[CONV]], float* [[F]], align 4 4484 // CHECK9-NEXT: ret void 4485 // 4486 // 4487 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 4488 // CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4489 // CHECK9-NEXT: entry: 4490 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 4491 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 4492 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 4493 // CHECK9-NEXT: ret void 4494 // 4495 // 4496 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 4497 // CHECK9-SAME: () #[[ATTR0]] { 4498 // CHECK9-NEXT: entry: 4499 // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) 4500 // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) 4501 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] 4502 // CHECK9-NEXT: ret void 4503 // 4504 // 4505 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 4506 // CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4507 // CHECK9-NEXT: entry: 4508 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 4509 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 4510 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 4511 // CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4 4512 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 4513 // CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 4514 // CHECK9-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) 4515 // CHECK9-NEXT: ret void 4516 // 4517 // 4518 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 4519 // CHECK9-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { 4520 // CHECK9-NEXT: entry: 4521 // CHECK9-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 4522 // CHECK9-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 4523 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 4524 // CHECK9: arraydestroy.body: 4525 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 4526 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 4527 // CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 4528 // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) 4529 // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 4530 // CHECK9: arraydestroy.done1: 4531 // CHECK9-NEXT: ret void 4532 // 4533 // 4534 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 4535 // CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4536 // CHECK9-NEXT: entry: 4537 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 4538 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 4539 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 4540 // CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4 4541 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 4542 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 4543 // CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 4544 // CHECK9-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 4545 // CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 4546 // CHECK9-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 4547 // CHECK9-NEXT: store float [[ADD]], float* [[F]], align 4 4548 // CHECK9-NEXT: ret void 4549 // 4550 // 4551 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 4552 // CHECK9-SAME: () #[[ATTR0]] { 4553 // CHECK9-NEXT: entry: 4554 // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) 4555 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] 4556 // CHECK9-NEXT: ret void 4557 // 4558 // 4559 // CHECK9-LABEL: define {{[^@]+}}@main 4560 // CHECK9-SAME: () #[[ATTR3:[0-9]+]] { 4561 // CHECK9-NEXT: entry: 4562 // CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 4563 // CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 4564 // CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 4565 // CHECK9-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) 4566 // CHECK9-NEXT: ret i32 0 4567 // 4568 // 4569 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l74 4570 // CHECK9-SAME: (i64 [[G:%.*]], i64 [[G1:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR5:[0-9]+]] { 4571 // CHECK9-NEXT: entry: 4572 // CHECK9-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8 4573 // CHECK9-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 4574 // CHECK9-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 4575 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32*, align 8 4576 // CHECK9-NEXT: [[G_CASTED:%.*]] = alloca i64, align 8 4577 // CHECK9-NEXT: [[G1_CASTED:%.*]] = alloca i64, align 8 4578 // CHECK9-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 4579 // CHECK9-NEXT: store i64 [[G]], i64* [[G_ADDR]], align 8 4580 // CHECK9-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8 4581 // CHECK9-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 4582 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[G_ADDR]] to i32* 4583 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[G1_ADDR]] to i32* 4584 // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* 4585 // CHECK9-NEXT: store i32* [[CONV1]], i32** [[TMP]], align 8 4586 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 4587 // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[G_CASTED]] to i32* 4588 // CHECK9-NEXT: store i32 [[TMP0]], i32* [[CONV3]], align 4 4589 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[G_CASTED]], align 8 4590 // CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[TMP]], align 8 4591 // CHECK9-NEXT: [[TMP3:%.*]] = load volatile i32, i32* [[TMP2]], align 4 4592 // CHECK9-NEXT: [[CONV4:%.*]] = bitcast i64* [[G1_CASTED]] to i32* 4593 // CHECK9-NEXT: store i32 [[TMP3]], i32* [[CONV4]], align 4 4594 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[G1_CASTED]], align 8 4595 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV2]], align 8 4596 // CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* 4597 // CHECK9-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4 4598 // CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 4599 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP4]], i64 [[TMP6]]) 4600 // CHECK9-NEXT: ret void 4601 // 4602 // 4603 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. 4604 // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[G:%.*]], i64 [[G1:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR5]] { 4605 // CHECK9-NEXT: entry: 4606 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 4607 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 4608 // CHECK9-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8 4609 // CHECK9-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 4610 // CHECK9-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 4611 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32*, align 8 4612 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 4613 // CHECK9-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 4614 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 4615 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 4616 // CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 4617 // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 4618 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 4619 // CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 4620 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 4621 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 4622 // CHECK9-NEXT: store i64 [[G]], i64* [[G_ADDR]], align 8 4623 // CHECK9-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8 4624 // CHECK9-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 4625 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[G_ADDR]] to i32* 4626 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[G1_ADDR]] to i32* 4627 // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* 4628 // CHECK9-NEXT: store i32* [[CONV1]], i32** [[TMP]], align 8 4629 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 4630 // CHECK9-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 4631 // CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 4632 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 4633 // CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 4634 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 4635 // CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 4636 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4637 // CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 4638 // CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 4639 // CHECK9: cond.true: 4640 // CHECK9-NEXT: br label [[COND_END:%.*]] 4641 // CHECK9: cond.false: 4642 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4643 // CHECK9-NEXT: br label [[COND_END]] 4644 // CHECK9: cond.end: 4645 // CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 4646 // CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 4647 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 4648 // CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 4649 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4650 // CHECK9: omp.inner.for.cond: 4651 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4652 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4653 // CHECK9-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 4654 // CHECK9-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 4655 // CHECK9: omp.inner.for.body: 4656 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4657 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 4658 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 4659 // CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 4660 // CHECK9-NEXT: store i32 1, i32* [[CONV]], align 8 4661 // CHECK9-NEXT: [[TMP8:%.*]] = load i32*, i32** [[TMP]], align 8 4662 // CHECK9-NEXT: store volatile i32 1, i32* [[TMP8]], align 4 4663 // CHECK9-NEXT: store i32 2, i32* [[CONV2]], align 8 4664 // CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 4665 // CHECK9-NEXT: store i32* [[CONV]], i32** [[TMP9]], align 8 4666 // CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 4667 // CHECK9-NEXT: [[TMP11:%.*]] = load i32*, i32** [[TMP]], align 8 4668 // CHECK9-NEXT: store i32* [[TMP11]], i32** [[TMP10]], align 8 4669 // CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 4670 // CHECK9-NEXT: store i32* [[CONV2]], i32** [[TMP12]], align 8 4671 // CHECK9-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(24) [[REF_TMP]]) 4672 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 4673 // CHECK9: omp.body.continue: 4674 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4675 // CHECK9: omp.inner.for.inc: 4676 // CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4677 // CHECK9-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP13]], 1 4678 // CHECK9-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 4679 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] 4680 // CHECK9: omp.inner.for.end: 4681 // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 4682 // CHECK9: omp.loop.exit: 4683 // CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 4684 // CHECK9-NEXT: ret void 4685 // 4686 // 4687 // CHECK9-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_firstprivate_codegen.cpp 4688 // CHECK9-SAME: () #[[ATTR0]] { 4689 // CHECK9-NEXT: entry: 4690 // CHECK9-NEXT: call void @__cxx_global_var_init() 4691 // CHECK9-NEXT: call void @__cxx_global_var_init.1() 4692 // CHECK9-NEXT: call void @__cxx_global_var_init.2() 4693 // CHECK9-NEXT: ret void 4694 // 4695 // 4696 // CHECK9-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 4697 // CHECK9-SAME: () #[[ATTR0]] { 4698 // CHECK9-NEXT: entry: 4699 // CHECK9-NEXT: call void @__tgt_register_requires(i64 1) 4700 // CHECK9-NEXT: ret void 4701 // 4702 // 4703 // CHECK10-LABEL: define {{[^@]+}}@__cxx_global_var_init 4704 // CHECK10-SAME: () #[[ATTR0:[0-9]+]] { 4705 // CHECK10-NEXT: entry: 4706 // CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) 4707 // CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] 4708 // CHECK10-NEXT: ret void 4709 // 4710 // 4711 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 4712 // CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 4713 // CHECK10-NEXT: entry: 4714 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 4715 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 4716 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 4717 // CHECK10-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) 4718 // CHECK10-NEXT: ret void 4719 // 4720 // 4721 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 4722 // CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4723 // CHECK10-NEXT: entry: 4724 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 4725 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 4726 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 4727 // CHECK10-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 4728 // CHECK10-NEXT: ret void 4729 // 4730 // 4731 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 4732 // CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4733 // CHECK10-NEXT: entry: 4734 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 4735 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 4736 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 4737 // CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 4738 // CHECK10-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 4739 // CHECK10-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 4740 // CHECK10-NEXT: store float [[CONV]], float* [[F]], align 4 4741 // CHECK10-NEXT: ret void 4742 // 4743 // 4744 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 4745 // CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4746 // CHECK10-NEXT: entry: 4747 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 4748 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 4749 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 4750 // CHECK10-NEXT: ret void 4751 // 4752 // 4753 // CHECK10-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 4754 // CHECK10-SAME: () #[[ATTR0]] { 4755 // CHECK10-NEXT: entry: 4756 // CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) 4757 // CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) 4758 // CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] 4759 // CHECK10-NEXT: ret void 4760 // 4761 // 4762 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 4763 // CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4764 // CHECK10-NEXT: entry: 4765 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 4766 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 4767 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 4768 // CHECK10-NEXT: store float [[A]], float* [[A_ADDR]], align 4 4769 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 4770 // CHECK10-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 4771 // CHECK10-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) 4772 // CHECK10-NEXT: ret void 4773 // 4774 // 4775 // CHECK10-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 4776 // CHECK10-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { 4777 // CHECK10-NEXT: entry: 4778 // CHECK10-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 4779 // CHECK10-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 4780 // CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 4781 // CHECK10: arraydestroy.body: 4782 // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 4783 // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 4784 // CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 4785 // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) 4786 // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 4787 // CHECK10: arraydestroy.done1: 4788 // CHECK10-NEXT: ret void 4789 // 4790 // 4791 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 4792 // CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4793 // CHECK10-NEXT: entry: 4794 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 4795 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 4796 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 4797 // CHECK10-NEXT: store float [[A]], float* [[A_ADDR]], align 4 4798 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 4799 // CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 4800 // CHECK10-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 4801 // CHECK10-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 4802 // CHECK10-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 4803 // CHECK10-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 4804 // CHECK10-NEXT: store float [[ADD]], float* [[F]], align 4 4805 // CHECK10-NEXT: ret void 4806 // 4807 // 4808 // CHECK10-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 4809 // CHECK10-SAME: () #[[ATTR0]] { 4810 // CHECK10-NEXT: entry: 4811 // CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) 4812 // CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] 4813 // CHECK10-NEXT: ret void 4814 // 4815 // 4816 // CHECK10-LABEL: define {{[^@]+}}@main 4817 // CHECK10-SAME: () #[[ATTR3:[0-9]+]] { 4818 // CHECK10-NEXT: entry: 4819 // CHECK10-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 4820 // CHECK10-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 4821 // CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4 4822 // CHECK10-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) 4823 // CHECK10-NEXT: ret i32 0 4824 // 4825 // 4826 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l74 4827 // CHECK10-SAME: (i64 [[G:%.*]], i64 [[G1:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR5:[0-9]+]] { 4828 // CHECK10-NEXT: entry: 4829 // CHECK10-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8 4830 // CHECK10-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 4831 // CHECK10-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 4832 // CHECK10-NEXT: [[TMP:%.*]] = alloca i32*, align 8 4833 // CHECK10-NEXT: [[G_CASTED:%.*]] = alloca i64, align 8 4834 // CHECK10-NEXT: [[G1_CASTED:%.*]] = alloca i64, align 8 4835 // CHECK10-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 4836 // CHECK10-NEXT: store i64 [[G]], i64* [[G_ADDR]], align 8 4837 // CHECK10-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8 4838 // CHECK10-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 4839 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[G_ADDR]] to i32* 4840 // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[G1_ADDR]] to i32* 4841 // CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* 4842 // CHECK10-NEXT: store i32* [[CONV1]], i32** [[TMP]], align 8 4843 // CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 4844 // CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[G_CASTED]] to i32* 4845 // CHECK10-NEXT: store i32 [[TMP0]], i32* [[CONV3]], align 4 4846 // CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[G_CASTED]], align 8 4847 // CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[TMP]], align 8 4848 // CHECK10-NEXT: [[TMP3:%.*]] = load volatile i32, i32* [[TMP2]], align 4 4849 // CHECK10-NEXT: [[CONV4:%.*]] = bitcast i64* [[G1_CASTED]] to i32* 4850 // CHECK10-NEXT: store i32 [[TMP3]], i32* [[CONV4]], align 4 4851 // CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[G1_CASTED]], align 8 4852 // CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV2]], align 8 4853 // CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* 4854 // CHECK10-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4 4855 // CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 4856 // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP4]], i64 [[TMP6]]) 4857 // CHECK10-NEXT: ret void 4858 // 4859 // 4860 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. 4861 // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[G:%.*]], i64 [[G1:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR5]] { 4862 // CHECK10-NEXT: entry: 4863 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 4864 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 4865 // CHECK10-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8 4866 // CHECK10-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 4867 // CHECK10-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 4868 // CHECK10-NEXT: [[TMP:%.*]] = alloca i32*, align 8 4869 // CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 4870 // CHECK10-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 4871 // CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 4872 // CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 4873 // CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 4874 // CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 4875 // CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 4876 // CHECK10-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 4877 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 4878 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 4879 // CHECK10-NEXT: store i64 [[G]], i64* [[G_ADDR]], align 8 4880 // CHECK10-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8 4881 // CHECK10-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 4882 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[G_ADDR]] to i32* 4883 // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[G1_ADDR]] to i32* 4884 // CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* 4885 // CHECK10-NEXT: store i32* [[CONV1]], i32** [[TMP]], align 8 4886 // CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 4887 // CHECK10-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 4888 // CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 4889 // CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 4890 // CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 4891 // CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 4892 // CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 4893 // CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4894 // CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 4895 // CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 4896 // CHECK10: cond.true: 4897 // CHECK10-NEXT: br label [[COND_END:%.*]] 4898 // CHECK10: cond.false: 4899 // CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4900 // CHECK10-NEXT: br label [[COND_END]] 4901 // CHECK10: cond.end: 4902 // CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 4903 // CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 4904 // CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 4905 // CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 4906 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4907 // CHECK10: omp.inner.for.cond: 4908 // CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4909 // CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4910 // CHECK10-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 4911 // CHECK10-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 4912 // CHECK10: omp.inner.for.body: 4913 // CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4914 // CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 4915 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 4916 // CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 4917 // CHECK10-NEXT: store i32 1, i32* [[CONV]], align 8 4918 // CHECK10-NEXT: [[TMP8:%.*]] = load i32*, i32** [[TMP]], align 8 4919 // CHECK10-NEXT: store volatile i32 1, i32* [[TMP8]], align 4 4920 // CHECK10-NEXT: store i32 2, i32* [[CONV2]], align 8 4921 // CHECK10-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 4922 // CHECK10-NEXT: store i32* [[CONV]], i32** [[TMP9]], align 8 4923 // CHECK10-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 4924 // CHECK10-NEXT: [[TMP11:%.*]] = load i32*, i32** [[TMP]], align 8 4925 // CHECK10-NEXT: store i32* [[TMP11]], i32** [[TMP10]], align 8 4926 // CHECK10-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 4927 // CHECK10-NEXT: store i32* [[CONV2]], i32** [[TMP12]], align 8 4928 // CHECK10-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(24) [[REF_TMP]]) 4929 // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 4930 // CHECK10: omp.body.continue: 4931 // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4932 // CHECK10: omp.inner.for.inc: 4933 // CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4934 // CHECK10-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP13]], 1 4935 // CHECK10-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 4936 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] 4937 // CHECK10: omp.inner.for.end: 4938 // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 4939 // CHECK10: omp.loop.exit: 4940 // CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 4941 // CHECK10-NEXT: ret void 4942 // 4943 // 4944 // CHECK10-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_firstprivate_codegen.cpp 4945 // CHECK10-SAME: () #[[ATTR0]] { 4946 // CHECK10-NEXT: entry: 4947 // CHECK10-NEXT: call void @__cxx_global_var_init() 4948 // CHECK10-NEXT: call void @__cxx_global_var_init.1() 4949 // CHECK10-NEXT: call void @__cxx_global_var_init.2() 4950 // CHECK10-NEXT: ret void 4951 // 4952 // 4953 // CHECK10-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 4954 // CHECK10-SAME: () #[[ATTR0]] { 4955 // CHECK10-NEXT: entry: 4956 // CHECK10-NEXT: call void @__tgt_register_requires(i64 1) 4957 // CHECK10-NEXT: ret void 4958 // 4959 // 4960 // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init 4961 // CHECK11-SAME: () #[[ATTR0:[0-9]+]] { 4962 // CHECK11-NEXT: entry: 4963 // CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) 4964 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] 4965 // CHECK11-NEXT: ret void 4966 // 4967 // 4968 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 4969 // CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 4970 // CHECK11-NEXT: entry: 4971 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 4972 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 4973 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 4974 // CHECK11-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) 4975 // CHECK11-NEXT: ret void 4976 // 4977 // 4978 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 4979 // CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4980 // CHECK11-NEXT: entry: 4981 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 4982 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 4983 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 4984 // CHECK11-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 4985 // CHECK11-NEXT: ret void 4986 // 4987 // 4988 // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 4989 // CHECK11-SAME: () #[[ATTR0]] { 4990 // CHECK11-NEXT: entry: 4991 // CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) 4992 // CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) 4993 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] 4994 // CHECK11-NEXT: ret void 4995 // 4996 // 4997 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 4998 // CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4999 // CHECK11-NEXT: entry: 5000 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 5001 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 5002 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 5003 // CHECK11-NEXT: store float [[A]], float* [[A_ADDR]], align 4 5004 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 5005 // CHECK11-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 5006 // CHECK11-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) 5007 // CHECK11-NEXT: ret void 5008 // 5009 // 5010 // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 5011 // CHECK11-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { 5012 // CHECK11-NEXT: entry: 5013 // CHECK11-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 5014 // CHECK11-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 5015 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 5016 // CHECK11: arraydestroy.body: 5017 // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 5018 // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 5019 // CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 5020 // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) 5021 // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 5022 // CHECK11: arraydestroy.done1: 5023 // CHECK11-NEXT: ret void 5024 // 5025 // 5026 // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 5027 // CHECK11-SAME: () #[[ATTR0]] { 5028 // CHECK11-NEXT: entry: 5029 // CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) 5030 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] 5031 // CHECK11-NEXT: ret void 5032 // 5033 // 5034 // CHECK11-LABEL: define {{[^@]+}}@main 5035 // CHECK11-SAME: () #[[ATTR3:[0-9]+]] { 5036 // CHECK11-NEXT: entry: 5037 // CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 5038 // CHECK11-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 5039 // CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4 5040 // CHECK11-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) 5041 // CHECK11-NEXT: ret i32 0 5042 // 5043 // 5044 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 5045 // CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 5046 // CHECK11-NEXT: entry: 5047 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 5048 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 5049 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 5050 // CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 5051 // CHECK11-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 5052 // CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 5053 // CHECK11-NEXT: store float [[CONV]], float* [[F]], align 4 5054 // CHECK11-NEXT: ret void 5055 // 5056 // 5057 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 5058 // CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 5059 // CHECK11-NEXT: entry: 5060 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 5061 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 5062 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 5063 // CHECK11-NEXT: ret void 5064 // 5065 // 5066 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 5067 // CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 5068 // CHECK11-NEXT: entry: 5069 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 5070 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 5071 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 5072 // CHECK11-NEXT: store float [[A]], float* [[A_ADDR]], align 4 5073 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 5074 // CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 5075 // CHECK11-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 5076 // CHECK11-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 5077 // CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 5078 // CHECK11-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 5079 // CHECK11-NEXT: store float [[ADD]], float* [[F]], align 4 5080 // CHECK11-NEXT: ret void 5081 // 5082 // 5083 // CHECK11-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_firstprivate_codegen.cpp 5084 // CHECK11-SAME: () #[[ATTR0]] { 5085 // CHECK11-NEXT: entry: 5086 // CHECK11-NEXT: call void @__cxx_global_var_init() 5087 // CHECK11-NEXT: call void @__cxx_global_var_init.1() 5088 // CHECK11-NEXT: call void @__cxx_global_var_init.2() 5089 // CHECK11-NEXT: ret void 5090 // 5091 // 5092 // CHECK12-LABEL: define {{[^@]+}}@__cxx_global_var_init 5093 // CHECK12-SAME: () #[[ATTR0:[0-9]+]] { 5094 // CHECK12-NEXT: entry: 5095 // CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) 5096 // CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] 5097 // CHECK12-NEXT: ret void 5098 // 5099 // 5100 // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 5101 // CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 5102 // CHECK12-NEXT: entry: 5103 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 5104 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 5105 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 5106 // CHECK12-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) 5107 // CHECK12-NEXT: ret void 5108 // 5109 // 5110 // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 5111 // CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 5112 // CHECK12-NEXT: entry: 5113 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 5114 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 5115 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 5116 // CHECK12-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 5117 // CHECK12-NEXT: ret void 5118 // 5119 // 5120 // CHECK12-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 5121 // CHECK12-SAME: () #[[ATTR0]] { 5122 // CHECK12-NEXT: entry: 5123 // CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) 5124 // CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) 5125 // CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] 5126 // CHECK12-NEXT: ret void 5127 // 5128 // 5129 // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 5130 // CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 5131 // CHECK12-NEXT: entry: 5132 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 5133 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 5134 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 5135 // CHECK12-NEXT: store float [[A]], float* [[A_ADDR]], align 4 5136 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 5137 // CHECK12-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 5138 // CHECK12-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) 5139 // CHECK12-NEXT: ret void 5140 // 5141 // 5142 // CHECK12-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 5143 // CHECK12-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { 5144 // CHECK12-NEXT: entry: 5145 // CHECK12-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 5146 // CHECK12-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 5147 // CHECK12-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 5148 // CHECK12: arraydestroy.body: 5149 // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 5150 // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 5151 // CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 5152 // CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) 5153 // CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 5154 // CHECK12: arraydestroy.done1: 5155 // CHECK12-NEXT: ret void 5156 // 5157 // 5158 // CHECK12-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 5159 // CHECK12-SAME: () #[[ATTR0]] { 5160 // CHECK12-NEXT: entry: 5161 // CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) 5162 // CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] 5163 // CHECK12-NEXT: ret void 5164 // 5165 // 5166 // CHECK12-LABEL: define {{[^@]+}}@main 5167 // CHECK12-SAME: () #[[ATTR3:[0-9]+]] { 5168 // CHECK12-NEXT: entry: 5169 // CHECK12-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 5170 // CHECK12-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 5171 // CHECK12-NEXT: store i32 0, i32* [[RETVAL]], align 4 5172 // CHECK12-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) 5173 // CHECK12-NEXT: ret i32 0 5174 // 5175 // 5176 // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 5177 // CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 5178 // CHECK12-NEXT: entry: 5179 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 5180 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 5181 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 5182 // CHECK12-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 5183 // CHECK12-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 5184 // CHECK12-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 5185 // CHECK12-NEXT: store float [[CONV]], float* [[F]], align 4 5186 // CHECK12-NEXT: ret void 5187 // 5188 // 5189 // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 5190 // CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 5191 // CHECK12-NEXT: entry: 5192 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 5193 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 5194 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 5195 // CHECK12-NEXT: ret void 5196 // 5197 // 5198 // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 5199 // CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 5200 // CHECK12-NEXT: entry: 5201 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 5202 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 5203 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 5204 // CHECK12-NEXT: store float [[A]], float* [[A_ADDR]], align 4 5205 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 5206 // CHECK12-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 5207 // CHECK12-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 5208 // CHECK12-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 5209 // CHECK12-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 5210 // CHECK12-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 5211 // CHECK12-NEXT: store float [[ADD]], float* [[F]], align 4 5212 // CHECK12-NEXT: ret void 5213 // 5214 // 5215 // CHECK12-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_firstprivate_codegen.cpp 5216 // CHECK12-SAME: () #[[ATTR0]] { 5217 // CHECK12-NEXT: entry: 5218 // CHECK12-NEXT: call void @__cxx_global_var_init() 5219 // CHECK12-NEXT: call void @__cxx_global_var_init.1() 5220 // CHECK12-NEXT: call void @__cxx_global_var_init.2() 5221 // CHECK12-NEXT: ret void 5222 // 5223