1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ 2 // expected-no-diagnostics 3 #ifndef HEADER 4 #define HEADER 5 6 // Test host codegen. 7 // RUN: %clang_cc1 -no-opaque-pointers -DCK1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 8 // RUN: %clang_cc1 -no-opaque-pointers -DCK1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 9 // RUN: %clang_cc1 -no-opaque-pointers -DCK1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK2 10 // RUN: %clang_cc1 -no-opaque-pointers -DCK1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 11 // RUN: %clang_cc1 -no-opaque-pointers -DCK1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 12 // RUN: %clang_cc1 -no-opaque-pointers -DCK1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 13 14 // RUN: %clang_cc1 -no-opaque-pointers -DCK1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 15 // RUN: %clang_cc1 -no-opaque-pointers -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 16 // RUN: %clang_cc1 -no-opaque-pointers -DCK1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 17 // RUN: %clang_cc1 -no-opaque-pointers -DCK1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 18 // RUN: %clang_cc1 -no-opaque-pointers -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 19 // RUN: %clang_cc1 -no-opaque-pointers -DCK1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 20 #ifdef CK1 21 22 template <typename T, int X, long long Y> 23 struct SS{ 24 T a[X][Y]; 25 26 int foo(void) { 27 28 #pragma omp target teams distribute collapse(2) 29 for(int i = 0; i < X; i++) { 30 for(int j = 0; j < Y; j++) { 31 a[i][j] = (T)0; 32 } 33 } 34 35 // discard loop variables not needed here 36 37 return a[0][0]; 38 } 39 }; 40 41 int teams_template_struct(void) { 42 SS<int, 123, 456> V; 43 return V.foo(); 44 45 } 46 #endif // CK1 47 48 // Test host codegen. 49 // RUN: %clang_cc1 -no-opaque-pointers -DCK2 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 50 // RUN: %clang_cc1 -no-opaque-pointers -DCK2 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 51 // RUN: %clang_cc1 -no-opaque-pointers -DCK2 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK10 52 // RUN: %clang_cc1 -no-opaque-pointers -DCK2 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11 53 // RUN: %clang_cc1 -no-opaque-pointers -DCK2 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 54 // RUN: %clang_cc1 -no-opaque-pointers -DCK2 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK12 55 56 // RUN: %clang_cc1 -no-opaque-pointers -DCK2 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 57 // RUN: %clang_cc1 -no-opaque-pointers -DCK2 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 58 // RUN: %clang_cc1 -no-opaque-pointers -DCK2 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 59 // RUN: %clang_cc1 -no-opaque-pointers -DCK2 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 60 // RUN: %clang_cc1 -no-opaque-pointers -DCK2 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 61 // RUN: %clang_cc1 -no-opaque-pointers -DCK2 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 62 #ifdef CK2 63 64 template <typename T, int n, int m> 65 int tmain(T argc) { 66 T a[n][m]; 67 #pragma omp target teams distribute collapse(2) 68 for(int i = 0; i < n; i++) { 69 for(int j = 0; j < m; j++) { 70 a[i][j] = (T)0; 71 } 72 } 73 return 0; 74 } 75 76 int main (int argc, char **argv) { 77 int n = 100; 78 int m = 2; 79 int a[n][m]; 80 #pragma omp target teams distribute collapse(2) 81 for(int i = 0; i < n; i++) { 82 for(int j = 0; j < m; j++) { 83 a[i][j] = 0; 84 } 85 } 86 return tmain<int, 10, 2>(argc); 87 } 88 89 90 91 92 93 // discard loop variables not needed here 94 95 #endif // CK2 96 #endif // #ifndef HEADER 97 // CHECK1-LABEL: define {{[^@]+}}@_Z21teams_template_structv 98 // CHECK1-SAME: () #[[ATTR0:[0-9]+]] { 99 // CHECK1-NEXT: entry: 100 // CHECK1-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 101 // CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef nonnull align 4 dereferenceable(224352) [[V]]) 102 // CHECK1-NEXT: ret i32 [[CALL]] 103 // 104 // 105 // CHECK1-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv 106 // CHECK1-SAME: (%struct.SS* noundef nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { 107 // CHECK1-NEXT: entry: 108 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 109 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 110 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 111 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 112 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 113 // CHECK1-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 114 // CHECK1-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 115 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 116 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 117 // CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 118 // CHECK1-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to %struct.SS** 119 // CHECK1-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP1]], align 8 120 // CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 121 // CHECK1-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [123 x [456 x i32]]** 122 // CHECK1-NEXT: store [123 x [456 x i32]]* [[A]], [123 x [456 x i32]]** [[TMP3]], align 8 123 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 124 // CHECK1-NEXT: store i8* null, i8** [[TMP4]], align 8 125 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 126 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 127 // CHECK1-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 56088) 128 // CHECK1-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 129 // CHECK1-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 130 // CHECK1-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 131 // CHECK1: omp_offload.failed: 132 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28(%struct.SS* [[THIS1]]) #[[ATTR2:[0-9]+]] 133 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 134 // CHECK1: omp_offload.cont: 135 // CHECK1-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 136 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A3]], i64 0, i64 0 137 // CHECK1-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX]], i64 0, i64 0 138 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[ARRAYIDX4]], align 4 139 // CHECK1-NEXT: ret i32 [[TMP9]] 140 // 141 // 142 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28 143 // CHECK1-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { 144 // CHECK1-NEXT: entry: 145 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 146 // CHECK1-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 147 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 148 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.SS*)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.SS* [[TMP0]]) 149 // CHECK1-NEXT: ret void 150 // 151 // 152 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. 153 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { 154 // CHECK1-NEXT: entry: 155 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 156 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 157 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 158 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 159 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 160 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 161 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 162 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 163 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 164 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 165 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 166 // CHECK1-NEXT: [[J:%.*]] = alloca i32, align 4 167 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 168 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 169 // CHECK1-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 170 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 171 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 172 // CHECK1-NEXT: store i32 56087, i32* [[DOTOMP_UB]], align 4 173 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 174 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 175 // CHECK1-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 176 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 177 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 178 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 179 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 56087 180 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 181 // CHECK1: cond.true: 182 // CHECK1-NEXT: br label [[COND_END:%.*]] 183 // CHECK1: cond.false: 184 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 185 // CHECK1-NEXT: br label [[COND_END]] 186 // CHECK1: cond.end: 187 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 56087, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 188 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 189 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 190 // CHECK1-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 191 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 192 // CHECK1: omp.inner.for.cond: 193 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 194 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 195 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] 196 // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 197 // CHECK1: omp.inner.for.body: 198 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 199 // CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP8]], 456 200 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 201 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 202 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4 203 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 204 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 205 // CHECK1-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP10]], 456 206 // CHECK1-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 456 207 // CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP9]], [[MUL4]] 208 // CHECK1-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1 209 // CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]] 210 // CHECK1-NEXT: store i32 [[ADD6]], i32* [[J]], align 4 211 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP0]], i32 0, i32 0 212 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 213 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 214 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A]], i64 0, i64 [[IDXPROM]] 215 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[J]], align 4 216 // CHECK1-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP12]] to i64 217 // CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX]], i64 0, i64 [[IDXPROM7]] 218 // CHECK1-NEXT: store i32 0, i32* [[ARRAYIDX8]], align 4 219 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 220 // CHECK1: omp.body.continue: 221 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 222 // CHECK1: omp.inner.for.inc: 223 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 224 // CHECK1-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP13]], 1 225 // CHECK1-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 226 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 227 // CHECK1: omp.inner.for.end: 228 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 229 // CHECK1: omp.loop.exit: 230 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) 231 // CHECK1-NEXT: ret void 232 // 233 // 234 // CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 235 // CHECK1-SAME: () #[[ATTR3:[0-9]+]] { 236 // CHECK1-NEXT: entry: 237 // CHECK1-NEXT: call void @__tgt_register_requires(i64 1) 238 // CHECK1-NEXT: ret void 239 // 240 // 241 // CHECK2-LABEL: define {{[^@]+}}@_Z21teams_template_structv 242 // CHECK2-SAME: () #[[ATTR0:[0-9]+]] { 243 // CHECK2-NEXT: entry: 244 // CHECK2-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 245 // CHECK2-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef nonnull align 4 dereferenceable(224352) [[V]]) 246 // CHECK2-NEXT: ret i32 [[CALL]] 247 // 248 // 249 // CHECK2-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv 250 // CHECK2-SAME: (%struct.SS* noundef nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { 251 // CHECK2-NEXT: entry: 252 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 253 // CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 254 // CHECK2-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 255 // CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 256 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4 257 // CHECK2-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 258 // CHECK2-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 259 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 260 // CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 261 // CHECK2-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 262 // CHECK2-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to %struct.SS** 263 // CHECK2-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP1]], align 8 264 // CHECK2-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 265 // CHECK2-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [123 x [456 x i32]]** 266 // CHECK2-NEXT: store [123 x [456 x i32]]* [[A]], [123 x [456 x i32]]** [[TMP3]], align 8 267 // CHECK2-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 268 // CHECK2-NEXT: store i8* null, i8** [[TMP4]], align 8 269 // CHECK2-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 270 // CHECK2-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 271 // CHECK2-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 56088) 272 // CHECK2-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 273 // CHECK2-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 274 // CHECK2-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 275 // CHECK2: omp_offload.failed: 276 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28(%struct.SS* [[THIS1]]) #[[ATTR2:[0-9]+]] 277 // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]] 278 // CHECK2: omp_offload.cont: 279 // CHECK2-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 280 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A3]], i64 0, i64 0 281 // CHECK2-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX]], i64 0, i64 0 282 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[ARRAYIDX4]], align 4 283 // CHECK2-NEXT: ret i32 [[TMP9]] 284 // 285 // 286 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28 287 // CHECK2-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { 288 // CHECK2-NEXT: entry: 289 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 290 // CHECK2-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 291 // CHECK2-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 292 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.SS*)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.SS* [[TMP0]]) 293 // CHECK2-NEXT: ret void 294 // 295 // 296 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. 297 // CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { 298 // CHECK2-NEXT: entry: 299 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 300 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 301 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 302 // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 303 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4 304 // CHECK2-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 305 // CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 306 // CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 307 // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 308 // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 309 // CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4 310 // CHECK2-NEXT: [[J:%.*]] = alloca i32, align 4 311 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 312 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 313 // CHECK2-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 314 // CHECK2-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 315 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 316 // CHECK2-NEXT: store i32 56087, i32* [[DOTOMP_UB]], align 4 317 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 318 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 319 // CHECK2-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 320 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 321 // CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 322 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 323 // CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 56087 324 // CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 325 // CHECK2: cond.true: 326 // CHECK2-NEXT: br label [[COND_END:%.*]] 327 // CHECK2: cond.false: 328 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 329 // CHECK2-NEXT: br label [[COND_END]] 330 // CHECK2: cond.end: 331 // CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 56087, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 332 // CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 333 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 334 // CHECK2-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 335 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 336 // CHECK2: omp.inner.for.cond: 337 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 338 // CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 339 // CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] 340 // CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 341 // CHECK2: omp.inner.for.body: 342 // CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 343 // CHECK2-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP8]], 456 344 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 345 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 346 // CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4 347 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 348 // CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 349 // CHECK2-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP10]], 456 350 // CHECK2-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 456 351 // CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP9]], [[MUL4]] 352 // CHECK2-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1 353 // CHECK2-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]] 354 // CHECK2-NEXT: store i32 [[ADD6]], i32* [[J]], align 4 355 // CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP0]], i32 0, i32 0 356 // CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 357 // CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 358 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A]], i64 0, i64 [[IDXPROM]] 359 // CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[J]], align 4 360 // CHECK2-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP12]] to i64 361 // CHECK2-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX]], i64 0, i64 [[IDXPROM7]] 362 // CHECK2-NEXT: store i32 0, i32* [[ARRAYIDX8]], align 4 363 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 364 // CHECK2: omp.body.continue: 365 // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 366 // CHECK2: omp.inner.for.inc: 367 // CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 368 // CHECK2-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP13]], 1 369 // CHECK2-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 370 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]] 371 // CHECK2: omp.inner.for.end: 372 // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 373 // CHECK2: omp.loop.exit: 374 // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) 375 // CHECK2-NEXT: ret void 376 // 377 // 378 // CHECK2-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 379 // CHECK2-SAME: () #[[ATTR3:[0-9]+]] { 380 // CHECK2-NEXT: entry: 381 // CHECK2-NEXT: call void @__tgt_register_requires(i64 1) 382 // CHECK2-NEXT: ret void 383 // 384 // 385 // CHECK3-LABEL: define {{[^@]+}}@_Z21teams_template_structv 386 // CHECK3-SAME: () #[[ATTR0:[0-9]+]] { 387 // CHECK3-NEXT: entry: 388 // CHECK3-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 389 // CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef nonnull align 4 dereferenceable(224352) [[V]]) 390 // CHECK3-NEXT: ret i32 [[CALL]] 391 // 392 // 393 // CHECK3-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv 394 // CHECK3-SAME: (%struct.SS* noundef nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { 395 // CHECK3-NEXT: entry: 396 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 397 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 398 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 399 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 400 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 401 // CHECK3-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 402 // CHECK3-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 403 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 404 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 405 // CHECK3-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 406 // CHECK3-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to %struct.SS** 407 // CHECK3-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP1]], align 4 408 // CHECK3-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 409 // CHECK3-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [123 x [456 x i32]]** 410 // CHECK3-NEXT: store [123 x [456 x i32]]* [[A]], [123 x [456 x i32]]** [[TMP3]], align 4 411 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 412 // CHECK3-NEXT: store i8* null, i8** [[TMP4]], align 4 413 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 414 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 415 // CHECK3-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 56088) 416 // CHECK3-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 417 // CHECK3-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 418 // CHECK3-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 419 // CHECK3: omp_offload.failed: 420 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28(%struct.SS* [[THIS1]]) #[[ATTR2:[0-9]+]] 421 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 422 // CHECK3: omp_offload.cont: 423 // CHECK3-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 424 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A3]], i32 0, i32 0 425 // CHECK3-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX]], i32 0, i32 0 426 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[ARRAYIDX4]], align 4 427 // CHECK3-NEXT: ret i32 [[TMP9]] 428 // 429 // 430 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28 431 // CHECK3-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { 432 // CHECK3-NEXT: entry: 433 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 434 // CHECK3-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 435 // CHECK3-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 436 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.SS*)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.SS* [[TMP0]]) 437 // CHECK3-NEXT: ret void 438 // 439 // 440 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. 441 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { 442 // CHECK3-NEXT: entry: 443 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 444 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 445 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 446 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 447 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 448 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 449 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 450 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 451 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 452 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 453 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 454 // CHECK3-NEXT: [[J:%.*]] = alloca i32, align 4 455 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 456 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 457 // CHECK3-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 458 // CHECK3-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 459 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 460 // CHECK3-NEXT: store i32 56087, i32* [[DOTOMP_UB]], align 4 461 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 462 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 463 // CHECK3-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 464 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 465 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 466 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 467 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 56087 468 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 469 // CHECK3: cond.true: 470 // CHECK3-NEXT: br label [[COND_END:%.*]] 471 // CHECK3: cond.false: 472 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 473 // CHECK3-NEXT: br label [[COND_END]] 474 // CHECK3: cond.end: 475 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 56087, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 476 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 477 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 478 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 479 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 480 // CHECK3: omp.inner.for.cond: 481 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 482 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 483 // CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] 484 // CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 485 // CHECK3: omp.inner.for.body: 486 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 487 // CHECK3-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP8]], 456 488 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 489 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 490 // CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4 491 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 492 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 493 // CHECK3-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP10]], 456 494 // CHECK3-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 456 495 // CHECK3-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP9]], [[MUL4]] 496 // CHECK3-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1 497 // CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]] 498 // CHECK3-NEXT: store i32 [[ADD6]], i32* [[J]], align 4 499 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP0]], i32 0, i32 0 500 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 501 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A]], i32 0, i32 [[TMP11]] 502 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[J]], align 4 503 // CHECK3-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX]], i32 0, i32 [[TMP12]] 504 // CHECK3-NEXT: store i32 0, i32* [[ARRAYIDX7]], align 4 505 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 506 // CHECK3: omp.body.continue: 507 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 508 // CHECK3: omp.inner.for.inc: 509 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 510 // CHECK3-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP13]], 1 511 // CHECK3-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 512 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] 513 // CHECK3: omp.inner.for.end: 514 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 515 // CHECK3: omp.loop.exit: 516 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) 517 // CHECK3-NEXT: ret void 518 // 519 // 520 // CHECK3-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 521 // CHECK3-SAME: () #[[ATTR3:[0-9]+]] { 522 // CHECK3-NEXT: entry: 523 // CHECK3-NEXT: call void @__tgt_register_requires(i64 1) 524 // CHECK3-NEXT: ret void 525 // 526 // 527 // CHECK4-LABEL: define {{[^@]+}}@_Z21teams_template_structv 528 // CHECK4-SAME: () #[[ATTR0:[0-9]+]] { 529 // CHECK4-NEXT: entry: 530 // CHECK4-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 531 // CHECK4-NEXT: [[CALL:%.*]] = call noundef i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef nonnull align 4 dereferenceable(224352) [[V]]) 532 // CHECK4-NEXT: ret i32 [[CALL]] 533 // 534 // 535 // CHECK4-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv 536 // CHECK4-SAME: (%struct.SS* noundef nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { 537 // CHECK4-NEXT: entry: 538 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 539 // CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 540 // CHECK4-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 541 // CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 542 // CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 543 // CHECK4-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 544 // CHECK4-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 545 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 546 // CHECK4-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 547 // CHECK4-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 548 // CHECK4-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to %struct.SS** 549 // CHECK4-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP1]], align 4 550 // CHECK4-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 551 // CHECK4-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [123 x [456 x i32]]** 552 // CHECK4-NEXT: store [123 x [456 x i32]]* [[A]], [123 x [456 x i32]]** [[TMP3]], align 4 553 // CHECK4-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 554 // CHECK4-NEXT: store i8* null, i8** [[TMP4]], align 4 555 // CHECK4-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 556 // CHECK4-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 557 // CHECK4-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 56088) 558 // CHECK4-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 559 // CHECK4-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 560 // CHECK4-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 561 // CHECK4: omp_offload.failed: 562 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28(%struct.SS* [[THIS1]]) #[[ATTR2:[0-9]+]] 563 // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]] 564 // CHECK4: omp_offload.cont: 565 // CHECK4-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 566 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A3]], i32 0, i32 0 567 // CHECK4-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX]], i32 0, i32 0 568 // CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[ARRAYIDX4]], align 4 569 // CHECK4-NEXT: ret i32 [[TMP9]] 570 // 571 // 572 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28 573 // CHECK4-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { 574 // CHECK4-NEXT: entry: 575 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 576 // CHECK4-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 577 // CHECK4-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 578 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.SS*)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.SS* [[TMP0]]) 579 // CHECK4-NEXT: ret void 580 // 581 // 582 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. 583 // CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { 584 // CHECK4-NEXT: entry: 585 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 586 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 587 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 588 // CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 589 // CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 590 // CHECK4-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 591 // CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 592 // CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 593 // CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 594 // CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 595 // CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 596 // CHECK4-NEXT: [[J:%.*]] = alloca i32, align 4 597 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 598 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 599 // CHECK4-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 600 // CHECK4-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 601 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 602 // CHECK4-NEXT: store i32 56087, i32* [[DOTOMP_UB]], align 4 603 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 604 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 605 // CHECK4-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 606 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 607 // CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 608 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 609 // CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 56087 610 // CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 611 // CHECK4: cond.true: 612 // CHECK4-NEXT: br label [[COND_END:%.*]] 613 // CHECK4: cond.false: 614 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 615 // CHECK4-NEXT: br label [[COND_END]] 616 // CHECK4: cond.end: 617 // CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 56087, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 618 // CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 619 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 620 // CHECK4-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 621 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 622 // CHECK4: omp.inner.for.cond: 623 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 624 // CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 625 // CHECK4-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] 626 // CHECK4-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 627 // CHECK4: omp.inner.for.body: 628 // CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 629 // CHECK4-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP8]], 456 630 // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 631 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 632 // CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4 633 // CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 634 // CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 635 // CHECK4-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP10]], 456 636 // CHECK4-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 456 637 // CHECK4-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP9]], [[MUL4]] 638 // CHECK4-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1 639 // CHECK4-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]] 640 // CHECK4-NEXT: store i32 [[ADD6]], i32* [[J]], align 4 641 // CHECK4-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP0]], i32 0, i32 0 642 // CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 643 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A]], i32 0, i32 [[TMP11]] 644 // CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[J]], align 4 645 // CHECK4-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX]], i32 0, i32 [[TMP12]] 646 // CHECK4-NEXT: store i32 0, i32* [[ARRAYIDX7]], align 4 647 // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 648 // CHECK4: omp.body.continue: 649 // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 650 // CHECK4: omp.inner.for.inc: 651 // CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 652 // CHECK4-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP13]], 1 653 // CHECK4-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 654 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] 655 // CHECK4: omp.inner.for.end: 656 // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 657 // CHECK4: omp.loop.exit: 658 // CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) 659 // CHECK4-NEXT: ret void 660 // 661 // 662 // CHECK4-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 663 // CHECK4-SAME: () #[[ATTR3:[0-9]+]] { 664 // CHECK4-NEXT: entry: 665 // CHECK4-NEXT: call void @__tgt_register_requires(i64 1) 666 // CHECK4-NEXT: ret void 667 // 668 // 669 // CHECK9-LABEL: define {{[^@]+}}@main 670 // CHECK9-SAME: (i32 noundef signext [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { 671 // CHECK9-NEXT: entry: 672 // CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 673 // CHECK9-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 674 // CHECK9-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 675 // CHECK9-NEXT: [[N:%.*]] = alloca i32, align 4 676 // CHECK9-NEXT: [[M:%.*]] = alloca i32, align 4 677 // CHECK9-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 678 // CHECK9-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 679 // CHECK9-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 680 // CHECK9-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 681 // CHECK9-NEXT: [[M_CASTED:%.*]] = alloca i64, align 8 682 // CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8 683 // CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8 684 // CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8 685 // CHECK9-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 8 686 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 687 // CHECK9-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 688 // CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 689 // CHECK9-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4 690 // CHECK9-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i64, align 8 691 // CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 692 // CHECK9-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 693 // CHECK9-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 694 // CHECK9-NEXT: store i32 100, i32* [[N]], align 4 695 // CHECK9-NEXT: store i32 2, i32* [[M]], align 4 696 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 697 // CHECK9-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 698 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[M]], align 4 699 // CHECK9-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 700 // CHECK9-NEXT: [[TMP4:%.*]] = call i8* @llvm.stacksave() 701 // CHECK9-NEXT: store i8* [[TMP4]], i8** [[SAVED_STACK]], align 8 702 // CHECK9-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], [[TMP3]] 703 // CHECK9-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP5]], align 4 704 // CHECK9-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 705 // CHECK9-NEXT: store i64 [[TMP3]], i64* [[__VLA_EXPR1]], align 8 706 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[N]], align 4 707 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_CASTED]] to i32* 708 // CHECK9-NEXT: store i32 [[TMP6]], i32* [[CONV]], align 4 709 // CHECK9-NEXT: [[TMP7:%.*]] = load i64, i64* [[N_CASTED]], align 8 710 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[M]], align 4 711 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[M_CASTED]] to i32* 712 // CHECK9-NEXT: store i32 [[TMP8]], i32* [[CONV1]], align 4 713 // CHECK9-NEXT: [[TMP9:%.*]] = load i64, i64* [[M_CASTED]], align 8 714 // CHECK9-NEXT: [[TMP10:%.*]] = mul nuw i64 [[TMP1]], [[TMP3]] 715 // CHECK9-NEXT: [[TMP11:%.*]] = mul nuw i64 [[TMP10]], 4 716 // CHECK9-NEXT: [[TMP12:%.*]] = bitcast [5 x i64]* [[DOTOFFLOAD_SIZES]] to i8* 717 // CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP12]], i8* align 8 bitcast ([5 x i64]* @.offload_sizes to i8*), i64 40, i1 false) 718 // CHECK9-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 719 // CHECK9-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i64* 720 // CHECK9-NEXT: store i64 [[TMP7]], i64* [[TMP14]], align 8 721 // CHECK9-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 722 // CHECK9-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i64* 723 // CHECK9-NEXT: store i64 [[TMP7]], i64* [[TMP16]], align 8 724 // CHECK9-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 725 // CHECK9-NEXT: store i8* null, i8** [[TMP17]], align 8 726 // CHECK9-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 727 // CHECK9-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64* 728 // CHECK9-NEXT: store i64 [[TMP9]], i64* [[TMP19]], align 8 729 // CHECK9-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 730 // CHECK9-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i64* 731 // CHECK9-NEXT: store i64 [[TMP9]], i64* [[TMP21]], align 8 732 // CHECK9-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 733 // CHECK9-NEXT: store i8* null, i8** [[TMP22]], align 8 734 // CHECK9-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 735 // CHECK9-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i64* 736 // CHECK9-NEXT: store i64 [[TMP1]], i64* [[TMP24]], align 8 737 // CHECK9-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 738 // CHECK9-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i64* 739 // CHECK9-NEXT: store i64 [[TMP1]], i64* [[TMP26]], align 8 740 // CHECK9-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 741 // CHECK9-NEXT: store i8* null, i8** [[TMP27]], align 8 742 // CHECK9-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 743 // CHECK9-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i64* 744 // CHECK9-NEXT: store i64 [[TMP3]], i64* [[TMP29]], align 8 745 // CHECK9-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 746 // CHECK9-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i64* 747 // CHECK9-NEXT: store i64 [[TMP3]], i64* [[TMP31]], align 8 748 // CHECK9-NEXT: [[TMP32:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 749 // CHECK9-NEXT: store i8* null, i8** [[TMP32]], align 8 750 // CHECK9-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 751 // CHECK9-NEXT: [[TMP34:%.*]] = bitcast i8** [[TMP33]] to i32** 752 // CHECK9-NEXT: store i32* [[VLA]], i32** [[TMP34]], align 8 753 // CHECK9-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 754 // CHECK9-NEXT: [[TMP36:%.*]] = bitcast i8** [[TMP35]] to i32** 755 // CHECK9-NEXT: store i32* [[VLA]], i32** [[TMP36]], align 8 756 // CHECK9-NEXT: [[TMP37:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 757 // CHECK9-NEXT: store i64 [[TMP11]], i64* [[TMP37]], align 8 758 // CHECK9-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 759 // CHECK9-NEXT: store i8* null, i8** [[TMP38]], align 8 760 // CHECK9-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 761 // CHECK9-NEXT: [[TMP40:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 762 // CHECK9-NEXT: [[TMP41:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 763 // CHECK9-NEXT: [[TMP42:%.*]] = load i32, i32* [[N]], align 4 764 // CHECK9-NEXT: store i32 [[TMP42]], i32* [[DOTCAPTURE_EXPR_]], align 4 765 // CHECK9-NEXT: [[TMP43:%.*]] = load i32, i32* [[M]], align 4 766 // CHECK9-NEXT: store i32 [[TMP43]], i32* [[DOTCAPTURE_EXPR_3]], align 4 767 // CHECK9-NEXT: [[TMP44:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 768 // CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP44]], 0 769 // CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 770 // CHECK9-NEXT: [[CONV5:%.*]] = sext i32 [[DIV]] to i64 771 // CHECK9-NEXT: [[TMP45:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 772 // CHECK9-NEXT: [[SUB6:%.*]] = sub nsw i32 [[TMP45]], 0 773 // CHECK9-NEXT: [[DIV7:%.*]] = sdiv i32 [[SUB6]], 1 774 // CHECK9-NEXT: [[CONV8:%.*]] = sext i32 [[DIV7]] to i64 775 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV5]], [[CONV8]] 776 // CHECK9-NEXT: [[SUB9:%.*]] = sub nsw i64 [[MUL]], 1 777 // CHECK9-NEXT: store i64 [[SUB9]], i64* [[DOTCAPTURE_EXPR_4]], align 8 778 // CHECK9-NEXT: [[TMP46:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_4]], align 8 779 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP46]], 1 780 // CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 [[ADD]]) 781 // CHECK9-NEXT: [[TMP47:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l80.region_id, i32 5, i8** [[TMP39]], i8** [[TMP40]], i64* [[TMP41]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 782 // CHECK9-NEXT: [[TMP48:%.*]] = icmp ne i32 [[TMP47]], 0 783 // CHECK9-NEXT: br i1 [[TMP48]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 784 // CHECK9: omp_offload.failed: 785 // CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l80(i64 [[TMP7]], i64 [[TMP9]], i64 [[TMP1]], i64 [[TMP3]], i32* [[VLA]]) #[[ATTR3:[0-9]+]] 786 // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] 787 // CHECK9: omp_offload.cont: 788 // CHECK9-NEXT: [[TMP49:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 789 // CHECK9-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef signext [[TMP49]]) 790 // CHECK9-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 791 // CHECK9-NEXT: [[TMP50:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 792 // CHECK9-NEXT: call void @llvm.stackrestore(i8* [[TMP50]]) 793 // CHECK9-NEXT: [[TMP51:%.*]] = load i32, i32* [[RETVAL]], align 4 794 // CHECK9-NEXT: ret i32 [[TMP51]] 795 // 796 // 797 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l80 798 // CHECK9-SAME: (i64 noundef [[N:%.*]], i64 noundef [[M:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { 799 // CHECK9-NEXT: entry: 800 // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 801 // CHECK9-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 802 // CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 803 // CHECK9-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 804 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 805 // CHECK9-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 806 // CHECK9-NEXT: [[M_CASTED:%.*]] = alloca i64, align 8 807 // CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 808 // CHECK9-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8 809 // CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 810 // CHECK9-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 811 // CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 812 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* 813 // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[M_ADDR]] to i32* 814 // CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 815 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 816 // CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 817 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4 818 // CHECK9-NEXT: [[CONV4:%.*]] = bitcast i64* [[N_CASTED]] to i32* 819 // CHECK9-NEXT: store i32 [[TMP3]], i32* [[CONV4]], align 4 820 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8 821 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV3]], align 4 822 // CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[M_CASTED]] to i32* 823 // CHECK9-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4 824 // CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[M_CASTED]], align 8 825 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP0]], i64 [[TMP1]], i32* [[TMP2]]) 826 // CHECK9-NEXT: ret void 827 // 828 // 829 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. 830 // CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[M:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { 831 // CHECK9-NEXT: entry: 832 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 833 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 834 // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 835 // CHECK9-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 836 // CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 837 // CHECK9-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 838 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 839 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 840 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 841 // CHECK9-NEXT: [[_TMP4:%.*]] = alloca i32, align 4 842 // CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 843 // CHECK9-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i32, align 4 844 // CHECK9-NEXT: [[DOTCAPTURE_EXPR_6:%.*]] = alloca i64, align 8 845 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 846 // CHECK9-NEXT: [[J:%.*]] = alloca i32, align 4 847 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 848 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 849 // CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 850 // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 851 // CHECK9-NEXT: [[I13:%.*]] = alloca i32, align 4 852 // CHECK9-NEXT: [[J14:%.*]] = alloca i32, align 4 853 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 854 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 855 // CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 856 // CHECK9-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8 857 // CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 858 // CHECK9-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 859 // CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 860 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* 861 // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[M_ADDR]] to i32* 862 // CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 863 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 864 // CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 865 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4 866 // CHECK9-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 867 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV3]], align 4 868 // CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_5]], align 4 869 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 870 // CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 871 // CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 872 // CHECK9-NEXT: [[CONV7:%.*]] = sext i32 [[DIV]] to i64 873 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 874 // CHECK9-NEXT: [[SUB8:%.*]] = sub nsw i32 [[TMP6]], 0 875 // CHECK9-NEXT: [[DIV9:%.*]] = sdiv i32 [[SUB8]], 1 876 // CHECK9-NEXT: [[CONV10:%.*]] = sext i32 [[DIV9]] to i64 877 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV7]], [[CONV10]] 878 // CHECK9-NEXT: [[SUB11:%.*]] = sub nsw i64 [[MUL]], 1 879 // CHECK9-NEXT: store i64 [[SUB11]], i64* [[DOTCAPTURE_EXPR_6]], align 8 880 // CHECK9-NEXT: store i32 0, i32* [[I]], align 4 881 // CHECK9-NEXT: store i32 0, i32* [[J]], align 4 882 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 883 // CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP7]] 884 // CHECK9-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]] 885 // CHECK9: land.lhs.true: 886 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 887 // CHECK9-NEXT: [[CMP12:%.*]] = icmp slt i32 0, [[TMP8]] 888 // CHECK9-NEXT: br i1 [[CMP12]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]] 889 // CHECK9: omp.precond.then: 890 // CHECK9-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 891 // CHECK9-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_6]], align 8 892 // CHECK9-NEXT: store i64 [[TMP9]], i64* [[DOTOMP_UB]], align 8 893 // CHECK9-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 894 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 895 // CHECK9-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 896 // CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 897 // CHECK9-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP11]], i32 92, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 898 // CHECK9-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 899 // CHECK9-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_6]], align 8 900 // CHECK9-NEXT: [[CMP15:%.*]] = icmp sgt i64 [[TMP12]], [[TMP13]] 901 // CHECK9-NEXT: br i1 [[CMP15]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 902 // CHECK9: cond.true: 903 // CHECK9-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_6]], align 8 904 // CHECK9-NEXT: br label [[COND_END:%.*]] 905 // CHECK9: cond.false: 906 // CHECK9-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 907 // CHECK9-NEXT: br label [[COND_END]] 908 // CHECK9: cond.end: 909 // CHECK9-NEXT: [[COND:%.*]] = phi i64 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] 910 // CHECK9-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 911 // CHECK9-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 912 // CHECK9-NEXT: store i64 [[TMP16]], i64* [[DOTOMP_IV]], align 8 913 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 914 // CHECK9: omp.inner.for.cond: 915 // CHECK9-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 916 // CHECK9-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 917 // CHECK9-NEXT: [[CMP16:%.*]] = icmp sle i64 [[TMP17]], [[TMP18]] 918 // CHECK9-NEXT: br i1 [[CMP16]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 919 // CHECK9: omp.inner.for.body: 920 // CHECK9-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 921 // CHECK9-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 922 // CHECK9-NEXT: [[SUB17:%.*]] = sub nsw i32 [[TMP20]], 0 923 // CHECK9-NEXT: [[DIV18:%.*]] = sdiv i32 [[SUB17]], 1 924 // CHECK9-NEXT: [[MUL19:%.*]] = mul nsw i32 1, [[DIV18]] 925 // CHECK9-NEXT: [[CONV20:%.*]] = sext i32 [[MUL19]] to i64 926 // CHECK9-NEXT: [[DIV21:%.*]] = sdiv i64 [[TMP19]], [[CONV20]] 927 // CHECK9-NEXT: [[MUL22:%.*]] = mul nsw i64 [[DIV21]], 1 928 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i64 0, [[MUL22]] 929 // CHECK9-NEXT: [[CONV23:%.*]] = trunc i64 [[ADD]] to i32 930 // CHECK9-NEXT: store i32 [[CONV23]], i32* [[I13]], align 4 931 // CHECK9-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 932 // CHECK9-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 933 // CHECK9-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 934 // CHECK9-NEXT: [[SUB24:%.*]] = sub nsw i32 [[TMP23]], 0 935 // CHECK9-NEXT: [[DIV25:%.*]] = sdiv i32 [[SUB24]], 1 936 // CHECK9-NEXT: [[MUL26:%.*]] = mul nsw i32 1, [[DIV25]] 937 // CHECK9-NEXT: [[CONV27:%.*]] = sext i32 [[MUL26]] to i64 938 // CHECK9-NEXT: [[DIV28:%.*]] = sdiv i64 [[TMP22]], [[CONV27]] 939 // CHECK9-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 940 // CHECK9-NEXT: [[SUB29:%.*]] = sub nsw i32 [[TMP24]], 0 941 // CHECK9-NEXT: [[DIV30:%.*]] = sdiv i32 [[SUB29]], 1 942 // CHECK9-NEXT: [[MUL31:%.*]] = mul nsw i32 1, [[DIV30]] 943 // CHECK9-NEXT: [[CONV32:%.*]] = sext i32 [[MUL31]] to i64 944 // CHECK9-NEXT: [[MUL33:%.*]] = mul nsw i64 [[DIV28]], [[CONV32]] 945 // CHECK9-NEXT: [[SUB34:%.*]] = sub nsw i64 [[TMP21]], [[MUL33]] 946 // CHECK9-NEXT: [[MUL35:%.*]] = mul nsw i64 [[SUB34]], 1 947 // CHECK9-NEXT: [[ADD36:%.*]] = add nsw i64 0, [[MUL35]] 948 // CHECK9-NEXT: [[CONV37:%.*]] = trunc i64 [[ADD36]] to i32 949 // CHECK9-NEXT: store i32 [[CONV37]], i32* [[J14]], align 4 950 // CHECK9-NEXT: [[TMP25:%.*]] = load i32, i32* [[I13]], align 4 951 // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP25]] to i64 952 // CHECK9-NEXT: [[TMP26:%.*]] = mul nsw i64 [[IDXPROM]], [[TMP1]] 953 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i64 [[TMP26]] 954 // CHECK9-NEXT: [[TMP27:%.*]] = load i32, i32* [[J14]], align 4 955 // CHECK9-NEXT: [[IDXPROM38:%.*]] = sext i32 [[TMP27]] to i64 956 // CHECK9-NEXT: [[ARRAYIDX39:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX]], i64 [[IDXPROM38]] 957 // CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX39]], align 4 958 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 959 // CHECK9: omp.body.continue: 960 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 961 // CHECK9: omp.inner.for.inc: 962 // CHECK9-NEXT: [[TMP28:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 963 // CHECK9-NEXT: [[ADD40:%.*]] = add nsw i64 [[TMP28]], 1 964 // CHECK9-NEXT: store i64 [[ADD40]], i64* [[DOTOMP_IV]], align 8 965 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] 966 // CHECK9: omp.inner.for.end: 967 // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 968 // CHECK9: omp.loop.exit: 969 // CHECK9-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 970 // CHECK9-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4 971 // CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP30]]) 972 // CHECK9-NEXT: br label [[OMP_PRECOND_END]] 973 // CHECK9: omp.precond.end: 974 // CHECK9-NEXT: ret void 975 // 976 // 977 // CHECK9-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ 978 // CHECK9-SAME: (i32 noundef signext [[ARGC:%.*]]) #[[ATTR5:[0-9]+]] comdat { 979 // CHECK9-NEXT: entry: 980 // CHECK9-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 981 // CHECK9-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 982 // CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 983 // CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 984 // CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 985 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 986 // CHECK9-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 987 // CHECK9-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 988 // CHECK9-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 989 // CHECK9-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to [10 x [2 x i32]]** 990 // CHECK9-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[TMP1]], align 8 991 // CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 992 // CHECK9-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [10 x [2 x i32]]** 993 // CHECK9-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[TMP3]], align 8 994 // CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 995 // CHECK9-NEXT: store i8* null, i8** [[TMP4]], align 8 996 // CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 997 // CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 998 // CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 20) 999 // CHECK9-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l67.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 1000 // CHECK9-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 1001 // CHECK9-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1002 // CHECK9: omp_offload.failed: 1003 // CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l67([10 x [2 x i32]]* [[A]]) #[[ATTR3]] 1004 // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] 1005 // CHECK9: omp_offload.cont: 1006 // CHECK9-NEXT: ret i32 0 1007 // 1008 // 1009 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l67 1010 // CHECK9-SAME: ([10 x [2 x i32]]* noundef nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { 1011 // CHECK9-NEXT: entry: 1012 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 8 1013 // CHECK9-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 8 1014 // CHECK9-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 8 1015 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x [2 x i32]]*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), [10 x [2 x i32]]* [[TMP0]]) 1016 // CHECK9-NEXT: ret void 1017 // 1018 // 1019 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 1020 // CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x [2 x i32]]* noundef nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { 1021 // CHECK9-NEXT: entry: 1022 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1023 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1024 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 8 1025 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1026 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 1027 // CHECK9-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 1028 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1029 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1030 // CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1031 // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1032 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 1033 // CHECK9-NEXT: [[J:%.*]] = alloca i32, align 4 1034 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1035 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1036 // CHECK9-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 8 1037 // CHECK9-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 8 1038 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1039 // CHECK9-NEXT: store i32 19, i32* [[DOTOMP_UB]], align 4 1040 // CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 1041 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1042 // CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 1043 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 1044 // CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 1045 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1046 // CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 19 1047 // CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1048 // CHECK9: cond.true: 1049 // CHECK9-NEXT: br label [[COND_END:%.*]] 1050 // CHECK9: cond.false: 1051 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1052 // CHECK9-NEXT: br label [[COND_END]] 1053 // CHECK9: cond.end: 1054 // CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 19, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 1055 // CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 1056 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1057 // CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 1058 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1059 // CHECK9: omp.inner.for.cond: 1060 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1061 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1062 // CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] 1063 // CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1064 // CHECK9: omp.inner.for.body: 1065 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1066 // CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP8]], 2 1067 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 1068 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1069 // CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 1070 // CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1071 // CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1072 // CHECK9-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP10]], 2 1073 // CHECK9-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 2 1074 // CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP9]], [[MUL4]] 1075 // CHECK9-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1 1076 // CHECK9-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]] 1077 // CHECK9-NEXT: store i32 [[ADD6]], i32* [[J]], align 4 1078 // CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 1079 // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 1080 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]]* [[TMP0]], i64 0, i64 [[IDXPROM]] 1081 // CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[J]], align 4 1082 // CHECK9-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP12]] to i64 1083 // CHECK9-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[ARRAYIDX]], i64 0, i64 [[IDXPROM7]] 1084 // CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX8]], align 4 1085 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1086 // CHECK9: omp.body.continue: 1087 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1088 // CHECK9: omp.inner.for.inc: 1089 // CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1090 // CHECK9-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP13]], 1 1091 // CHECK9-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 1092 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] 1093 // CHECK9: omp.inner.for.end: 1094 // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1095 // CHECK9: omp.loop.exit: 1096 // CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) 1097 // CHECK9-NEXT: ret void 1098 // 1099 // 1100 // CHECK9-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 1101 // CHECK9-SAME: () #[[ATTR6:[0-9]+]] { 1102 // CHECK9-NEXT: entry: 1103 // CHECK9-NEXT: call void @__tgt_register_requires(i64 1) 1104 // CHECK9-NEXT: ret void 1105 // 1106 // 1107 // CHECK10-LABEL: define {{[^@]+}}@main 1108 // CHECK10-SAME: (i32 noundef signext [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { 1109 // CHECK10-NEXT: entry: 1110 // CHECK10-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1111 // CHECK10-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 1112 // CHECK10-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 1113 // CHECK10-NEXT: [[N:%.*]] = alloca i32, align 4 1114 // CHECK10-NEXT: [[M:%.*]] = alloca i32, align 4 1115 // CHECK10-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 1116 // CHECK10-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 1117 // CHECK10-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 1118 // CHECK10-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 1119 // CHECK10-NEXT: [[M_CASTED:%.*]] = alloca i64, align 8 1120 // CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8 1121 // CHECK10-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8 1122 // CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8 1123 // CHECK10-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 8 1124 // CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 1125 // CHECK10-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 1126 // CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 1127 // CHECK10-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4 1128 // CHECK10-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i64, align 8 1129 // CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4 1130 // CHECK10-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 1131 // CHECK10-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 1132 // CHECK10-NEXT: store i32 100, i32* [[N]], align 4 1133 // CHECK10-NEXT: store i32 2, i32* [[M]], align 4 1134 // CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 1135 // CHECK10-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 1136 // CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[M]], align 4 1137 // CHECK10-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 1138 // CHECK10-NEXT: [[TMP4:%.*]] = call i8* @llvm.stacksave() 1139 // CHECK10-NEXT: store i8* [[TMP4]], i8** [[SAVED_STACK]], align 8 1140 // CHECK10-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], [[TMP3]] 1141 // CHECK10-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP5]], align 4 1142 // CHECK10-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 1143 // CHECK10-NEXT: store i64 [[TMP3]], i64* [[__VLA_EXPR1]], align 8 1144 // CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[N]], align 4 1145 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_CASTED]] to i32* 1146 // CHECK10-NEXT: store i32 [[TMP6]], i32* [[CONV]], align 4 1147 // CHECK10-NEXT: [[TMP7:%.*]] = load i64, i64* [[N_CASTED]], align 8 1148 // CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[M]], align 4 1149 // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[M_CASTED]] to i32* 1150 // CHECK10-NEXT: store i32 [[TMP8]], i32* [[CONV1]], align 4 1151 // CHECK10-NEXT: [[TMP9:%.*]] = load i64, i64* [[M_CASTED]], align 8 1152 // CHECK10-NEXT: [[TMP10:%.*]] = mul nuw i64 [[TMP1]], [[TMP3]] 1153 // CHECK10-NEXT: [[TMP11:%.*]] = mul nuw i64 [[TMP10]], 4 1154 // CHECK10-NEXT: [[TMP12:%.*]] = bitcast [5 x i64]* [[DOTOFFLOAD_SIZES]] to i8* 1155 // CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP12]], i8* align 8 bitcast ([5 x i64]* @.offload_sizes to i8*), i64 40, i1 false) 1156 // CHECK10-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1157 // CHECK10-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i64* 1158 // CHECK10-NEXT: store i64 [[TMP7]], i64* [[TMP14]], align 8 1159 // CHECK10-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1160 // CHECK10-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i64* 1161 // CHECK10-NEXT: store i64 [[TMP7]], i64* [[TMP16]], align 8 1162 // CHECK10-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 1163 // CHECK10-NEXT: store i8* null, i8** [[TMP17]], align 8 1164 // CHECK10-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1165 // CHECK10-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64* 1166 // CHECK10-NEXT: store i64 [[TMP9]], i64* [[TMP19]], align 8 1167 // CHECK10-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1168 // CHECK10-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i64* 1169 // CHECK10-NEXT: store i64 [[TMP9]], i64* [[TMP21]], align 8 1170 // CHECK10-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 1171 // CHECK10-NEXT: store i8* null, i8** [[TMP22]], align 8 1172 // CHECK10-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1173 // CHECK10-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i64* 1174 // CHECK10-NEXT: store i64 [[TMP1]], i64* [[TMP24]], align 8 1175 // CHECK10-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1176 // CHECK10-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i64* 1177 // CHECK10-NEXT: store i64 [[TMP1]], i64* [[TMP26]], align 8 1178 // CHECK10-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 1179 // CHECK10-NEXT: store i8* null, i8** [[TMP27]], align 8 1180 // CHECK10-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 1181 // CHECK10-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i64* 1182 // CHECK10-NEXT: store i64 [[TMP3]], i64* [[TMP29]], align 8 1183 // CHECK10-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 1184 // CHECK10-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i64* 1185 // CHECK10-NEXT: store i64 [[TMP3]], i64* [[TMP31]], align 8 1186 // CHECK10-NEXT: [[TMP32:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 1187 // CHECK10-NEXT: store i8* null, i8** [[TMP32]], align 8 1188 // CHECK10-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 1189 // CHECK10-NEXT: [[TMP34:%.*]] = bitcast i8** [[TMP33]] to i32** 1190 // CHECK10-NEXT: store i32* [[VLA]], i32** [[TMP34]], align 8 1191 // CHECK10-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 1192 // CHECK10-NEXT: [[TMP36:%.*]] = bitcast i8** [[TMP35]] to i32** 1193 // CHECK10-NEXT: store i32* [[VLA]], i32** [[TMP36]], align 8 1194 // CHECK10-NEXT: [[TMP37:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 1195 // CHECK10-NEXT: store i64 [[TMP11]], i64* [[TMP37]], align 8 1196 // CHECK10-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 1197 // CHECK10-NEXT: store i8* null, i8** [[TMP38]], align 8 1198 // CHECK10-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1199 // CHECK10-NEXT: [[TMP40:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1200 // CHECK10-NEXT: [[TMP41:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 1201 // CHECK10-NEXT: [[TMP42:%.*]] = load i32, i32* [[N]], align 4 1202 // CHECK10-NEXT: store i32 [[TMP42]], i32* [[DOTCAPTURE_EXPR_]], align 4 1203 // CHECK10-NEXT: [[TMP43:%.*]] = load i32, i32* [[M]], align 4 1204 // CHECK10-NEXT: store i32 [[TMP43]], i32* [[DOTCAPTURE_EXPR_3]], align 4 1205 // CHECK10-NEXT: [[TMP44:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 1206 // CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP44]], 0 1207 // CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 1208 // CHECK10-NEXT: [[CONV5:%.*]] = sext i32 [[DIV]] to i64 1209 // CHECK10-NEXT: [[TMP45:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 1210 // CHECK10-NEXT: [[SUB6:%.*]] = sub nsw i32 [[TMP45]], 0 1211 // CHECK10-NEXT: [[DIV7:%.*]] = sdiv i32 [[SUB6]], 1 1212 // CHECK10-NEXT: [[CONV8:%.*]] = sext i32 [[DIV7]] to i64 1213 // CHECK10-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV5]], [[CONV8]] 1214 // CHECK10-NEXT: [[SUB9:%.*]] = sub nsw i64 [[MUL]], 1 1215 // CHECK10-NEXT: store i64 [[SUB9]], i64* [[DOTCAPTURE_EXPR_4]], align 8 1216 // CHECK10-NEXT: [[TMP46:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_4]], align 8 1217 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP46]], 1 1218 // CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 [[ADD]]) 1219 // CHECK10-NEXT: [[TMP47:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l80.region_id, i32 5, i8** [[TMP39]], i8** [[TMP40]], i64* [[TMP41]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 1220 // CHECK10-NEXT: [[TMP48:%.*]] = icmp ne i32 [[TMP47]], 0 1221 // CHECK10-NEXT: br i1 [[TMP48]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1222 // CHECK10: omp_offload.failed: 1223 // CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l80(i64 [[TMP7]], i64 [[TMP9]], i64 [[TMP1]], i64 [[TMP3]], i32* [[VLA]]) #[[ATTR3:[0-9]+]] 1224 // CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]] 1225 // CHECK10: omp_offload.cont: 1226 // CHECK10-NEXT: [[TMP49:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 1227 // CHECK10-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef signext [[TMP49]]) 1228 // CHECK10-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 1229 // CHECK10-NEXT: [[TMP50:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 1230 // CHECK10-NEXT: call void @llvm.stackrestore(i8* [[TMP50]]) 1231 // CHECK10-NEXT: [[TMP51:%.*]] = load i32, i32* [[RETVAL]], align 4 1232 // CHECK10-NEXT: ret i32 [[TMP51]] 1233 // 1234 // 1235 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l80 1236 // CHECK10-SAME: (i64 noundef [[N:%.*]], i64 noundef [[M:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { 1237 // CHECK10-NEXT: entry: 1238 // CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 1239 // CHECK10-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 1240 // CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 1241 // CHECK10-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 1242 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 1243 // CHECK10-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 1244 // CHECK10-NEXT: [[M_CASTED:%.*]] = alloca i64, align 8 1245 // CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 1246 // CHECK10-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8 1247 // CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 1248 // CHECK10-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 1249 // CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 1250 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* 1251 // CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[M_ADDR]] to i32* 1252 // CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 1253 // CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 1254 // CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 1255 // CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4 1256 // CHECK10-NEXT: [[CONV4:%.*]] = bitcast i64* [[N_CASTED]] to i32* 1257 // CHECK10-NEXT: store i32 [[TMP3]], i32* [[CONV4]], align 4 1258 // CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8 1259 // CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV3]], align 4 1260 // CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[M_CASTED]] to i32* 1261 // CHECK10-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4 1262 // CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[M_CASTED]], align 8 1263 // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP0]], i64 [[TMP1]], i32* [[TMP2]]) 1264 // CHECK10-NEXT: ret void 1265 // 1266 // 1267 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. 1268 // CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[M:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { 1269 // CHECK10-NEXT: entry: 1270 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1271 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1272 // CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 1273 // CHECK10-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 1274 // CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 1275 // CHECK10-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 1276 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 1277 // CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 1278 // CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 1279 // CHECK10-NEXT: [[_TMP4:%.*]] = alloca i32, align 4 1280 // CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 1281 // CHECK10-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i32, align 4 1282 // CHECK10-NEXT: [[DOTCAPTURE_EXPR_6:%.*]] = alloca i64, align 8 1283 // CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 1284 // CHECK10-NEXT: [[J:%.*]] = alloca i32, align 4 1285 // CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 1286 // CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 1287 // CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 1288 // CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1289 // CHECK10-NEXT: [[I13:%.*]] = alloca i32, align 4 1290 // CHECK10-NEXT: [[J14:%.*]] = alloca i32, align 4 1291 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1292 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1293 // CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 1294 // CHECK10-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8 1295 // CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 1296 // CHECK10-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 1297 // CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 1298 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* 1299 // CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[M_ADDR]] to i32* 1300 // CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 1301 // CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 1302 // CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 1303 // CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4 1304 // CHECK10-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 1305 // CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV3]], align 4 1306 // CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_5]], align 4 1307 // CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 1308 // CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 1309 // CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 1310 // CHECK10-NEXT: [[CONV7:%.*]] = sext i32 [[DIV]] to i64 1311 // CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 1312 // CHECK10-NEXT: [[SUB8:%.*]] = sub nsw i32 [[TMP6]], 0 1313 // CHECK10-NEXT: [[DIV9:%.*]] = sdiv i32 [[SUB8]], 1 1314 // CHECK10-NEXT: [[CONV10:%.*]] = sext i32 [[DIV9]] to i64 1315 // CHECK10-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV7]], [[CONV10]] 1316 // CHECK10-NEXT: [[SUB11:%.*]] = sub nsw i64 [[MUL]], 1 1317 // CHECK10-NEXT: store i64 [[SUB11]], i64* [[DOTCAPTURE_EXPR_6]], align 8 1318 // CHECK10-NEXT: store i32 0, i32* [[I]], align 4 1319 // CHECK10-NEXT: store i32 0, i32* [[J]], align 4 1320 // CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 1321 // CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP7]] 1322 // CHECK10-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]] 1323 // CHECK10: land.lhs.true: 1324 // CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 1325 // CHECK10-NEXT: [[CMP12:%.*]] = icmp slt i32 0, [[TMP8]] 1326 // CHECK10-NEXT: br i1 [[CMP12]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]] 1327 // CHECK10: omp.precond.then: 1328 // CHECK10-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 1329 // CHECK10-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_6]], align 8 1330 // CHECK10-NEXT: store i64 [[TMP9]], i64* [[DOTOMP_UB]], align 8 1331 // CHECK10-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 1332 // CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1333 // CHECK10-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 1334 // CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 1335 // CHECK10-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP11]], i32 92, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 1336 // CHECK10-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 1337 // CHECK10-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_6]], align 8 1338 // CHECK10-NEXT: [[CMP15:%.*]] = icmp sgt i64 [[TMP12]], [[TMP13]] 1339 // CHECK10-NEXT: br i1 [[CMP15]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1340 // CHECK10: cond.true: 1341 // CHECK10-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_6]], align 8 1342 // CHECK10-NEXT: br label [[COND_END:%.*]] 1343 // CHECK10: cond.false: 1344 // CHECK10-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 1345 // CHECK10-NEXT: br label [[COND_END]] 1346 // CHECK10: cond.end: 1347 // CHECK10-NEXT: [[COND:%.*]] = phi i64 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] 1348 // CHECK10-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 1349 // CHECK10-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 1350 // CHECK10-NEXT: store i64 [[TMP16]], i64* [[DOTOMP_IV]], align 8 1351 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1352 // CHECK10: omp.inner.for.cond: 1353 // CHECK10-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 1354 // CHECK10-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 1355 // CHECK10-NEXT: [[CMP16:%.*]] = icmp sle i64 [[TMP17]], [[TMP18]] 1356 // CHECK10-NEXT: br i1 [[CMP16]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1357 // CHECK10: omp.inner.for.body: 1358 // CHECK10-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 1359 // CHECK10-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 1360 // CHECK10-NEXT: [[SUB17:%.*]] = sub nsw i32 [[TMP20]], 0 1361 // CHECK10-NEXT: [[DIV18:%.*]] = sdiv i32 [[SUB17]], 1 1362 // CHECK10-NEXT: [[MUL19:%.*]] = mul nsw i32 1, [[DIV18]] 1363 // CHECK10-NEXT: [[CONV20:%.*]] = sext i32 [[MUL19]] to i64 1364 // CHECK10-NEXT: [[DIV21:%.*]] = sdiv i64 [[TMP19]], [[CONV20]] 1365 // CHECK10-NEXT: [[MUL22:%.*]] = mul nsw i64 [[DIV21]], 1 1366 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i64 0, [[MUL22]] 1367 // CHECK10-NEXT: [[CONV23:%.*]] = trunc i64 [[ADD]] to i32 1368 // CHECK10-NEXT: store i32 [[CONV23]], i32* [[I13]], align 4 1369 // CHECK10-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 1370 // CHECK10-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 1371 // CHECK10-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 1372 // CHECK10-NEXT: [[SUB24:%.*]] = sub nsw i32 [[TMP23]], 0 1373 // CHECK10-NEXT: [[DIV25:%.*]] = sdiv i32 [[SUB24]], 1 1374 // CHECK10-NEXT: [[MUL26:%.*]] = mul nsw i32 1, [[DIV25]] 1375 // CHECK10-NEXT: [[CONV27:%.*]] = sext i32 [[MUL26]] to i64 1376 // CHECK10-NEXT: [[DIV28:%.*]] = sdiv i64 [[TMP22]], [[CONV27]] 1377 // CHECK10-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 1378 // CHECK10-NEXT: [[SUB29:%.*]] = sub nsw i32 [[TMP24]], 0 1379 // CHECK10-NEXT: [[DIV30:%.*]] = sdiv i32 [[SUB29]], 1 1380 // CHECK10-NEXT: [[MUL31:%.*]] = mul nsw i32 1, [[DIV30]] 1381 // CHECK10-NEXT: [[CONV32:%.*]] = sext i32 [[MUL31]] to i64 1382 // CHECK10-NEXT: [[MUL33:%.*]] = mul nsw i64 [[DIV28]], [[CONV32]] 1383 // CHECK10-NEXT: [[SUB34:%.*]] = sub nsw i64 [[TMP21]], [[MUL33]] 1384 // CHECK10-NEXT: [[MUL35:%.*]] = mul nsw i64 [[SUB34]], 1 1385 // CHECK10-NEXT: [[ADD36:%.*]] = add nsw i64 0, [[MUL35]] 1386 // CHECK10-NEXT: [[CONV37:%.*]] = trunc i64 [[ADD36]] to i32 1387 // CHECK10-NEXT: store i32 [[CONV37]], i32* [[J14]], align 4 1388 // CHECK10-NEXT: [[TMP25:%.*]] = load i32, i32* [[I13]], align 4 1389 // CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP25]] to i64 1390 // CHECK10-NEXT: [[TMP26:%.*]] = mul nsw i64 [[IDXPROM]], [[TMP1]] 1391 // CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i64 [[TMP26]] 1392 // CHECK10-NEXT: [[TMP27:%.*]] = load i32, i32* [[J14]], align 4 1393 // CHECK10-NEXT: [[IDXPROM38:%.*]] = sext i32 [[TMP27]] to i64 1394 // CHECK10-NEXT: [[ARRAYIDX39:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX]], i64 [[IDXPROM38]] 1395 // CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX39]], align 4 1396 // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1397 // CHECK10: omp.body.continue: 1398 // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1399 // CHECK10: omp.inner.for.inc: 1400 // CHECK10-NEXT: [[TMP28:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 1401 // CHECK10-NEXT: [[ADD40:%.*]] = add nsw i64 [[TMP28]], 1 1402 // CHECK10-NEXT: store i64 [[ADD40]], i64* [[DOTOMP_IV]], align 8 1403 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] 1404 // CHECK10: omp.inner.for.end: 1405 // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1406 // CHECK10: omp.loop.exit: 1407 // CHECK10-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 1408 // CHECK10-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4 1409 // CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP30]]) 1410 // CHECK10-NEXT: br label [[OMP_PRECOND_END]] 1411 // CHECK10: omp.precond.end: 1412 // CHECK10-NEXT: ret void 1413 // 1414 // 1415 // CHECK10-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ 1416 // CHECK10-SAME: (i32 noundef signext [[ARGC:%.*]]) #[[ATTR5:[0-9]+]] comdat { 1417 // CHECK10-NEXT: entry: 1418 // CHECK10-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 1419 // CHECK10-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 1420 // CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 1421 // CHECK10-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 1422 // CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 1423 // CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 1424 // CHECK10-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 1425 // CHECK10-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 1426 // CHECK10-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1427 // CHECK10-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to [10 x [2 x i32]]** 1428 // CHECK10-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[TMP1]], align 8 1429 // CHECK10-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1430 // CHECK10-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [10 x [2 x i32]]** 1431 // CHECK10-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[TMP3]], align 8 1432 // CHECK10-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 1433 // CHECK10-NEXT: store i8* null, i8** [[TMP4]], align 8 1434 // CHECK10-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1435 // CHECK10-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1436 // CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 20) 1437 // CHECK10-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l67.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 1438 // CHECK10-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 1439 // CHECK10-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1440 // CHECK10: omp_offload.failed: 1441 // CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l67([10 x [2 x i32]]* [[A]]) #[[ATTR3]] 1442 // CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]] 1443 // CHECK10: omp_offload.cont: 1444 // CHECK10-NEXT: ret i32 0 1445 // 1446 // 1447 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l67 1448 // CHECK10-SAME: ([10 x [2 x i32]]* noundef nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { 1449 // CHECK10-NEXT: entry: 1450 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 8 1451 // CHECK10-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 8 1452 // CHECK10-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 8 1453 // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x [2 x i32]]*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), [10 x [2 x i32]]* [[TMP0]]) 1454 // CHECK10-NEXT: ret void 1455 // 1456 // 1457 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 1458 // CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x [2 x i32]]* noundef nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { 1459 // CHECK10-NEXT: entry: 1460 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1461 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1462 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 8 1463 // CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1464 // CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 1465 // CHECK10-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 1466 // CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1467 // CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1468 // CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1469 // CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1470 // CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 1471 // CHECK10-NEXT: [[J:%.*]] = alloca i32, align 4 1472 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1473 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1474 // CHECK10-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 8 1475 // CHECK10-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 8 1476 // CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1477 // CHECK10-NEXT: store i32 19, i32* [[DOTOMP_UB]], align 4 1478 // CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 1479 // CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1480 // CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 1481 // CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 1482 // CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 1483 // CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1484 // CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 19 1485 // CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1486 // CHECK10: cond.true: 1487 // CHECK10-NEXT: br label [[COND_END:%.*]] 1488 // CHECK10: cond.false: 1489 // CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1490 // CHECK10-NEXT: br label [[COND_END]] 1491 // CHECK10: cond.end: 1492 // CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 19, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 1493 // CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 1494 // CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1495 // CHECK10-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 1496 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1497 // CHECK10: omp.inner.for.cond: 1498 // CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1499 // CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1500 // CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] 1501 // CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1502 // CHECK10: omp.inner.for.body: 1503 // CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1504 // CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP8]], 2 1505 // CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 1506 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1507 // CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 1508 // CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1509 // CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1510 // CHECK10-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP10]], 2 1511 // CHECK10-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 2 1512 // CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP9]], [[MUL4]] 1513 // CHECK10-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1 1514 // CHECK10-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]] 1515 // CHECK10-NEXT: store i32 [[ADD6]], i32* [[J]], align 4 1516 // CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 1517 // CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 1518 // CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]]* [[TMP0]], i64 0, i64 [[IDXPROM]] 1519 // CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[J]], align 4 1520 // CHECK10-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP12]] to i64 1521 // CHECK10-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[ARRAYIDX]], i64 0, i64 [[IDXPROM7]] 1522 // CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX8]], align 4 1523 // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1524 // CHECK10: omp.body.continue: 1525 // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1526 // CHECK10: omp.inner.for.inc: 1527 // CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1528 // CHECK10-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP13]], 1 1529 // CHECK10-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 1530 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] 1531 // CHECK10: omp.inner.for.end: 1532 // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1533 // CHECK10: omp.loop.exit: 1534 // CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) 1535 // CHECK10-NEXT: ret void 1536 // 1537 // 1538 // CHECK10-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 1539 // CHECK10-SAME: () #[[ATTR6:[0-9]+]] { 1540 // CHECK10-NEXT: entry: 1541 // CHECK10-NEXT: call void @__tgt_register_requires(i64 1) 1542 // CHECK10-NEXT: ret void 1543 // 1544 // 1545 // CHECK11-LABEL: define {{[^@]+}}@main 1546 // CHECK11-SAME: (i32 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { 1547 // CHECK11-NEXT: entry: 1548 // CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1549 // CHECK11-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 1550 // CHECK11-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 4 1551 // CHECK11-NEXT: [[N:%.*]] = alloca i32, align 4 1552 // CHECK11-NEXT: [[M:%.*]] = alloca i32, align 4 1553 // CHECK11-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 1554 // CHECK11-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 1555 // CHECK11-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 1556 // CHECK11-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 1557 // CHECK11-NEXT: [[M_CASTED:%.*]] = alloca i32, align 4 1558 // CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4 1559 // CHECK11-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4 1560 // CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4 1561 // CHECK11-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 4 1562 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 1563 // CHECK11-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 1564 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 1565 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 1566 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i64, align 8 1567 // CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4 1568 // CHECK11-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 1569 // CHECK11-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 4 1570 // CHECK11-NEXT: store i32 100, i32* [[N]], align 4 1571 // CHECK11-NEXT: store i32 2, i32* [[M]], align 4 1572 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 1573 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[M]], align 4 1574 // CHECK11-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() 1575 // CHECK11-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 1576 // CHECK11-NEXT: [[TMP3:%.*]] = mul nuw i32 [[TMP0]], [[TMP1]] 1577 // CHECK11-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP3]], align 4 1578 // CHECK11-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 1579 // CHECK11-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR1]], align 4 1580 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[N]], align 4 1581 // CHECK11-NEXT: store i32 [[TMP4]], i32* [[N_CASTED]], align 4 1582 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[N_CASTED]], align 4 1583 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[M]], align 4 1584 // CHECK11-NEXT: store i32 [[TMP6]], i32* [[M_CASTED]], align 4 1585 // CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[M_CASTED]], align 4 1586 // CHECK11-NEXT: [[TMP8:%.*]] = mul nuw i32 [[TMP0]], [[TMP1]] 1587 // CHECK11-NEXT: [[TMP9:%.*]] = mul nuw i32 [[TMP8]], 4 1588 // CHECK11-NEXT: [[TMP10:%.*]] = sext i32 [[TMP9]] to i64 1589 // CHECK11-NEXT: [[TMP11:%.*]] = bitcast [5 x i64]* [[DOTOFFLOAD_SIZES]] to i8* 1590 // CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP11]], i8* align 4 bitcast ([5 x i64]* @.offload_sizes to i8*), i32 40, i1 false) 1591 // CHECK11-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1592 // CHECK11-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* 1593 // CHECK11-NEXT: store i32 [[TMP5]], i32* [[TMP13]], align 4 1594 // CHECK11-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1595 // CHECK11-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32* 1596 // CHECK11-NEXT: store i32 [[TMP5]], i32* [[TMP15]], align 4 1597 // CHECK11-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 1598 // CHECK11-NEXT: store i8* null, i8** [[TMP16]], align 4 1599 // CHECK11-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1600 // CHECK11-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32* 1601 // CHECK11-NEXT: store i32 [[TMP7]], i32* [[TMP18]], align 4 1602 // CHECK11-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1603 // CHECK11-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32* 1604 // CHECK11-NEXT: store i32 [[TMP7]], i32* [[TMP20]], align 4 1605 // CHECK11-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 1606 // CHECK11-NEXT: store i8* null, i8** [[TMP21]], align 4 1607 // CHECK11-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1608 // CHECK11-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i32* 1609 // CHECK11-NEXT: store i32 [[TMP0]], i32* [[TMP23]], align 4 1610 // CHECK11-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1611 // CHECK11-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i32* 1612 // CHECK11-NEXT: store i32 [[TMP0]], i32* [[TMP25]], align 4 1613 // CHECK11-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 1614 // CHECK11-NEXT: store i8* null, i8** [[TMP26]], align 4 1615 // CHECK11-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 1616 // CHECK11-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i32* 1617 // CHECK11-NEXT: store i32 [[TMP1]], i32* [[TMP28]], align 4 1618 // CHECK11-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 1619 // CHECK11-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i32* 1620 // CHECK11-NEXT: store i32 [[TMP1]], i32* [[TMP30]], align 4 1621 // CHECK11-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 1622 // CHECK11-NEXT: store i8* null, i8** [[TMP31]], align 4 1623 // CHECK11-NEXT: [[TMP32:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 1624 // CHECK11-NEXT: [[TMP33:%.*]] = bitcast i8** [[TMP32]] to i32** 1625 // CHECK11-NEXT: store i32* [[VLA]], i32** [[TMP33]], align 4 1626 // CHECK11-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 1627 // CHECK11-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i32** 1628 // CHECK11-NEXT: store i32* [[VLA]], i32** [[TMP35]], align 4 1629 // CHECK11-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 1630 // CHECK11-NEXT: store i64 [[TMP10]], i64* [[TMP36]], align 4 1631 // CHECK11-NEXT: [[TMP37:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 1632 // CHECK11-NEXT: store i8* null, i8** [[TMP37]], align 4 1633 // CHECK11-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1634 // CHECK11-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1635 // CHECK11-NEXT: [[TMP40:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 1636 // CHECK11-NEXT: [[TMP41:%.*]] = load i32, i32* [[N]], align 4 1637 // CHECK11-NEXT: store i32 [[TMP41]], i32* [[DOTCAPTURE_EXPR_]], align 4 1638 // CHECK11-NEXT: [[TMP42:%.*]] = load i32, i32* [[M]], align 4 1639 // CHECK11-NEXT: store i32 [[TMP42]], i32* [[DOTCAPTURE_EXPR_2]], align 4 1640 // CHECK11-NEXT: [[TMP43:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 1641 // CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP43]], 0 1642 // CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 1643 // CHECK11-NEXT: [[CONV:%.*]] = sext i32 [[DIV]] to i64 1644 // CHECK11-NEXT: [[TMP44:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 1645 // CHECK11-NEXT: [[SUB4:%.*]] = sub nsw i32 [[TMP44]], 0 1646 // CHECK11-NEXT: [[DIV5:%.*]] = sdiv i32 [[SUB4]], 1 1647 // CHECK11-NEXT: [[CONV6:%.*]] = sext i32 [[DIV5]] to i64 1648 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV6]] 1649 // CHECK11-NEXT: [[SUB7:%.*]] = sub nsw i64 [[MUL]], 1 1650 // CHECK11-NEXT: store i64 [[SUB7]], i64* [[DOTCAPTURE_EXPR_3]], align 8 1651 // CHECK11-NEXT: [[TMP45:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_3]], align 8 1652 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP45]], 1 1653 // CHECK11-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 [[ADD]]) 1654 // CHECK11-NEXT: [[TMP46:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l80.region_id, i32 5, i8** [[TMP38]], i8** [[TMP39]], i64* [[TMP40]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 1655 // CHECK11-NEXT: [[TMP47:%.*]] = icmp ne i32 [[TMP46]], 0 1656 // CHECK11-NEXT: br i1 [[TMP47]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1657 // CHECK11: omp_offload.failed: 1658 // CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l80(i32 [[TMP5]], i32 [[TMP7]], i32 [[TMP0]], i32 [[TMP1]], i32* [[VLA]]) #[[ATTR3:[0-9]+]] 1659 // CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] 1660 // CHECK11: omp_offload.cont: 1661 // CHECK11-NEXT: [[TMP48:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 1662 // CHECK11-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef [[TMP48]]) 1663 // CHECK11-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 1664 // CHECK11-NEXT: [[TMP49:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 1665 // CHECK11-NEXT: call void @llvm.stackrestore(i8* [[TMP49]]) 1666 // CHECK11-NEXT: [[TMP50:%.*]] = load i32, i32* [[RETVAL]], align 4 1667 // CHECK11-NEXT: ret i32 [[TMP50]] 1668 // 1669 // 1670 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l80 1671 // CHECK11-SAME: (i32 noundef [[N:%.*]], i32 noundef [[M:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { 1672 // CHECK11-NEXT: entry: 1673 // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 1674 // CHECK11-NEXT: [[M_ADDR:%.*]] = alloca i32, align 4 1675 // CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 1676 // CHECK11-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 1677 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 1678 // CHECK11-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 1679 // CHECK11-NEXT: [[M_CASTED:%.*]] = alloca i32, align 4 1680 // CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 1681 // CHECK11-NEXT: store i32 [[M]], i32* [[M_ADDR]], align 4 1682 // CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 1683 // CHECK11-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 1684 // CHECK11-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 1685 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 1686 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 1687 // CHECK11-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4 1688 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 1689 // CHECK11-NEXT: store i32 [[TMP3]], i32* [[N_CASTED]], align 4 1690 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_CASTED]], align 4 1691 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[M_ADDR]], align 4 1692 // CHECK11-NEXT: store i32 [[TMP5]], i32* [[M_CASTED]], align 4 1693 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[M_CASTED]], align 4 1694 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP0]], i32 [[TMP1]], i32* [[TMP2]]) 1695 // CHECK11-NEXT: ret void 1696 // 1697 // 1698 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. 1699 // CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[M:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { 1700 // CHECK11-NEXT: entry: 1701 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 1702 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 1703 // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 1704 // CHECK11-NEXT: [[M_ADDR:%.*]] = alloca i32, align 4 1705 // CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 1706 // CHECK11-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 1707 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 1708 // CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 1709 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 1710 // CHECK11-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 1711 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 1712 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4 1713 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i64, align 8 1714 // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 1715 // CHECK11-NEXT: [[J:%.*]] = alloca i32, align 4 1716 // CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 1717 // CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 1718 // CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 1719 // CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1720 // CHECK11-NEXT: [[I11:%.*]] = alloca i32, align 4 1721 // CHECK11-NEXT: [[J12:%.*]] = alloca i32, align 4 1722 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 1723 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 1724 // CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 1725 // CHECK11-NEXT: store i32 [[M]], i32* [[M_ADDR]], align 4 1726 // CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 1727 // CHECK11-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 1728 // CHECK11-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 1729 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 1730 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 1731 // CHECK11-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4 1732 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 1733 // CHECK11-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 1734 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[M_ADDR]], align 4 1735 // CHECK11-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_4]], align 4 1736 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 1737 // CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 1738 // CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 1739 // CHECK11-NEXT: [[CONV:%.*]] = sext i32 [[DIV]] to i64 1740 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 1741 // CHECK11-NEXT: [[SUB6:%.*]] = sub nsw i32 [[TMP6]], 0 1742 // CHECK11-NEXT: [[DIV7:%.*]] = sdiv i32 [[SUB6]], 1 1743 // CHECK11-NEXT: [[CONV8:%.*]] = sext i32 [[DIV7]] to i64 1744 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV8]] 1745 // CHECK11-NEXT: [[SUB9:%.*]] = sub nsw i64 [[MUL]], 1 1746 // CHECK11-NEXT: store i64 [[SUB9]], i64* [[DOTCAPTURE_EXPR_5]], align 8 1747 // CHECK11-NEXT: store i32 0, i32* [[I]], align 4 1748 // CHECK11-NEXT: store i32 0, i32* [[J]], align 4 1749 // CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 1750 // CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP7]] 1751 // CHECK11-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]] 1752 // CHECK11: land.lhs.true: 1753 // CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 1754 // CHECK11-NEXT: [[CMP10:%.*]] = icmp slt i32 0, [[TMP8]] 1755 // CHECK11-NEXT: br i1 [[CMP10]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]] 1756 // CHECK11: omp.precond.then: 1757 // CHECK11-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 1758 // CHECK11-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 1759 // CHECK11-NEXT: store i64 [[TMP9]], i64* [[DOTOMP_UB]], align 8 1760 // CHECK11-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 1761 // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1762 // CHECK11-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 1763 // CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 1764 // CHECK11-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP11]], i32 92, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 1765 // CHECK11-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 1766 // CHECK11-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 1767 // CHECK11-NEXT: [[CMP13:%.*]] = icmp sgt i64 [[TMP12]], [[TMP13]] 1768 // CHECK11-NEXT: br i1 [[CMP13]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1769 // CHECK11: cond.true: 1770 // CHECK11-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 1771 // CHECK11-NEXT: br label [[COND_END:%.*]] 1772 // CHECK11: cond.false: 1773 // CHECK11-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 1774 // CHECK11-NEXT: br label [[COND_END]] 1775 // CHECK11: cond.end: 1776 // CHECK11-NEXT: [[COND:%.*]] = phi i64 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] 1777 // CHECK11-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 1778 // CHECK11-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 1779 // CHECK11-NEXT: store i64 [[TMP16]], i64* [[DOTOMP_IV]], align 8 1780 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1781 // CHECK11: omp.inner.for.cond: 1782 // CHECK11-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 1783 // CHECK11-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 1784 // CHECK11-NEXT: [[CMP14:%.*]] = icmp sle i64 [[TMP17]], [[TMP18]] 1785 // CHECK11-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1786 // CHECK11: omp.inner.for.body: 1787 // CHECK11-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 1788 // CHECK11-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 1789 // CHECK11-NEXT: [[SUB15:%.*]] = sub nsw i32 [[TMP20]], 0 1790 // CHECK11-NEXT: [[DIV16:%.*]] = sdiv i32 [[SUB15]], 1 1791 // CHECK11-NEXT: [[MUL17:%.*]] = mul nsw i32 1, [[DIV16]] 1792 // CHECK11-NEXT: [[CONV18:%.*]] = sext i32 [[MUL17]] to i64 1793 // CHECK11-NEXT: [[DIV19:%.*]] = sdiv i64 [[TMP19]], [[CONV18]] 1794 // CHECK11-NEXT: [[MUL20:%.*]] = mul nsw i64 [[DIV19]], 1 1795 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i64 0, [[MUL20]] 1796 // CHECK11-NEXT: [[CONV21:%.*]] = trunc i64 [[ADD]] to i32 1797 // CHECK11-NEXT: store i32 [[CONV21]], i32* [[I11]], align 4 1798 // CHECK11-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 1799 // CHECK11-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 1800 // CHECK11-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 1801 // CHECK11-NEXT: [[SUB22:%.*]] = sub nsw i32 [[TMP23]], 0 1802 // CHECK11-NEXT: [[DIV23:%.*]] = sdiv i32 [[SUB22]], 1 1803 // CHECK11-NEXT: [[MUL24:%.*]] = mul nsw i32 1, [[DIV23]] 1804 // CHECK11-NEXT: [[CONV25:%.*]] = sext i32 [[MUL24]] to i64 1805 // CHECK11-NEXT: [[DIV26:%.*]] = sdiv i64 [[TMP22]], [[CONV25]] 1806 // CHECK11-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 1807 // CHECK11-NEXT: [[SUB27:%.*]] = sub nsw i32 [[TMP24]], 0 1808 // CHECK11-NEXT: [[DIV28:%.*]] = sdiv i32 [[SUB27]], 1 1809 // CHECK11-NEXT: [[MUL29:%.*]] = mul nsw i32 1, [[DIV28]] 1810 // CHECK11-NEXT: [[CONV30:%.*]] = sext i32 [[MUL29]] to i64 1811 // CHECK11-NEXT: [[MUL31:%.*]] = mul nsw i64 [[DIV26]], [[CONV30]] 1812 // CHECK11-NEXT: [[SUB32:%.*]] = sub nsw i64 [[TMP21]], [[MUL31]] 1813 // CHECK11-NEXT: [[MUL33:%.*]] = mul nsw i64 [[SUB32]], 1 1814 // CHECK11-NEXT: [[ADD34:%.*]] = add nsw i64 0, [[MUL33]] 1815 // CHECK11-NEXT: [[CONV35:%.*]] = trunc i64 [[ADD34]] to i32 1816 // CHECK11-NEXT: store i32 [[CONV35]], i32* [[J12]], align 4 1817 // CHECK11-NEXT: [[TMP25:%.*]] = load i32, i32* [[I11]], align 4 1818 // CHECK11-NEXT: [[TMP26:%.*]] = mul nsw i32 [[TMP25]], [[TMP1]] 1819 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i32 [[TMP26]] 1820 // CHECK11-NEXT: [[TMP27:%.*]] = load i32, i32* [[J12]], align 4 1821 // CHECK11-NEXT: [[ARRAYIDX36:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX]], i32 [[TMP27]] 1822 // CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX36]], align 4 1823 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1824 // CHECK11: omp.body.continue: 1825 // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1826 // CHECK11: omp.inner.for.inc: 1827 // CHECK11-NEXT: [[TMP28:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 1828 // CHECK11-NEXT: [[ADD37:%.*]] = add nsw i64 [[TMP28]], 1 1829 // CHECK11-NEXT: store i64 [[ADD37]], i64* [[DOTOMP_IV]], align 8 1830 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] 1831 // CHECK11: omp.inner.for.end: 1832 // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1833 // CHECK11: omp.loop.exit: 1834 // CHECK11-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 1835 // CHECK11-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4 1836 // CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP30]]) 1837 // CHECK11-NEXT: br label [[OMP_PRECOND_END]] 1838 // CHECK11: omp.precond.end: 1839 // CHECK11-NEXT: ret void 1840 // 1841 // 1842 // CHECK11-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ 1843 // CHECK11-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR5:[0-9]+]] comdat { 1844 // CHECK11-NEXT: entry: 1845 // CHECK11-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 1846 // CHECK11-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 1847 // CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 1848 // CHECK11-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 1849 // CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 1850 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 1851 // CHECK11-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 1852 // CHECK11-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 1853 // CHECK11-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1854 // CHECK11-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to [10 x [2 x i32]]** 1855 // CHECK11-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[TMP1]], align 4 1856 // CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1857 // CHECK11-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [10 x [2 x i32]]** 1858 // CHECK11-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[TMP3]], align 4 1859 // CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 1860 // CHECK11-NEXT: store i8* null, i8** [[TMP4]], align 4 1861 // CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1862 // CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1863 // CHECK11-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 20) 1864 // CHECK11-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l67.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 1865 // CHECK11-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 1866 // CHECK11-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1867 // CHECK11: omp_offload.failed: 1868 // CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l67([10 x [2 x i32]]* [[A]]) #[[ATTR3]] 1869 // CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] 1870 // CHECK11: omp_offload.cont: 1871 // CHECK11-NEXT: ret i32 0 1872 // 1873 // 1874 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l67 1875 // CHECK11-SAME: ([10 x [2 x i32]]* noundef nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { 1876 // CHECK11-NEXT: entry: 1877 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 4 1878 // CHECK11-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 4 1879 // CHECK11-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 4 1880 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x [2 x i32]]*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), [10 x [2 x i32]]* [[TMP0]]) 1881 // CHECK11-NEXT: ret void 1882 // 1883 // 1884 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 1885 // CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x [2 x i32]]* noundef nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { 1886 // CHECK11-NEXT: entry: 1887 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 1888 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 1889 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 4 1890 // CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1891 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 1892 // CHECK11-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 1893 // CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1894 // CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1895 // CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1896 // CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1897 // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 1898 // CHECK11-NEXT: [[J:%.*]] = alloca i32, align 4 1899 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 1900 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 1901 // CHECK11-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 4 1902 // CHECK11-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 4 1903 // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1904 // CHECK11-NEXT: store i32 19, i32* [[DOTOMP_UB]], align 4 1905 // CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 1906 // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1907 // CHECK11-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 1908 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 1909 // CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 1910 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1911 // CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 19 1912 // CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1913 // CHECK11: cond.true: 1914 // CHECK11-NEXT: br label [[COND_END:%.*]] 1915 // CHECK11: cond.false: 1916 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1917 // CHECK11-NEXT: br label [[COND_END]] 1918 // CHECK11: cond.end: 1919 // CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 19, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 1920 // CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 1921 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1922 // CHECK11-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 1923 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1924 // CHECK11: omp.inner.for.cond: 1925 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1926 // CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1927 // CHECK11-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] 1928 // CHECK11-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1929 // CHECK11: omp.inner.for.body: 1930 // CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1931 // CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP8]], 2 1932 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 1933 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1934 // CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4 1935 // CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1936 // CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1937 // CHECK11-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP10]], 2 1938 // CHECK11-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 2 1939 // CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP9]], [[MUL4]] 1940 // CHECK11-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1 1941 // CHECK11-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]] 1942 // CHECK11-NEXT: store i32 [[ADD6]], i32* [[J]], align 4 1943 // CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 1944 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]]* [[TMP0]], i32 0, i32 [[TMP11]] 1945 // CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[J]], align 4 1946 // CHECK11-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[ARRAYIDX]], i32 0, i32 [[TMP12]] 1947 // CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX7]], align 4 1948 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1949 // CHECK11: omp.body.continue: 1950 // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1951 // CHECK11: omp.inner.for.inc: 1952 // CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1953 // CHECK11-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP13]], 1 1954 // CHECK11-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 1955 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] 1956 // CHECK11: omp.inner.for.end: 1957 // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1958 // CHECK11: omp.loop.exit: 1959 // CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) 1960 // CHECK11-NEXT: ret void 1961 // 1962 // 1963 // CHECK11-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 1964 // CHECK11-SAME: () #[[ATTR6:[0-9]+]] { 1965 // CHECK11-NEXT: entry: 1966 // CHECK11-NEXT: call void @__tgt_register_requires(i64 1) 1967 // CHECK11-NEXT: ret void 1968 // 1969 // 1970 // CHECK12-LABEL: define {{[^@]+}}@main 1971 // CHECK12-SAME: (i32 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { 1972 // CHECK12-NEXT: entry: 1973 // CHECK12-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1974 // CHECK12-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 1975 // CHECK12-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 4 1976 // CHECK12-NEXT: [[N:%.*]] = alloca i32, align 4 1977 // CHECK12-NEXT: [[M:%.*]] = alloca i32, align 4 1978 // CHECK12-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 1979 // CHECK12-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 1980 // CHECK12-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 1981 // CHECK12-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 1982 // CHECK12-NEXT: [[M_CASTED:%.*]] = alloca i32, align 4 1983 // CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4 1984 // CHECK12-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4 1985 // CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4 1986 // CHECK12-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 4 1987 // CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 1988 // CHECK12-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 1989 // CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 1990 // CHECK12-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 1991 // CHECK12-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i64, align 8 1992 // CHECK12-NEXT: store i32 0, i32* [[RETVAL]], align 4 1993 // CHECK12-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 1994 // CHECK12-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 4 1995 // CHECK12-NEXT: store i32 100, i32* [[N]], align 4 1996 // CHECK12-NEXT: store i32 2, i32* [[M]], align 4 1997 // CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 1998 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[M]], align 4 1999 // CHECK12-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() 2000 // CHECK12-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 2001 // CHECK12-NEXT: [[TMP3:%.*]] = mul nuw i32 [[TMP0]], [[TMP1]] 2002 // CHECK12-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP3]], align 4 2003 // CHECK12-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 2004 // CHECK12-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR1]], align 4 2005 // CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[N]], align 4 2006 // CHECK12-NEXT: store i32 [[TMP4]], i32* [[N_CASTED]], align 4 2007 // CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[N_CASTED]], align 4 2008 // CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[M]], align 4 2009 // CHECK12-NEXT: store i32 [[TMP6]], i32* [[M_CASTED]], align 4 2010 // CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[M_CASTED]], align 4 2011 // CHECK12-NEXT: [[TMP8:%.*]] = mul nuw i32 [[TMP0]], [[TMP1]] 2012 // CHECK12-NEXT: [[TMP9:%.*]] = mul nuw i32 [[TMP8]], 4 2013 // CHECK12-NEXT: [[TMP10:%.*]] = sext i32 [[TMP9]] to i64 2014 // CHECK12-NEXT: [[TMP11:%.*]] = bitcast [5 x i64]* [[DOTOFFLOAD_SIZES]] to i8* 2015 // CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP11]], i8* align 4 bitcast ([5 x i64]* @.offload_sizes to i8*), i32 40, i1 false) 2016 // CHECK12-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2017 // CHECK12-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* 2018 // CHECK12-NEXT: store i32 [[TMP5]], i32* [[TMP13]], align 4 2019 // CHECK12-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2020 // CHECK12-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32* 2021 // CHECK12-NEXT: store i32 [[TMP5]], i32* [[TMP15]], align 4 2022 // CHECK12-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 2023 // CHECK12-NEXT: store i8* null, i8** [[TMP16]], align 4 2024 // CHECK12-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 2025 // CHECK12-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32* 2026 // CHECK12-NEXT: store i32 [[TMP7]], i32* [[TMP18]], align 4 2027 // CHECK12-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 2028 // CHECK12-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32* 2029 // CHECK12-NEXT: store i32 [[TMP7]], i32* [[TMP20]], align 4 2030 // CHECK12-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 2031 // CHECK12-NEXT: store i8* null, i8** [[TMP21]], align 4 2032 // CHECK12-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 2033 // CHECK12-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i32* 2034 // CHECK12-NEXT: store i32 [[TMP0]], i32* [[TMP23]], align 4 2035 // CHECK12-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 2036 // CHECK12-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i32* 2037 // CHECK12-NEXT: store i32 [[TMP0]], i32* [[TMP25]], align 4 2038 // CHECK12-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 2039 // CHECK12-NEXT: store i8* null, i8** [[TMP26]], align 4 2040 // CHECK12-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 2041 // CHECK12-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i32* 2042 // CHECK12-NEXT: store i32 [[TMP1]], i32* [[TMP28]], align 4 2043 // CHECK12-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 2044 // CHECK12-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i32* 2045 // CHECK12-NEXT: store i32 [[TMP1]], i32* [[TMP30]], align 4 2046 // CHECK12-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 2047 // CHECK12-NEXT: store i8* null, i8** [[TMP31]], align 4 2048 // CHECK12-NEXT: [[TMP32:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 2049 // CHECK12-NEXT: [[TMP33:%.*]] = bitcast i8** [[TMP32]] to i32** 2050 // CHECK12-NEXT: store i32* [[VLA]], i32** [[TMP33]], align 4 2051 // CHECK12-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 2052 // CHECK12-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i32** 2053 // CHECK12-NEXT: store i32* [[VLA]], i32** [[TMP35]], align 4 2054 // CHECK12-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 2055 // CHECK12-NEXT: store i64 [[TMP10]], i64* [[TMP36]], align 4 2056 // CHECK12-NEXT: [[TMP37:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 2057 // CHECK12-NEXT: store i8* null, i8** [[TMP37]], align 4 2058 // CHECK12-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2059 // CHECK12-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2060 // CHECK12-NEXT: [[TMP40:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 2061 // CHECK12-NEXT: [[TMP41:%.*]] = load i32, i32* [[N]], align 4 2062 // CHECK12-NEXT: store i32 [[TMP41]], i32* [[DOTCAPTURE_EXPR_]], align 4 2063 // CHECK12-NEXT: [[TMP42:%.*]] = load i32, i32* [[M]], align 4 2064 // CHECK12-NEXT: store i32 [[TMP42]], i32* [[DOTCAPTURE_EXPR_2]], align 4 2065 // CHECK12-NEXT: [[TMP43:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 2066 // CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP43]], 0 2067 // CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 2068 // CHECK12-NEXT: [[CONV:%.*]] = sext i32 [[DIV]] to i64 2069 // CHECK12-NEXT: [[TMP44:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 2070 // CHECK12-NEXT: [[SUB4:%.*]] = sub nsw i32 [[TMP44]], 0 2071 // CHECK12-NEXT: [[DIV5:%.*]] = sdiv i32 [[SUB4]], 1 2072 // CHECK12-NEXT: [[CONV6:%.*]] = sext i32 [[DIV5]] to i64 2073 // CHECK12-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV6]] 2074 // CHECK12-NEXT: [[SUB7:%.*]] = sub nsw i64 [[MUL]], 1 2075 // CHECK12-NEXT: store i64 [[SUB7]], i64* [[DOTCAPTURE_EXPR_3]], align 8 2076 // CHECK12-NEXT: [[TMP45:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_3]], align 8 2077 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP45]], 1 2078 // CHECK12-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 [[ADD]]) 2079 // CHECK12-NEXT: [[TMP46:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l80.region_id, i32 5, i8** [[TMP38]], i8** [[TMP39]], i64* [[TMP40]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 2080 // CHECK12-NEXT: [[TMP47:%.*]] = icmp ne i32 [[TMP46]], 0 2081 // CHECK12-NEXT: br i1 [[TMP47]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 2082 // CHECK12: omp_offload.failed: 2083 // CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l80(i32 [[TMP5]], i32 [[TMP7]], i32 [[TMP0]], i32 [[TMP1]], i32* [[VLA]]) #[[ATTR3:[0-9]+]] 2084 // CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT]] 2085 // CHECK12: omp_offload.cont: 2086 // CHECK12-NEXT: [[TMP48:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 2087 // CHECK12-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef [[TMP48]]) 2088 // CHECK12-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 2089 // CHECK12-NEXT: [[TMP49:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 2090 // CHECK12-NEXT: call void @llvm.stackrestore(i8* [[TMP49]]) 2091 // CHECK12-NEXT: [[TMP50:%.*]] = load i32, i32* [[RETVAL]], align 4 2092 // CHECK12-NEXT: ret i32 [[TMP50]] 2093 // 2094 // 2095 // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l80 2096 // CHECK12-SAME: (i32 noundef [[N:%.*]], i32 noundef [[M:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { 2097 // CHECK12-NEXT: entry: 2098 // CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 2099 // CHECK12-NEXT: [[M_ADDR:%.*]] = alloca i32, align 4 2100 // CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 2101 // CHECK12-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 2102 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 2103 // CHECK12-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 2104 // CHECK12-NEXT: [[M_CASTED:%.*]] = alloca i32, align 4 2105 // CHECK12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 2106 // CHECK12-NEXT: store i32 [[M]], i32* [[M_ADDR]], align 4 2107 // CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 2108 // CHECK12-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 2109 // CHECK12-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 2110 // CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 2111 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 2112 // CHECK12-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4 2113 // CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 2114 // CHECK12-NEXT: store i32 [[TMP3]], i32* [[N_CASTED]], align 4 2115 // CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_CASTED]], align 4 2116 // CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[M_ADDR]], align 4 2117 // CHECK12-NEXT: store i32 [[TMP5]], i32* [[M_CASTED]], align 4 2118 // CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[M_CASTED]], align 4 2119 // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP0]], i32 [[TMP1]], i32* [[TMP2]]) 2120 // CHECK12-NEXT: ret void 2121 // 2122 // 2123 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined. 2124 // CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[M:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { 2125 // CHECK12-NEXT: entry: 2126 // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2127 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2128 // CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 2129 // CHECK12-NEXT: [[M_ADDR:%.*]] = alloca i32, align 4 2130 // CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 2131 // CHECK12-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 2132 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 2133 // CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 2134 // CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 2135 // CHECK12-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 2136 // CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 2137 // CHECK12-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4 2138 // CHECK12-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i64, align 8 2139 // CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 2140 // CHECK12-NEXT: [[J:%.*]] = alloca i32, align 4 2141 // CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 2142 // CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 2143 // CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 2144 // CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2145 // CHECK12-NEXT: [[I11:%.*]] = alloca i32, align 4 2146 // CHECK12-NEXT: [[J12:%.*]] = alloca i32, align 4 2147 // CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2148 // CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2149 // CHECK12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 2150 // CHECK12-NEXT: store i32 [[M]], i32* [[M_ADDR]], align 4 2151 // CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 2152 // CHECK12-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 2153 // CHECK12-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 2154 // CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 2155 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 2156 // CHECK12-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4 2157 // CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 2158 // CHECK12-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 2159 // CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[M_ADDR]], align 4 2160 // CHECK12-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_4]], align 4 2161 // CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 2162 // CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 2163 // CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 2164 // CHECK12-NEXT: [[CONV:%.*]] = sext i32 [[DIV]] to i64 2165 // CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 2166 // CHECK12-NEXT: [[SUB6:%.*]] = sub nsw i32 [[TMP6]], 0 2167 // CHECK12-NEXT: [[DIV7:%.*]] = sdiv i32 [[SUB6]], 1 2168 // CHECK12-NEXT: [[CONV8:%.*]] = sext i32 [[DIV7]] to i64 2169 // CHECK12-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV8]] 2170 // CHECK12-NEXT: [[SUB9:%.*]] = sub nsw i64 [[MUL]], 1 2171 // CHECK12-NEXT: store i64 [[SUB9]], i64* [[DOTCAPTURE_EXPR_5]], align 8 2172 // CHECK12-NEXT: store i32 0, i32* [[I]], align 4 2173 // CHECK12-NEXT: store i32 0, i32* [[J]], align 4 2174 // CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 2175 // CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP7]] 2176 // CHECK12-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]] 2177 // CHECK12: land.lhs.true: 2178 // CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 2179 // CHECK12-NEXT: [[CMP10:%.*]] = icmp slt i32 0, [[TMP8]] 2180 // CHECK12-NEXT: br i1 [[CMP10]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]] 2181 // CHECK12: omp.precond.then: 2182 // CHECK12-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 2183 // CHECK12-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 2184 // CHECK12-NEXT: store i64 [[TMP9]], i64* [[DOTOMP_UB]], align 8 2185 // CHECK12-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 2186 // CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 2187 // CHECK12-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 2188 // CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 2189 // CHECK12-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP11]], i32 92, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 2190 // CHECK12-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 2191 // CHECK12-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 2192 // CHECK12-NEXT: [[CMP13:%.*]] = icmp sgt i64 [[TMP12]], [[TMP13]] 2193 // CHECK12-NEXT: br i1 [[CMP13]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2194 // CHECK12: cond.true: 2195 // CHECK12-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 2196 // CHECK12-NEXT: br label [[COND_END:%.*]] 2197 // CHECK12: cond.false: 2198 // CHECK12-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 2199 // CHECK12-NEXT: br label [[COND_END]] 2200 // CHECK12: cond.end: 2201 // CHECK12-NEXT: [[COND:%.*]] = phi i64 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] 2202 // CHECK12-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 2203 // CHECK12-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 2204 // CHECK12-NEXT: store i64 [[TMP16]], i64* [[DOTOMP_IV]], align 8 2205 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2206 // CHECK12: omp.inner.for.cond: 2207 // CHECK12-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 2208 // CHECK12-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 2209 // CHECK12-NEXT: [[CMP14:%.*]] = icmp sle i64 [[TMP17]], [[TMP18]] 2210 // CHECK12-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2211 // CHECK12: omp.inner.for.body: 2212 // CHECK12-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 2213 // CHECK12-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 2214 // CHECK12-NEXT: [[SUB15:%.*]] = sub nsw i32 [[TMP20]], 0 2215 // CHECK12-NEXT: [[DIV16:%.*]] = sdiv i32 [[SUB15]], 1 2216 // CHECK12-NEXT: [[MUL17:%.*]] = mul nsw i32 1, [[DIV16]] 2217 // CHECK12-NEXT: [[CONV18:%.*]] = sext i32 [[MUL17]] to i64 2218 // CHECK12-NEXT: [[DIV19:%.*]] = sdiv i64 [[TMP19]], [[CONV18]] 2219 // CHECK12-NEXT: [[MUL20:%.*]] = mul nsw i64 [[DIV19]], 1 2220 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i64 0, [[MUL20]] 2221 // CHECK12-NEXT: [[CONV21:%.*]] = trunc i64 [[ADD]] to i32 2222 // CHECK12-NEXT: store i32 [[CONV21]], i32* [[I11]], align 4 2223 // CHECK12-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 2224 // CHECK12-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 2225 // CHECK12-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 2226 // CHECK12-NEXT: [[SUB22:%.*]] = sub nsw i32 [[TMP23]], 0 2227 // CHECK12-NEXT: [[DIV23:%.*]] = sdiv i32 [[SUB22]], 1 2228 // CHECK12-NEXT: [[MUL24:%.*]] = mul nsw i32 1, [[DIV23]] 2229 // CHECK12-NEXT: [[CONV25:%.*]] = sext i32 [[MUL24]] to i64 2230 // CHECK12-NEXT: [[DIV26:%.*]] = sdiv i64 [[TMP22]], [[CONV25]] 2231 // CHECK12-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 2232 // CHECK12-NEXT: [[SUB27:%.*]] = sub nsw i32 [[TMP24]], 0 2233 // CHECK12-NEXT: [[DIV28:%.*]] = sdiv i32 [[SUB27]], 1 2234 // CHECK12-NEXT: [[MUL29:%.*]] = mul nsw i32 1, [[DIV28]] 2235 // CHECK12-NEXT: [[CONV30:%.*]] = sext i32 [[MUL29]] to i64 2236 // CHECK12-NEXT: [[MUL31:%.*]] = mul nsw i64 [[DIV26]], [[CONV30]] 2237 // CHECK12-NEXT: [[SUB32:%.*]] = sub nsw i64 [[TMP21]], [[MUL31]] 2238 // CHECK12-NEXT: [[MUL33:%.*]] = mul nsw i64 [[SUB32]], 1 2239 // CHECK12-NEXT: [[ADD34:%.*]] = add nsw i64 0, [[MUL33]] 2240 // CHECK12-NEXT: [[CONV35:%.*]] = trunc i64 [[ADD34]] to i32 2241 // CHECK12-NEXT: store i32 [[CONV35]], i32* [[J12]], align 4 2242 // CHECK12-NEXT: [[TMP25:%.*]] = load i32, i32* [[I11]], align 4 2243 // CHECK12-NEXT: [[TMP26:%.*]] = mul nsw i32 [[TMP25]], [[TMP1]] 2244 // CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i32 [[TMP26]] 2245 // CHECK12-NEXT: [[TMP27:%.*]] = load i32, i32* [[J12]], align 4 2246 // CHECK12-NEXT: [[ARRAYIDX36:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX]], i32 [[TMP27]] 2247 // CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX36]], align 4 2248 // CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2249 // CHECK12: omp.body.continue: 2250 // CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2251 // CHECK12: omp.inner.for.inc: 2252 // CHECK12-NEXT: [[TMP28:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 2253 // CHECK12-NEXT: [[ADD37:%.*]] = add nsw i64 [[TMP28]], 1 2254 // CHECK12-NEXT: store i64 [[ADD37]], i64* [[DOTOMP_IV]], align 8 2255 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] 2256 // CHECK12: omp.inner.for.end: 2257 // CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2258 // CHECK12: omp.loop.exit: 2259 // CHECK12-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 2260 // CHECK12-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4 2261 // CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP30]]) 2262 // CHECK12-NEXT: br label [[OMP_PRECOND_END]] 2263 // CHECK12: omp.precond.end: 2264 // CHECK12-NEXT: ret void 2265 // 2266 // 2267 // CHECK12-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ 2268 // CHECK12-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR5:[0-9]+]] comdat { 2269 // CHECK12-NEXT: entry: 2270 // CHECK12-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 2271 // CHECK12-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 2272 // CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 2273 // CHECK12-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 2274 // CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 2275 // CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 2276 // CHECK12-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 2277 // CHECK12-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 2278 // CHECK12-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2279 // CHECK12-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to [10 x [2 x i32]]** 2280 // CHECK12-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[TMP1]], align 4 2281 // CHECK12-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2282 // CHECK12-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [10 x [2 x i32]]** 2283 // CHECK12-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[TMP3]], align 4 2284 // CHECK12-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 2285 // CHECK12-NEXT: store i8* null, i8** [[TMP4]], align 4 2286 // CHECK12-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2287 // CHECK12-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2288 // CHECK12-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 20) 2289 // CHECK12-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l67.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 2290 // CHECK12-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 2291 // CHECK12-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 2292 // CHECK12: omp_offload.failed: 2293 // CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l67([10 x [2 x i32]]* [[A]]) #[[ATTR3]] 2294 // CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT]] 2295 // CHECK12: omp_offload.cont: 2296 // CHECK12-NEXT: ret i32 0 2297 // 2298 // 2299 // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l67 2300 // CHECK12-SAME: ([10 x [2 x i32]]* noundef nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { 2301 // CHECK12-NEXT: entry: 2302 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 4 2303 // CHECK12-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 4 2304 // CHECK12-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 4 2305 // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x [2 x i32]]*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), [10 x [2 x i32]]* [[TMP0]]) 2306 // CHECK12-NEXT: ret void 2307 // 2308 // 2309 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..1 2310 // CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x [2 x i32]]* noundef nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { 2311 // CHECK12-NEXT: entry: 2312 // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2313 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2314 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 4 2315 // CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2316 // CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 2317 // CHECK12-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 2318 // CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2319 // CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2320 // CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2321 // CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2322 // CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 2323 // CHECK12-NEXT: [[J:%.*]] = alloca i32, align 4 2324 // CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2325 // CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2326 // CHECK12-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 4 2327 // CHECK12-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 4 2328 // CHECK12-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 2329 // CHECK12-NEXT: store i32 19, i32* [[DOTOMP_UB]], align 4 2330 // CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 2331 // CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 2332 // CHECK12-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 2333 // CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 2334 // CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 2335 // CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2336 // CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 19 2337 // CHECK12-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2338 // CHECK12: cond.true: 2339 // CHECK12-NEXT: br label [[COND_END:%.*]] 2340 // CHECK12: cond.false: 2341 // CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2342 // CHECK12-NEXT: br label [[COND_END]] 2343 // CHECK12: cond.end: 2344 // CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 19, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 2345 // CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 2346 // CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 2347 // CHECK12-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 2348 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2349 // CHECK12: omp.inner.for.cond: 2350 // CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2351 // CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2352 // CHECK12-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] 2353 // CHECK12-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2354 // CHECK12: omp.inner.for.body: 2355 // CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2356 // CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP8]], 2 2357 // CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 2358 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 2359 // CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4 2360 // CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2361 // CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2362 // CHECK12-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP10]], 2 2363 // CHECK12-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 2 2364 // CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP9]], [[MUL4]] 2365 // CHECK12-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1 2366 // CHECK12-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]] 2367 // CHECK12-NEXT: store i32 [[ADD6]], i32* [[J]], align 4 2368 // CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 2369 // CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]]* [[TMP0]], i32 0, i32 [[TMP11]] 2370 // CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[J]], align 4 2371 // CHECK12-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[ARRAYIDX]], i32 0, i32 [[TMP12]] 2372 // CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX7]], align 4 2373 // CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2374 // CHECK12: omp.body.continue: 2375 // CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2376 // CHECK12: omp.inner.for.inc: 2377 // CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2378 // CHECK12-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP13]], 1 2379 // CHECK12-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 2380 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] 2381 // CHECK12: omp.inner.for.end: 2382 // CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2383 // CHECK12: omp.loop.exit: 2384 // CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) 2385 // CHECK12-NEXT: ret void 2386 // 2387 // 2388 // CHECK12-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 2389 // CHECK12-SAME: () #[[ATTR6:[0-9]+]] { 2390 // CHECK12-NEXT: entry: 2391 // CHECK12-NEXT: call void @__tgt_register_requires(i64 1) 2392 // CHECK12-NEXT: ret void 2393 // 2394