1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ 2 // Test host codegen. 3 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1 4 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 5 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1 6 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK3 7 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 8 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK3 9 10 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 11 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 12 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 13 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 14 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 15 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 16 17 // Test target codegen - host bc file has to be created first. 18 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc 19 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9 20 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s 21 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9 22 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc 23 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11 24 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s 25 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11 26 27 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc 28 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 29 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s 30 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 31 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc 32 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 33 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s 34 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 35 36 // Test host codegen. 37 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1 38 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 39 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1 40 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK3 41 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 42 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK3 43 44 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 45 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 46 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 47 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 48 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 49 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 50 51 // Test target codegen - host bc file has to be created first. 52 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc 53 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9 54 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s 55 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9 56 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc 57 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11 58 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s 59 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11 60 61 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc 62 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 63 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s 64 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 65 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc 66 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 67 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s 68 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 69 70 // expected-no-diagnostics 71 #ifndef HEADER 72 #define HEADER 73 74 75 76 77 // We have 8 target regions, but only 7 that actually will generate offloading 78 // code, only 6 will have mapped arguments, and only 4 have all-constant map 79 // sizes. 80 81 82 83 // Check target registration is registered as a Ctor. 84 85 86 template<typename tx, typename ty> 87 struct TT{ 88 tx X; 89 ty Y; 90 }; 91 92 int global; 93 94 int foo(int n) { 95 int a = 0; 96 short aa = 0; 97 float b[10]; 98 float bn[n]; 99 double c[5][10]; 100 double cn[5][n]; 101 TT<long long, char> d; 102 103 #pragma omp target teams distribute num_teams(a) thread_limit(a) firstprivate(aa) nowait 104 for (int i = 0; i < 10; ++i) { 105 } 106 107 #pragma omp target teams distribute if(target: 0) 108 for (int i = 0; i < 10; ++i) { 109 a += 1; 110 } 111 112 113 #pragma omp target teams distribute if(target: 1) 114 for (int i = 0; i < 10; ++i) { 115 aa += 1; 116 } 117 118 119 120 #pragma omp target teams distribute if(target: n>10) 121 for (int i = 0; i < 10; ++i) { 122 a += 1; 123 aa += 1; 124 } 125 126 // We capture 3 VLA sizes in this target region 127 128 129 130 131 132 // The names below are not necessarily consistent with the names used for the 133 // addresses above as some are repeated. 134 135 136 137 138 139 140 141 142 143 144 145 #pragma omp target teams distribute if(target: n>20) dist_schedule(static, n) 146 for (int i = 0; i < 10; ++i) { 147 a += 1; 148 b[2] += 1.0; 149 bn[3] += 1.0; 150 c[1][2] += 1.0; 151 cn[1][3] += 1.0; 152 d.X += 1; 153 d.Y += 1; 154 } 155 156 return a; 157 } 158 159 // Check that the offloading functions are emitted and that the arguments are 160 // correct and loaded correctly for the target regions in foo(). 161 162 163 164 165 // Create stack storage and store argument in there. 166 167 // Create stack storage and store argument in there. 168 169 // Create stack storage and store argument in there. 170 171 // Create local storage for each capture. 172 173 174 175 // To reduce complexity, we're only going as far as validating the signature of the outlined parallel function. 176 177 template<typename tx> 178 tx ftemplate(int n) { 179 tx a = 0; 180 short aa = 0; 181 tx b[10]; 182 183 #pragma omp target teams distribute if(target: n>40) 184 for (int i = 0; i < 10; ++i) { 185 a += 1; 186 aa += 1; 187 b[2] += 1; 188 } 189 190 return a; 191 } 192 193 static 194 int fstatic(int n) { 195 int a = 0; 196 short aa = 0; 197 char aaa = 0; 198 int b[10]; 199 200 #pragma omp target teams distribute if(target: n>50) 201 for (int i = a; i < n; ++i) { 202 a += 1; 203 aa += 1; 204 aaa += 1; 205 b[2] += 1; 206 } 207 208 return a; 209 } 210 211 struct S1 { 212 double a; 213 214 int r1(int n){ 215 int b = n+1; 216 short int c[2][n]; 217 218 #pragma omp target teams distribute if(target: n>60) 219 for (int i = 0; i < 10; ++i) { 220 this->a = (double)b + 1.5; 221 c[1][1] = ++a; 222 } 223 224 return c[1][1] + (int)b; 225 } 226 }; 227 228 int bar(int n){ 229 int a = 0; 230 231 a += foo(n); 232 233 S1 S; 234 a += S.r1(n); 235 236 a += fstatic(n); 237 238 a += ftemplate<int>(n); 239 240 return a; 241 } 242 243 244 245 // We capture 2 VLA sizes in this target region 246 247 248 // The names below are not necessarily consistent with the names used for the 249 // addresses above as some are repeated. 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 // Check that the offloading functions are emitted and that the arguments are 272 // correct and loaded correctly for the target regions of the callees of bar(). 273 274 // Create local storage for each capture. 275 // Store captures in the context. 276 277 278 // To reduce complexity, we're only going as far as validating the signature of the outlined parallel function. 279 280 281 // Create local storage for each capture. 282 // Store captures in the context. 283 284 285 286 287 // To reduce complexity, we're only going as far as validating the signature of the outlined parallel function. 288 289 // Create local storage for each capture. 290 // Store captures in the context. 291 292 293 294 // To reduce complexity, we're only going as far as validating the signature of the outlined parallel function. 295 296 #endif 297 // CHECK1-LABEL: define {{[^@]+}}@_Z3fooi 298 // CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { 299 // CHECK1-NEXT: entry: 300 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 301 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4 302 // CHECK1-NEXT: [[AA:%.*]] = alloca i16, align 2 303 // CHECK1-NEXT: [[B:%.*]] = alloca [10 x float], align 4 304 // CHECK1-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 305 // CHECK1-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 306 // CHECK1-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 307 // CHECK1-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 308 // CHECK1-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 309 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 310 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 311 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 312 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 313 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED4:%.*]] = alloca i64, align 8 314 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 315 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 316 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 317 // CHECK1-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4 318 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 319 // CHECK1-NEXT: [[AA_CASTED7:%.*]] = alloca i64, align 8 320 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS9:%.*]] = alloca [1 x i8*], align 8 321 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS10:%.*]] = alloca [1 x i8*], align 8 322 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS11:%.*]] = alloca [1 x i8*], align 8 323 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 324 // CHECK1-NEXT: [[A_CASTED12:%.*]] = alloca i64, align 8 325 // CHECK1-NEXT: [[AA_CASTED14:%.*]] = alloca i64, align 8 326 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS16:%.*]] = alloca [2 x i8*], align 8 327 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS17:%.*]] = alloca [2 x i8*], align 8 328 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS18:%.*]] = alloca [2 x i8*], align 8 329 // CHECK1-NEXT: [[_TMP19:%.*]] = alloca i32, align 4 330 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_22:%.*]] = alloca i32, align 4 331 // CHECK1-NEXT: [[A_CASTED23:%.*]] = alloca i64, align 8 332 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED25:%.*]] = alloca i64, align 8 333 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS29:%.*]] = alloca [10 x i8*], align 8 334 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS30:%.*]] = alloca [10 x i8*], align 8 335 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS31:%.*]] = alloca [10 x i8*], align 8 336 // CHECK1-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 8 337 // CHECK1-NEXT: [[_TMP32:%.*]] = alloca i32, align 4 338 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) 339 // CHECK1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 340 // CHECK1-NEXT: store i32 0, i32* [[A]], align 4 341 // CHECK1-NEXT: store i16 0, i16* [[AA]], align 2 342 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 343 // CHECK1-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 344 // CHECK1-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() 345 // CHECK1-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 346 // CHECK1-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP2]], align 4 347 // CHECK1-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 348 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 349 // CHECK1-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64 350 // CHECK1-NEXT: [[TMP6:%.*]] = mul nuw i64 5, [[TMP5]] 351 // CHECK1-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP6]], align 8 352 // CHECK1-NEXT: store i64 [[TMP5]], i64* [[__VLA_EXPR1]], align 8 353 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 354 // CHECK1-NEXT: store i32 [[TMP7]], i32* [[DOTCAPTURE_EXPR_]], align 4 355 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 356 // CHECK1-NEXT: store i32 [[TMP8]], i32* [[DOTCAPTURE_EXPR_2]], align 4 357 // CHECK1-NEXT: [[TMP9:%.*]] = load i16, i16* [[AA]], align 2 358 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 359 // CHECK1-NEXT: store i16 [[TMP9]], i16* [[CONV]], align 2 360 // CHECK1-NEXT: [[TMP10:%.*]] = load i64, i64* [[AA_CASTED]], align 8 361 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 362 // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* 363 // CHECK1-NEXT: store i32 [[TMP11]], i32* [[CONV3]], align 4 364 // CHECK1-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 365 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 366 // CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED4]] to i32* 367 // CHECK1-NEXT: store i32 [[TMP13]], i32* [[CONV5]], align 4 368 // CHECK1-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED4]], align 8 369 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 370 // CHECK1-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i64* 371 // CHECK1-NEXT: store i64 [[TMP10]], i64* [[TMP16]], align 8 372 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 373 // CHECK1-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64* 374 // CHECK1-NEXT: store i64 [[TMP10]], i64* [[TMP18]], align 8 375 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 376 // CHECK1-NEXT: store i8* null, i8** [[TMP19]], align 8 377 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 378 // CHECK1-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i64* 379 // CHECK1-NEXT: store i64 [[TMP12]], i64* [[TMP21]], align 8 380 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 381 // CHECK1-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i64* 382 // CHECK1-NEXT: store i64 [[TMP12]], i64* [[TMP23]], align 8 383 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 384 // CHECK1-NEXT: store i8* null, i8** [[TMP24]], align 8 385 // CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 386 // CHECK1-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i64* 387 // CHECK1-NEXT: store i64 [[TMP14]], i64* [[TMP26]], align 8 388 // CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 389 // CHECK1-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i64* 390 // CHECK1-NEXT: store i64 [[TMP14]], i64* [[TMP28]], align 8 391 // CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 392 // CHECK1-NEXT: store i8* null, i8** [[TMP29]], align 8 393 // CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 394 // CHECK1-NEXT: [[TMP31:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 395 // CHECK1-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 0 396 // CHECK1-NEXT: [[TMP33:%.*]] = load i16, i16* [[AA]], align 2 397 // CHECK1-NEXT: store i16 [[TMP33]], i16* [[TMP32]], align 4 398 // CHECK1-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 1 399 // CHECK1-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 400 // CHECK1-NEXT: store i32 [[TMP35]], i32* [[TMP34]], align 4 401 // CHECK1-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 2 402 // CHECK1-NEXT: [[TMP37:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 403 // CHECK1-NEXT: store i32 [[TMP37]], i32* [[TMP36]], align 4 404 // CHECK1-NEXT: [[TMP38:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 1, i64 120, i64 12, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1) 405 // CHECK1-NEXT: [[TMP39:%.*]] = bitcast i8* [[TMP38]] to %struct.kmp_task_t_with_privates* 406 // CHECK1-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP39]], i32 0, i32 0 407 // CHECK1-NEXT: [[TMP41:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP40]], i32 0, i32 0 408 // CHECK1-NEXT: [[TMP42:%.*]] = load i8*, i8** [[TMP41]], align 8 409 // CHECK1-NEXT: [[TMP43:%.*]] = bitcast %struct.anon* [[AGG_CAPTURED]] to i8* 410 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP42]], i8* align 4 [[TMP43]], i64 12, i1 false) 411 // CHECK1-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP39]], i32 0, i32 1 412 // CHECK1-NEXT: [[TMP45:%.*]] = bitcast i8* [[TMP42]] to %struct.anon* 413 // CHECK1-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 0 414 // CHECK1-NEXT: [[TMP47:%.*]] = bitcast [3 x i8*]* [[TMP46]] to i8* 415 // CHECK1-NEXT: [[TMP48:%.*]] = bitcast i8** [[TMP30]] to i8* 416 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP47]], i8* align 8 [[TMP48]], i64 24, i1 false) 417 // CHECK1-NEXT: [[TMP49:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 1 418 // CHECK1-NEXT: [[TMP50:%.*]] = bitcast [3 x i8*]* [[TMP49]] to i8* 419 // CHECK1-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP31]] to i8* 420 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP50]], i8* align 8 [[TMP51]], i64 24, i1 false) 421 // CHECK1-NEXT: [[TMP52:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 2 422 // CHECK1-NEXT: [[TMP53:%.*]] = bitcast [3 x i64]* [[TMP52]] to i8* 423 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP53]], i8* align 8 bitcast ([3 x i64]* @.offload_sizes to i8*), i64 24, i1 false) 424 // CHECK1-NEXT: [[TMP54:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 3 425 // CHECK1-NEXT: [[TMP55:%.*]] = load i16, i16* [[AA]], align 2 426 // CHECK1-NEXT: store i16 [[TMP55]], i16* [[TMP54]], align 8 427 // CHECK1-NEXT: [[TMP56:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i8* [[TMP38]]) 428 // CHECK1-NEXT: [[TMP57:%.*]] = load i32, i32* [[A]], align 4 429 // CHECK1-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32* 430 // CHECK1-NEXT: store i32 [[TMP57]], i32* [[CONV6]], align 4 431 // CHECK1-NEXT: [[TMP58:%.*]] = load i64, i64* [[A_CASTED]], align 8 432 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l107(i64 [[TMP58]]) #[[ATTR3:[0-9]+]] 433 // CHECK1-NEXT: [[TMP59:%.*]] = load i16, i16* [[AA]], align 2 434 // CHECK1-NEXT: [[CONV8:%.*]] = bitcast i64* [[AA_CASTED7]] to i16* 435 // CHECK1-NEXT: store i16 [[TMP59]], i16* [[CONV8]], align 2 436 // CHECK1-NEXT: [[TMP60:%.*]] = load i64, i64* [[AA_CASTED7]], align 8 437 // CHECK1-NEXT: [[TMP61:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS9]], i32 0, i32 0 438 // CHECK1-NEXT: [[TMP62:%.*]] = bitcast i8** [[TMP61]] to i64* 439 // CHECK1-NEXT: store i64 [[TMP60]], i64* [[TMP62]], align 8 440 // CHECK1-NEXT: [[TMP63:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS10]], i32 0, i32 0 441 // CHECK1-NEXT: [[TMP64:%.*]] = bitcast i8** [[TMP63]] to i64* 442 // CHECK1-NEXT: store i64 [[TMP60]], i64* [[TMP64]], align 8 443 // CHECK1-NEXT: [[TMP65:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS11]], i64 0, i64 0 444 // CHECK1-NEXT: store i8* null, i8** [[TMP65]], align 8 445 // CHECK1-NEXT: [[TMP66:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS9]], i32 0, i32 0 446 // CHECK1-NEXT: [[TMP67:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS10]], i32 0, i32 0 447 // CHECK1-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) 448 // CHECK1-NEXT: [[TMP68:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113.region_id, i32 1, i8** [[TMP66]], i8** [[TMP67]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.4, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.5, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 449 // CHECK1-NEXT: [[TMP69:%.*]] = icmp ne i32 [[TMP68]], 0 450 // CHECK1-NEXT: br i1 [[TMP69]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 451 // CHECK1: omp_offload.failed: 452 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113(i64 [[TMP60]]) #[[ATTR3]] 453 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 454 // CHECK1: omp_offload.cont: 455 // CHECK1-NEXT: [[TMP70:%.*]] = load i32, i32* [[A]], align 4 456 // CHECK1-NEXT: [[CONV13:%.*]] = bitcast i64* [[A_CASTED12]] to i32* 457 // CHECK1-NEXT: store i32 [[TMP70]], i32* [[CONV13]], align 4 458 // CHECK1-NEXT: [[TMP71:%.*]] = load i64, i64* [[A_CASTED12]], align 8 459 // CHECK1-NEXT: [[TMP72:%.*]] = load i16, i16* [[AA]], align 2 460 // CHECK1-NEXT: [[CONV15:%.*]] = bitcast i64* [[AA_CASTED14]] to i16* 461 // CHECK1-NEXT: store i16 [[TMP72]], i16* [[CONV15]], align 2 462 // CHECK1-NEXT: [[TMP73:%.*]] = load i64, i64* [[AA_CASTED14]], align 8 463 // CHECK1-NEXT: [[TMP74:%.*]] = load i32, i32* [[N_ADDR]], align 4 464 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP74]], 10 465 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 466 // CHECK1: omp_if.then: 467 // CHECK1-NEXT: [[TMP75:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 0 468 // CHECK1-NEXT: [[TMP76:%.*]] = bitcast i8** [[TMP75]] to i64* 469 // CHECK1-NEXT: store i64 [[TMP71]], i64* [[TMP76]], align 8 470 // CHECK1-NEXT: [[TMP77:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 0 471 // CHECK1-NEXT: [[TMP78:%.*]] = bitcast i8** [[TMP77]] to i64* 472 // CHECK1-NEXT: store i64 [[TMP71]], i64* [[TMP78]], align 8 473 // CHECK1-NEXT: [[TMP79:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 0 474 // CHECK1-NEXT: store i8* null, i8** [[TMP79]], align 8 475 // CHECK1-NEXT: [[TMP80:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 1 476 // CHECK1-NEXT: [[TMP81:%.*]] = bitcast i8** [[TMP80]] to i64* 477 // CHECK1-NEXT: store i64 [[TMP73]], i64* [[TMP81]], align 8 478 // CHECK1-NEXT: [[TMP82:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 1 479 // CHECK1-NEXT: [[TMP83:%.*]] = bitcast i8** [[TMP82]] to i64* 480 // CHECK1-NEXT: store i64 [[TMP73]], i64* [[TMP83]], align 8 481 // CHECK1-NEXT: [[TMP84:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 1 482 // CHECK1-NEXT: store i8* null, i8** [[TMP84]], align 8 483 // CHECK1-NEXT: [[TMP85:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 0 484 // CHECK1-NEXT: [[TMP86:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 0 485 // CHECK1-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) 486 // CHECK1-NEXT: [[TMP87:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120.region_id, i32 2, i8** [[TMP85]], i8** [[TMP86]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.7, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.8, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 487 // CHECK1-NEXT: [[TMP88:%.*]] = icmp ne i32 [[TMP87]], 0 488 // CHECK1-NEXT: br i1 [[TMP88]], label [[OMP_OFFLOAD_FAILED20:%.*]], label [[OMP_OFFLOAD_CONT21:%.*]] 489 // CHECK1: omp_offload.failed20: 490 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120(i64 [[TMP71]], i64 [[TMP73]]) #[[ATTR3]] 491 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT21]] 492 // CHECK1: omp_offload.cont21: 493 // CHECK1-NEXT: br label [[OMP_IF_END:%.*]] 494 // CHECK1: omp_if.else: 495 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120(i64 [[TMP71]], i64 [[TMP73]]) #[[ATTR3]] 496 // CHECK1-NEXT: br label [[OMP_IF_END]] 497 // CHECK1: omp_if.end: 498 // CHECK1-NEXT: [[TMP89:%.*]] = load i32, i32* [[N_ADDR]], align 4 499 // CHECK1-NEXT: store i32 [[TMP89]], i32* [[DOTCAPTURE_EXPR_22]], align 4 500 // CHECK1-NEXT: [[TMP90:%.*]] = load i32, i32* [[A]], align 4 501 // CHECK1-NEXT: [[CONV24:%.*]] = bitcast i64* [[A_CASTED23]] to i32* 502 // CHECK1-NEXT: store i32 [[TMP90]], i32* [[CONV24]], align 4 503 // CHECK1-NEXT: [[TMP91:%.*]] = load i64, i64* [[A_CASTED23]], align 8 504 // CHECK1-NEXT: [[TMP92:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_22]], align 4 505 // CHECK1-NEXT: [[CONV26:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED25]] to i32* 506 // CHECK1-NEXT: store i32 [[TMP92]], i32* [[CONV26]], align 4 507 // CHECK1-NEXT: [[TMP93:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED25]], align 8 508 // CHECK1-NEXT: [[TMP94:%.*]] = load i32, i32* [[N_ADDR]], align 4 509 // CHECK1-NEXT: [[CMP27:%.*]] = icmp sgt i32 [[TMP94]], 20 510 // CHECK1-NEXT: br i1 [[CMP27]], label [[OMP_IF_THEN28:%.*]], label [[OMP_IF_ELSE35:%.*]] 511 // CHECK1: omp_if.then28: 512 // CHECK1-NEXT: [[TMP95:%.*]] = mul nuw i64 [[TMP2]], 4 513 // CHECK1-NEXT: [[TMP96:%.*]] = mul nuw i64 5, [[TMP5]] 514 // CHECK1-NEXT: [[TMP97:%.*]] = mul nuw i64 [[TMP96]], 8 515 // CHECK1-NEXT: [[TMP98:%.*]] = bitcast [10 x i64]* [[DOTOFFLOAD_SIZES]] to i8* 516 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP98]], i8* align 8 bitcast ([10 x i64]* @.offload_sizes.10 to i8*), i64 80, i1 false) 517 // CHECK1-NEXT: [[TMP99:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS29]], i32 0, i32 0 518 // CHECK1-NEXT: [[TMP100:%.*]] = bitcast i8** [[TMP99]] to i64* 519 // CHECK1-NEXT: store i64 [[TMP91]], i64* [[TMP100]], align 8 520 // CHECK1-NEXT: [[TMP101:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS30]], i32 0, i32 0 521 // CHECK1-NEXT: [[TMP102:%.*]] = bitcast i8** [[TMP101]] to i64* 522 // CHECK1-NEXT: store i64 [[TMP91]], i64* [[TMP102]], align 8 523 // CHECK1-NEXT: [[TMP103:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS31]], i64 0, i64 0 524 // CHECK1-NEXT: store i8* null, i8** [[TMP103]], align 8 525 // CHECK1-NEXT: [[TMP104:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS29]], i32 0, i32 1 526 // CHECK1-NEXT: [[TMP105:%.*]] = bitcast i8** [[TMP104]] to [10 x float]** 527 // CHECK1-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP105]], align 8 528 // CHECK1-NEXT: [[TMP106:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS30]], i32 0, i32 1 529 // CHECK1-NEXT: [[TMP107:%.*]] = bitcast i8** [[TMP106]] to [10 x float]** 530 // CHECK1-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP107]], align 8 531 // CHECK1-NEXT: [[TMP108:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS31]], i64 0, i64 1 532 // CHECK1-NEXT: store i8* null, i8** [[TMP108]], align 8 533 // CHECK1-NEXT: [[TMP109:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS29]], i32 0, i32 2 534 // CHECK1-NEXT: [[TMP110:%.*]] = bitcast i8** [[TMP109]] to i64* 535 // CHECK1-NEXT: store i64 [[TMP2]], i64* [[TMP110]], align 8 536 // CHECK1-NEXT: [[TMP111:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS30]], i32 0, i32 2 537 // CHECK1-NEXT: [[TMP112:%.*]] = bitcast i8** [[TMP111]] to i64* 538 // CHECK1-NEXT: store i64 [[TMP2]], i64* [[TMP112]], align 8 539 // CHECK1-NEXT: [[TMP113:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS31]], i64 0, i64 2 540 // CHECK1-NEXT: store i8* null, i8** [[TMP113]], align 8 541 // CHECK1-NEXT: [[TMP114:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS29]], i32 0, i32 3 542 // CHECK1-NEXT: [[TMP115:%.*]] = bitcast i8** [[TMP114]] to float** 543 // CHECK1-NEXT: store float* [[VLA]], float** [[TMP115]], align 8 544 // CHECK1-NEXT: [[TMP116:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS30]], i32 0, i32 3 545 // CHECK1-NEXT: [[TMP117:%.*]] = bitcast i8** [[TMP116]] to float** 546 // CHECK1-NEXT: store float* [[VLA]], float** [[TMP117]], align 8 547 // CHECK1-NEXT: [[TMP118:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 548 // CHECK1-NEXT: store i64 [[TMP95]], i64* [[TMP118]], align 8 549 // CHECK1-NEXT: [[TMP119:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS31]], i64 0, i64 3 550 // CHECK1-NEXT: store i8* null, i8** [[TMP119]], align 8 551 // CHECK1-NEXT: [[TMP120:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS29]], i32 0, i32 4 552 // CHECK1-NEXT: [[TMP121:%.*]] = bitcast i8** [[TMP120]] to [5 x [10 x double]]** 553 // CHECK1-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP121]], align 8 554 // CHECK1-NEXT: [[TMP122:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS30]], i32 0, i32 4 555 // CHECK1-NEXT: [[TMP123:%.*]] = bitcast i8** [[TMP122]] to [5 x [10 x double]]** 556 // CHECK1-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP123]], align 8 557 // CHECK1-NEXT: [[TMP124:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS31]], i64 0, i64 4 558 // CHECK1-NEXT: store i8* null, i8** [[TMP124]], align 8 559 // CHECK1-NEXT: [[TMP125:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS29]], i32 0, i32 5 560 // CHECK1-NEXT: [[TMP126:%.*]] = bitcast i8** [[TMP125]] to i64* 561 // CHECK1-NEXT: store i64 5, i64* [[TMP126]], align 8 562 // CHECK1-NEXT: [[TMP127:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS30]], i32 0, i32 5 563 // CHECK1-NEXT: [[TMP128:%.*]] = bitcast i8** [[TMP127]] to i64* 564 // CHECK1-NEXT: store i64 5, i64* [[TMP128]], align 8 565 // CHECK1-NEXT: [[TMP129:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS31]], i64 0, i64 5 566 // CHECK1-NEXT: store i8* null, i8** [[TMP129]], align 8 567 // CHECK1-NEXT: [[TMP130:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS29]], i32 0, i32 6 568 // CHECK1-NEXT: [[TMP131:%.*]] = bitcast i8** [[TMP130]] to i64* 569 // CHECK1-NEXT: store i64 [[TMP5]], i64* [[TMP131]], align 8 570 // CHECK1-NEXT: [[TMP132:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS30]], i32 0, i32 6 571 // CHECK1-NEXT: [[TMP133:%.*]] = bitcast i8** [[TMP132]] to i64* 572 // CHECK1-NEXT: store i64 [[TMP5]], i64* [[TMP133]], align 8 573 // CHECK1-NEXT: [[TMP134:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS31]], i64 0, i64 6 574 // CHECK1-NEXT: store i8* null, i8** [[TMP134]], align 8 575 // CHECK1-NEXT: [[TMP135:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS29]], i32 0, i32 7 576 // CHECK1-NEXT: [[TMP136:%.*]] = bitcast i8** [[TMP135]] to double** 577 // CHECK1-NEXT: store double* [[VLA1]], double** [[TMP136]], align 8 578 // CHECK1-NEXT: [[TMP137:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS30]], i32 0, i32 7 579 // CHECK1-NEXT: [[TMP138:%.*]] = bitcast i8** [[TMP137]] to double** 580 // CHECK1-NEXT: store double* [[VLA1]], double** [[TMP138]], align 8 581 // CHECK1-NEXT: [[TMP139:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 582 // CHECK1-NEXT: store i64 [[TMP97]], i64* [[TMP139]], align 8 583 // CHECK1-NEXT: [[TMP140:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS31]], i64 0, i64 7 584 // CHECK1-NEXT: store i8* null, i8** [[TMP140]], align 8 585 // CHECK1-NEXT: [[TMP141:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS29]], i32 0, i32 8 586 // CHECK1-NEXT: [[TMP142:%.*]] = bitcast i8** [[TMP141]] to %struct.TT** 587 // CHECK1-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP142]], align 8 588 // CHECK1-NEXT: [[TMP143:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS30]], i32 0, i32 8 589 // CHECK1-NEXT: [[TMP144:%.*]] = bitcast i8** [[TMP143]] to %struct.TT** 590 // CHECK1-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP144]], align 8 591 // CHECK1-NEXT: [[TMP145:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS31]], i64 0, i64 8 592 // CHECK1-NEXT: store i8* null, i8** [[TMP145]], align 8 593 // CHECK1-NEXT: [[TMP146:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS29]], i32 0, i32 9 594 // CHECK1-NEXT: [[TMP147:%.*]] = bitcast i8** [[TMP146]] to i64* 595 // CHECK1-NEXT: store i64 [[TMP93]], i64* [[TMP147]], align 8 596 // CHECK1-NEXT: [[TMP148:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS30]], i32 0, i32 9 597 // CHECK1-NEXT: [[TMP149:%.*]] = bitcast i8** [[TMP148]] to i64* 598 // CHECK1-NEXT: store i64 [[TMP93]], i64* [[TMP149]], align 8 599 // CHECK1-NEXT: [[TMP150:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS31]], i64 0, i64 9 600 // CHECK1-NEXT: store i8* null, i8** [[TMP150]], align 8 601 // CHECK1-NEXT: [[TMP151:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS29]], i32 0, i32 0 602 // CHECK1-NEXT: [[TMP152:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS30]], i32 0, i32 0 603 // CHECK1-NEXT: [[TMP153:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 604 // CHECK1-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) 605 // CHECK1-NEXT: [[TMP154:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145.region_id, i32 10, i8** [[TMP151]], i8** [[TMP152]], i64* [[TMP153]], i64* getelementptr inbounds ([10 x i64], [10 x i64]* @.offload_maptypes.11, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 606 // CHECK1-NEXT: [[TMP155:%.*]] = icmp ne i32 [[TMP154]], 0 607 // CHECK1-NEXT: br i1 [[TMP155]], label [[OMP_OFFLOAD_FAILED33:%.*]], label [[OMP_OFFLOAD_CONT34:%.*]] 608 // CHECK1: omp_offload.failed33: 609 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145(i64 [[TMP91]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]], i64 [[TMP93]]) #[[ATTR3]] 610 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT34]] 611 // CHECK1: omp_offload.cont34: 612 // CHECK1-NEXT: br label [[OMP_IF_END36:%.*]] 613 // CHECK1: omp_if.else35: 614 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145(i64 [[TMP91]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]], i64 [[TMP93]]) #[[ATTR3]] 615 // CHECK1-NEXT: br label [[OMP_IF_END36]] 616 // CHECK1: omp_if.end36: 617 // CHECK1-NEXT: [[TMP156:%.*]] = load i32, i32* [[A]], align 4 618 // CHECK1-NEXT: [[TMP157:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 619 // CHECK1-NEXT: call void @llvm.stackrestore(i8* [[TMP157]]) 620 // CHECK1-NEXT: ret i32 [[TMP156]] 621 // 622 // 623 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103 624 // CHECK1-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] { 625 // CHECK1-NEXT: entry: 626 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 627 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 628 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8 629 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 630 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]]) 631 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 632 // CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 633 // CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8 634 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 635 // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* 636 // CHECK1-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32* 637 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 4 638 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 4 639 // CHECK1-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) 640 // CHECK1-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 641 // CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 642 // CHECK1-NEXT: store i16 [[TMP3]], i16* [[CONV5]], align 2 643 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 644 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]]) 645 // CHECK1-NEXT: ret void 646 // 647 // 648 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. 649 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { 650 // CHECK1-NEXT: entry: 651 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 652 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 653 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 654 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 655 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 656 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 657 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 658 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 659 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 660 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 661 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 662 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 663 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 664 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 665 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 666 // CHECK1-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 667 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 668 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 669 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 670 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 671 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 672 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 673 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 674 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 675 // CHECK1: cond.true: 676 // CHECK1-NEXT: br label [[COND_END:%.*]] 677 // CHECK1: cond.false: 678 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 679 // CHECK1-NEXT: br label [[COND_END]] 680 // CHECK1: cond.end: 681 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 682 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 683 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 684 // CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 685 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 686 // CHECK1: omp.inner.for.cond: 687 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 688 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 689 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 690 // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 691 // CHECK1: omp.inner.for.body: 692 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 693 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 694 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 695 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4 696 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 697 // CHECK1: omp.body.continue: 698 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 699 // CHECK1: omp.inner.for.inc: 700 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 701 // CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 702 // CHECK1-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 703 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 704 // CHECK1: omp.inner.for.end: 705 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 706 // CHECK1: omp.loop.exit: 707 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 708 // CHECK1-NEXT: ret void 709 // 710 // 711 // CHECK1-LABEL: define {{[^@]+}}@.omp_task_privates_map. 712 // CHECK1-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], i16** noalias noundef [[TMP1:%.*]], [3 x i8*]** noalias noundef [[TMP2:%.*]], [3 x i8*]** noalias noundef [[TMP3:%.*]], [3 x i64]** noalias noundef [[TMP4:%.*]]) #[[ATTR4:[0-9]+]] { 713 // CHECK1-NEXT: entry: 714 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 8 715 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i16**, align 8 716 // CHECK1-NEXT: [[DOTADDR2:%.*]] = alloca [3 x i8*]**, align 8 717 // CHECK1-NEXT: [[DOTADDR3:%.*]] = alloca [3 x i8*]**, align 8 718 // CHECK1-NEXT: [[DOTADDR4:%.*]] = alloca [3 x i64]**, align 8 719 // CHECK1-NEXT: store %struct..kmp_privates.t* [[TMP0]], %struct..kmp_privates.t** [[DOTADDR]], align 8 720 // CHECK1-NEXT: store i16** [[TMP1]], i16*** [[DOTADDR1]], align 8 721 // CHECK1-NEXT: store [3 x i8*]** [[TMP2]], [3 x i8*]*** [[DOTADDR2]], align 8 722 // CHECK1-NEXT: store [3 x i8*]** [[TMP3]], [3 x i8*]*** [[DOTADDR3]], align 8 723 // CHECK1-NEXT: store [3 x i64]** [[TMP4]], [3 x i64]*** [[DOTADDR4]], align 8 724 // CHECK1-NEXT: [[TMP5:%.*]] = load %struct..kmp_privates.t*, %struct..kmp_privates.t** [[DOTADDR]], align 8 725 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 0 726 // CHECK1-NEXT: [[TMP7:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR2]], align 8 727 // CHECK1-NEXT: store [3 x i8*]* [[TMP6]], [3 x i8*]** [[TMP7]], align 8 728 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 1 729 // CHECK1-NEXT: [[TMP9:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR3]], align 8 730 // CHECK1-NEXT: store [3 x i8*]* [[TMP8]], [3 x i8*]** [[TMP9]], align 8 731 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 2 732 // CHECK1-NEXT: [[TMP11:%.*]] = load [3 x i64]**, [3 x i64]*** [[DOTADDR4]], align 8 733 // CHECK1-NEXT: store [3 x i64]* [[TMP10]], [3 x i64]** [[TMP11]], align 8 734 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 3 735 // CHECK1-NEXT: [[TMP13:%.*]] = load i16**, i16*** [[DOTADDR1]], align 8 736 // CHECK1-NEXT: store i16* [[TMP12]], i16** [[TMP13]], align 8 737 // CHECK1-NEXT: ret void 738 // 739 // 740 // CHECK1-LABEL: define {{[^@]+}}@.omp_task_entry. 741 // CHECK1-SAME: (i32 noundef signext [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { 742 // CHECK1-NEXT: entry: 743 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 744 // CHECK1-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 745 // CHECK1-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8 746 // CHECK1-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8 747 // CHECK1-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8 748 // CHECK1-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 8 749 // CHECK1-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca i16*, align 8 750 // CHECK1-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca [3 x i8*]*, align 8 751 // CHECK1-NEXT: [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca [3 x i8*]*, align 8 752 // CHECK1-NEXT: [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca [3 x i64]*, align 8 753 // CHECK1-NEXT: [[AA_CASTED_I:%.*]] = alloca i64, align 8 754 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED_I:%.*]] = alloca i64, align 8 755 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED5_I:%.*]] = alloca i64, align 8 756 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 757 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8 758 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 759 // CHECK1-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 760 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 761 // CHECK1-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 762 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0 763 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 764 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 765 // CHECK1-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 766 // CHECK1-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon* 767 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1 768 // CHECK1-NEXT: [[TMP10:%.*]] = bitcast %struct..kmp_privates.t* [[TMP9]] to i8* 769 // CHECK1-NEXT: [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8* 770 // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META12:![0-9]+]]) 771 // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]]) 772 // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META17:![0-9]+]]) 773 // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]]) 774 // CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !21 775 // CHECK1-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !21 776 // CHECK1-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !21 777 // CHECK1-NEXT: store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* @.omp_task_privates_map. to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !21 778 // CHECK1-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !21 779 // CHECK1-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !21 780 // CHECK1-NEXT: [[TMP12:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !21 781 // CHECK1-NEXT: [[TMP13:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !21 782 // CHECK1-NEXT: [[TMP14:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !21 783 // CHECK1-NEXT: [[TMP15:%.*]] = bitcast void (i8*, ...)* [[TMP13]] to void (i8*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* 784 // CHECK1-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]] 785 // CHECK1-NEXT: [[TMP16:%.*]] = load i16*, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !21 786 // CHECK1-NEXT: [[TMP17:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !21 787 // CHECK1-NEXT: [[TMP18:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 8, !noalias !21 788 // CHECK1-NEXT: [[TMP19:%.*]] = load [3 x i64]*, [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 8, !noalias !21 789 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP17]], i64 0, i64 0 790 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP18]], i64 0, i64 0 791 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[TMP19]], i64 0, i64 0 792 // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP12]], i32 0, i32 1 793 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[TMP12]], i32 0, i32 2 794 // CHECK1-NEXT: [[TMP25:%.*]] = load i32, i32* [[TMP23]], align 4 795 // CHECK1-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP24]], align 4 796 // CHECK1-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) #[[ATTR3]] 797 // CHECK1-NEXT: [[TMP27:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 [[TMP25]], i32 [[TMP26]], i32 0, i8* null, i32 0, i8* null) #[[ATTR3]] 798 // CHECK1-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0 799 // CHECK1-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]] 800 // CHECK1: omp_offload.failed.i: 801 // CHECK1-NEXT: [[TMP29:%.*]] = load i16, i16* [[TMP16]], align 2 802 // CHECK1-NEXT: [[CONV_I:%.*]] = bitcast i64* [[AA_CASTED_I]] to i16* 803 // CHECK1-NEXT: store i16 [[TMP29]], i16* [[CONV_I]], align 2, !noalias !21 804 // CHECK1-NEXT: [[TMP30:%.*]] = load i64, i64* [[AA_CASTED_I]], align 8, !noalias !21 805 // CHECK1-NEXT: [[TMP31:%.*]] = load i32, i32* [[TMP23]], align 4 806 // CHECK1-NEXT: [[CONV4_I:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED_I]] to i32* 807 // CHECK1-NEXT: store i32 [[TMP31]], i32* [[CONV4_I]], align 4, !noalias !21 808 // CHECK1-NEXT: [[TMP32:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED_I]], align 8, !noalias !21 809 // CHECK1-NEXT: [[TMP33:%.*]] = load i32, i32* [[TMP24]], align 4 810 // CHECK1-NEXT: [[CONV6_I:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED5_I]] to i32* 811 // CHECK1-NEXT: store i32 [[TMP33]], i32* [[CONV6_I]], align 4, !noalias !21 812 // CHECK1-NEXT: [[TMP34:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED5_I]], align 8, !noalias !21 813 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103(i64 [[TMP30]], i64 [[TMP32]], i64 [[TMP34]]) #[[ATTR3]] 814 // CHECK1-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]] 815 // CHECK1: .omp_outlined..1.exit: 816 // CHECK1-NEXT: ret i32 0 817 // 818 // 819 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l107 820 // CHECK1-SAME: (i64 noundef [[A:%.*]]) #[[ATTR2]] { 821 // CHECK1-NEXT: entry: 822 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 823 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 824 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 825 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 826 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 827 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32* 828 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 829 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 830 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]]) 831 // CHECK1-NEXT: ret void 832 // 833 // 834 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..2 835 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]]) #[[ATTR2]] { 836 // CHECK1-NEXT: entry: 837 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 838 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 839 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 840 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 841 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 842 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 843 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 844 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 845 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 846 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 847 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 848 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 849 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 850 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 851 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 852 // CHECK1-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 853 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 854 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 855 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 856 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 857 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 858 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 859 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 860 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 861 // CHECK1: cond.true: 862 // CHECK1-NEXT: br label [[COND_END:%.*]] 863 // CHECK1: cond.false: 864 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 865 // CHECK1-NEXT: br label [[COND_END]] 866 // CHECK1: cond.end: 867 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 868 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 869 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 870 // CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 871 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 872 // CHECK1: omp.inner.for.cond: 873 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 874 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 875 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 876 // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 877 // CHECK1: omp.inner.for.body: 878 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 879 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 880 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 881 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4 882 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 883 // CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 884 // CHECK1-NEXT: store i32 [[ADD2]], i32* [[CONV]], align 4 885 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 886 // CHECK1: omp.body.continue: 887 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 888 // CHECK1: omp.inner.for.inc: 889 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 890 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1 891 // CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 892 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 893 // CHECK1: omp.inner.for.end: 894 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 895 // CHECK1: omp.loop.exit: 896 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 897 // CHECK1-NEXT: ret void 898 // 899 // 900 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113 901 // CHECK1-SAME: (i64 noundef [[AA:%.*]]) #[[ATTR2]] { 902 // CHECK1-NEXT: entry: 903 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 904 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 905 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 906 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 907 // CHECK1-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 908 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 909 // CHECK1-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 910 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 911 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP1]]) 912 // CHECK1-NEXT: ret void 913 // 914 // 915 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..3 916 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { 917 // CHECK1-NEXT: entry: 918 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 919 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 920 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 921 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 922 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 923 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 924 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 925 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 926 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 927 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 928 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 929 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 930 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 931 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 932 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 933 // CHECK1-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 934 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 935 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 936 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 937 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 938 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 939 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 940 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 941 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 942 // CHECK1: cond.true: 943 // CHECK1-NEXT: br label [[COND_END:%.*]] 944 // CHECK1: cond.false: 945 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 946 // CHECK1-NEXT: br label [[COND_END]] 947 // CHECK1: cond.end: 948 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 949 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 950 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 951 // CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 952 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 953 // CHECK1: omp.inner.for.cond: 954 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 955 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 956 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 957 // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 958 // CHECK1: omp.inner.for.body: 959 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 960 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 961 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 962 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4 963 // CHECK1-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 2 964 // CHECK1-NEXT: [[CONV2:%.*]] = sext i16 [[TMP8]] to i32 965 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 966 // CHECK1-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 967 // CHECK1-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2 968 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 969 // CHECK1: omp.body.continue: 970 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 971 // CHECK1: omp.inner.for.inc: 972 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 973 // CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP9]], 1 974 // CHECK1-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 975 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 976 // CHECK1: omp.inner.for.end: 977 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 978 // CHECK1: omp.loop.exit: 979 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 980 // CHECK1-NEXT: ret void 981 // 982 // 983 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120 984 // CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { 985 // CHECK1-NEXT: entry: 986 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 987 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 988 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 989 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 990 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 991 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 992 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 993 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 994 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 995 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* 996 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 997 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 998 // CHECK1-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 999 // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 1000 // CHECK1-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 1001 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 1002 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) 1003 // CHECK1-NEXT: ret void 1004 // 1005 // 1006 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..6 1007 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { 1008 // CHECK1-NEXT: entry: 1009 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1010 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1011 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1012 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 1013 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1014 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 1015 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1016 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1017 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1018 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1019 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 1020 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1021 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1022 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 1023 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 1024 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 1025 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 1026 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1027 // CHECK1-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 1028 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 1029 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1030 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 1031 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 1032 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 1033 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1034 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 1035 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1036 // CHECK1: cond.true: 1037 // CHECK1-NEXT: br label [[COND_END:%.*]] 1038 // CHECK1: cond.false: 1039 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1040 // CHECK1-NEXT: br label [[COND_END]] 1041 // CHECK1: cond.end: 1042 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 1043 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 1044 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1045 // CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 1046 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1047 // CHECK1: omp.inner.for.cond: 1048 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1049 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1050 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 1051 // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1052 // CHECK1: omp.inner.for.body: 1053 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1054 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 1055 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1056 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4 1057 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 1058 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1 1059 // CHECK1-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4 1060 // CHECK1-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 2 1061 // CHECK1-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32 1062 // CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 1063 // CHECK1-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 1064 // CHECK1-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2 1065 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1066 // CHECK1: omp.body.continue: 1067 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1068 // CHECK1: omp.inner.for.inc: 1069 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1070 // CHECK1-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1 1071 // CHECK1-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 1072 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 1073 // CHECK1: omp.inner.for.end: 1074 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1075 // CHECK1: omp.loop.exit: 1076 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 1077 // CHECK1-NEXT: ret void 1078 // 1079 // 1080 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145 1081 // CHECK1-SAME: (i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { 1082 // CHECK1-NEXT: entry: 1083 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1084 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 1085 // CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 1086 // CHECK1-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 1087 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 1088 // CHECK1-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 1089 // CHECK1-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 1090 // CHECK1-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 1091 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 1092 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 1093 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 1094 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 1095 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 1096 // CHECK1-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 1097 // CHECK1-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 1098 // CHECK1-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 1099 // CHECK1-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 1100 // CHECK1-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 1101 // CHECK1-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 1102 // CHECK1-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 1103 // CHECK1-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 1104 // CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 1105 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 1106 // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 1107 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 1108 // CHECK1-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 1109 // CHECK1-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 1110 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 1111 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 1112 // CHECK1-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 1113 // CHECK1-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 1114 // CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* 1115 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 1116 // CHECK1-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32* 1117 // CHECK1-NEXT: store i32 [[TMP8]], i32* [[CONV6]], align 4 1118 // CHECK1-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 1119 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 4 1120 // CHECK1-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* 1121 // CHECK1-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4 1122 // CHECK1-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 1123 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]]) 1124 // CHECK1-NEXT: ret void 1125 // 1126 // 1127 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..9 1128 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { 1129 // CHECK1-NEXT: entry: 1130 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1131 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1132 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1133 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 1134 // CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 1135 // CHECK1-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 1136 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 1137 // CHECK1-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 1138 // CHECK1-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 1139 // CHECK1-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 1140 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 1141 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 1142 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1143 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 1144 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1145 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1146 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1147 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1148 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 1149 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1150 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1151 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 1152 // CHECK1-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 1153 // CHECK1-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 1154 // CHECK1-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 1155 // CHECK1-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 1156 // CHECK1-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 1157 // CHECK1-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 1158 // CHECK1-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 1159 // CHECK1-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 1160 // CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 1161 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 1162 // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 1163 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 1164 // CHECK1-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 1165 // CHECK1-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 1166 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 1167 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 1168 // CHECK1-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 1169 // CHECK1-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 1170 // CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* 1171 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1172 // CHECK1-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 1173 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 1174 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1175 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 4 1176 // CHECK1-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 1177 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 1178 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) 1179 // CHECK1-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 1180 // CHECK1: omp.dispatch.cond: 1181 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1182 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 9 1183 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1184 // CHECK1: cond.true: 1185 // CHECK1-NEXT: br label [[COND_END:%.*]] 1186 // CHECK1: cond.false: 1187 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1188 // CHECK1-NEXT: br label [[COND_END]] 1189 // CHECK1: cond.end: 1190 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] 1191 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 1192 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1193 // CHECK1-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 1194 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1195 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1196 // CHECK1-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] 1197 // CHECK1-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 1198 // CHECK1: omp.dispatch.body: 1199 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1200 // CHECK1: omp.inner.for.cond: 1201 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 1202 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !22 1203 // CHECK1-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] 1204 // CHECK1-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1205 // CHECK1: omp.inner.for.body: 1206 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 1207 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 1208 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1209 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !22 1210 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !22 1211 // CHECK1-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP19]], 1 1212 // CHECK1-NEXT: store i32 [[ADD8]], i32* [[CONV]], align 4, !llvm.access.group !22 1213 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 1214 // CHECK1-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !22 1215 // CHECK1-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double 1216 // CHECK1-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 1217 // CHECK1-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float 1218 // CHECK1-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4, !llvm.access.group !22 1219 // CHECK1-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 1220 // CHECK1-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4, !llvm.access.group !22 1221 // CHECK1-NEXT: [[CONV13:%.*]] = fpext float [[TMP21]] to double 1222 // CHECK1-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00 1223 // CHECK1-NEXT: [[CONV15:%.*]] = fptrunc double [[ADD14]] to float 1224 // CHECK1-NEXT: store float [[CONV15]], float* [[ARRAYIDX12]], align 4, !llvm.access.group !22 1225 // CHECK1-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1 1226 // CHECK1-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i64 0, i64 2 1227 // CHECK1-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX17]], align 8, !llvm.access.group !22 1228 // CHECK1-NEXT: [[ADD18:%.*]] = fadd double [[TMP22]], 1.000000e+00 1229 // CHECK1-NEXT: store double [[ADD18]], double* [[ARRAYIDX17]], align 8, !llvm.access.group !22 1230 // CHECK1-NEXT: [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]] 1231 // CHECK1-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP23]] 1232 // CHECK1-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i64 3 1233 // CHECK1-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX20]], align 8, !llvm.access.group !22 1234 // CHECK1-NEXT: [[ADD21:%.*]] = fadd double [[TMP24]], 1.000000e+00 1235 // CHECK1-NEXT: store double [[ADD21]], double* [[ARRAYIDX20]], align 8, !llvm.access.group !22 1236 // CHECK1-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 1237 // CHECK1-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 8, !llvm.access.group !22 1238 // CHECK1-NEXT: [[ADD22:%.*]] = add nsw i64 [[TMP25]], 1 1239 // CHECK1-NEXT: store i64 [[ADD22]], i64* [[X]], align 8, !llvm.access.group !22 1240 // CHECK1-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 1241 // CHECK1-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 8, !llvm.access.group !22 1242 // CHECK1-NEXT: [[CONV23:%.*]] = sext i8 [[TMP26]] to i32 1243 // CHECK1-NEXT: [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1 1244 // CHECK1-NEXT: [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8 1245 // CHECK1-NEXT: store i8 [[CONV25]], i8* [[Y]], align 8, !llvm.access.group !22 1246 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1247 // CHECK1: omp.body.continue: 1248 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1249 // CHECK1: omp.inner.for.inc: 1250 // CHECK1-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 1251 // CHECK1-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP27]], 1 1252 // CHECK1-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22 1253 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]] 1254 // CHECK1: omp.inner.for.end: 1255 // CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 1256 // CHECK1: omp.dispatch.inc: 1257 // CHECK1-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1258 // CHECK1-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 1259 // CHECK1-NEXT: [[ADD27:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] 1260 // CHECK1-NEXT: store i32 [[ADD27]], i32* [[DOTOMP_LB]], align 4 1261 // CHECK1-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1262 // CHECK1-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 1263 // CHECK1-NEXT: [[ADD28:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] 1264 // CHECK1-NEXT: store i32 [[ADD28]], i32* [[DOTOMP_UB]], align 4 1265 // CHECK1-NEXT: br label [[OMP_DISPATCH_COND]] 1266 // CHECK1: omp.dispatch.end: 1267 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]]) 1268 // CHECK1-NEXT: ret void 1269 // 1270 // 1271 // CHECK1-LABEL: define {{[^@]+}}@_Z3bari 1272 // CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { 1273 // CHECK1-NEXT: entry: 1274 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 1275 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4 1276 // CHECK1-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 1277 // CHECK1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 1278 // CHECK1-NEXT: store i32 0, i32* [[A]], align 4 1279 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 1280 // CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]]) 1281 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 1282 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 1283 // CHECK1-NEXT: store i32 [[ADD]], i32* [[A]], align 4 1284 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 1285 // CHECK1-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP2]]) 1286 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 1287 // CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 1288 // CHECK1-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 1289 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 1290 // CHECK1-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]]) 1291 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 1292 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 1293 // CHECK1-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 1294 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 1295 // CHECK1-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]]) 1296 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 1297 // CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] 1298 // CHECK1-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 1299 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 1300 // CHECK1-NEXT: ret i32 [[TMP8]] 1301 // 1302 // 1303 // CHECK1-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 1304 // CHECK1-SAME: (%struct.S1* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { 1305 // CHECK1-NEXT: entry: 1306 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 1307 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 1308 // CHECK1-NEXT: [[B:%.*]] = alloca i32, align 4 1309 // CHECK1-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 1310 // CHECK1-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 1311 // CHECK1-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 1312 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8 1313 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8 1314 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8 1315 // CHECK1-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 8 1316 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 1317 // CHECK1-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 1318 // CHECK1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 1319 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 1320 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 1321 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 1322 // CHECK1-NEXT: store i32 [[ADD]], i32* [[B]], align 4 1323 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 1324 // CHECK1-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 1325 // CHECK1-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() 1326 // CHECK1-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 1327 // CHECK1-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] 1328 // CHECK1-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 1329 // CHECK1-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 1330 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 1331 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32* 1332 // CHECK1-NEXT: store i32 [[TMP5]], i32* [[CONV]], align 4 1333 // CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 1334 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4 1335 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 60 1336 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 1337 // CHECK1: omp_if.then: 1338 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 1339 // CHECK1-NEXT: [[TMP8:%.*]] = mul nuw i64 2, [[TMP2]] 1340 // CHECK1-NEXT: [[TMP9:%.*]] = mul nuw i64 [[TMP8]], 2 1341 // CHECK1-NEXT: [[TMP10:%.*]] = bitcast [5 x i64]* [[DOTOFFLOAD_SIZES]] to i8* 1342 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP10]], i8* align 8 bitcast ([5 x i64]* @.offload_sizes.13 to i8*), i64 40, i1 false) 1343 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1344 // CHECK1-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to %struct.S1** 1345 // CHECK1-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP12]], align 8 1346 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1347 // CHECK1-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to double** 1348 // CHECK1-NEXT: store double* [[A]], double** [[TMP14]], align 8 1349 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 1350 // CHECK1-NEXT: store i8* null, i8** [[TMP15]], align 8 1351 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1352 // CHECK1-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64* 1353 // CHECK1-NEXT: store i64 [[TMP6]], i64* [[TMP17]], align 8 1354 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1355 // CHECK1-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64* 1356 // CHECK1-NEXT: store i64 [[TMP6]], i64* [[TMP19]], align 8 1357 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 1358 // CHECK1-NEXT: store i8* null, i8** [[TMP20]], align 8 1359 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1360 // CHECK1-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i64* 1361 // CHECK1-NEXT: store i64 2, i64* [[TMP22]], align 8 1362 // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1363 // CHECK1-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i64* 1364 // CHECK1-NEXT: store i64 2, i64* [[TMP24]], align 8 1365 // CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 1366 // CHECK1-NEXT: store i8* null, i8** [[TMP25]], align 8 1367 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 1368 // CHECK1-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64* 1369 // CHECK1-NEXT: store i64 [[TMP2]], i64* [[TMP27]], align 8 1370 // CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 1371 // CHECK1-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i64* 1372 // CHECK1-NEXT: store i64 [[TMP2]], i64* [[TMP29]], align 8 1373 // CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 1374 // CHECK1-NEXT: store i8* null, i8** [[TMP30]], align 8 1375 // CHECK1-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 1376 // CHECK1-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i16** 1377 // CHECK1-NEXT: store i16* [[VLA]], i16** [[TMP32]], align 8 1378 // CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 1379 // CHECK1-NEXT: [[TMP34:%.*]] = bitcast i8** [[TMP33]] to i16** 1380 // CHECK1-NEXT: store i16* [[VLA]], i16** [[TMP34]], align 8 1381 // CHECK1-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 1382 // CHECK1-NEXT: store i64 [[TMP9]], i64* [[TMP35]], align 8 1383 // CHECK1-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 1384 // CHECK1-NEXT: store i8* null, i8** [[TMP36]], align 8 1385 // CHECK1-NEXT: [[TMP37:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1386 // CHECK1-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1387 // CHECK1-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 1388 // CHECK1-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) 1389 // CHECK1-NEXT: [[TMP40:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218.region_id, i32 5, i8** [[TMP37]], i8** [[TMP38]], i64* [[TMP39]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.14, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 1390 // CHECK1-NEXT: [[TMP41:%.*]] = icmp ne i32 [[TMP40]], 0 1391 // CHECK1-NEXT: br i1 [[TMP41]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1392 // CHECK1: omp_offload.failed: 1393 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR3]] 1394 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 1395 // CHECK1: omp_offload.cont: 1396 // CHECK1-NEXT: br label [[OMP_IF_END:%.*]] 1397 // CHECK1: omp_if.else: 1398 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR3]] 1399 // CHECK1-NEXT: br label [[OMP_IF_END]] 1400 // CHECK1: omp_if.end: 1401 // CHECK1-NEXT: [[TMP42:%.*]] = mul nsw i64 1, [[TMP2]] 1402 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP42]] 1403 // CHECK1-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 1404 // CHECK1-NEXT: [[TMP43:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2 1405 // CHECK1-NEXT: [[CONV3:%.*]] = sext i16 [[TMP43]] to i32 1406 // CHECK1-NEXT: [[TMP44:%.*]] = load i32, i32* [[B]], align 4 1407 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], [[TMP44]] 1408 // CHECK1-NEXT: [[TMP45:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 1409 // CHECK1-NEXT: call void @llvm.stackrestore(i8* [[TMP45]]) 1410 // CHECK1-NEXT: ret i32 [[ADD4]] 1411 // 1412 // 1413 // CHECK1-LABEL: define {{[^@]+}}@_ZL7fstatici 1414 // CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { 1415 // CHECK1-NEXT: entry: 1416 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 1417 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4 1418 // CHECK1-NEXT: [[AA:%.*]] = alloca i16, align 2 1419 // CHECK1-NEXT: [[AAA:%.*]] = alloca i8, align 1 1420 // CHECK1-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 1421 // CHECK1-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 1422 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 1423 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 1424 // CHECK1-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 1425 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8 1426 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8 1427 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8 1428 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 1429 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 1430 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4 1431 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i32, align 4 1432 // CHECK1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 1433 // CHECK1-NEXT: store i32 0, i32* [[A]], align 4 1434 // CHECK1-NEXT: store i16 0, i16* [[AA]], align 2 1435 // CHECK1-NEXT: store i8 0, i8* [[AAA]], align 1 1436 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 1437 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[N_CASTED]] to i32* 1438 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 1439 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[N_CASTED]], align 8 1440 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 1441 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32* 1442 // CHECK1-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4 1443 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[A_CASTED]], align 8 1444 // CHECK1-NEXT: [[TMP4:%.*]] = load i16, i16* [[AA]], align 2 1445 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 1446 // CHECK1-NEXT: store i16 [[TMP4]], i16* [[CONV2]], align 2 1447 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[AA_CASTED]], align 8 1448 // CHECK1-NEXT: [[TMP6:%.*]] = load i8, i8* [[AAA]], align 1 1449 // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* 1450 // CHECK1-NEXT: store i8 [[TMP6]], i8* [[CONV3]], align 1 1451 // CHECK1-NEXT: [[TMP7:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 1452 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[N_ADDR]], align 4 1453 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP8]], 50 1454 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 1455 // CHECK1: omp_if.then: 1456 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1457 // CHECK1-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* 1458 // CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP10]], align 8 1459 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1460 // CHECK1-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64* 1461 // CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP12]], align 8 1462 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 1463 // CHECK1-NEXT: store i8* null, i8** [[TMP13]], align 8 1464 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1465 // CHECK1-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* 1466 // CHECK1-NEXT: store i64 [[TMP3]], i64* [[TMP15]], align 8 1467 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1468 // CHECK1-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64* 1469 // CHECK1-NEXT: store i64 [[TMP3]], i64* [[TMP17]], align 8 1470 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 1471 // CHECK1-NEXT: store i8* null, i8** [[TMP18]], align 8 1472 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1473 // CHECK1-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64* 1474 // CHECK1-NEXT: store i64 [[TMP5]], i64* [[TMP20]], align 8 1475 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1476 // CHECK1-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i64* 1477 // CHECK1-NEXT: store i64 [[TMP5]], i64* [[TMP22]], align 8 1478 // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 1479 // CHECK1-NEXT: store i8* null, i8** [[TMP23]], align 8 1480 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 1481 // CHECK1-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i64* 1482 // CHECK1-NEXT: store i64 [[TMP7]], i64* [[TMP25]], align 8 1483 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 1484 // CHECK1-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64* 1485 // CHECK1-NEXT: store i64 [[TMP7]], i64* [[TMP27]], align 8 1486 // CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 1487 // CHECK1-NEXT: store i8* null, i8** [[TMP28]], align 8 1488 // CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 1489 // CHECK1-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to [10 x i32]** 1490 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP30]], align 8 1491 // CHECK1-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 1492 // CHECK1-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to [10 x i32]** 1493 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP32]], align 8 1494 // CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 1495 // CHECK1-NEXT: store i8* null, i8** [[TMP33]], align 8 1496 // CHECK1-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1497 // CHECK1-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1498 // CHECK1-NEXT: [[TMP36:%.*]] = load i32, i32* [[A]], align 4 1499 // CHECK1-NEXT: store i32 [[TMP36]], i32* [[DOTCAPTURE_EXPR_]], align 4 1500 // CHECK1-NEXT: [[TMP37:%.*]] = load i32, i32* [[N_ADDR]], align 4 1501 // CHECK1-NEXT: store i32 [[TMP37]], i32* [[DOTCAPTURE_EXPR_4]], align 4 1502 // CHECK1-NEXT: [[TMP38:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 1503 // CHECK1-NEXT: [[TMP39:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 1504 // CHECK1-NEXT: [[SUB:%.*]] = sub i32 [[TMP38]], [[TMP39]] 1505 // CHECK1-NEXT: [[SUB6:%.*]] = sub i32 [[SUB]], 1 1506 // CHECK1-NEXT: [[ADD:%.*]] = add i32 [[SUB6]], 1 1507 // CHECK1-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 1508 // CHECK1-NEXT: [[SUB7:%.*]] = sub i32 [[DIV]], 1 1509 // CHECK1-NEXT: store i32 [[SUB7]], i32* [[DOTCAPTURE_EXPR_5]], align 4 1510 // CHECK1-NEXT: [[TMP40:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 1511 // CHECK1-NEXT: [[ADD8:%.*]] = add i32 [[TMP40]], 1 1512 // CHECK1-NEXT: [[TMP41:%.*]] = zext i32 [[ADD8]] to i64 1513 // CHECK1-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 [[TMP41]]) 1514 // CHECK1-NEXT: [[TMP42:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200.region_id, i32 5, i8** [[TMP34]], i8** [[TMP35]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes.16, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.17, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 1515 // CHECK1-NEXT: [[TMP43:%.*]] = icmp ne i32 [[TMP42]], 0 1516 // CHECK1-NEXT: br i1 [[TMP43]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1517 // CHECK1: omp_offload.failed: 1518 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], i64 [[TMP7]], [10 x i32]* [[B]]) #[[ATTR3]] 1519 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 1520 // CHECK1: omp_offload.cont: 1521 // CHECK1-NEXT: br label [[OMP_IF_END:%.*]] 1522 // CHECK1: omp_if.else: 1523 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], i64 [[TMP7]], [10 x i32]* [[B]]) #[[ATTR3]] 1524 // CHECK1-NEXT: br label [[OMP_IF_END]] 1525 // CHECK1: omp_if.end: 1526 // CHECK1-NEXT: [[TMP44:%.*]] = load i32, i32* [[A]], align 4 1527 // CHECK1-NEXT: ret i32 [[TMP44]] 1528 // 1529 // 1530 // CHECK1-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 1531 // CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat { 1532 // CHECK1-NEXT: entry: 1533 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 1534 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4 1535 // CHECK1-NEXT: [[AA:%.*]] = alloca i16, align 2 1536 // CHECK1-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 1537 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 1538 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 1539 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 1540 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 1541 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 1542 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 1543 // CHECK1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 1544 // CHECK1-NEXT: store i32 0, i32* [[A]], align 4 1545 // CHECK1-NEXT: store i16 0, i16* [[AA]], align 2 1546 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 1547 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* 1548 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 1549 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 1550 // CHECK1-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 1551 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 1552 // CHECK1-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 1553 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 1554 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 1555 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40 1556 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 1557 // CHECK1: omp_if.then: 1558 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1559 // CHECK1-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64* 1560 // CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP6]], align 8 1561 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1562 // CHECK1-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* 1563 // CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8 1564 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 1565 // CHECK1-NEXT: store i8* null, i8** [[TMP9]], align 8 1566 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1567 // CHECK1-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i64* 1568 // CHECK1-NEXT: store i64 [[TMP3]], i64* [[TMP11]], align 8 1569 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1570 // CHECK1-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* 1571 // CHECK1-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8 1572 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 1573 // CHECK1-NEXT: store i8* null, i8** [[TMP14]], align 8 1574 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1575 // CHECK1-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]** 1576 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 8 1577 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1578 // CHECK1-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]** 1579 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 8 1580 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 1581 // CHECK1-NEXT: store i8* null, i8** [[TMP19]], align 8 1582 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1583 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1584 // CHECK1-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) 1585 // CHECK1-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.19, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.20, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 1586 // CHECK1-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 1587 // CHECK1-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1588 // CHECK1: omp_offload.failed: 1589 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]] 1590 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 1591 // CHECK1: omp_offload.cont: 1592 // CHECK1-NEXT: br label [[OMP_IF_END:%.*]] 1593 // CHECK1: omp_if.else: 1594 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]] 1595 // CHECK1-NEXT: br label [[OMP_IF_END]] 1596 // CHECK1: omp_if.end: 1597 // CHECK1-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4 1598 // CHECK1-NEXT: ret i32 [[TMP24]] 1599 // 1600 // 1601 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218 1602 // CHECK1-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { 1603 // CHECK1-NEXT: entry: 1604 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 1605 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 1606 // CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 1607 // CHECK1-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 1608 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 1609 // CHECK1-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 1610 // CHECK1-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 1611 // CHECK1-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 1612 // CHECK1-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 1613 // CHECK1-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 1614 // CHECK1-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 1615 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 1616 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 1617 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 1618 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 1619 // CHECK1-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 1620 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4 1621 // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* 1622 // CHECK1-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 1623 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 1624 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..12 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) 1625 // CHECK1-NEXT: ret void 1626 // 1627 // 1628 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..12 1629 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { 1630 // CHECK1-NEXT: entry: 1631 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1632 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1633 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 1634 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 1635 // CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 1636 // CHECK1-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 1637 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 1638 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1639 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 1640 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1641 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1642 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1643 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1644 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 1645 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1646 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1647 // CHECK1-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 1648 // CHECK1-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 1649 // CHECK1-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 1650 // CHECK1-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 1651 // CHECK1-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 1652 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 1653 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 1654 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 1655 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 1656 // CHECK1-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 1657 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1658 // CHECK1-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 1659 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 1660 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1661 // CHECK1-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 1662 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 1663 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 1664 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1665 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 9 1666 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1667 // CHECK1: cond.true: 1668 // CHECK1-NEXT: br label [[COND_END:%.*]] 1669 // CHECK1: cond.false: 1670 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1671 // CHECK1-NEXT: br label [[COND_END]] 1672 // CHECK1: cond.end: 1673 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 1674 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 1675 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1676 // CHECK1-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 1677 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1678 // CHECK1: omp.inner.for.cond: 1679 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1680 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1681 // CHECK1-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 1682 // CHECK1-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1683 // CHECK1: omp.inner.for.body: 1684 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1685 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 1686 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1687 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4 1688 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4 1689 // CHECK1-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double 1690 // CHECK1-NEXT: [[ADD5:%.*]] = fadd double [[CONV4]], 1.500000e+00 1691 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 1692 // CHECK1-NEXT: store double [[ADD5]], double* [[A]], align 8 1693 // CHECK1-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 1694 // CHECK1-NEXT: [[TMP13:%.*]] = load double, double* [[A6]], align 8 1695 // CHECK1-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 1696 // CHECK1-NEXT: store double [[INC]], double* [[A6]], align 8 1697 // CHECK1-NEXT: [[CONV7:%.*]] = fptosi double [[INC]] to i16 1698 // CHECK1-NEXT: [[TMP14:%.*]] = mul nsw i64 1, [[TMP2]] 1699 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP14]] 1700 // CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 1701 // CHECK1-NEXT: store i16 [[CONV7]], i16* [[ARRAYIDX8]], align 2 1702 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1703 // CHECK1: omp.body.continue: 1704 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1705 // CHECK1: omp.inner.for.inc: 1706 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1707 // CHECK1-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP15]], 1 1708 // CHECK1-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 1709 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 1710 // CHECK1: omp.inner.for.end: 1711 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1712 // CHECK1: omp.loop.exit: 1713 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 1714 // CHECK1-NEXT: ret void 1715 // 1716 // 1717 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200 1718 // CHECK1-SAME: (i64 noundef [[N:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 1719 // CHECK1-NEXT: entry: 1720 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 1721 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1722 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 1723 // CHECK1-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 1724 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 1725 // CHECK1-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 1726 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 1727 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 1728 // CHECK1-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 1729 // CHECK1-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 1730 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 1731 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 1732 // CHECK1-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 1733 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 1734 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* 1735 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_ADDR]] to i32* 1736 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 1737 // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 1738 // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 1739 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 1740 // CHECK1-NEXT: [[CONV4:%.*]] = bitcast i64* [[N_CASTED]] to i32* 1741 // CHECK1-NEXT: store i32 [[TMP1]], i32* [[CONV4]], align 4 1742 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[N_CASTED]], align 8 1743 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 4 1744 // CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* 1745 // CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV5]], align 4 1746 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8 1747 // CHECK1-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV2]], align 2 1748 // CHECK1-NEXT: [[CONV6:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 1749 // CHECK1-NEXT: store i16 [[TMP5]], i16* [[CONV6]], align 2 1750 // CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[AA_CASTED]], align 8 1751 // CHECK1-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV3]], align 1 1752 // CHECK1-NEXT: [[CONV7:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* 1753 // CHECK1-NEXT: store i8 [[TMP7]], i8* [[CONV7]], align 1 1754 // CHECK1-NEXT: [[TMP8:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 1755 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, [10 x i32]*)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]], [10 x i32]* [[TMP0]]) 1756 // CHECK1-NEXT: ret void 1757 // 1758 // 1759 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..15 1760 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 1761 // CHECK1-NEXT: entry: 1762 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1763 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1764 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 1765 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1766 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 1767 // CHECK1-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 1768 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 1769 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1770 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 1771 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 1772 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4 1773 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i32, align 4 1774 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 1775 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1776 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1777 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1778 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1779 // CHECK1-NEXT: [[I8:%.*]] = alloca i32, align 4 1780 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1781 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1782 // CHECK1-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 1783 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 1784 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 1785 // CHECK1-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 1786 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 1787 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* 1788 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_ADDR]] to i32* 1789 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 1790 // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 1791 // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 1792 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV1]], align 4 1793 // CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 1794 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4 1795 // CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_4]], align 4 1796 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 1797 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 1798 // CHECK1-NEXT: [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]] 1799 // CHECK1-NEXT: [[SUB6:%.*]] = sub i32 [[SUB]], 1 1800 // CHECK1-NEXT: [[ADD:%.*]] = add i32 [[SUB6]], 1 1801 // CHECK1-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 1802 // CHECK1-NEXT: [[SUB7:%.*]] = sub i32 [[DIV]], 1 1803 // CHECK1-NEXT: store i32 [[SUB7]], i32* [[DOTCAPTURE_EXPR_5]], align 4 1804 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 1805 // CHECK1-NEXT: store i32 [[TMP5]], i32* [[I]], align 4 1806 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 1807 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 1808 // CHECK1-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]] 1809 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] 1810 // CHECK1: omp.precond.then: 1811 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1812 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 1813 // CHECK1-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_UB]], align 4 1814 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 1815 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1816 // CHECK1-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 1817 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 1818 // CHECK1-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 1819 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1820 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 1821 // CHECK1-NEXT: [[CMP9:%.*]] = icmp ugt i32 [[TMP11]], [[TMP12]] 1822 // CHECK1-NEXT: br i1 [[CMP9]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1823 // CHECK1: cond.true: 1824 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 1825 // CHECK1-NEXT: br label [[COND_END:%.*]] 1826 // CHECK1: cond.false: 1827 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1828 // CHECK1-NEXT: br label [[COND_END]] 1829 // CHECK1: cond.end: 1830 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ] 1831 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 1832 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1833 // CHECK1-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4 1834 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1835 // CHECK1: omp.inner.for.cond: 1836 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1837 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1838 // CHECK1-NEXT: [[ADD10:%.*]] = add i32 [[TMP17]], 1 1839 // CHECK1-NEXT: [[CMP11:%.*]] = icmp ult i32 [[TMP16]], [[ADD10]] 1840 // CHECK1-NEXT: br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1841 // CHECK1: omp.inner.for.body: 1842 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 1843 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1844 // CHECK1-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 1 1845 // CHECK1-NEXT: [[ADD12:%.*]] = add i32 [[TMP18]], [[MUL]] 1846 // CHECK1-NEXT: store i32 [[ADD12]], i32* [[I8]], align 4 1847 // CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 4 1848 // CHECK1-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP20]], 1 1849 // CHECK1-NEXT: store i32 [[ADD13]], i32* [[CONV1]], align 4 1850 // CHECK1-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV2]], align 2 1851 // CHECK1-NEXT: [[CONV14:%.*]] = sext i16 [[TMP21]] to i32 1852 // CHECK1-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1 1853 // CHECK1-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16 1854 // CHECK1-NEXT: store i16 [[CONV16]], i16* [[CONV2]], align 2 1855 // CHECK1-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV3]], align 1 1856 // CHECK1-NEXT: [[CONV17:%.*]] = sext i8 [[TMP22]] to i32 1857 // CHECK1-NEXT: [[ADD18:%.*]] = add nsw i32 [[CONV17]], 1 1858 // CHECK1-NEXT: [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8 1859 // CHECK1-NEXT: store i8 [[CONV19]], i8* [[CONV3]], align 1 1860 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 1861 // CHECK1-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 1862 // CHECK1-NEXT: [[ADD20:%.*]] = add nsw i32 [[TMP23]], 1 1863 // CHECK1-NEXT: store i32 [[ADD20]], i32* [[ARRAYIDX]], align 4 1864 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1865 // CHECK1: omp.body.continue: 1866 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1867 // CHECK1: omp.inner.for.inc: 1868 // CHECK1-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1869 // CHECK1-NEXT: [[ADD21:%.*]] = add i32 [[TMP24]], 1 1870 // CHECK1-NEXT: store i32 [[ADD21]], i32* [[DOTOMP_IV]], align 4 1871 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 1872 // CHECK1: omp.inner.for.end: 1873 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1874 // CHECK1: omp.loop.exit: 1875 // CHECK1-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 1876 // CHECK1-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 1877 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) 1878 // CHECK1-NEXT: br label [[OMP_PRECOND_END]] 1879 // CHECK1: omp.precond.end: 1880 // CHECK1-NEXT: ret void 1881 // 1882 // 1883 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183 1884 // CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 1885 // CHECK1-NEXT: entry: 1886 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1887 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 1888 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 1889 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 1890 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 1891 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 1892 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 1893 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 1894 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 1895 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 1896 // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 1897 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 1898 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* 1899 // CHECK1-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 1900 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 1901 // CHECK1-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 1902 // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 1903 // CHECK1-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 1904 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 1905 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..18 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) 1906 // CHECK1-NEXT: ret void 1907 // 1908 // 1909 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..18 1910 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 1911 // CHECK1-NEXT: entry: 1912 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1913 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1914 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1915 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 1916 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 1917 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1918 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 1919 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1920 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1921 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1922 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1923 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 1924 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1925 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1926 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 1927 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 1928 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 1929 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 1930 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 1931 // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 1932 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1933 // CHECK1-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 1934 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 1935 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1936 // CHECK1-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 1937 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 1938 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 1939 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1940 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 1941 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1942 // CHECK1: cond.true: 1943 // CHECK1-NEXT: br label [[COND_END:%.*]] 1944 // CHECK1: cond.false: 1945 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1946 // CHECK1-NEXT: br label [[COND_END]] 1947 // CHECK1: cond.end: 1948 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 1949 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 1950 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1951 // CHECK1-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 1952 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1953 // CHECK1: omp.inner.for.cond: 1954 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1955 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1956 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] 1957 // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1958 // CHECK1: omp.inner.for.body: 1959 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1960 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 1961 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1962 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4 1963 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4 1964 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1 1965 // CHECK1-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4 1966 // CHECK1-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 2 1967 // CHECK1-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32 1968 // CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 1969 // CHECK1-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 1970 // CHECK1-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2 1971 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 1972 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 1973 // CHECK1-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1 1974 // CHECK1-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4 1975 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1976 // CHECK1: omp.body.continue: 1977 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1978 // CHECK1: omp.inner.for.inc: 1979 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1980 // CHECK1-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP12]], 1 1981 // CHECK1-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 1982 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 1983 // CHECK1: omp.inner.for.end: 1984 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1985 // CHECK1: omp.loop.exit: 1986 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) 1987 // CHECK1-NEXT: ret void 1988 // 1989 // 1990 // CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 1991 // CHECK1-SAME: () #[[ATTR4]] { 1992 // CHECK1-NEXT: entry: 1993 // CHECK1-NEXT: call void @__tgt_register_requires(i64 1) 1994 // CHECK1-NEXT: ret void 1995 // 1996 // 1997 // CHECK3-LABEL: define {{[^@]+}}@_Z3fooi 1998 // CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0:[0-9]+]] { 1999 // CHECK3-NEXT: entry: 2000 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 2001 // CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4 2002 // CHECK3-NEXT: [[AA:%.*]] = alloca i16, align 2 2003 // CHECK3-NEXT: [[B:%.*]] = alloca [10 x float], align 4 2004 // CHECK3-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 2005 // CHECK3-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 2006 // CHECK3-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 2007 // CHECK3-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 2008 // CHECK3-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 2009 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 2010 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 2011 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 2012 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 2013 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__CASTED3:%.*]] = alloca i32, align 4 2014 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 2015 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 2016 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 2017 // CHECK3-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4 2018 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 2019 // CHECK3-NEXT: [[AA_CASTED4:%.*]] = alloca i32, align 4 2020 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS6:%.*]] = alloca [1 x i8*], align 4 2021 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS7:%.*]] = alloca [1 x i8*], align 4 2022 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS8:%.*]] = alloca [1 x i8*], align 4 2023 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 2024 // CHECK3-NEXT: [[A_CASTED9:%.*]] = alloca i32, align 4 2025 // CHECK3-NEXT: [[AA_CASTED10:%.*]] = alloca i32, align 4 2026 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS12:%.*]] = alloca [2 x i8*], align 4 2027 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS13:%.*]] = alloca [2 x i8*], align 4 2028 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS14:%.*]] = alloca [2 x i8*], align 4 2029 // CHECK3-NEXT: [[_TMP15:%.*]] = alloca i32, align 4 2030 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_18:%.*]] = alloca i32, align 4 2031 // CHECK3-NEXT: [[A_CASTED19:%.*]] = alloca i32, align 4 2032 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__CASTED20:%.*]] = alloca i32, align 4 2033 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS23:%.*]] = alloca [10 x i8*], align 4 2034 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS24:%.*]] = alloca [10 x i8*], align 4 2035 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS25:%.*]] = alloca [10 x i8*], align 4 2036 // CHECK3-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 4 2037 // CHECK3-NEXT: [[_TMP26:%.*]] = alloca i32, align 4 2038 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) 2039 // CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 2040 // CHECK3-NEXT: store i32 0, i32* [[A]], align 4 2041 // CHECK3-NEXT: store i16 0, i16* [[AA]], align 2 2042 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 2043 // CHECK3-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() 2044 // CHECK3-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 2045 // CHECK3-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP1]], align 4 2046 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 2047 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 2048 // CHECK3-NEXT: [[TMP4:%.*]] = mul nuw i32 5, [[TMP3]] 2049 // CHECK3-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP4]], align 8 2050 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[__VLA_EXPR1]], align 4 2051 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 2052 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_]], align 4 2053 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 2054 // CHECK3-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_2]], align 4 2055 // CHECK3-NEXT: [[TMP7:%.*]] = load i16, i16* [[AA]], align 2 2056 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 2057 // CHECK3-NEXT: store i16 [[TMP7]], i16* [[CONV]], align 2 2058 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[AA_CASTED]], align 4 2059 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 2060 // CHECK3-NEXT: store i32 [[TMP9]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 2061 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 2062 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 2063 // CHECK3-NEXT: store i32 [[TMP11]], i32* [[DOTCAPTURE_EXPR__CASTED3]], align 4 2064 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED3]], align 4 2065 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2066 // CHECK3-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i32* 2067 // CHECK3-NEXT: store i32 [[TMP8]], i32* [[TMP14]], align 4 2068 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2069 // CHECK3-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i32* 2070 // CHECK3-NEXT: store i32 [[TMP8]], i32* [[TMP16]], align 4 2071 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 2072 // CHECK3-NEXT: store i8* null, i8** [[TMP17]], align 4 2073 // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 2074 // CHECK3-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32* 2075 // CHECK3-NEXT: store i32 [[TMP10]], i32* [[TMP19]], align 4 2076 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 2077 // CHECK3-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32* 2078 // CHECK3-NEXT: store i32 [[TMP10]], i32* [[TMP21]], align 4 2079 // CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 2080 // CHECK3-NEXT: store i8* null, i8** [[TMP22]], align 4 2081 // CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 2082 // CHECK3-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i32* 2083 // CHECK3-NEXT: store i32 [[TMP12]], i32* [[TMP24]], align 4 2084 // CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 2085 // CHECK3-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i32* 2086 // CHECK3-NEXT: store i32 [[TMP12]], i32* [[TMP26]], align 4 2087 // CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 2088 // CHECK3-NEXT: store i8* null, i8** [[TMP27]], align 4 2089 // CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2090 // CHECK3-NEXT: [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2091 // CHECK3-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 0 2092 // CHECK3-NEXT: [[TMP31:%.*]] = load i16, i16* [[AA]], align 2 2093 // CHECK3-NEXT: store i16 [[TMP31]], i16* [[TMP30]], align 4 2094 // CHECK3-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 1 2095 // CHECK3-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 2096 // CHECK3-NEXT: store i32 [[TMP33]], i32* [[TMP32]], align 4 2097 // CHECK3-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 2 2098 // CHECK3-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 2099 // CHECK3-NEXT: store i32 [[TMP35]], i32* [[TMP34]], align 4 2100 // CHECK3-NEXT: [[TMP36:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 1, i32 72, i32 12, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1) 2101 // CHECK3-NEXT: [[TMP37:%.*]] = bitcast i8* [[TMP36]] to %struct.kmp_task_t_with_privates* 2102 // CHECK3-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP37]], i32 0, i32 0 2103 // CHECK3-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP38]], i32 0, i32 0 2104 // CHECK3-NEXT: [[TMP40:%.*]] = load i8*, i8** [[TMP39]], align 4 2105 // CHECK3-NEXT: [[TMP41:%.*]] = bitcast %struct.anon* [[AGG_CAPTURED]] to i8* 2106 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP40]], i8* align 4 [[TMP41]], i32 12, i1 false) 2107 // CHECK3-NEXT: [[TMP42:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP37]], i32 0, i32 1 2108 // CHECK3-NEXT: [[TMP43:%.*]] = bitcast i8* [[TMP40]] to %struct.anon* 2109 // CHECK3-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 0 2110 // CHECK3-NEXT: [[TMP45:%.*]] = bitcast [3 x i64]* [[TMP44]] to i8* 2111 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP45]], i8* align 4 bitcast ([3 x i64]* @.offload_sizes to i8*), i32 24, i1 false) 2112 // CHECK3-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 1 2113 // CHECK3-NEXT: [[TMP47:%.*]] = bitcast [3 x i8*]* [[TMP46]] to i8* 2114 // CHECK3-NEXT: [[TMP48:%.*]] = bitcast i8** [[TMP28]] to i8* 2115 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP47]], i8* align 4 [[TMP48]], i32 12, i1 false) 2116 // CHECK3-NEXT: [[TMP49:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 2 2117 // CHECK3-NEXT: [[TMP50:%.*]] = bitcast [3 x i8*]* [[TMP49]] to i8* 2118 // CHECK3-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP29]] to i8* 2119 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP50]], i8* align 4 [[TMP51]], i32 12, i1 false) 2120 // CHECK3-NEXT: [[TMP52:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 3 2121 // CHECK3-NEXT: [[TMP53:%.*]] = load i16, i16* [[AA]], align 2 2122 // CHECK3-NEXT: store i16 [[TMP53]], i16* [[TMP52]], align 4 2123 // CHECK3-NEXT: [[TMP54:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i8* [[TMP36]]) 2124 // CHECK3-NEXT: [[TMP55:%.*]] = load i32, i32* [[A]], align 4 2125 // CHECK3-NEXT: store i32 [[TMP55]], i32* [[A_CASTED]], align 4 2126 // CHECK3-NEXT: [[TMP56:%.*]] = load i32, i32* [[A_CASTED]], align 4 2127 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l107(i32 [[TMP56]]) #[[ATTR3:[0-9]+]] 2128 // CHECK3-NEXT: [[TMP57:%.*]] = load i16, i16* [[AA]], align 2 2129 // CHECK3-NEXT: [[CONV5:%.*]] = bitcast i32* [[AA_CASTED4]] to i16* 2130 // CHECK3-NEXT: store i16 [[TMP57]], i16* [[CONV5]], align 2 2131 // CHECK3-NEXT: [[TMP58:%.*]] = load i32, i32* [[AA_CASTED4]], align 4 2132 // CHECK3-NEXT: [[TMP59:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0 2133 // CHECK3-NEXT: [[TMP60:%.*]] = bitcast i8** [[TMP59]] to i32* 2134 // CHECK3-NEXT: store i32 [[TMP58]], i32* [[TMP60]], align 4 2135 // CHECK3-NEXT: [[TMP61:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0 2136 // CHECK3-NEXT: [[TMP62:%.*]] = bitcast i8** [[TMP61]] to i32* 2137 // CHECK3-NEXT: store i32 [[TMP58]], i32* [[TMP62]], align 4 2138 // CHECK3-NEXT: [[TMP63:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS8]], i32 0, i32 0 2139 // CHECK3-NEXT: store i8* null, i8** [[TMP63]], align 4 2140 // CHECK3-NEXT: [[TMP64:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0 2141 // CHECK3-NEXT: [[TMP65:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0 2142 // CHECK3-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) 2143 // CHECK3-NEXT: [[TMP66:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113.region_id, i32 1, i8** [[TMP64]], i8** [[TMP65]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.4, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.5, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 2144 // CHECK3-NEXT: [[TMP67:%.*]] = icmp ne i32 [[TMP66]], 0 2145 // CHECK3-NEXT: br i1 [[TMP67]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 2146 // CHECK3: omp_offload.failed: 2147 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113(i32 [[TMP58]]) #[[ATTR3]] 2148 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 2149 // CHECK3: omp_offload.cont: 2150 // CHECK3-NEXT: [[TMP68:%.*]] = load i32, i32* [[A]], align 4 2151 // CHECK3-NEXT: store i32 [[TMP68]], i32* [[A_CASTED9]], align 4 2152 // CHECK3-NEXT: [[TMP69:%.*]] = load i32, i32* [[A_CASTED9]], align 4 2153 // CHECK3-NEXT: [[TMP70:%.*]] = load i16, i16* [[AA]], align 2 2154 // CHECK3-NEXT: [[CONV11:%.*]] = bitcast i32* [[AA_CASTED10]] to i16* 2155 // CHECK3-NEXT: store i16 [[TMP70]], i16* [[CONV11]], align 2 2156 // CHECK3-NEXT: [[TMP71:%.*]] = load i32, i32* [[AA_CASTED10]], align 4 2157 // CHECK3-NEXT: [[TMP72:%.*]] = load i32, i32* [[N_ADDR]], align 4 2158 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP72]], 10 2159 // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 2160 // CHECK3: omp_if.then: 2161 // CHECK3-NEXT: [[TMP73:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS12]], i32 0, i32 0 2162 // CHECK3-NEXT: [[TMP74:%.*]] = bitcast i8** [[TMP73]] to i32* 2163 // CHECK3-NEXT: store i32 [[TMP69]], i32* [[TMP74]], align 4 2164 // CHECK3-NEXT: [[TMP75:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS13]], i32 0, i32 0 2165 // CHECK3-NEXT: [[TMP76:%.*]] = bitcast i8** [[TMP75]] to i32* 2166 // CHECK3-NEXT: store i32 [[TMP69]], i32* [[TMP76]], align 4 2167 // CHECK3-NEXT: [[TMP77:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS14]], i32 0, i32 0 2168 // CHECK3-NEXT: store i8* null, i8** [[TMP77]], align 4 2169 // CHECK3-NEXT: [[TMP78:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS12]], i32 0, i32 1 2170 // CHECK3-NEXT: [[TMP79:%.*]] = bitcast i8** [[TMP78]] to i32* 2171 // CHECK3-NEXT: store i32 [[TMP71]], i32* [[TMP79]], align 4 2172 // CHECK3-NEXT: [[TMP80:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS13]], i32 0, i32 1 2173 // CHECK3-NEXT: [[TMP81:%.*]] = bitcast i8** [[TMP80]] to i32* 2174 // CHECK3-NEXT: store i32 [[TMP71]], i32* [[TMP81]], align 4 2175 // CHECK3-NEXT: [[TMP82:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS14]], i32 0, i32 1 2176 // CHECK3-NEXT: store i8* null, i8** [[TMP82]], align 4 2177 // CHECK3-NEXT: [[TMP83:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS12]], i32 0, i32 0 2178 // CHECK3-NEXT: [[TMP84:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS13]], i32 0, i32 0 2179 // CHECK3-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) 2180 // CHECK3-NEXT: [[TMP85:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120.region_id, i32 2, i8** [[TMP83]], i8** [[TMP84]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.7, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.8, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 2181 // CHECK3-NEXT: [[TMP86:%.*]] = icmp ne i32 [[TMP85]], 0 2182 // CHECK3-NEXT: br i1 [[TMP86]], label [[OMP_OFFLOAD_FAILED16:%.*]], label [[OMP_OFFLOAD_CONT17:%.*]] 2183 // CHECK3: omp_offload.failed16: 2184 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120(i32 [[TMP69]], i32 [[TMP71]]) #[[ATTR3]] 2185 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT17]] 2186 // CHECK3: omp_offload.cont17: 2187 // CHECK3-NEXT: br label [[OMP_IF_END:%.*]] 2188 // CHECK3: omp_if.else: 2189 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120(i32 [[TMP69]], i32 [[TMP71]]) #[[ATTR3]] 2190 // CHECK3-NEXT: br label [[OMP_IF_END]] 2191 // CHECK3: omp_if.end: 2192 // CHECK3-NEXT: [[TMP87:%.*]] = load i32, i32* [[N_ADDR]], align 4 2193 // CHECK3-NEXT: store i32 [[TMP87]], i32* [[DOTCAPTURE_EXPR_18]], align 4 2194 // CHECK3-NEXT: [[TMP88:%.*]] = load i32, i32* [[A]], align 4 2195 // CHECK3-NEXT: store i32 [[TMP88]], i32* [[A_CASTED19]], align 4 2196 // CHECK3-NEXT: [[TMP89:%.*]] = load i32, i32* [[A_CASTED19]], align 4 2197 // CHECK3-NEXT: [[TMP90:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_18]], align 4 2198 // CHECK3-NEXT: store i32 [[TMP90]], i32* [[DOTCAPTURE_EXPR__CASTED20]], align 4 2199 // CHECK3-NEXT: [[TMP91:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED20]], align 4 2200 // CHECK3-NEXT: [[TMP92:%.*]] = load i32, i32* [[N_ADDR]], align 4 2201 // CHECK3-NEXT: [[CMP21:%.*]] = icmp sgt i32 [[TMP92]], 20 2202 // CHECK3-NEXT: br i1 [[CMP21]], label [[OMP_IF_THEN22:%.*]], label [[OMP_IF_ELSE29:%.*]] 2203 // CHECK3: omp_if.then22: 2204 // CHECK3-NEXT: [[TMP93:%.*]] = mul nuw i32 [[TMP1]], 4 2205 // CHECK3-NEXT: [[TMP94:%.*]] = sext i32 [[TMP93]] to i64 2206 // CHECK3-NEXT: [[TMP95:%.*]] = mul nuw i32 5, [[TMP3]] 2207 // CHECK3-NEXT: [[TMP96:%.*]] = mul nuw i32 [[TMP95]], 8 2208 // CHECK3-NEXT: [[TMP97:%.*]] = sext i32 [[TMP96]] to i64 2209 // CHECK3-NEXT: [[TMP98:%.*]] = bitcast [10 x i64]* [[DOTOFFLOAD_SIZES]] to i8* 2210 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP98]], i8* align 4 bitcast ([10 x i64]* @.offload_sizes.10 to i8*), i32 80, i1 false) 2211 // CHECK3-NEXT: [[TMP99:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS23]], i32 0, i32 0 2212 // CHECK3-NEXT: [[TMP100:%.*]] = bitcast i8** [[TMP99]] to i32* 2213 // CHECK3-NEXT: store i32 [[TMP89]], i32* [[TMP100]], align 4 2214 // CHECK3-NEXT: [[TMP101:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS24]], i32 0, i32 0 2215 // CHECK3-NEXT: [[TMP102:%.*]] = bitcast i8** [[TMP101]] to i32* 2216 // CHECK3-NEXT: store i32 [[TMP89]], i32* [[TMP102]], align 4 2217 // CHECK3-NEXT: [[TMP103:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS25]], i32 0, i32 0 2218 // CHECK3-NEXT: store i8* null, i8** [[TMP103]], align 4 2219 // CHECK3-NEXT: [[TMP104:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS23]], i32 0, i32 1 2220 // CHECK3-NEXT: [[TMP105:%.*]] = bitcast i8** [[TMP104]] to [10 x float]** 2221 // CHECK3-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP105]], align 4 2222 // CHECK3-NEXT: [[TMP106:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS24]], i32 0, i32 1 2223 // CHECK3-NEXT: [[TMP107:%.*]] = bitcast i8** [[TMP106]] to [10 x float]** 2224 // CHECK3-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP107]], align 4 2225 // CHECK3-NEXT: [[TMP108:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS25]], i32 0, i32 1 2226 // CHECK3-NEXT: store i8* null, i8** [[TMP108]], align 4 2227 // CHECK3-NEXT: [[TMP109:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS23]], i32 0, i32 2 2228 // CHECK3-NEXT: [[TMP110:%.*]] = bitcast i8** [[TMP109]] to i32* 2229 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP110]], align 4 2230 // CHECK3-NEXT: [[TMP111:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS24]], i32 0, i32 2 2231 // CHECK3-NEXT: [[TMP112:%.*]] = bitcast i8** [[TMP111]] to i32* 2232 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP112]], align 4 2233 // CHECK3-NEXT: [[TMP113:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS25]], i32 0, i32 2 2234 // CHECK3-NEXT: store i8* null, i8** [[TMP113]], align 4 2235 // CHECK3-NEXT: [[TMP114:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS23]], i32 0, i32 3 2236 // CHECK3-NEXT: [[TMP115:%.*]] = bitcast i8** [[TMP114]] to float** 2237 // CHECK3-NEXT: store float* [[VLA]], float** [[TMP115]], align 4 2238 // CHECK3-NEXT: [[TMP116:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS24]], i32 0, i32 3 2239 // CHECK3-NEXT: [[TMP117:%.*]] = bitcast i8** [[TMP116]] to float** 2240 // CHECK3-NEXT: store float* [[VLA]], float** [[TMP117]], align 4 2241 // CHECK3-NEXT: [[TMP118:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 2242 // CHECK3-NEXT: store i64 [[TMP94]], i64* [[TMP118]], align 4 2243 // CHECK3-NEXT: [[TMP119:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS25]], i32 0, i32 3 2244 // CHECK3-NEXT: store i8* null, i8** [[TMP119]], align 4 2245 // CHECK3-NEXT: [[TMP120:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS23]], i32 0, i32 4 2246 // CHECK3-NEXT: [[TMP121:%.*]] = bitcast i8** [[TMP120]] to [5 x [10 x double]]** 2247 // CHECK3-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP121]], align 4 2248 // CHECK3-NEXT: [[TMP122:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS24]], i32 0, i32 4 2249 // CHECK3-NEXT: [[TMP123:%.*]] = bitcast i8** [[TMP122]] to [5 x [10 x double]]** 2250 // CHECK3-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP123]], align 4 2251 // CHECK3-NEXT: [[TMP124:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS25]], i32 0, i32 4 2252 // CHECK3-NEXT: store i8* null, i8** [[TMP124]], align 4 2253 // CHECK3-NEXT: [[TMP125:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS23]], i32 0, i32 5 2254 // CHECK3-NEXT: [[TMP126:%.*]] = bitcast i8** [[TMP125]] to i32* 2255 // CHECK3-NEXT: store i32 5, i32* [[TMP126]], align 4 2256 // CHECK3-NEXT: [[TMP127:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS24]], i32 0, i32 5 2257 // CHECK3-NEXT: [[TMP128:%.*]] = bitcast i8** [[TMP127]] to i32* 2258 // CHECK3-NEXT: store i32 5, i32* [[TMP128]], align 4 2259 // CHECK3-NEXT: [[TMP129:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS25]], i32 0, i32 5 2260 // CHECK3-NEXT: store i8* null, i8** [[TMP129]], align 4 2261 // CHECK3-NEXT: [[TMP130:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS23]], i32 0, i32 6 2262 // CHECK3-NEXT: [[TMP131:%.*]] = bitcast i8** [[TMP130]] to i32* 2263 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP131]], align 4 2264 // CHECK3-NEXT: [[TMP132:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS24]], i32 0, i32 6 2265 // CHECK3-NEXT: [[TMP133:%.*]] = bitcast i8** [[TMP132]] to i32* 2266 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP133]], align 4 2267 // CHECK3-NEXT: [[TMP134:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS25]], i32 0, i32 6 2268 // CHECK3-NEXT: store i8* null, i8** [[TMP134]], align 4 2269 // CHECK3-NEXT: [[TMP135:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS23]], i32 0, i32 7 2270 // CHECK3-NEXT: [[TMP136:%.*]] = bitcast i8** [[TMP135]] to double** 2271 // CHECK3-NEXT: store double* [[VLA1]], double** [[TMP136]], align 4 2272 // CHECK3-NEXT: [[TMP137:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS24]], i32 0, i32 7 2273 // CHECK3-NEXT: [[TMP138:%.*]] = bitcast i8** [[TMP137]] to double** 2274 // CHECK3-NEXT: store double* [[VLA1]], double** [[TMP138]], align 4 2275 // CHECK3-NEXT: [[TMP139:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 2276 // CHECK3-NEXT: store i64 [[TMP97]], i64* [[TMP139]], align 4 2277 // CHECK3-NEXT: [[TMP140:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS25]], i32 0, i32 7 2278 // CHECK3-NEXT: store i8* null, i8** [[TMP140]], align 4 2279 // CHECK3-NEXT: [[TMP141:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS23]], i32 0, i32 8 2280 // CHECK3-NEXT: [[TMP142:%.*]] = bitcast i8** [[TMP141]] to %struct.TT** 2281 // CHECK3-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP142]], align 4 2282 // CHECK3-NEXT: [[TMP143:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS24]], i32 0, i32 8 2283 // CHECK3-NEXT: [[TMP144:%.*]] = bitcast i8** [[TMP143]] to %struct.TT** 2284 // CHECK3-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP144]], align 4 2285 // CHECK3-NEXT: [[TMP145:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS25]], i32 0, i32 8 2286 // CHECK3-NEXT: store i8* null, i8** [[TMP145]], align 4 2287 // CHECK3-NEXT: [[TMP146:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS23]], i32 0, i32 9 2288 // CHECK3-NEXT: [[TMP147:%.*]] = bitcast i8** [[TMP146]] to i32* 2289 // CHECK3-NEXT: store i32 [[TMP91]], i32* [[TMP147]], align 4 2290 // CHECK3-NEXT: [[TMP148:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS24]], i32 0, i32 9 2291 // CHECK3-NEXT: [[TMP149:%.*]] = bitcast i8** [[TMP148]] to i32* 2292 // CHECK3-NEXT: store i32 [[TMP91]], i32* [[TMP149]], align 4 2293 // CHECK3-NEXT: [[TMP150:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS25]], i32 0, i32 9 2294 // CHECK3-NEXT: store i8* null, i8** [[TMP150]], align 4 2295 // CHECK3-NEXT: [[TMP151:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS23]], i32 0, i32 0 2296 // CHECK3-NEXT: [[TMP152:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS24]], i32 0, i32 0 2297 // CHECK3-NEXT: [[TMP153:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 2298 // CHECK3-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) 2299 // CHECK3-NEXT: [[TMP154:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145.region_id, i32 10, i8** [[TMP151]], i8** [[TMP152]], i64* [[TMP153]], i64* getelementptr inbounds ([10 x i64], [10 x i64]* @.offload_maptypes.11, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 2300 // CHECK3-NEXT: [[TMP155:%.*]] = icmp ne i32 [[TMP154]], 0 2301 // CHECK3-NEXT: br i1 [[TMP155]], label [[OMP_OFFLOAD_FAILED27:%.*]], label [[OMP_OFFLOAD_CONT28:%.*]] 2302 // CHECK3: omp_offload.failed27: 2303 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145(i32 [[TMP89]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]], i32 [[TMP91]]) #[[ATTR3]] 2304 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT28]] 2305 // CHECK3: omp_offload.cont28: 2306 // CHECK3-NEXT: br label [[OMP_IF_END30:%.*]] 2307 // CHECK3: omp_if.else29: 2308 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145(i32 [[TMP89]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]], i32 [[TMP91]]) #[[ATTR3]] 2309 // CHECK3-NEXT: br label [[OMP_IF_END30]] 2310 // CHECK3: omp_if.end30: 2311 // CHECK3-NEXT: [[TMP156:%.*]] = load i32, i32* [[A]], align 4 2312 // CHECK3-NEXT: [[TMP157:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 2313 // CHECK3-NEXT: call void @llvm.stackrestore(i8* [[TMP157]]) 2314 // CHECK3-NEXT: ret i32 [[TMP156]] 2315 // 2316 // 2317 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103 2318 // CHECK3-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]], i32 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] { 2319 // CHECK3-NEXT: entry: 2320 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 2321 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 2322 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4 2323 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 2324 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]]) 2325 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 2326 // CHECK3-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 2327 // CHECK3-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 2328 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 2329 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 2330 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 2331 // CHECK3-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) 2332 // CHECK3-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 2333 // CHECK3-NEXT: [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 2334 // CHECK3-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 2335 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 2336 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]]) 2337 // CHECK3-NEXT: ret void 2338 // 2339 // 2340 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. 2341 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { 2342 // CHECK3-NEXT: entry: 2343 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2344 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2345 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 2346 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2347 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 2348 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2349 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2350 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2351 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2352 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 2353 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2354 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2355 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 2356 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 2357 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 2358 // CHECK3-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 2359 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 2360 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 2361 // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 2362 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 2363 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 2364 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2365 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 2366 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2367 // CHECK3: cond.true: 2368 // CHECK3-NEXT: br label [[COND_END:%.*]] 2369 // CHECK3: cond.false: 2370 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2371 // CHECK3-NEXT: br label [[COND_END]] 2372 // CHECK3: cond.end: 2373 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 2374 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 2375 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 2376 // CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 2377 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2378 // CHECK3: omp.inner.for.cond: 2379 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2380 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2381 // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 2382 // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2383 // CHECK3: omp.inner.for.body: 2384 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2385 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 2386 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 2387 // CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4 2388 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2389 // CHECK3: omp.body.continue: 2390 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2391 // CHECK3: omp.inner.for.inc: 2392 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2393 // CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 2394 // CHECK3-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 2395 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] 2396 // CHECK3: omp.inner.for.end: 2397 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2398 // CHECK3: omp.loop.exit: 2399 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 2400 // CHECK3-NEXT: ret void 2401 // 2402 // 2403 // CHECK3-LABEL: define {{[^@]+}}@.omp_task_privates_map. 2404 // CHECK3-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], i16** noalias noundef [[TMP1:%.*]], [3 x i8*]** noalias noundef [[TMP2:%.*]], [3 x i8*]** noalias noundef [[TMP3:%.*]], [3 x i64]** noalias noundef [[TMP4:%.*]]) #[[ATTR4:[0-9]+]] { 2405 // CHECK3-NEXT: entry: 2406 // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 4 2407 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i16**, align 4 2408 // CHECK3-NEXT: [[DOTADDR2:%.*]] = alloca [3 x i8*]**, align 4 2409 // CHECK3-NEXT: [[DOTADDR3:%.*]] = alloca [3 x i8*]**, align 4 2410 // CHECK3-NEXT: [[DOTADDR4:%.*]] = alloca [3 x i64]**, align 4 2411 // CHECK3-NEXT: store %struct..kmp_privates.t* [[TMP0]], %struct..kmp_privates.t** [[DOTADDR]], align 4 2412 // CHECK3-NEXT: store i16** [[TMP1]], i16*** [[DOTADDR1]], align 4 2413 // CHECK3-NEXT: store [3 x i8*]** [[TMP2]], [3 x i8*]*** [[DOTADDR2]], align 4 2414 // CHECK3-NEXT: store [3 x i8*]** [[TMP3]], [3 x i8*]*** [[DOTADDR3]], align 4 2415 // CHECK3-NEXT: store [3 x i64]** [[TMP4]], [3 x i64]*** [[DOTADDR4]], align 4 2416 // CHECK3-NEXT: [[TMP5:%.*]] = load %struct..kmp_privates.t*, %struct..kmp_privates.t** [[DOTADDR]], align 4 2417 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 0 2418 // CHECK3-NEXT: [[TMP7:%.*]] = load [3 x i64]**, [3 x i64]*** [[DOTADDR4]], align 4 2419 // CHECK3-NEXT: store [3 x i64]* [[TMP6]], [3 x i64]** [[TMP7]], align 4 2420 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 1 2421 // CHECK3-NEXT: [[TMP9:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR2]], align 4 2422 // CHECK3-NEXT: store [3 x i8*]* [[TMP8]], [3 x i8*]** [[TMP9]], align 4 2423 // CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 2 2424 // CHECK3-NEXT: [[TMP11:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR3]], align 4 2425 // CHECK3-NEXT: store [3 x i8*]* [[TMP10]], [3 x i8*]** [[TMP11]], align 4 2426 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 3 2427 // CHECK3-NEXT: [[TMP13:%.*]] = load i16**, i16*** [[DOTADDR1]], align 4 2428 // CHECK3-NEXT: store i16* [[TMP12]], i16** [[TMP13]], align 4 2429 // CHECK3-NEXT: ret void 2430 // 2431 // 2432 // CHECK3-LABEL: define {{[^@]+}}@.omp_task_entry. 2433 // CHECK3-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { 2434 // CHECK3-NEXT: entry: 2435 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 2436 // CHECK3-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 4 2437 // CHECK3-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 4 2438 // CHECK3-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 4 2439 // CHECK3-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 4 2440 // CHECK3-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 4 2441 // CHECK3-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca i16*, align 4 2442 // CHECK3-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca [3 x i8*]*, align 4 2443 // CHECK3-NEXT: [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca [3 x i8*]*, align 4 2444 // CHECK3-NEXT: [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca [3 x i64]*, align 4 2445 // CHECK3-NEXT: [[AA_CASTED_I:%.*]] = alloca i32, align 4 2446 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__CASTED_I:%.*]] = alloca i32, align 4 2447 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__CASTED4_I:%.*]] = alloca i32, align 4 2448 // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 2449 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 4 2450 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 2451 // CHECK3-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4 2452 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 2453 // CHECK3-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4 2454 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0 2455 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 2456 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 2457 // CHECK3-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 4 2458 // CHECK3-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon* 2459 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1 2460 // CHECK3-NEXT: [[TMP10:%.*]] = bitcast %struct..kmp_privates.t* [[TMP9]] to i8* 2461 // CHECK3-NEXT: [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8* 2462 // CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META13:![0-9]+]]) 2463 // CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META16:![0-9]+]]) 2464 // CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]]) 2465 // CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]]) 2466 // CHECK3-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !22 2467 // CHECK3-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 4, !noalias !22 2468 // CHECK3-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !22 2469 // CHECK3-NEXT: store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* @.omp_task_privates_map. to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !22 2470 // CHECK3-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 4, !noalias !22 2471 // CHECK3-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !22 2472 // CHECK3-NEXT: [[TMP12:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !22 2473 // CHECK3-NEXT: [[TMP13:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !22 2474 // CHECK3-NEXT: [[TMP14:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !22 2475 // CHECK3-NEXT: [[TMP15:%.*]] = bitcast void (i8*, ...)* [[TMP13]] to void (i8*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* 2476 // CHECK3-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]] 2477 // CHECK3-NEXT: [[TMP16:%.*]] = load i16*, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 4, !noalias !22 2478 // CHECK3-NEXT: [[TMP17:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 4, !noalias !22 2479 // CHECK3-NEXT: [[TMP18:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 4, !noalias !22 2480 // CHECK3-NEXT: [[TMP19:%.*]] = load [3 x i64]*, [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 4, !noalias !22 2481 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP17]], i32 0, i32 0 2482 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP18]], i32 0, i32 0 2483 // CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[TMP19]], i32 0, i32 0 2484 // CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP12]], i32 0, i32 1 2485 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[TMP12]], i32 0, i32 2 2486 // CHECK3-NEXT: [[TMP25:%.*]] = load i32, i32* [[TMP23]], align 4 2487 // CHECK3-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP24]], align 4 2488 // CHECK3-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) #[[ATTR3]] 2489 // CHECK3-NEXT: [[TMP27:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 [[TMP25]], i32 [[TMP26]], i32 0, i8* null, i32 0, i8* null) #[[ATTR3]] 2490 // CHECK3-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0 2491 // CHECK3-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]] 2492 // CHECK3: omp_offload.failed.i: 2493 // CHECK3-NEXT: [[TMP29:%.*]] = load i16, i16* [[TMP16]], align 2 2494 // CHECK3-NEXT: [[CONV_I:%.*]] = bitcast i32* [[AA_CASTED_I]] to i16* 2495 // CHECK3-NEXT: store i16 [[TMP29]], i16* [[CONV_I]], align 2, !noalias !22 2496 // CHECK3-NEXT: [[TMP30:%.*]] = load i32, i32* [[AA_CASTED_I]], align 4, !noalias !22 2497 // CHECK3-NEXT: [[TMP31:%.*]] = load i32, i32* [[TMP23]], align 4 2498 // CHECK3-NEXT: store i32 [[TMP31]], i32* [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias !22 2499 // CHECK3-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias !22 2500 // CHECK3-NEXT: [[TMP33:%.*]] = load i32, i32* [[TMP24]], align 4 2501 // CHECK3-NEXT: store i32 [[TMP33]], i32* [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias !22 2502 // CHECK3-NEXT: [[TMP34:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias !22 2503 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103(i32 [[TMP30]], i32 [[TMP32]], i32 [[TMP34]]) #[[ATTR3]] 2504 // CHECK3-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]] 2505 // CHECK3: .omp_outlined..1.exit: 2506 // CHECK3-NEXT: ret i32 0 2507 // 2508 // 2509 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l107 2510 // CHECK3-SAME: (i32 noundef [[A:%.*]]) #[[ATTR2]] { 2511 // CHECK3-NEXT: entry: 2512 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2513 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 2514 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 2515 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 2516 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 2517 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 2518 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]]) 2519 // CHECK3-NEXT: ret void 2520 // 2521 // 2522 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..2 2523 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]]) #[[ATTR2]] { 2524 // CHECK3-NEXT: entry: 2525 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2526 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2527 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2528 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2529 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 2530 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2531 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2532 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2533 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2534 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 2535 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2536 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2537 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 2538 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 2539 // CHECK3-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 2540 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 2541 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 2542 // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 2543 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 2544 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 2545 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2546 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 2547 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2548 // CHECK3: cond.true: 2549 // CHECK3-NEXT: br label [[COND_END:%.*]] 2550 // CHECK3: cond.false: 2551 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2552 // CHECK3-NEXT: br label [[COND_END]] 2553 // CHECK3: cond.end: 2554 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 2555 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 2556 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 2557 // CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 2558 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2559 // CHECK3: omp.inner.for.cond: 2560 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2561 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2562 // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 2563 // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2564 // CHECK3: omp.inner.for.body: 2565 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2566 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 2567 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 2568 // CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4 2569 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 2570 // CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 2571 // CHECK3-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4 2572 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2573 // CHECK3: omp.body.continue: 2574 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2575 // CHECK3: omp.inner.for.inc: 2576 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2577 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1 2578 // CHECK3-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4 2579 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] 2580 // CHECK3: omp.inner.for.end: 2581 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2582 // CHECK3: omp.loop.exit: 2583 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 2584 // CHECK3-NEXT: ret void 2585 // 2586 // 2587 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113 2588 // CHECK3-SAME: (i32 noundef [[AA:%.*]]) #[[ATTR2]] { 2589 // CHECK3-NEXT: entry: 2590 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 2591 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 2592 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 2593 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 2594 // CHECK3-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 2595 // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 2596 // CHECK3-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 2597 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 2598 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP1]]) 2599 // CHECK3-NEXT: ret void 2600 // 2601 // 2602 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..3 2603 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { 2604 // CHECK3-NEXT: entry: 2605 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2606 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2607 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 2608 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2609 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 2610 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2611 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2612 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2613 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2614 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 2615 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2616 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2617 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 2618 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 2619 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 2620 // CHECK3-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 2621 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 2622 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 2623 // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 2624 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 2625 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 2626 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2627 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 2628 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2629 // CHECK3: cond.true: 2630 // CHECK3-NEXT: br label [[COND_END:%.*]] 2631 // CHECK3: cond.false: 2632 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2633 // CHECK3-NEXT: br label [[COND_END]] 2634 // CHECK3: cond.end: 2635 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 2636 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 2637 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 2638 // CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 2639 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2640 // CHECK3: omp.inner.for.cond: 2641 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2642 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2643 // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 2644 // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2645 // CHECK3: omp.inner.for.body: 2646 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2647 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 2648 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 2649 // CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4 2650 // CHECK3-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 2 2651 // CHECK3-NEXT: [[CONV2:%.*]] = sext i16 [[TMP8]] to i32 2652 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 2653 // CHECK3-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 2654 // CHECK3-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2 2655 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2656 // CHECK3: omp.body.continue: 2657 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2658 // CHECK3: omp.inner.for.inc: 2659 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2660 // CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP9]], 1 2661 // CHECK3-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 2662 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] 2663 // CHECK3: omp.inner.for.end: 2664 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2665 // CHECK3: omp.loop.exit: 2666 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 2667 // CHECK3-NEXT: ret void 2668 // 2669 // 2670 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120 2671 // CHECK3-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { 2672 // CHECK3-NEXT: entry: 2673 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2674 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 2675 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 2676 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 2677 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 2678 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 2679 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 2680 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 2681 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 2682 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 2683 // CHECK3-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 2684 // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 2685 // CHECK3-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 2686 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 2687 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) 2688 // CHECK3-NEXT: ret void 2689 // 2690 // 2691 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..6 2692 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { 2693 // CHECK3-NEXT: entry: 2694 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2695 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2696 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2697 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 2698 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2699 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 2700 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2701 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2702 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2703 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2704 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 2705 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2706 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2707 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 2708 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 2709 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 2710 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 2711 // CHECK3-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 2712 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 2713 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 2714 // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 2715 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 2716 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 2717 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2718 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 2719 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2720 // CHECK3: cond.true: 2721 // CHECK3-NEXT: br label [[COND_END:%.*]] 2722 // CHECK3: cond.false: 2723 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2724 // CHECK3-NEXT: br label [[COND_END]] 2725 // CHECK3: cond.end: 2726 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 2727 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 2728 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 2729 // CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 2730 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2731 // CHECK3: omp.inner.for.cond: 2732 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2733 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2734 // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 2735 // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2736 // CHECK3: omp.inner.for.body: 2737 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2738 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 2739 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 2740 // CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4 2741 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 2742 // CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 2743 // CHECK3-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4 2744 // CHECK3-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 2 2745 // CHECK3-NEXT: [[CONV3:%.*]] = sext i16 [[TMP9]] to i32 2746 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 2747 // CHECK3-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 2748 // CHECK3-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2 2749 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2750 // CHECK3: omp.body.continue: 2751 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2752 // CHECK3: omp.inner.for.inc: 2753 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2754 // CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP10]], 1 2755 // CHECK3-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 2756 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] 2757 // CHECK3: omp.inner.for.end: 2758 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2759 // CHECK3: omp.loop.exit: 2760 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 2761 // CHECK3-NEXT: ret void 2762 // 2763 // 2764 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145 2765 // CHECK3-SAME: (i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { 2766 // CHECK3-NEXT: entry: 2767 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2768 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 2769 // CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 2770 // CHECK3-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 2771 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 2772 // CHECK3-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 2773 // CHECK3-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 2774 // CHECK3-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 2775 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 2776 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 2777 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 2778 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 2779 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 2780 // CHECK3-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 2781 // CHECK3-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 2782 // CHECK3-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 2783 // CHECK3-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 2784 // CHECK3-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 2785 // CHECK3-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 2786 // CHECK3-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 2787 // CHECK3-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 2788 // CHECK3-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 2789 // CHECK3-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 2790 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 2791 // CHECK3-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 2792 // CHECK3-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 2793 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 2794 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 2795 // CHECK3-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 2796 // CHECK3-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 2797 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 2798 // CHECK3-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4 2799 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4 2800 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 2801 // CHECK3-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 2802 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 2803 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*, i32)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i32 [[TMP11]]) 2804 // CHECK3-NEXT: ret void 2805 // 2806 // 2807 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..9 2808 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { 2809 // CHECK3-NEXT: entry: 2810 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2811 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2812 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2813 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 2814 // CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 2815 // CHECK3-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 2816 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 2817 // CHECK3-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 2818 // CHECK3-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 2819 // CHECK3-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 2820 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 2821 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 2822 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2823 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 2824 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2825 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2826 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2827 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2828 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 2829 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2830 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2831 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 2832 // CHECK3-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 2833 // CHECK3-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 2834 // CHECK3-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 2835 // CHECK3-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 2836 // CHECK3-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 2837 // CHECK3-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 2838 // CHECK3-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 2839 // CHECK3-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 2840 // CHECK3-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 2841 // CHECK3-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 2842 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 2843 // CHECK3-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 2844 // CHECK3-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 2845 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 2846 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 2847 // CHECK3-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 2848 // CHECK3-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 2849 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 2850 // CHECK3-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 2851 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 2852 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 2853 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 2854 // CHECK3-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 2855 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 2856 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) 2857 // CHECK3-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 2858 // CHECK3: omp.dispatch.cond: 2859 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2860 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 9 2861 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2862 // CHECK3: cond.true: 2863 // CHECK3-NEXT: br label [[COND_END:%.*]] 2864 // CHECK3: cond.false: 2865 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2866 // CHECK3-NEXT: br label [[COND_END]] 2867 // CHECK3: cond.end: 2868 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] 2869 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 2870 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 2871 // CHECK3-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 2872 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2873 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2874 // CHECK3-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] 2875 // CHECK3-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 2876 // CHECK3: omp.dispatch.body: 2877 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2878 // CHECK3: omp.inner.for.cond: 2879 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23 2880 // CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !23 2881 // CHECK3-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] 2882 // CHECK3-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2883 // CHECK3: omp.inner.for.body: 2884 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23 2885 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 2886 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 2887 // CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !23 2888 // CHECK3-NEXT: [[TMP19:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !23 2889 // CHECK3-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP19]], 1 2890 // CHECK3-NEXT: store i32 [[ADD7]], i32* [[A_ADDR]], align 4, !llvm.access.group !23 2891 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2 2892 // CHECK3-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !23 2893 // CHECK3-NEXT: [[CONV:%.*]] = fpext float [[TMP20]] to double 2894 // CHECK3-NEXT: [[ADD8:%.*]] = fadd double [[CONV]], 1.000000e+00 2895 // CHECK3-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float 2896 // CHECK3-NEXT: store float [[CONV9]], float* [[ARRAYIDX]], align 4, !llvm.access.group !23 2897 // CHECK3-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3 2898 // CHECK3-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX10]], align 4, !llvm.access.group !23 2899 // CHECK3-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double 2900 // CHECK3-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00 2901 // CHECK3-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float 2902 // CHECK3-NEXT: store float [[CONV13]], float* [[ARRAYIDX10]], align 4, !llvm.access.group !23 2903 // CHECK3-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1 2904 // CHECK3-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX14]], i32 0, i32 2 2905 // CHECK3-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX15]], align 8, !llvm.access.group !23 2906 // CHECK3-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00 2907 // CHECK3-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8, !llvm.access.group !23 2908 // CHECK3-NEXT: [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]] 2909 // CHECK3-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP23]] 2910 // CHECK3-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX17]], i32 3 2911 // CHECK3-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX18]], align 8, !llvm.access.group !23 2912 // CHECK3-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00 2913 // CHECK3-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8, !llvm.access.group !23 2914 // CHECK3-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 2915 // CHECK3-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 4, !llvm.access.group !23 2916 // CHECK3-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1 2917 // CHECK3-NEXT: store i64 [[ADD20]], i64* [[X]], align 4, !llvm.access.group !23 2918 // CHECK3-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 2919 // CHECK3-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 4, !llvm.access.group !23 2920 // CHECK3-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i32 2921 // CHECK3-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1 2922 // CHECK3-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8 2923 // CHECK3-NEXT: store i8 [[CONV23]], i8* [[Y]], align 4, !llvm.access.group !23 2924 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2925 // CHECK3: omp.body.continue: 2926 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2927 // CHECK3: omp.inner.for.inc: 2928 // CHECK3-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23 2929 // CHECK3-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1 2930 // CHECK3-NEXT: store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23 2931 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP24:![0-9]+]] 2932 // CHECK3: omp.inner.for.end: 2933 // CHECK3-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 2934 // CHECK3: omp.dispatch.inc: 2935 // CHECK3-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 2936 // CHECK3-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 2937 // CHECK3-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] 2938 // CHECK3-NEXT: store i32 [[ADD25]], i32* [[DOTOMP_LB]], align 4 2939 // CHECK3-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2940 // CHECK3-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 2941 // CHECK3-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] 2942 // CHECK3-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_UB]], align 4 2943 // CHECK3-NEXT: br label [[OMP_DISPATCH_COND]] 2944 // CHECK3: omp.dispatch.end: 2945 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]]) 2946 // CHECK3-NEXT: ret void 2947 // 2948 // 2949 // CHECK3-LABEL: define {{[^@]+}}@_Z3bari 2950 // CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { 2951 // CHECK3-NEXT: entry: 2952 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 2953 // CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4 2954 // CHECK3-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 2955 // CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 2956 // CHECK3-NEXT: store i32 0, i32* [[A]], align 4 2957 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 2958 // CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]]) 2959 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 2960 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 2961 // CHECK3-NEXT: store i32 [[ADD]], i32* [[A]], align 4 2962 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 2963 // CHECK3-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP2]]) 2964 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 2965 // CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 2966 // CHECK3-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 2967 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 2968 // CHECK3-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]]) 2969 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 2970 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 2971 // CHECK3-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 2972 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 2973 // CHECK3-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]]) 2974 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 2975 // CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] 2976 // CHECK3-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 2977 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 2978 // CHECK3-NEXT: ret i32 [[TMP8]] 2979 // 2980 // 2981 // CHECK3-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 2982 // CHECK3-SAME: (%struct.S1* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 { 2983 // CHECK3-NEXT: entry: 2984 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 2985 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 2986 // CHECK3-NEXT: [[B:%.*]] = alloca i32, align 4 2987 // CHECK3-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 2988 // CHECK3-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 2989 // CHECK3-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 2990 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4 2991 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4 2992 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4 2993 // CHECK3-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 4 2994 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 2995 // CHECK3-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 2996 // CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 2997 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 2998 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 2999 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 3000 // CHECK3-NEXT: store i32 [[ADD]], i32* [[B]], align 4 3001 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 3002 // CHECK3-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() 3003 // CHECK3-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 3004 // CHECK3-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] 3005 // CHECK3-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 3006 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 3007 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[B]], align 4 3008 // CHECK3-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 3009 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 3010 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 3011 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 60 3012 // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 3013 // CHECK3: omp_if.then: 3014 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 3015 // CHECK3-NEXT: [[TMP7:%.*]] = mul nuw i32 2, [[TMP1]] 3016 // CHECK3-NEXT: [[TMP8:%.*]] = mul nuw i32 [[TMP7]], 2 3017 // CHECK3-NEXT: [[TMP9:%.*]] = sext i32 [[TMP8]] to i64 3018 // CHECK3-NEXT: [[TMP10:%.*]] = bitcast [5 x i64]* [[DOTOFFLOAD_SIZES]] to i8* 3019 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP10]], i8* align 4 bitcast ([5 x i64]* @.offload_sizes.13 to i8*), i32 40, i1 false) 3020 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3021 // CHECK3-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to %struct.S1** 3022 // CHECK3-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP12]], align 4 3023 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3024 // CHECK3-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to double** 3025 // CHECK3-NEXT: store double* [[A]], double** [[TMP14]], align 4 3026 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 3027 // CHECK3-NEXT: store i8* null, i8** [[TMP15]], align 4 3028 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 3029 // CHECK3-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32* 3030 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[TMP17]], align 4 3031 // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 3032 // CHECK3-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32* 3033 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[TMP19]], align 4 3034 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 3035 // CHECK3-NEXT: store i8* null, i8** [[TMP20]], align 4 3036 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 3037 // CHECK3-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i32* 3038 // CHECK3-NEXT: store i32 2, i32* [[TMP22]], align 4 3039 // CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 3040 // CHECK3-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i32* 3041 // CHECK3-NEXT: store i32 2, i32* [[TMP24]], align 4 3042 // CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 3043 // CHECK3-NEXT: store i8* null, i8** [[TMP25]], align 4 3044 // CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 3045 // CHECK3-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i32* 3046 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP27]], align 4 3047 // CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 3048 // CHECK3-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i32* 3049 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP29]], align 4 3050 // CHECK3-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 3051 // CHECK3-NEXT: store i8* null, i8** [[TMP30]], align 4 3052 // CHECK3-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 3053 // CHECK3-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i16** 3054 // CHECK3-NEXT: store i16* [[VLA]], i16** [[TMP32]], align 4 3055 // CHECK3-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 3056 // CHECK3-NEXT: [[TMP34:%.*]] = bitcast i8** [[TMP33]] to i16** 3057 // CHECK3-NEXT: store i16* [[VLA]], i16** [[TMP34]], align 4 3058 // CHECK3-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 3059 // CHECK3-NEXT: store i64 [[TMP9]], i64* [[TMP35]], align 4 3060 // CHECK3-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 3061 // CHECK3-NEXT: store i8* null, i8** [[TMP36]], align 4 3062 // CHECK3-NEXT: [[TMP37:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3063 // CHECK3-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3064 // CHECK3-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 3065 // CHECK3-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) 3066 // CHECK3-NEXT: [[TMP40:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218.region_id, i32 5, i8** [[TMP37]], i8** [[TMP38]], i64* [[TMP39]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.14, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 3067 // CHECK3-NEXT: [[TMP41:%.*]] = icmp ne i32 [[TMP40]], 0 3068 // CHECK3-NEXT: br i1 [[TMP41]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 3069 // CHECK3: omp_offload.failed: 3070 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR3]] 3071 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 3072 // CHECK3: omp_offload.cont: 3073 // CHECK3-NEXT: br label [[OMP_IF_END:%.*]] 3074 // CHECK3: omp_if.else: 3075 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR3]] 3076 // CHECK3-NEXT: br label [[OMP_IF_END]] 3077 // CHECK3: omp_if.end: 3078 // CHECK3-NEXT: [[TMP42:%.*]] = mul nsw i32 1, [[TMP1]] 3079 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP42]] 3080 // CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 3081 // CHECK3-NEXT: [[TMP43:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2 3082 // CHECK3-NEXT: [[CONV:%.*]] = sext i16 [[TMP43]] to i32 3083 // CHECK3-NEXT: [[TMP44:%.*]] = load i32, i32* [[B]], align 4 3084 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP44]] 3085 // CHECK3-NEXT: [[TMP45:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 3086 // CHECK3-NEXT: call void @llvm.stackrestore(i8* [[TMP45]]) 3087 // CHECK3-NEXT: ret i32 [[ADD3]] 3088 // 3089 // 3090 // CHECK3-LABEL: define {{[^@]+}}@_ZL7fstatici 3091 // CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { 3092 // CHECK3-NEXT: entry: 3093 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 3094 // CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4 3095 // CHECK3-NEXT: [[AA:%.*]] = alloca i16, align 2 3096 // CHECK3-NEXT: [[AAA:%.*]] = alloca i8, align 1 3097 // CHECK3-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 3098 // CHECK3-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 3099 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 3100 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 3101 // CHECK3-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 3102 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4 3103 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4 3104 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4 3105 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 3106 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 3107 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 3108 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4 3109 // CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 3110 // CHECK3-NEXT: store i32 0, i32* [[A]], align 4 3111 // CHECK3-NEXT: store i16 0, i16* [[AA]], align 2 3112 // CHECK3-NEXT: store i8 0, i8* [[AAA]], align 1 3113 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 3114 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[N_CASTED]], align 4 3115 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_CASTED]], align 4 3116 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 3117 // CHECK3-NEXT: store i32 [[TMP2]], i32* [[A_CASTED]], align 4 3118 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_CASTED]], align 4 3119 // CHECK3-NEXT: [[TMP4:%.*]] = load i16, i16* [[AA]], align 2 3120 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 3121 // CHECK3-NEXT: store i16 [[TMP4]], i16* [[CONV]], align 2 3122 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[AA_CASTED]], align 4 3123 // CHECK3-NEXT: [[TMP6:%.*]] = load i8, i8* [[AAA]], align 1 3124 // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* 3125 // CHECK3-NEXT: store i8 [[TMP6]], i8* [[CONV1]], align 1 3126 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 3127 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[N_ADDR]], align 4 3128 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP8]], 50 3129 // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 3130 // CHECK3: omp_if.then: 3131 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3132 // CHECK3-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* 3133 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP10]], align 4 3134 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3135 // CHECK3-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32* 3136 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP12]], align 4 3137 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 3138 // CHECK3-NEXT: store i8* null, i8** [[TMP13]], align 4 3139 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 3140 // CHECK3-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32* 3141 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP15]], align 4 3142 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 3143 // CHECK3-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32* 3144 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP17]], align 4 3145 // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 3146 // CHECK3-NEXT: store i8* null, i8** [[TMP18]], align 4 3147 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 3148 // CHECK3-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32* 3149 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[TMP20]], align 4 3150 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 3151 // CHECK3-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i32* 3152 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[TMP22]], align 4 3153 // CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 3154 // CHECK3-NEXT: store i8* null, i8** [[TMP23]], align 4 3155 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 3156 // CHECK3-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i32* 3157 // CHECK3-NEXT: store i32 [[TMP7]], i32* [[TMP25]], align 4 3158 // CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 3159 // CHECK3-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i32* 3160 // CHECK3-NEXT: store i32 [[TMP7]], i32* [[TMP27]], align 4 3161 // CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 3162 // CHECK3-NEXT: store i8* null, i8** [[TMP28]], align 4 3163 // CHECK3-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 3164 // CHECK3-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to [10 x i32]** 3165 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP30]], align 4 3166 // CHECK3-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 3167 // CHECK3-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to [10 x i32]** 3168 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP32]], align 4 3169 // CHECK3-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 3170 // CHECK3-NEXT: store i8* null, i8** [[TMP33]], align 4 3171 // CHECK3-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3172 // CHECK3-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3173 // CHECK3-NEXT: [[TMP36:%.*]] = load i32, i32* [[A]], align 4 3174 // CHECK3-NEXT: store i32 [[TMP36]], i32* [[DOTCAPTURE_EXPR_]], align 4 3175 // CHECK3-NEXT: [[TMP37:%.*]] = load i32, i32* [[N_ADDR]], align 4 3176 // CHECK3-NEXT: store i32 [[TMP37]], i32* [[DOTCAPTURE_EXPR_2]], align 4 3177 // CHECK3-NEXT: [[TMP38:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 3178 // CHECK3-NEXT: [[TMP39:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 3179 // CHECK3-NEXT: [[SUB:%.*]] = sub i32 [[TMP38]], [[TMP39]] 3180 // CHECK3-NEXT: [[SUB4:%.*]] = sub i32 [[SUB]], 1 3181 // CHECK3-NEXT: [[ADD:%.*]] = add i32 [[SUB4]], 1 3182 // CHECK3-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 3183 // CHECK3-NEXT: [[SUB5:%.*]] = sub i32 [[DIV]], 1 3184 // CHECK3-NEXT: store i32 [[SUB5]], i32* [[DOTCAPTURE_EXPR_3]], align 4 3185 // CHECK3-NEXT: [[TMP40:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 3186 // CHECK3-NEXT: [[ADD6:%.*]] = add i32 [[TMP40]], 1 3187 // CHECK3-NEXT: [[TMP41:%.*]] = zext i32 [[ADD6]] to i64 3188 // CHECK3-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 [[TMP41]]) 3189 // CHECK3-NEXT: [[TMP42:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200.region_id, i32 5, i8** [[TMP34]], i8** [[TMP35]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes.16, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.17, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 3190 // CHECK3-NEXT: [[TMP43:%.*]] = icmp ne i32 [[TMP42]], 0 3191 // CHECK3-NEXT: br i1 [[TMP43]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 3192 // CHECK3: omp_offload.failed: 3193 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], i32 [[TMP7]], [10 x i32]* [[B]]) #[[ATTR3]] 3194 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 3195 // CHECK3: omp_offload.cont: 3196 // CHECK3-NEXT: br label [[OMP_IF_END:%.*]] 3197 // CHECK3: omp_if.else: 3198 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], i32 [[TMP7]], [10 x i32]* [[B]]) #[[ATTR3]] 3199 // CHECK3-NEXT: br label [[OMP_IF_END]] 3200 // CHECK3: omp_if.end: 3201 // CHECK3-NEXT: [[TMP44:%.*]] = load i32, i32* [[A]], align 4 3202 // CHECK3-NEXT: ret i32 [[TMP44]] 3203 // 3204 // 3205 // CHECK3-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 3206 // CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat { 3207 // CHECK3-NEXT: entry: 3208 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 3209 // CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4 3210 // CHECK3-NEXT: [[AA:%.*]] = alloca i16, align 2 3211 // CHECK3-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 3212 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 3213 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 3214 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 3215 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 3216 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 3217 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 3218 // CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 3219 // CHECK3-NEXT: store i32 0, i32* [[A]], align 4 3220 // CHECK3-NEXT: store i16 0, i16* [[AA]], align 2 3221 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 3222 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 3223 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 3224 // CHECK3-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 3225 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 3226 // CHECK3-NEXT: store i16 [[TMP2]], i16* [[CONV]], align 2 3227 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 3228 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 3229 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40 3230 // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 3231 // CHECK3: omp_if.then: 3232 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3233 // CHECK3-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i32* 3234 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP6]], align 4 3235 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3236 // CHECK3-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* 3237 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4 3238 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 3239 // CHECK3-NEXT: store i8* null, i8** [[TMP9]], align 4 3240 // CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 3241 // CHECK3-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i32* 3242 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP11]], align 4 3243 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 3244 // CHECK3-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* 3245 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4 3246 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 3247 // CHECK3-NEXT: store i8* null, i8** [[TMP14]], align 4 3248 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 3249 // CHECK3-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]** 3250 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 4 3251 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 3252 // CHECK3-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]** 3253 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 4 3254 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 3255 // CHECK3-NEXT: store i8* null, i8** [[TMP19]], align 4 3256 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3257 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3258 // CHECK3-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) 3259 // CHECK3-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.19, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.20, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 3260 // CHECK3-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 3261 // CHECK3-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 3262 // CHECK3: omp_offload.failed: 3263 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]] 3264 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 3265 // CHECK3: omp_offload.cont: 3266 // CHECK3-NEXT: br label [[OMP_IF_END:%.*]] 3267 // CHECK3: omp_if.else: 3268 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]] 3269 // CHECK3-NEXT: br label [[OMP_IF_END]] 3270 // CHECK3: omp_if.end: 3271 // CHECK3-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4 3272 // CHECK3-NEXT: ret i32 [[TMP24]] 3273 // 3274 // 3275 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218 3276 // CHECK3-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { 3277 // CHECK3-NEXT: entry: 3278 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 3279 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 3280 // CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 3281 // CHECK3-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 3282 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 3283 // CHECK3-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 3284 // CHECK3-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 3285 // CHECK3-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 3286 // CHECK3-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 3287 // CHECK3-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 3288 // CHECK3-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 3289 // CHECK3-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 3290 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 3291 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 3292 // CHECK3-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 3293 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 3294 // CHECK3-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 3295 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 3296 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..12 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]]) 3297 // CHECK3-NEXT: ret void 3298 // 3299 // 3300 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..12 3301 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { 3302 // CHECK3-NEXT: entry: 3303 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 3304 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 3305 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 3306 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 3307 // CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 3308 // CHECK3-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 3309 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 3310 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 3311 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 3312 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 3313 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 3314 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 3315 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 3316 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 3317 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 3318 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 3319 // CHECK3-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 3320 // CHECK3-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 3321 // CHECK3-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 3322 // CHECK3-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 3323 // CHECK3-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 3324 // CHECK3-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 3325 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 3326 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 3327 // CHECK3-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 3328 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 3329 // CHECK3-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 3330 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 3331 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 3332 // CHECK3-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 3333 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 3334 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 3335 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 3336 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 9 3337 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 3338 // CHECK3: cond.true: 3339 // CHECK3-NEXT: br label [[COND_END:%.*]] 3340 // CHECK3: cond.false: 3341 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 3342 // CHECK3-NEXT: br label [[COND_END]] 3343 // CHECK3: cond.end: 3344 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 3345 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 3346 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 3347 // CHECK3-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 3348 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 3349 // CHECK3: omp.inner.for.cond: 3350 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 3351 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 3352 // CHECK3-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 3353 // CHECK3-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 3354 // CHECK3: omp.inner.for.body: 3355 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 3356 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 3357 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 3358 // CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4 3359 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[B_ADDR]], align 4 3360 // CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP12]] to double 3361 // CHECK3-NEXT: [[ADD4:%.*]] = fadd double [[CONV]], 1.500000e+00 3362 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 3363 // CHECK3-NEXT: store double [[ADD4]], double* [[A]], align 4 3364 // CHECK3-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 3365 // CHECK3-NEXT: [[TMP13:%.*]] = load double, double* [[A5]], align 4 3366 // CHECK3-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 3367 // CHECK3-NEXT: store double [[INC]], double* [[A5]], align 4 3368 // CHECK3-NEXT: [[CONV6:%.*]] = fptosi double [[INC]] to i16 3369 // CHECK3-NEXT: [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]] 3370 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP14]] 3371 // CHECK3-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 3372 // CHECK3-NEXT: store i16 [[CONV6]], i16* [[ARRAYIDX7]], align 2 3373 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 3374 // CHECK3: omp.body.continue: 3375 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 3376 // CHECK3: omp.inner.for.inc: 3377 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 3378 // CHECK3-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP15]], 1 3379 // CHECK3-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 3380 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] 3381 // CHECK3: omp.inner.for.end: 3382 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 3383 // CHECK3: omp.loop.exit: 3384 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 3385 // CHECK3-NEXT: ret void 3386 // 3387 // 3388 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200 3389 // CHECK3-SAME: (i32 noundef [[N:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 3390 // CHECK3-NEXT: entry: 3391 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 3392 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3393 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 3394 // CHECK3-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 3395 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 3396 // CHECK3-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 3397 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 3398 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 3399 // CHECK3-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 3400 // CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 3401 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 3402 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 3403 // CHECK3-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 3404 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 3405 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 3406 // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 3407 // CHECK3-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 3408 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 3409 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[N_CASTED]], align 4 3410 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_CASTED]], align 4 3411 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4 3412 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4 3413 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4 3414 // CHECK3-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 2 3415 // CHECK3-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 3416 // CHECK3-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2 3417 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[AA_CASTED]], align 4 3418 // CHECK3-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV1]], align 1 3419 // CHECK3-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* 3420 // CHECK3-NEXT: store i8 [[TMP7]], i8* [[CONV3]], align 1 3421 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 3422 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, [10 x i32]*)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP8]], [10 x i32]* [[TMP0]]) 3423 // CHECK3-NEXT: ret void 3424 // 3425 // 3426 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..15 3427 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 3428 // CHECK3-NEXT: entry: 3429 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 3430 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 3431 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 3432 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3433 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 3434 // CHECK3-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 3435 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 3436 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 3437 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 3438 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 3439 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 3440 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4 3441 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 3442 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 3443 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 3444 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 3445 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 3446 // CHECK3-NEXT: [[I6:%.*]] = alloca i32, align 4 3447 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 3448 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 3449 // CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 3450 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 3451 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 3452 // CHECK3-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 3453 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 3454 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 3455 // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 3456 // CHECK3-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 3457 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 3458 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 3459 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 3460 // CHECK3-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4 3461 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 3462 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 3463 // CHECK3-NEXT: [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]] 3464 // CHECK3-NEXT: [[SUB4:%.*]] = sub i32 [[SUB]], 1 3465 // CHECK3-NEXT: [[ADD:%.*]] = add i32 [[SUB4]], 1 3466 // CHECK3-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 3467 // CHECK3-NEXT: [[SUB5:%.*]] = sub i32 [[DIV]], 1 3468 // CHECK3-NEXT: store i32 [[SUB5]], i32* [[DOTCAPTURE_EXPR_3]], align 4 3469 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 3470 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[I]], align 4 3471 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 3472 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 3473 // CHECK3-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]] 3474 // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] 3475 // CHECK3: omp.precond.then: 3476 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 3477 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 3478 // CHECK3-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_UB]], align 4 3479 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 3480 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 3481 // CHECK3-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 3482 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 3483 // CHECK3-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 3484 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 3485 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 3486 // CHECK3-NEXT: [[CMP7:%.*]] = icmp ugt i32 [[TMP11]], [[TMP12]] 3487 // CHECK3-NEXT: br i1 [[CMP7]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 3488 // CHECK3: cond.true: 3489 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 3490 // CHECK3-NEXT: br label [[COND_END:%.*]] 3491 // CHECK3: cond.false: 3492 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 3493 // CHECK3-NEXT: br label [[COND_END]] 3494 // CHECK3: cond.end: 3495 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ] 3496 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 3497 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 3498 // CHECK3-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4 3499 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 3500 // CHECK3: omp.inner.for.cond: 3501 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 3502 // CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 3503 // CHECK3-NEXT: [[ADD8:%.*]] = add i32 [[TMP17]], 1 3504 // CHECK3-NEXT: [[CMP9:%.*]] = icmp ult i32 [[TMP16]], [[ADD8]] 3505 // CHECK3-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 3506 // CHECK3: omp.inner.for.body: 3507 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 3508 // CHECK3-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 3509 // CHECK3-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 1 3510 // CHECK3-NEXT: [[ADD10:%.*]] = add i32 [[TMP18]], [[MUL]] 3511 // CHECK3-NEXT: store i32 [[ADD10]], i32* [[I6]], align 4 3512 // CHECK3-NEXT: [[TMP20:%.*]] = load i32, i32* [[A_ADDR]], align 4 3513 // CHECK3-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP20]], 1 3514 // CHECK3-NEXT: store i32 [[ADD11]], i32* [[A_ADDR]], align 4 3515 // CHECK3-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV]], align 2 3516 // CHECK3-NEXT: [[CONV12:%.*]] = sext i16 [[TMP21]] to i32 3517 // CHECK3-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1 3518 // CHECK3-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16 3519 // CHECK3-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 2 3520 // CHECK3-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV1]], align 1 3521 // CHECK3-NEXT: [[CONV15:%.*]] = sext i8 [[TMP22]] to i32 3522 // CHECK3-NEXT: [[ADD16:%.*]] = add nsw i32 [[CONV15]], 1 3523 // CHECK3-NEXT: [[CONV17:%.*]] = trunc i32 [[ADD16]] to i8 3524 // CHECK3-NEXT: store i8 [[CONV17]], i8* [[CONV1]], align 1 3525 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 3526 // CHECK3-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 3527 // CHECK3-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP23]], 1 3528 // CHECK3-NEXT: store i32 [[ADD18]], i32* [[ARRAYIDX]], align 4 3529 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 3530 // CHECK3: omp.body.continue: 3531 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 3532 // CHECK3: omp.inner.for.inc: 3533 // CHECK3-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 3534 // CHECK3-NEXT: [[ADD19:%.*]] = add i32 [[TMP24]], 1 3535 // CHECK3-NEXT: store i32 [[ADD19]], i32* [[DOTOMP_IV]], align 4 3536 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] 3537 // CHECK3: omp.inner.for.end: 3538 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 3539 // CHECK3: omp.loop.exit: 3540 // CHECK3-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 3541 // CHECK3-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 3542 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) 3543 // CHECK3-NEXT: br label [[OMP_PRECOND_END]] 3544 // CHECK3: omp.precond.end: 3545 // CHECK3-NEXT: ret void 3546 // 3547 // 3548 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183 3549 // CHECK3-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 3550 // CHECK3-NEXT: entry: 3551 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3552 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 3553 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 3554 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 3555 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 3556 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 3557 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 3558 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 3559 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 3560 // CHECK3-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 3561 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 3562 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 3563 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 3564 // CHECK3-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 3565 // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 3566 // CHECK3-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 3567 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 3568 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..18 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) 3569 // CHECK3-NEXT: ret void 3570 // 3571 // 3572 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..18 3573 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 3574 // CHECK3-NEXT: entry: 3575 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 3576 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 3577 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3578 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 3579 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 3580 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 3581 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 3582 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 3583 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 3584 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 3585 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 3586 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 3587 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 3588 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 3589 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 3590 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 3591 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 3592 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 3593 // CHECK3-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 3594 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 3595 // CHECK3-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 3596 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 3597 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 3598 // CHECK3-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 3599 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 3600 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 3601 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 3602 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 3603 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 3604 // CHECK3: cond.true: 3605 // CHECK3-NEXT: br label [[COND_END:%.*]] 3606 // CHECK3: cond.false: 3607 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 3608 // CHECK3-NEXT: br label [[COND_END]] 3609 // CHECK3: cond.end: 3610 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 3611 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 3612 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 3613 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 3614 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 3615 // CHECK3: omp.inner.for.cond: 3616 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 3617 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 3618 // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] 3619 // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 3620 // CHECK3: omp.inner.for.body: 3621 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 3622 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 3623 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 3624 // CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4 3625 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4 3626 // CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 3627 // CHECK3-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4 3628 // CHECK3-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 2 3629 // CHECK3-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32 3630 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 3631 // CHECK3-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 3632 // CHECK3-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2 3633 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 3634 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 3635 // CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1 3636 // CHECK3-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 3637 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 3638 // CHECK3: omp.body.continue: 3639 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 3640 // CHECK3: omp.inner.for.inc: 3641 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 3642 // CHECK3-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP12]], 1 3643 // CHECK3-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 3644 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] 3645 // CHECK3: omp.inner.for.end: 3646 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 3647 // CHECK3: omp.loop.exit: 3648 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) 3649 // CHECK3-NEXT: ret void 3650 // 3651 // 3652 // CHECK3-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 3653 // CHECK3-SAME: () #[[ATTR4]] { 3654 // CHECK3-NEXT: entry: 3655 // CHECK3-NEXT: call void @__tgt_register_requires(i64 1) 3656 // CHECK3-NEXT: ret void 3657 // 3658 // 3659 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103 3660 // CHECK9-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { 3661 // CHECK9-NEXT: entry: 3662 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 3663 // CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 3664 // CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8 3665 // CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 3666 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) 3667 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 3668 // CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 3669 // CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8 3670 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 3671 // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* 3672 // CHECK9-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32* 3673 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 4 3674 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 4 3675 // CHECK9-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) 3676 // CHECK9-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 3677 // CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 3678 // CHECK9-NEXT: store i16 [[TMP3]], i16* [[CONV5]], align 2 3679 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 3680 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]]) 3681 // CHECK9-NEXT: ret void 3682 // 3683 // 3684 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. 3685 // CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { 3686 // CHECK9-NEXT: entry: 3687 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 3688 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 3689 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 3690 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 3691 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 3692 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 3693 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 3694 // CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 3695 // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 3696 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 3697 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 3698 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 3699 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 3700 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 3701 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 3702 // CHECK9-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 3703 // CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 3704 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 3705 // CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 3706 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 3707 // CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 3708 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 3709 // CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 3710 // CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 3711 // CHECK9: cond.true: 3712 // CHECK9-NEXT: br label [[COND_END:%.*]] 3713 // CHECK9: cond.false: 3714 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 3715 // CHECK9-NEXT: br label [[COND_END]] 3716 // CHECK9: cond.end: 3717 // CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 3718 // CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 3719 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 3720 // CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 3721 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 3722 // CHECK9: omp.inner.for.cond: 3723 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 3724 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 3725 // CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 3726 // CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 3727 // CHECK9: omp.inner.for.body: 3728 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 3729 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 3730 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 3731 // CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 3732 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 3733 // CHECK9: omp.body.continue: 3734 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 3735 // CHECK9: omp.inner.for.inc: 3736 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 3737 // CHECK9-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 3738 // CHECK9-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 3739 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] 3740 // CHECK9: omp.inner.for.end: 3741 // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 3742 // CHECK9: omp.loop.exit: 3743 // CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 3744 // CHECK9-NEXT: ret void 3745 // 3746 // 3747 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113 3748 // CHECK9-SAME: (i64 noundef [[AA:%.*]]) #[[ATTR0]] { 3749 // CHECK9-NEXT: entry: 3750 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 3751 // CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 3752 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 3753 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 3754 // CHECK9-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 3755 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 3756 // CHECK9-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 3757 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 3758 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]]) 3759 // CHECK9-NEXT: ret void 3760 // 3761 // 3762 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 3763 // CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { 3764 // CHECK9-NEXT: entry: 3765 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 3766 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 3767 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 3768 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 3769 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 3770 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 3771 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 3772 // CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 3773 // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 3774 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 3775 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 3776 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 3777 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 3778 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 3779 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 3780 // CHECK9-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 3781 // CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 3782 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 3783 // CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 3784 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 3785 // CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 3786 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 3787 // CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 3788 // CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 3789 // CHECK9: cond.true: 3790 // CHECK9-NEXT: br label [[COND_END:%.*]] 3791 // CHECK9: cond.false: 3792 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 3793 // CHECK9-NEXT: br label [[COND_END]] 3794 // CHECK9: cond.end: 3795 // CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 3796 // CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 3797 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 3798 // CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 3799 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 3800 // CHECK9: omp.inner.for.cond: 3801 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 3802 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 3803 // CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 3804 // CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 3805 // CHECK9: omp.inner.for.body: 3806 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 3807 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 3808 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 3809 // CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 3810 // CHECK9-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 2 3811 // CHECK9-NEXT: [[CONV2:%.*]] = sext i16 [[TMP8]] to i32 3812 // CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 3813 // CHECK9-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 3814 // CHECK9-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2 3815 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 3816 // CHECK9: omp.body.continue: 3817 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 3818 // CHECK9: omp.inner.for.inc: 3819 // CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 3820 // CHECK9-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP9]], 1 3821 // CHECK9-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 3822 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] 3823 // CHECK9: omp.inner.for.end: 3824 // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 3825 // CHECK9: omp.loop.exit: 3826 // CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 3827 // CHECK9-NEXT: ret void 3828 // 3829 // 3830 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120 3831 // CHECK9-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { 3832 // CHECK9-NEXT: entry: 3833 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 3834 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 3835 // CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 3836 // CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 3837 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 3838 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 3839 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 3840 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 3841 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 3842 // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* 3843 // CHECK9-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 3844 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 3845 // CHECK9-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 3846 // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 3847 // CHECK9-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 3848 // CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 3849 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) 3850 // CHECK9-NEXT: ret void 3851 // 3852 // 3853 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..2 3854 // CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { 3855 // CHECK9-NEXT: entry: 3856 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 3857 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 3858 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 3859 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 3860 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 3861 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 3862 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 3863 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 3864 // CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 3865 // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 3866 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 3867 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 3868 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 3869 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 3870 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 3871 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 3872 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 3873 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 3874 // CHECK9-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 3875 // CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 3876 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 3877 // CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 3878 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 3879 // CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 3880 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 3881 // CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 3882 // CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 3883 // CHECK9: cond.true: 3884 // CHECK9-NEXT: br label [[COND_END:%.*]] 3885 // CHECK9: cond.false: 3886 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 3887 // CHECK9-NEXT: br label [[COND_END]] 3888 // CHECK9: cond.end: 3889 // CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 3890 // CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 3891 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 3892 // CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 3893 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 3894 // CHECK9: omp.inner.for.cond: 3895 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 3896 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 3897 // CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 3898 // CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 3899 // CHECK9: omp.inner.for.body: 3900 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 3901 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 3902 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 3903 // CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 3904 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 3905 // CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1 3906 // CHECK9-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4 3907 // CHECK9-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 2 3908 // CHECK9-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32 3909 // CHECK9-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 3910 // CHECK9-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 3911 // CHECK9-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2 3912 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 3913 // CHECK9: omp.body.continue: 3914 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 3915 // CHECK9: omp.inner.for.inc: 3916 // CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 3917 // CHECK9-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1 3918 // CHECK9-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 3919 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] 3920 // CHECK9: omp.inner.for.end: 3921 // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 3922 // CHECK9: omp.loop.exit: 3923 // CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 3924 // CHECK9-NEXT: ret void 3925 // 3926 // 3927 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145 3928 // CHECK9-SAME: (i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { 3929 // CHECK9-NEXT: entry: 3930 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 3931 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 3932 // CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 3933 // CHECK9-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 3934 // CHECK9-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 3935 // CHECK9-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 3936 // CHECK9-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 3937 // CHECK9-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 3938 // CHECK9-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 3939 // CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 3940 // CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 3941 // CHECK9-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 3942 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 3943 // CHECK9-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 3944 // CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 3945 // CHECK9-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 3946 // CHECK9-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 3947 // CHECK9-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 3948 // CHECK9-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 3949 // CHECK9-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 3950 // CHECK9-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 3951 // CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 3952 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 3953 // CHECK9-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 3954 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 3955 // CHECK9-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 3956 // CHECK9-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 3957 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 3958 // CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 3959 // CHECK9-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 3960 // CHECK9-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 3961 // CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* 3962 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 3963 // CHECK9-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32* 3964 // CHECK9-NEXT: store i32 [[TMP8]], i32* [[CONV6]], align 4 3965 // CHECK9-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 3966 // CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 4 3967 // CHECK9-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* 3968 // CHECK9-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4 3969 // CHECK9-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 3970 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]]) 3971 // CHECK9-NEXT: ret void 3972 // 3973 // 3974 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..3 3975 // CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { 3976 // CHECK9-NEXT: entry: 3977 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 3978 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 3979 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 3980 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 3981 // CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 3982 // CHECK9-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 3983 // CHECK9-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 3984 // CHECK9-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 3985 // CHECK9-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 3986 // CHECK9-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 3987 // CHECK9-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 3988 // CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 3989 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 3990 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 3991 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 3992 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 3993 // CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 3994 // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 3995 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 3996 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 3997 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 3998 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 3999 // CHECK9-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 4000 // CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 4001 // CHECK9-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 4002 // CHECK9-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 4003 // CHECK9-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 4004 // CHECK9-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 4005 // CHECK9-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 4006 // CHECK9-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 4007 // CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 4008 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 4009 // CHECK9-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 4010 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 4011 // CHECK9-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 4012 // CHECK9-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 4013 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 4014 // CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 4015 // CHECK9-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 4016 // CHECK9-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 4017 // CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* 4018 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 4019 // CHECK9-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 4020 // CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 4021 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 4022 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 4 4023 // CHECK9-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 4024 // CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 4025 // CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) 4026 // CHECK9-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 4027 // CHECK9: omp.dispatch.cond: 4028 // CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4029 // CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 9 4030 // CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 4031 // CHECK9: cond.true: 4032 // CHECK9-NEXT: br label [[COND_END:%.*]] 4033 // CHECK9: cond.false: 4034 // CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4035 // CHECK9-NEXT: br label [[COND_END]] 4036 // CHECK9: cond.end: 4037 // CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] 4038 // CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 4039 // CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 4040 // CHECK9-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 4041 // CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4042 // CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4043 // CHECK9-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] 4044 // CHECK9-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 4045 // CHECK9: omp.dispatch.body: 4046 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4047 // CHECK9: omp.inner.for.cond: 4048 // CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 4049 // CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !13 4050 // CHECK9-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] 4051 // CHECK9-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 4052 // CHECK9: omp.inner.for.body: 4053 // CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 4054 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 4055 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 4056 // CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !13 4057 // CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !13 4058 // CHECK9-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP19]], 1 4059 // CHECK9-NEXT: store i32 [[ADD8]], i32* [[CONV]], align 4, !llvm.access.group !13 4060 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 4061 // CHECK9-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !13 4062 // CHECK9-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double 4063 // CHECK9-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 4064 // CHECK9-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float 4065 // CHECK9-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4, !llvm.access.group !13 4066 // CHECK9-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 4067 // CHECK9-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4, !llvm.access.group !13 4068 // CHECK9-NEXT: [[CONV13:%.*]] = fpext float [[TMP21]] to double 4069 // CHECK9-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00 4070 // CHECK9-NEXT: [[CONV15:%.*]] = fptrunc double [[ADD14]] to float 4071 // CHECK9-NEXT: store float [[CONV15]], float* [[ARRAYIDX12]], align 4, !llvm.access.group !13 4072 // CHECK9-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1 4073 // CHECK9-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i64 0, i64 2 4074 // CHECK9-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX17]], align 8, !llvm.access.group !13 4075 // CHECK9-NEXT: [[ADD18:%.*]] = fadd double [[TMP22]], 1.000000e+00 4076 // CHECK9-NEXT: store double [[ADD18]], double* [[ARRAYIDX17]], align 8, !llvm.access.group !13 4077 // CHECK9-NEXT: [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]] 4078 // CHECK9-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP23]] 4079 // CHECK9-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i64 3 4080 // CHECK9-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX20]], align 8, !llvm.access.group !13 4081 // CHECK9-NEXT: [[ADD21:%.*]] = fadd double [[TMP24]], 1.000000e+00 4082 // CHECK9-NEXT: store double [[ADD21]], double* [[ARRAYIDX20]], align 8, !llvm.access.group !13 4083 // CHECK9-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 4084 // CHECK9-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 8, !llvm.access.group !13 4085 // CHECK9-NEXT: [[ADD22:%.*]] = add nsw i64 [[TMP25]], 1 4086 // CHECK9-NEXT: store i64 [[ADD22]], i64* [[X]], align 8, !llvm.access.group !13 4087 // CHECK9-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 4088 // CHECK9-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 8, !llvm.access.group !13 4089 // CHECK9-NEXT: [[CONV23:%.*]] = sext i8 [[TMP26]] to i32 4090 // CHECK9-NEXT: [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1 4091 // CHECK9-NEXT: [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8 4092 // CHECK9-NEXT: store i8 [[CONV25]], i8* [[Y]], align 8, !llvm.access.group !13 4093 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 4094 // CHECK9: omp.body.continue: 4095 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4096 // CHECK9: omp.inner.for.inc: 4097 // CHECK9-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 4098 // CHECK9-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP27]], 1 4099 // CHECK9-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 4100 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]] 4101 // CHECK9: omp.inner.for.end: 4102 // CHECK9-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 4103 // CHECK9: omp.dispatch.inc: 4104 // CHECK9-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 4105 // CHECK9-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 4106 // CHECK9-NEXT: [[ADD27:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] 4107 // CHECK9-NEXT: store i32 [[ADD27]], i32* [[DOTOMP_LB]], align 4 4108 // CHECK9-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4109 // CHECK9-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 4110 // CHECK9-NEXT: [[ADD28:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] 4111 // CHECK9-NEXT: store i32 [[ADD28]], i32* [[DOTOMP_UB]], align 4 4112 // CHECK9-NEXT: br label [[OMP_DISPATCH_COND]] 4113 // CHECK9: omp.dispatch.end: 4114 // CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]]) 4115 // CHECK9-NEXT: ret void 4116 // 4117 // 4118 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200 4119 // CHECK9-SAME: (i64 noundef [[N:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 4120 // CHECK9-NEXT: entry: 4121 // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 4122 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 4123 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 4124 // CHECK9-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 4125 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 4126 // CHECK9-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 4127 // CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 4128 // CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 4129 // CHECK9-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 4130 // CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 4131 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 4132 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 4133 // CHECK9-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 4134 // CHECK9-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 4135 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* 4136 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_ADDR]] to i32* 4137 // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 4138 // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 4139 // CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 4140 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 4141 // CHECK9-NEXT: [[CONV4:%.*]] = bitcast i64* [[N_CASTED]] to i32* 4142 // CHECK9-NEXT: store i32 [[TMP1]], i32* [[CONV4]], align 4 4143 // CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[N_CASTED]], align 8 4144 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 4 4145 // CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* 4146 // CHECK9-NEXT: store i32 [[TMP3]], i32* [[CONV5]], align 4 4147 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8 4148 // CHECK9-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV2]], align 2 4149 // CHECK9-NEXT: [[CONV6:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 4150 // CHECK9-NEXT: store i16 [[TMP5]], i16* [[CONV6]], align 2 4151 // CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[AA_CASTED]], align 8 4152 // CHECK9-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV3]], align 1 4153 // CHECK9-NEXT: [[CONV7:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* 4154 // CHECK9-NEXT: store i8 [[TMP7]], i8* [[CONV7]], align 1 4155 // CHECK9-NEXT: [[TMP8:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 4156 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]], [10 x i32]* [[TMP0]]) 4157 // CHECK9-NEXT: ret void 4158 // 4159 // 4160 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..4 4161 // CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 4162 // CHECK9-NEXT: entry: 4163 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 4164 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 4165 // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 4166 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 4167 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 4168 // CHECK9-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 4169 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 4170 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 4171 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 4172 // CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 4173 // CHECK9-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4 4174 // CHECK9-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i32, align 4 4175 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 4176 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 4177 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 4178 // CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 4179 // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 4180 // CHECK9-NEXT: [[I8:%.*]] = alloca i32, align 4 4181 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 4182 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 4183 // CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 4184 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 4185 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 4186 // CHECK9-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 4187 // CHECK9-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 4188 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* 4189 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_ADDR]] to i32* 4190 // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 4191 // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 4192 // CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 4193 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV1]], align 4 4194 // CHECK9-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 4195 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4 4196 // CHECK9-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_4]], align 4 4197 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 4198 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 4199 // CHECK9-NEXT: [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]] 4200 // CHECK9-NEXT: [[SUB6:%.*]] = sub i32 [[SUB]], 1 4201 // CHECK9-NEXT: [[ADD:%.*]] = add i32 [[SUB6]], 1 4202 // CHECK9-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 4203 // CHECK9-NEXT: [[SUB7:%.*]] = sub i32 [[DIV]], 1 4204 // CHECK9-NEXT: store i32 [[SUB7]], i32* [[DOTCAPTURE_EXPR_5]], align 4 4205 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 4206 // CHECK9-NEXT: store i32 [[TMP5]], i32* [[I]], align 4 4207 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 4208 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 4209 // CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]] 4210 // CHECK9-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] 4211 // CHECK9: omp.precond.then: 4212 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 4213 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 4214 // CHECK9-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_UB]], align 4 4215 // CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 4216 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 4217 // CHECK9-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 4218 // CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 4219 // CHECK9-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 4220 // CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4221 // CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 4222 // CHECK9-NEXT: [[CMP9:%.*]] = icmp ugt i32 [[TMP11]], [[TMP12]] 4223 // CHECK9-NEXT: br i1 [[CMP9]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 4224 // CHECK9: cond.true: 4225 // CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 4226 // CHECK9-NEXT: br label [[COND_END:%.*]] 4227 // CHECK9: cond.false: 4228 // CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4229 // CHECK9-NEXT: br label [[COND_END]] 4230 // CHECK9: cond.end: 4231 // CHECK9-NEXT: [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ] 4232 // CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 4233 // CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 4234 // CHECK9-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4 4235 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4236 // CHECK9: omp.inner.for.cond: 4237 // CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4238 // CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4239 // CHECK9-NEXT: [[ADD10:%.*]] = add i32 [[TMP17]], 1 4240 // CHECK9-NEXT: [[CMP11:%.*]] = icmp ult i32 [[TMP16]], [[ADD10]] 4241 // CHECK9-NEXT: br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 4242 // CHECK9: omp.inner.for.body: 4243 // CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 4244 // CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4245 // CHECK9-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 1 4246 // CHECK9-NEXT: [[ADD12:%.*]] = add i32 [[TMP18]], [[MUL]] 4247 // CHECK9-NEXT: store i32 [[ADD12]], i32* [[I8]], align 4 4248 // CHECK9-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 4 4249 // CHECK9-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP20]], 1 4250 // CHECK9-NEXT: store i32 [[ADD13]], i32* [[CONV1]], align 4 4251 // CHECK9-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV2]], align 2 4252 // CHECK9-NEXT: [[CONV14:%.*]] = sext i16 [[TMP21]] to i32 4253 // CHECK9-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1 4254 // CHECK9-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16 4255 // CHECK9-NEXT: store i16 [[CONV16]], i16* [[CONV2]], align 2 4256 // CHECK9-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV3]], align 1 4257 // CHECK9-NEXT: [[CONV17:%.*]] = sext i8 [[TMP22]] to i32 4258 // CHECK9-NEXT: [[ADD18:%.*]] = add nsw i32 [[CONV17]], 1 4259 // CHECK9-NEXT: [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8 4260 // CHECK9-NEXT: store i8 [[CONV19]], i8* [[CONV3]], align 1 4261 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 4262 // CHECK9-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 4263 // CHECK9-NEXT: [[ADD20:%.*]] = add nsw i32 [[TMP23]], 1 4264 // CHECK9-NEXT: store i32 [[ADD20]], i32* [[ARRAYIDX]], align 4 4265 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 4266 // CHECK9: omp.body.continue: 4267 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4268 // CHECK9: omp.inner.for.inc: 4269 // CHECK9-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4270 // CHECK9-NEXT: [[ADD21:%.*]] = add i32 [[TMP24]], 1 4271 // CHECK9-NEXT: store i32 [[ADD21]], i32* [[DOTOMP_IV]], align 4 4272 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] 4273 // CHECK9: omp.inner.for.end: 4274 // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 4275 // CHECK9: omp.loop.exit: 4276 // CHECK9-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 4277 // CHECK9-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 4278 // CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) 4279 // CHECK9-NEXT: br label [[OMP_PRECOND_END]] 4280 // CHECK9: omp.precond.end: 4281 // CHECK9-NEXT: ret void 4282 // 4283 // 4284 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218 4285 // CHECK9-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { 4286 // CHECK9-NEXT: entry: 4287 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 4288 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 4289 // CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 4290 // CHECK9-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 4291 // CHECK9-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 4292 // CHECK9-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 4293 // CHECK9-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 4294 // CHECK9-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 4295 // CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 4296 // CHECK9-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 4297 // CHECK9-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 4298 // CHECK9-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 4299 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 4300 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 4301 // CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 4302 // CHECK9-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 4303 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4 4304 // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* 4305 // CHECK9-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 4306 // CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 4307 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) 4308 // CHECK9-NEXT: ret void 4309 // 4310 // 4311 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..5 4312 // CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { 4313 // CHECK9-NEXT: entry: 4314 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 4315 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 4316 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 4317 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 4318 // CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 4319 // CHECK9-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 4320 // CHECK9-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 4321 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 4322 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 4323 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 4324 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 4325 // CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 4326 // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 4327 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 4328 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 4329 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 4330 // CHECK9-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 4331 // CHECK9-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 4332 // CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 4333 // CHECK9-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 4334 // CHECK9-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 4335 // CHECK9-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 4336 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 4337 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 4338 // CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 4339 // CHECK9-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 4340 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 4341 // CHECK9-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 4342 // CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 4343 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 4344 // CHECK9-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 4345 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 4346 // CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 4347 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4348 // CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 9 4349 // CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 4350 // CHECK9: cond.true: 4351 // CHECK9-NEXT: br label [[COND_END:%.*]] 4352 // CHECK9: cond.false: 4353 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4354 // CHECK9-NEXT: br label [[COND_END]] 4355 // CHECK9: cond.end: 4356 // CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 4357 // CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 4358 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 4359 // CHECK9-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 4360 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4361 // CHECK9: omp.inner.for.cond: 4362 // CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4363 // CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4364 // CHECK9-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 4365 // CHECK9-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 4366 // CHECK9: omp.inner.for.body: 4367 // CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4368 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 4369 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 4370 // CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 4371 // CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4 4372 // CHECK9-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double 4373 // CHECK9-NEXT: [[ADD5:%.*]] = fadd double [[CONV4]], 1.500000e+00 4374 // CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 4375 // CHECK9-NEXT: store double [[ADD5]], double* [[A]], align 8 4376 // CHECK9-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 4377 // CHECK9-NEXT: [[TMP13:%.*]] = load double, double* [[A6]], align 8 4378 // CHECK9-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 4379 // CHECK9-NEXT: store double [[INC]], double* [[A6]], align 8 4380 // CHECK9-NEXT: [[CONV7:%.*]] = fptosi double [[INC]] to i16 4381 // CHECK9-NEXT: [[TMP14:%.*]] = mul nsw i64 1, [[TMP2]] 4382 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP14]] 4383 // CHECK9-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 4384 // CHECK9-NEXT: store i16 [[CONV7]], i16* [[ARRAYIDX8]], align 2 4385 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 4386 // CHECK9: omp.body.continue: 4387 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4388 // CHECK9: omp.inner.for.inc: 4389 // CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4390 // CHECK9-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP15]], 1 4391 // CHECK9-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 4392 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] 4393 // CHECK9: omp.inner.for.end: 4394 // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 4395 // CHECK9: omp.loop.exit: 4396 // CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 4397 // CHECK9-NEXT: ret void 4398 // 4399 // 4400 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183 4401 // CHECK9-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 4402 // CHECK9-NEXT: entry: 4403 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 4404 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 4405 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 4406 // CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 4407 // CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 4408 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 4409 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 4410 // CHECK9-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 4411 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 4412 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 4413 // CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 4414 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 4415 // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* 4416 // CHECK9-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 4417 // CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 4418 // CHECK9-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 4419 // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 4420 // CHECK9-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 4421 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 4422 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) 4423 // CHECK9-NEXT: ret void 4424 // 4425 // 4426 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..6 4427 // CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 4428 // CHECK9-NEXT: entry: 4429 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 4430 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 4431 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 4432 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 4433 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 4434 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 4435 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 4436 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 4437 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 4438 // CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 4439 // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 4440 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 4441 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 4442 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 4443 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 4444 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 4445 // CHECK9-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 4446 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 4447 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 4448 // CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 4449 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 4450 // CHECK9-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 4451 // CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 4452 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 4453 // CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 4454 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 4455 // CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 4456 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4457 // CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 4458 // CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 4459 // CHECK9: cond.true: 4460 // CHECK9-NEXT: br label [[COND_END:%.*]] 4461 // CHECK9: cond.false: 4462 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4463 // CHECK9-NEXT: br label [[COND_END]] 4464 // CHECK9: cond.end: 4465 // CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 4466 // CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 4467 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 4468 // CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 4469 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4470 // CHECK9: omp.inner.for.cond: 4471 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4472 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4473 // CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] 4474 // CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 4475 // CHECK9: omp.inner.for.body: 4476 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4477 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 4478 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 4479 // CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 4480 // CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4 4481 // CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1 4482 // CHECK9-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4 4483 // CHECK9-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 2 4484 // CHECK9-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32 4485 // CHECK9-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 4486 // CHECK9-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 4487 // CHECK9-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2 4488 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 4489 // CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 4490 // CHECK9-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1 4491 // CHECK9-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4 4492 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 4493 // CHECK9: omp.body.continue: 4494 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4495 // CHECK9: omp.inner.for.inc: 4496 // CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4497 // CHECK9-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP12]], 1 4498 // CHECK9-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 4499 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] 4500 // CHECK9: omp.inner.for.end: 4501 // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 4502 // CHECK9: omp.loop.exit: 4503 // CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) 4504 // CHECK9-NEXT: ret void 4505 // 4506 // 4507 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103 4508 // CHECK11-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]], i32 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { 4509 // CHECK11-NEXT: entry: 4510 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 4511 // CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 4512 // CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4 4513 // CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 4514 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) 4515 // CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 4516 // CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 4517 // CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 4518 // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 4519 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 4520 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 4521 // CHECK11-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) 4522 // CHECK11-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 4523 // CHECK11-NEXT: [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 4524 // CHECK11-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 4525 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 4526 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]]) 4527 // CHECK11-NEXT: ret void 4528 // 4529 // 4530 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. 4531 // CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { 4532 // CHECK11-NEXT: entry: 4533 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 4534 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 4535 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 4536 // CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 4537 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 4538 // CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 4539 // CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 4540 // CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 4541 // CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 4542 // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 4543 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 4544 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 4545 // CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 4546 // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 4547 // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 4548 // CHECK11-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 4549 // CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 4550 // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 4551 // CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 4552 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 4553 // CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 4554 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4555 // CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 4556 // CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 4557 // CHECK11: cond.true: 4558 // CHECK11-NEXT: br label [[COND_END:%.*]] 4559 // CHECK11: cond.false: 4560 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4561 // CHECK11-NEXT: br label [[COND_END]] 4562 // CHECK11: cond.end: 4563 // CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 4564 // CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 4565 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 4566 // CHECK11-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 4567 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4568 // CHECK11: omp.inner.for.cond: 4569 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4570 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4571 // CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 4572 // CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 4573 // CHECK11: omp.inner.for.body: 4574 // CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4575 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 4576 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 4577 // CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4 4578 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 4579 // CHECK11: omp.body.continue: 4580 // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4581 // CHECK11: omp.inner.for.inc: 4582 // CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4583 // CHECK11-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 4584 // CHECK11-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 4585 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] 4586 // CHECK11: omp.inner.for.end: 4587 // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 4588 // CHECK11: omp.loop.exit: 4589 // CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 4590 // CHECK11-NEXT: ret void 4591 // 4592 // 4593 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113 4594 // CHECK11-SAME: (i32 noundef [[AA:%.*]]) #[[ATTR0]] { 4595 // CHECK11-NEXT: entry: 4596 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 4597 // CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 4598 // CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 4599 // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 4600 // CHECK11-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 4601 // CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 4602 // CHECK11-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 4603 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 4604 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]]) 4605 // CHECK11-NEXT: ret void 4606 // 4607 // 4608 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 4609 // CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { 4610 // CHECK11-NEXT: entry: 4611 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 4612 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 4613 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 4614 // CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 4615 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 4616 // CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 4617 // CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 4618 // CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 4619 // CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 4620 // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 4621 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 4622 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 4623 // CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 4624 // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 4625 // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 4626 // CHECK11-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 4627 // CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 4628 // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 4629 // CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 4630 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 4631 // CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 4632 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4633 // CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 4634 // CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 4635 // CHECK11: cond.true: 4636 // CHECK11-NEXT: br label [[COND_END:%.*]] 4637 // CHECK11: cond.false: 4638 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4639 // CHECK11-NEXT: br label [[COND_END]] 4640 // CHECK11: cond.end: 4641 // CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 4642 // CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 4643 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 4644 // CHECK11-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 4645 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4646 // CHECK11: omp.inner.for.cond: 4647 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4648 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4649 // CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 4650 // CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 4651 // CHECK11: omp.inner.for.body: 4652 // CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4653 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 4654 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 4655 // CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4 4656 // CHECK11-NEXT: [[TMP8:%.*]] = load i16, i16* [[CONV]], align 2 4657 // CHECK11-NEXT: [[CONV2:%.*]] = sext i16 [[TMP8]] to i32 4658 // CHECK11-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 4659 // CHECK11-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 4660 // CHECK11-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2 4661 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 4662 // CHECK11: omp.body.continue: 4663 // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4664 // CHECK11: omp.inner.for.inc: 4665 // CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4666 // CHECK11-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP9]], 1 4667 // CHECK11-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 4668 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] 4669 // CHECK11: omp.inner.for.end: 4670 // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 4671 // CHECK11: omp.loop.exit: 4672 // CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 4673 // CHECK11-NEXT: ret void 4674 // 4675 // 4676 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120 4677 // CHECK11-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { 4678 // CHECK11-NEXT: entry: 4679 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 4680 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 4681 // CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 4682 // CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 4683 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 4684 // CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 4685 // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 4686 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 4687 // CHECK11-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 4688 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 4689 // CHECK11-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 4690 // CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 4691 // CHECK11-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 4692 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 4693 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) 4694 // CHECK11-NEXT: ret void 4695 // 4696 // 4697 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..2 4698 // CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { 4699 // CHECK11-NEXT: entry: 4700 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 4701 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 4702 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 4703 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 4704 // CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 4705 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 4706 // CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 4707 // CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 4708 // CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 4709 // CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 4710 // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 4711 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 4712 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 4713 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 4714 // CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 4715 // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 4716 // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 4717 // CHECK11-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 4718 // CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 4719 // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 4720 // CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 4721 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 4722 // CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 4723 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4724 // CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 4725 // CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 4726 // CHECK11: cond.true: 4727 // CHECK11-NEXT: br label [[COND_END:%.*]] 4728 // CHECK11: cond.false: 4729 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4730 // CHECK11-NEXT: br label [[COND_END]] 4731 // CHECK11: cond.end: 4732 // CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 4733 // CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 4734 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 4735 // CHECK11-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 4736 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4737 // CHECK11: omp.inner.for.cond: 4738 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4739 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4740 // CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 4741 // CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 4742 // CHECK11: omp.inner.for.body: 4743 // CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4744 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 4745 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 4746 // CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4 4747 // CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 4748 // CHECK11-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 4749 // CHECK11-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4 4750 // CHECK11-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 2 4751 // CHECK11-NEXT: [[CONV3:%.*]] = sext i16 [[TMP9]] to i32 4752 // CHECK11-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 4753 // CHECK11-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 4754 // CHECK11-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2 4755 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 4756 // CHECK11: omp.body.continue: 4757 // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4758 // CHECK11: omp.inner.for.inc: 4759 // CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4760 // CHECK11-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP10]], 1 4761 // CHECK11-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 4762 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] 4763 // CHECK11: omp.inner.for.end: 4764 // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 4765 // CHECK11: omp.loop.exit: 4766 // CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 4767 // CHECK11-NEXT: ret void 4768 // 4769 // 4770 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145 4771 // CHECK11-SAME: (i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { 4772 // CHECK11-NEXT: entry: 4773 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 4774 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 4775 // CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 4776 // CHECK11-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 4777 // CHECK11-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 4778 // CHECK11-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 4779 // CHECK11-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 4780 // CHECK11-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 4781 // CHECK11-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 4782 // CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 4783 // CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 4784 // CHECK11-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 4785 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 4786 // CHECK11-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 4787 // CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 4788 // CHECK11-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 4789 // CHECK11-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 4790 // CHECK11-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 4791 // CHECK11-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 4792 // CHECK11-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 4793 // CHECK11-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 4794 // CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 4795 // CHECK11-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 4796 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 4797 // CHECK11-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 4798 // CHECK11-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 4799 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 4800 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 4801 // CHECK11-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 4802 // CHECK11-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 4803 // CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 4804 // CHECK11-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4 4805 // CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4 4806 // CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 4807 // CHECK11-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 4808 // CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 4809 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i32 [[TMP11]]) 4810 // CHECK11-NEXT: ret void 4811 // 4812 // 4813 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..3 4814 // CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { 4815 // CHECK11-NEXT: entry: 4816 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 4817 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 4818 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 4819 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 4820 // CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 4821 // CHECK11-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 4822 // CHECK11-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 4823 // CHECK11-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 4824 // CHECK11-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 4825 // CHECK11-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 4826 // CHECK11-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 4827 // CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 4828 // CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 4829 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 4830 // CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 4831 // CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 4832 // CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 4833 // CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 4834 // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 4835 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 4836 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 4837 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 4838 // CHECK11-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 4839 // CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 4840 // CHECK11-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 4841 // CHECK11-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 4842 // CHECK11-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 4843 // CHECK11-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 4844 // CHECK11-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 4845 // CHECK11-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 4846 // CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 4847 // CHECK11-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 4848 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 4849 // CHECK11-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 4850 // CHECK11-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 4851 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 4852 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 4853 // CHECK11-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 4854 // CHECK11-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 4855 // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 4856 // CHECK11-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 4857 // CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 4858 // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 4859 // CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 4860 // CHECK11-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 4861 // CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 4862 // CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) 4863 // CHECK11-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 4864 // CHECK11: omp.dispatch.cond: 4865 // CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4866 // CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 9 4867 // CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 4868 // CHECK11: cond.true: 4869 // CHECK11-NEXT: br label [[COND_END:%.*]] 4870 // CHECK11: cond.false: 4871 // CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4872 // CHECK11-NEXT: br label [[COND_END]] 4873 // CHECK11: cond.end: 4874 // CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] 4875 // CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 4876 // CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 4877 // CHECK11-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 4878 // CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4879 // CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4880 // CHECK11-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] 4881 // CHECK11-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 4882 // CHECK11: omp.dispatch.body: 4883 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4884 // CHECK11: omp.inner.for.cond: 4885 // CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 4886 // CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !14 4887 // CHECK11-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] 4888 // CHECK11-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 4889 // CHECK11: omp.inner.for.body: 4890 // CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 4891 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 4892 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 4893 // CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !14 4894 // CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !14 4895 // CHECK11-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP19]], 1 4896 // CHECK11-NEXT: store i32 [[ADD7]], i32* [[A_ADDR]], align 4, !llvm.access.group !14 4897 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2 4898 // CHECK11-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !14 4899 // CHECK11-NEXT: [[CONV:%.*]] = fpext float [[TMP20]] to double 4900 // CHECK11-NEXT: [[ADD8:%.*]] = fadd double [[CONV]], 1.000000e+00 4901 // CHECK11-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float 4902 // CHECK11-NEXT: store float [[CONV9]], float* [[ARRAYIDX]], align 4, !llvm.access.group !14 4903 // CHECK11-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3 4904 // CHECK11-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX10]], align 4, !llvm.access.group !14 4905 // CHECK11-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double 4906 // CHECK11-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00 4907 // CHECK11-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float 4908 // CHECK11-NEXT: store float [[CONV13]], float* [[ARRAYIDX10]], align 4, !llvm.access.group !14 4909 // CHECK11-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1 4910 // CHECK11-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX14]], i32 0, i32 2 4911 // CHECK11-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX15]], align 8, !llvm.access.group !14 4912 // CHECK11-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00 4913 // CHECK11-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8, !llvm.access.group !14 4914 // CHECK11-NEXT: [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]] 4915 // CHECK11-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP23]] 4916 // CHECK11-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX17]], i32 3 4917 // CHECK11-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX18]], align 8, !llvm.access.group !14 4918 // CHECK11-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00 4919 // CHECK11-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8, !llvm.access.group !14 4920 // CHECK11-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 4921 // CHECK11-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 4, !llvm.access.group !14 4922 // CHECK11-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1 4923 // CHECK11-NEXT: store i64 [[ADD20]], i64* [[X]], align 4, !llvm.access.group !14 4924 // CHECK11-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 4925 // CHECK11-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 4, !llvm.access.group !14 4926 // CHECK11-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i32 4927 // CHECK11-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1 4928 // CHECK11-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8 4929 // CHECK11-NEXT: store i8 [[CONV23]], i8* [[Y]], align 4, !llvm.access.group !14 4930 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 4931 // CHECK11: omp.body.continue: 4932 // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4933 // CHECK11: omp.inner.for.inc: 4934 // CHECK11-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 4935 // CHECK11-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1 4936 // CHECK11-NEXT: store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 4937 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]] 4938 // CHECK11: omp.inner.for.end: 4939 // CHECK11-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 4940 // CHECK11: omp.dispatch.inc: 4941 // CHECK11-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 4942 // CHECK11-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 4943 // CHECK11-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] 4944 // CHECK11-NEXT: store i32 [[ADD25]], i32* [[DOTOMP_LB]], align 4 4945 // CHECK11-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4946 // CHECK11-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 4947 // CHECK11-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] 4948 // CHECK11-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_UB]], align 4 4949 // CHECK11-NEXT: br label [[OMP_DISPATCH_COND]] 4950 // CHECK11: omp.dispatch.end: 4951 // CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]]) 4952 // CHECK11-NEXT: ret void 4953 // 4954 // 4955 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200 4956 // CHECK11-SAME: (i32 noundef [[N:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 4957 // CHECK11-NEXT: entry: 4958 // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 4959 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 4960 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 4961 // CHECK11-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 4962 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 4963 // CHECK11-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 4964 // CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 4965 // CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 4966 // CHECK11-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 4967 // CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 4968 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 4969 // CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 4970 // CHECK11-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 4971 // CHECK11-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 4972 // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 4973 // CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 4974 // CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 4975 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 4976 // CHECK11-NEXT: store i32 [[TMP1]], i32* [[N_CASTED]], align 4 4977 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_CASTED]], align 4 4978 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4 4979 // CHECK11-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4 4980 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4 4981 // CHECK11-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 2 4982 // CHECK11-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 4983 // CHECK11-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2 4984 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[AA_CASTED]], align 4 4985 // CHECK11-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV1]], align 1 4986 // CHECK11-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* 4987 // CHECK11-NEXT: store i8 [[TMP7]], i8* [[CONV3]], align 1 4988 // CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 4989 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP8]], [10 x i32]* [[TMP0]]) 4990 // CHECK11-NEXT: ret void 4991 // 4992 // 4993 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..4 4994 // CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 4995 // CHECK11-NEXT: entry: 4996 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 4997 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 4998 // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 4999 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 5000 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 5001 // CHECK11-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 5002 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 5003 // CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 5004 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 5005 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 5006 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 5007 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4 5008 // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 5009 // CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 5010 // CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 5011 // CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 5012 // CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 5013 // CHECK11-NEXT: [[I6:%.*]] = alloca i32, align 4 5014 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 5015 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 5016 // CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 5017 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 5018 // CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 5019 // CHECK11-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 5020 // CHECK11-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 5021 // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 5022 // CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 5023 // CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 5024 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 5025 // CHECK11-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 5026 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 5027 // CHECK11-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4 5028 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 5029 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 5030 // CHECK11-NEXT: [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]] 5031 // CHECK11-NEXT: [[SUB4:%.*]] = sub i32 [[SUB]], 1 5032 // CHECK11-NEXT: [[ADD:%.*]] = add i32 [[SUB4]], 1 5033 // CHECK11-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 5034 // CHECK11-NEXT: [[SUB5:%.*]] = sub i32 [[DIV]], 1 5035 // CHECK11-NEXT: store i32 [[SUB5]], i32* [[DOTCAPTURE_EXPR_3]], align 4 5036 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 5037 // CHECK11-NEXT: store i32 [[TMP5]], i32* [[I]], align 4 5038 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 5039 // CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 5040 // CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]] 5041 // CHECK11-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] 5042 // CHECK11: omp.precond.then: 5043 // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 5044 // CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 5045 // CHECK11-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_UB]], align 4 5046 // CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 5047 // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 5048 // CHECK11-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 5049 // CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 5050 // CHECK11-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 5051 // CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 5052 // CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 5053 // CHECK11-NEXT: [[CMP7:%.*]] = icmp ugt i32 [[TMP11]], [[TMP12]] 5054 // CHECK11-NEXT: br i1 [[CMP7]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 5055 // CHECK11: cond.true: 5056 // CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 5057 // CHECK11-NEXT: br label [[COND_END:%.*]] 5058 // CHECK11: cond.false: 5059 // CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 5060 // CHECK11-NEXT: br label [[COND_END]] 5061 // CHECK11: cond.end: 5062 // CHECK11-NEXT: [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ] 5063 // CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 5064 // CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 5065 // CHECK11-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4 5066 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 5067 // CHECK11: omp.inner.for.cond: 5068 // CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 5069 // CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 5070 // CHECK11-NEXT: [[ADD8:%.*]] = add i32 [[TMP17]], 1 5071 // CHECK11-NEXT: [[CMP9:%.*]] = icmp ult i32 [[TMP16]], [[ADD8]] 5072 // CHECK11-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 5073 // CHECK11: omp.inner.for.body: 5074 // CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 5075 // CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 5076 // CHECK11-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 1 5077 // CHECK11-NEXT: [[ADD10:%.*]] = add i32 [[TMP18]], [[MUL]] 5078 // CHECK11-NEXT: store i32 [[ADD10]], i32* [[I6]], align 4 5079 // CHECK11-NEXT: [[TMP20:%.*]] = load i32, i32* [[A_ADDR]], align 4 5080 // CHECK11-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP20]], 1 5081 // CHECK11-NEXT: store i32 [[ADD11]], i32* [[A_ADDR]], align 4 5082 // CHECK11-NEXT: [[TMP21:%.*]] = load i16, i16* [[CONV]], align 2 5083 // CHECK11-NEXT: [[CONV12:%.*]] = sext i16 [[TMP21]] to i32 5084 // CHECK11-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1 5085 // CHECK11-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16 5086 // CHECK11-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 2 5087 // CHECK11-NEXT: [[TMP22:%.*]] = load i8, i8* [[CONV1]], align 1 5088 // CHECK11-NEXT: [[CONV15:%.*]] = sext i8 [[TMP22]] to i32 5089 // CHECK11-NEXT: [[ADD16:%.*]] = add nsw i32 [[CONV15]], 1 5090 // CHECK11-NEXT: [[CONV17:%.*]] = trunc i32 [[ADD16]] to i8 5091 // CHECK11-NEXT: store i8 [[CONV17]], i8* [[CONV1]], align 1 5092 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 5093 // CHECK11-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 5094 // CHECK11-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP23]], 1 5095 // CHECK11-NEXT: store i32 [[ADD18]], i32* [[ARRAYIDX]], align 4 5096 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 5097 // CHECK11: omp.body.continue: 5098 // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 5099 // CHECK11: omp.inner.for.inc: 5100 // CHECK11-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 5101 // CHECK11-NEXT: [[ADD19:%.*]] = add i32 [[TMP24]], 1 5102 // CHECK11-NEXT: store i32 [[ADD19]], i32* [[DOTOMP_IV]], align 4 5103 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] 5104 // CHECK11: omp.inner.for.end: 5105 // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 5106 // CHECK11: omp.loop.exit: 5107 // CHECK11-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 5108 // CHECK11-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 5109 // CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) 5110 // CHECK11-NEXT: br label [[OMP_PRECOND_END]] 5111 // CHECK11: omp.precond.end: 5112 // CHECK11-NEXT: ret void 5113 // 5114 // 5115 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218 5116 // CHECK11-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { 5117 // CHECK11-NEXT: entry: 5118 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 5119 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 5120 // CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 5121 // CHECK11-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 5122 // CHECK11-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 5123 // CHECK11-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 5124 // CHECK11-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 5125 // CHECK11-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 5126 // CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 5127 // CHECK11-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 5128 // CHECK11-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 5129 // CHECK11-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 5130 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 5131 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 5132 // CHECK11-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 5133 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 5134 // CHECK11-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 5135 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 5136 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]]) 5137 // CHECK11-NEXT: ret void 5138 // 5139 // 5140 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..5 5141 // CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { 5142 // CHECK11-NEXT: entry: 5143 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 5144 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 5145 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 5146 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 5147 // CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 5148 // CHECK11-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 5149 // CHECK11-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 5150 // CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 5151 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 5152 // CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 5153 // CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 5154 // CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 5155 // CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 5156 // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 5157 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 5158 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 5159 // CHECK11-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 5160 // CHECK11-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 5161 // CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 5162 // CHECK11-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 5163 // CHECK11-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 5164 // CHECK11-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 5165 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 5166 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 5167 // CHECK11-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 5168 // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 5169 // CHECK11-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 5170 // CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 5171 // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 5172 // CHECK11-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 5173 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 5174 // CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 5175 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 5176 // CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 9 5177 // CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 5178 // CHECK11: cond.true: 5179 // CHECK11-NEXT: br label [[COND_END:%.*]] 5180 // CHECK11: cond.false: 5181 // CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 5182 // CHECK11-NEXT: br label [[COND_END]] 5183 // CHECK11: cond.end: 5184 // CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 5185 // CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 5186 // CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 5187 // CHECK11-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 5188 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 5189 // CHECK11: omp.inner.for.cond: 5190 // CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 5191 // CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 5192 // CHECK11-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 5193 // CHECK11-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 5194 // CHECK11: omp.inner.for.body: 5195 // CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 5196 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 5197 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 5198 // CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4 5199 // CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[B_ADDR]], align 4 5200 // CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP12]] to double 5201 // CHECK11-NEXT: [[ADD4:%.*]] = fadd double [[CONV]], 1.500000e+00 5202 // CHECK11-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 5203 // CHECK11-NEXT: store double [[ADD4]], double* [[A]], align 4 5204 // CHECK11-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 5205 // CHECK11-NEXT: [[TMP13:%.*]] = load double, double* [[A5]], align 4 5206 // CHECK11-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 5207 // CHECK11-NEXT: store double [[INC]], double* [[A5]], align 4 5208 // CHECK11-NEXT: [[CONV6:%.*]] = fptosi double [[INC]] to i16 5209 // CHECK11-NEXT: [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]] 5210 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP14]] 5211 // CHECK11-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 5212 // CHECK11-NEXT: store i16 [[CONV6]], i16* [[ARRAYIDX7]], align 2 5213 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 5214 // CHECK11: omp.body.continue: 5215 // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 5216 // CHECK11: omp.inner.for.inc: 5217 // CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 5218 // CHECK11-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP15]], 1 5219 // CHECK11-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 5220 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] 5221 // CHECK11: omp.inner.for.end: 5222 // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 5223 // CHECK11: omp.loop.exit: 5224 // CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 5225 // CHECK11-NEXT: ret void 5226 // 5227 // 5228 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183 5229 // CHECK11-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 5230 // CHECK11-NEXT: entry: 5231 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 5232 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 5233 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 5234 // CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 5235 // CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 5236 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 5237 // CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 5238 // CHECK11-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 5239 // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 5240 // CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 5241 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 5242 // CHECK11-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 5243 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 5244 // CHECK11-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 5245 // CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 5246 // CHECK11-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 5247 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 5248 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) 5249 // CHECK11-NEXT: ret void 5250 // 5251 // 5252 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..6 5253 // CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 5254 // CHECK11-NEXT: entry: 5255 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 5256 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 5257 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 5258 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 5259 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 5260 // CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 5261 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 5262 // CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 5263 // CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 5264 // CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 5265 // CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 5266 // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 5267 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 5268 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 5269 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 5270 // CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 5271 // CHECK11-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 5272 // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 5273 // CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 5274 // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 5275 // CHECK11-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4 5276 // CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 5277 // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 5278 // CHECK11-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 5279 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 5280 // CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 5281 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 5282 // CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 5283 // CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 5284 // CHECK11: cond.true: 5285 // CHECK11-NEXT: br label [[COND_END:%.*]] 5286 // CHECK11: cond.false: 5287 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 5288 // CHECK11-NEXT: br label [[COND_END]] 5289 // CHECK11: cond.end: 5290 // CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 5291 // CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 5292 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 5293 // CHECK11-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 5294 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 5295 // CHECK11: omp.inner.for.cond: 5296 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 5297 // CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 5298 // CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] 5299 // CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 5300 // CHECK11: omp.inner.for.body: 5301 // CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 5302 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 5303 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 5304 // CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4 5305 // CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4 5306 // CHECK11-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 5307 // CHECK11-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4 5308 // CHECK11-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 2 5309 // CHECK11-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32 5310 // CHECK11-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 5311 // CHECK11-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 5312 // CHECK11-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2 5313 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 5314 // CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 5315 // CHECK11-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1 5316 // CHECK11-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 5317 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 5318 // CHECK11: omp.body.continue: 5319 // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 5320 // CHECK11: omp.inner.for.inc: 5321 // CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 5322 // CHECK11-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP12]], 1 5323 // CHECK11-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 5324 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] 5325 // CHECK11: omp.inner.for.end: 5326 // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 5327 // CHECK11: omp.loop.exit: 5328 // CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) 5329 // CHECK11-NEXT: ret void 5330 // 5331