1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _
2 // Test host codegen.
3 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK1
4 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
5 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK2
6 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK3
7 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
8 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK4
9 
10 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK5
11 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
12 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK6
13 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK7
14 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
15 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK8
16 
17 // Test target codegen - host bc file has to be created first.
18 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc
19 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK9
20 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s
21 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK10
22 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc
23 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK11
24 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s
25 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK12
26 
27 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc
28 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK13
29 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s
30 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK14
31 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc
32 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK15
33 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s
34 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK16
35 
36 // Test host codegen.
37 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK17
38 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
39 // RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK18
40 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK19
41 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
42 // RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK20
43 
44 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK21
45 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
46 // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK22
47 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK23
48 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
49 // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK24
50 
51 // Test target codegen - host bc file has to be created first.
52 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc
53 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK25
54 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s
55 // RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK26
56 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc
57 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK27
58 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s
59 // RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK28
60 
61 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc
62 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK29
63 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s
64 // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK30
65 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc
66 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK31
67 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s
68 // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK32
69 
70 // expected-no-diagnostics
71 #ifndef HEADER
72 #define HEADER
73 
74 
75 
76 
77 // We have 8 target regions, but only 7 that actually will generate offloading
78 // code, only 6 will have mapped arguments, and only 4 have all-constant map
79 // sizes.
80 
81 
82 
83 // Check target registration is registered as a Ctor.
84 
85 
86 template<typename tx, typename ty>
87 struct TT{
88   tx X;
89   ty Y;
90 };
91 
92 int global;
93 
94 int foo(int n) {
95   int a = 0;
96   short aa = 0;
97   float b[10];
98   float bn[n];
99   double c[5][10];
100   double cn[5][n];
101   TT<long long, char> d;
102 
103   #pragma omp target teams distribute num_teams(a) thread_limit(a) firstprivate(aa) nowait
104   for (int i = 0; i < 10; ++i) {
105   }
106 
107   #pragma omp target teams distribute if(target: 0)
108   for (int i = 0; i < 10; ++i) {
109     a += 1;
110   }
111 
112 
113   #pragma omp target teams distribute if(target: 1)
114   for (int i = 0; i < 10; ++i) {
115     aa += 1;
116   }
117 
118 
119 
120   #pragma omp target teams distribute if(target: n>10)
121   for (int i = 0; i < 10; ++i) {
122     a += 1;
123     aa += 1;
124   }
125 
126   // We capture 3 VLA sizes in this target region
127 
128 
129 
130 
131 
132   // The names below are not necessarily consistent with the names used for the
133   // addresses above as some are repeated.
134 
135 
136 
137 
138 
139 
140 
141 
142 
143 
144 
145   #pragma omp target teams distribute if(target: n>20) dist_schedule(static, n)
146   for (int i = 0; i < 10; ++i) {
147     a += 1;
148     b[2] += 1.0;
149     bn[3] += 1.0;
150     c[1][2] += 1.0;
151     cn[1][3] += 1.0;
152     d.X += 1;
153     d.Y += 1;
154   }
155 
156   return a;
157 }
158 
159 // Check that the offloading functions are emitted and that the arguments are
160 // correct and loaded correctly for the target regions in foo().
161 
162 
163 
164 
165 // Create stack storage and store argument in there.
166 
167 // Create stack storage and store argument in there.
168 
169 // Create stack storage and store argument in there.
170 
171 // Create local storage for each capture.
172 
173 
174 
175 // To reduce complexity, we're only going as far as validating the signature of the outlined parallel function.
176 
177 template<typename tx>
178 tx ftemplate(int n) {
179   tx a = 0;
180   short aa = 0;
181   tx b[10];
182 
183   #pragma omp target teams distribute if(target: n>40)
184   for (int i = 0; i < 10; ++i) {
185     a += 1;
186     aa += 1;
187     b[2] += 1;
188   }
189 
190   return a;
191 }
192 
193 static
194 int fstatic(int n) {
195   int a = 0;
196   short aa = 0;
197   char aaa = 0;
198   int b[10];
199 
200   #pragma omp target teams distribute if(target: n>50)
201   for (int i = a; i < n; ++i) {
202     a += 1;
203     aa += 1;
204     aaa += 1;
205     b[2] += 1;
206   }
207 
208   return a;
209 }
210 
211 struct S1 {
212   double a;
213 
214   int r1(int n){
215     int b = n+1;
216     short int c[2][n];
217 
218     #pragma omp target teams distribute if(target: n>60)
219     for (int i = 0; i < 10; ++i) {
220       this->a = (double)b + 1.5;
221       c[1][1] = ++a;
222     }
223 
224     return c[1][1] + (int)b;
225   }
226 };
227 
228 int bar(int n){
229   int a = 0;
230 
231   a += foo(n);
232 
233   S1 S;
234   a += S.r1(n);
235 
236   a += fstatic(n);
237 
238   a += ftemplate<int>(n);
239 
240   return a;
241 }
242 
243 
244 
245 // We capture 2 VLA sizes in this target region
246 
247 
248 // The names below are not necessarily consistent with the names used for the
249 // addresses above as some are repeated.
250 
251 
252 
253 
254 
255 
256 
257 
258 
259 
260 
261 
262 
263 
264 
265 
266 
267 
268 
269 
270 
271 // Check that the offloading functions are emitted and that the arguments are
272 // correct and loaded correctly for the target regions of the callees of bar().
273 
274 // Create local storage for each capture.
275 // Store captures in the context.
276 
277 
278 // To reduce complexity, we're only going as far as validating the signature of the outlined parallel function.
279 
280 
281 // Create local storage for each capture.
282 // Store captures in the context.
283 
284 
285 
286 
287 // To reduce complexity, we're only going as far as validating the signature of the outlined parallel function.
288 
289 // Create local storage for each capture.
290 // Store captures in the context.
291 
292 
293 
294 // To reduce complexity, we're only going as far as validating the signature of the outlined parallel function.
295 
296 #endif
297 // CHECK1-LABEL: define {{[^@]+}}@_Z3fooi
298 // CHECK1-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] {
299 // CHECK1-NEXT:  entry:
300 // CHECK1-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
301 // CHECK1-NEXT:    [[A:%.*]] = alloca i32, align 4
302 // CHECK1-NEXT:    [[AA:%.*]] = alloca i16, align 2
303 // CHECK1-NEXT:    [[B:%.*]] = alloca [10 x float], align 4
304 // CHECK1-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 8
305 // CHECK1-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
306 // CHECK1-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 8
307 // CHECK1-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i64, align 8
308 // CHECK1-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8
309 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
310 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
311 // CHECK1-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
312 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
313 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR__CASTED4:%.*]] = alloca i64, align 8
314 // CHECK1-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8
315 // CHECK1-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8
316 // CHECK1-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8
317 // CHECK1-NEXT:    [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4
318 // CHECK1-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
319 // CHECK1-NEXT:    [[AA_CASTED7:%.*]] = alloca i64, align 8
320 // CHECK1-NEXT:    [[DOTOFFLOAD_BASEPTRS9:%.*]] = alloca [1 x i8*], align 8
321 // CHECK1-NEXT:    [[DOTOFFLOAD_PTRS10:%.*]] = alloca [1 x i8*], align 8
322 // CHECK1-NEXT:    [[DOTOFFLOAD_MAPPERS11:%.*]] = alloca [1 x i8*], align 8
323 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
324 // CHECK1-NEXT:    [[A_CASTED12:%.*]] = alloca i64, align 8
325 // CHECK1-NEXT:    [[AA_CASTED14:%.*]] = alloca i64, align 8
326 // CHECK1-NEXT:    [[DOTOFFLOAD_BASEPTRS16:%.*]] = alloca [2 x i8*], align 8
327 // CHECK1-NEXT:    [[DOTOFFLOAD_PTRS17:%.*]] = alloca [2 x i8*], align 8
328 // CHECK1-NEXT:    [[DOTOFFLOAD_MAPPERS18:%.*]] = alloca [2 x i8*], align 8
329 // CHECK1-NEXT:    [[_TMP19:%.*]] = alloca i32, align 4
330 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR_22:%.*]] = alloca i32, align 4
331 // CHECK1-NEXT:    [[A_CASTED23:%.*]] = alloca i64, align 8
332 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR__CASTED25:%.*]] = alloca i64, align 8
333 // CHECK1-NEXT:    [[DOTOFFLOAD_BASEPTRS29:%.*]] = alloca [10 x i8*], align 8
334 // CHECK1-NEXT:    [[DOTOFFLOAD_PTRS30:%.*]] = alloca [10 x i8*], align 8
335 // CHECK1-NEXT:    [[DOTOFFLOAD_MAPPERS31:%.*]] = alloca [10 x i8*], align 8
336 // CHECK1-NEXT:    [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 8
337 // CHECK1-NEXT:    [[_TMP32:%.*]] = alloca i32, align 4
338 // CHECK1-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]])
339 // CHECK1-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
340 // CHECK1-NEXT:    store i32 0, i32* [[A]], align 4
341 // CHECK1-NEXT:    store i16 0, i16* [[AA]], align 2
342 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
343 // CHECK1-NEXT:    [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
344 // CHECK1-NEXT:    [[TMP3:%.*]] = call i8* @llvm.stacksave()
345 // CHECK1-NEXT:    store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8
346 // CHECK1-NEXT:    [[VLA:%.*]] = alloca float, i64 [[TMP2]], align 4
347 // CHECK1-NEXT:    store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8
348 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
349 // CHECK1-NEXT:    [[TMP5:%.*]] = zext i32 [[TMP4]] to i64
350 // CHECK1-NEXT:    [[TMP6:%.*]] = mul nuw i64 5, [[TMP5]]
351 // CHECK1-NEXT:    [[VLA1:%.*]] = alloca double, i64 [[TMP6]], align 8
352 // CHECK1-NEXT:    store i64 [[TMP5]], i64* [[__VLA_EXPR1]], align 8
353 // CHECK1-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
354 // CHECK1-NEXT:    store i32 [[TMP7]], i32* [[DOTCAPTURE_EXPR_]], align 4
355 // CHECK1-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
356 // CHECK1-NEXT:    store i32 [[TMP8]], i32* [[DOTCAPTURE_EXPR_2]], align 4
357 // CHECK1-NEXT:    [[TMP9:%.*]] = load i16, i16* [[AA]], align 2
358 // CHECK1-NEXT:    [[CONV:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
359 // CHECK1-NEXT:    store i16 [[TMP9]], i16* [[CONV]], align 2
360 // CHECK1-NEXT:    [[TMP10:%.*]] = load i64, i64* [[AA_CASTED]], align 8
361 // CHECK1-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
362 // CHECK1-NEXT:    [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
363 // CHECK1-NEXT:    store i32 [[TMP11]], i32* [[CONV3]], align 4
364 // CHECK1-NEXT:    [[TMP12:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
365 // CHECK1-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
366 // CHECK1-NEXT:    [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED4]] to i32*
367 // CHECK1-NEXT:    store i32 [[TMP13]], i32* [[CONV5]], align 4
368 // CHECK1-NEXT:    [[TMP14:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED4]], align 8
369 // CHECK1-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
370 // CHECK1-NEXT:    [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i64*
371 // CHECK1-NEXT:    store i64 [[TMP10]], i64* [[TMP16]], align 8
372 // CHECK1-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
373 // CHECK1-NEXT:    [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64*
374 // CHECK1-NEXT:    store i64 [[TMP10]], i64* [[TMP18]], align 8
375 // CHECK1-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
376 // CHECK1-NEXT:    store i8* null, i8** [[TMP19]], align 8
377 // CHECK1-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
378 // CHECK1-NEXT:    [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i64*
379 // CHECK1-NEXT:    store i64 [[TMP12]], i64* [[TMP21]], align 8
380 // CHECK1-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
381 // CHECK1-NEXT:    [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i64*
382 // CHECK1-NEXT:    store i64 [[TMP12]], i64* [[TMP23]], align 8
383 // CHECK1-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
384 // CHECK1-NEXT:    store i8* null, i8** [[TMP24]], align 8
385 // CHECK1-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
386 // CHECK1-NEXT:    [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i64*
387 // CHECK1-NEXT:    store i64 [[TMP14]], i64* [[TMP26]], align 8
388 // CHECK1-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
389 // CHECK1-NEXT:    [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i64*
390 // CHECK1-NEXT:    store i64 [[TMP14]], i64* [[TMP28]], align 8
391 // CHECK1-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
392 // CHECK1-NEXT:    store i8* null, i8** [[TMP29]], align 8
393 // CHECK1-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
394 // CHECK1-NEXT:    [[TMP31:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
395 // CHECK1-NEXT:    [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 0
396 // CHECK1-NEXT:    [[TMP33:%.*]] = load i16, i16* [[AA]], align 2
397 // CHECK1-NEXT:    store i16 [[TMP33]], i16* [[TMP32]], align 4
398 // CHECK1-NEXT:    [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 1
399 // CHECK1-NEXT:    [[TMP35:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
400 // CHECK1-NEXT:    store i32 [[TMP35]], i32* [[TMP34]], align 4
401 // CHECK1-NEXT:    [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 2
402 // CHECK1-NEXT:    [[TMP37:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
403 // CHECK1-NEXT:    store i32 [[TMP37]], i32* [[TMP36]], align 4
404 // CHECK1-NEXT:    [[TMP38:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 1, i64 120, i64 12, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1)
405 // CHECK1-NEXT:    [[TMP39:%.*]] = bitcast i8* [[TMP38]] to %struct.kmp_task_t_with_privates*
406 // CHECK1-NEXT:    [[TMP40:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP39]], i32 0, i32 0
407 // CHECK1-NEXT:    [[TMP41:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP40]], i32 0, i32 0
408 // CHECK1-NEXT:    [[TMP42:%.*]] = load i8*, i8** [[TMP41]], align 8
409 // CHECK1-NEXT:    [[TMP43:%.*]] = bitcast %struct.anon* [[AGG_CAPTURED]] to i8*
410 // CHECK1-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP42]], i8* align 4 [[TMP43]], i64 12, i1 false)
411 // CHECK1-NEXT:    [[TMP44:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP39]], i32 0, i32 1
412 // CHECK1-NEXT:    [[TMP45:%.*]] = bitcast i8* [[TMP42]] to %struct.anon*
413 // CHECK1-NEXT:    [[TMP46:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 0
414 // CHECK1-NEXT:    [[TMP47:%.*]] = bitcast [3 x i8*]* [[TMP46]] to i8*
415 // CHECK1-NEXT:    [[TMP48:%.*]] = bitcast i8** [[TMP30]] to i8*
416 // CHECK1-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP47]], i8* align 8 [[TMP48]], i64 24, i1 false)
417 // CHECK1-NEXT:    [[TMP49:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 1
418 // CHECK1-NEXT:    [[TMP50:%.*]] = bitcast [3 x i8*]* [[TMP49]] to i8*
419 // CHECK1-NEXT:    [[TMP51:%.*]] = bitcast i8** [[TMP31]] to i8*
420 // CHECK1-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP50]], i8* align 8 [[TMP51]], i64 24, i1 false)
421 // CHECK1-NEXT:    [[TMP52:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 2
422 // CHECK1-NEXT:    [[TMP53:%.*]] = bitcast [3 x i64]* [[TMP52]] to i8*
423 // CHECK1-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP53]], i8* align 8 bitcast ([3 x i64]* @.offload_sizes to i8*), i64 24, i1 false)
424 // CHECK1-NEXT:    [[TMP54:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 3
425 // CHECK1-NEXT:    [[TMP55:%.*]] = load i16, i16* [[AA]], align 2
426 // CHECK1-NEXT:    store i16 [[TMP55]], i16* [[TMP54]], align 8
427 // CHECK1-NEXT:    [[TMP56:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i8* [[TMP38]])
428 // CHECK1-NEXT:    [[TMP57:%.*]] = load i32, i32* [[A]], align 4
429 // CHECK1-NEXT:    [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32*
430 // CHECK1-NEXT:    store i32 [[TMP57]], i32* [[CONV6]], align 4
431 // CHECK1-NEXT:    [[TMP58:%.*]] = load i64, i64* [[A_CASTED]], align 8
432 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l107(i64 [[TMP58]]) #[[ATTR3:[0-9]+]]
433 // CHECK1-NEXT:    [[TMP59:%.*]] = load i16, i16* [[AA]], align 2
434 // CHECK1-NEXT:    [[CONV8:%.*]] = bitcast i64* [[AA_CASTED7]] to i16*
435 // CHECK1-NEXT:    store i16 [[TMP59]], i16* [[CONV8]], align 2
436 // CHECK1-NEXT:    [[TMP60:%.*]] = load i64, i64* [[AA_CASTED7]], align 8
437 // CHECK1-NEXT:    [[TMP61:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS9]], i32 0, i32 0
438 // CHECK1-NEXT:    [[TMP62:%.*]] = bitcast i8** [[TMP61]] to i64*
439 // CHECK1-NEXT:    store i64 [[TMP60]], i64* [[TMP62]], align 8
440 // CHECK1-NEXT:    [[TMP63:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS10]], i32 0, i32 0
441 // CHECK1-NEXT:    [[TMP64:%.*]] = bitcast i8** [[TMP63]] to i64*
442 // CHECK1-NEXT:    store i64 [[TMP60]], i64* [[TMP64]], align 8
443 // CHECK1-NEXT:    [[TMP65:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS11]], i64 0, i64 0
444 // CHECK1-NEXT:    store i8* null, i8** [[TMP65]], align 8
445 // CHECK1-NEXT:    [[TMP66:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS9]], i32 0, i32 0
446 // CHECK1-NEXT:    [[TMP67:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS10]], i32 0, i32 0
447 // CHECK1-NEXT:    call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10)
448 // CHECK1-NEXT:    [[TMP68:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113.region_id, i32 1, i8** [[TMP66]], i8** [[TMP67]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.4, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.5, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
449 // CHECK1-NEXT:    [[TMP69:%.*]] = icmp ne i32 [[TMP68]], 0
450 // CHECK1-NEXT:    br i1 [[TMP69]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
451 // CHECK1:       omp_offload.failed:
452 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113(i64 [[TMP60]]) #[[ATTR3]]
453 // CHECK1-NEXT:    br label [[OMP_OFFLOAD_CONT]]
454 // CHECK1:       omp_offload.cont:
455 // CHECK1-NEXT:    [[TMP70:%.*]] = load i32, i32* [[A]], align 4
456 // CHECK1-NEXT:    [[CONV13:%.*]] = bitcast i64* [[A_CASTED12]] to i32*
457 // CHECK1-NEXT:    store i32 [[TMP70]], i32* [[CONV13]], align 4
458 // CHECK1-NEXT:    [[TMP71:%.*]] = load i64, i64* [[A_CASTED12]], align 8
459 // CHECK1-NEXT:    [[TMP72:%.*]] = load i16, i16* [[AA]], align 2
460 // CHECK1-NEXT:    [[CONV15:%.*]] = bitcast i64* [[AA_CASTED14]] to i16*
461 // CHECK1-NEXT:    store i16 [[TMP72]], i16* [[CONV15]], align 2
462 // CHECK1-NEXT:    [[TMP73:%.*]] = load i64, i64* [[AA_CASTED14]], align 8
463 // CHECK1-NEXT:    [[TMP74:%.*]] = load i32, i32* [[N_ADDR]], align 4
464 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP74]], 10
465 // CHECK1-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
466 // CHECK1:       omp_if.then:
467 // CHECK1-NEXT:    [[TMP75:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 0
468 // CHECK1-NEXT:    [[TMP76:%.*]] = bitcast i8** [[TMP75]] to i64*
469 // CHECK1-NEXT:    store i64 [[TMP71]], i64* [[TMP76]], align 8
470 // CHECK1-NEXT:    [[TMP77:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 0
471 // CHECK1-NEXT:    [[TMP78:%.*]] = bitcast i8** [[TMP77]] to i64*
472 // CHECK1-NEXT:    store i64 [[TMP71]], i64* [[TMP78]], align 8
473 // CHECK1-NEXT:    [[TMP79:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 0
474 // CHECK1-NEXT:    store i8* null, i8** [[TMP79]], align 8
475 // CHECK1-NEXT:    [[TMP80:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 1
476 // CHECK1-NEXT:    [[TMP81:%.*]] = bitcast i8** [[TMP80]] to i64*
477 // CHECK1-NEXT:    store i64 [[TMP73]], i64* [[TMP81]], align 8
478 // CHECK1-NEXT:    [[TMP82:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 1
479 // CHECK1-NEXT:    [[TMP83:%.*]] = bitcast i8** [[TMP82]] to i64*
480 // CHECK1-NEXT:    store i64 [[TMP73]], i64* [[TMP83]], align 8
481 // CHECK1-NEXT:    [[TMP84:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 1
482 // CHECK1-NEXT:    store i8* null, i8** [[TMP84]], align 8
483 // CHECK1-NEXT:    [[TMP85:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 0
484 // CHECK1-NEXT:    [[TMP86:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 0
485 // CHECK1-NEXT:    call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10)
486 // CHECK1-NEXT:    [[TMP87:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120.region_id, i32 2, i8** [[TMP85]], i8** [[TMP86]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.7, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.8, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
487 // CHECK1-NEXT:    [[TMP88:%.*]] = icmp ne i32 [[TMP87]], 0
488 // CHECK1-NEXT:    br i1 [[TMP88]], label [[OMP_OFFLOAD_FAILED20:%.*]], label [[OMP_OFFLOAD_CONT21:%.*]]
489 // CHECK1:       omp_offload.failed20:
490 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120(i64 [[TMP71]], i64 [[TMP73]]) #[[ATTR3]]
491 // CHECK1-NEXT:    br label [[OMP_OFFLOAD_CONT21]]
492 // CHECK1:       omp_offload.cont21:
493 // CHECK1-NEXT:    br label [[OMP_IF_END:%.*]]
494 // CHECK1:       omp_if.else:
495 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120(i64 [[TMP71]], i64 [[TMP73]]) #[[ATTR3]]
496 // CHECK1-NEXT:    br label [[OMP_IF_END]]
497 // CHECK1:       omp_if.end:
498 // CHECK1-NEXT:    [[TMP89:%.*]] = load i32, i32* [[N_ADDR]], align 4
499 // CHECK1-NEXT:    store i32 [[TMP89]], i32* [[DOTCAPTURE_EXPR_22]], align 4
500 // CHECK1-NEXT:    [[TMP90:%.*]] = load i32, i32* [[A]], align 4
501 // CHECK1-NEXT:    [[CONV24:%.*]] = bitcast i64* [[A_CASTED23]] to i32*
502 // CHECK1-NEXT:    store i32 [[TMP90]], i32* [[CONV24]], align 4
503 // CHECK1-NEXT:    [[TMP91:%.*]] = load i64, i64* [[A_CASTED23]], align 8
504 // CHECK1-NEXT:    [[TMP92:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_22]], align 4
505 // CHECK1-NEXT:    [[CONV26:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED25]] to i32*
506 // CHECK1-NEXT:    store i32 [[TMP92]], i32* [[CONV26]], align 4
507 // CHECK1-NEXT:    [[TMP93:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED25]], align 8
508 // CHECK1-NEXT:    [[TMP94:%.*]] = load i32, i32* [[N_ADDR]], align 4
509 // CHECK1-NEXT:    [[CMP27:%.*]] = icmp sgt i32 [[TMP94]], 20
510 // CHECK1-NEXT:    br i1 [[CMP27]], label [[OMP_IF_THEN28:%.*]], label [[OMP_IF_ELSE35:%.*]]
511 // CHECK1:       omp_if.then28:
512 // CHECK1-NEXT:    [[TMP95:%.*]] = mul nuw i64 [[TMP2]], 4
513 // CHECK1-NEXT:    [[TMP96:%.*]] = mul nuw i64 5, [[TMP5]]
514 // CHECK1-NEXT:    [[TMP97:%.*]] = mul nuw i64 [[TMP96]], 8
515 // CHECK1-NEXT:    [[TMP98:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS29]], i32 0, i32 0
516 // CHECK1-NEXT:    [[TMP99:%.*]] = bitcast i8** [[TMP98]] to i64*
517 // CHECK1-NEXT:    store i64 [[TMP91]], i64* [[TMP99]], align 8
518 // CHECK1-NEXT:    [[TMP100:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS30]], i32 0, i32 0
519 // CHECK1-NEXT:    [[TMP101:%.*]] = bitcast i8** [[TMP100]] to i64*
520 // CHECK1-NEXT:    store i64 [[TMP91]], i64* [[TMP101]], align 8
521 // CHECK1-NEXT:    [[TMP102:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
522 // CHECK1-NEXT:    store i64 4, i64* [[TMP102]], align 8
523 // CHECK1-NEXT:    [[TMP103:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS31]], i64 0, i64 0
524 // CHECK1-NEXT:    store i8* null, i8** [[TMP103]], align 8
525 // CHECK1-NEXT:    [[TMP104:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS29]], i32 0, i32 1
526 // CHECK1-NEXT:    [[TMP105:%.*]] = bitcast i8** [[TMP104]] to [10 x float]**
527 // CHECK1-NEXT:    store [10 x float]* [[B]], [10 x float]** [[TMP105]], align 8
528 // CHECK1-NEXT:    [[TMP106:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS30]], i32 0, i32 1
529 // CHECK1-NEXT:    [[TMP107:%.*]] = bitcast i8** [[TMP106]] to [10 x float]**
530 // CHECK1-NEXT:    store [10 x float]* [[B]], [10 x float]** [[TMP107]], align 8
531 // CHECK1-NEXT:    [[TMP108:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1
532 // CHECK1-NEXT:    store i64 40, i64* [[TMP108]], align 8
533 // CHECK1-NEXT:    [[TMP109:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS31]], i64 0, i64 1
534 // CHECK1-NEXT:    store i8* null, i8** [[TMP109]], align 8
535 // CHECK1-NEXT:    [[TMP110:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS29]], i32 0, i32 2
536 // CHECK1-NEXT:    [[TMP111:%.*]] = bitcast i8** [[TMP110]] to i64*
537 // CHECK1-NEXT:    store i64 [[TMP2]], i64* [[TMP111]], align 8
538 // CHECK1-NEXT:    [[TMP112:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS30]], i32 0, i32 2
539 // CHECK1-NEXT:    [[TMP113:%.*]] = bitcast i8** [[TMP112]] to i64*
540 // CHECK1-NEXT:    store i64 [[TMP2]], i64* [[TMP113]], align 8
541 // CHECK1-NEXT:    [[TMP114:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2
542 // CHECK1-NEXT:    store i64 8, i64* [[TMP114]], align 8
543 // CHECK1-NEXT:    [[TMP115:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS31]], i64 0, i64 2
544 // CHECK1-NEXT:    store i8* null, i8** [[TMP115]], align 8
545 // CHECK1-NEXT:    [[TMP116:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS29]], i32 0, i32 3
546 // CHECK1-NEXT:    [[TMP117:%.*]] = bitcast i8** [[TMP116]] to float**
547 // CHECK1-NEXT:    store float* [[VLA]], float** [[TMP117]], align 8
548 // CHECK1-NEXT:    [[TMP118:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS30]], i32 0, i32 3
549 // CHECK1-NEXT:    [[TMP119:%.*]] = bitcast i8** [[TMP118]] to float**
550 // CHECK1-NEXT:    store float* [[VLA]], float** [[TMP119]], align 8
551 // CHECK1-NEXT:    [[TMP120:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3
552 // CHECK1-NEXT:    store i64 [[TMP95]], i64* [[TMP120]], align 8
553 // CHECK1-NEXT:    [[TMP121:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS31]], i64 0, i64 3
554 // CHECK1-NEXT:    store i8* null, i8** [[TMP121]], align 8
555 // CHECK1-NEXT:    [[TMP122:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS29]], i32 0, i32 4
556 // CHECK1-NEXT:    [[TMP123:%.*]] = bitcast i8** [[TMP122]] to [5 x [10 x double]]**
557 // CHECK1-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP123]], align 8
558 // CHECK1-NEXT:    [[TMP124:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS30]], i32 0, i32 4
559 // CHECK1-NEXT:    [[TMP125:%.*]] = bitcast i8** [[TMP124]] to [5 x [10 x double]]**
560 // CHECK1-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP125]], align 8
561 // CHECK1-NEXT:    [[TMP126:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4
562 // CHECK1-NEXT:    store i64 400, i64* [[TMP126]], align 8
563 // CHECK1-NEXT:    [[TMP127:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS31]], i64 0, i64 4
564 // CHECK1-NEXT:    store i8* null, i8** [[TMP127]], align 8
565 // CHECK1-NEXT:    [[TMP128:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS29]], i32 0, i32 5
566 // CHECK1-NEXT:    [[TMP129:%.*]] = bitcast i8** [[TMP128]] to i64*
567 // CHECK1-NEXT:    store i64 5, i64* [[TMP129]], align 8
568 // CHECK1-NEXT:    [[TMP130:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS30]], i32 0, i32 5
569 // CHECK1-NEXT:    [[TMP131:%.*]] = bitcast i8** [[TMP130]] to i64*
570 // CHECK1-NEXT:    store i64 5, i64* [[TMP131]], align 8
571 // CHECK1-NEXT:    [[TMP132:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 5
572 // CHECK1-NEXT:    store i64 8, i64* [[TMP132]], align 8
573 // CHECK1-NEXT:    [[TMP133:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS31]], i64 0, i64 5
574 // CHECK1-NEXT:    store i8* null, i8** [[TMP133]], align 8
575 // CHECK1-NEXT:    [[TMP134:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS29]], i32 0, i32 6
576 // CHECK1-NEXT:    [[TMP135:%.*]] = bitcast i8** [[TMP134]] to i64*
577 // CHECK1-NEXT:    store i64 [[TMP5]], i64* [[TMP135]], align 8
578 // CHECK1-NEXT:    [[TMP136:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS30]], i32 0, i32 6
579 // CHECK1-NEXT:    [[TMP137:%.*]] = bitcast i8** [[TMP136]] to i64*
580 // CHECK1-NEXT:    store i64 [[TMP5]], i64* [[TMP137]], align 8
581 // CHECK1-NEXT:    [[TMP138:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 6
582 // CHECK1-NEXT:    store i64 8, i64* [[TMP138]], align 8
583 // CHECK1-NEXT:    [[TMP139:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS31]], i64 0, i64 6
584 // CHECK1-NEXT:    store i8* null, i8** [[TMP139]], align 8
585 // CHECK1-NEXT:    [[TMP140:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS29]], i32 0, i32 7
586 // CHECK1-NEXT:    [[TMP141:%.*]] = bitcast i8** [[TMP140]] to double**
587 // CHECK1-NEXT:    store double* [[VLA1]], double** [[TMP141]], align 8
588 // CHECK1-NEXT:    [[TMP142:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS30]], i32 0, i32 7
589 // CHECK1-NEXT:    [[TMP143:%.*]] = bitcast i8** [[TMP142]] to double**
590 // CHECK1-NEXT:    store double* [[VLA1]], double** [[TMP143]], align 8
591 // CHECK1-NEXT:    [[TMP144:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7
592 // CHECK1-NEXT:    store i64 [[TMP97]], i64* [[TMP144]], align 8
593 // CHECK1-NEXT:    [[TMP145:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS31]], i64 0, i64 7
594 // CHECK1-NEXT:    store i8* null, i8** [[TMP145]], align 8
595 // CHECK1-NEXT:    [[TMP146:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS29]], i32 0, i32 8
596 // CHECK1-NEXT:    [[TMP147:%.*]] = bitcast i8** [[TMP146]] to %struct.TT**
597 // CHECK1-NEXT:    store %struct.TT* [[D]], %struct.TT** [[TMP147]], align 8
598 // CHECK1-NEXT:    [[TMP148:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS30]], i32 0, i32 8
599 // CHECK1-NEXT:    [[TMP149:%.*]] = bitcast i8** [[TMP148]] to %struct.TT**
600 // CHECK1-NEXT:    store %struct.TT* [[D]], %struct.TT** [[TMP149]], align 8
601 // CHECK1-NEXT:    [[TMP150:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 8
602 // CHECK1-NEXT:    store i64 16, i64* [[TMP150]], align 8
603 // CHECK1-NEXT:    [[TMP151:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS31]], i64 0, i64 8
604 // CHECK1-NEXT:    store i8* null, i8** [[TMP151]], align 8
605 // CHECK1-NEXT:    [[TMP152:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS29]], i32 0, i32 9
606 // CHECK1-NEXT:    [[TMP153:%.*]] = bitcast i8** [[TMP152]] to i64*
607 // CHECK1-NEXT:    store i64 [[TMP93]], i64* [[TMP153]], align 8
608 // CHECK1-NEXT:    [[TMP154:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS30]], i32 0, i32 9
609 // CHECK1-NEXT:    [[TMP155:%.*]] = bitcast i8** [[TMP154]] to i64*
610 // CHECK1-NEXT:    store i64 [[TMP93]], i64* [[TMP155]], align 8
611 // CHECK1-NEXT:    [[TMP156:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 9
612 // CHECK1-NEXT:    store i64 4, i64* [[TMP156]], align 8
613 // CHECK1-NEXT:    [[TMP157:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS31]], i64 0, i64 9
614 // CHECK1-NEXT:    store i8* null, i8** [[TMP157]], align 8
615 // CHECK1-NEXT:    [[TMP158:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS29]], i32 0, i32 0
616 // CHECK1-NEXT:    [[TMP159:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS30]], i32 0, i32 0
617 // CHECK1-NEXT:    [[TMP160:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
618 // CHECK1-NEXT:    call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10)
619 // CHECK1-NEXT:    [[TMP161:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145.region_id, i32 10, i8** [[TMP158]], i8** [[TMP159]], i64* [[TMP160]], i64* getelementptr inbounds ([10 x i64], [10 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
620 // CHECK1-NEXT:    [[TMP162:%.*]] = icmp ne i32 [[TMP161]], 0
621 // CHECK1-NEXT:    br i1 [[TMP162]], label [[OMP_OFFLOAD_FAILED33:%.*]], label [[OMP_OFFLOAD_CONT34:%.*]]
622 // CHECK1:       omp_offload.failed33:
623 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145(i64 [[TMP91]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]], i64 [[TMP93]]) #[[ATTR3]]
624 // CHECK1-NEXT:    br label [[OMP_OFFLOAD_CONT34]]
625 // CHECK1:       omp_offload.cont34:
626 // CHECK1-NEXT:    br label [[OMP_IF_END36:%.*]]
627 // CHECK1:       omp_if.else35:
628 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145(i64 [[TMP91]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]], i64 [[TMP93]]) #[[ATTR3]]
629 // CHECK1-NEXT:    br label [[OMP_IF_END36]]
630 // CHECK1:       omp_if.end36:
631 // CHECK1-NEXT:    [[TMP163:%.*]] = load i32, i32* [[A]], align 4
632 // CHECK1-NEXT:    [[TMP164:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
633 // CHECK1-NEXT:    call void @llvm.stackrestore(i8* [[TMP164]])
634 // CHECK1-NEXT:    ret i32 [[TMP163]]
635 //
636 //
637 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103
638 // CHECK1-SAME: (i64 [[AA:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] {
639 // CHECK1-NEXT:  entry:
640 // CHECK1-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
641 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
642 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8
643 // CHECK1-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
644 // CHECK1-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]])
645 // CHECK1-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
646 // CHECK1-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
647 // CHECK1-NEXT:    store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8
648 // CHECK1-NEXT:    [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
649 // CHECK1-NEXT:    [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
650 // CHECK1-NEXT:    [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32*
651 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 8
652 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 8
653 // CHECK1-NEXT:    call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
654 // CHECK1-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV]], align 8
655 // CHECK1-NEXT:    [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
656 // CHECK1-NEXT:    store i16 [[TMP3]], i16* [[CONV5]], align 2
657 // CHECK1-NEXT:    [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
658 // CHECK1-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]])
659 // CHECK1-NEXT:    ret void
660 //
661 //
662 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined.
663 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] {
664 // CHECK1-NEXT:  entry:
665 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
666 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
667 // CHECK1-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
668 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
669 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
670 // CHECK1-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
671 // CHECK1-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
672 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
673 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
674 // CHECK1-NEXT:    [[I:%.*]] = alloca i32, align 4
675 // CHECK1-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
676 // CHECK1-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
677 // CHECK1-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
678 // CHECK1-NEXT:    [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
679 // CHECK1-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
680 // CHECK1-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
681 // CHECK1-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
682 // CHECK1-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
683 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
684 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
685 // CHECK1-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
686 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
687 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
688 // CHECK1-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
689 // CHECK1:       cond.true:
690 // CHECK1-NEXT:    br label [[COND_END:%.*]]
691 // CHECK1:       cond.false:
692 // CHECK1-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
693 // CHECK1-NEXT:    br label [[COND_END]]
694 // CHECK1:       cond.end:
695 // CHECK1-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
696 // CHECK1-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
697 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
698 // CHECK1-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
699 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
700 // CHECK1:       omp.inner.for.cond:
701 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
702 // CHECK1-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
703 // CHECK1-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
704 // CHECK1-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
705 // CHECK1:       omp.inner.for.body:
706 // CHECK1-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
707 // CHECK1-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
708 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
709 // CHECK1-NEXT:    store i32 [[ADD]], i32* [[I]], align 4
710 // CHECK1-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
711 // CHECK1:       omp.body.continue:
712 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
713 // CHECK1:       omp.inner.for.inc:
714 // CHECK1-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
715 // CHECK1-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
716 // CHECK1-NEXT:    store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4
717 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]]
718 // CHECK1:       omp.inner.for.end:
719 // CHECK1-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
720 // CHECK1:       omp.loop.exit:
721 // CHECK1-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
722 // CHECK1-NEXT:    ret void
723 //
724 //
725 // CHECK1-LABEL: define {{[^@]+}}@.omp_task_privates_map.
726 // CHECK1-SAME: (%struct..kmp_privates.t* noalias [[TMP0:%.*]], i16** noalias [[TMP1:%.*]], [3 x i8*]** noalias [[TMP2:%.*]], [3 x i8*]** noalias [[TMP3:%.*]], [3 x i64]** noalias [[TMP4:%.*]]) #[[ATTR4:[0-9]+]] {
727 // CHECK1-NEXT:  entry:
728 // CHECK1-NEXT:    [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 8
729 // CHECK1-NEXT:    [[DOTADDR1:%.*]] = alloca i16**, align 8
730 // CHECK1-NEXT:    [[DOTADDR2:%.*]] = alloca [3 x i8*]**, align 8
731 // CHECK1-NEXT:    [[DOTADDR3:%.*]] = alloca [3 x i8*]**, align 8
732 // CHECK1-NEXT:    [[DOTADDR4:%.*]] = alloca [3 x i64]**, align 8
733 // CHECK1-NEXT:    store %struct..kmp_privates.t* [[TMP0]], %struct..kmp_privates.t** [[DOTADDR]], align 8
734 // CHECK1-NEXT:    store i16** [[TMP1]], i16*** [[DOTADDR1]], align 8
735 // CHECK1-NEXT:    store [3 x i8*]** [[TMP2]], [3 x i8*]*** [[DOTADDR2]], align 8
736 // CHECK1-NEXT:    store [3 x i8*]** [[TMP3]], [3 x i8*]*** [[DOTADDR3]], align 8
737 // CHECK1-NEXT:    store [3 x i64]** [[TMP4]], [3 x i64]*** [[DOTADDR4]], align 8
738 // CHECK1-NEXT:    [[TMP5:%.*]] = load %struct..kmp_privates.t*, %struct..kmp_privates.t** [[DOTADDR]], align 8
739 // CHECK1-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 0
740 // CHECK1-NEXT:    [[TMP7:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR2]], align 8
741 // CHECK1-NEXT:    store [3 x i8*]* [[TMP6]], [3 x i8*]** [[TMP7]], align 8
742 // CHECK1-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 1
743 // CHECK1-NEXT:    [[TMP9:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR3]], align 8
744 // CHECK1-NEXT:    store [3 x i8*]* [[TMP8]], [3 x i8*]** [[TMP9]], align 8
745 // CHECK1-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 2
746 // CHECK1-NEXT:    [[TMP11:%.*]] = load [3 x i64]**, [3 x i64]*** [[DOTADDR4]], align 8
747 // CHECK1-NEXT:    store [3 x i64]* [[TMP10]], [3 x i64]** [[TMP11]], align 8
748 // CHECK1-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 3
749 // CHECK1-NEXT:    [[TMP13:%.*]] = load i16**, i16*** [[DOTADDR1]], align 8
750 // CHECK1-NEXT:    store i16* [[TMP12]], i16** [[TMP13]], align 8
751 // CHECK1-NEXT:    ret void
752 //
753 //
754 // CHECK1-LABEL: define {{[^@]+}}@.omp_task_entry.
755 // CHECK1-SAME: (i32 signext [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] {
756 // CHECK1-NEXT:  entry:
757 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
758 // CHECK1-NEXT:    [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8
759 // CHECK1-NEXT:    [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8
760 // CHECK1-NEXT:    [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8
761 // CHECK1-NEXT:    [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8
762 // CHECK1-NEXT:    [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 8
763 // CHECK1-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca i16*, align 8
764 // CHECK1-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca [3 x i8*]*, align 8
765 // CHECK1-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca [3 x i8*]*, align 8
766 // CHECK1-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca [3 x i64]*, align 8
767 // CHECK1-NEXT:    [[AA_CASTED_I:%.*]] = alloca i64, align 8
768 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR__CASTED_I:%.*]] = alloca i64, align 8
769 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR__CASTED5_I:%.*]] = alloca i64, align 8
770 // CHECK1-NEXT:    [[DOTADDR:%.*]] = alloca i32, align 4
771 // CHECK1-NEXT:    [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8
772 // CHECK1-NEXT:    store i32 [[TMP0]], i32* [[DOTADDR]], align 4
773 // CHECK1-NEXT:    store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8
774 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4
775 // CHECK1-NEXT:    [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8
776 // CHECK1-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
777 // CHECK1-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
778 // CHECK1-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0
779 // CHECK1-NEXT:    [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8
780 // CHECK1-NEXT:    [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon*
781 // CHECK1-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1
782 // CHECK1-NEXT:    [[TMP10:%.*]] = bitcast %struct..kmp_privates.t* [[TMP9]] to i8*
783 // CHECK1-NEXT:    [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8*
784 // CHECK1-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META11:![0-9]+]])
785 // CHECK1-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META14:![0-9]+]])
786 // CHECK1-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META16:![0-9]+]])
787 // CHECK1-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]])
788 // CHECK1-NEXT:    store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !20
789 // CHECK1-NEXT:    store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !20
790 // CHECK1-NEXT:    store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !20
791 // CHECK1-NEXT:    store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* @.omp_task_privates_map. to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !20
792 // CHECK1-NEXT:    store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !20
793 // CHECK1-NEXT:    store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !20
794 // CHECK1-NEXT:    [[TMP12:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !20
795 // CHECK1-NEXT:    [[TMP13:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !20
796 // CHECK1-NEXT:    [[TMP14:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !20
797 // CHECK1-NEXT:    [[TMP15:%.*]] = bitcast void (i8*, ...)* [[TMP13]] to void (i8*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)*
798 // CHECK1-NEXT:    call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]]
799 // CHECK1-NEXT:    [[TMP16:%.*]] = load i16*, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !20
800 // CHECK1-NEXT:    [[TMP17:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !20
801 // CHECK1-NEXT:    [[TMP18:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 8, !noalias !20
802 // CHECK1-NEXT:    [[TMP19:%.*]] = load [3 x i64]*, [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 8, !noalias !20
803 // CHECK1-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP17]], i64 0, i64 0
804 // CHECK1-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP18]], i64 0, i64 0
805 // CHECK1-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[TMP19]], i64 0, i64 0
806 // CHECK1-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP12]], i32 0, i32 1
807 // CHECK1-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[TMP12]], i32 0, i32 2
808 // CHECK1-NEXT:    [[TMP25:%.*]] = load i32, i32* [[TMP23]], align 4
809 // CHECK1-NEXT:    [[TMP26:%.*]] = load i32, i32* [[TMP24]], align 4
810 // CHECK1-NEXT:    call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) #[[ATTR3]]
811 // CHECK1-NEXT:    [[TMP27:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 [[TMP25]], i32 [[TMP26]]) #[[ATTR3]]
812 // CHECK1-NEXT:    [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0
813 // CHECK1-NEXT:    br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]]
814 // CHECK1:       omp_offload.failed.i:
815 // CHECK1-NEXT:    [[TMP29:%.*]] = load i16, i16* [[TMP16]], align 2
816 // CHECK1-NEXT:    [[CONV_I:%.*]] = bitcast i64* [[AA_CASTED_I]] to i16*
817 // CHECK1-NEXT:    store i16 [[TMP29]], i16* [[CONV_I]], align 2, !noalias !20
818 // CHECK1-NEXT:    [[TMP30:%.*]] = load i64, i64* [[AA_CASTED_I]], align 8, !noalias !20
819 // CHECK1-NEXT:    [[TMP31:%.*]] = load i32, i32* [[TMP23]], align 4
820 // CHECK1-NEXT:    [[CONV4_I:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED_I]] to i32*
821 // CHECK1-NEXT:    store i32 [[TMP31]], i32* [[CONV4_I]], align 4, !noalias !20
822 // CHECK1-NEXT:    [[TMP32:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED_I]], align 8, !noalias !20
823 // CHECK1-NEXT:    [[TMP33:%.*]] = load i32, i32* [[TMP24]], align 4
824 // CHECK1-NEXT:    [[CONV6_I:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED5_I]] to i32*
825 // CHECK1-NEXT:    store i32 [[TMP33]], i32* [[CONV6_I]], align 4, !noalias !20
826 // CHECK1-NEXT:    [[TMP34:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED5_I]], align 8, !noalias !20
827 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103(i64 [[TMP30]], i64 [[TMP32]], i64 [[TMP34]]) #[[ATTR3]]
828 // CHECK1-NEXT:    br label [[DOTOMP_OUTLINED__1_EXIT]]
829 // CHECK1:       .omp_outlined..1.exit:
830 // CHECK1-NEXT:    ret i32 0
831 //
832 //
833 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l107
834 // CHECK1-SAME: (i64 [[A:%.*]]) #[[ATTR2]] {
835 // CHECK1-NEXT:  entry:
836 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
837 // CHECK1-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
838 // CHECK1-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
839 // CHECK1-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
840 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
841 // CHECK1-NEXT:    [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32*
842 // CHECK1-NEXT:    store i32 [[TMP0]], i32* [[CONV1]], align 4
843 // CHECK1-NEXT:    [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
844 // CHECK1-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]])
845 // CHECK1-NEXT:    ret void
846 //
847 //
848 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..2
849 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]]) #[[ATTR2]] {
850 // CHECK1-NEXT:  entry:
851 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
852 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
853 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
854 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
855 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
856 // CHECK1-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
857 // CHECK1-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
858 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
859 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
860 // CHECK1-NEXT:    [[I:%.*]] = alloca i32, align 4
861 // CHECK1-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
862 // CHECK1-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
863 // CHECK1-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
864 // CHECK1-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
865 // CHECK1-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
866 // CHECK1-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
867 // CHECK1-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
868 // CHECK1-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
869 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
870 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
871 // CHECK1-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
872 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
873 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
874 // CHECK1-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
875 // CHECK1:       cond.true:
876 // CHECK1-NEXT:    br label [[COND_END:%.*]]
877 // CHECK1:       cond.false:
878 // CHECK1-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
879 // CHECK1-NEXT:    br label [[COND_END]]
880 // CHECK1:       cond.end:
881 // CHECK1-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
882 // CHECK1-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
883 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
884 // CHECK1-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
885 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
886 // CHECK1:       omp.inner.for.cond:
887 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
888 // CHECK1-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
889 // CHECK1-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
890 // CHECK1-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
891 // CHECK1:       omp.inner.for.body:
892 // CHECK1-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
893 // CHECK1-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
894 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
895 // CHECK1-NEXT:    store i32 [[ADD]], i32* [[I]], align 4
896 // CHECK1-NEXT:    [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
897 // CHECK1-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
898 // CHECK1-NEXT:    store i32 [[ADD2]], i32* [[CONV]], align 8
899 // CHECK1-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
900 // CHECK1:       omp.body.continue:
901 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
902 // CHECK1:       omp.inner.for.inc:
903 // CHECK1-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
904 // CHECK1-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1
905 // CHECK1-NEXT:    store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4
906 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]]
907 // CHECK1:       omp.inner.for.end:
908 // CHECK1-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
909 // CHECK1:       omp.loop.exit:
910 // CHECK1-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
911 // CHECK1-NEXT:    ret void
912 //
913 //
914 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113
915 // CHECK1-SAME: (i64 [[AA:%.*]]) #[[ATTR2]] {
916 // CHECK1-NEXT:  entry:
917 // CHECK1-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
918 // CHECK1-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
919 // CHECK1-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
920 // CHECK1-NEXT:    [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
921 // CHECK1-NEXT:    [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8
922 // CHECK1-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
923 // CHECK1-NEXT:    store i16 [[TMP0]], i16* [[CONV1]], align 2
924 // CHECK1-NEXT:    [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
925 // CHECK1-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP1]])
926 // CHECK1-NEXT:    ret void
927 //
928 //
929 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..3
930 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] {
931 // CHECK1-NEXT:  entry:
932 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
933 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
934 // CHECK1-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
935 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
936 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
937 // CHECK1-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
938 // CHECK1-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
939 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
940 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
941 // CHECK1-NEXT:    [[I:%.*]] = alloca i32, align 4
942 // CHECK1-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
943 // CHECK1-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
944 // CHECK1-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
945 // CHECK1-NEXT:    [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
946 // CHECK1-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
947 // CHECK1-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
948 // CHECK1-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
949 // CHECK1-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
950 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
951 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
952 // CHECK1-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
953 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
954 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
955 // CHECK1-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
956 // CHECK1:       cond.true:
957 // CHECK1-NEXT:    br label [[COND_END:%.*]]
958 // CHECK1:       cond.false:
959 // CHECK1-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
960 // CHECK1-NEXT:    br label [[COND_END]]
961 // CHECK1:       cond.end:
962 // CHECK1-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
963 // CHECK1-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
964 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
965 // CHECK1-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
966 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
967 // CHECK1:       omp.inner.for.cond:
968 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
969 // CHECK1-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
970 // CHECK1-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
971 // CHECK1-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
972 // CHECK1:       omp.inner.for.body:
973 // CHECK1-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
974 // CHECK1-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
975 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
976 // CHECK1-NEXT:    store i32 [[ADD]], i32* [[I]], align 4
977 // CHECK1-NEXT:    [[TMP8:%.*]] = load i16, i16* [[CONV]], align 8
978 // CHECK1-NEXT:    [[CONV2:%.*]] = sext i16 [[TMP8]] to i32
979 // CHECK1-NEXT:    [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
980 // CHECK1-NEXT:    [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
981 // CHECK1-NEXT:    store i16 [[CONV4]], i16* [[CONV]], align 8
982 // CHECK1-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
983 // CHECK1:       omp.body.continue:
984 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
985 // CHECK1:       omp.inner.for.inc:
986 // CHECK1-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
987 // CHECK1-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP9]], 1
988 // CHECK1-NEXT:    store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4
989 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]]
990 // CHECK1:       omp.inner.for.end:
991 // CHECK1-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
992 // CHECK1:       omp.loop.exit:
993 // CHECK1-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
994 // CHECK1-NEXT:    ret void
995 //
996 //
997 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120
998 // CHECK1-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] {
999 // CHECK1-NEXT:  entry:
1000 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
1001 // CHECK1-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
1002 // CHECK1-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
1003 // CHECK1-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
1004 // CHECK1-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
1005 // CHECK1-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
1006 // CHECK1-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
1007 // CHECK1-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
1008 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
1009 // CHECK1-NEXT:    [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
1010 // CHECK1-NEXT:    store i32 [[TMP0]], i32* [[CONV2]], align 4
1011 // CHECK1-NEXT:    [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
1012 // CHECK1-NEXT:    [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
1013 // CHECK1-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
1014 // CHECK1-NEXT:    store i16 [[TMP2]], i16* [[CONV3]], align 2
1015 // CHECK1-NEXT:    [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
1016 // CHECK1-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
1017 // CHECK1-NEXT:    ret void
1018 //
1019 //
1020 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..6
1021 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] {
1022 // CHECK1-NEXT:  entry:
1023 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
1024 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
1025 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
1026 // CHECK1-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
1027 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
1028 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
1029 // CHECK1-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
1030 // CHECK1-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
1031 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1032 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1033 // CHECK1-NEXT:    [[I:%.*]] = alloca i32, align 4
1034 // CHECK1-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
1035 // CHECK1-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
1036 // CHECK1-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
1037 // CHECK1-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
1038 // CHECK1-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
1039 // CHECK1-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
1040 // CHECK1-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
1041 // CHECK1-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
1042 // CHECK1-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
1043 // CHECK1-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
1044 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
1045 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
1046 // CHECK1-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
1047 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1048 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
1049 // CHECK1-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1050 // CHECK1:       cond.true:
1051 // CHECK1-NEXT:    br label [[COND_END:%.*]]
1052 // CHECK1:       cond.false:
1053 // CHECK1-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1054 // CHECK1-NEXT:    br label [[COND_END]]
1055 // CHECK1:       cond.end:
1056 // CHECK1-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
1057 // CHECK1-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
1058 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
1059 // CHECK1-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
1060 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
1061 // CHECK1:       omp.inner.for.cond:
1062 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1063 // CHECK1-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1064 // CHECK1-NEXT:    [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
1065 // CHECK1-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1066 // CHECK1:       omp.inner.for.body:
1067 // CHECK1-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1068 // CHECK1-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
1069 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1070 // CHECK1-NEXT:    store i32 [[ADD]], i32* [[I]], align 4
1071 // CHECK1-NEXT:    [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
1072 // CHECK1-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
1073 // CHECK1-NEXT:    store i32 [[ADD3]], i32* [[CONV]], align 8
1074 // CHECK1-NEXT:    [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 8
1075 // CHECK1-NEXT:    [[CONV4:%.*]] = sext i16 [[TMP9]] to i32
1076 // CHECK1-NEXT:    [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
1077 // CHECK1-NEXT:    [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
1078 // CHECK1-NEXT:    store i16 [[CONV6]], i16* [[CONV1]], align 8
1079 // CHECK1-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
1080 // CHECK1:       omp.body.continue:
1081 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
1082 // CHECK1:       omp.inner.for.inc:
1083 // CHECK1-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1084 // CHECK1-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1
1085 // CHECK1-NEXT:    store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4
1086 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]]
1087 // CHECK1:       omp.inner.for.end:
1088 // CHECK1-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
1089 // CHECK1:       omp.loop.exit:
1090 // CHECK1-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
1091 // CHECK1-NEXT:    ret void
1092 //
1093 //
1094 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145
1095 // CHECK1-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] {
1096 // CHECK1-NEXT:  entry:
1097 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
1098 // CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
1099 // CHECK1-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
1100 // CHECK1-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 8
1101 // CHECK1-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
1102 // CHECK1-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
1103 // CHECK1-NEXT:    [[VLA_ADDR4:%.*]] = alloca i64, align 8
1104 // CHECK1-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 8
1105 // CHECK1-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
1106 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
1107 // CHECK1-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
1108 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
1109 // CHECK1-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
1110 // CHECK1-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
1111 // CHECK1-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
1112 // CHECK1-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 8
1113 // CHECK1-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
1114 // CHECK1-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
1115 // CHECK1-NEXT:    store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
1116 // CHECK1-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 8
1117 // CHECK1-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
1118 // CHECK1-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
1119 // CHECK1-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
1120 // CHECK1-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
1121 // CHECK1-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
1122 // CHECK1-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
1123 // CHECK1-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
1124 // CHECK1-NEXT:    [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
1125 // CHECK1-NEXT:    [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
1126 // CHECK1-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
1127 // CHECK1-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
1128 // CHECK1-NEXT:    [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
1129 // CHECK1-NEXT:    [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
1130 // CHECK1-NEXT:    [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32*
1131 // CHECK1-NEXT:    store i32 [[TMP8]], i32* [[CONV6]], align 4
1132 // CHECK1-NEXT:    [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
1133 // CHECK1-NEXT:    [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 8
1134 // CHECK1-NEXT:    [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
1135 // CHECK1-NEXT:    store i32 [[TMP10]], i32* [[CONV7]], align 4
1136 // CHECK1-NEXT:    [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
1137 // CHECK1-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]])
1138 // CHECK1-NEXT:    ret void
1139 //
1140 //
1141 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..9
1142 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] {
1143 // CHECK1-NEXT:  entry:
1144 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
1145 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
1146 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
1147 // CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
1148 // CHECK1-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
1149 // CHECK1-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 8
1150 // CHECK1-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
1151 // CHECK1-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
1152 // CHECK1-NEXT:    [[VLA_ADDR4:%.*]] = alloca i64, align 8
1153 // CHECK1-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 8
1154 // CHECK1-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
1155 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
1156 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
1157 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
1158 // CHECK1-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
1159 // CHECK1-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
1160 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1161 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1162 // CHECK1-NEXT:    [[I:%.*]] = alloca i32, align 4
1163 // CHECK1-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
1164 // CHECK1-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
1165 // CHECK1-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
1166 // CHECK1-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
1167 // CHECK1-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
1168 // CHECK1-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 8
1169 // CHECK1-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
1170 // CHECK1-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
1171 // CHECK1-NEXT:    store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
1172 // CHECK1-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 8
1173 // CHECK1-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
1174 // CHECK1-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
1175 // CHECK1-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
1176 // CHECK1-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
1177 // CHECK1-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
1178 // CHECK1-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
1179 // CHECK1-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
1180 // CHECK1-NEXT:    [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
1181 // CHECK1-NEXT:    [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
1182 // CHECK1-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
1183 // CHECK1-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
1184 // CHECK1-NEXT:    [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
1185 // CHECK1-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
1186 // CHECK1-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
1187 // CHECK1-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
1188 // CHECK1-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
1189 // CHECK1-NEXT:    [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 8
1190 // CHECK1-NEXT:    [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
1191 // CHECK1-NEXT:    [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
1192 // CHECK1-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
1193 // CHECK1-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
1194 // CHECK1:       omp.dispatch.cond:
1195 // CHECK1-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1196 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 9
1197 // CHECK1-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1198 // CHECK1:       cond.true:
1199 // CHECK1-NEXT:    br label [[COND_END:%.*]]
1200 // CHECK1:       cond.false:
1201 // CHECK1-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1202 // CHECK1-NEXT:    br label [[COND_END]]
1203 // CHECK1:       cond.end:
1204 // CHECK1-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
1205 // CHECK1-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
1206 // CHECK1-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
1207 // CHECK1-NEXT:    store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
1208 // CHECK1-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1209 // CHECK1-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1210 // CHECK1-NEXT:    [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
1211 // CHECK1-NEXT:    br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
1212 // CHECK1:       omp.dispatch.body:
1213 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
1214 // CHECK1:       omp.inner.for.cond:
1215 // CHECK1-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
1216 // CHECK1-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !21
1217 // CHECK1-NEXT:    [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
1218 // CHECK1-NEXT:    br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1219 // CHECK1:       omp.inner.for.body:
1220 // CHECK1-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
1221 // CHECK1-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
1222 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1223 // CHECK1-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !21
1224 // CHECK1-NEXT:    [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !21
1225 // CHECK1-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP19]], 1
1226 // CHECK1-NEXT:    store i32 [[ADD8]], i32* [[CONV]], align 8, !llvm.access.group !21
1227 // CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
1228 // CHECK1-NEXT:    [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !21
1229 // CHECK1-NEXT:    [[CONV9:%.*]] = fpext float [[TMP20]] to double
1230 // CHECK1-NEXT:    [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00
1231 // CHECK1-NEXT:    [[CONV11:%.*]] = fptrunc double [[ADD10]] to float
1232 // CHECK1-NEXT:    store float [[CONV11]], float* [[ARRAYIDX]], align 4, !llvm.access.group !21
1233 // CHECK1-NEXT:    [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3
1234 // CHECK1-NEXT:    [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4, !llvm.access.group !21
1235 // CHECK1-NEXT:    [[CONV13:%.*]] = fpext float [[TMP21]] to double
1236 // CHECK1-NEXT:    [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00
1237 // CHECK1-NEXT:    [[CONV15:%.*]] = fptrunc double [[ADD14]] to float
1238 // CHECK1-NEXT:    store float [[CONV15]], float* [[ARRAYIDX12]], align 4, !llvm.access.group !21
1239 // CHECK1-NEXT:    [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1
1240 // CHECK1-NEXT:    [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i64 0, i64 2
1241 // CHECK1-NEXT:    [[TMP22:%.*]] = load double, double* [[ARRAYIDX17]], align 8, !llvm.access.group !21
1242 // CHECK1-NEXT:    [[ADD18:%.*]] = fadd double [[TMP22]], 1.000000e+00
1243 // CHECK1-NEXT:    store double [[ADD18]], double* [[ARRAYIDX17]], align 8, !llvm.access.group !21
1244 // CHECK1-NEXT:    [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]]
1245 // CHECK1-NEXT:    [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP23]]
1246 // CHECK1-NEXT:    [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i64 3
1247 // CHECK1-NEXT:    [[TMP24:%.*]] = load double, double* [[ARRAYIDX20]], align 8, !llvm.access.group !21
1248 // CHECK1-NEXT:    [[ADD21:%.*]] = fadd double [[TMP24]], 1.000000e+00
1249 // CHECK1-NEXT:    store double [[ADD21]], double* [[ARRAYIDX20]], align 8, !llvm.access.group !21
1250 // CHECK1-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0
1251 // CHECK1-NEXT:    [[TMP25:%.*]] = load i64, i64* [[X]], align 8, !llvm.access.group !21
1252 // CHECK1-NEXT:    [[ADD22:%.*]] = add nsw i64 [[TMP25]], 1
1253 // CHECK1-NEXT:    store i64 [[ADD22]], i64* [[X]], align 8, !llvm.access.group !21
1254 // CHECK1-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1
1255 // CHECK1-NEXT:    [[TMP26:%.*]] = load i8, i8* [[Y]], align 8, !llvm.access.group !21
1256 // CHECK1-NEXT:    [[CONV23:%.*]] = sext i8 [[TMP26]] to i32
1257 // CHECK1-NEXT:    [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1
1258 // CHECK1-NEXT:    [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8
1259 // CHECK1-NEXT:    store i8 [[CONV25]], i8* [[Y]], align 8, !llvm.access.group !21
1260 // CHECK1-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
1261 // CHECK1:       omp.body.continue:
1262 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
1263 // CHECK1:       omp.inner.for.inc:
1264 // CHECK1-NEXT:    [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
1265 // CHECK1-NEXT:    [[ADD26:%.*]] = add nsw i32 [[TMP27]], 1
1266 // CHECK1-NEXT:    store i32 [[ADD26]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
1267 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]]
1268 // CHECK1:       omp.inner.for.end:
1269 // CHECK1-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
1270 // CHECK1:       omp.dispatch.inc:
1271 // CHECK1-NEXT:    [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
1272 // CHECK1-NEXT:    [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
1273 // CHECK1-NEXT:    [[ADD27:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]
1274 // CHECK1-NEXT:    store i32 [[ADD27]], i32* [[DOTOMP_LB]], align 4
1275 // CHECK1-NEXT:    [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1276 // CHECK1-NEXT:    [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
1277 // CHECK1-NEXT:    [[ADD28:%.*]] = add nsw i32 [[TMP30]], [[TMP31]]
1278 // CHECK1-NEXT:    store i32 [[ADD28]], i32* [[DOTOMP_UB]], align 4
1279 // CHECK1-NEXT:    br label [[OMP_DISPATCH_COND]]
1280 // CHECK1:       omp.dispatch.end:
1281 // CHECK1-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]])
1282 // CHECK1-NEXT:    ret void
1283 //
1284 //
1285 // CHECK1-LABEL: define {{[^@]+}}@_Z3bari
1286 // CHECK1-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
1287 // CHECK1-NEXT:  entry:
1288 // CHECK1-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
1289 // CHECK1-NEXT:    [[A:%.*]] = alloca i32, align 4
1290 // CHECK1-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8
1291 // CHECK1-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
1292 // CHECK1-NEXT:    store i32 0, i32* [[A]], align 4
1293 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
1294 // CHECK1-NEXT:    [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]])
1295 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
1296 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
1297 // CHECK1-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
1298 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
1299 // CHECK1-NEXT:    [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]])
1300 // CHECK1-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
1301 // CHECK1-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
1302 // CHECK1-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
1303 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
1304 // CHECK1-NEXT:    [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]])
1305 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
1306 // CHECK1-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
1307 // CHECK1-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
1308 // CHECK1-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
1309 // CHECK1-NEXT:    [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]])
1310 // CHECK1-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
1311 // CHECK1-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
1312 // CHECK1-NEXT:    store i32 [[ADD6]], i32* [[A]], align 4
1313 // CHECK1-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
1314 // CHECK1-NEXT:    ret i32 [[TMP8]]
1315 //
1316 //
1317 // CHECK1-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
1318 // CHECK1-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 {
1319 // CHECK1-NEXT:  entry:
1320 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
1321 // CHECK1-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
1322 // CHECK1-NEXT:    [[B:%.*]] = alloca i32, align 4
1323 // CHECK1-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 8
1324 // CHECK1-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
1325 // CHECK1-NEXT:    [[B_CASTED:%.*]] = alloca i64, align 8
1326 // CHECK1-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8
1327 // CHECK1-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8
1328 // CHECK1-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8
1329 // CHECK1-NEXT:    [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 8
1330 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
1331 // CHECK1-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
1332 // CHECK1-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
1333 // CHECK1-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
1334 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
1335 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
1336 // CHECK1-NEXT:    store i32 [[ADD]], i32* [[B]], align 4
1337 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
1338 // CHECK1-NEXT:    [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
1339 // CHECK1-NEXT:    [[TMP3:%.*]] = call i8* @llvm.stacksave()
1340 // CHECK1-NEXT:    store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8
1341 // CHECK1-NEXT:    [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]
1342 // CHECK1-NEXT:    [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2
1343 // CHECK1-NEXT:    store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8
1344 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, i32* [[B]], align 4
1345 // CHECK1-NEXT:    [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32*
1346 // CHECK1-NEXT:    store i32 [[TMP5]], i32* [[CONV]], align 4
1347 // CHECK1-NEXT:    [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8
1348 // CHECK1-NEXT:    [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4
1349 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 60
1350 // CHECK1-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
1351 // CHECK1:       omp_if.then:
1352 // CHECK1-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
1353 // CHECK1-NEXT:    [[TMP8:%.*]] = mul nuw i64 2, [[TMP2]]
1354 // CHECK1-NEXT:    [[TMP9:%.*]] = mul nuw i64 [[TMP8]], 2
1355 // CHECK1-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1356 // CHECK1-NEXT:    [[TMP11:%.*]] = bitcast i8** [[TMP10]] to %struct.S1**
1357 // CHECK1-NEXT:    store %struct.S1* [[THIS1]], %struct.S1** [[TMP11]], align 8
1358 // CHECK1-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1359 // CHECK1-NEXT:    [[TMP13:%.*]] = bitcast i8** [[TMP12]] to double**
1360 // CHECK1-NEXT:    store double* [[A]], double** [[TMP13]], align 8
1361 // CHECK1-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
1362 // CHECK1-NEXT:    store i64 8, i64* [[TMP14]], align 8
1363 // CHECK1-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
1364 // CHECK1-NEXT:    store i8* null, i8** [[TMP15]], align 8
1365 // CHECK1-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
1366 // CHECK1-NEXT:    [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64*
1367 // CHECK1-NEXT:    store i64 [[TMP6]], i64* [[TMP17]], align 8
1368 // CHECK1-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
1369 // CHECK1-NEXT:    [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64*
1370 // CHECK1-NEXT:    store i64 [[TMP6]], i64* [[TMP19]], align 8
1371 // CHECK1-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1
1372 // CHECK1-NEXT:    store i64 4, i64* [[TMP20]], align 8
1373 // CHECK1-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
1374 // CHECK1-NEXT:    store i8* null, i8** [[TMP21]], align 8
1375 // CHECK1-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
1376 // CHECK1-NEXT:    [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i64*
1377 // CHECK1-NEXT:    store i64 2, i64* [[TMP23]], align 8
1378 // CHECK1-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
1379 // CHECK1-NEXT:    [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i64*
1380 // CHECK1-NEXT:    store i64 2, i64* [[TMP25]], align 8
1381 // CHECK1-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2
1382 // CHECK1-NEXT:    store i64 8, i64* [[TMP26]], align 8
1383 // CHECK1-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
1384 // CHECK1-NEXT:    store i8* null, i8** [[TMP27]], align 8
1385 // CHECK1-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
1386 // CHECK1-NEXT:    [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i64*
1387 // CHECK1-NEXT:    store i64 [[TMP2]], i64* [[TMP29]], align 8
1388 // CHECK1-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
1389 // CHECK1-NEXT:    [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i64*
1390 // CHECK1-NEXT:    store i64 [[TMP2]], i64* [[TMP31]], align 8
1391 // CHECK1-NEXT:    [[TMP32:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3
1392 // CHECK1-NEXT:    store i64 8, i64* [[TMP32]], align 8
1393 // CHECK1-NEXT:    [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
1394 // CHECK1-NEXT:    store i8* null, i8** [[TMP33]], align 8
1395 // CHECK1-NEXT:    [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
1396 // CHECK1-NEXT:    [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i16**
1397 // CHECK1-NEXT:    store i16* [[VLA]], i16** [[TMP35]], align 8
1398 // CHECK1-NEXT:    [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
1399 // CHECK1-NEXT:    [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i16**
1400 // CHECK1-NEXT:    store i16* [[VLA]], i16** [[TMP37]], align 8
1401 // CHECK1-NEXT:    [[TMP38:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4
1402 // CHECK1-NEXT:    store i64 [[TMP9]], i64* [[TMP38]], align 8
1403 // CHECK1-NEXT:    [[TMP39:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4
1404 // CHECK1-NEXT:    store i8* null, i8** [[TMP39]], align 8
1405 // CHECK1-NEXT:    [[TMP40:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1406 // CHECK1-NEXT:    [[TMP41:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1407 // CHECK1-NEXT:    [[TMP42:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
1408 // CHECK1-NEXT:    call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10)
1409 // CHECK1-NEXT:    [[TMP43:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218.region_id, i32 5, i8** [[TMP40]], i8** [[TMP41]], i64* [[TMP42]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.12, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
1410 // CHECK1-NEXT:    [[TMP44:%.*]] = icmp ne i32 [[TMP43]], 0
1411 // CHECK1-NEXT:    br i1 [[TMP44]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
1412 // CHECK1:       omp_offload.failed:
1413 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR3]]
1414 // CHECK1-NEXT:    br label [[OMP_OFFLOAD_CONT]]
1415 // CHECK1:       omp_offload.cont:
1416 // CHECK1-NEXT:    br label [[OMP_IF_END:%.*]]
1417 // CHECK1:       omp_if.else:
1418 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR3]]
1419 // CHECK1-NEXT:    br label [[OMP_IF_END]]
1420 // CHECK1:       omp_if.end:
1421 // CHECK1-NEXT:    [[TMP45:%.*]] = mul nsw i64 1, [[TMP2]]
1422 // CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP45]]
1423 // CHECK1-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
1424 // CHECK1-NEXT:    [[TMP46:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2
1425 // CHECK1-NEXT:    [[CONV3:%.*]] = sext i16 [[TMP46]] to i32
1426 // CHECK1-NEXT:    [[TMP47:%.*]] = load i32, i32* [[B]], align 4
1427 // CHECK1-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], [[TMP47]]
1428 // CHECK1-NEXT:    [[TMP48:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
1429 // CHECK1-NEXT:    call void @llvm.stackrestore(i8* [[TMP48]])
1430 // CHECK1-NEXT:    ret i32 [[ADD4]]
1431 //
1432 //
1433 // CHECK1-LABEL: define {{[^@]+}}@_ZL7fstatici
1434 // CHECK1-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
1435 // CHECK1-NEXT:  entry:
1436 // CHECK1-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
1437 // CHECK1-NEXT:    [[A:%.*]] = alloca i32, align 4
1438 // CHECK1-NEXT:    [[AA:%.*]] = alloca i16, align 2
1439 // CHECK1-NEXT:    [[AAA:%.*]] = alloca i8, align 1
1440 // CHECK1-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
1441 // CHECK1-NEXT:    [[N_CASTED:%.*]] = alloca i64, align 8
1442 // CHECK1-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
1443 // CHECK1-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
1444 // CHECK1-NEXT:    [[AAA_CASTED:%.*]] = alloca i64, align 8
1445 // CHECK1-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8
1446 // CHECK1-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8
1447 // CHECK1-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8
1448 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
1449 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
1450 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4
1451 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR_5:%.*]] = alloca i32, align 4
1452 // CHECK1-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
1453 // CHECK1-NEXT:    store i32 0, i32* [[A]], align 4
1454 // CHECK1-NEXT:    store i16 0, i16* [[AA]], align 2
1455 // CHECK1-NEXT:    store i8 0, i8* [[AAA]], align 1
1456 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
1457 // CHECK1-NEXT:    [[CONV:%.*]] = bitcast i64* [[N_CASTED]] to i32*
1458 // CHECK1-NEXT:    store i32 [[TMP0]], i32* [[CONV]], align 4
1459 // CHECK1-NEXT:    [[TMP1:%.*]] = load i64, i64* [[N_CASTED]], align 8
1460 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32, i32* [[A]], align 4
1461 // CHECK1-NEXT:    [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32*
1462 // CHECK1-NEXT:    store i32 [[TMP2]], i32* [[CONV1]], align 4
1463 // CHECK1-NEXT:    [[TMP3:%.*]] = load i64, i64* [[A_CASTED]], align 8
1464 // CHECK1-NEXT:    [[TMP4:%.*]] = load i16, i16* [[AA]], align 2
1465 // CHECK1-NEXT:    [[CONV2:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
1466 // CHECK1-NEXT:    store i16 [[TMP4]], i16* [[CONV2]], align 2
1467 // CHECK1-NEXT:    [[TMP5:%.*]] = load i64, i64* [[AA_CASTED]], align 8
1468 // CHECK1-NEXT:    [[TMP6:%.*]] = load i8, i8* [[AAA]], align 1
1469 // CHECK1-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
1470 // CHECK1-NEXT:    store i8 [[TMP6]], i8* [[CONV3]], align 1
1471 // CHECK1-NEXT:    [[TMP7:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
1472 // CHECK1-NEXT:    [[TMP8:%.*]] = load i32, i32* [[N_ADDR]], align 4
1473 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP8]], 50
1474 // CHECK1-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
1475 // CHECK1:       omp_if.then:
1476 // CHECK1-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1477 // CHECK1-NEXT:    [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64*
1478 // CHECK1-NEXT:    store i64 [[TMP1]], i64* [[TMP10]], align 8
1479 // CHECK1-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1480 // CHECK1-NEXT:    [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64*
1481 // CHECK1-NEXT:    store i64 [[TMP1]], i64* [[TMP12]], align 8
1482 // CHECK1-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
1483 // CHECK1-NEXT:    store i8* null, i8** [[TMP13]], align 8
1484 // CHECK1-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
1485 // CHECK1-NEXT:    [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64*
1486 // CHECK1-NEXT:    store i64 [[TMP3]], i64* [[TMP15]], align 8
1487 // CHECK1-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
1488 // CHECK1-NEXT:    [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64*
1489 // CHECK1-NEXT:    store i64 [[TMP3]], i64* [[TMP17]], align 8
1490 // CHECK1-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
1491 // CHECK1-NEXT:    store i8* null, i8** [[TMP18]], align 8
1492 // CHECK1-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
1493 // CHECK1-NEXT:    [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64*
1494 // CHECK1-NEXT:    store i64 [[TMP5]], i64* [[TMP20]], align 8
1495 // CHECK1-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
1496 // CHECK1-NEXT:    [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i64*
1497 // CHECK1-NEXT:    store i64 [[TMP5]], i64* [[TMP22]], align 8
1498 // CHECK1-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
1499 // CHECK1-NEXT:    store i8* null, i8** [[TMP23]], align 8
1500 // CHECK1-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
1501 // CHECK1-NEXT:    [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i64*
1502 // CHECK1-NEXT:    store i64 [[TMP7]], i64* [[TMP25]], align 8
1503 // CHECK1-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
1504 // CHECK1-NEXT:    [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64*
1505 // CHECK1-NEXT:    store i64 [[TMP7]], i64* [[TMP27]], align 8
1506 // CHECK1-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
1507 // CHECK1-NEXT:    store i8* null, i8** [[TMP28]], align 8
1508 // CHECK1-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
1509 // CHECK1-NEXT:    [[TMP30:%.*]] = bitcast i8** [[TMP29]] to [10 x i32]**
1510 // CHECK1-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP30]], align 8
1511 // CHECK1-NEXT:    [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
1512 // CHECK1-NEXT:    [[TMP32:%.*]] = bitcast i8** [[TMP31]] to [10 x i32]**
1513 // CHECK1-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP32]], align 8
1514 // CHECK1-NEXT:    [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4
1515 // CHECK1-NEXT:    store i8* null, i8** [[TMP33]], align 8
1516 // CHECK1-NEXT:    [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1517 // CHECK1-NEXT:    [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1518 // CHECK1-NEXT:    [[TMP36:%.*]] = load i32, i32* [[A]], align 4
1519 // CHECK1-NEXT:    store i32 [[TMP36]], i32* [[DOTCAPTURE_EXPR_]], align 4
1520 // CHECK1-NEXT:    [[TMP37:%.*]] = load i32, i32* [[N_ADDR]], align 4
1521 // CHECK1-NEXT:    store i32 [[TMP37]], i32* [[DOTCAPTURE_EXPR_4]], align 4
1522 // CHECK1-NEXT:    [[TMP38:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4
1523 // CHECK1-NEXT:    [[TMP39:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
1524 // CHECK1-NEXT:    [[SUB:%.*]] = sub i32 [[TMP38]], [[TMP39]]
1525 // CHECK1-NEXT:    [[SUB6:%.*]] = sub i32 [[SUB]], 1
1526 // CHECK1-NEXT:    [[ADD:%.*]] = add i32 [[SUB6]], 1
1527 // CHECK1-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], 1
1528 // CHECK1-NEXT:    [[SUB7:%.*]] = sub i32 [[DIV]], 1
1529 // CHECK1-NEXT:    store i32 [[SUB7]], i32* [[DOTCAPTURE_EXPR_5]], align 4
1530 // CHECK1-NEXT:    [[TMP40:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4
1531 // CHECK1-NEXT:    [[ADD8:%.*]] = add i32 [[TMP40]], 1
1532 // CHECK1-NEXT:    [[TMP41:%.*]] = zext i32 [[ADD8]] to i64
1533 // CHECK1-NEXT:    call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 [[TMP41]])
1534 // CHECK1-NEXT:    [[TMP42:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200.region_id, i32 5, i8** [[TMP34]], i8** [[TMP35]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes.14, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.15, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
1535 // CHECK1-NEXT:    [[TMP43:%.*]] = icmp ne i32 [[TMP42]], 0
1536 // CHECK1-NEXT:    br i1 [[TMP43]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
1537 // CHECK1:       omp_offload.failed:
1538 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], i64 [[TMP7]], [10 x i32]* [[B]]) #[[ATTR3]]
1539 // CHECK1-NEXT:    br label [[OMP_OFFLOAD_CONT]]
1540 // CHECK1:       omp_offload.cont:
1541 // CHECK1-NEXT:    br label [[OMP_IF_END:%.*]]
1542 // CHECK1:       omp_if.else:
1543 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], i64 [[TMP7]], [10 x i32]* [[B]]) #[[ATTR3]]
1544 // CHECK1-NEXT:    br label [[OMP_IF_END]]
1545 // CHECK1:       omp_if.end:
1546 // CHECK1-NEXT:    [[TMP44:%.*]] = load i32, i32* [[A]], align 4
1547 // CHECK1-NEXT:    ret i32 [[TMP44]]
1548 //
1549 //
1550 // CHECK1-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
1551 // CHECK1-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat {
1552 // CHECK1-NEXT:  entry:
1553 // CHECK1-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
1554 // CHECK1-NEXT:    [[A:%.*]] = alloca i32, align 4
1555 // CHECK1-NEXT:    [[AA:%.*]] = alloca i16, align 2
1556 // CHECK1-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
1557 // CHECK1-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
1558 // CHECK1-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
1559 // CHECK1-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8
1560 // CHECK1-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8
1561 // CHECK1-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8
1562 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
1563 // CHECK1-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
1564 // CHECK1-NEXT:    store i32 0, i32* [[A]], align 4
1565 // CHECK1-NEXT:    store i16 0, i16* [[AA]], align 2
1566 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
1567 // CHECK1-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32*
1568 // CHECK1-NEXT:    store i32 [[TMP0]], i32* [[CONV]], align 4
1569 // CHECK1-NEXT:    [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
1570 // CHECK1-NEXT:    [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
1571 // CHECK1-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
1572 // CHECK1-NEXT:    store i16 [[TMP2]], i16* [[CONV1]], align 2
1573 // CHECK1-NEXT:    [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
1574 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
1575 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40
1576 // CHECK1-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
1577 // CHECK1:       omp_if.then:
1578 // CHECK1-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1579 // CHECK1-NEXT:    [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64*
1580 // CHECK1-NEXT:    store i64 [[TMP1]], i64* [[TMP6]], align 8
1581 // CHECK1-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1582 // CHECK1-NEXT:    [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64*
1583 // CHECK1-NEXT:    store i64 [[TMP1]], i64* [[TMP8]], align 8
1584 // CHECK1-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
1585 // CHECK1-NEXT:    store i8* null, i8** [[TMP9]], align 8
1586 // CHECK1-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
1587 // CHECK1-NEXT:    [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i64*
1588 // CHECK1-NEXT:    store i64 [[TMP3]], i64* [[TMP11]], align 8
1589 // CHECK1-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
1590 // CHECK1-NEXT:    [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64*
1591 // CHECK1-NEXT:    store i64 [[TMP3]], i64* [[TMP13]], align 8
1592 // CHECK1-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
1593 // CHECK1-NEXT:    store i8* null, i8** [[TMP14]], align 8
1594 // CHECK1-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
1595 // CHECK1-NEXT:    [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]**
1596 // CHECK1-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 8
1597 // CHECK1-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
1598 // CHECK1-NEXT:    [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]**
1599 // CHECK1-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 8
1600 // CHECK1-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
1601 // CHECK1-NEXT:    store i8* null, i8** [[TMP19]], align 8
1602 // CHECK1-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1603 // CHECK1-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1604 // CHECK1-NEXT:    call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10)
1605 // CHECK1-NEXT:    [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.17, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.18, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
1606 // CHECK1-NEXT:    [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0
1607 // CHECK1-NEXT:    br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
1608 // CHECK1:       omp_offload.failed:
1609 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]]
1610 // CHECK1-NEXT:    br label [[OMP_OFFLOAD_CONT]]
1611 // CHECK1:       omp_offload.cont:
1612 // CHECK1-NEXT:    br label [[OMP_IF_END:%.*]]
1613 // CHECK1:       omp_if.else:
1614 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]]
1615 // CHECK1-NEXT:    br label [[OMP_IF_END]]
1616 // CHECK1:       omp_if.end:
1617 // CHECK1-NEXT:    [[TMP24:%.*]] = load i32, i32* [[A]], align 4
1618 // CHECK1-NEXT:    ret i32 [[TMP24]]
1619 //
1620 //
1621 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218
1622 // CHECK1-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {
1623 // CHECK1-NEXT:  entry:
1624 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
1625 // CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
1626 // CHECK1-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
1627 // CHECK1-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
1628 // CHECK1-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 8
1629 // CHECK1-NEXT:    [[B_CASTED:%.*]] = alloca i64, align 8
1630 // CHECK1-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
1631 // CHECK1-NEXT:    store i64 [[B]], i64* [[B_ADDR]], align 8
1632 // CHECK1-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
1633 // CHECK1-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
1634 // CHECK1-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 8
1635 // CHECK1-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
1636 // CHECK1-NEXT:    [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
1637 // CHECK1-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
1638 // CHECK1-NEXT:    [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
1639 // CHECK1-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
1640 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
1641 // CHECK1-NEXT:    [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32*
1642 // CHECK1-NEXT:    store i32 [[TMP4]], i32* [[CONV3]], align 4
1643 // CHECK1-NEXT:    [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
1644 // CHECK1-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]])
1645 // CHECK1-NEXT:    ret void
1646 //
1647 //
1648 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..11
1649 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {
1650 // CHECK1-NEXT:  entry:
1651 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
1652 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
1653 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
1654 // CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
1655 // CHECK1-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
1656 // CHECK1-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
1657 // CHECK1-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 8
1658 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
1659 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
1660 // CHECK1-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
1661 // CHECK1-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
1662 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1663 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1664 // CHECK1-NEXT:    [[I:%.*]] = alloca i32, align 4
1665 // CHECK1-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
1666 // CHECK1-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
1667 // CHECK1-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
1668 // CHECK1-NEXT:    store i64 [[B]], i64* [[B_ADDR]], align 8
1669 // CHECK1-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
1670 // CHECK1-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
1671 // CHECK1-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 8
1672 // CHECK1-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
1673 // CHECK1-NEXT:    [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
1674 // CHECK1-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
1675 // CHECK1-NEXT:    [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
1676 // CHECK1-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
1677 // CHECK1-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
1678 // CHECK1-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
1679 // CHECK1-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
1680 // CHECK1-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
1681 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
1682 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
1683 // CHECK1-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
1684 // CHECK1-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1685 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 9
1686 // CHECK1-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1687 // CHECK1:       cond.true:
1688 // CHECK1-NEXT:    br label [[COND_END:%.*]]
1689 // CHECK1:       cond.false:
1690 // CHECK1-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1691 // CHECK1-NEXT:    br label [[COND_END]]
1692 // CHECK1:       cond.end:
1693 // CHECK1-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
1694 // CHECK1-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
1695 // CHECK1-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
1696 // CHECK1-NEXT:    store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
1697 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
1698 // CHECK1:       omp.inner.for.cond:
1699 // CHECK1-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1700 // CHECK1-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1701 // CHECK1-NEXT:    [[CMP3:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
1702 // CHECK1-NEXT:    br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1703 // CHECK1:       omp.inner.for.body:
1704 // CHECK1-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1705 // CHECK1-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
1706 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1707 // CHECK1-NEXT:    store i32 [[ADD]], i32* [[I]], align 4
1708 // CHECK1-NEXT:    [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8
1709 // CHECK1-NEXT:    [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double
1710 // CHECK1-NEXT:    [[ADD5:%.*]] = fadd double [[CONV4]], 1.500000e+00
1711 // CHECK1-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
1712 // CHECK1-NEXT:    store double [[ADD5]], double* [[A]], align 8
1713 // CHECK1-NEXT:    [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
1714 // CHECK1-NEXT:    [[TMP13:%.*]] = load double, double* [[A6]], align 8
1715 // CHECK1-NEXT:    [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00
1716 // CHECK1-NEXT:    store double [[INC]], double* [[A6]], align 8
1717 // CHECK1-NEXT:    [[CONV7:%.*]] = fptosi double [[INC]] to i16
1718 // CHECK1-NEXT:    [[TMP14:%.*]] = mul nsw i64 1, [[TMP2]]
1719 // CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP14]]
1720 // CHECK1-NEXT:    [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
1721 // CHECK1-NEXT:    store i16 [[CONV7]], i16* [[ARRAYIDX8]], align 2
1722 // CHECK1-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
1723 // CHECK1:       omp.body.continue:
1724 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
1725 // CHECK1:       omp.inner.for.inc:
1726 // CHECK1-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1727 // CHECK1-NEXT:    [[ADD9:%.*]] = add nsw i32 [[TMP15]], 1
1728 // CHECK1-NEXT:    store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4
1729 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]]
1730 // CHECK1:       omp.inner.for.end:
1731 // CHECK1-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
1732 // CHECK1:       omp.loop.exit:
1733 // CHECK1-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
1734 // CHECK1-NEXT:    ret void
1735 //
1736 //
1737 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200
1738 // CHECK1-SAME: (i64 [[N:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
1739 // CHECK1-NEXT:  entry:
1740 // CHECK1-NEXT:    [[N_ADDR:%.*]] = alloca i64, align 8
1741 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
1742 // CHECK1-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
1743 // CHECK1-NEXT:    [[AAA_ADDR:%.*]] = alloca i64, align 8
1744 // CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
1745 // CHECK1-NEXT:    [[N_CASTED:%.*]] = alloca i64, align 8
1746 // CHECK1-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
1747 // CHECK1-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
1748 // CHECK1-NEXT:    [[AAA_CASTED:%.*]] = alloca i64, align 8
1749 // CHECK1-NEXT:    store i64 [[N]], i64* [[N_ADDR]], align 8
1750 // CHECK1-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
1751 // CHECK1-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
1752 // CHECK1-NEXT:    store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
1753 // CHECK1-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
1754 // CHECK1-NEXT:    [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
1755 // CHECK1-NEXT:    [[CONV1:%.*]] = bitcast i64* [[A_ADDR]] to i32*
1756 // CHECK1-NEXT:    [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
1757 // CHECK1-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
1758 // CHECK1-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
1759 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
1760 // CHECK1-NEXT:    [[CONV4:%.*]] = bitcast i64* [[N_CASTED]] to i32*
1761 // CHECK1-NEXT:    store i32 [[TMP1]], i32* [[CONV4]], align 4
1762 // CHECK1-NEXT:    [[TMP2:%.*]] = load i64, i64* [[N_CASTED]], align 8
1763 // CHECK1-NEXT:    [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 8
1764 // CHECK1-NEXT:    [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
1765 // CHECK1-NEXT:    store i32 [[TMP3]], i32* [[CONV5]], align 4
1766 // CHECK1-NEXT:    [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8
1767 // CHECK1-NEXT:    [[TMP5:%.*]] = load i16, i16* [[CONV2]], align 8
1768 // CHECK1-NEXT:    [[CONV6:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
1769 // CHECK1-NEXT:    store i16 [[TMP5]], i16* [[CONV6]], align 2
1770 // CHECK1-NEXT:    [[TMP6:%.*]] = load i64, i64* [[AA_CASTED]], align 8
1771 // CHECK1-NEXT:    [[TMP7:%.*]] = load i8, i8* [[CONV3]], align 8
1772 // CHECK1-NEXT:    [[CONV7:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
1773 // CHECK1-NEXT:    store i8 [[TMP7]], i8* [[CONV7]], align 1
1774 // CHECK1-NEXT:    [[TMP8:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
1775 // CHECK1-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, [10 x i32]*)* @.omp_outlined..13 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]], [10 x i32]* [[TMP0]])
1776 // CHECK1-NEXT:    ret void
1777 //
1778 //
1779 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..13
1780 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
1781 // CHECK1-NEXT:  entry:
1782 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
1783 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
1784 // CHECK1-NEXT:    [[N_ADDR:%.*]] = alloca i64, align 8
1785 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
1786 // CHECK1-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
1787 // CHECK1-NEXT:    [[AAA_ADDR:%.*]] = alloca i64, align 8
1788 // CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
1789 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
1790 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
1791 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
1792 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4
1793 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR_5:%.*]] = alloca i32, align 4
1794 // CHECK1-NEXT:    [[I:%.*]] = alloca i32, align 4
1795 // CHECK1-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
1796 // CHECK1-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
1797 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1798 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1799 // CHECK1-NEXT:    [[I8:%.*]] = alloca i32, align 4
1800 // CHECK1-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
1801 // CHECK1-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
1802 // CHECK1-NEXT:    store i64 [[N]], i64* [[N_ADDR]], align 8
1803 // CHECK1-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
1804 // CHECK1-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
1805 // CHECK1-NEXT:    store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
1806 // CHECK1-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
1807 // CHECK1-NEXT:    [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
1808 // CHECK1-NEXT:    [[CONV1:%.*]] = bitcast i64* [[A_ADDR]] to i32*
1809 // CHECK1-NEXT:    [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
1810 // CHECK1-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
1811 // CHECK1-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
1812 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV1]], align 8
1813 // CHECK1-NEXT:    store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
1814 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
1815 // CHECK1-NEXT:    store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_4]], align 4
1816 // CHECK1-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4
1817 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
1818 // CHECK1-NEXT:    [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]]
1819 // CHECK1-NEXT:    [[SUB6:%.*]] = sub i32 [[SUB]], 1
1820 // CHECK1-NEXT:    [[ADD:%.*]] = add i32 [[SUB6]], 1
1821 // CHECK1-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], 1
1822 // CHECK1-NEXT:    [[SUB7:%.*]] = sub i32 [[DIV]], 1
1823 // CHECK1-NEXT:    store i32 [[SUB7]], i32* [[DOTCAPTURE_EXPR_5]], align 4
1824 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
1825 // CHECK1-NEXT:    store i32 [[TMP5]], i32* [[I]], align 4
1826 // CHECK1-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
1827 // CHECK1-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4
1828 // CHECK1-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]]
1829 // CHECK1-NEXT:    br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
1830 // CHECK1:       omp.precond.then:
1831 // CHECK1-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
1832 // CHECK1-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4
1833 // CHECK1-NEXT:    store i32 [[TMP8]], i32* [[DOTOMP_UB]], align 4
1834 // CHECK1-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
1835 // CHECK1-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
1836 // CHECK1-NEXT:    [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
1837 // CHECK1-NEXT:    [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
1838 // CHECK1-NEXT:    call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
1839 // CHECK1-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1840 // CHECK1-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4
1841 // CHECK1-NEXT:    [[CMP9:%.*]] = icmp ugt i32 [[TMP11]], [[TMP12]]
1842 // CHECK1-NEXT:    br i1 [[CMP9]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1843 // CHECK1:       cond.true:
1844 // CHECK1-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4
1845 // CHECK1-NEXT:    br label [[COND_END:%.*]]
1846 // CHECK1:       cond.false:
1847 // CHECK1-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1848 // CHECK1-NEXT:    br label [[COND_END]]
1849 // CHECK1:       cond.end:
1850 // CHECK1-NEXT:    [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ]
1851 // CHECK1-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
1852 // CHECK1-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
1853 // CHECK1-NEXT:    store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4
1854 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
1855 // CHECK1:       omp.inner.for.cond:
1856 // CHECK1-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1857 // CHECK1-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1858 // CHECK1-NEXT:    [[ADD10:%.*]] = add i32 [[TMP17]], 1
1859 // CHECK1-NEXT:    [[CMP11:%.*]] = icmp ult i32 [[TMP16]], [[ADD10]]
1860 // CHECK1-NEXT:    br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1861 // CHECK1:       omp.inner.for.body:
1862 // CHECK1-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
1863 // CHECK1-NEXT:    [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1864 // CHECK1-NEXT:    [[MUL:%.*]] = mul i32 [[TMP19]], 1
1865 // CHECK1-NEXT:    [[ADD12:%.*]] = add i32 [[TMP18]], [[MUL]]
1866 // CHECK1-NEXT:    store i32 [[ADD12]], i32* [[I8]], align 4
1867 // CHECK1-NEXT:    [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 8
1868 // CHECK1-NEXT:    [[ADD13:%.*]] = add nsw i32 [[TMP20]], 1
1869 // CHECK1-NEXT:    store i32 [[ADD13]], i32* [[CONV1]], align 8
1870 // CHECK1-NEXT:    [[TMP21:%.*]] = load i16, i16* [[CONV2]], align 8
1871 // CHECK1-NEXT:    [[CONV14:%.*]] = sext i16 [[TMP21]] to i32
1872 // CHECK1-NEXT:    [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1
1873 // CHECK1-NEXT:    [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16
1874 // CHECK1-NEXT:    store i16 [[CONV16]], i16* [[CONV2]], align 8
1875 // CHECK1-NEXT:    [[TMP22:%.*]] = load i8, i8* [[CONV3]], align 8
1876 // CHECK1-NEXT:    [[CONV17:%.*]] = sext i8 [[TMP22]] to i32
1877 // CHECK1-NEXT:    [[ADD18:%.*]] = add nsw i32 [[CONV17]], 1
1878 // CHECK1-NEXT:    [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8
1879 // CHECK1-NEXT:    store i8 [[CONV19]], i8* [[CONV3]], align 8
1880 // CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
1881 // CHECK1-NEXT:    [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
1882 // CHECK1-NEXT:    [[ADD20:%.*]] = add nsw i32 [[TMP23]], 1
1883 // CHECK1-NEXT:    store i32 [[ADD20]], i32* [[ARRAYIDX]], align 4
1884 // CHECK1-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
1885 // CHECK1:       omp.body.continue:
1886 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
1887 // CHECK1:       omp.inner.for.inc:
1888 // CHECK1-NEXT:    [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1889 // CHECK1-NEXT:    [[ADD21:%.*]] = add i32 [[TMP24]], 1
1890 // CHECK1-NEXT:    store i32 [[ADD21]], i32* [[DOTOMP_IV]], align 4
1891 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]]
1892 // CHECK1:       omp.inner.for.end:
1893 // CHECK1-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
1894 // CHECK1:       omp.loop.exit:
1895 // CHECK1-NEXT:    [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
1896 // CHECK1-NEXT:    [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4
1897 // CHECK1-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]])
1898 // CHECK1-NEXT:    br label [[OMP_PRECOND_END]]
1899 // CHECK1:       omp.precond.end:
1900 // CHECK1-NEXT:    ret void
1901 //
1902 //
1903 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183
1904 // CHECK1-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
1905 // CHECK1-NEXT:  entry:
1906 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
1907 // CHECK1-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
1908 // CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
1909 // CHECK1-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
1910 // CHECK1-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
1911 // CHECK1-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
1912 // CHECK1-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
1913 // CHECK1-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
1914 // CHECK1-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
1915 // CHECK1-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
1916 // CHECK1-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
1917 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
1918 // CHECK1-NEXT:    [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
1919 // CHECK1-NEXT:    store i32 [[TMP1]], i32* [[CONV2]], align 4
1920 // CHECK1-NEXT:    [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
1921 // CHECK1-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
1922 // CHECK1-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
1923 // CHECK1-NEXT:    store i16 [[TMP3]], i16* [[CONV3]], align 2
1924 // CHECK1-NEXT:    [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
1925 // CHECK1-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]])
1926 // CHECK1-NEXT:    ret void
1927 //
1928 //
1929 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..16
1930 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
1931 // CHECK1-NEXT:  entry:
1932 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
1933 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
1934 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
1935 // CHECK1-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
1936 // CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
1937 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
1938 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
1939 // CHECK1-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
1940 // CHECK1-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
1941 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1942 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1943 // CHECK1-NEXT:    [[I:%.*]] = alloca i32, align 4
1944 // CHECK1-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
1945 // CHECK1-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
1946 // CHECK1-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
1947 // CHECK1-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
1948 // CHECK1-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
1949 // CHECK1-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
1950 // CHECK1-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
1951 // CHECK1-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
1952 // CHECK1-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
1953 // CHECK1-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
1954 // CHECK1-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
1955 // CHECK1-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
1956 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
1957 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
1958 // CHECK1-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
1959 // CHECK1-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1960 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9
1961 // CHECK1-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1962 // CHECK1:       cond.true:
1963 // CHECK1-NEXT:    br label [[COND_END:%.*]]
1964 // CHECK1:       cond.false:
1965 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1966 // CHECK1-NEXT:    br label [[COND_END]]
1967 // CHECK1:       cond.end:
1968 // CHECK1-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
1969 // CHECK1-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
1970 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
1971 // CHECK1-NEXT:    store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
1972 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
1973 // CHECK1:       omp.inner.for.cond:
1974 // CHECK1-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1975 // CHECK1-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1976 // CHECK1-NEXT:    [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
1977 // CHECK1-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1978 // CHECK1:       omp.inner.for.body:
1979 // CHECK1-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1980 // CHECK1-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
1981 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1982 // CHECK1-NEXT:    store i32 [[ADD]], i32* [[I]], align 4
1983 // CHECK1-NEXT:    [[TMP9:%.*]] = load i32, i32* [[CONV]], align 8
1984 // CHECK1-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1
1985 // CHECK1-NEXT:    store i32 [[ADD3]], i32* [[CONV]], align 8
1986 // CHECK1-NEXT:    [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 8
1987 // CHECK1-NEXT:    [[CONV4:%.*]] = sext i16 [[TMP10]] to i32
1988 // CHECK1-NEXT:    [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
1989 // CHECK1-NEXT:    [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
1990 // CHECK1-NEXT:    store i16 [[CONV6]], i16* [[CONV1]], align 8
1991 // CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
1992 // CHECK1-NEXT:    [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
1993 // CHECK1-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1
1994 // CHECK1-NEXT:    store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4
1995 // CHECK1-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
1996 // CHECK1:       omp.body.continue:
1997 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
1998 // CHECK1:       omp.inner.for.inc:
1999 // CHECK1-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2000 // CHECK1-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP12]], 1
2001 // CHECK1-NEXT:    store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4
2002 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]]
2003 // CHECK1:       omp.inner.for.end:
2004 // CHECK1-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
2005 // CHECK1:       omp.loop.exit:
2006 // CHECK1-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
2007 // CHECK1-NEXT:    ret void
2008 //
2009 //
2010 // CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
2011 // CHECK1-SAME: () #[[ATTR4]] {
2012 // CHECK1-NEXT:  entry:
2013 // CHECK1-NEXT:    call void @__tgt_register_requires(i64 1)
2014 // CHECK1-NEXT:    ret void
2015 //
2016 //
2017 // CHECK2-LABEL: define {{[^@]+}}@_Z3fooi
2018 // CHECK2-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] {
2019 // CHECK2-NEXT:  entry:
2020 // CHECK2-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
2021 // CHECK2-NEXT:    [[A:%.*]] = alloca i32, align 4
2022 // CHECK2-NEXT:    [[AA:%.*]] = alloca i16, align 2
2023 // CHECK2-NEXT:    [[B:%.*]] = alloca [10 x float], align 4
2024 // CHECK2-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 8
2025 // CHECK2-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
2026 // CHECK2-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 8
2027 // CHECK2-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i64, align 8
2028 // CHECK2-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8
2029 // CHECK2-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
2030 // CHECK2-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
2031 // CHECK2-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
2032 // CHECK2-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
2033 // CHECK2-NEXT:    [[DOTCAPTURE_EXPR__CASTED4:%.*]] = alloca i64, align 8
2034 // CHECK2-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8
2035 // CHECK2-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8
2036 // CHECK2-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8
2037 // CHECK2-NEXT:    [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4
2038 // CHECK2-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
2039 // CHECK2-NEXT:    [[AA_CASTED7:%.*]] = alloca i64, align 8
2040 // CHECK2-NEXT:    [[DOTOFFLOAD_BASEPTRS9:%.*]] = alloca [1 x i8*], align 8
2041 // CHECK2-NEXT:    [[DOTOFFLOAD_PTRS10:%.*]] = alloca [1 x i8*], align 8
2042 // CHECK2-NEXT:    [[DOTOFFLOAD_MAPPERS11:%.*]] = alloca [1 x i8*], align 8
2043 // CHECK2-NEXT:    [[TMP:%.*]] = alloca i32, align 4
2044 // CHECK2-NEXT:    [[A_CASTED12:%.*]] = alloca i64, align 8
2045 // CHECK2-NEXT:    [[AA_CASTED14:%.*]] = alloca i64, align 8
2046 // CHECK2-NEXT:    [[DOTOFFLOAD_BASEPTRS16:%.*]] = alloca [2 x i8*], align 8
2047 // CHECK2-NEXT:    [[DOTOFFLOAD_PTRS17:%.*]] = alloca [2 x i8*], align 8
2048 // CHECK2-NEXT:    [[DOTOFFLOAD_MAPPERS18:%.*]] = alloca [2 x i8*], align 8
2049 // CHECK2-NEXT:    [[_TMP19:%.*]] = alloca i32, align 4
2050 // CHECK2-NEXT:    [[DOTCAPTURE_EXPR_22:%.*]] = alloca i32, align 4
2051 // CHECK2-NEXT:    [[A_CASTED23:%.*]] = alloca i64, align 8
2052 // CHECK2-NEXT:    [[DOTCAPTURE_EXPR__CASTED25:%.*]] = alloca i64, align 8
2053 // CHECK2-NEXT:    [[DOTOFFLOAD_BASEPTRS29:%.*]] = alloca [10 x i8*], align 8
2054 // CHECK2-NEXT:    [[DOTOFFLOAD_PTRS30:%.*]] = alloca [10 x i8*], align 8
2055 // CHECK2-NEXT:    [[DOTOFFLOAD_MAPPERS31:%.*]] = alloca [10 x i8*], align 8
2056 // CHECK2-NEXT:    [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 8
2057 // CHECK2-NEXT:    [[_TMP32:%.*]] = alloca i32, align 4
2058 // CHECK2-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]])
2059 // CHECK2-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
2060 // CHECK2-NEXT:    store i32 0, i32* [[A]], align 4
2061 // CHECK2-NEXT:    store i16 0, i16* [[AA]], align 2
2062 // CHECK2-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
2063 // CHECK2-NEXT:    [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
2064 // CHECK2-NEXT:    [[TMP3:%.*]] = call i8* @llvm.stacksave()
2065 // CHECK2-NEXT:    store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8
2066 // CHECK2-NEXT:    [[VLA:%.*]] = alloca float, i64 [[TMP2]], align 4
2067 // CHECK2-NEXT:    store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8
2068 // CHECK2-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
2069 // CHECK2-NEXT:    [[TMP5:%.*]] = zext i32 [[TMP4]] to i64
2070 // CHECK2-NEXT:    [[TMP6:%.*]] = mul nuw i64 5, [[TMP5]]
2071 // CHECK2-NEXT:    [[VLA1:%.*]] = alloca double, i64 [[TMP6]], align 8
2072 // CHECK2-NEXT:    store i64 [[TMP5]], i64* [[__VLA_EXPR1]], align 8
2073 // CHECK2-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
2074 // CHECK2-NEXT:    store i32 [[TMP7]], i32* [[DOTCAPTURE_EXPR_]], align 4
2075 // CHECK2-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
2076 // CHECK2-NEXT:    store i32 [[TMP8]], i32* [[DOTCAPTURE_EXPR_2]], align 4
2077 // CHECK2-NEXT:    [[TMP9:%.*]] = load i16, i16* [[AA]], align 2
2078 // CHECK2-NEXT:    [[CONV:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
2079 // CHECK2-NEXT:    store i16 [[TMP9]], i16* [[CONV]], align 2
2080 // CHECK2-NEXT:    [[TMP10:%.*]] = load i64, i64* [[AA_CASTED]], align 8
2081 // CHECK2-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
2082 // CHECK2-NEXT:    [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
2083 // CHECK2-NEXT:    store i32 [[TMP11]], i32* [[CONV3]], align 4
2084 // CHECK2-NEXT:    [[TMP12:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
2085 // CHECK2-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
2086 // CHECK2-NEXT:    [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED4]] to i32*
2087 // CHECK2-NEXT:    store i32 [[TMP13]], i32* [[CONV5]], align 4
2088 // CHECK2-NEXT:    [[TMP14:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED4]], align 8
2089 // CHECK2-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
2090 // CHECK2-NEXT:    [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i64*
2091 // CHECK2-NEXT:    store i64 [[TMP10]], i64* [[TMP16]], align 8
2092 // CHECK2-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
2093 // CHECK2-NEXT:    [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64*
2094 // CHECK2-NEXT:    store i64 [[TMP10]], i64* [[TMP18]], align 8
2095 // CHECK2-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
2096 // CHECK2-NEXT:    store i8* null, i8** [[TMP19]], align 8
2097 // CHECK2-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
2098 // CHECK2-NEXT:    [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i64*
2099 // CHECK2-NEXT:    store i64 [[TMP12]], i64* [[TMP21]], align 8
2100 // CHECK2-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
2101 // CHECK2-NEXT:    [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i64*
2102 // CHECK2-NEXT:    store i64 [[TMP12]], i64* [[TMP23]], align 8
2103 // CHECK2-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
2104 // CHECK2-NEXT:    store i8* null, i8** [[TMP24]], align 8
2105 // CHECK2-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
2106 // CHECK2-NEXT:    [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i64*
2107 // CHECK2-NEXT:    store i64 [[TMP14]], i64* [[TMP26]], align 8
2108 // CHECK2-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
2109 // CHECK2-NEXT:    [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i64*
2110 // CHECK2-NEXT:    store i64 [[TMP14]], i64* [[TMP28]], align 8
2111 // CHECK2-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
2112 // CHECK2-NEXT:    store i8* null, i8** [[TMP29]], align 8
2113 // CHECK2-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
2114 // CHECK2-NEXT:    [[TMP31:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
2115 // CHECK2-NEXT:    [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 0
2116 // CHECK2-NEXT:    [[TMP33:%.*]] = load i16, i16* [[AA]], align 2
2117 // CHECK2-NEXT:    store i16 [[TMP33]], i16* [[TMP32]], align 4
2118 // CHECK2-NEXT:    [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 1
2119 // CHECK2-NEXT:    [[TMP35:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
2120 // CHECK2-NEXT:    store i32 [[TMP35]], i32* [[TMP34]], align 4
2121 // CHECK2-NEXT:    [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 2
2122 // CHECK2-NEXT:    [[TMP37:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
2123 // CHECK2-NEXT:    store i32 [[TMP37]], i32* [[TMP36]], align 4
2124 // CHECK2-NEXT:    [[TMP38:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 1, i64 120, i64 12, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1)
2125 // CHECK2-NEXT:    [[TMP39:%.*]] = bitcast i8* [[TMP38]] to %struct.kmp_task_t_with_privates*
2126 // CHECK2-NEXT:    [[TMP40:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP39]], i32 0, i32 0
2127 // CHECK2-NEXT:    [[TMP41:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP40]], i32 0, i32 0
2128 // CHECK2-NEXT:    [[TMP42:%.*]] = load i8*, i8** [[TMP41]], align 8
2129 // CHECK2-NEXT:    [[TMP43:%.*]] = bitcast %struct.anon* [[AGG_CAPTURED]] to i8*
2130 // CHECK2-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP42]], i8* align 4 [[TMP43]], i64 12, i1 false)
2131 // CHECK2-NEXT:    [[TMP44:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP39]], i32 0, i32 1
2132 // CHECK2-NEXT:    [[TMP45:%.*]] = bitcast i8* [[TMP42]] to %struct.anon*
2133 // CHECK2-NEXT:    [[TMP46:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 0
2134 // CHECK2-NEXT:    [[TMP47:%.*]] = bitcast [3 x i8*]* [[TMP46]] to i8*
2135 // CHECK2-NEXT:    [[TMP48:%.*]] = bitcast i8** [[TMP30]] to i8*
2136 // CHECK2-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP47]], i8* align 8 [[TMP48]], i64 24, i1 false)
2137 // CHECK2-NEXT:    [[TMP49:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 1
2138 // CHECK2-NEXT:    [[TMP50:%.*]] = bitcast [3 x i8*]* [[TMP49]] to i8*
2139 // CHECK2-NEXT:    [[TMP51:%.*]] = bitcast i8** [[TMP31]] to i8*
2140 // CHECK2-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP50]], i8* align 8 [[TMP51]], i64 24, i1 false)
2141 // CHECK2-NEXT:    [[TMP52:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 2
2142 // CHECK2-NEXT:    [[TMP53:%.*]] = bitcast [3 x i64]* [[TMP52]] to i8*
2143 // CHECK2-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP53]], i8* align 8 bitcast ([3 x i64]* @.offload_sizes to i8*), i64 24, i1 false)
2144 // CHECK2-NEXT:    [[TMP54:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 3
2145 // CHECK2-NEXT:    [[TMP55:%.*]] = load i16, i16* [[AA]], align 2
2146 // CHECK2-NEXT:    store i16 [[TMP55]], i16* [[TMP54]], align 8
2147 // CHECK2-NEXT:    [[TMP56:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i8* [[TMP38]])
2148 // CHECK2-NEXT:    [[TMP57:%.*]] = load i32, i32* [[A]], align 4
2149 // CHECK2-NEXT:    [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32*
2150 // CHECK2-NEXT:    store i32 [[TMP57]], i32* [[CONV6]], align 4
2151 // CHECK2-NEXT:    [[TMP58:%.*]] = load i64, i64* [[A_CASTED]], align 8
2152 // CHECK2-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l107(i64 [[TMP58]]) #[[ATTR3:[0-9]+]]
2153 // CHECK2-NEXT:    [[TMP59:%.*]] = load i16, i16* [[AA]], align 2
2154 // CHECK2-NEXT:    [[CONV8:%.*]] = bitcast i64* [[AA_CASTED7]] to i16*
2155 // CHECK2-NEXT:    store i16 [[TMP59]], i16* [[CONV8]], align 2
2156 // CHECK2-NEXT:    [[TMP60:%.*]] = load i64, i64* [[AA_CASTED7]], align 8
2157 // CHECK2-NEXT:    [[TMP61:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS9]], i32 0, i32 0
2158 // CHECK2-NEXT:    [[TMP62:%.*]] = bitcast i8** [[TMP61]] to i64*
2159 // CHECK2-NEXT:    store i64 [[TMP60]], i64* [[TMP62]], align 8
2160 // CHECK2-NEXT:    [[TMP63:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS10]], i32 0, i32 0
2161 // CHECK2-NEXT:    [[TMP64:%.*]] = bitcast i8** [[TMP63]] to i64*
2162 // CHECK2-NEXT:    store i64 [[TMP60]], i64* [[TMP64]], align 8
2163 // CHECK2-NEXT:    [[TMP65:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS11]], i64 0, i64 0
2164 // CHECK2-NEXT:    store i8* null, i8** [[TMP65]], align 8
2165 // CHECK2-NEXT:    [[TMP66:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS9]], i32 0, i32 0
2166 // CHECK2-NEXT:    [[TMP67:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS10]], i32 0, i32 0
2167 // CHECK2-NEXT:    call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10)
2168 // CHECK2-NEXT:    [[TMP68:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113.region_id, i32 1, i8** [[TMP66]], i8** [[TMP67]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.4, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.5, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
2169 // CHECK2-NEXT:    [[TMP69:%.*]] = icmp ne i32 [[TMP68]], 0
2170 // CHECK2-NEXT:    br i1 [[TMP69]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
2171 // CHECK2:       omp_offload.failed:
2172 // CHECK2-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113(i64 [[TMP60]]) #[[ATTR3]]
2173 // CHECK2-NEXT:    br label [[OMP_OFFLOAD_CONT]]
2174 // CHECK2:       omp_offload.cont:
2175 // CHECK2-NEXT:    [[TMP70:%.*]] = load i32, i32* [[A]], align 4
2176 // CHECK2-NEXT:    [[CONV13:%.*]] = bitcast i64* [[A_CASTED12]] to i32*
2177 // CHECK2-NEXT:    store i32 [[TMP70]], i32* [[CONV13]], align 4
2178 // CHECK2-NEXT:    [[TMP71:%.*]] = load i64, i64* [[A_CASTED12]], align 8
2179 // CHECK2-NEXT:    [[TMP72:%.*]] = load i16, i16* [[AA]], align 2
2180 // CHECK2-NEXT:    [[CONV15:%.*]] = bitcast i64* [[AA_CASTED14]] to i16*
2181 // CHECK2-NEXT:    store i16 [[TMP72]], i16* [[CONV15]], align 2
2182 // CHECK2-NEXT:    [[TMP73:%.*]] = load i64, i64* [[AA_CASTED14]], align 8
2183 // CHECK2-NEXT:    [[TMP74:%.*]] = load i32, i32* [[N_ADDR]], align 4
2184 // CHECK2-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP74]], 10
2185 // CHECK2-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
2186 // CHECK2:       omp_if.then:
2187 // CHECK2-NEXT:    [[TMP75:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 0
2188 // CHECK2-NEXT:    [[TMP76:%.*]] = bitcast i8** [[TMP75]] to i64*
2189 // CHECK2-NEXT:    store i64 [[TMP71]], i64* [[TMP76]], align 8
2190 // CHECK2-NEXT:    [[TMP77:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 0
2191 // CHECK2-NEXT:    [[TMP78:%.*]] = bitcast i8** [[TMP77]] to i64*
2192 // CHECK2-NEXT:    store i64 [[TMP71]], i64* [[TMP78]], align 8
2193 // CHECK2-NEXT:    [[TMP79:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 0
2194 // CHECK2-NEXT:    store i8* null, i8** [[TMP79]], align 8
2195 // CHECK2-NEXT:    [[TMP80:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 1
2196 // CHECK2-NEXT:    [[TMP81:%.*]] = bitcast i8** [[TMP80]] to i64*
2197 // CHECK2-NEXT:    store i64 [[TMP73]], i64* [[TMP81]], align 8
2198 // CHECK2-NEXT:    [[TMP82:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 1
2199 // CHECK2-NEXT:    [[TMP83:%.*]] = bitcast i8** [[TMP82]] to i64*
2200 // CHECK2-NEXT:    store i64 [[TMP73]], i64* [[TMP83]], align 8
2201 // CHECK2-NEXT:    [[TMP84:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 1
2202 // CHECK2-NEXT:    store i8* null, i8** [[TMP84]], align 8
2203 // CHECK2-NEXT:    [[TMP85:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 0
2204 // CHECK2-NEXT:    [[TMP86:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 0
2205 // CHECK2-NEXT:    call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10)
2206 // CHECK2-NEXT:    [[TMP87:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120.region_id, i32 2, i8** [[TMP85]], i8** [[TMP86]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.7, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.8, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
2207 // CHECK2-NEXT:    [[TMP88:%.*]] = icmp ne i32 [[TMP87]], 0
2208 // CHECK2-NEXT:    br i1 [[TMP88]], label [[OMP_OFFLOAD_FAILED20:%.*]], label [[OMP_OFFLOAD_CONT21:%.*]]
2209 // CHECK2:       omp_offload.failed20:
2210 // CHECK2-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120(i64 [[TMP71]], i64 [[TMP73]]) #[[ATTR3]]
2211 // CHECK2-NEXT:    br label [[OMP_OFFLOAD_CONT21]]
2212 // CHECK2:       omp_offload.cont21:
2213 // CHECK2-NEXT:    br label [[OMP_IF_END:%.*]]
2214 // CHECK2:       omp_if.else:
2215 // CHECK2-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120(i64 [[TMP71]], i64 [[TMP73]]) #[[ATTR3]]
2216 // CHECK2-NEXT:    br label [[OMP_IF_END]]
2217 // CHECK2:       omp_if.end:
2218 // CHECK2-NEXT:    [[TMP89:%.*]] = load i32, i32* [[N_ADDR]], align 4
2219 // CHECK2-NEXT:    store i32 [[TMP89]], i32* [[DOTCAPTURE_EXPR_22]], align 4
2220 // CHECK2-NEXT:    [[TMP90:%.*]] = load i32, i32* [[A]], align 4
2221 // CHECK2-NEXT:    [[CONV24:%.*]] = bitcast i64* [[A_CASTED23]] to i32*
2222 // CHECK2-NEXT:    store i32 [[TMP90]], i32* [[CONV24]], align 4
2223 // CHECK2-NEXT:    [[TMP91:%.*]] = load i64, i64* [[A_CASTED23]], align 8
2224 // CHECK2-NEXT:    [[TMP92:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_22]], align 4
2225 // CHECK2-NEXT:    [[CONV26:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED25]] to i32*
2226 // CHECK2-NEXT:    store i32 [[TMP92]], i32* [[CONV26]], align 4
2227 // CHECK2-NEXT:    [[TMP93:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED25]], align 8
2228 // CHECK2-NEXT:    [[TMP94:%.*]] = load i32, i32* [[N_ADDR]], align 4
2229 // CHECK2-NEXT:    [[CMP27:%.*]] = icmp sgt i32 [[TMP94]], 20
2230 // CHECK2-NEXT:    br i1 [[CMP27]], label [[OMP_IF_THEN28:%.*]], label [[OMP_IF_ELSE35:%.*]]
2231 // CHECK2:       omp_if.then28:
2232 // CHECK2-NEXT:    [[TMP95:%.*]] = mul nuw i64 [[TMP2]], 4
2233 // CHECK2-NEXT:    [[TMP96:%.*]] = mul nuw i64 5, [[TMP5]]
2234 // CHECK2-NEXT:    [[TMP97:%.*]] = mul nuw i64 [[TMP96]], 8
2235 // CHECK2-NEXT:    [[TMP98:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS29]], i32 0, i32 0
2236 // CHECK2-NEXT:    [[TMP99:%.*]] = bitcast i8** [[TMP98]] to i64*
2237 // CHECK2-NEXT:    store i64 [[TMP91]], i64* [[TMP99]], align 8
2238 // CHECK2-NEXT:    [[TMP100:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS30]], i32 0, i32 0
2239 // CHECK2-NEXT:    [[TMP101:%.*]] = bitcast i8** [[TMP100]] to i64*
2240 // CHECK2-NEXT:    store i64 [[TMP91]], i64* [[TMP101]], align 8
2241 // CHECK2-NEXT:    [[TMP102:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
2242 // CHECK2-NEXT:    store i64 4, i64* [[TMP102]], align 8
2243 // CHECK2-NEXT:    [[TMP103:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS31]], i64 0, i64 0
2244 // CHECK2-NEXT:    store i8* null, i8** [[TMP103]], align 8
2245 // CHECK2-NEXT:    [[TMP104:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS29]], i32 0, i32 1
2246 // CHECK2-NEXT:    [[TMP105:%.*]] = bitcast i8** [[TMP104]] to [10 x float]**
2247 // CHECK2-NEXT:    store [10 x float]* [[B]], [10 x float]** [[TMP105]], align 8
2248 // CHECK2-NEXT:    [[TMP106:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS30]], i32 0, i32 1
2249 // CHECK2-NEXT:    [[TMP107:%.*]] = bitcast i8** [[TMP106]] to [10 x float]**
2250 // CHECK2-NEXT:    store [10 x float]* [[B]], [10 x float]** [[TMP107]], align 8
2251 // CHECK2-NEXT:    [[TMP108:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1
2252 // CHECK2-NEXT:    store i64 40, i64* [[TMP108]], align 8
2253 // CHECK2-NEXT:    [[TMP109:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS31]], i64 0, i64 1
2254 // CHECK2-NEXT:    store i8* null, i8** [[TMP109]], align 8
2255 // CHECK2-NEXT:    [[TMP110:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS29]], i32 0, i32 2
2256 // CHECK2-NEXT:    [[TMP111:%.*]] = bitcast i8** [[TMP110]] to i64*
2257 // CHECK2-NEXT:    store i64 [[TMP2]], i64* [[TMP111]], align 8
2258 // CHECK2-NEXT:    [[TMP112:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS30]], i32 0, i32 2
2259 // CHECK2-NEXT:    [[TMP113:%.*]] = bitcast i8** [[TMP112]] to i64*
2260 // CHECK2-NEXT:    store i64 [[TMP2]], i64* [[TMP113]], align 8
2261 // CHECK2-NEXT:    [[TMP114:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2
2262 // CHECK2-NEXT:    store i64 8, i64* [[TMP114]], align 8
2263 // CHECK2-NEXT:    [[TMP115:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS31]], i64 0, i64 2
2264 // CHECK2-NEXT:    store i8* null, i8** [[TMP115]], align 8
2265 // CHECK2-NEXT:    [[TMP116:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS29]], i32 0, i32 3
2266 // CHECK2-NEXT:    [[TMP117:%.*]] = bitcast i8** [[TMP116]] to float**
2267 // CHECK2-NEXT:    store float* [[VLA]], float** [[TMP117]], align 8
2268 // CHECK2-NEXT:    [[TMP118:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS30]], i32 0, i32 3
2269 // CHECK2-NEXT:    [[TMP119:%.*]] = bitcast i8** [[TMP118]] to float**
2270 // CHECK2-NEXT:    store float* [[VLA]], float** [[TMP119]], align 8
2271 // CHECK2-NEXT:    [[TMP120:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3
2272 // CHECK2-NEXT:    store i64 [[TMP95]], i64* [[TMP120]], align 8
2273 // CHECK2-NEXT:    [[TMP121:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS31]], i64 0, i64 3
2274 // CHECK2-NEXT:    store i8* null, i8** [[TMP121]], align 8
2275 // CHECK2-NEXT:    [[TMP122:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS29]], i32 0, i32 4
2276 // CHECK2-NEXT:    [[TMP123:%.*]] = bitcast i8** [[TMP122]] to [5 x [10 x double]]**
2277 // CHECK2-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP123]], align 8
2278 // CHECK2-NEXT:    [[TMP124:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS30]], i32 0, i32 4
2279 // CHECK2-NEXT:    [[TMP125:%.*]] = bitcast i8** [[TMP124]] to [5 x [10 x double]]**
2280 // CHECK2-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP125]], align 8
2281 // CHECK2-NEXT:    [[TMP126:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4
2282 // CHECK2-NEXT:    store i64 400, i64* [[TMP126]], align 8
2283 // CHECK2-NEXT:    [[TMP127:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS31]], i64 0, i64 4
2284 // CHECK2-NEXT:    store i8* null, i8** [[TMP127]], align 8
2285 // CHECK2-NEXT:    [[TMP128:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS29]], i32 0, i32 5
2286 // CHECK2-NEXT:    [[TMP129:%.*]] = bitcast i8** [[TMP128]] to i64*
2287 // CHECK2-NEXT:    store i64 5, i64* [[TMP129]], align 8
2288 // CHECK2-NEXT:    [[TMP130:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS30]], i32 0, i32 5
2289 // CHECK2-NEXT:    [[TMP131:%.*]] = bitcast i8** [[TMP130]] to i64*
2290 // CHECK2-NEXT:    store i64 5, i64* [[TMP131]], align 8
2291 // CHECK2-NEXT:    [[TMP132:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 5
2292 // CHECK2-NEXT:    store i64 8, i64* [[TMP132]], align 8
2293 // CHECK2-NEXT:    [[TMP133:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS31]], i64 0, i64 5
2294 // CHECK2-NEXT:    store i8* null, i8** [[TMP133]], align 8
2295 // CHECK2-NEXT:    [[TMP134:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS29]], i32 0, i32 6
2296 // CHECK2-NEXT:    [[TMP135:%.*]] = bitcast i8** [[TMP134]] to i64*
2297 // CHECK2-NEXT:    store i64 [[TMP5]], i64* [[TMP135]], align 8
2298 // CHECK2-NEXT:    [[TMP136:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS30]], i32 0, i32 6
2299 // CHECK2-NEXT:    [[TMP137:%.*]] = bitcast i8** [[TMP136]] to i64*
2300 // CHECK2-NEXT:    store i64 [[TMP5]], i64* [[TMP137]], align 8
2301 // CHECK2-NEXT:    [[TMP138:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 6
2302 // CHECK2-NEXT:    store i64 8, i64* [[TMP138]], align 8
2303 // CHECK2-NEXT:    [[TMP139:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS31]], i64 0, i64 6
2304 // CHECK2-NEXT:    store i8* null, i8** [[TMP139]], align 8
2305 // CHECK2-NEXT:    [[TMP140:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS29]], i32 0, i32 7
2306 // CHECK2-NEXT:    [[TMP141:%.*]] = bitcast i8** [[TMP140]] to double**
2307 // CHECK2-NEXT:    store double* [[VLA1]], double** [[TMP141]], align 8
2308 // CHECK2-NEXT:    [[TMP142:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS30]], i32 0, i32 7
2309 // CHECK2-NEXT:    [[TMP143:%.*]] = bitcast i8** [[TMP142]] to double**
2310 // CHECK2-NEXT:    store double* [[VLA1]], double** [[TMP143]], align 8
2311 // CHECK2-NEXT:    [[TMP144:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7
2312 // CHECK2-NEXT:    store i64 [[TMP97]], i64* [[TMP144]], align 8
2313 // CHECK2-NEXT:    [[TMP145:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS31]], i64 0, i64 7
2314 // CHECK2-NEXT:    store i8* null, i8** [[TMP145]], align 8
2315 // CHECK2-NEXT:    [[TMP146:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS29]], i32 0, i32 8
2316 // CHECK2-NEXT:    [[TMP147:%.*]] = bitcast i8** [[TMP146]] to %struct.TT**
2317 // CHECK2-NEXT:    store %struct.TT* [[D]], %struct.TT** [[TMP147]], align 8
2318 // CHECK2-NEXT:    [[TMP148:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS30]], i32 0, i32 8
2319 // CHECK2-NEXT:    [[TMP149:%.*]] = bitcast i8** [[TMP148]] to %struct.TT**
2320 // CHECK2-NEXT:    store %struct.TT* [[D]], %struct.TT** [[TMP149]], align 8
2321 // CHECK2-NEXT:    [[TMP150:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 8
2322 // CHECK2-NEXT:    store i64 16, i64* [[TMP150]], align 8
2323 // CHECK2-NEXT:    [[TMP151:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS31]], i64 0, i64 8
2324 // CHECK2-NEXT:    store i8* null, i8** [[TMP151]], align 8
2325 // CHECK2-NEXT:    [[TMP152:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS29]], i32 0, i32 9
2326 // CHECK2-NEXT:    [[TMP153:%.*]] = bitcast i8** [[TMP152]] to i64*
2327 // CHECK2-NEXT:    store i64 [[TMP93]], i64* [[TMP153]], align 8
2328 // CHECK2-NEXT:    [[TMP154:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS30]], i32 0, i32 9
2329 // CHECK2-NEXT:    [[TMP155:%.*]] = bitcast i8** [[TMP154]] to i64*
2330 // CHECK2-NEXT:    store i64 [[TMP93]], i64* [[TMP155]], align 8
2331 // CHECK2-NEXT:    [[TMP156:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 9
2332 // CHECK2-NEXT:    store i64 4, i64* [[TMP156]], align 8
2333 // CHECK2-NEXT:    [[TMP157:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS31]], i64 0, i64 9
2334 // CHECK2-NEXT:    store i8* null, i8** [[TMP157]], align 8
2335 // CHECK2-NEXT:    [[TMP158:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS29]], i32 0, i32 0
2336 // CHECK2-NEXT:    [[TMP159:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS30]], i32 0, i32 0
2337 // CHECK2-NEXT:    [[TMP160:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
2338 // CHECK2-NEXT:    call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10)
2339 // CHECK2-NEXT:    [[TMP161:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145.region_id, i32 10, i8** [[TMP158]], i8** [[TMP159]], i64* [[TMP160]], i64* getelementptr inbounds ([10 x i64], [10 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
2340 // CHECK2-NEXT:    [[TMP162:%.*]] = icmp ne i32 [[TMP161]], 0
2341 // CHECK2-NEXT:    br i1 [[TMP162]], label [[OMP_OFFLOAD_FAILED33:%.*]], label [[OMP_OFFLOAD_CONT34:%.*]]
2342 // CHECK2:       omp_offload.failed33:
2343 // CHECK2-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145(i64 [[TMP91]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]], i64 [[TMP93]]) #[[ATTR3]]
2344 // CHECK2-NEXT:    br label [[OMP_OFFLOAD_CONT34]]
2345 // CHECK2:       omp_offload.cont34:
2346 // CHECK2-NEXT:    br label [[OMP_IF_END36:%.*]]
2347 // CHECK2:       omp_if.else35:
2348 // CHECK2-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145(i64 [[TMP91]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]], i64 [[TMP93]]) #[[ATTR3]]
2349 // CHECK2-NEXT:    br label [[OMP_IF_END36]]
2350 // CHECK2:       omp_if.end36:
2351 // CHECK2-NEXT:    [[TMP163:%.*]] = load i32, i32* [[A]], align 4
2352 // CHECK2-NEXT:    [[TMP164:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
2353 // CHECK2-NEXT:    call void @llvm.stackrestore(i8* [[TMP164]])
2354 // CHECK2-NEXT:    ret i32 [[TMP163]]
2355 //
2356 //
2357 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103
2358 // CHECK2-SAME: (i64 [[AA:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] {
2359 // CHECK2-NEXT:  entry:
2360 // CHECK2-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
2361 // CHECK2-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
2362 // CHECK2-NEXT:    [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8
2363 // CHECK2-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
2364 // CHECK2-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]])
2365 // CHECK2-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
2366 // CHECK2-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
2367 // CHECK2-NEXT:    store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8
2368 // CHECK2-NEXT:    [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
2369 // CHECK2-NEXT:    [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
2370 // CHECK2-NEXT:    [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32*
2371 // CHECK2-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 8
2372 // CHECK2-NEXT:    [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 8
2373 // CHECK2-NEXT:    call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
2374 // CHECK2-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV]], align 8
2375 // CHECK2-NEXT:    [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
2376 // CHECK2-NEXT:    store i16 [[TMP3]], i16* [[CONV5]], align 2
2377 // CHECK2-NEXT:    [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
2378 // CHECK2-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]])
2379 // CHECK2-NEXT:    ret void
2380 //
2381 //
2382 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined.
2383 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] {
2384 // CHECK2-NEXT:  entry:
2385 // CHECK2-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
2386 // CHECK2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
2387 // CHECK2-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
2388 // CHECK2-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
2389 // CHECK2-NEXT:    [[TMP:%.*]] = alloca i32, align 4
2390 // CHECK2-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
2391 // CHECK2-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
2392 // CHECK2-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2393 // CHECK2-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2394 // CHECK2-NEXT:    [[I:%.*]] = alloca i32, align 4
2395 // CHECK2-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
2396 // CHECK2-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
2397 // CHECK2-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
2398 // CHECK2-NEXT:    [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
2399 // CHECK2-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
2400 // CHECK2-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
2401 // CHECK2-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
2402 // CHECK2-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
2403 // CHECK2-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
2404 // CHECK2-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
2405 // CHECK2-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
2406 // CHECK2-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2407 // CHECK2-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
2408 // CHECK2-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2409 // CHECK2:       cond.true:
2410 // CHECK2-NEXT:    br label [[COND_END:%.*]]
2411 // CHECK2:       cond.false:
2412 // CHECK2-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2413 // CHECK2-NEXT:    br label [[COND_END]]
2414 // CHECK2:       cond.end:
2415 // CHECK2-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
2416 // CHECK2-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
2417 // CHECK2-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
2418 // CHECK2-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
2419 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
2420 // CHECK2:       omp.inner.for.cond:
2421 // CHECK2-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2422 // CHECK2-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2423 // CHECK2-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
2424 // CHECK2-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2425 // CHECK2:       omp.inner.for.body:
2426 // CHECK2-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2427 // CHECK2-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
2428 // CHECK2-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
2429 // CHECK2-NEXT:    store i32 [[ADD]], i32* [[I]], align 4
2430 // CHECK2-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
2431 // CHECK2:       omp.body.continue:
2432 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
2433 // CHECK2:       omp.inner.for.inc:
2434 // CHECK2-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2435 // CHECK2-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
2436 // CHECK2-NEXT:    store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4
2437 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_COND]]
2438 // CHECK2:       omp.inner.for.end:
2439 // CHECK2-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
2440 // CHECK2:       omp.loop.exit:
2441 // CHECK2-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
2442 // CHECK2-NEXT:    ret void
2443 //
2444 //
2445 // CHECK2-LABEL: define {{[^@]+}}@.omp_task_privates_map.
2446 // CHECK2-SAME: (%struct..kmp_privates.t* noalias [[TMP0:%.*]], i16** noalias [[TMP1:%.*]], [3 x i8*]** noalias [[TMP2:%.*]], [3 x i8*]** noalias [[TMP3:%.*]], [3 x i64]** noalias [[TMP4:%.*]]) #[[ATTR4:[0-9]+]] {
2447 // CHECK2-NEXT:  entry:
2448 // CHECK2-NEXT:    [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 8
2449 // CHECK2-NEXT:    [[DOTADDR1:%.*]] = alloca i16**, align 8
2450 // CHECK2-NEXT:    [[DOTADDR2:%.*]] = alloca [3 x i8*]**, align 8
2451 // CHECK2-NEXT:    [[DOTADDR3:%.*]] = alloca [3 x i8*]**, align 8
2452 // CHECK2-NEXT:    [[DOTADDR4:%.*]] = alloca [3 x i64]**, align 8
2453 // CHECK2-NEXT:    store %struct..kmp_privates.t* [[TMP0]], %struct..kmp_privates.t** [[DOTADDR]], align 8
2454 // CHECK2-NEXT:    store i16** [[TMP1]], i16*** [[DOTADDR1]], align 8
2455 // CHECK2-NEXT:    store [3 x i8*]** [[TMP2]], [3 x i8*]*** [[DOTADDR2]], align 8
2456 // CHECK2-NEXT:    store [3 x i8*]** [[TMP3]], [3 x i8*]*** [[DOTADDR3]], align 8
2457 // CHECK2-NEXT:    store [3 x i64]** [[TMP4]], [3 x i64]*** [[DOTADDR4]], align 8
2458 // CHECK2-NEXT:    [[TMP5:%.*]] = load %struct..kmp_privates.t*, %struct..kmp_privates.t** [[DOTADDR]], align 8
2459 // CHECK2-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 0
2460 // CHECK2-NEXT:    [[TMP7:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR2]], align 8
2461 // CHECK2-NEXT:    store [3 x i8*]* [[TMP6]], [3 x i8*]** [[TMP7]], align 8
2462 // CHECK2-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 1
2463 // CHECK2-NEXT:    [[TMP9:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR3]], align 8
2464 // CHECK2-NEXT:    store [3 x i8*]* [[TMP8]], [3 x i8*]** [[TMP9]], align 8
2465 // CHECK2-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 2
2466 // CHECK2-NEXT:    [[TMP11:%.*]] = load [3 x i64]**, [3 x i64]*** [[DOTADDR4]], align 8
2467 // CHECK2-NEXT:    store [3 x i64]* [[TMP10]], [3 x i64]** [[TMP11]], align 8
2468 // CHECK2-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 3
2469 // CHECK2-NEXT:    [[TMP13:%.*]] = load i16**, i16*** [[DOTADDR1]], align 8
2470 // CHECK2-NEXT:    store i16* [[TMP12]], i16** [[TMP13]], align 8
2471 // CHECK2-NEXT:    ret void
2472 //
2473 //
2474 // CHECK2-LABEL: define {{[^@]+}}@.omp_task_entry.
2475 // CHECK2-SAME: (i32 signext [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] {
2476 // CHECK2-NEXT:  entry:
2477 // CHECK2-NEXT:    [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
2478 // CHECK2-NEXT:    [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8
2479 // CHECK2-NEXT:    [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8
2480 // CHECK2-NEXT:    [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8
2481 // CHECK2-NEXT:    [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8
2482 // CHECK2-NEXT:    [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 8
2483 // CHECK2-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca i16*, align 8
2484 // CHECK2-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca [3 x i8*]*, align 8
2485 // CHECK2-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca [3 x i8*]*, align 8
2486 // CHECK2-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca [3 x i64]*, align 8
2487 // CHECK2-NEXT:    [[AA_CASTED_I:%.*]] = alloca i64, align 8
2488 // CHECK2-NEXT:    [[DOTCAPTURE_EXPR__CASTED_I:%.*]] = alloca i64, align 8
2489 // CHECK2-NEXT:    [[DOTCAPTURE_EXPR__CASTED5_I:%.*]] = alloca i64, align 8
2490 // CHECK2-NEXT:    [[DOTADDR:%.*]] = alloca i32, align 4
2491 // CHECK2-NEXT:    [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8
2492 // CHECK2-NEXT:    store i32 [[TMP0]], i32* [[DOTADDR]], align 4
2493 // CHECK2-NEXT:    store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8
2494 // CHECK2-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4
2495 // CHECK2-NEXT:    [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8
2496 // CHECK2-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
2497 // CHECK2-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
2498 // CHECK2-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0
2499 // CHECK2-NEXT:    [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8
2500 // CHECK2-NEXT:    [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon*
2501 // CHECK2-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1
2502 // CHECK2-NEXT:    [[TMP10:%.*]] = bitcast %struct..kmp_privates.t* [[TMP9]] to i8*
2503 // CHECK2-NEXT:    [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8*
2504 // CHECK2-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META11:![0-9]+]])
2505 // CHECK2-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META14:![0-9]+]])
2506 // CHECK2-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META16:![0-9]+]])
2507 // CHECK2-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]])
2508 // CHECK2-NEXT:    store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !20
2509 // CHECK2-NEXT:    store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !20
2510 // CHECK2-NEXT:    store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !20
2511 // CHECK2-NEXT:    store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* @.omp_task_privates_map. to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !20
2512 // CHECK2-NEXT:    store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !20
2513 // CHECK2-NEXT:    store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !20
2514 // CHECK2-NEXT:    [[TMP12:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !20
2515 // CHECK2-NEXT:    [[TMP13:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !20
2516 // CHECK2-NEXT:    [[TMP14:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !20
2517 // CHECK2-NEXT:    [[TMP15:%.*]] = bitcast void (i8*, ...)* [[TMP13]] to void (i8*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)*
2518 // CHECK2-NEXT:    call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]]
2519 // CHECK2-NEXT:    [[TMP16:%.*]] = load i16*, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !20
2520 // CHECK2-NEXT:    [[TMP17:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !20
2521 // CHECK2-NEXT:    [[TMP18:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 8, !noalias !20
2522 // CHECK2-NEXT:    [[TMP19:%.*]] = load [3 x i64]*, [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 8, !noalias !20
2523 // CHECK2-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP17]], i64 0, i64 0
2524 // CHECK2-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP18]], i64 0, i64 0
2525 // CHECK2-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[TMP19]], i64 0, i64 0
2526 // CHECK2-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP12]], i32 0, i32 1
2527 // CHECK2-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[TMP12]], i32 0, i32 2
2528 // CHECK2-NEXT:    [[TMP25:%.*]] = load i32, i32* [[TMP23]], align 4
2529 // CHECK2-NEXT:    [[TMP26:%.*]] = load i32, i32* [[TMP24]], align 4
2530 // CHECK2-NEXT:    call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) #[[ATTR3]]
2531 // CHECK2-NEXT:    [[TMP27:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 [[TMP25]], i32 [[TMP26]]) #[[ATTR3]]
2532 // CHECK2-NEXT:    [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0
2533 // CHECK2-NEXT:    br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]]
2534 // CHECK2:       omp_offload.failed.i:
2535 // CHECK2-NEXT:    [[TMP29:%.*]] = load i16, i16* [[TMP16]], align 2
2536 // CHECK2-NEXT:    [[CONV_I:%.*]] = bitcast i64* [[AA_CASTED_I]] to i16*
2537 // CHECK2-NEXT:    store i16 [[TMP29]], i16* [[CONV_I]], align 2, !noalias !20
2538 // CHECK2-NEXT:    [[TMP30:%.*]] = load i64, i64* [[AA_CASTED_I]], align 8, !noalias !20
2539 // CHECK2-NEXT:    [[TMP31:%.*]] = load i32, i32* [[TMP23]], align 4
2540 // CHECK2-NEXT:    [[CONV4_I:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED_I]] to i32*
2541 // CHECK2-NEXT:    store i32 [[TMP31]], i32* [[CONV4_I]], align 4, !noalias !20
2542 // CHECK2-NEXT:    [[TMP32:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED_I]], align 8, !noalias !20
2543 // CHECK2-NEXT:    [[TMP33:%.*]] = load i32, i32* [[TMP24]], align 4
2544 // CHECK2-NEXT:    [[CONV6_I:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED5_I]] to i32*
2545 // CHECK2-NEXT:    store i32 [[TMP33]], i32* [[CONV6_I]], align 4, !noalias !20
2546 // CHECK2-NEXT:    [[TMP34:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED5_I]], align 8, !noalias !20
2547 // CHECK2-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103(i64 [[TMP30]], i64 [[TMP32]], i64 [[TMP34]]) #[[ATTR3]]
2548 // CHECK2-NEXT:    br label [[DOTOMP_OUTLINED__1_EXIT]]
2549 // CHECK2:       .omp_outlined..1.exit:
2550 // CHECK2-NEXT:    ret i32 0
2551 //
2552 //
2553 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l107
2554 // CHECK2-SAME: (i64 [[A:%.*]]) #[[ATTR2]] {
2555 // CHECK2-NEXT:  entry:
2556 // CHECK2-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
2557 // CHECK2-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
2558 // CHECK2-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
2559 // CHECK2-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
2560 // CHECK2-NEXT:    [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
2561 // CHECK2-NEXT:    [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32*
2562 // CHECK2-NEXT:    store i32 [[TMP0]], i32* [[CONV1]], align 4
2563 // CHECK2-NEXT:    [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
2564 // CHECK2-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]])
2565 // CHECK2-NEXT:    ret void
2566 //
2567 //
2568 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..2
2569 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]]) #[[ATTR2]] {
2570 // CHECK2-NEXT:  entry:
2571 // CHECK2-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
2572 // CHECK2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
2573 // CHECK2-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
2574 // CHECK2-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
2575 // CHECK2-NEXT:    [[TMP:%.*]] = alloca i32, align 4
2576 // CHECK2-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
2577 // CHECK2-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
2578 // CHECK2-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2579 // CHECK2-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2580 // CHECK2-NEXT:    [[I:%.*]] = alloca i32, align 4
2581 // CHECK2-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
2582 // CHECK2-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
2583 // CHECK2-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
2584 // CHECK2-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
2585 // CHECK2-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
2586 // CHECK2-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
2587 // CHECK2-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
2588 // CHECK2-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
2589 // CHECK2-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
2590 // CHECK2-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
2591 // CHECK2-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
2592 // CHECK2-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2593 // CHECK2-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
2594 // CHECK2-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2595 // CHECK2:       cond.true:
2596 // CHECK2-NEXT:    br label [[COND_END:%.*]]
2597 // CHECK2:       cond.false:
2598 // CHECK2-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2599 // CHECK2-NEXT:    br label [[COND_END]]
2600 // CHECK2:       cond.end:
2601 // CHECK2-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
2602 // CHECK2-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
2603 // CHECK2-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
2604 // CHECK2-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
2605 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
2606 // CHECK2:       omp.inner.for.cond:
2607 // CHECK2-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2608 // CHECK2-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2609 // CHECK2-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
2610 // CHECK2-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2611 // CHECK2:       omp.inner.for.body:
2612 // CHECK2-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2613 // CHECK2-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
2614 // CHECK2-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
2615 // CHECK2-NEXT:    store i32 [[ADD]], i32* [[I]], align 4
2616 // CHECK2-NEXT:    [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
2617 // CHECK2-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
2618 // CHECK2-NEXT:    store i32 [[ADD2]], i32* [[CONV]], align 8
2619 // CHECK2-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
2620 // CHECK2:       omp.body.continue:
2621 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
2622 // CHECK2:       omp.inner.for.inc:
2623 // CHECK2-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2624 // CHECK2-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1
2625 // CHECK2-NEXT:    store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4
2626 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_COND]]
2627 // CHECK2:       omp.inner.for.end:
2628 // CHECK2-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
2629 // CHECK2:       omp.loop.exit:
2630 // CHECK2-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
2631 // CHECK2-NEXT:    ret void
2632 //
2633 //
2634 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113
2635 // CHECK2-SAME: (i64 [[AA:%.*]]) #[[ATTR2]] {
2636 // CHECK2-NEXT:  entry:
2637 // CHECK2-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
2638 // CHECK2-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
2639 // CHECK2-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
2640 // CHECK2-NEXT:    [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
2641 // CHECK2-NEXT:    [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8
2642 // CHECK2-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
2643 // CHECK2-NEXT:    store i16 [[TMP0]], i16* [[CONV1]], align 2
2644 // CHECK2-NEXT:    [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
2645 // CHECK2-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP1]])
2646 // CHECK2-NEXT:    ret void
2647 //
2648 //
2649 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..3
2650 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] {
2651 // CHECK2-NEXT:  entry:
2652 // CHECK2-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
2653 // CHECK2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
2654 // CHECK2-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
2655 // CHECK2-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
2656 // CHECK2-NEXT:    [[TMP:%.*]] = alloca i32, align 4
2657 // CHECK2-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
2658 // CHECK2-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
2659 // CHECK2-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2660 // CHECK2-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2661 // CHECK2-NEXT:    [[I:%.*]] = alloca i32, align 4
2662 // CHECK2-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
2663 // CHECK2-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
2664 // CHECK2-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
2665 // CHECK2-NEXT:    [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
2666 // CHECK2-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
2667 // CHECK2-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
2668 // CHECK2-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
2669 // CHECK2-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
2670 // CHECK2-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
2671 // CHECK2-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
2672 // CHECK2-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
2673 // CHECK2-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2674 // CHECK2-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
2675 // CHECK2-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2676 // CHECK2:       cond.true:
2677 // CHECK2-NEXT:    br label [[COND_END:%.*]]
2678 // CHECK2:       cond.false:
2679 // CHECK2-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2680 // CHECK2-NEXT:    br label [[COND_END]]
2681 // CHECK2:       cond.end:
2682 // CHECK2-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
2683 // CHECK2-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
2684 // CHECK2-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
2685 // CHECK2-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
2686 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
2687 // CHECK2:       omp.inner.for.cond:
2688 // CHECK2-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2689 // CHECK2-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2690 // CHECK2-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
2691 // CHECK2-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2692 // CHECK2:       omp.inner.for.body:
2693 // CHECK2-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2694 // CHECK2-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
2695 // CHECK2-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
2696 // CHECK2-NEXT:    store i32 [[ADD]], i32* [[I]], align 4
2697 // CHECK2-NEXT:    [[TMP8:%.*]] = load i16, i16* [[CONV]], align 8
2698 // CHECK2-NEXT:    [[CONV2:%.*]] = sext i16 [[TMP8]] to i32
2699 // CHECK2-NEXT:    [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
2700 // CHECK2-NEXT:    [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
2701 // CHECK2-NEXT:    store i16 [[CONV4]], i16* [[CONV]], align 8
2702 // CHECK2-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
2703 // CHECK2:       omp.body.continue:
2704 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
2705 // CHECK2:       omp.inner.for.inc:
2706 // CHECK2-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2707 // CHECK2-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP9]], 1
2708 // CHECK2-NEXT:    store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4
2709 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_COND]]
2710 // CHECK2:       omp.inner.for.end:
2711 // CHECK2-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
2712 // CHECK2:       omp.loop.exit:
2713 // CHECK2-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
2714 // CHECK2-NEXT:    ret void
2715 //
2716 //
2717 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120
2718 // CHECK2-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] {
2719 // CHECK2-NEXT:  entry:
2720 // CHECK2-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
2721 // CHECK2-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
2722 // CHECK2-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
2723 // CHECK2-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
2724 // CHECK2-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
2725 // CHECK2-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
2726 // CHECK2-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
2727 // CHECK2-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
2728 // CHECK2-NEXT:    [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
2729 // CHECK2-NEXT:    [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
2730 // CHECK2-NEXT:    store i32 [[TMP0]], i32* [[CONV2]], align 4
2731 // CHECK2-NEXT:    [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
2732 // CHECK2-NEXT:    [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
2733 // CHECK2-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
2734 // CHECK2-NEXT:    store i16 [[TMP2]], i16* [[CONV3]], align 2
2735 // CHECK2-NEXT:    [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
2736 // CHECK2-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
2737 // CHECK2-NEXT:    ret void
2738 //
2739 //
2740 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..6
2741 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] {
2742 // CHECK2-NEXT:  entry:
2743 // CHECK2-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
2744 // CHECK2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
2745 // CHECK2-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
2746 // CHECK2-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
2747 // CHECK2-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
2748 // CHECK2-NEXT:    [[TMP:%.*]] = alloca i32, align 4
2749 // CHECK2-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
2750 // CHECK2-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
2751 // CHECK2-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2752 // CHECK2-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2753 // CHECK2-NEXT:    [[I:%.*]] = alloca i32, align 4
2754 // CHECK2-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
2755 // CHECK2-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
2756 // CHECK2-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
2757 // CHECK2-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
2758 // CHECK2-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
2759 // CHECK2-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
2760 // CHECK2-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
2761 // CHECK2-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
2762 // CHECK2-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
2763 // CHECK2-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
2764 // CHECK2-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
2765 // CHECK2-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
2766 // CHECK2-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
2767 // CHECK2-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2768 // CHECK2-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
2769 // CHECK2-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2770 // CHECK2:       cond.true:
2771 // CHECK2-NEXT:    br label [[COND_END:%.*]]
2772 // CHECK2:       cond.false:
2773 // CHECK2-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2774 // CHECK2-NEXT:    br label [[COND_END]]
2775 // CHECK2:       cond.end:
2776 // CHECK2-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
2777 // CHECK2-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
2778 // CHECK2-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
2779 // CHECK2-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
2780 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
2781 // CHECK2:       omp.inner.for.cond:
2782 // CHECK2-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2783 // CHECK2-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2784 // CHECK2-NEXT:    [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
2785 // CHECK2-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2786 // CHECK2:       omp.inner.for.body:
2787 // CHECK2-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2788 // CHECK2-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
2789 // CHECK2-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
2790 // CHECK2-NEXT:    store i32 [[ADD]], i32* [[I]], align 4
2791 // CHECK2-NEXT:    [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
2792 // CHECK2-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
2793 // CHECK2-NEXT:    store i32 [[ADD3]], i32* [[CONV]], align 8
2794 // CHECK2-NEXT:    [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 8
2795 // CHECK2-NEXT:    [[CONV4:%.*]] = sext i16 [[TMP9]] to i32
2796 // CHECK2-NEXT:    [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
2797 // CHECK2-NEXT:    [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
2798 // CHECK2-NEXT:    store i16 [[CONV6]], i16* [[CONV1]], align 8
2799 // CHECK2-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
2800 // CHECK2:       omp.body.continue:
2801 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
2802 // CHECK2:       omp.inner.for.inc:
2803 // CHECK2-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2804 // CHECK2-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1
2805 // CHECK2-NEXT:    store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4
2806 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_COND]]
2807 // CHECK2:       omp.inner.for.end:
2808 // CHECK2-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
2809 // CHECK2:       omp.loop.exit:
2810 // CHECK2-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
2811 // CHECK2-NEXT:    ret void
2812 //
2813 //
2814 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145
2815 // CHECK2-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] {
2816 // CHECK2-NEXT:  entry:
2817 // CHECK2-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
2818 // CHECK2-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
2819 // CHECK2-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
2820 // CHECK2-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 8
2821 // CHECK2-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
2822 // CHECK2-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
2823 // CHECK2-NEXT:    [[VLA_ADDR4:%.*]] = alloca i64, align 8
2824 // CHECK2-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 8
2825 // CHECK2-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
2826 // CHECK2-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
2827 // CHECK2-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
2828 // CHECK2-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
2829 // CHECK2-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
2830 // CHECK2-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
2831 // CHECK2-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
2832 // CHECK2-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 8
2833 // CHECK2-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
2834 // CHECK2-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
2835 // CHECK2-NEXT:    store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
2836 // CHECK2-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 8
2837 // CHECK2-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
2838 // CHECK2-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
2839 // CHECK2-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
2840 // CHECK2-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
2841 // CHECK2-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
2842 // CHECK2-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
2843 // CHECK2-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
2844 // CHECK2-NEXT:    [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
2845 // CHECK2-NEXT:    [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
2846 // CHECK2-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
2847 // CHECK2-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
2848 // CHECK2-NEXT:    [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
2849 // CHECK2-NEXT:    [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
2850 // CHECK2-NEXT:    [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32*
2851 // CHECK2-NEXT:    store i32 [[TMP8]], i32* [[CONV6]], align 4
2852 // CHECK2-NEXT:    [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
2853 // CHECK2-NEXT:    [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 8
2854 // CHECK2-NEXT:    [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
2855 // CHECK2-NEXT:    store i32 [[TMP10]], i32* [[CONV7]], align 4
2856 // CHECK2-NEXT:    [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
2857 // CHECK2-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]])
2858 // CHECK2-NEXT:    ret void
2859 //
2860 //
2861 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..9
2862 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] {
2863 // CHECK2-NEXT:  entry:
2864 // CHECK2-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
2865 // CHECK2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
2866 // CHECK2-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
2867 // CHECK2-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
2868 // CHECK2-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
2869 // CHECK2-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 8
2870 // CHECK2-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
2871 // CHECK2-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
2872 // CHECK2-NEXT:    [[VLA_ADDR4:%.*]] = alloca i64, align 8
2873 // CHECK2-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 8
2874 // CHECK2-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
2875 // CHECK2-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
2876 // CHECK2-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
2877 // CHECK2-NEXT:    [[TMP:%.*]] = alloca i32, align 4
2878 // CHECK2-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
2879 // CHECK2-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
2880 // CHECK2-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2881 // CHECK2-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2882 // CHECK2-NEXT:    [[I:%.*]] = alloca i32, align 4
2883 // CHECK2-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
2884 // CHECK2-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
2885 // CHECK2-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
2886 // CHECK2-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
2887 // CHECK2-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
2888 // CHECK2-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 8
2889 // CHECK2-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
2890 // CHECK2-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
2891 // CHECK2-NEXT:    store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
2892 // CHECK2-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 8
2893 // CHECK2-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
2894 // CHECK2-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
2895 // CHECK2-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
2896 // CHECK2-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
2897 // CHECK2-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
2898 // CHECK2-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
2899 // CHECK2-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
2900 // CHECK2-NEXT:    [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
2901 // CHECK2-NEXT:    [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
2902 // CHECK2-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
2903 // CHECK2-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
2904 // CHECK2-NEXT:    [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
2905 // CHECK2-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
2906 // CHECK2-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
2907 // CHECK2-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
2908 // CHECK2-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
2909 // CHECK2-NEXT:    [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 8
2910 // CHECK2-NEXT:    [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
2911 // CHECK2-NEXT:    [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
2912 // CHECK2-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
2913 // CHECK2-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
2914 // CHECK2:       omp.dispatch.cond:
2915 // CHECK2-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2916 // CHECK2-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 9
2917 // CHECK2-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2918 // CHECK2:       cond.true:
2919 // CHECK2-NEXT:    br label [[COND_END:%.*]]
2920 // CHECK2:       cond.false:
2921 // CHECK2-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2922 // CHECK2-NEXT:    br label [[COND_END]]
2923 // CHECK2:       cond.end:
2924 // CHECK2-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
2925 // CHECK2-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
2926 // CHECK2-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
2927 // CHECK2-NEXT:    store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
2928 // CHECK2-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2929 // CHECK2-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2930 // CHECK2-NEXT:    [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
2931 // CHECK2-NEXT:    br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
2932 // CHECK2:       omp.dispatch.body:
2933 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
2934 // CHECK2:       omp.inner.for.cond:
2935 // CHECK2-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
2936 // CHECK2-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !21
2937 // CHECK2-NEXT:    [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
2938 // CHECK2-NEXT:    br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2939 // CHECK2:       omp.inner.for.body:
2940 // CHECK2-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
2941 // CHECK2-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
2942 // CHECK2-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
2943 // CHECK2-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !21
2944 // CHECK2-NEXT:    [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !21
2945 // CHECK2-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP19]], 1
2946 // CHECK2-NEXT:    store i32 [[ADD8]], i32* [[CONV]], align 8, !llvm.access.group !21
2947 // CHECK2-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
2948 // CHECK2-NEXT:    [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !21
2949 // CHECK2-NEXT:    [[CONV9:%.*]] = fpext float [[TMP20]] to double
2950 // CHECK2-NEXT:    [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00
2951 // CHECK2-NEXT:    [[CONV11:%.*]] = fptrunc double [[ADD10]] to float
2952 // CHECK2-NEXT:    store float [[CONV11]], float* [[ARRAYIDX]], align 4, !llvm.access.group !21
2953 // CHECK2-NEXT:    [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3
2954 // CHECK2-NEXT:    [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4, !llvm.access.group !21
2955 // CHECK2-NEXT:    [[CONV13:%.*]] = fpext float [[TMP21]] to double
2956 // CHECK2-NEXT:    [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00
2957 // CHECK2-NEXT:    [[CONV15:%.*]] = fptrunc double [[ADD14]] to float
2958 // CHECK2-NEXT:    store float [[CONV15]], float* [[ARRAYIDX12]], align 4, !llvm.access.group !21
2959 // CHECK2-NEXT:    [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1
2960 // CHECK2-NEXT:    [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i64 0, i64 2
2961 // CHECK2-NEXT:    [[TMP22:%.*]] = load double, double* [[ARRAYIDX17]], align 8, !llvm.access.group !21
2962 // CHECK2-NEXT:    [[ADD18:%.*]] = fadd double [[TMP22]], 1.000000e+00
2963 // CHECK2-NEXT:    store double [[ADD18]], double* [[ARRAYIDX17]], align 8, !llvm.access.group !21
2964 // CHECK2-NEXT:    [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]]
2965 // CHECK2-NEXT:    [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP23]]
2966 // CHECK2-NEXT:    [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i64 3
2967 // CHECK2-NEXT:    [[TMP24:%.*]] = load double, double* [[ARRAYIDX20]], align 8, !llvm.access.group !21
2968 // CHECK2-NEXT:    [[ADD21:%.*]] = fadd double [[TMP24]], 1.000000e+00
2969 // CHECK2-NEXT:    store double [[ADD21]], double* [[ARRAYIDX20]], align 8, !llvm.access.group !21
2970 // CHECK2-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0
2971 // CHECK2-NEXT:    [[TMP25:%.*]] = load i64, i64* [[X]], align 8, !llvm.access.group !21
2972 // CHECK2-NEXT:    [[ADD22:%.*]] = add nsw i64 [[TMP25]], 1
2973 // CHECK2-NEXT:    store i64 [[ADD22]], i64* [[X]], align 8, !llvm.access.group !21
2974 // CHECK2-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1
2975 // CHECK2-NEXT:    [[TMP26:%.*]] = load i8, i8* [[Y]], align 8, !llvm.access.group !21
2976 // CHECK2-NEXT:    [[CONV23:%.*]] = sext i8 [[TMP26]] to i32
2977 // CHECK2-NEXT:    [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1
2978 // CHECK2-NEXT:    [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8
2979 // CHECK2-NEXT:    store i8 [[CONV25]], i8* [[Y]], align 8, !llvm.access.group !21
2980 // CHECK2-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
2981 // CHECK2:       omp.body.continue:
2982 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
2983 // CHECK2:       omp.inner.for.inc:
2984 // CHECK2-NEXT:    [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
2985 // CHECK2-NEXT:    [[ADD26:%.*]] = add nsw i32 [[TMP27]], 1
2986 // CHECK2-NEXT:    store i32 [[ADD26]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
2987 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]]
2988 // CHECK2:       omp.inner.for.end:
2989 // CHECK2-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
2990 // CHECK2:       omp.dispatch.inc:
2991 // CHECK2-NEXT:    [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
2992 // CHECK2-NEXT:    [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
2993 // CHECK2-NEXT:    [[ADD27:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]
2994 // CHECK2-NEXT:    store i32 [[ADD27]], i32* [[DOTOMP_LB]], align 4
2995 // CHECK2-NEXT:    [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2996 // CHECK2-NEXT:    [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
2997 // CHECK2-NEXT:    [[ADD28:%.*]] = add nsw i32 [[TMP30]], [[TMP31]]
2998 // CHECK2-NEXT:    store i32 [[ADD28]], i32* [[DOTOMP_UB]], align 4
2999 // CHECK2-NEXT:    br label [[OMP_DISPATCH_COND]]
3000 // CHECK2:       omp.dispatch.end:
3001 // CHECK2-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]])
3002 // CHECK2-NEXT:    ret void
3003 //
3004 //
3005 // CHECK2-LABEL: define {{[^@]+}}@_Z3bari
3006 // CHECK2-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
3007 // CHECK2-NEXT:  entry:
3008 // CHECK2-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
3009 // CHECK2-NEXT:    [[A:%.*]] = alloca i32, align 4
3010 // CHECK2-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8
3011 // CHECK2-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
3012 // CHECK2-NEXT:    store i32 0, i32* [[A]], align 4
3013 // CHECK2-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
3014 // CHECK2-NEXT:    [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]])
3015 // CHECK2-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
3016 // CHECK2-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
3017 // CHECK2-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
3018 // CHECK2-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
3019 // CHECK2-NEXT:    [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]])
3020 // CHECK2-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
3021 // CHECK2-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
3022 // CHECK2-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
3023 // CHECK2-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
3024 // CHECK2-NEXT:    [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]])
3025 // CHECK2-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
3026 // CHECK2-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
3027 // CHECK2-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
3028 // CHECK2-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
3029 // CHECK2-NEXT:    [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]])
3030 // CHECK2-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
3031 // CHECK2-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
3032 // CHECK2-NEXT:    store i32 [[ADD6]], i32* [[A]], align 4
3033 // CHECK2-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
3034 // CHECK2-NEXT:    ret i32 [[TMP8]]
3035 //
3036 //
3037 // CHECK2-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
3038 // CHECK2-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 {
3039 // CHECK2-NEXT:  entry:
3040 // CHECK2-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
3041 // CHECK2-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
3042 // CHECK2-NEXT:    [[B:%.*]] = alloca i32, align 4
3043 // CHECK2-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 8
3044 // CHECK2-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
3045 // CHECK2-NEXT:    [[B_CASTED:%.*]] = alloca i64, align 8
3046 // CHECK2-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8
3047 // CHECK2-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8
3048 // CHECK2-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8
3049 // CHECK2-NEXT:    [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 8
3050 // CHECK2-NEXT:    [[TMP:%.*]] = alloca i32, align 4
3051 // CHECK2-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
3052 // CHECK2-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
3053 // CHECK2-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
3054 // CHECK2-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
3055 // CHECK2-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
3056 // CHECK2-NEXT:    store i32 [[ADD]], i32* [[B]], align 4
3057 // CHECK2-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
3058 // CHECK2-NEXT:    [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
3059 // CHECK2-NEXT:    [[TMP3:%.*]] = call i8* @llvm.stacksave()
3060 // CHECK2-NEXT:    store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8
3061 // CHECK2-NEXT:    [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]
3062 // CHECK2-NEXT:    [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2
3063 // CHECK2-NEXT:    store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8
3064 // CHECK2-NEXT:    [[TMP5:%.*]] = load i32, i32* [[B]], align 4
3065 // CHECK2-NEXT:    [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32*
3066 // CHECK2-NEXT:    store i32 [[TMP5]], i32* [[CONV]], align 4
3067 // CHECK2-NEXT:    [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8
3068 // CHECK2-NEXT:    [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4
3069 // CHECK2-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 60
3070 // CHECK2-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
3071 // CHECK2:       omp_if.then:
3072 // CHECK2-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
3073 // CHECK2-NEXT:    [[TMP8:%.*]] = mul nuw i64 2, [[TMP2]]
3074 // CHECK2-NEXT:    [[TMP9:%.*]] = mul nuw i64 [[TMP8]], 2
3075 // CHECK2-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
3076 // CHECK2-NEXT:    [[TMP11:%.*]] = bitcast i8** [[TMP10]] to %struct.S1**
3077 // CHECK2-NEXT:    store %struct.S1* [[THIS1]], %struct.S1** [[TMP11]], align 8
3078 // CHECK2-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
3079 // CHECK2-NEXT:    [[TMP13:%.*]] = bitcast i8** [[TMP12]] to double**
3080 // CHECK2-NEXT:    store double* [[A]], double** [[TMP13]], align 8
3081 // CHECK2-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
3082 // CHECK2-NEXT:    store i64 8, i64* [[TMP14]], align 8
3083 // CHECK2-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
3084 // CHECK2-NEXT:    store i8* null, i8** [[TMP15]], align 8
3085 // CHECK2-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
3086 // CHECK2-NEXT:    [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64*
3087 // CHECK2-NEXT:    store i64 [[TMP6]], i64* [[TMP17]], align 8
3088 // CHECK2-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
3089 // CHECK2-NEXT:    [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64*
3090 // CHECK2-NEXT:    store i64 [[TMP6]], i64* [[TMP19]], align 8
3091 // CHECK2-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1
3092 // CHECK2-NEXT:    store i64 4, i64* [[TMP20]], align 8
3093 // CHECK2-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
3094 // CHECK2-NEXT:    store i8* null, i8** [[TMP21]], align 8
3095 // CHECK2-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
3096 // CHECK2-NEXT:    [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i64*
3097 // CHECK2-NEXT:    store i64 2, i64* [[TMP23]], align 8
3098 // CHECK2-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
3099 // CHECK2-NEXT:    [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i64*
3100 // CHECK2-NEXT:    store i64 2, i64* [[TMP25]], align 8
3101 // CHECK2-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2
3102 // CHECK2-NEXT:    store i64 8, i64* [[TMP26]], align 8
3103 // CHECK2-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
3104 // CHECK2-NEXT:    store i8* null, i8** [[TMP27]], align 8
3105 // CHECK2-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
3106 // CHECK2-NEXT:    [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i64*
3107 // CHECK2-NEXT:    store i64 [[TMP2]], i64* [[TMP29]], align 8
3108 // CHECK2-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
3109 // CHECK2-NEXT:    [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i64*
3110 // CHECK2-NEXT:    store i64 [[TMP2]], i64* [[TMP31]], align 8
3111 // CHECK2-NEXT:    [[TMP32:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3
3112 // CHECK2-NEXT:    store i64 8, i64* [[TMP32]], align 8
3113 // CHECK2-NEXT:    [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
3114 // CHECK2-NEXT:    store i8* null, i8** [[TMP33]], align 8
3115 // CHECK2-NEXT:    [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
3116 // CHECK2-NEXT:    [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i16**
3117 // CHECK2-NEXT:    store i16* [[VLA]], i16** [[TMP35]], align 8
3118 // CHECK2-NEXT:    [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
3119 // CHECK2-NEXT:    [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i16**
3120 // CHECK2-NEXT:    store i16* [[VLA]], i16** [[TMP37]], align 8
3121 // CHECK2-NEXT:    [[TMP38:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4
3122 // CHECK2-NEXT:    store i64 [[TMP9]], i64* [[TMP38]], align 8
3123 // CHECK2-NEXT:    [[TMP39:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4
3124 // CHECK2-NEXT:    store i8* null, i8** [[TMP39]], align 8
3125 // CHECK2-NEXT:    [[TMP40:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
3126 // CHECK2-NEXT:    [[TMP41:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
3127 // CHECK2-NEXT:    [[TMP42:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
3128 // CHECK2-NEXT:    call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10)
3129 // CHECK2-NEXT:    [[TMP43:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218.region_id, i32 5, i8** [[TMP40]], i8** [[TMP41]], i64* [[TMP42]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.12, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
3130 // CHECK2-NEXT:    [[TMP44:%.*]] = icmp ne i32 [[TMP43]], 0
3131 // CHECK2-NEXT:    br i1 [[TMP44]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
3132 // CHECK2:       omp_offload.failed:
3133 // CHECK2-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR3]]
3134 // CHECK2-NEXT:    br label [[OMP_OFFLOAD_CONT]]
3135 // CHECK2:       omp_offload.cont:
3136 // CHECK2-NEXT:    br label [[OMP_IF_END:%.*]]
3137 // CHECK2:       omp_if.else:
3138 // CHECK2-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR3]]
3139 // CHECK2-NEXT:    br label [[OMP_IF_END]]
3140 // CHECK2:       omp_if.end:
3141 // CHECK2-NEXT:    [[TMP45:%.*]] = mul nsw i64 1, [[TMP2]]
3142 // CHECK2-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP45]]
3143 // CHECK2-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
3144 // CHECK2-NEXT:    [[TMP46:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2
3145 // CHECK2-NEXT:    [[CONV3:%.*]] = sext i16 [[TMP46]] to i32
3146 // CHECK2-NEXT:    [[TMP47:%.*]] = load i32, i32* [[B]], align 4
3147 // CHECK2-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], [[TMP47]]
3148 // CHECK2-NEXT:    [[TMP48:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
3149 // CHECK2-NEXT:    call void @llvm.stackrestore(i8* [[TMP48]])
3150 // CHECK2-NEXT:    ret i32 [[ADD4]]
3151 //
3152 //
3153 // CHECK2-LABEL: define {{[^@]+}}@_ZL7fstatici
3154 // CHECK2-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
3155 // CHECK2-NEXT:  entry:
3156 // CHECK2-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
3157 // CHECK2-NEXT:    [[A:%.*]] = alloca i32, align 4
3158 // CHECK2-NEXT:    [[AA:%.*]] = alloca i16, align 2
3159 // CHECK2-NEXT:    [[AAA:%.*]] = alloca i8, align 1
3160 // CHECK2-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
3161 // CHECK2-NEXT:    [[N_CASTED:%.*]] = alloca i64, align 8
3162 // CHECK2-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
3163 // CHECK2-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
3164 // CHECK2-NEXT:    [[AAA_CASTED:%.*]] = alloca i64, align 8
3165 // CHECK2-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8
3166 // CHECK2-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8
3167 // CHECK2-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8
3168 // CHECK2-NEXT:    [[TMP:%.*]] = alloca i32, align 4
3169 // CHECK2-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
3170 // CHECK2-NEXT:    [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4
3171 // CHECK2-NEXT:    [[DOTCAPTURE_EXPR_5:%.*]] = alloca i32, align 4
3172 // CHECK2-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
3173 // CHECK2-NEXT:    store i32 0, i32* [[A]], align 4
3174 // CHECK2-NEXT:    store i16 0, i16* [[AA]], align 2
3175 // CHECK2-NEXT:    store i8 0, i8* [[AAA]], align 1
3176 // CHECK2-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
3177 // CHECK2-NEXT:    [[CONV:%.*]] = bitcast i64* [[N_CASTED]] to i32*
3178 // CHECK2-NEXT:    store i32 [[TMP0]], i32* [[CONV]], align 4
3179 // CHECK2-NEXT:    [[TMP1:%.*]] = load i64, i64* [[N_CASTED]], align 8
3180 // CHECK2-NEXT:    [[TMP2:%.*]] = load i32, i32* [[A]], align 4
3181 // CHECK2-NEXT:    [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32*
3182 // CHECK2-NEXT:    store i32 [[TMP2]], i32* [[CONV1]], align 4
3183 // CHECK2-NEXT:    [[TMP3:%.*]] = load i64, i64* [[A_CASTED]], align 8
3184 // CHECK2-NEXT:    [[TMP4:%.*]] = load i16, i16* [[AA]], align 2
3185 // CHECK2-NEXT:    [[CONV2:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
3186 // CHECK2-NEXT:    store i16 [[TMP4]], i16* [[CONV2]], align 2
3187 // CHECK2-NEXT:    [[TMP5:%.*]] = load i64, i64* [[AA_CASTED]], align 8
3188 // CHECK2-NEXT:    [[TMP6:%.*]] = load i8, i8* [[AAA]], align 1
3189 // CHECK2-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
3190 // CHECK2-NEXT:    store i8 [[TMP6]], i8* [[CONV3]], align 1
3191 // CHECK2-NEXT:    [[TMP7:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
3192 // CHECK2-NEXT:    [[TMP8:%.*]] = load i32, i32* [[N_ADDR]], align 4
3193 // CHECK2-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP8]], 50
3194 // CHECK2-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
3195 // CHECK2:       omp_if.then:
3196 // CHECK2-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
3197 // CHECK2-NEXT:    [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64*
3198 // CHECK2-NEXT:    store i64 [[TMP1]], i64* [[TMP10]], align 8
3199 // CHECK2-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
3200 // CHECK2-NEXT:    [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64*
3201 // CHECK2-NEXT:    store i64 [[TMP1]], i64* [[TMP12]], align 8
3202 // CHECK2-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
3203 // CHECK2-NEXT:    store i8* null, i8** [[TMP13]], align 8
3204 // CHECK2-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
3205 // CHECK2-NEXT:    [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64*
3206 // CHECK2-NEXT:    store i64 [[TMP3]], i64* [[TMP15]], align 8
3207 // CHECK2-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
3208 // CHECK2-NEXT:    [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64*
3209 // CHECK2-NEXT:    store i64 [[TMP3]], i64* [[TMP17]], align 8
3210 // CHECK2-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
3211 // CHECK2-NEXT:    store i8* null, i8** [[TMP18]], align 8
3212 // CHECK2-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
3213 // CHECK2-NEXT:    [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64*
3214 // CHECK2-NEXT:    store i64 [[TMP5]], i64* [[TMP20]], align 8
3215 // CHECK2-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
3216 // CHECK2-NEXT:    [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i64*
3217 // CHECK2-NEXT:    store i64 [[TMP5]], i64* [[TMP22]], align 8
3218 // CHECK2-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
3219 // CHECK2-NEXT:    store i8* null, i8** [[TMP23]], align 8
3220 // CHECK2-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
3221 // CHECK2-NEXT:    [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i64*
3222 // CHECK2-NEXT:    store i64 [[TMP7]], i64* [[TMP25]], align 8
3223 // CHECK2-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
3224 // CHECK2-NEXT:    [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64*
3225 // CHECK2-NEXT:    store i64 [[TMP7]], i64* [[TMP27]], align 8
3226 // CHECK2-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
3227 // CHECK2-NEXT:    store i8* null, i8** [[TMP28]], align 8
3228 // CHECK2-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
3229 // CHECK2-NEXT:    [[TMP30:%.*]] = bitcast i8** [[TMP29]] to [10 x i32]**
3230 // CHECK2-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP30]], align 8
3231 // CHECK2-NEXT:    [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
3232 // CHECK2-NEXT:    [[TMP32:%.*]] = bitcast i8** [[TMP31]] to [10 x i32]**
3233 // CHECK2-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP32]], align 8
3234 // CHECK2-NEXT:    [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4
3235 // CHECK2-NEXT:    store i8* null, i8** [[TMP33]], align 8
3236 // CHECK2-NEXT:    [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
3237 // CHECK2-NEXT:    [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
3238 // CHECK2-NEXT:    [[TMP36:%.*]] = load i32, i32* [[A]], align 4
3239 // CHECK2-NEXT:    store i32 [[TMP36]], i32* [[DOTCAPTURE_EXPR_]], align 4
3240 // CHECK2-NEXT:    [[TMP37:%.*]] = load i32, i32* [[N_ADDR]], align 4
3241 // CHECK2-NEXT:    store i32 [[TMP37]], i32* [[DOTCAPTURE_EXPR_4]], align 4
3242 // CHECK2-NEXT:    [[TMP38:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4
3243 // CHECK2-NEXT:    [[TMP39:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
3244 // CHECK2-NEXT:    [[SUB:%.*]] = sub i32 [[TMP38]], [[TMP39]]
3245 // CHECK2-NEXT:    [[SUB6:%.*]] = sub i32 [[SUB]], 1
3246 // CHECK2-NEXT:    [[ADD:%.*]] = add i32 [[SUB6]], 1
3247 // CHECK2-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], 1
3248 // CHECK2-NEXT:    [[SUB7:%.*]] = sub i32 [[DIV]], 1
3249 // CHECK2-NEXT:    store i32 [[SUB7]], i32* [[DOTCAPTURE_EXPR_5]], align 4
3250 // CHECK2-NEXT:    [[TMP40:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4
3251 // CHECK2-NEXT:    [[ADD8:%.*]] = add i32 [[TMP40]], 1
3252 // CHECK2-NEXT:    [[TMP41:%.*]] = zext i32 [[ADD8]] to i64
3253 // CHECK2-NEXT:    call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 [[TMP41]])
3254 // CHECK2-NEXT:    [[TMP42:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200.region_id, i32 5, i8** [[TMP34]], i8** [[TMP35]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes.14, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.15, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
3255 // CHECK2-NEXT:    [[TMP43:%.*]] = icmp ne i32 [[TMP42]], 0
3256 // CHECK2-NEXT:    br i1 [[TMP43]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
3257 // CHECK2:       omp_offload.failed:
3258 // CHECK2-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], i64 [[TMP7]], [10 x i32]* [[B]]) #[[ATTR3]]
3259 // CHECK2-NEXT:    br label [[OMP_OFFLOAD_CONT]]
3260 // CHECK2:       omp_offload.cont:
3261 // CHECK2-NEXT:    br label [[OMP_IF_END:%.*]]
3262 // CHECK2:       omp_if.else:
3263 // CHECK2-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], i64 [[TMP7]], [10 x i32]* [[B]]) #[[ATTR3]]
3264 // CHECK2-NEXT:    br label [[OMP_IF_END]]
3265 // CHECK2:       omp_if.end:
3266 // CHECK2-NEXT:    [[TMP44:%.*]] = load i32, i32* [[A]], align 4
3267 // CHECK2-NEXT:    ret i32 [[TMP44]]
3268 //
3269 //
3270 // CHECK2-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
3271 // CHECK2-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat {
3272 // CHECK2-NEXT:  entry:
3273 // CHECK2-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
3274 // CHECK2-NEXT:    [[A:%.*]] = alloca i32, align 4
3275 // CHECK2-NEXT:    [[AA:%.*]] = alloca i16, align 2
3276 // CHECK2-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
3277 // CHECK2-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
3278 // CHECK2-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
3279 // CHECK2-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8
3280 // CHECK2-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8
3281 // CHECK2-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8
3282 // CHECK2-NEXT:    [[TMP:%.*]] = alloca i32, align 4
3283 // CHECK2-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
3284 // CHECK2-NEXT:    store i32 0, i32* [[A]], align 4
3285 // CHECK2-NEXT:    store i16 0, i16* [[AA]], align 2
3286 // CHECK2-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
3287 // CHECK2-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32*
3288 // CHECK2-NEXT:    store i32 [[TMP0]], i32* [[CONV]], align 4
3289 // CHECK2-NEXT:    [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
3290 // CHECK2-NEXT:    [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
3291 // CHECK2-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
3292 // CHECK2-NEXT:    store i16 [[TMP2]], i16* [[CONV1]], align 2
3293 // CHECK2-NEXT:    [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
3294 // CHECK2-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
3295 // CHECK2-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40
3296 // CHECK2-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
3297 // CHECK2:       omp_if.then:
3298 // CHECK2-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
3299 // CHECK2-NEXT:    [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64*
3300 // CHECK2-NEXT:    store i64 [[TMP1]], i64* [[TMP6]], align 8
3301 // CHECK2-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
3302 // CHECK2-NEXT:    [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64*
3303 // CHECK2-NEXT:    store i64 [[TMP1]], i64* [[TMP8]], align 8
3304 // CHECK2-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
3305 // CHECK2-NEXT:    store i8* null, i8** [[TMP9]], align 8
3306 // CHECK2-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
3307 // CHECK2-NEXT:    [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i64*
3308 // CHECK2-NEXT:    store i64 [[TMP3]], i64* [[TMP11]], align 8
3309 // CHECK2-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
3310 // CHECK2-NEXT:    [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64*
3311 // CHECK2-NEXT:    store i64 [[TMP3]], i64* [[TMP13]], align 8
3312 // CHECK2-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
3313 // CHECK2-NEXT:    store i8* null, i8** [[TMP14]], align 8
3314 // CHECK2-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
3315 // CHECK2-NEXT:    [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]**
3316 // CHECK2-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 8
3317 // CHECK2-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
3318 // CHECK2-NEXT:    [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]**
3319 // CHECK2-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 8
3320 // CHECK2-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
3321 // CHECK2-NEXT:    store i8* null, i8** [[TMP19]], align 8
3322 // CHECK2-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
3323 // CHECK2-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
3324 // CHECK2-NEXT:    call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10)
3325 // CHECK2-NEXT:    [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.17, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.18, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
3326 // CHECK2-NEXT:    [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0
3327 // CHECK2-NEXT:    br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
3328 // CHECK2:       omp_offload.failed:
3329 // CHECK2-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]]
3330 // CHECK2-NEXT:    br label [[OMP_OFFLOAD_CONT]]
3331 // CHECK2:       omp_offload.cont:
3332 // CHECK2-NEXT:    br label [[OMP_IF_END:%.*]]
3333 // CHECK2:       omp_if.else:
3334 // CHECK2-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]]
3335 // CHECK2-NEXT:    br label [[OMP_IF_END]]
3336 // CHECK2:       omp_if.end:
3337 // CHECK2-NEXT:    [[TMP24:%.*]] = load i32, i32* [[A]], align 4
3338 // CHECK2-NEXT:    ret i32 [[TMP24]]
3339 //
3340 //
3341 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218
3342 // CHECK2-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {
3343 // CHECK2-NEXT:  entry:
3344 // CHECK2-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
3345 // CHECK2-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
3346 // CHECK2-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
3347 // CHECK2-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
3348 // CHECK2-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 8
3349 // CHECK2-NEXT:    [[B_CASTED:%.*]] = alloca i64, align 8
3350 // CHECK2-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
3351 // CHECK2-NEXT:    store i64 [[B]], i64* [[B_ADDR]], align 8
3352 // CHECK2-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
3353 // CHECK2-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
3354 // CHECK2-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 8
3355 // CHECK2-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
3356 // CHECK2-NEXT:    [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
3357 // CHECK2-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
3358 // CHECK2-NEXT:    [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
3359 // CHECK2-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
3360 // CHECK2-NEXT:    [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
3361 // CHECK2-NEXT:    [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32*
3362 // CHECK2-NEXT:    store i32 [[TMP4]], i32* [[CONV3]], align 4
3363 // CHECK2-NEXT:    [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
3364 // CHECK2-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]])
3365 // CHECK2-NEXT:    ret void
3366 //
3367 //
3368 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..11
3369 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {
3370 // CHECK2-NEXT:  entry:
3371 // CHECK2-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
3372 // CHECK2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
3373 // CHECK2-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
3374 // CHECK2-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
3375 // CHECK2-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
3376 // CHECK2-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
3377 // CHECK2-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 8
3378 // CHECK2-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
3379 // CHECK2-NEXT:    [[TMP:%.*]] = alloca i32, align 4
3380 // CHECK2-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
3381 // CHECK2-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
3382 // CHECK2-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
3383 // CHECK2-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
3384 // CHECK2-NEXT:    [[I:%.*]] = alloca i32, align 4
3385 // CHECK2-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
3386 // CHECK2-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
3387 // CHECK2-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
3388 // CHECK2-NEXT:    store i64 [[B]], i64* [[B_ADDR]], align 8
3389 // CHECK2-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
3390 // CHECK2-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
3391 // CHECK2-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 8
3392 // CHECK2-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
3393 // CHECK2-NEXT:    [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
3394 // CHECK2-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
3395 // CHECK2-NEXT:    [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
3396 // CHECK2-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
3397 // CHECK2-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
3398 // CHECK2-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
3399 // CHECK2-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
3400 // CHECK2-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
3401 // CHECK2-NEXT:    [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
3402 // CHECK2-NEXT:    [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
3403 // CHECK2-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
3404 // CHECK2-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
3405 // CHECK2-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 9
3406 // CHECK2-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
3407 // CHECK2:       cond.true:
3408 // CHECK2-NEXT:    br label [[COND_END:%.*]]
3409 // CHECK2:       cond.false:
3410 // CHECK2-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
3411 // CHECK2-NEXT:    br label [[COND_END]]
3412 // CHECK2:       cond.end:
3413 // CHECK2-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
3414 // CHECK2-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
3415 // CHECK2-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
3416 // CHECK2-NEXT:    store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
3417 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
3418 // CHECK2:       omp.inner.for.cond:
3419 // CHECK2-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
3420 // CHECK2-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
3421 // CHECK2-NEXT:    [[CMP3:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
3422 // CHECK2-NEXT:    br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
3423 // CHECK2:       omp.inner.for.body:
3424 // CHECK2-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
3425 // CHECK2-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
3426 // CHECK2-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
3427 // CHECK2-NEXT:    store i32 [[ADD]], i32* [[I]], align 4
3428 // CHECK2-NEXT:    [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8
3429 // CHECK2-NEXT:    [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double
3430 // CHECK2-NEXT:    [[ADD5:%.*]] = fadd double [[CONV4]], 1.500000e+00
3431 // CHECK2-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
3432 // CHECK2-NEXT:    store double [[ADD5]], double* [[A]], align 8
3433 // CHECK2-NEXT:    [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
3434 // CHECK2-NEXT:    [[TMP13:%.*]] = load double, double* [[A6]], align 8
3435 // CHECK2-NEXT:    [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00
3436 // CHECK2-NEXT:    store double [[INC]], double* [[A6]], align 8
3437 // CHECK2-NEXT:    [[CONV7:%.*]] = fptosi double [[INC]] to i16
3438 // CHECK2-NEXT:    [[TMP14:%.*]] = mul nsw i64 1, [[TMP2]]
3439 // CHECK2-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP14]]
3440 // CHECK2-NEXT:    [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
3441 // CHECK2-NEXT:    store i16 [[CONV7]], i16* [[ARRAYIDX8]], align 2
3442 // CHECK2-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
3443 // CHECK2:       omp.body.continue:
3444 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
3445 // CHECK2:       omp.inner.for.inc:
3446 // CHECK2-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
3447 // CHECK2-NEXT:    [[ADD9:%.*]] = add nsw i32 [[TMP15]], 1
3448 // CHECK2-NEXT:    store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4
3449 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_COND]]
3450 // CHECK2:       omp.inner.for.end:
3451 // CHECK2-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
3452 // CHECK2:       omp.loop.exit:
3453 // CHECK2-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
3454 // CHECK2-NEXT:    ret void
3455 //
3456 //
3457 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200
3458 // CHECK2-SAME: (i64 [[N:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
3459 // CHECK2-NEXT:  entry:
3460 // CHECK2-NEXT:    [[N_ADDR:%.*]] = alloca i64, align 8
3461 // CHECK2-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
3462 // CHECK2-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
3463 // CHECK2-NEXT:    [[AAA_ADDR:%.*]] = alloca i64, align 8
3464 // CHECK2-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
3465 // CHECK2-NEXT:    [[N_CASTED:%.*]] = alloca i64, align 8
3466 // CHECK2-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
3467 // CHECK2-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
3468 // CHECK2-NEXT:    [[AAA_CASTED:%.*]] = alloca i64, align 8
3469 // CHECK2-NEXT:    store i64 [[N]], i64* [[N_ADDR]], align 8
3470 // CHECK2-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
3471 // CHECK2-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
3472 // CHECK2-NEXT:    store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
3473 // CHECK2-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
3474 // CHECK2-NEXT:    [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
3475 // CHECK2-NEXT:    [[CONV1:%.*]] = bitcast i64* [[A_ADDR]] to i32*
3476 // CHECK2-NEXT:    [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
3477 // CHECK2-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
3478 // CHECK2-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
3479 // CHECK2-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
3480 // CHECK2-NEXT:    [[CONV4:%.*]] = bitcast i64* [[N_CASTED]] to i32*
3481 // CHECK2-NEXT:    store i32 [[TMP1]], i32* [[CONV4]], align 4
3482 // CHECK2-NEXT:    [[TMP2:%.*]] = load i64, i64* [[N_CASTED]], align 8
3483 // CHECK2-NEXT:    [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 8
3484 // CHECK2-NEXT:    [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
3485 // CHECK2-NEXT:    store i32 [[TMP3]], i32* [[CONV5]], align 4
3486 // CHECK2-NEXT:    [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8
3487 // CHECK2-NEXT:    [[TMP5:%.*]] = load i16, i16* [[CONV2]], align 8
3488 // CHECK2-NEXT:    [[CONV6:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
3489 // CHECK2-NEXT:    store i16 [[TMP5]], i16* [[CONV6]], align 2
3490 // CHECK2-NEXT:    [[TMP6:%.*]] = load i64, i64* [[AA_CASTED]], align 8
3491 // CHECK2-NEXT:    [[TMP7:%.*]] = load i8, i8* [[CONV3]], align 8
3492 // CHECK2-NEXT:    [[CONV7:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
3493 // CHECK2-NEXT:    store i8 [[TMP7]], i8* [[CONV7]], align 1
3494 // CHECK2-NEXT:    [[TMP8:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
3495 // CHECK2-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, [10 x i32]*)* @.omp_outlined..13 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]], [10 x i32]* [[TMP0]])
3496 // CHECK2-NEXT:    ret void
3497 //
3498 //
3499 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..13
3500 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
3501 // CHECK2-NEXT:  entry:
3502 // CHECK2-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
3503 // CHECK2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
3504 // CHECK2-NEXT:    [[N_ADDR:%.*]] = alloca i64, align 8
3505 // CHECK2-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
3506 // CHECK2-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
3507 // CHECK2-NEXT:    [[AAA_ADDR:%.*]] = alloca i64, align 8
3508 // CHECK2-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
3509 // CHECK2-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
3510 // CHECK2-NEXT:    [[TMP:%.*]] = alloca i32, align 4
3511 // CHECK2-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
3512 // CHECK2-NEXT:    [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4
3513 // CHECK2-NEXT:    [[DOTCAPTURE_EXPR_5:%.*]] = alloca i32, align 4
3514 // CHECK2-NEXT:    [[I:%.*]] = alloca i32, align 4
3515 // CHECK2-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
3516 // CHECK2-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
3517 // CHECK2-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
3518 // CHECK2-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
3519 // CHECK2-NEXT:    [[I8:%.*]] = alloca i32, align 4
3520 // CHECK2-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
3521 // CHECK2-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
3522 // CHECK2-NEXT:    store i64 [[N]], i64* [[N_ADDR]], align 8
3523 // CHECK2-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
3524 // CHECK2-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
3525 // CHECK2-NEXT:    store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
3526 // CHECK2-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
3527 // CHECK2-NEXT:    [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
3528 // CHECK2-NEXT:    [[CONV1:%.*]] = bitcast i64* [[A_ADDR]] to i32*
3529 // CHECK2-NEXT:    [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
3530 // CHECK2-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
3531 // CHECK2-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
3532 // CHECK2-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV1]], align 8
3533 // CHECK2-NEXT:    store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
3534 // CHECK2-NEXT:    [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
3535 // CHECK2-NEXT:    store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_4]], align 4
3536 // CHECK2-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4
3537 // CHECK2-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
3538 // CHECK2-NEXT:    [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]]
3539 // CHECK2-NEXT:    [[SUB6:%.*]] = sub i32 [[SUB]], 1
3540 // CHECK2-NEXT:    [[ADD:%.*]] = add i32 [[SUB6]], 1
3541 // CHECK2-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], 1
3542 // CHECK2-NEXT:    [[SUB7:%.*]] = sub i32 [[DIV]], 1
3543 // CHECK2-NEXT:    store i32 [[SUB7]], i32* [[DOTCAPTURE_EXPR_5]], align 4
3544 // CHECK2-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
3545 // CHECK2-NEXT:    store i32 [[TMP5]], i32* [[I]], align 4
3546 // CHECK2-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
3547 // CHECK2-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4
3548 // CHECK2-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]]
3549 // CHECK2-NEXT:    br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
3550 // CHECK2:       omp.precond.then:
3551 // CHECK2-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
3552 // CHECK2-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4
3553 // CHECK2-NEXT:    store i32 [[TMP8]], i32* [[DOTOMP_UB]], align 4
3554 // CHECK2-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
3555 // CHECK2-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
3556 // CHECK2-NEXT:    [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
3557 // CHECK2-NEXT:    [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
3558 // CHECK2-NEXT:    call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
3559 // CHECK2-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
3560 // CHECK2-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4
3561 // CHECK2-NEXT:    [[CMP9:%.*]] = icmp ugt i32 [[TMP11]], [[TMP12]]
3562 // CHECK2-NEXT:    br i1 [[CMP9]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
3563 // CHECK2:       cond.true:
3564 // CHECK2-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4
3565 // CHECK2-NEXT:    br label [[COND_END:%.*]]
3566 // CHECK2:       cond.false:
3567 // CHECK2-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
3568 // CHECK2-NEXT:    br label [[COND_END]]
3569 // CHECK2:       cond.end:
3570 // CHECK2-NEXT:    [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ]
3571 // CHECK2-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
3572 // CHECK2-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
3573 // CHECK2-NEXT:    store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4
3574 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
3575 // CHECK2:       omp.inner.for.cond:
3576 // CHECK2-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
3577 // CHECK2-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
3578 // CHECK2-NEXT:    [[ADD10:%.*]] = add i32 [[TMP17]], 1
3579 // CHECK2-NEXT:    [[CMP11:%.*]] = icmp ult i32 [[TMP16]], [[ADD10]]
3580 // CHECK2-NEXT:    br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
3581 // CHECK2:       omp.inner.for.body:
3582 // CHECK2-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
3583 // CHECK2-NEXT:    [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
3584 // CHECK2-NEXT:    [[MUL:%.*]] = mul i32 [[TMP19]], 1
3585 // CHECK2-NEXT:    [[ADD12:%.*]] = add i32 [[TMP18]], [[MUL]]
3586 // CHECK2-NEXT:    store i32 [[ADD12]], i32* [[I8]], align 4
3587 // CHECK2-NEXT:    [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 8
3588 // CHECK2-NEXT:    [[ADD13:%.*]] = add nsw i32 [[TMP20]], 1
3589 // CHECK2-NEXT:    store i32 [[ADD13]], i32* [[CONV1]], align 8
3590 // CHECK2-NEXT:    [[TMP21:%.*]] = load i16, i16* [[CONV2]], align 8
3591 // CHECK2-NEXT:    [[CONV14:%.*]] = sext i16 [[TMP21]] to i32
3592 // CHECK2-NEXT:    [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1
3593 // CHECK2-NEXT:    [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16
3594 // CHECK2-NEXT:    store i16 [[CONV16]], i16* [[CONV2]], align 8
3595 // CHECK2-NEXT:    [[TMP22:%.*]] = load i8, i8* [[CONV3]], align 8
3596 // CHECK2-NEXT:    [[CONV17:%.*]] = sext i8 [[TMP22]] to i32
3597 // CHECK2-NEXT:    [[ADD18:%.*]] = add nsw i32 [[CONV17]], 1
3598 // CHECK2-NEXT:    [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8
3599 // CHECK2-NEXT:    store i8 [[CONV19]], i8* [[CONV3]], align 8
3600 // CHECK2-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
3601 // CHECK2-NEXT:    [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
3602 // CHECK2-NEXT:    [[ADD20:%.*]] = add nsw i32 [[TMP23]], 1
3603 // CHECK2-NEXT:    store i32 [[ADD20]], i32* [[ARRAYIDX]], align 4
3604 // CHECK2-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
3605 // CHECK2:       omp.body.continue:
3606 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
3607 // CHECK2:       omp.inner.for.inc:
3608 // CHECK2-NEXT:    [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
3609 // CHECK2-NEXT:    [[ADD21:%.*]] = add i32 [[TMP24]], 1
3610 // CHECK2-NEXT:    store i32 [[ADD21]], i32* [[DOTOMP_IV]], align 4
3611 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_COND]]
3612 // CHECK2:       omp.inner.for.end:
3613 // CHECK2-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
3614 // CHECK2:       omp.loop.exit:
3615 // CHECK2-NEXT:    [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
3616 // CHECK2-NEXT:    [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4
3617 // CHECK2-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]])
3618 // CHECK2-NEXT:    br label [[OMP_PRECOND_END]]
3619 // CHECK2:       omp.precond.end:
3620 // CHECK2-NEXT:    ret void
3621 //
3622 //
3623 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183
3624 // CHECK2-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
3625 // CHECK2-NEXT:  entry:
3626 // CHECK2-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
3627 // CHECK2-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
3628 // CHECK2-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
3629 // CHECK2-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
3630 // CHECK2-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
3631 // CHECK2-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
3632 // CHECK2-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
3633 // CHECK2-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
3634 // CHECK2-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
3635 // CHECK2-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
3636 // CHECK2-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
3637 // CHECK2-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
3638 // CHECK2-NEXT:    [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
3639 // CHECK2-NEXT:    store i32 [[TMP1]], i32* [[CONV2]], align 4
3640 // CHECK2-NEXT:    [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
3641 // CHECK2-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
3642 // CHECK2-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
3643 // CHECK2-NEXT:    store i16 [[TMP3]], i16* [[CONV3]], align 2
3644 // CHECK2-NEXT:    [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
3645 // CHECK2-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]])
3646 // CHECK2-NEXT:    ret void
3647 //
3648 //
3649 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..16
3650 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
3651 // CHECK2-NEXT:  entry:
3652 // CHECK2-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
3653 // CHECK2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
3654 // CHECK2-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
3655 // CHECK2-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
3656 // CHECK2-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
3657 // CHECK2-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
3658 // CHECK2-NEXT:    [[TMP:%.*]] = alloca i32, align 4
3659 // CHECK2-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
3660 // CHECK2-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
3661 // CHECK2-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
3662 // CHECK2-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
3663 // CHECK2-NEXT:    [[I:%.*]] = alloca i32, align 4
3664 // CHECK2-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
3665 // CHECK2-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
3666 // CHECK2-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
3667 // CHECK2-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
3668 // CHECK2-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
3669 // CHECK2-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
3670 // CHECK2-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
3671 // CHECK2-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
3672 // CHECK2-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
3673 // CHECK2-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
3674 // CHECK2-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
3675 // CHECK2-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
3676 // CHECK2-NEXT:    [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
3677 // CHECK2-NEXT:    [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
3678 // CHECK2-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
3679 // CHECK2-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
3680 // CHECK2-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9
3681 // CHECK2-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
3682 // CHECK2:       cond.true:
3683 // CHECK2-NEXT:    br label [[COND_END:%.*]]
3684 // CHECK2:       cond.false:
3685 // CHECK2-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
3686 // CHECK2-NEXT:    br label [[COND_END]]
3687 // CHECK2:       cond.end:
3688 // CHECK2-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
3689 // CHECK2-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
3690 // CHECK2-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
3691 // CHECK2-NEXT:    store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
3692 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
3693 // CHECK2:       omp.inner.for.cond:
3694 // CHECK2-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
3695 // CHECK2-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
3696 // CHECK2-NEXT:    [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
3697 // CHECK2-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
3698 // CHECK2:       omp.inner.for.body:
3699 // CHECK2-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
3700 // CHECK2-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
3701 // CHECK2-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
3702 // CHECK2-NEXT:    store i32 [[ADD]], i32* [[I]], align 4
3703 // CHECK2-NEXT:    [[TMP9:%.*]] = load i32, i32* [[CONV]], align 8
3704 // CHECK2-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1
3705 // CHECK2-NEXT:    store i32 [[ADD3]], i32* [[CONV]], align 8
3706 // CHECK2-NEXT:    [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 8
3707 // CHECK2-NEXT:    [[CONV4:%.*]] = sext i16 [[TMP10]] to i32
3708 // CHECK2-NEXT:    [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
3709 // CHECK2-NEXT:    [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
3710 // CHECK2-NEXT:    store i16 [[CONV6]], i16* [[CONV1]], align 8
3711 // CHECK2-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
3712 // CHECK2-NEXT:    [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
3713 // CHECK2-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1
3714 // CHECK2-NEXT:    store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4
3715 // CHECK2-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
3716 // CHECK2:       omp.body.continue:
3717 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
3718 // CHECK2:       omp.inner.for.inc:
3719 // CHECK2-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
3720 // CHECK2-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP12]], 1
3721 // CHECK2-NEXT:    store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4
3722 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_COND]]
3723 // CHECK2:       omp.inner.for.end:
3724 // CHECK2-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
3725 // CHECK2:       omp.loop.exit:
3726 // CHECK2-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
3727 // CHECK2-NEXT:    ret void
3728 //
3729 //
3730 // CHECK2-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
3731 // CHECK2-SAME: () #[[ATTR4]] {
3732 // CHECK2-NEXT:  entry:
3733 // CHECK2-NEXT:    call void @__tgt_register_requires(i64 1)
3734 // CHECK2-NEXT:    ret void
3735 //
3736 //
3737 // CHECK3-LABEL: define {{[^@]+}}@_Z3fooi
3738 // CHECK3-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] {
3739 // CHECK3-NEXT:  entry:
3740 // CHECK3-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
3741 // CHECK3-NEXT:    [[A:%.*]] = alloca i32, align 4
3742 // CHECK3-NEXT:    [[AA:%.*]] = alloca i16, align 2
3743 // CHECK3-NEXT:    [[B:%.*]] = alloca [10 x float], align 4
3744 // CHECK3-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 4
3745 // CHECK3-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 4
3746 // CHECK3-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 8
3747 // CHECK3-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i32, align 4
3748 // CHECK3-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4
3749 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
3750 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
3751 // CHECK3-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
3752 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
3753 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR__CASTED3:%.*]] = alloca i32, align 4
3754 // CHECK3-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4
3755 // CHECK3-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4
3756 // CHECK3-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4
3757 // CHECK3-NEXT:    [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4
3758 // CHECK3-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
3759 // CHECK3-NEXT:    [[AA_CASTED4:%.*]] = alloca i32, align 4
3760 // CHECK3-NEXT:    [[DOTOFFLOAD_BASEPTRS6:%.*]] = alloca [1 x i8*], align 4
3761 // CHECK3-NEXT:    [[DOTOFFLOAD_PTRS7:%.*]] = alloca [1 x i8*], align 4
3762 // CHECK3-NEXT:    [[DOTOFFLOAD_MAPPERS8:%.*]] = alloca [1 x i8*], align 4
3763 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 4
3764 // CHECK3-NEXT:    [[A_CASTED9:%.*]] = alloca i32, align 4
3765 // CHECK3-NEXT:    [[AA_CASTED10:%.*]] = alloca i32, align 4
3766 // CHECK3-NEXT:    [[DOTOFFLOAD_BASEPTRS12:%.*]] = alloca [2 x i8*], align 4
3767 // CHECK3-NEXT:    [[DOTOFFLOAD_PTRS13:%.*]] = alloca [2 x i8*], align 4
3768 // CHECK3-NEXT:    [[DOTOFFLOAD_MAPPERS14:%.*]] = alloca [2 x i8*], align 4
3769 // CHECK3-NEXT:    [[_TMP15:%.*]] = alloca i32, align 4
3770 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR_18:%.*]] = alloca i32, align 4
3771 // CHECK3-NEXT:    [[A_CASTED19:%.*]] = alloca i32, align 4
3772 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR__CASTED20:%.*]] = alloca i32, align 4
3773 // CHECK3-NEXT:    [[DOTOFFLOAD_BASEPTRS23:%.*]] = alloca [10 x i8*], align 4
3774 // CHECK3-NEXT:    [[DOTOFFLOAD_PTRS24:%.*]] = alloca [10 x i8*], align 4
3775 // CHECK3-NEXT:    [[DOTOFFLOAD_MAPPERS25:%.*]] = alloca [10 x i8*], align 4
3776 // CHECK3-NEXT:    [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 4
3777 // CHECK3-NEXT:    [[_TMP26:%.*]] = alloca i32, align 4
3778 // CHECK3-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]])
3779 // CHECK3-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
3780 // CHECK3-NEXT:    store i32 0, i32* [[A]], align 4
3781 // CHECK3-NEXT:    store i16 0, i16* [[AA]], align 2
3782 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
3783 // CHECK3-NEXT:    [[TMP2:%.*]] = call i8* @llvm.stacksave()
3784 // CHECK3-NEXT:    store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4
3785 // CHECK3-NEXT:    [[VLA:%.*]] = alloca float, i32 [[TMP1]], align 4
3786 // CHECK3-NEXT:    store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
3787 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
3788 // CHECK3-NEXT:    [[TMP4:%.*]] = mul nuw i32 5, [[TMP3]]
3789 // CHECK3-NEXT:    [[VLA1:%.*]] = alloca double, i32 [[TMP4]], align 8
3790 // CHECK3-NEXT:    store i32 [[TMP3]], i32* [[__VLA_EXPR1]], align 4
3791 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
3792 // CHECK3-NEXT:    store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_]], align 4
3793 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, i32* [[A]], align 4
3794 // CHECK3-NEXT:    store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_2]], align 4
3795 // CHECK3-NEXT:    [[TMP7:%.*]] = load i16, i16* [[AA]], align 2
3796 // CHECK3-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
3797 // CHECK3-NEXT:    store i16 [[TMP7]], i16* [[CONV]], align 2
3798 // CHECK3-NEXT:    [[TMP8:%.*]] = load i32, i32* [[AA_CASTED]], align 4
3799 // CHECK3-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
3800 // CHECK3-NEXT:    store i32 [[TMP9]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
3801 // CHECK3-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
3802 // CHECK3-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
3803 // CHECK3-NEXT:    store i32 [[TMP11]], i32* [[DOTCAPTURE_EXPR__CASTED3]], align 4
3804 // CHECK3-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED3]], align 4
3805 // CHECK3-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
3806 // CHECK3-NEXT:    [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i32*
3807 // CHECK3-NEXT:    store i32 [[TMP8]], i32* [[TMP14]], align 4
3808 // CHECK3-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
3809 // CHECK3-NEXT:    [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i32*
3810 // CHECK3-NEXT:    store i32 [[TMP8]], i32* [[TMP16]], align 4
3811 // CHECK3-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
3812 // CHECK3-NEXT:    store i8* null, i8** [[TMP17]], align 4
3813 // CHECK3-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
3814 // CHECK3-NEXT:    [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32*
3815 // CHECK3-NEXT:    store i32 [[TMP10]], i32* [[TMP19]], align 4
3816 // CHECK3-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
3817 // CHECK3-NEXT:    [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32*
3818 // CHECK3-NEXT:    store i32 [[TMP10]], i32* [[TMP21]], align 4
3819 // CHECK3-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
3820 // CHECK3-NEXT:    store i8* null, i8** [[TMP22]], align 4
3821 // CHECK3-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
3822 // CHECK3-NEXT:    [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i32*
3823 // CHECK3-NEXT:    store i32 [[TMP12]], i32* [[TMP24]], align 4
3824 // CHECK3-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
3825 // CHECK3-NEXT:    [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i32*
3826 // CHECK3-NEXT:    store i32 [[TMP12]], i32* [[TMP26]], align 4
3827 // CHECK3-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
3828 // CHECK3-NEXT:    store i8* null, i8** [[TMP27]], align 4
3829 // CHECK3-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
3830 // CHECK3-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
3831 // CHECK3-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 0
3832 // CHECK3-NEXT:    [[TMP31:%.*]] = load i16, i16* [[AA]], align 2
3833 // CHECK3-NEXT:    store i16 [[TMP31]], i16* [[TMP30]], align 4
3834 // CHECK3-NEXT:    [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 1
3835 // CHECK3-NEXT:    [[TMP33:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
3836 // CHECK3-NEXT:    store i32 [[TMP33]], i32* [[TMP32]], align 4
3837 // CHECK3-NEXT:    [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 2
3838 // CHECK3-NEXT:    [[TMP35:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
3839 // CHECK3-NEXT:    store i32 [[TMP35]], i32* [[TMP34]], align 4
3840 // CHECK3-NEXT:    [[TMP36:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 1, i32 72, i32 12, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1)
3841 // CHECK3-NEXT:    [[TMP37:%.*]] = bitcast i8* [[TMP36]] to %struct.kmp_task_t_with_privates*
3842 // CHECK3-NEXT:    [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP37]], i32 0, i32 0
3843 // CHECK3-NEXT:    [[TMP39:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP38]], i32 0, i32 0
3844 // CHECK3-NEXT:    [[TMP40:%.*]] = load i8*, i8** [[TMP39]], align 4
3845 // CHECK3-NEXT:    [[TMP41:%.*]] = bitcast %struct.anon* [[AGG_CAPTURED]] to i8*
3846 // CHECK3-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP40]], i8* align 4 [[TMP41]], i32 12, i1 false)
3847 // CHECK3-NEXT:    [[TMP42:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP37]], i32 0, i32 1
3848 // CHECK3-NEXT:    [[TMP43:%.*]] = bitcast i8* [[TMP40]] to %struct.anon*
3849 // CHECK3-NEXT:    [[TMP44:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 0
3850 // CHECK3-NEXT:    [[TMP45:%.*]] = bitcast [3 x i64]* [[TMP44]] to i8*
3851 // CHECK3-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP45]], i8* align 4 bitcast ([3 x i64]* @.offload_sizes to i8*), i32 24, i1 false)
3852 // CHECK3-NEXT:    [[TMP46:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 1
3853 // CHECK3-NEXT:    [[TMP47:%.*]] = bitcast [3 x i8*]* [[TMP46]] to i8*
3854 // CHECK3-NEXT:    [[TMP48:%.*]] = bitcast i8** [[TMP28]] to i8*
3855 // CHECK3-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP47]], i8* align 4 [[TMP48]], i32 12, i1 false)
3856 // CHECK3-NEXT:    [[TMP49:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 2
3857 // CHECK3-NEXT:    [[TMP50:%.*]] = bitcast [3 x i8*]* [[TMP49]] to i8*
3858 // CHECK3-NEXT:    [[TMP51:%.*]] = bitcast i8** [[TMP29]] to i8*
3859 // CHECK3-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP50]], i8* align 4 [[TMP51]], i32 12, i1 false)
3860 // CHECK3-NEXT:    [[TMP52:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 3
3861 // CHECK3-NEXT:    [[TMP53:%.*]] = load i16, i16* [[AA]], align 2
3862 // CHECK3-NEXT:    store i16 [[TMP53]], i16* [[TMP52]], align 4
3863 // CHECK3-NEXT:    [[TMP54:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i8* [[TMP36]])
3864 // CHECK3-NEXT:    [[TMP55:%.*]] = load i32, i32* [[A]], align 4
3865 // CHECK3-NEXT:    store i32 [[TMP55]], i32* [[A_CASTED]], align 4
3866 // CHECK3-NEXT:    [[TMP56:%.*]] = load i32, i32* [[A_CASTED]], align 4
3867 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l107(i32 [[TMP56]]) #[[ATTR3:[0-9]+]]
3868 // CHECK3-NEXT:    [[TMP57:%.*]] = load i16, i16* [[AA]], align 2
3869 // CHECK3-NEXT:    [[CONV5:%.*]] = bitcast i32* [[AA_CASTED4]] to i16*
3870 // CHECK3-NEXT:    store i16 [[TMP57]], i16* [[CONV5]], align 2
3871 // CHECK3-NEXT:    [[TMP58:%.*]] = load i32, i32* [[AA_CASTED4]], align 4
3872 // CHECK3-NEXT:    [[TMP59:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0
3873 // CHECK3-NEXT:    [[TMP60:%.*]] = bitcast i8** [[TMP59]] to i32*
3874 // CHECK3-NEXT:    store i32 [[TMP58]], i32* [[TMP60]], align 4
3875 // CHECK3-NEXT:    [[TMP61:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0
3876 // CHECK3-NEXT:    [[TMP62:%.*]] = bitcast i8** [[TMP61]] to i32*
3877 // CHECK3-NEXT:    store i32 [[TMP58]], i32* [[TMP62]], align 4
3878 // CHECK3-NEXT:    [[TMP63:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS8]], i32 0, i32 0
3879 // CHECK3-NEXT:    store i8* null, i8** [[TMP63]], align 4
3880 // CHECK3-NEXT:    [[TMP64:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0
3881 // CHECK3-NEXT:    [[TMP65:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0
3882 // CHECK3-NEXT:    call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10)
3883 // CHECK3-NEXT:    [[TMP66:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113.region_id, i32 1, i8** [[TMP64]], i8** [[TMP65]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.4, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.5, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
3884 // CHECK3-NEXT:    [[TMP67:%.*]] = icmp ne i32 [[TMP66]], 0
3885 // CHECK3-NEXT:    br i1 [[TMP67]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
3886 // CHECK3:       omp_offload.failed:
3887 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113(i32 [[TMP58]]) #[[ATTR3]]
3888 // CHECK3-NEXT:    br label [[OMP_OFFLOAD_CONT]]
3889 // CHECK3:       omp_offload.cont:
3890 // CHECK3-NEXT:    [[TMP68:%.*]] = load i32, i32* [[A]], align 4
3891 // CHECK3-NEXT:    store i32 [[TMP68]], i32* [[A_CASTED9]], align 4
3892 // CHECK3-NEXT:    [[TMP69:%.*]] = load i32, i32* [[A_CASTED9]], align 4
3893 // CHECK3-NEXT:    [[TMP70:%.*]] = load i16, i16* [[AA]], align 2
3894 // CHECK3-NEXT:    [[CONV11:%.*]] = bitcast i32* [[AA_CASTED10]] to i16*
3895 // CHECK3-NEXT:    store i16 [[TMP70]], i16* [[CONV11]], align 2
3896 // CHECK3-NEXT:    [[TMP71:%.*]] = load i32, i32* [[AA_CASTED10]], align 4
3897 // CHECK3-NEXT:    [[TMP72:%.*]] = load i32, i32* [[N_ADDR]], align 4
3898 // CHECK3-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP72]], 10
3899 // CHECK3-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
3900 // CHECK3:       omp_if.then:
3901 // CHECK3-NEXT:    [[TMP73:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS12]], i32 0, i32 0
3902 // CHECK3-NEXT:    [[TMP74:%.*]] = bitcast i8** [[TMP73]] to i32*
3903 // CHECK3-NEXT:    store i32 [[TMP69]], i32* [[TMP74]], align 4
3904 // CHECK3-NEXT:    [[TMP75:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS13]], i32 0, i32 0
3905 // CHECK3-NEXT:    [[TMP76:%.*]] = bitcast i8** [[TMP75]] to i32*
3906 // CHECK3-NEXT:    store i32 [[TMP69]], i32* [[TMP76]], align 4
3907 // CHECK3-NEXT:    [[TMP77:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS14]], i32 0, i32 0
3908 // CHECK3-NEXT:    store i8* null, i8** [[TMP77]], align 4
3909 // CHECK3-NEXT:    [[TMP78:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS12]], i32 0, i32 1
3910 // CHECK3-NEXT:    [[TMP79:%.*]] = bitcast i8** [[TMP78]] to i32*
3911 // CHECK3-NEXT:    store i32 [[TMP71]], i32* [[TMP79]], align 4
3912 // CHECK3-NEXT:    [[TMP80:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS13]], i32 0, i32 1
3913 // CHECK3-NEXT:    [[TMP81:%.*]] = bitcast i8** [[TMP80]] to i32*
3914 // CHECK3-NEXT:    store i32 [[TMP71]], i32* [[TMP81]], align 4
3915 // CHECK3-NEXT:    [[TMP82:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS14]], i32 0, i32 1
3916 // CHECK3-NEXT:    store i8* null, i8** [[TMP82]], align 4
3917 // CHECK3-NEXT:    [[TMP83:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS12]], i32 0, i32 0
3918 // CHECK3-NEXT:    [[TMP84:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS13]], i32 0, i32 0
3919 // CHECK3-NEXT:    call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10)
3920 // CHECK3-NEXT:    [[TMP85:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120.region_id, i32 2, i8** [[TMP83]], i8** [[TMP84]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.7, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.8, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
3921 // CHECK3-NEXT:    [[TMP86:%.*]] = icmp ne i32 [[TMP85]], 0
3922 // CHECK3-NEXT:    br i1 [[TMP86]], label [[OMP_OFFLOAD_FAILED16:%.*]], label [[OMP_OFFLOAD_CONT17:%.*]]
3923 // CHECK3:       omp_offload.failed16:
3924 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120(i32 [[TMP69]], i32 [[TMP71]]) #[[ATTR3]]
3925 // CHECK3-NEXT:    br label [[OMP_OFFLOAD_CONT17]]
3926 // CHECK3:       omp_offload.cont17:
3927 // CHECK3-NEXT:    br label [[OMP_IF_END:%.*]]
3928 // CHECK3:       omp_if.else:
3929 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120(i32 [[TMP69]], i32 [[TMP71]]) #[[ATTR3]]
3930 // CHECK3-NEXT:    br label [[OMP_IF_END]]
3931 // CHECK3:       omp_if.end:
3932 // CHECK3-NEXT:    [[TMP87:%.*]] = load i32, i32* [[N_ADDR]], align 4
3933 // CHECK3-NEXT:    store i32 [[TMP87]], i32* [[DOTCAPTURE_EXPR_18]], align 4
3934 // CHECK3-NEXT:    [[TMP88:%.*]] = load i32, i32* [[A]], align 4
3935 // CHECK3-NEXT:    store i32 [[TMP88]], i32* [[A_CASTED19]], align 4
3936 // CHECK3-NEXT:    [[TMP89:%.*]] = load i32, i32* [[A_CASTED19]], align 4
3937 // CHECK3-NEXT:    [[TMP90:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_18]], align 4
3938 // CHECK3-NEXT:    store i32 [[TMP90]], i32* [[DOTCAPTURE_EXPR__CASTED20]], align 4
3939 // CHECK3-NEXT:    [[TMP91:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED20]], align 4
3940 // CHECK3-NEXT:    [[TMP92:%.*]] = load i32, i32* [[N_ADDR]], align 4
3941 // CHECK3-NEXT:    [[CMP21:%.*]] = icmp sgt i32 [[TMP92]], 20
3942 // CHECK3-NEXT:    br i1 [[CMP21]], label [[OMP_IF_THEN22:%.*]], label [[OMP_IF_ELSE29:%.*]]
3943 // CHECK3:       omp_if.then22:
3944 // CHECK3-NEXT:    [[TMP93:%.*]] = mul nuw i32 [[TMP1]], 4
3945 // CHECK3-NEXT:    [[TMP94:%.*]] = sext i32 [[TMP93]] to i64
3946 // CHECK3-NEXT:    [[TMP95:%.*]] = mul nuw i32 5, [[TMP3]]
3947 // CHECK3-NEXT:    [[TMP96:%.*]] = mul nuw i32 [[TMP95]], 8
3948 // CHECK3-NEXT:    [[TMP97:%.*]] = sext i32 [[TMP96]] to i64
3949 // CHECK3-NEXT:    [[TMP98:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS23]], i32 0, i32 0
3950 // CHECK3-NEXT:    [[TMP99:%.*]] = bitcast i8** [[TMP98]] to i32*
3951 // CHECK3-NEXT:    store i32 [[TMP89]], i32* [[TMP99]], align 4
3952 // CHECK3-NEXT:    [[TMP100:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS24]], i32 0, i32 0
3953 // CHECK3-NEXT:    [[TMP101:%.*]] = bitcast i8** [[TMP100]] to i32*
3954 // CHECK3-NEXT:    store i32 [[TMP89]], i32* [[TMP101]], align 4
3955 // CHECK3-NEXT:    [[TMP102:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
3956 // CHECK3-NEXT:    store i64 4, i64* [[TMP102]], align 4
3957 // CHECK3-NEXT:    [[TMP103:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS25]], i32 0, i32 0
3958 // CHECK3-NEXT:    store i8* null, i8** [[TMP103]], align 4
3959 // CHECK3-NEXT:    [[TMP104:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS23]], i32 0, i32 1
3960 // CHECK3-NEXT:    [[TMP105:%.*]] = bitcast i8** [[TMP104]] to [10 x float]**
3961 // CHECK3-NEXT:    store [10 x float]* [[B]], [10 x float]** [[TMP105]], align 4
3962 // CHECK3-NEXT:    [[TMP106:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS24]], i32 0, i32 1
3963 // CHECK3-NEXT:    [[TMP107:%.*]] = bitcast i8** [[TMP106]] to [10 x float]**
3964 // CHECK3-NEXT:    store [10 x float]* [[B]], [10 x float]** [[TMP107]], align 4
3965 // CHECK3-NEXT:    [[TMP108:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1
3966 // CHECK3-NEXT:    store i64 40, i64* [[TMP108]], align 4
3967 // CHECK3-NEXT:    [[TMP109:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS25]], i32 0, i32 1
3968 // CHECK3-NEXT:    store i8* null, i8** [[TMP109]], align 4
3969 // CHECK3-NEXT:    [[TMP110:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS23]], i32 0, i32 2
3970 // CHECK3-NEXT:    [[TMP111:%.*]] = bitcast i8** [[TMP110]] to i32*
3971 // CHECK3-NEXT:    store i32 [[TMP1]], i32* [[TMP111]], align 4
3972 // CHECK3-NEXT:    [[TMP112:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS24]], i32 0, i32 2
3973 // CHECK3-NEXT:    [[TMP113:%.*]] = bitcast i8** [[TMP112]] to i32*
3974 // CHECK3-NEXT:    store i32 [[TMP1]], i32* [[TMP113]], align 4
3975 // CHECK3-NEXT:    [[TMP114:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2
3976 // CHECK3-NEXT:    store i64 4, i64* [[TMP114]], align 4
3977 // CHECK3-NEXT:    [[TMP115:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS25]], i32 0, i32 2
3978 // CHECK3-NEXT:    store i8* null, i8** [[TMP115]], align 4
3979 // CHECK3-NEXT:    [[TMP116:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS23]], i32 0, i32 3
3980 // CHECK3-NEXT:    [[TMP117:%.*]] = bitcast i8** [[TMP116]] to float**
3981 // CHECK3-NEXT:    store float* [[VLA]], float** [[TMP117]], align 4
3982 // CHECK3-NEXT:    [[TMP118:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS24]], i32 0, i32 3
3983 // CHECK3-NEXT:    [[TMP119:%.*]] = bitcast i8** [[TMP118]] to float**
3984 // CHECK3-NEXT:    store float* [[VLA]], float** [[TMP119]], align 4
3985 // CHECK3-NEXT:    [[TMP120:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3
3986 // CHECK3-NEXT:    store i64 [[TMP94]], i64* [[TMP120]], align 4
3987 // CHECK3-NEXT:    [[TMP121:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS25]], i32 0, i32 3
3988 // CHECK3-NEXT:    store i8* null, i8** [[TMP121]], align 4
3989 // CHECK3-NEXT:    [[TMP122:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS23]], i32 0, i32 4
3990 // CHECK3-NEXT:    [[TMP123:%.*]] = bitcast i8** [[TMP122]] to [5 x [10 x double]]**
3991 // CHECK3-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP123]], align 4
3992 // CHECK3-NEXT:    [[TMP124:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS24]], i32 0, i32 4
3993 // CHECK3-NEXT:    [[TMP125:%.*]] = bitcast i8** [[TMP124]] to [5 x [10 x double]]**
3994 // CHECK3-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP125]], align 4
3995 // CHECK3-NEXT:    [[TMP126:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4
3996 // CHECK3-NEXT:    store i64 400, i64* [[TMP126]], align 4
3997 // CHECK3-NEXT:    [[TMP127:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS25]], i32 0, i32 4
3998 // CHECK3-NEXT:    store i8* null, i8** [[TMP127]], align 4
3999 // CHECK3-NEXT:    [[TMP128:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS23]], i32 0, i32 5
4000 // CHECK3-NEXT:    [[TMP129:%.*]] = bitcast i8** [[TMP128]] to i32*
4001 // CHECK3-NEXT:    store i32 5, i32* [[TMP129]], align 4
4002 // CHECK3-NEXT:    [[TMP130:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS24]], i32 0, i32 5
4003 // CHECK3-NEXT:    [[TMP131:%.*]] = bitcast i8** [[TMP130]] to i32*
4004 // CHECK3-NEXT:    store i32 5, i32* [[TMP131]], align 4
4005 // CHECK3-NEXT:    [[TMP132:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 5
4006 // CHECK3-NEXT:    store i64 4, i64* [[TMP132]], align 4
4007 // CHECK3-NEXT:    [[TMP133:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS25]], i32 0, i32 5
4008 // CHECK3-NEXT:    store i8* null, i8** [[TMP133]], align 4
4009 // CHECK3-NEXT:    [[TMP134:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS23]], i32 0, i32 6
4010 // CHECK3-NEXT:    [[TMP135:%.*]] = bitcast i8** [[TMP134]] to i32*
4011 // CHECK3-NEXT:    store i32 [[TMP3]], i32* [[TMP135]], align 4
4012 // CHECK3-NEXT:    [[TMP136:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS24]], i32 0, i32 6
4013 // CHECK3-NEXT:    [[TMP137:%.*]] = bitcast i8** [[TMP136]] to i32*
4014 // CHECK3-NEXT:    store i32 [[TMP3]], i32* [[TMP137]], align 4
4015 // CHECK3-NEXT:    [[TMP138:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 6
4016 // CHECK3-NEXT:    store i64 4, i64* [[TMP138]], align 4
4017 // CHECK3-NEXT:    [[TMP139:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS25]], i32 0, i32 6
4018 // CHECK3-NEXT:    store i8* null, i8** [[TMP139]], align 4
4019 // CHECK3-NEXT:    [[TMP140:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS23]], i32 0, i32 7
4020 // CHECK3-NEXT:    [[TMP141:%.*]] = bitcast i8** [[TMP140]] to double**
4021 // CHECK3-NEXT:    store double* [[VLA1]], double** [[TMP141]], align 4
4022 // CHECK3-NEXT:    [[TMP142:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS24]], i32 0, i32 7
4023 // CHECK3-NEXT:    [[TMP143:%.*]] = bitcast i8** [[TMP142]] to double**
4024 // CHECK3-NEXT:    store double* [[VLA1]], double** [[TMP143]], align 4
4025 // CHECK3-NEXT:    [[TMP144:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7
4026 // CHECK3-NEXT:    store i64 [[TMP97]], i64* [[TMP144]], align 4
4027 // CHECK3-NEXT:    [[TMP145:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS25]], i32 0, i32 7
4028 // CHECK3-NEXT:    store i8* null, i8** [[TMP145]], align 4
4029 // CHECK3-NEXT:    [[TMP146:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS23]], i32 0, i32 8
4030 // CHECK3-NEXT:    [[TMP147:%.*]] = bitcast i8** [[TMP146]] to %struct.TT**
4031 // CHECK3-NEXT:    store %struct.TT* [[D]], %struct.TT** [[TMP147]], align 4
4032 // CHECK3-NEXT:    [[TMP148:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS24]], i32 0, i32 8
4033 // CHECK3-NEXT:    [[TMP149:%.*]] = bitcast i8** [[TMP148]] to %struct.TT**
4034 // CHECK3-NEXT:    store %struct.TT* [[D]], %struct.TT** [[TMP149]], align 4
4035 // CHECK3-NEXT:    [[TMP150:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 8
4036 // CHECK3-NEXT:    store i64 12, i64* [[TMP150]], align 4
4037 // CHECK3-NEXT:    [[TMP151:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS25]], i32 0, i32 8
4038 // CHECK3-NEXT:    store i8* null, i8** [[TMP151]], align 4
4039 // CHECK3-NEXT:    [[TMP152:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS23]], i32 0, i32 9
4040 // CHECK3-NEXT:    [[TMP153:%.*]] = bitcast i8** [[TMP152]] to i32*
4041 // CHECK3-NEXT:    store i32 [[TMP91]], i32* [[TMP153]], align 4
4042 // CHECK3-NEXT:    [[TMP154:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS24]], i32 0, i32 9
4043 // CHECK3-NEXT:    [[TMP155:%.*]] = bitcast i8** [[TMP154]] to i32*
4044 // CHECK3-NEXT:    store i32 [[TMP91]], i32* [[TMP155]], align 4
4045 // CHECK3-NEXT:    [[TMP156:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 9
4046 // CHECK3-NEXT:    store i64 4, i64* [[TMP156]], align 4
4047 // CHECK3-NEXT:    [[TMP157:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS25]], i32 0, i32 9
4048 // CHECK3-NEXT:    store i8* null, i8** [[TMP157]], align 4
4049 // CHECK3-NEXT:    [[TMP158:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS23]], i32 0, i32 0
4050 // CHECK3-NEXT:    [[TMP159:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS24]], i32 0, i32 0
4051 // CHECK3-NEXT:    [[TMP160:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
4052 // CHECK3-NEXT:    call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10)
4053 // CHECK3-NEXT:    [[TMP161:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145.region_id, i32 10, i8** [[TMP158]], i8** [[TMP159]], i64* [[TMP160]], i64* getelementptr inbounds ([10 x i64], [10 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
4054 // CHECK3-NEXT:    [[TMP162:%.*]] = icmp ne i32 [[TMP161]], 0
4055 // CHECK3-NEXT:    br i1 [[TMP162]], label [[OMP_OFFLOAD_FAILED27:%.*]], label [[OMP_OFFLOAD_CONT28:%.*]]
4056 // CHECK3:       omp_offload.failed27:
4057 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145(i32 [[TMP89]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]], i32 [[TMP91]]) #[[ATTR3]]
4058 // CHECK3-NEXT:    br label [[OMP_OFFLOAD_CONT28]]
4059 // CHECK3:       omp_offload.cont28:
4060 // CHECK3-NEXT:    br label [[OMP_IF_END30:%.*]]
4061 // CHECK3:       omp_if.else29:
4062 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145(i32 [[TMP89]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]], i32 [[TMP91]]) #[[ATTR3]]
4063 // CHECK3-NEXT:    br label [[OMP_IF_END30]]
4064 // CHECK3:       omp_if.end30:
4065 // CHECK3-NEXT:    [[TMP163:%.*]] = load i32, i32* [[A]], align 4
4066 // CHECK3-NEXT:    [[TMP164:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
4067 // CHECK3-NEXT:    call void @llvm.stackrestore(i8* [[TMP164]])
4068 // CHECK3-NEXT:    ret i32 [[TMP163]]
4069 //
4070 //
4071 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103
4072 // CHECK3-SAME: (i32 [[AA:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]], i32 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] {
4073 // CHECK3-NEXT:  entry:
4074 // CHECK3-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
4075 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
4076 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4
4077 // CHECK3-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
4078 // CHECK3-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]])
4079 // CHECK3-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
4080 // CHECK3-NEXT:    store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
4081 // CHECK3-NEXT:    store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4
4082 // CHECK3-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
4083 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
4084 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4
4085 // CHECK3-NEXT:    call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
4086 // CHECK3-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
4087 // CHECK3-NEXT:    [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
4088 // CHECK3-NEXT:    store i16 [[TMP3]], i16* [[CONV3]], align 2
4089 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
4090 // CHECK3-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]])
4091 // CHECK3-NEXT:    ret void
4092 //
4093 //
4094 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined.
4095 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] {
4096 // CHECK3-NEXT:  entry:
4097 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
4098 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
4099 // CHECK3-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
4100 // CHECK3-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
4101 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 4
4102 // CHECK3-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
4103 // CHECK3-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
4104 // CHECK3-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
4105 // CHECK3-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
4106 // CHECK3-NEXT:    [[I:%.*]] = alloca i32, align 4
4107 // CHECK3-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
4108 // CHECK3-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
4109 // CHECK3-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
4110 // CHECK3-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
4111 // CHECK3-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
4112 // CHECK3-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
4113 // CHECK3-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
4114 // CHECK3-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
4115 // CHECK3-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
4116 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
4117 // CHECK3-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
4118 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
4119 // CHECK3-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
4120 // CHECK3-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
4121 // CHECK3:       cond.true:
4122 // CHECK3-NEXT:    br label [[COND_END:%.*]]
4123 // CHECK3:       cond.false:
4124 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
4125 // CHECK3-NEXT:    br label [[COND_END]]
4126 // CHECK3:       cond.end:
4127 // CHECK3-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
4128 // CHECK3-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
4129 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
4130 // CHECK3-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
4131 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
4132 // CHECK3:       omp.inner.for.cond:
4133 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
4134 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
4135 // CHECK3-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
4136 // CHECK3-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
4137 // CHECK3:       omp.inner.for.body:
4138 // CHECK3-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
4139 // CHECK3-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
4140 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
4141 // CHECK3-NEXT:    store i32 [[ADD]], i32* [[I]], align 4
4142 // CHECK3-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
4143 // CHECK3:       omp.body.continue:
4144 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
4145 // CHECK3:       omp.inner.for.inc:
4146 // CHECK3-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
4147 // CHECK3-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
4148 // CHECK3-NEXT:    store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4
4149 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND]]
4150 // CHECK3:       omp.inner.for.end:
4151 // CHECK3-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
4152 // CHECK3:       omp.loop.exit:
4153 // CHECK3-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
4154 // CHECK3-NEXT:    ret void
4155 //
4156 //
4157 // CHECK3-LABEL: define {{[^@]+}}@.omp_task_privates_map.
4158 // CHECK3-SAME: (%struct..kmp_privates.t* noalias [[TMP0:%.*]], i16** noalias [[TMP1:%.*]], [3 x i8*]** noalias [[TMP2:%.*]], [3 x i8*]** noalias [[TMP3:%.*]], [3 x i64]** noalias [[TMP4:%.*]]) #[[ATTR4:[0-9]+]] {
4159 // CHECK3-NEXT:  entry:
4160 // CHECK3-NEXT:    [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 4
4161 // CHECK3-NEXT:    [[DOTADDR1:%.*]] = alloca i16**, align 4
4162 // CHECK3-NEXT:    [[DOTADDR2:%.*]] = alloca [3 x i8*]**, align 4
4163 // CHECK3-NEXT:    [[DOTADDR3:%.*]] = alloca [3 x i8*]**, align 4
4164 // CHECK3-NEXT:    [[DOTADDR4:%.*]] = alloca [3 x i64]**, align 4
4165 // CHECK3-NEXT:    store %struct..kmp_privates.t* [[TMP0]], %struct..kmp_privates.t** [[DOTADDR]], align 4
4166 // CHECK3-NEXT:    store i16** [[TMP1]], i16*** [[DOTADDR1]], align 4
4167 // CHECK3-NEXT:    store [3 x i8*]** [[TMP2]], [3 x i8*]*** [[DOTADDR2]], align 4
4168 // CHECK3-NEXT:    store [3 x i8*]** [[TMP3]], [3 x i8*]*** [[DOTADDR3]], align 4
4169 // CHECK3-NEXT:    store [3 x i64]** [[TMP4]], [3 x i64]*** [[DOTADDR4]], align 4
4170 // CHECK3-NEXT:    [[TMP5:%.*]] = load %struct..kmp_privates.t*, %struct..kmp_privates.t** [[DOTADDR]], align 4
4171 // CHECK3-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 0
4172 // CHECK3-NEXT:    [[TMP7:%.*]] = load [3 x i64]**, [3 x i64]*** [[DOTADDR4]], align 4
4173 // CHECK3-NEXT:    store [3 x i64]* [[TMP6]], [3 x i64]** [[TMP7]], align 4
4174 // CHECK3-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 1
4175 // CHECK3-NEXT:    [[TMP9:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR2]], align 4
4176 // CHECK3-NEXT:    store [3 x i8*]* [[TMP8]], [3 x i8*]** [[TMP9]], align 4
4177 // CHECK3-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 2
4178 // CHECK3-NEXT:    [[TMP11:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR3]], align 4
4179 // CHECK3-NEXT:    store [3 x i8*]* [[TMP10]], [3 x i8*]** [[TMP11]], align 4
4180 // CHECK3-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 3
4181 // CHECK3-NEXT:    [[TMP13:%.*]] = load i16**, i16*** [[DOTADDR1]], align 4
4182 // CHECK3-NEXT:    store i16* [[TMP12]], i16** [[TMP13]], align 4
4183 // CHECK3-NEXT:    ret void
4184 //
4185 //
4186 // CHECK3-LABEL: define {{[^@]+}}@.omp_task_entry.
4187 // CHECK3-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] {
4188 // CHECK3-NEXT:  entry:
4189 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
4190 // CHECK3-NEXT:    [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 4
4191 // CHECK3-NEXT:    [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 4
4192 // CHECK3-NEXT:    [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 4
4193 // CHECK3-NEXT:    [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 4
4194 // CHECK3-NEXT:    [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 4
4195 // CHECK3-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca i16*, align 4
4196 // CHECK3-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca [3 x i8*]*, align 4
4197 // CHECK3-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca [3 x i8*]*, align 4
4198 // CHECK3-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca [3 x i64]*, align 4
4199 // CHECK3-NEXT:    [[AA_CASTED_I:%.*]] = alloca i32, align 4
4200 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR__CASTED_I:%.*]] = alloca i32, align 4
4201 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR__CASTED4_I:%.*]] = alloca i32, align 4
4202 // CHECK3-NEXT:    [[DOTADDR:%.*]] = alloca i32, align 4
4203 // CHECK3-NEXT:    [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 4
4204 // CHECK3-NEXT:    store i32 [[TMP0]], i32* [[DOTADDR]], align 4
4205 // CHECK3-NEXT:    store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4
4206 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4
4207 // CHECK3-NEXT:    [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4
4208 // CHECK3-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
4209 // CHECK3-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
4210 // CHECK3-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0
4211 // CHECK3-NEXT:    [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 4
4212 // CHECK3-NEXT:    [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon*
4213 // CHECK3-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1
4214 // CHECK3-NEXT:    [[TMP10:%.*]] = bitcast %struct..kmp_privates.t* [[TMP9]] to i8*
4215 // CHECK3-NEXT:    [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8*
4216 // CHECK3-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META12:![0-9]+]])
4217 // CHECK3-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]])
4218 // CHECK3-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META17:![0-9]+]])
4219 // CHECK3-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]])
4220 // CHECK3-NEXT:    store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !21
4221 // CHECK3-NEXT:    store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 4, !noalias !21
4222 // CHECK3-NEXT:    store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !21
4223 // CHECK3-NEXT:    store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* @.omp_task_privates_map. to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !21
4224 // CHECK3-NEXT:    store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 4, !noalias !21
4225 // CHECK3-NEXT:    store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !21
4226 // CHECK3-NEXT:    [[TMP12:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !21
4227 // CHECK3-NEXT:    [[TMP13:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !21
4228 // CHECK3-NEXT:    [[TMP14:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !21
4229 // CHECK3-NEXT:    [[TMP15:%.*]] = bitcast void (i8*, ...)* [[TMP13]] to void (i8*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)*
4230 // CHECK3-NEXT:    call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]]
4231 // CHECK3-NEXT:    [[TMP16:%.*]] = load i16*, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 4, !noalias !21
4232 // CHECK3-NEXT:    [[TMP17:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 4, !noalias !21
4233 // CHECK3-NEXT:    [[TMP18:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 4, !noalias !21
4234 // CHECK3-NEXT:    [[TMP19:%.*]] = load [3 x i64]*, [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 4, !noalias !21
4235 // CHECK3-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP17]], i32 0, i32 0
4236 // CHECK3-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP18]], i32 0, i32 0
4237 // CHECK3-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[TMP19]], i32 0, i32 0
4238 // CHECK3-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP12]], i32 0, i32 1
4239 // CHECK3-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[TMP12]], i32 0, i32 2
4240 // CHECK3-NEXT:    [[TMP25:%.*]] = load i32, i32* [[TMP23]], align 4
4241 // CHECK3-NEXT:    [[TMP26:%.*]] = load i32, i32* [[TMP24]], align 4
4242 // CHECK3-NEXT:    call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) #[[ATTR3]]
4243 // CHECK3-NEXT:    [[TMP27:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 [[TMP25]], i32 [[TMP26]]) #[[ATTR3]]
4244 // CHECK3-NEXT:    [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0
4245 // CHECK3-NEXT:    br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]]
4246 // CHECK3:       omp_offload.failed.i:
4247 // CHECK3-NEXT:    [[TMP29:%.*]] = load i16, i16* [[TMP16]], align 2
4248 // CHECK3-NEXT:    [[CONV_I:%.*]] = bitcast i32* [[AA_CASTED_I]] to i16*
4249 // CHECK3-NEXT:    store i16 [[TMP29]], i16* [[CONV_I]], align 2, !noalias !21
4250 // CHECK3-NEXT:    [[TMP30:%.*]] = load i32, i32* [[AA_CASTED_I]], align 4, !noalias !21
4251 // CHECK3-NEXT:    [[TMP31:%.*]] = load i32, i32* [[TMP23]], align 4
4252 // CHECK3-NEXT:    store i32 [[TMP31]], i32* [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias !21
4253 // CHECK3-NEXT:    [[TMP32:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias !21
4254 // CHECK3-NEXT:    [[TMP33:%.*]] = load i32, i32* [[TMP24]], align 4
4255 // CHECK3-NEXT:    store i32 [[TMP33]], i32* [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias !21
4256 // CHECK3-NEXT:    [[TMP34:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias !21
4257 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103(i32 [[TMP30]], i32 [[TMP32]], i32 [[TMP34]]) #[[ATTR3]]
4258 // CHECK3-NEXT:    br label [[DOTOMP_OUTLINED__1_EXIT]]
4259 // CHECK3:       .omp_outlined..1.exit:
4260 // CHECK3-NEXT:    ret i32 0
4261 //
4262 //
4263 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l107
4264 // CHECK3-SAME: (i32 [[A:%.*]]) #[[ATTR2]] {
4265 // CHECK3-NEXT:  entry:
4266 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
4267 // CHECK3-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
4268 // CHECK3-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
4269 // CHECK3-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
4270 // CHECK3-NEXT:    store i32 [[TMP0]], i32* [[A_CASTED]], align 4
4271 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
4272 // CHECK3-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]])
4273 // CHECK3-NEXT:    ret void
4274 //
4275 //
4276 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..2
4277 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]]) #[[ATTR2]] {
4278 // CHECK3-NEXT:  entry:
4279 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
4280 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
4281 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
4282 // CHECK3-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
4283 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 4
4284 // CHECK3-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
4285 // CHECK3-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
4286 // CHECK3-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
4287 // CHECK3-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
4288 // CHECK3-NEXT:    [[I:%.*]] = alloca i32, align 4
4289 // CHECK3-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
4290 // CHECK3-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
4291 // CHECK3-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
4292 // CHECK3-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
4293 // CHECK3-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
4294 // CHECK3-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
4295 // CHECK3-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
4296 // CHECK3-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
4297 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
4298 // CHECK3-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
4299 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
4300 // CHECK3-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
4301 // CHECK3-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
4302 // CHECK3:       cond.true:
4303 // CHECK3-NEXT:    br label [[COND_END:%.*]]
4304 // CHECK3:       cond.false:
4305 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
4306 // CHECK3-NEXT:    br label [[COND_END]]
4307 // CHECK3:       cond.end:
4308 // CHECK3-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
4309 // CHECK3-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
4310 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
4311 // CHECK3-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
4312 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
4313 // CHECK3:       omp.inner.for.cond:
4314 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
4315 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
4316 // CHECK3-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
4317 // CHECK3-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
4318 // CHECK3:       omp.inner.for.body:
4319 // CHECK3-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
4320 // CHECK3-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
4321 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
4322 // CHECK3-NEXT:    store i32 [[ADD]], i32* [[I]], align 4
4323 // CHECK3-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
4324 // CHECK3-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
4325 // CHECK3-NEXT:    store i32 [[ADD2]], i32* [[A_ADDR]], align 4
4326 // CHECK3-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
4327 // CHECK3:       omp.body.continue:
4328 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
4329 // CHECK3:       omp.inner.for.inc:
4330 // CHECK3-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
4331 // CHECK3-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1
4332 // CHECK3-NEXT:    store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4
4333 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND]]
4334 // CHECK3:       omp.inner.for.end:
4335 // CHECK3-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
4336 // CHECK3:       omp.loop.exit:
4337 // CHECK3-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
4338 // CHECK3-NEXT:    ret void
4339 //
4340 //
4341 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113
4342 // CHECK3-SAME: (i32 [[AA:%.*]]) #[[ATTR2]] {
4343 // CHECK3-NEXT:  entry:
4344 // CHECK3-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
4345 // CHECK3-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
4346 // CHECK3-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
4347 // CHECK3-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
4348 // CHECK3-NEXT:    [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
4349 // CHECK3-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
4350 // CHECK3-NEXT:    store i16 [[TMP0]], i16* [[CONV1]], align 2
4351 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
4352 // CHECK3-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP1]])
4353 // CHECK3-NEXT:    ret void
4354 //
4355 //
4356 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..3
4357 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] {
4358 // CHECK3-NEXT:  entry:
4359 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
4360 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
4361 // CHECK3-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
4362 // CHECK3-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
4363 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 4
4364 // CHECK3-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
4365 // CHECK3-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
4366 // CHECK3-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
4367 // CHECK3-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
4368 // CHECK3-NEXT:    [[I:%.*]] = alloca i32, align 4
4369 // CHECK3-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
4370 // CHECK3-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
4371 // CHECK3-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
4372 // CHECK3-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
4373 // CHECK3-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
4374 // CHECK3-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
4375 // CHECK3-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
4376 // CHECK3-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
4377 // CHECK3-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
4378 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
4379 // CHECK3-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
4380 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
4381 // CHECK3-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
4382 // CHECK3-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
4383 // CHECK3:       cond.true:
4384 // CHECK3-NEXT:    br label [[COND_END:%.*]]
4385 // CHECK3:       cond.false:
4386 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
4387 // CHECK3-NEXT:    br label [[COND_END]]
4388 // CHECK3:       cond.end:
4389 // CHECK3-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
4390 // CHECK3-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
4391 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
4392 // CHECK3-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
4393 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
4394 // CHECK3:       omp.inner.for.cond:
4395 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
4396 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
4397 // CHECK3-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
4398 // CHECK3-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
4399 // CHECK3:       omp.inner.for.body:
4400 // CHECK3-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
4401 // CHECK3-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
4402 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
4403 // CHECK3-NEXT:    store i32 [[ADD]], i32* [[I]], align 4
4404 // CHECK3-NEXT:    [[TMP8:%.*]] = load i16, i16* [[CONV]], align 4
4405 // CHECK3-NEXT:    [[CONV2:%.*]] = sext i16 [[TMP8]] to i32
4406 // CHECK3-NEXT:    [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
4407 // CHECK3-NEXT:    [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
4408 // CHECK3-NEXT:    store i16 [[CONV4]], i16* [[CONV]], align 4
4409 // CHECK3-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
4410 // CHECK3:       omp.body.continue:
4411 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
4412 // CHECK3:       omp.inner.for.inc:
4413 // CHECK3-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
4414 // CHECK3-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP9]], 1
4415 // CHECK3-NEXT:    store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4
4416 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND]]
4417 // CHECK3:       omp.inner.for.end:
4418 // CHECK3-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
4419 // CHECK3:       omp.loop.exit:
4420 // CHECK3-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
4421 // CHECK3-NEXT:    ret void
4422 //
4423 //
4424 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120
4425 // CHECK3-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] {
4426 // CHECK3-NEXT:  entry:
4427 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
4428 // CHECK3-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
4429 // CHECK3-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
4430 // CHECK3-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
4431 // CHECK3-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
4432 // CHECK3-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
4433 // CHECK3-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
4434 // CHECK3-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
4435 // CHECK3-NEXT:    store i32 [[TMP0]], i32* [[A_CASTED]], align 4
4436 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
4437 // CHECK3-NEXT:    [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
4438 // CHECK3-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
4439 // CHECK3-NEXT:    store i16 [[TMP2]], i16* [[CONV1]], align 2
4440 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
4441 // CHECK3-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]])
4442 // CHECK3-NEXT:    ret void
4443 //
4444 //
4445 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..6
4446 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] {
4447 // CHECK3-NEXT:  entry:
4448 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
4449 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
4450 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
4451 // CHECK3-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
4452 // CHECK3-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
4453 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 4
4454 // CHECK3-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
4455 // CHECK3-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
4456 // CHECK3-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
4457 // CHECK3-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
4458 // CHECK3-NEXT:    [[I:%.*]] = alloca i32, align 4
4459 // CHECK3-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
4460 // CHECK3-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
4461 // CHECK3-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
4462 // CHECK3-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
4463 // CHECK3-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
4464 // CHECK3-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
4465 // CHECK3-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
4466 // CHECK3-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
4467 // CHECK3-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
4468 // CHECK3-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
4469 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
4470 // CHECK3-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
4471 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
4472 // CHECK3-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
4473 // CHECK3-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
4474 // CHECK3:       cond.true:
4475 // CHECK3-NEXT:    br label [[COND_END:%.*]]
4476 // CHECK3:       cond.false:
4477 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
4478 // CHECK3-NEXT:    br label [[COND_END]]
4479 // CHECK3:       cond.end:
4480 // CHECK3-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
4481 // CHECK3-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
4482 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
4483 // CHECK3-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
4484 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
4485 // CHECK3:       omp.inner.for.cond:
4486 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
4487 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
4488 // CHECK3-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
4489 // CHECK3-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
4490 // CHECK3:       omp.inner.for.body:
4491 // CHECK3-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
4492 // CHECK3-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
4493 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
4494 // CHECK3-NEXT:    store i32 [[ADD]], i32* [[I]], align 4
4495 // CHECK3-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
4496 // CHECK3-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
4497 // CHECK3-NEXT:    store i32 [[ADD2]], i32* [[A_ADDR]], align 4
4498 // CHECK3-NEXT:    [[TMP9:%.*]] = load i16, i16* [[CONV]], align 4
4499 // CHECK3-NEXT:    [[CONV3:%.*]] = sext i16 [[TMP9]] to i32
4500 // CHECK3-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
4501 // CHECK3-NEXT:    [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
4502 // CHECK3-NEXT:    store i16 [[CONV5]], i16* [[CONV]], align 4
4503 // CHECK3-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
4504 // CHECK3:       omp.body.continue:
4505 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
4506 // CHECK3:       omp.inner.for.inc:
4507 // CHECK3-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
4508 // CHECK3-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP10]], 1
4509 // CHECK3-NEXT:    store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4
4510 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND]]
4511 // CHECK3:       omp.inner.for.end:
4512 // CHECK3-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
4513 // CHECK3:       omp.loop.exit:
4514 // CHECK3-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
4515 // CHECK3-NEXT:    ret void
4516 //
4517 //
4518 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145
4519 // CHECK3-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] {
4520 // CHECK3-NEXT:  entry:
4521 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
4522 // CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
4523 // CHECK3-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
4524 // CHECK3-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 4
4525 // CHECK3-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
4526 // CHECK3-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
4527 // CHECK3-NEXT:    [[VLA_ADDR4:%.*]] = alloca i32, align 4
4528 // CHECK3-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 4
4529 // CHECK3-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
4530 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
4531 // CHECK3-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
4532 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
4533 // CHECK3-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
4534 // CHECK3-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
4535 // CHECK3-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
4536 // CHECK3-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 4
4537 // CHECK3-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
4538 // CHECK3-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
4539 // CHECK3-NEXT:    store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
4540 // CHECK3-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 4
4541 // CHECK3-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
4542 // CHECK3-NEXT:    store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
4543 // CHECK3-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
4544 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
4545 // CHECK3-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
4546 // CHECK3-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
4547 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
4548 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
4549 // CHECK3-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
4550 // CHECK3-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
4551 // CHECK3-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
4552 // CHECK3-NEXT:    store i32 [[TMP8]], i32* [[A_CASTED]], align 4
4553 // CHECK3-NEXT:    [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4
4554 // CHECK3-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
4555 // CHECK3-NEXT:    store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
4556 // CHECK3-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
4557 // CHECK3-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*, i32)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i32 [[TMP11]])
4558 // CHECK3-NEXT:    ret void
4559 //
4560 //
4561 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..9
4562 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] {
4563 // CHECK3-NEXT:  entry:
4564 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
4565 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
4566 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
4567 // CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
4568 // CHECK3-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
4569 // CHECK3-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 4
4570 // CHECK3-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
4571 // CHECK3-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
4572 // CHECK3-NEXT:    [[VLA_ADDR4:%.*]] = alloca i32, align 4
4573 // CHECK3-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 4
4574 // CHECK3-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
4575 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
4576 // CHECK3-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
4577 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 4
4578 // CHECK3-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
4579 // CHECK3-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
4580 // CHECK3-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
4581 // CHECK3-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
4582 // CHECK3-NEXT:    [[I:%.*]] = alloca i32, align 4
4583 // CHECK3-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
4584 // CHECK3-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
4585 // CHECK3-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
4586 // CHECK3-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
4587 // CHECK3-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
4588 // CHECK3-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 4
4589 // CHECK3-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
4590 // CHECK3-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
4591 // CHECK3-NEXT:    store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
4592 // CHECK3-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 4
4593 // CHECK3-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
4594 // CHECK3-NEXT:    store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
4595 // CHECK3-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
4596 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
4597 // CHECK3-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
4598 // CHECK3-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
4599 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
4600 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
4601 // CHECK3-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
4602 // CHECK3-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
4603 // CHECK3-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
4604 // CHECK3-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
4605 // CHECK3-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
4606 // CHECK3-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
4607 // CHECK3-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
4608 // CHECK3-NEXT:    [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
4609 // CHECK3-NEXT:    [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
4610 // CHECK3-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
4611 // CHECK3-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
4612 // CHECK3:       omp.dispatch.cond:
4613 // CHECK3-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
4614 // CHECK3-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 9
4615 // CHECK3-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
4616 // CHECK3:       cond.true:
4617 // CHECK3-NEXT:    br label [[COND_END:%.*]]
4618 // CHECK3:       cond.false:
4619 // CHECK3-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
4620 // CHECK3-NEXT:    br label [[COND_END]]
4621 // CHECK3:       cond.end:
4622 // CHECK3-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
4623 // CHECK3-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
4624 // CHECK3-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
4625 // CHECK3-NEXT:    store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
4626 // CHECK3-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
4627 // CHECK3-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
4628 // CHECK3-NEXT:    [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
4629 // CHECK3-NEXT:    br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
4630 // CHECK3:       omp.dispatch.body:
4631 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
4632 // CHECK3:       omp.inner.for.cond:
4633 // CHECK3-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
4634 // CHECK3-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !22
4635 // CHECK3-NEXT:    [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
4636 // CHECK3-NEXT:    br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
4637 // CHECK3:       omp.inner.for.body:
4638 // CHECK3-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
4639 // CHECK3-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
4640 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
4641 // CHECK3-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !22
4642 // CHECK3-NEXT:    [[TMP19:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !22
4643 // CHECK3-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP19]], 1
4644 // CHECK3-NEXT:    store i32 [[ADD7]], i32* [[A_ADDR]], align 4, !llvm.access.group !22
4645 // CHECK3-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2
4646 // CHECK3-NEXT:    [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !22
4647 // CHECK3-NEXT:    [[CONV:%.*]] = fpext float [[TMP20]] to double
4648 // CHECK3-NEXT:    [[ADD8:%.*]] = fadd double [[CONV]], 1.000000e+00
4649 // CHECK3-NEXT:    [[CONV9:%.*]] = fptrunc double [[ADD8]] to float
4650 // CHECK3-NEXT:    store float [[CONV9]], float* [[ARRAYIDX]], align 4, !llvm.access.group !22
4651 // CHECK3-NEXT:    [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3
4652 // CHECK3-NEXT:    [[TMP21:%.*]] = load float, float* [[ARRAYIDX10]], align 4, !llvm.access.group !22
4653 // CHECK3-NEXT:    [[CONV11:%.*]] = fpext float [[TMP21]] to double
4654 // CHECK3-NEXT:    [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00
4655 // CHECK3-NEXT:    [[CONV13:%.*]] = fptrunc double [[ADD12]] to float
4656 // CHECK3-NEXT:    store float [[CONV13]], float* [[ARRAYIDX10]], align 4, !llvm.access.group !22
4657 // CHECK3-NEXT:    [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1
4658 // CHECK3-NEXT:    [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX14]], i32 0, i32 2
4659 // CHECK3-NEXT:    [[TMP22:%.*]] = load double, double* [[ARRAYIDX15]], align 8, !llvm.access.group !22
4660 // CHECK3-NEXT:    [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00
4661 // CHECK3-NEXT:    store double [[ADD16]], double* [[ARRAYIDX15]], align 8, !llvm.access.group !22
4662 // CHECK3-NEXT:    [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]]
4663 // CHECK3-NEXT:    [[ARRAYIDX17:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP23]]
4664 // CHECK3-NEXT:    [[ARRAYIDX18:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX17]], i32 3
4665 // CHECK3-NEXT:    [[TMP24:%.*]] = load double, double* [[ARRAYIDX18]], align 8, !llvm.access.group !22
4666 // CHECK3-NEXT:    [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00
4667 // CHECK3-NEXT:    store double [[ADD19]], double* [[ARRAYIDX18]], align 8, !llvm.access.group !22
4668 // CHECK3-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0
4669 // CHECK3-NEXT:    [[TMP25:%.*]] = load i64, i64* [[X]], align 4, !llvm.access.group !22
4670 // CHECK3-NEXT:    [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1
4671 // CHECK3-NEXT:    store i64 [[ADD20]], i64* [[X]], align 4, !llvm.access.group !22
4672 // CHECK3-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1
4673 // CHECK3-NEXT:    [[TMP26:%.*]] = load i8, i8* [[Y]], align 4, !llvm.access.group !22
4674 // CHECK3-NEXT:    [[CONV21:%.*]] = sext i8 [[TMP26]] to i32
4675 // CHECK3-NEXT:    [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1
4676 // CHECK3-NEXT:    [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8
4677 // CHECK3-NEXT:    store i8 [[CONV23]], i8* [[Y]], align 4, !llvm.access.group !22
4678 // CHECK3-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
4679 // CHECK3:       omp.body.continue:
4680 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
4681 // CHECK3:       omp.inner.for.inc:
4682 // CHECK3-NEXT:    [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
4683 // CHECK3-NEXT:    [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1
4684 // CHECK3-NEXT:    store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
4685 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]]
4686 // CHECK3:       omp.inner.for.end:
4687 // CHECK3-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
4688 // CHECK3:       omp.dispatch.inc:
4689 // CHECK3-NEXT:    [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
4690 // CHECK3-NEXT:    [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
4691 // CHECK3-NEXT:    [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]
4692 // CHECK3-NEXT:    store i32 [[ADD25]], i32* [[DOTOMP_LB]], align 4
4693 // CHECK3-NEXT:    [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
4694 // CHECK3-NEXT:    [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
4695 // CHECK3-NEXT:    [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]]
4696 // CHECK3-NEXT:    store i32 [[ADD26]], i32* [[DOTOMP_UB]], align 4
4697 // CHECK3-NEXT:    br label [[OMP_DISPATCH_COND]]
4698 // CHECK3:       omp.dispatch.end:
4699 // CHECK3-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]])
4700 // CHECK3-NEXT:    ret void
4701 //
4702 //
4703 // CHECK3-LABEL: define {{[^@]+}}@_Z3bari
4704 // CHECK3-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
4705 // CHECK3-NEXT:  entry:
4706 // CHECK3-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
4707 // CHECK3-NEXT:    [[A:%.*]] = alloca i32, align 4
4708 // CHECK3-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4
4709 // CHECK3-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
4710 // CHECK3-NEXT:    store i32 0, i32* [[A]], align 4
4711 // CHECK3-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
4712 // CHECK3-NEXT:    [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]])
4713 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
4714 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
4715 // CHECK3-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
4716 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
4717 // CHECK3-NEXT:    [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]])
4718 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
4719 // CHECK3-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
4720 // CHECK3-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
4721 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
4722 // CHECK3-NEXT:    [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]])
4723 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
4724 // CHECK3-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
4725 // CHECK3-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
4726 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
4727 // CHECK3-NEXT:    [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]])
4728 // CHECK3-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
4729 // CHECK3-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
4730 // CHECK3-NEXT:    store i32 [[ADD6]], i32* [[A]], align 4
4731 // CHECK3-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
4732 // CHECK3-NEXT:    ret i32 [[TMP8]]
4733 //
4734 //
4735 // CHECK3-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
4736 // CHECK3-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 {
4737 // CHECK3-NEXT:  entry:
4738 // CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
4739 // CHECK3-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
4740 // CHECK3-NEXT:    [[B:%.*]] = alloca i32, align 4
4741 // CHECK3-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 4
4742 // CHECK3-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 4
4743 // CHECK3-NEXT:    [[B_CASTED:%.*]] = alloca i32, align 4
4744 // CHECK3-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4
4745 // CHECK3-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4
4746 // CHECK3-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4
4747 // CHECK3-NEXT:    [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 4
4748 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 4
4749 // CHECK3-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
4750 // CHECK3-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
4751 // CHECK3-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
4752 // CHECK3-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
4753 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
4754 // CHECK3-NEXT:    store i32 [[ADD]], i32* [[B]], align 4
4755 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
4756 // CHECK3-NEXT:    [[TMP2:%.*]] = call i8* @llvm.stacksave()
4757 // CHECK3-NEXT:    store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4
4758 // CHECK3-NEXT:    [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]
4759 // CHECK3-NEXT:    [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2
4760 // CHECK3-NEXT:    store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
4761 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, i32* [[B]], align 4
4762 // CHECK3-NEXT:    store i32 [[TMP4]], i32* [[B_CASTED]], align 4
4763 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4
4764 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
4765 // CHECK3-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 60
4766 // CHECK3-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
4767 // CHECK3:       omp_if.then:
4768 // CHECK3-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
4769 // CHECK3-NEXT:    [[TMP7:%.*]] = mul nuw i32 2, [[TMP1]]
4770 // CHECK3-NEXT:    [[TMP8:%.*]] = mul nuw i32 [[TMP7]], 2
4771 // CHECK3-NEXT:    [[TMP9:%.*]] = sext i32 [[TMP8]] to i64
4772 // CHECK3-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
4773 // CHECK3-NEXT:    [[TMP11:%.*]] = bitcast i8** [[TMP10]] to %struct.S1**
4774 // CHECK3-NEXT:    store %struct.S1* [[THIS1]], %struct.S1** [[TMP11]], align 4
4775 // CHECK3-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
4776 // CHECK3-NEXT:    [[TMP13:%.*]] = bitcast i8** [[TMP12]] to double**
4777 // CHECK3-NEXT:    store double* [[A]], double** [[TMP13]], align 4
4778 // CHECK3-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
4779 // CHECK3-NEXT:    store i64 8, i64* [[TMP14]], align 4
4780 // CHECK3-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
4781 // CHECK3-NEXT:    store i8* null, i8** [[TMP15]], align 4
4782 // CHECK3-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
4783 // CHECK3-NEXT:    [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32*
4784 // CHECK3-NEXT:    store i32 [[TMP5]], i32* [[TMP17]], align 4
4785 // CHECK3-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
4786 // CHECK3-NEXT:    [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32*
4787 // CHECK3-NEXT:    store i32 [[TMP5]], i32* [[TMP19]], align 4
4788 // CHECK3-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1
4789 // CHECK3-NEXT:    store i64 4, i64* [[TMP20]], align 4
4790 // CHECK3-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
4791 // CHECK3-NEXT:    store i8* null, i8** [[TMP21]], align 4
4792 // CHECK3-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
4793 // CHECK3-NEXT:    [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i32*
4794 // CHECK3-NEXT:    store i32 2, i32* [[TMP23]], align 4
4795 // CHECK3-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
4796 // CHECK3-NEXT:    [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i32*
4797 // CHECK3-NEXT:    store i32 2, i32* [[TMP25]], align 4
4798 // CHECK3-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2
4799 // CHECK3-NEXT:    store i64 4, i64* [[TMP26]], align 4
4800 // CHECK3-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
4801 // CHECK3-NEXT:    store i8* null, i8** [[TMP27]], align 4
4802 // CHECK3-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
4803 // CHECK3-NEXT:    [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i32*
4804 // CHECK3-NEXT:    store i32 [[TMP1]], i32* [[TMP29]], align 4
4805 // CHECK3-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
4806 // CHECK3-NEXT:    [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i32*
4807 // CHECK3-NEXT:    store i32 [[TMP1]], i32* [[TMP31]], align 4
4808 // CHECK3-NEXT:    [[TMP32:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3
4809 // CHECK3-NEXT:    store i64 4, i64* [[TMP32]], align 4
4810 // CHECK3-NEXT:    [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
4811 // CHECK3-NEXT:    store i8* null, i8** [[TMP33]], align 4
4812 // CHECK3-NEXT:    [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
4813 // CHECK3-NEXT:    [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i16**
4814 // CHECK3-NEXT:    store i16* [[VLA]], i16** [[TMP35]], align 4
4815 // CHECK3-NEXT:    [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
4816 // CHECK3-NEXT:    [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i16**
4817 // CHECK3-NEXT:    store i16* [[VLA]], i16** [[TMP37]], align 4
4818 // CHECK3-NEXT:    [[TMP38:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4
4819 // CHECK3-NEXT:    store i64 [[TMP9]], i64* [[TMP38]], align 4
4820 // CHECK3-NEXT:    [[TMP39:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4
4821 // CHECK3-NEXT:    store i8* null, i8** [[TMP39]], align 4
4822 // CHECK3-NEXT:    [[TMP40:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
4823 // CHECK3-NEXT:    [[TMP41:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
4824 // CHECK3-NEXT:    [[TMP42:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
4825 // CHECK3-NEXT:    call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10)
4826 // CHECK3-NEXT:    [[TMP43:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218.region_id, i32 5, i8** [[TMP40]], i8** [[TMP41]], i64* [[TMP42]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.12, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
4827 // CHECK3-NEXT:    [[TMP44:%.*]] = icmp ne i32 [[TMP43]], 0
4828 // CHECK3-NEXT:    br i1 [[TMP44]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
4829 // CHECK3:       omp_offload.failed:
4830 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR3]]
4831 // CHECK3-NEXT:    br label [[OMP_OFFLOAD_CONT]]
4832 // CHECK3:       omp_offload.cont:
4833 // CHECK3-NEXT:    br label [[OMP_IF_END:%.*]]
4834 // CHECK3:       omp_if.else:
4835 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR3]]
4836 // CHECK3-NEXT:    br label [[OMP_IF_END]]
4837 // CHECK3:       omp_if.end:
4838 // CHECK3-NEXT:    [[TMP45:%.*]] = mul nsw i32 1, [[TMP1]]
4839 // CHECK3-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP45]]
4840 // CHECK3-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
4841 // CHECK3-NEXT:    [[TMP46:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2
4842 // CHECK3-NEXT:    [[CONV:%.*]] = sext i16 [[TMP46]] to i32
4843 // CHECK3-NEXT:    [[TMP47:%.*]] = load i32, i32* [[B]], align 4
4844 // CHECK3-NEXT:    [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP47]]
4845 // CHECK3-NEXT:    [[TMP48:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
4846 // CHECK3-NEXT:    call void @llvm.stackrestore(i8* [[TMP48]])
4847 // CHECK3-NEXT:    ret i32 [[ADD3]]
4848 //
4849 //
4850 // CHECK3-LABEL: define {{[^@]+}}@_ZL7fstatici
4851 // CHECK3-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
4852 // CHECK3-NEXT:  entry:
4853 // CHECK3-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
4854 // CHECK3-NEXT:    [[A:%.*]] = alloca i32, align 4
4855 // CHECK3-NEXT:    [[AA:%.*]] = alloca i16, align 2
4856 // CHECK3-NEXT:    [[AAA:%.*]] = alloca i8, align 1
4857 // CHECK3-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
4858 // CHECK3-NEXT:    [[N_CASTED:%.*]] = alloca i32, align 4
4859 // CHECK3-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
4860 // CHECK3-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
4861 // CHECK3-NEXT:    [[AAA_CASTED:%.*]] = alloca i32, align 4
4862 // CHECK3-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4
4863 // CHECK3-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4
4864 // CHECK3-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4
4865 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 4
4866 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
4867 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
4868 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4
4869 // CHECK3-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
4870 // CHECK3-NEXT:    store i32 0, i32* [[A]], align 4
4871 // CHECK3-NEXT:    store i16 0, i16* [[AA]], align 2
4872 // CHECK3-NEXT:    store i8 0, i8* [[AAA]], align 1
4873 // CHECK3-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
4874 // CHECK3-NEXT:    store i32 [[TMP0]], i32* [[N_CASTED]], align 4
4875 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_CASTED]], align 4
4876 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, i32* [[A]], align 4
4877 // CHECK3-NEXT:    store i32 [[TMP2]], i32* [[A_CASTED]], align 4
4878 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A_CASTED]], align 4
4879 // CHECK3-NEXT:    [[TMP4:%.*]] = load i16, i16* [[AA]], align 2
4880 // CHECK3-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
4881 // CHECK3-NEXT:    store i16 [[TMP4]], i16* [[CONV]], align 2
4882 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, i32* [[AA_CASTED]], align 4
4883 // CHECK3-NEXT:    [[TMP6:%.*]] = load i8, i8* [[AAA]], align 1
4884 // CHECK3-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
4885 // CHECK3-NEXT:    store i8 [[TMP6]], i8* [[CONV1]], align 1
4886 // CHECK3-NEXT:    [[TMP7:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
4887 // CHECK3-NEXT:    [[TMP8:%.*]] = load i32, i32* [[N_ADDR]], align 4
4888 // CHECK3-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP8]], 50
4889 // CHECK3-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
4890 // CHECK3:       omp_if.then:
4891 // CHECK3-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
4892 // CHECK3-NEXT:    [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32*
4893 // CHECK3-NEXT:    store i32 [[TMP1]], i32* [[TMP10]], align 4
4894 // CHECK3-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
4895 // CHECK3-NEXT:    [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32*
4896 // CHECK3-NEXT:    store i32 [[TMP1]], i32* [[TMP12]], align 4
4897 // CHECK3-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
4898 // CHECK3-NEXT:    store i8* null, i8** [[TMP13]], align 4
4899 // CHECK3-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
4900 // CHECK3-NEXT:    [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32*
4901 // CHECK3-NEXT:    store i32 [[TMP3]], i32* [[TMP15]], align 4
4902 // CHECK3-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
4903 // CHECK3-NEXT:    [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32*
4904 // CHECK3-NEXT:    store i32 [[TMP3]], i32* [[TMP17]], align 4
4905 // CHECK3-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
4906 // CHECK3-NEXT:    store i8* null, i8** [[TMP18]], align 4
4907 // CHECK3-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
4908 // CHECK3-NEXT:    [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32*
4909 // CHECK3-NEXT:    store i32 [[TMP5]], i32* [[TMP20]], align 4
4910 // CHECK3-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
4911 // CHECK3-NEXT:    [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i32*
4912 // CHECK3-NEXT:    store i32 [[TMP5]], i32* [[TMP22]], align 4
4913 // CHECK3-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
4914 // CHECK3-NEXT:    store i8* null, i8** [[TMP23]], align 4
4915 // CHECK3-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
4916 // CHECK3-NEXT:    [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i32*
4917 // CHECK3-NEXT:    store i32 [[TMP7]], i32* [[TMP25]], align 4
4918 // CHECK3-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
4919 // CHECK3-NEXT:    [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i32*
4920 // CHECK3-NEXT:    store i32 [[TMP7]], i32* [[TMP27]], align 4
4921 // CHECK3-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
4922 // CHECK3-NEXT:    store i8* null, i8** [[TMP28]], align 4
4923 // CHECK3-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
4924 // CHECK3-NEXT:    [[TMP30:%.*]] = bitcast i8** [[TMP29]] to [10 x i32]**
4925 // CHECK3-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP30]], align 4
4926 // CHECK3-NEXT:    [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
4927 // CHECK3-NEXT:    [[TMP32:%.*]] = bitcast i8** [[TMP31]] to [10 x i32]**
4928 // CHECK3-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP32]], align 4
4929 // CHECK3-NEXT:    [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4
4930 // CHECK3-NEXT:    store i8* null, i8** [[TMP33]], align 4
4931 // CHECK3-NEXT:    [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
4932 // CHECK3-NEXT:    [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
4933 // CHECK3-NEXT:    [[TMP36:%.*]] = load i32, i32* [[A]], align 4
4934 // CHECK3-NEXT:    store i32 [[TMP36]], i32* [[DOTCAPTURE_EXPR_]], align 4
4935 // CHECK3-NEXT:    [[TMP37:%.*]] = load i32, i32* [[N_ADDR]], align 4
4936 // CHECK3-NEXT:    store i32 [[TMP37]], i32* [[DOTCAPTURE_EXPR_2]], align 4
4937 // CHECK3-NEXT:    [[TMP38:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
4938 // CHECK3-NEXT:    [[TMP39:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
4939 // CHECK3-NEXT:    [[SUB:%.*]] = sub i32 [[TMP38]], [[TMP39]]
4940 // CHECK3-NEXT:    [[SUB4:%.*]] = sub i32 [[SUB]], 1
4941 // CHECK3-NEXT:    [[ADD:%.*]] = add i32 [[SUB4]], 1
4942 // CHECK3-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], 1
4943 // CHECK3-NEXT:    [[SUB5:%.*]] = sub i32 [[DIV]], 1
4944 // CHECK3-NEXT:    store i32 [[SUB5]], i32* [[DOTCAPTURE_EXPR_3]], align 4
4945 // CHECK3-NEXT:    [[TMP40:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
4946 // CHECK3-NEXT:    [[ADD6:%.*]] = add i32 [[TMP40]], 1
4947 // CHECK3-NEXT:    [[TMP41:%.*]] = zext i32 [[ADD6]] to i64
4948 // CHECK3-NEXT:    call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 [[TMP41]])
4949 // CHECK3-NEXT:    [[TMP42:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200.region_id, i32 5, i8** [[TMP34]], i8** [[TMP35]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes.14, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.15, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
4950 // CHECK3-NEXT:    [[TMP43:%.*]] = icmp ne i32 [[TMP42]], 0
4951 // CHECK3-NEXT:    br i1 [[TMP43]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
4952 // CHECK3:       omp_offload.failed:
4953 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], i32 [[TMP7]], [10 x i32]* [[B]]) #[[ATTR3]]
4954 // CHECK3-NEXT:    br label [[OMP_OFFLOAD_CONT]]
4955 // CHECK3:       omp_offload.cont:
4956 // CHECK3-NEXT:    br label [[OMP_IF_END:%.*]]
4957 // CHECK3:       omp_if.else:
4958 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], i32 [[TMP7]], [10 x i32]* [[B]]) #[[ATTR3]]
4959 // CHECK3-NEXT:    br label [[OMP_IF_END]]
4960 // CHECK3:       omp_if.end:
4961 // CHECK3-NEXT:    [[TMP44:%.*]] = load i32, i32* [[A]], align 4
4962 // CHECK3-NEXT:    ret i32 [[TMP44]]
4963 //
4964 //
4965 // CHECK3-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
4966 // CHECK3-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat {
4967 // CHECK3-NEXT:  entry:
4968 // CHECK3-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
4969 // CHECK3-NEXT:    [[A:%.*]] = alloca i32, align 4
4970 // CHECK3-NEXT:    [[AA:%.*]] = alloca i16, align 2
4971 // CHECK3-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
4972 // CHECK3-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
4973 // CHECK3-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
4974 // CHECK3-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4
4975 // CHECK3-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4
4976 // CHECK3-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4
4977 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 4
4978 // CHECK3-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
4979 // CHECK3-NEXT:    store i32 0, i32* [[A]], align 4
4980 // CHECK3-NEXT:    store i16 0, i16* [[AA]], align 2
4981 // CHECK3-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
4982 // CHECK3-NEXT:    store i32 [[TMP0]], i32* [[A_CASTED]], align 4
4983 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
4984 // CHECK3-NEXT:    [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
4985 // CHECK3-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
4986 // CHECK3-NEXT:    store i16 [[TMP2]], i16* [[CONV]], align 2
4987 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
4988 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
4989 // CHECK3-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40
4990 // CHECK3-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
4991 // CHECK3:       omp_if.then:
4992 // CHECK3-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
4993 // CHECK3-NEXT:    [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i32*
4994 // CHECK3-NEXT:    store i32 [[TMP1]], i32* [[TMP6]], align 4
4995 // CHECK3-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
4996 // CHECK3-NEXT:    [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32*
4997 // CHECK3-NEXT:    store i32 [[TMP1]], i32* [[TMP8]], align 4
4998 // CHECK3-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
4999 // CHECK3-NEXT:    store i8* null, i8** [[TMP9]], align 4
5000 // CHECK3-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
5001 // CHECK3-NEXT:    [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i32*
5002 // CHECK3-NEXT:    store i32 [[TMP3]], i32* [[TMP11]], align 4
5003 // CHECK3-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
5004 // CHECK3-NEXT:    [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32*
5005 // CHECK3-NEXT:    store i32 [[TMP3]], i32* [[TMP13]], align 4
5006 // CHECK3-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
5007 // CHECK3-NEXT:    store i8* null, i8** [[TMP14]], align 4
5008 // CHECK3-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
5009 // CHECK3-NEXT:    [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]**
5010 // CHECK3-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 4
5011 // CHECK3-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
5012 // CHECK3-NEXT:    [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]**
5013 // CHECK3-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 4
5014 // CHECK3-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
5015 // CHECK3-NEXT:    store i8* null, i8** [[TMP19]], align 4
5016 // CHECK3-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
5017 // CHECK3-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
5018 // CHECK3-NEXT:    call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10)
5019 // CHECK3-NEXT:    [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.17, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.18, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
5020 // CHECK3-NEXT:    [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0
5021 // CHECK3-NEXT:    br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
5022 // CHECK3:       omp_offload.failed:
5023 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]]
5024 // CHECK3-NEXT:    br label [[OMP_OFFLOAD_CONT]]
5025 // CHECK3:       omp_offload.cont:
5026 // CHECK3-NEXT:    br label [[OMP_IF_END:%.*]]
5027 // CHECK3:       omp_if.else:
5028 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]]
5029 // CHECK3-NEXT:    br label [[OMP_IF_END]]
5030 // CHECK3:       omp_if.end:
5031 // CHECK3-NEXT:    [[TMP24:%.*]] = load i32, i32* [[A]], align 4
5032 // CHECK3-NEXT:    ret i32 [[TMP24]]
5033 //
5034 //
5035 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218
5036 // CHECK3-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {
5037 // CHECK3-NEXT:  entry:
5038 // CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
5039 // CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
5040 // CHECK3-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
5041 // CHECK3-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
5042 // CHECK3-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 4
5043 // CHECK3-NEXT:    [[B_CASTED:%.*]] = alloca i32, align 4
5044 // CHECK3-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
5045 // CHECK3-NEXT:    store i32 [[B]], i32* [[B_ADDR]], align 4
5046 // CHECK3-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
5047 // CHECK3-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
5048 // CHECK3-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 4
5049 // CHECK3-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
5050 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
5051 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
5052 // CHECK3-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
5053 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4
5054 // CHECK3-NEXT:    store i32 [[TMP4]], i32* [[B_CASTED]], align 4
5055 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4
5056 // CHECK3-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]])
5057 // CHECK3-NEXT:    ret void
5058 //
5059 //
5060 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..11
5061 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {
5062 // CHECK3-NEXT:  entry:
5063 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
5064 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
5065 // CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
5066 // CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
5067 // CHECK3-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
5068 // CHECK3-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
5069 // CHECK3-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 4
5070 // CHECK3-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
5071 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 4
5072 // CHECK3-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
5073 // CHECK3-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
5074 // CHECK3-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
5075 // CHECK3-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
5076 // CHECK3-NEXT:    [[I:%.*]] = alloca i32, align 4
5077 // CHECK3-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
5078 // CHECK3-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
5079 // CHECK3-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
5080 // CHECK3-NEXT:    store i32 [[B]], i32* [[B_ADDR]], align 4
5081 // CHECK3-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
5082 // CHECK3-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
5083 // CHECK3-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 4
5084 // CHECK3-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
5085 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
5086 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
5087 // CHECK3-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
5088 // CHECK3-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
5089 // CHECK3-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
5090 // CHECK3-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
5091 // CHECK3-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
5092 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
5093 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
5094 // CHECK3-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
5095 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
5096 // CHECK3-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 9
5097 // CHECK3-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
5098 // CHECK3:       cond.true:
5099 // CHECK3-NEXT:    br label [[COND_END:%.*]]
5100 // CHECK3:       cond.false:
5101 // CHECK3-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
5102 // CHECK3-NEXT:    br label [[COND_END]]
5103 // CHECK3:       cond.end:
5104 // CHECK3-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
5105 // CHECK3-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
5106 // CHECK3-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
5107 // CHECK3-NEXT:    store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
5108 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
5109 // CHECK3:       omp.inner.for.cond:
5110 // CHECK3-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
5111 // CHECK3-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
5112 // CHECK3-NEXT:    [[CMP3:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
5113 // CHECK3-NEXT:    br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
5114 // CHECK3:       omp.inner.for.body:
5115 // CHECK3-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
5116 // CHECK3-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
5117 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
5118 // CHECK3-NEXT:    store i32 [[ADD]], i32* [[I]], align 4
5119 // CHECK3-NEXT:    [[TMP12:%.*]] = load i32, i32* [[B_ADDR]], align 4
5120 // CHECK3-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP12]] to double
5121 // CHECK3-NEXT:    [[ADD4:%.*]] = fadd double [[CONV]], 1.500000e+00
5122 // CHECK3-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
5123 // CHECK3-NEXT:    store double [[ADD4]], double* [[A]], align 4
5124 // CHECK3-NEXT:    [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
5125 // CHECK3-NEXT:    [[TMP13:%.*]] = load double, double* [[A5]], align 4
5126 // CHECK3-NEXT:    [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00
5127 // CHECK3-NEXT:    store double [[INC]], double* [[A5]], align 4
5128 // CHECK3-NEXT:    [[CONV6:%.*]] = fptosi double [[INC]] to i16
5129 // CHECK3-NEXT:    [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]]
5130 // CHECK3-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP14]]
5131 // CHECK3-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
5132 // CHECK3-NEXT:    store i16 [[CONV6]], i16* [[ARRAYIDX7]], align 2
5133 // CHECK3-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
5134 // CHECK3:       omp.body.continue:
5135 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
5136 // CHECK3:       omp.inner.for.inc:
5137 // CHECK3-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
5138 // CHECK3-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP15]], 1
5139 // CHECK3-NEXT:    store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4
5140 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND]]
5141 // CHECK3:       omp.inner.for.end:
5142 // CHECK3-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
5143 // CHECK3:       omp.loop.exit:
5144 // CHECK3-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
5145 // CHECK3-NEXT:    ret void
5146 //
5147 //
5148 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200
5149 // CHECK3-SAME: (i32 [[N:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
5150 // CHECK3-NEXT:  entry:
5151 // CHECK3-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
5152 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
5153 // CHECK3-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
5154 // CHECK3-NEXT:    [[AAA_ADDR:%.*]] = alloca i32, align 4
5155 // CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
5156 // CHECK3-NEXT:    [[N_CASTED:%.*]] = alloca i32, align 4
5157 // CHECK3-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
5158 // CHECK3-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
5159 // CHECK3-NEXT:    [[AAA_CASTED:%.*]] = alloca i32, align 4
5160 // CHECK3-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
5161 // CHECK3-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
5162 // CHECK3-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
5163 // CHECK3-NEXT:    store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
5164 // CHECK3-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
5165 // CHECK3-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
5166 // CHECK3-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
5167 // CHECK3-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
5168 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
5169 // CHECK3-NEXT:    store i32 [[TMP1]], i32* [[N_CASTED]], align 4
5170 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_CASTED]], align 4
5171 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4
5172 // CHECK3-NEXT:    store i32 [[TMP3]], i32* [[A_CASTED]], align 4
5173 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4
5174 // CHECK3-NEXT:    [[TMP5:%.*]] = load i16, i16* [[CONV]], align 4
5175 // CHECK3-NEXT:    [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
5176 // CHECK3-NEXT:    store i16 [[TMP5]], i16* [[CONV2]], align 2
5177 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, i32* [[AA_CASTED]], align 4
5178 // CHECK3-NEXT:    [[TMP7:%.*]] = load i8, i8* [[CONV1]], align 4
5179 // CHECK3-NEXT:    [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
5180 // CHECK3-NEXT:    store i8 [[TMP7]], i8* [[CONV3]], align 1
5181 // CHECK3-NEXT:    [[TMP8:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
5182 // CHECK3-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, [10 x i32]*)* @.omp_outlined..13 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP8]], [10 x i32]* [[TMP0]])
5183 // CHECK3-NEXT:    ret void
5184 //
5185 //
5186 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..13
5187 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
5188 // CHECK3-NEXT:  entry:
5189 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
5190 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
5191 // CHECK3-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
5192 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
5193 // CHECK3-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
5194 // CHECK3-NEXT:    [[AAA_ADDR:%.*]] = alloca i32, align 4
5195 // CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
5196 // CHECK3-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
5197 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 4
5198 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
5199 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
5200 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4
5201 // CHECK3-NEXT:    [[I:%.*]] = alloca i32, align 4
5202 // CHECK3-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
5203 // CHECK3-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
5204 // CHECK3-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
5205 // CHECK3-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
5206 // CHECK3-NEXT:    [[I6:%.*]] = alloca i32, align 4
5207 // CHECK3-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
5208 // CHECK3-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
5209 // CHECK3-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
5210 // CHECK3-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
5211 // CHECK3-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
5212 // CHECK3-NEXT:    store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
5213 // CHECK3-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
5214 // CHECK3-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
5215 // CHECK3-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
5216 // CHECK3-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
5217 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
5218 // CHECK3-NEXT:    store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
5219 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
5220 // CHECK3-NEXT:    store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4
5221 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
5222 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
5223 // CHECK3-NEXT:    [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]]
5224 // CHECK3-NEXT:    [[SUB4:%.*]] = sub i32 [[SUB]], 1
5225 // CHECK3-NEXT:    [[ADD:%.*]] = add i32 [[SUB4]], 1
5226 // CHECK3-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], 1
5227 // CHECK3-NEXT:    [[SUB5:%.*]] = sub i32 [[DIV]], 1
5228 // CHECK3-NEXT:    store i32 [[SUB5]], i32* [[DOTCAPTURE_EXPR_3]], align 4
5229 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
5230 // CHECK3-NEXT:    store i32 [[TMP5]], i32* [[I]], align 4
5231 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
5232 // CHECK3-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
5233 // CHECK3-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]]
5234 // CHECK3-NEXT:    br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
5235 // CHECK3:       omp.precond.then:
5236 // CHECK3-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
5237 // CHECK3-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
5238 // CHECK3-NEXT:    store i32 [[TMP8]], i32* [[DOTOMP_UB]], align 4
5239 // CHECK3-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
5240 // CHECK3-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
5241 // CHECK3-NEXT:    [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
5242 // CHECK3-NEXT:    [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
5243 // CHECK3-NEXT:    call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
5244 // CHECK3-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
5245 // CHECK3-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
5246 // CHECK3-NEXT:    [[CMP7:%.*]] = icmp ugt i32 [[TMP11]], [[TMP12]]
5247 // CHECK3-NEXT:    br i1 [[CMP7]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
5248 // CHECK3:       cond.true:
5249 // CHECK3-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
5250 // CHECK3-NEXT:    br label [[COND_END:%.*]]
5251 // CHECK3:       cond.false:
5252 // CHECK3-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
5253 // CHECK3-NEXT:    br label [[COND_END]]
5254 // CHECK3:       cond.end:
5255 // CHECK3-NEXT:    [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ]
5256 // CHECK3-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
5257 // CHECK3-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
5258 // CHECK3-NEXT:    store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4
5259 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
5260 // CHECK3:       omp.inner.for.cond:
5261 // CHECK3-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
5262 // CHECK3-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
5263 // CHECK3-NEXT:    [[ADD8:%.*]] = add i32 [[TMP17]], 1
5264 // CHECK3-NEXT:    [[CMP9:%.*]] = icmp ult i32 [[TMP16]], [[ADD8]]
5265 // CHECK3-NEXT:    br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
5266 // CHECK3:       omp.inner.for.body:
5267 // CHECK3-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
5268 // CHECK3-NEXT:    [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
5269 // CHECK3-NEXT:    [[MUL:%.*]] = mul i32 [[TMP19]], 1
5270 // CHECK3-NEXT:    [[ADD10:%.*]] = add i32 [[TMP18]], [[MUL]]
5271 // CHECK3-NEXT:    store i32 [[ADD10]], i32* [[I6]], align 4
5272 // CHECK3-NEXT:    [[TMP20:%.*]] = load i32, i32* [[A_ADDR]], align 4
5273 // CHECK3-NEXT:    [[ADD11:%.*]] = add nsw i32 [[TMP20]], 1
5274 // CHECK3-NEXT:    store i32 [[ADD11]], i32* [[A_ADDR]], align 4
5275 // CHECK3-NEXT:    [[TMP21:%.*]] = load i16, i16* [[CONV]], align 4
5276 // CHECK3-NEXT:    [[CONV12:%.*]] = sext i16 [[TMP21]] to i32
5277 // CHECK3-NEXT:    [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1
5278 // CHECK3-NEXT:    [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16
5279 // CHECK3-NEXT:    store i16 [[CONV14]], i16* [[CONV]], align 4
5280 // CHECK3-NEXT:    [[TMP22:%.*]] = load i8, i8* [[CONV1]], align 4
5281 // CHECK3-NEXT:    [[CONV15:%.*]] = sext i8 [[TMP22]] to i32
5282 // CHECK3-NEXT:    [[ADD16:%.*]] = add nsw i32 [[CONV15]], 1
5283 // CHECK3-NEXT:    [[CONV17:%.*]] = trunc i32 [[ADD16]] to i8
5284 // CHECK3-NEXT:    store i8 [[CONV17]], i8* [[CONV1]], align 4
5285 // CHECK3-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
5286 // CHECK3-NEXT:    [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
5287 // CHECK3-NEXT:    [[ADD18:%.*]] = add nsw i32 [[TMP23]], 1
5288 // CHECK3-NEXT:    store i32 [[ADD18]], i32* [[ARRAYIDX]], align 4
5289 // CHECK3-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
5290 // CHECK3:       omp.body.continue:
5291 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
5292 // CHECK3:       omp.inner.for.inc:
5293 // CHECK3-NEXT:    [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
5294 // CHECK3-NEXT:    [[ADD19:%.*]] = add i32 [[TMP24]], 1
5295 // CHECK3-NEXT:    store i32 [[ADD19]], i32* [[DOTOMP_IV]], align 4
5296 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND]]
5297 // CHECK3:       omp.inner.for.end:
5298 // CHECK3-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
5299 // CHECK3:       omp.loop.exit:
5300 // CHECK3-NEXT:    [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
5301 // CHECK3-NEXT:    [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4
5302 // CHECK3-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]])
5303 // CHECK3-NEXT:    br label [[OMP_PRECOND_END]]
5304 // CHECK3:       omp.precond.end:
5305 // CHECK3-NEXT:    ret void
5306 //
5307 //
5308 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183
5309 // CHECK3-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
5310 // CHECK3-NEXT:  entry:
5311 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
5312 // CHECK3-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
5313 // CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
5314 // CHECK3-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
5315 // CHECK3-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
5316 // CHECK3-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
5317 // CHECK3-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
5318 // CHECK3-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
5319 // CHECK3-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
5320 // CHECK3-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
5321 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
5322 // CHECK3-NEXT:    store i32 [[TMP1]], i32* [[A_CASTED]], align 4
5323 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
5324 // CHECK3-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
5325 // CHECK3-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
5326 // CHECK3-NEXT:    store i16 [[TMP3]], i16* [[CONV1]], align 2
5327 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
5328 // CHECK3-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]])
5329 // CHECK3-NEXT:    ret void
5330 //
5331 //
5332 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..16
5333 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
5334 // CHECK3-NEXT:  entry:
5335 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
5336 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
5337 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
5338 // CHECK3-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
5339 // CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
5340 // CHECK3-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
5341 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 4
5342 // CHECK3-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
5343 // CHECK3-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
5344 // CHECK3-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
5345 // CHECK3-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
5346 // CHECK3-NEXT:    [[I:%.*]] = alloca i32, align 4
5347 // CHECK3-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
5348 // CHECK3-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
5349 // CHECK3-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
5350 // CHECK3-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
5351 // CHECK3-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
5352 // CHECK3-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
5353 // CHECK3-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
5354 // CHECK3-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
5355 // CHECK3-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
5356 // CHECK3-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
5357 // CHECK3-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
5358 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
5359 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
5360 // CHECK3-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
5361 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
5362 // CHECK3-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9
5363 // CHECK3-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
5364 // CHECK3:       cond.true:
5365 // CHECK3-NEXT:    br label [[COND_END:%.*]]
5366 // CHECK3:       cond.false:
5367 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
5368 // CHECK3-NEXT:    br label [[COND_END]]
5369 // CHECK3:       cond.end:
5370 // CHECK3-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
5371 // CHECK3-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
5372 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
5373 // CHECK3-NEXT:    store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
5374 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
5375 // CHECK3:       omp.inner.for.cond:
5376 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
5377 // CHECK3-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
5378 // CHECK3-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
5379 // CHECK3-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
5380 // CHECK3:       omp.inner.for.body:
5381 // CHECK3-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
5382 // CHECK3-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
5383 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
5384 // CHECK3-NEXT:    store i32 [[ADD]], i32* [[I]], align 4
5385 // CHECK3-NEXT:    [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4
5386 // CHECK3-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
5387 // CHECK3-NEXT:    store i32 [[ADD2]], i32* [[A_ADDR]], align 4
5388 // CHECK3-NEXT:    [[TMP10:%.*]] = load i16, i16* [[CONV]], align 4
5389 // CHECK3-NEXT:    [[CONV3:%.*]] = sext i16 [[TMP10]] to i32
5390 // CHECK3-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
5391 // CHECK3-NEXT:    [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
5392 // CHECK3-NEXT:    store i16 [[CONV5]], i16* [[CONV]], align 4
5393 // CHECK3-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
5394 // CHECK3-NEXT:    [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
5395 // CHECK3-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1
5396 // CHECK3-NEXT:    store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4
5397 // CHECK3-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
5398 // CHECK3:       omp.body.continue:
5399 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
5400 // CHECK3:       omp.inner.for.inc:
5401 // CHECK3-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
5402 // CHECK3-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP12]], 1
5403 // CHECK3-NEXT:    store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4
5404 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND]]
5405 // CHECK3:       omp.inner.for.end:
5406 // CHECK3-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
5407 // CHECK3:       omp.loop.exit:
5408 // CHECK3-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
5409 // CHECK3-NEXT:    ret void
5410 //
5411 //
5412 // CHECK3-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
5413 // CHECK3-SAME: () #[[ATTR4]] {
5414 // CHECK3-NEXT:  entry:
5415 // CHECK3-NEXT:    call void @__tgt_register_requires(i64 1)
5416 // CHECK3-NEXT:    ret void
5417 //
5418 //
5419 // CHECK4-LABEL: define {{[^@]+}}@_Z3fooi
5420 // CHECK4-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] {
5421 // CHECK4-NEXT:  entry:
5422 // CHECK4-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
5423 // CHECK4-NEXT:    [[A:%.*]] = alloca i32, align 4
5424 // CHECK4-NEXT:    [[AA:%.*]] = alloca i16, align 2
5425 // CHECK4-NEXT:    [[B:%.*]] = alloca [10 x float], align 4
5426 // CHECK4-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 4
5427 // CHECK4-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 4
5428 // CHECK4-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 8
5429 // CHECK4-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i32, align 4
5430 // CHECK4-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4
5431 // CHECK4-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
5432 // CHECK4-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
5433 // CHECK4-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
5434 // CHECK4-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
5435 // CHECK4-NEXT:    [[DOTCAPTURE_EXPR__CASTED3:%.*]] = alloca i32, align 4
5436 // CHECK4-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4
5437 // CHECK4-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4
5438 // CHECK4-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4
5439 // CHECK4-NEXT:    [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4
5440 // CHECK4-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
5441 // CHECK4-NEXT:    [[AA_CASTED4:%.*]] = alloca i32, align 4
5442 // CHECK4-NEXT:    [[DOTOFFLOAD_BASEPTRS6:%.*]] = alloca [1 x i8*], align 4
5443 // CHECK4-NEXT:    [[DOTOFFLOAD_PTRS7:%.*]] = alloca [1 x i8*], align 4
5444 // CHECK4-NEXT:    [[DOTOFFLOAD_MAPPERS8:%.*]] = alloca [1 x i8*], align 4
5445 // CHECK4-NEXT:    [[TMP:%.*]] = alloca i32, align 4
5446 // CHECK4-NEXT:    [[A_CASTED9:%.*]] = alloca i32, align 4
5447 // CHECK4-NEXT:    [[AA_CASTED10:%.*]] = alloca i32, align 4
5448 // CHECK4-NEXT:    [[DOTOFFLOAD_BASEPTRS12:%.*]] = alloca [2 x i8*], align 4
5449 // CHECK4-NEXT:    [[DOTOFFLOAD_PTRS13:%.*]] = alloca [2 x i8*], align 4
5450 // CHECK4-NEXT:    [[DOTOFFLOAD_MAPPERS14:%.*]] = alloca [2 x i8*], align 4
5451 // CHECK4-NEXT:    [[_TMP15:%.*]] = alloca i32, align 4
5452 // CHECK4-NEXT:    [[DOTCAPTURE_EXPR_18:%.*]] = alloca i32, align 4
5453 // CHECK4-NEXT:    [[A_CASTED19:%.*]] = alloca i32, align 4
5454 // CHECK4-NEXT:    [[DOTCAPTURE_EXPR__CASTED20:%.*]] = alloca i32, align 4
5455 // CHECK4-NEXT:    [[DOTOFFLOAD_BASEPTRS23:%.*]] = alloca [10 x i8*], align 4
5456 // CHECK4-NEXT:    [[DOTOFFLOAD_PTRS24:%.*]] = alloca [10 x i8*], align 4
5457 // CHECK4-NEXT:    [[DOTOFFLOAD_MAPPERS25:%.*]] = alloca [10 x i8*], align 4
5458 // CHECK4-NEXT:    [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 4
5459 // CHECK4-NEXT:    [[_TMP26:%.*]] = alloca i32, align 4
5460 // CHECK4-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]])
5461 // CHECK4-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
5462 // CHECK4-NEXT:    store i32 0, i32* [[A]], align 4
5463 // CHECK4-NEXT:    store i16 0, i16* [[AA]], align 2
5464 // CHECK4-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
5465 // CHECK4-NEXT:    [[TMP2:%.*]] = call i8* @llvm.stacksave()
5466 // CHECK4-NEXT:    store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4
5467 // CHECK4-NEXT:    [[VLA:%.*]] = alloca float, i32 [[TMP1]], align 4
5468 // CHECK4-NEXT:    store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
5469 // CHECK4-NEXT:    [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
5470 // CHECK4-NEXT:    [[TMP4:%.*]] = mul nuw i32 5, [[TMP3]]
5471 // CHECK4-NEXT:    [[VLA1:%.*]] = alloca double, i32 [[TMP4]], align 8
5472 // CHECK4-NEXT:    store i32 [[TMP3]], i32* [[__VLA_EXPR1]], align 4
5473 // CHECK4-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
5474 // CHECK4-NEXT:    store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_]], align 4
5475 // CHECK4-NEXT:    [[TMP6:%.*]] = load i32, i32* [[A]], align 4
5476 // CHECK4-NEXT:    store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_2]], align 4
5477 // CHECK4-NEXT:    [[TMP7:%.*]] = load i16, i16* [[AA]], align 2
5478 // CHECK4-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
5479 // CHECK4-NEXT:    store i16 [[TMP7]], i16* [[CONV]], align 2
5480 // CHECK4-NEXT:    [[TMP8:%.*]] = load i32, i32* [[AA_CASTED]], align 4
5481 // CHECK4-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
5482 // CHECK4-NEXT:    store i32 [[TMP9]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
5483 // CHECK4-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
5484 // CHECK4-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
5485 // CHECK4-NEXT:    store i32 [[TMP11]], i32* [[DOTCAPTURE_EXPR__CASTED3]], align 4
5486 // CHECK4-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED3]], align 4
5487 // CHECK4-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
5488 // CHECK4-NEXT:    [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i32*
5489 // CHECK4-NEXT:    store i32 [[TMP8]], i32* [[TMP14]], align 4
5490 // CHECK4-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
5491 // CHECK4-NEXT:    [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i32*
5492 // CHECK4-NEXT:    store i32 [[TMP8]], i32* [[TMP16]], align 4
5493 // CHECK4-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
5494 // CHECK4-NEXT:    store i8* null, i8** [[TMP17]], align 4
5495 // CHECK4-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
5496 // CHECK4-NEXT:    [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32*
5497 // CHECK4-NEXT:    store i32 [[TMP10]], i32* [[TMP19]], align 4
5498 // CHECK4-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
5499 // CHECK4-NEXT:    [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32*
5500 // CHECK4-NEXT:    store i32 [[TMP10]], i32* [[TMP21]], align 4
5501 // CHECK4-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
5502 // CHECK4-NEXT:    store i8* null, i8** [[TMP22]], align 4
5503 // CHECK4-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
5504 // CHECK4-NEXT:    [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i32*
5505 // CHECK4-NEXT:    store i32 [[TMP12]], i32* [[TMP24]], align 4
5506 // CHECK4-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
5507 // CHECK4-NEXT:    [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i32*
5508 // CHECK4-NEXT:    store i32 [[TMP12]], i32* [[TMP26]], align 4
5509 // CHECK4-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
5510 // CHECK4-NEXT:    store i8* null, i8** [[TMP27]], align 4
5511 // CHECK4-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
5512 // CHECK4-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
5513 // CHECK4-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 0
5514 // CHECK4-NEXT:    [[TMP31:%.*]] = load i16, i16* [[AA]], align 2
5515 // CHECK4-NEXT:    store i16 [[TMP31]], i16* [[TMP30]], align 4
5516 // CHECK4-NEXT:    [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 1
5517 // CHECK4-NEXT:    [[TMP33:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
5518 // CHECK4-NEXT:    store i32 [[TMP33]], i32* [[TMP32]], align 4
5519 // CHECK4-NEXT:    [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 2
5520 // CHECK4-NEXT:    [[TMP35:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
5521 // CHECK4-NEXT:    store i32 [[TMP35]], i32* [[TMP34]], align 4
5522 // CHECK4-NEXT:    [[TMP36:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 1, i32 72, i32 12, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1)
5523 // CHECK4-NEXT:    [[TMP37:%.*]] = bitcast i8* [[TMP36]] to %struct.kmp_task_t_with_privates*
5524 // CHECK4-NEXT:    [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP37]], i32 0, i32 0
5525 // CHECK4-NEXT:    [[TMP39:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP38]], i32 0, i32 0
5526 // CHECK4-NEXT:    [[TMP40:%.*]] = load i8*, i8** [[TMP39]], align 4
5527 // CHECK4-NEXT:    [[TMP41:%.*]] = bitcast %struct.anon* [[AGG_CAPTURED]] to i8*
5528 // CHECK4-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP40]], i8* align 4 [[TMP41]], i32 12, i1 false)
5529 // CHECK4-NEXT:    [[TMP42:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP37]], i32 0, i32 1
5530 // CHECK4-NEXT:    [[TMP43:%.*]] = bitcast i8* [[TMP40]] to %struct.anon*
5531 // CHECK4-NEXT:    [[TMP44:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 0
5532 // CHECK4-NEXT:    [[TMP45:%.*]] = bitcast [3 x i64]* [[TMP44]] to i8*
5533 // CHECK4-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP45]], i8* align 4 bitcast ([3 x i64]* @.offload_sizes to i8*), i32 24, i1 false)
5534 // CHECK4-NEXT:    [[TMP46:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 1
5535 // CHECK4-NEXT:    [[TMP47:%.*]] = bitcast [3 x i8*]* [[TMP46]] to i8*
5536 // CHECK4-NEXT:    [[TMP48:%.*]] = bitcast i8** [[TMP28]] to i8*
5537 // CHECK4-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP47]], i8* align 4 [[TMP48]], i32 12, i1 false)
5538 // CHECK4-NEXT:    [[TMP49:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 2
5539 // CHECK4-NEXT:    [[TMP50:%.*]] = bitcast [3 x i8*]* [[TMP49]] to i8*
5540 // CHECK4-NEXT:    [[TMP51:%.*]] = bitcast i8** [[TMP29]] to i8*
5541 // CHECK4-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP50]], i8* align 4 [[TMP51]], i32 12, i1 false)
5542 // CHECK4-NEXT:    [[TMP52:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 3
5543 // CHECK4-NEXT:    [[TMP53:%.*]] = load i16, i16* [[AA]], align 2
5544 // CHECK4-NEXT:    store i16 [[TMP53]], i16* [[TMP52]], align 4
5545 // CHECK4-NEXT:    [[TMP54:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i8* [[TMP36]])
5546 // CHECK4-NEXT:    [[TMP55:%.*]] = load i32, i32* [[A]], align 4
5547 // CHECK4-NEXT:    store i32 [[TMP55]], i32* [[A_CASTED]], align 4
5548 // CHECK4-NEXT:    [[TMP56:%.*]] = load i32, i32* [[A_CASTED]], align 4
5549 // CHECK4-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l107(i32 [[TMP56]]) #[[ATTR3:[0-9]+]]
5550 // CHECK4-NEXT:    [[TMP57:%.*]] = load i16, i16* [[AA]], align 2
5551 // CHECK4-NEXT:    [[CONV5:%.*]] = bitcast i32* [[AA_CASTED4]] to i16*
5552 // CHECK4-NEXT:    store i16 [[TMP57]], i16* [[CONV5]], align 2
5553 // CHECK4-NEXT:    [[TMP58:%.*]] = load i32, i32* [[AA_CASTED4]], align 4
5554 // CHECK4-NEXT:    [[TMP59:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0
5555 // CHECK4-NEXT:    [[TMP60:%.*]] = bitcast i8** [[TMP59]] to i32*
5556 // CHECK4-NEXT:    store i32 [[TMP58]], i32* [[TMP60]], align 4
5557 // CHECK4-NEXT:    [[TMP61:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0
5558 // CHECK4-NEXT:    [[TMP62:%.*]] = bitcast i8** [[TMP61]] to i32*
5559 // CHECK4-NEXT:    store i32 [[TMP58]], i32* [[TMP62]], align 4
5560 // CHECK4-NEXT:    [[TMP63:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS8]], i32 0, i32 0
5561 // CHECK4-NEXT:    store i8* null, i8** [[TMP63]], align 4
5562 // CHECK4-NEXT:    [[TMP64:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0
5563 // CHECK4-NEXT:    [[TMP65:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0
5564 // CHECK4-NEXT:    call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10)
5565 // CHECK4-NEXT:    [[TMP66:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113.region_id, i32 1, i8** [[TMP64]], i8** [[TMP65]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.4, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.5, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
5566 // CHECK4-NEXT:    [[TMP67:%.*]] = icmp ne i32 [[TMP66]], 0
5567 // CHECK4-NEXT:    br i1 [[TMP67]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
5568 // CHECK4:       omp_offload.failed:
5569 // CHECK4-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113(i32 [[TMP58]]) #[[ATTR3]]
5570 // CHECK4-NEXT:    br label [[OMP_OFFLOAD_CONT]]
5571 // CHECK4:       omp_offload.cont:
5572 // CHECK4-NEXT:    [[TMP68:%.*]] = load i32, i32* [[A]], align 4
5573 // CHECK4-NEXT:    store i32 [[TMP68]], i32* [[A_CASTED9]], align 4
5574 // CHECK4-NEXT:    [[TMP69:%.*]] = load i32, i32* [[A_CASTED9]], align 4
5575 // CHECK4-NEXT:    [[TMP70:%.*]] = load i16, i16* [[AA]], align 2
5576 // CHECK4-NEXT:    [[CONV11:%.*]] = bitcast i32* [[AA_CASTED10]] to i16*
5577 // CHECK4-NEXT:    store i16 [[TMP70]], i16* [[CONV11]], align 2
5578 // CHECK4-NEXT:    [[TMP71:%.*]] = load i32, i32* [[AA_CASTED10]], align 4
5579 // CHECK4-NEXT:    [[TMP72:%.*]] = load i32, i32* [[N_ADDR]], align 4
5580 // CHECK4-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP72]], 10
5581 // CHECK4-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
5582 // CHECK4:       omp_if.then:
5583 // CHECK4-NEXT:    [[TMP73:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS12]], i32 0, i32 0
5584 // CHECK4-NEXT:    [[TMP74:%.*]] = bitcast i8** [[TMP73]] to i32*
5585 // CHECK4-NEXT:    store i32 [[TMP69]], i32* [[TMP74]], align 4
5586 // CHECK4-NEXT:    [[TMP75:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS13]], i32 0, i32 0
5587 // CHECK4-NEXT:    [[TMP76:%.*]] = bitcast i8** [[TMP75]] to i32*
5588 // CHECK4-NEXT:    store i32 [[TMP69]], i32* [[TMP76]], align 4
5589 // CHECK4-NEXT:    [[TMP77:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS14]], i32 0, i32 0
5590 // CHECK4-NEXT:    store i8* null, i8** [[TMP77]], align 4
5591 // CHECK4-NEXT:    [[TMP78:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS12]], i32 0, i32 1
5592 // CHECK4-NEXT:    [[TMP79:%.*]] = bitcast i8** [[TMP78]] to i32*
5593 // CHECK4-NEXT:    store i32 [[TMP71]], i32* [[TMP79]], align 4
5594 // CHECK4-NEXT:    [[TMP80:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS13]], i32 0, i32 1
5595 // CHECK4-NEXT:    [[TMP81:%.*]] = bitcast i8** [[TMP80]] to i32*
5596 // CHECK4-NEXT:    store i32 [[TMP71]], i32* [[TMP81]], align 4
5597 // CHECK4-NEXT:    [[TMP82:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS14]], i32 0, i32 1
5598 // CHECK4-NEXT:    store i8* null, i8** [[TMP82]], align 4
5599 // CHECK4-NEXT:    [[TMP83:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS12]], i32 0, i32 0
5600 // CHECK4-NEXT:    [[TMP84:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS13]], i32 0, i32 0
5601 // CHECK4-NEXT:    call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10)
5602 // CHECK4-NEXT:    [[TMP85:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120.region_id, i32 2, i8** [[TMP83]], i8** [[TMP84]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.7, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.8, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
5603 // CHECK4-NEXT:    [[TMP86:%.*]] = icmp ne i32 [[TMP85]], 0
5604 // CHECK4-NEXT:    br i1 [[TMP86]], label [[OMP_OFFLOAD_FAILED16:%.*]], label [[OMP_OFFLOAD_CONT17:%.*]]
5605 // CHECK4:       omp_offload.failed16:
5606 // CHECK4-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120(i32 [[TMP69]], i32 [[TMP71]]) #[[ATTR3]]
5607 // CHECK4-NEXT:    br label [[OMP_OFFLOAD_CONT17]]
5608 // CHECK4:       omp_offload.cont17:
5609 // CHECK4-NEXT:    br label [[OMP_IF_END:%.*]]
5610 // CHECK4:       omp_if.else:
5611 // CHECK4-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120(i32 [[TMP69]], i32 [[TMP71]]) #[[ATTR3]]
5612 // CHECK4-NEXT:    br label [[OMP_IF_END]]
5613 // CHECK4:       omp_if.end:
5614 // CHECK4-NEXT:    [[TMP87:%.*]] = load i32, i32* [[N_ADDR]], align 4
5615 // CHECK4-NEXT:    store i32 [[TMP87]], i32* [[DOTCAPTURE_EXPR_18]], align 4
5616 // CHECK4-NEXT:    [[TMP88:%.*]] = load i32, i32* [[A]], align 4
5617 // CHECK4-NEXT:    store i32 [[TMP88]], i32* [[A_CASTED19]], align 4
5618 // CHECK4-NEXT:    [[TMP89:%.*]] = load i32, i32* [[A_CASTED19]], align 4
5619 // CHECK4-NEXT:    [[TMP90:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_18]], align 4
5620 // CHECK4-NEXT:    store i32 [[TMP90]], i32* [[DOTCAPTURE_EXPR__CASTED20]], align 4
5621 // CHECK4-NEXT:    [[TMP91:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED20]], align 4
5622 // CHECK4-NEXT:    [[TMP92:%.*]] = load i32, i32* [[N_ADDR]], align 4
5623 // CHECK4-NEXT:    [[CMP21:%.*]] = icmp sgt i32 [[TMP92]], 20
5624 // CHECK4-NEXT:    br i1 [[CMP21]], label [[OMP_IF_THEN22:%.*]], label [[OMP_IF_ELSE29:%.*]]
5625 // CHECK4:       omp_if.then22:
5626 // CHECK4-NEXT:    [[TMP93:%.*]] = mul nuw i32 [[TMP1]], 4
5627 // CHECK4-NEXT:    [[TMP94:%.*]] = sext i32 [[TMP93]] to i64
5628 // CHECK4-NEXT:    [[TMP95:%.*]] = mul nuw i32 5, [[TMP3]]
5629 // CHECK4-NEXT:    [[TMP96:%.*]] = mul nuw i32 [[TMP95]], 8
5630 // CHECK4-NEXT:    [[TMP97:%.*]] = sext i32 [[TMP96]] to i64
5631 // CHECK4-NEXT:    [[TMP98:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS23]], i32 0, i32 0
5632 // CHECK4-NEXT:    [[TMP99:%.*]] = bitcast i8** [[TMP98]] to i32*
5633 // CHECK4-NEXT:    store i32 [[TMP89]], i32* [[TMP99]], align 4
5634 // CHECK4-NEXT:    [[TMP100:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS24]], i32 0, i32 0
5635 // CHECK4-NEXT:    [[TMP101:%.*]] = bitcast i8** [[TMP100]] to i32*
5636 // CHECK4-NEXT:    store i32 [[TMP89]], i32* [[TMP101]], align 4
5637 // CHECK4-NEXT:    [[TMP102:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
5638 // CHECK4-NEXT:    store i64 4, i64* [[TMP102]], align 4
5639 // CHECK4-NEXT:    [[TMP103:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS25]], i32 0, i32 0
5640 // CHECK4-NEXT:    store i8* null, i8** [[TMP103]], align 4
5641 // CHECK4-NEXT:    [[TMP104:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS23]], i32 0, i32 1
5642 // CHECK4-NEXT:    [[TMP105:%.*]] = bitcast i8** [[TMP104]] to [10 x float]**
5643 // CHECK4-NEXT:    store [10 x float]* [[B]], [10 x float]** [[TMP105]], align 4
5644 // CHECK4-NEXT:    [[TMP106:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS24]], i32 0, i32 1
5645 // CHECK4-NEXT:    [[TMP107:%.*]] = bitcast i8** [[TMP106]] to [10 x float]**
5646 // CHECK4-NEXT:    store [10 x float]* [[B]], [10 x float]** [[TMP107]], align 4
5647 // CHECK4-NEXT:    [[TMP108:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1
5648 // CHECK4-NEXT:    store i64 40, i64* [[TMP108]], align 4
5649 // CHECK4-NEXT:    [[TMP109:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS25]], i32 0, i32 1
5650 // CHECK4-NEXT:    store i8* null, i8** [[TMP109]], align 4
5651 // CHECK4-NEXT:    [[TMP110:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS23]], i32 0, i32 2
5652 // CHECK4-NEXT:    [[TMP111:%.*]] = bitcast i8** [[TMP110]] to i32*
5653 // CHECK4-NEXT:    store i32 [[TMP1]], i32* [[TMP111]], align 4
5654 // CHECK4-NEXT:    [[TMP112:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS24]], i32 0, i32 2
5655 // CHECK4-NEXT:    [[TMP113:%.*]] = bitcast i8** [[TMP112]] to i32*
5656 // CHECK4-NEXT:    store i32 [[TMP1]], i32* [[TMP113]], align 4
5657 // CHECK4-NEXT:    [[TMP114:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2
5658 // CHECK4-NEXT:    store i64 4, i64* [[TMP114]], align 4
5659 // CHECK4-NEXT:    [[TMP115:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS25]], i32 0, i32 2
5660 // CHECK4-NEXT:    store i8* null, i8** [[TMP115]], align 4
5661 // CHECK4-NEXT:    [[TMP116:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS23]], i32 0, i32 3
5662 // CHECK4-NEXT:    [[TMP117:%.*]] = bitcast i8** [[TMP116]] to float**
5663 // CHECK4-NEXT:    store float* [[VLA]], float** [[TMP117]], align 4
5664 // CHECK4-NEXT:    [[TMP118:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS24]], i32 0, i32 3
5665 // CHECK4-NEXT:    [[TMP119:%.*]] = bitcast i8** [[TMP118]] to float**
5666 // CHECK4-NEXT:    store float* [[VLA]], float** [[TMP119]], align 4
5667 // CHECK4-NEXT:    [[TMP120:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3
5668 // CHECK4-NEXT:    store i64 [[TMP94]], i64* [[TMP120]], align 4
5669 // CHECK4-NEXT:    [[TMP121:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS25]], i32 0, i32 3
5670 // CHECK4-NEXT:    store i8* null, i8** [[TMP121]], align 4
5671 // CHECK4-NEXT:    [[TMP122:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS23]], i32 0, i32 4
5672 // CHECK4-NEXT:    [[TMP123:%.*]] = bitcast i8** [[TMP122]] to [5 x [10 x double]]**
5673 // CHECK4-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP123]], align 4
5674 // CHECK4-NEXT:    [[TMP124:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS24]], i32 0, i32 4
5675 // CHECK4-NEXT:    [[TMP125:%.*]] = bitcast i8** [[TMP124]] to [5 x [10 x double]]**
5676 // CHECK4-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP125]], align 4
5677 // CHECK4-NEXT:    [[TMP126:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4
5678 // CHECK4-NEXT:    store i64 400, i64* [[TMP126]], align 4
5679 // CHECK4-NEXT:    [[TMP127:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS25]], i32 0, i32 4
5680 // CHECK4-NEXT:    store i8* null, i8** [[TMP127]], align 4
5681 // CHECK4-NEXT:    [[TMP128:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS23]], i32 0, i32 5
5682 // CHECK4-NEXT:    [[TMP129:%.*]] = bitcast i8** [[TMP128]] to i32*
5683 // CHECK4-NEXT:    store i32 5, i32* [[TMP129]], align 4
5684 // CHECK4-NEXT:    [[TMP130:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS24]], i32 0, i32 5
5685 // CHECK4-NEXT:    [[TMP131:%.*]] = bitcast i8** [[TMP130]] to i32*
5686 // CHECK4-NEXT:    store i32 5, i32* [[TMP131]], align 4
5687 // CHECK4-NEXT:    [[TMP132:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 5
5688 // CHECK4-NEXT:    store i64 4, i64* [[TMP132]], align 4
5689 // CHECK4-NEXT:    [[TMP133:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS25]], i32 0, i32 5
5690 // CHECK4-NEXT:    store i8* null, i8** [[TMP133]], align 4
5691 // CHECK4-NEXT:    [[TMP134:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS23]], i32 0, i32 6
5692 // CHECK4-NEXT:    [[TMP135:%.*]] = bitcast i8** [[TMP134]] to i32*
5693 // CHECK4-NEXT:    store i32 [[TMP3]], i32* [[TMP135]], align 4
5694 // CHECK4-NEXT:    [[TMP136:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS24]], i32 0, i32 6
5695 // CHECK4-NEXT:    [[TMP137:%.*]] = bitcast i8** [[TMP136]] to i32*
5696 // CHECK4-NEXT:    store i32 [[TMP3]], i32* [[TMP137]], align 4
5697 // CHECK4-NEXT:    [[TMP138:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 6
5698 // CHECK4-NEXT:    store i64 4, i64* [[TMP138]], align 4
5699 // CHECK4-NEXT:    [[TMP139:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS25]], i32 0, i32 6
5700 // CHECK4-NEXT:    store i8* null, i8** [[TMP139]], align 4
5701 // CHECK4-NEXT:    [[TMP140:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS23]], i32 0, i32 7
5702 // CHECK4-NEXT:    [[TMP141:%.*]] = bitcast i8** [[TMP140]] to double**
5703 // CHECK4-NEXT:    store double* [[VLA1]], double** [[TMP141]], align 4
5704 // CHECK4-NEXT:    [[TMP142:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS24]], i32 0, i32 7
5705 // CHECK4-NEXT:    [[TMP143:%.*]] = bitcast i8** [[TMP142]] to double**
5706 // CHECK4-NEXT:    store double* [[VLA1]], double** [[TMP143]], align 4
5707 // CHECK4-NEXT:    [[TMP144:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7
5708 // CHECK4-NEXT:    store i64 [[TMP97]], i64* [[TMP144]], align 4
5709 // CHECK4-NEXT:    [[TMP145:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS25]], i32 0, i32 7
5710 // CHECK4-NEXT:    store i8* null, i8** [[TMP145]], align 4
5711 // CHECK4-NEXT:    [[TMP146:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS23]], i32 0, i32 8
5712 // CHECK4-NEXT:    [[TMP147:%.*]] = bitcast i8** [[TMP146]] to %struct.TT**
5713 // CHECK4-NEXT:    store %struct.TT* [[D]], %struct.TT** [[TMP147]], align 4
5714 // CHECK4-NEXT:    [[TMP148:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS24]], i32 0, i32 8
5715 // CHECK4-NEXT:    [[TMP149:%.*]] = bitcast i8** [[TMP148]] to %struct.TT**
5716 // CHECK4-NEXT:    store %struct.TT* [[D]], %struct.TT** [[TMP149]], align 4
5717 // CHECK4-NEXT:    [[TMP150:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 8
5718 // CHECK4-NEXT:    store i64 12, i64* [[TMP150]], align 4
5719 // CHECK4-NEXT:    [[TMP151:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS25]], i32 0, i32 8
5720 // CHECK4-NEXT:    store i8* null, i8** [[TMP151]], align 4
5721 // CHECK4-NEXT:    [[TMP152:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS23]], i32 0, i32 9
5722 // CHECK4-NEXT:    [[TMP153:%.*]] = bitcast i8** [[TMP152]] to i32*
5723 // CHECK4-NEXT:    store i32 [[TMP91]], i32* [[TMP153]], align 4
5724 // CHECK4-NEXT:    [[TMP154:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS24]], i32 0, i32 9
5725 // CHECK4-NEXT:    [[TMP155:%.*]] = bitcast i8** [[TMP154]] to i32*
5726 // CHECK4-NEXT:    store i32 [[TMP91]], i32* [[TMP155]], align 4
5727 // CHECK4-NEXT:    [[TMP156:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 9
5728 // CHECK4-NEXT:    store i64 4, i64* [[TMP156]], align 4
5729 // CHECK4-NEXT:    [[TMP157:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS25]], i32 0, i32 9
5730 // CHECK4-NEXT:    store i8* null, i8** [[TMP157]], align 4
5731 // CHECK4-NEXT:    [[TMP158:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS23]], i32 0, i32 0
5732 // CHECK4-NEXT:    [[TMP159:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS24]], i32 0, i32 0
5733 // CHECK4-NEXT:    [[TMP160:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
5734 // CHECK4-NEXT:    call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10)
5735 // CHECK4-NEXT:    [[TMP161:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145.region_id, i32 10, i8** [[TMP158]], i8** [[TMP159]], i64* [[TMP160]], i64* getelementptr inbounds ([10 x i64], [10 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
5736 // CHECK4-NEXT:    [[TMP162:%.*]] = icmp ne i32 [[TMP161]], 0
5737 // CHECK4-NEXT:    br i1 [[TMP162]], label [[OMP_OFFLOAD_FAILED27:%.*]], label [[OMP_OFFLOAD_CONT28:%.*]]
5738 // CHECK4:       omp_offload.failed27:
5739 // CHECK4-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145(i32 [[TMP89]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]], i32 [[TMP91]]) #[[ATTR3]]
5740 // CHECK4-NEXT:    br label [[OMP_OFFLOAD_CONT28]]
5741 // CHECK4:       omp_offload.cont28:
5742 // CHECK4-NEXT:    br label [[OMP_IF_END30:%.*]]
5743 // CHECK4:       omp_if.else29:
5744 // CHECK4-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145(i32 [[TMP89]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]], i32 [[TMP91]]) #[[ATTR3]]
5745 // CHECK4-NEXT:    br label [[OMP_IF_END30]]
5746 // CHECK4:       omp_if.end30:
5747 // CHECK4-NEXT:    [[TMP163:%.*]] = load i32, i32* [[A]], align 4
5748 // CHECK4-NEXT:    [[TMP164:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
5749 // CHECK4-NEXT:    call void @llvm.stackrestore(i8* [[TMP164]])
5750 // CHECK4-NEXT:    ret i32 [[TMP163]]
5751 //
5752 //
5753 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103
5754 // CHECK4-SAME: (i32 [[AA:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]], i32 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] {
5755 // CHECK4-NEXT:  entry:
5756 // CHECK4-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
5757 // CHECK4-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
5758 // CHECK4-NEXT:    [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4
5759 // CHECK4-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
5760 // CHECK4-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]])
5761 // CHECK4-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
5762 // CHECK4-NEXT:    store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
5763 // CHECK4-NEXT:    store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4
5764 // CHECK4-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
5765 // CHECK4-NEXT:    [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
5766 // CHECK4-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4
5767 // CHECK4-NEXT:    call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
5768 // CHECK4-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
5769 // CHECK4-NEXT:    [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
5770 // CHECK4-NEXT:    store i16 [[TMP3]], i16* [[CONV3]], align 2
5771 // CHECK4-NEXT:    [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
5772 // CHECK4-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]])
5773 // CHECK4-NEXT:    ret void
5774 //
5775 //
5776 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined.
5777 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] {
5778 // CHECK4-NEXT:  entry:
5779 // CHECK4-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
5780 // CHECK4-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
5781 // CHECK4-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
5782 // CHECK4-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
5783 // CHECK4-NEXT:    [[TMP:%.*]] = alloca i32, align 4
5784 // CHECK4-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
5785 // CHECK4-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
5786 // CHECK4-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
5787 // CHECK4-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
5788 // CHECK4-NEXT:    [[I:%.*]] = alloca i32, align 4
5789 // CHECK4-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
5790 // CHECK4-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
5791 // CHECK4-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
5792 // CHECK4-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
5793 // CHECK4-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
5794 // CHECK4-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
5795 // CHECK4-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
5796 // CHECK4-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
5797 // CHECK4-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
5798 // CHECK4-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
5799 // CHECK4-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
5800 // CHECK4-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
5801 // CHECK4-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
5802 // CHECK4-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
5803 // CHECK4:       cond.true:
5804 // CHECK4-NEXT:    br label [[COND_END:%.*]]
5805 // CHECK4:       cond.false:
5806 // CHECK4-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
5807 // CHECK4-NEXT:    br label [[COND_END]]
5808 // CHECK4:       cond.end:
5809 // CHECK4-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
5810 // CHECK4-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
5811 // CHECK4-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
5812 // CHECK4-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
5813 // CHECK4-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
5814 // CHECK4:       omp.inner.for.cond:
5815 // CHECK4-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
5816 // CHECK4-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
5817 // CHECK4-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
5818 // CHECK4-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
5819 // CHECK4:       omp.inner.for.body:
5820 // CHECK4-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
5821 // CHECK4-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
5822 // CHECK4-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
5823 // CHECK4-NEXT:    store i32 [[ADD]], i32* [[I]], align 4
5824 // CHECK4-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
5825 // CHECK4:       omp.body.continue:
5826 // CHECK4-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
5827 // CHECK4:       omp.inner.for.inc:
5828 // CHECK4-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
5829 // CHECK4-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
5830 // CHECK4-NEXT:    store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4
5831 // CHECK4-NEXT:    br label [[OMP_INNER_FOR_COND]]
5832 // CHECK4:       omp.inner.for.end:
5833 // CHECK4-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
5834 // CHECK4:       omp.loop.exit:
5835 // CHECK4-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
5836 // CHECK4-NEXT:    ret void
5837 //
5838 //
5839 // CHECK4-LABEL: define {{[^@]+}}@.omp_task_privates_map.
5840 // CHECK4-SAME: (%struct..kmp_privates.t* noalias [[TMP0:%.*]], i16** noalias [[TMP1:%.*]], [3 x i8*]** noalias [[TMP2:%.*]], [3 x i8*]** noalias [[TMP3:%.*]], [3 x i64]** noalias [[TMP4:%.*]]) #[[ATTR4:[0-9]+]] {
5841 // CHECK4-NEXT:  entry:
5842 // CHECK4-NEXT:    [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 4
5843 // CHECK4-NEXT:    [[DOTADDR1:%.*]] = alloca i16**, align 4
5844 // CHECK4-NEXT:    [[DOTADDR2:%.*]] = alloca [3 x i8*]**, align 4
5845 // CHECK4-NEXT:    [[DOTADDR3:%.*]] = alloca [3 x i8*]**, align 4
5846 // CHECK4-NEXT:    [[DOTADDR4:%.*]] = alloca [3 x i64]**, align 4
5847 // CHECK4-NEXT:    store %struct..kmp_privates.t* [[TMP0]], %struct..kmp_privates.t** [[DOTADDR]], align 4
5848 // CHECK4-NEXT:    store i16** [[TMP1]], i16*** [[DOTADDR1]], align 4
5849 // CHECK4-NEXT:    store [3 x i8*]** [[TMP2]], [3 x i8*]*** [[DOTADDR2]], align 4
5850 // CHECK4-NEXT:    store [3 x i8*]** [[TMP3]], [3 x i8*]*** [[DOTADDR3]], align 4
5851 // CHECK4-NEXT:    store [3 x i64]** [[TMP4]], [3 x i64]*** [[DOTADDR4]], align 4
5852 // CHECK4-NEXT:    [[TMP5:%.*]] = load %struct..kmp_privates.t*, %struct..kmp_privates.t** [[DOTADDR]], align 4
5853 // CHECK4-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 0
5854 // CHECK4-NEXT:    [[TMP7:%.*]] = load [3 x i64]**, [3 x i64]*** [[DOTADDR4]], align 4
5855 // CHECK4-NEXT:    store [3 x i64]* [[TMP6]], [3 x i64]** [[TMP7]], align 4
5856 // CHECK4-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 1
5857 // CHECK4-NEXT:    [[TMP9:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR2]], align 4
5858 // CHECK4-NEXT:    store [3 x i8*]* [[TMP8]], [3 x i8*]** [[TMP9]], align 4
5859 // CHECK4-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 2
5860 // CHECK4-NEXT:    [[TMP11:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR3]], align 4
5861 // CHECK4-NEXT:    store [3 x i8*]* [[TMP10]], [3 x i8*]** [[TMP11]], align 4
5862 // CHECK4-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 3
5863 // CHECK4-NEXT:    [[TMP13:%.*]] = load i16**, i16*** [[DOTADDR1]], align 4
5864 // CHECK4-NEXT:    store i16* [[TMP12]], i16** [[TMP13]], align 4
5865 // CHECK4-NEXT:    ret void
5866 //
5867 //
5868 // CHECK4-LABEL: define {{[^@]+}}@.omp_task_entry.
5869 // CHECK4-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] {
5870 // CHECK4-NEXT:  entry:
5871 // CHECK4-NEXT:    [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
5872 // CHECK4-NEXT:    [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 4
5873 // CHECK4-NEXT:    [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 4
5874 // CHECK4-NEXT:    [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 4
5875 // CHECK4-NEXT:    [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 4
5876 // CHECK4-NEXT:    [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 4
5877 // CHECK4-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca i16*, align 4
5878 // CHECK4-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca [3 x i8*]*, align 4
5879 // CHECK4-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca [3 x i8*]*, align 4
5880 // CHECK4-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca [3 x i64]*, align 4
5881 // CHECK4-NEXT:    [[AA_CASTED_I:%.*]] = alloca i32, align 4
5882 // CHECK4-NEXT:    [[DOTCAPTURE_EXPR__CASTED_I:%.*]] = alloca i32, align 4
5883 // CHECK4-NEXT:    [[DOTCAPTURE_EXPR__CASTED4_I:%.*]] = alloca i32, align 4
5884 // CHECK4-NEXT:    [[DOTADDR:%.*]] = alloca i32, align 4
5885 // CHECK4-NEXT:    [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 4
5886 // CHECK4-NEXT:    store i32 [[TMP0]], i32* [[DOTADDR]], align 4
5887 // CHECK4-NEXT:    store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4
5888 // CHECK4-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4
5889 // CHECK4-NEXT:    [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4
5890 // CHECK4-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
5891 // CHECK4-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
5892 // CHECK4-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0
5893 // CHECK4-NEXT:    [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 4
5894 // CHECK4-NEXT:    [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon*
5895 // CHECK4-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1
5896 // CHECK4-NEXT:    [[TMP10:%.*]] = bitcast %struct..kmp_privates.t* [[TMP9]] to i8*
5897 // CHECK4-NEXT:    [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8*
5898 // CHECK4-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META12:![0-9]+]])
5899 // CHECK4-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]])
5900 // CHECK4-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META17:![0-9]+]])
5901 // CHECK4-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]])
5902 // CHECK4-NEXT:    store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !21
5903 // CHECK4-NEXT:    store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 4, !noalias !21
5904 // CHECK4-NEXT:    store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !21
5905 // CHECK4-NEXT:    store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* @.omp_task_privates_map. to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !21
5906 // CHECK4-NEXT:    store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 4, !noalias !21
5907 // CHECK4-NEXT:    store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !21
5908 // CHECK4-NEXT:    [[TMP12:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !21
5909 // CHECK4-NEXT:    [[TMP13:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !21
5910 // CHECK4-NEXT:    [[TMP14:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !21
5911 // CHECK4-NEXT:    [[TMP15:%.*]] = bitcast void (i8*, ...)* [[TMP13]] to void (i8*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)*
5912 // CHECK4-NEXT:    call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]]
5913 // CHECK4-NEXT:    [[TMP16:%.*]] = load i16*, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 4, !noalias !21
5914 // CHECK4-NEXT:    [[TMP17:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 4, !noalias !21
5915 // CHECK4-NEXT:    [[TMP18:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 4, !noalias !21
5916 // CHECK4-NEXT:    [[TMP19:%.*]] = load [3 x i64]*, [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 4, !noalias !21
5917 // CHECK4-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP17]], i32 0, i32 0
5918 // CHECK4-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP18]], i32 0, i32 0
5919 // CHECK4-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[TMP19]], i32 0, i32 0
5920 // CHECK4-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP12]], i32 0, i32 1
5921 // CHECK4-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[TMP12]], i32 0, i32 2
5922 // CHECK4-NEXT:    [[TMP25:%.*]] = load i32, i32* [[TMP23]], align 4
5923 // CHECK4-NEXT:    [[TMP26:%.*]] = load i32, i32* [[TMP24]], align 4
5924 // CHECK4-NEXT:    call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) #[[ATTR3]]
5925 // CHECK4-NEXT:    [[TMP27:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 [[TMP25]], i32 [[TMP26]]) #[[ATTR3]]
5926 // CHECK4-NEXT:    [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0
5927 // CHECK4-NEXT:    br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]]
5928 // CHECK4:       omp_offload.failed.i:
5929 // CHECK4-NEXT:    [[TMP29:%.*]] = load i16, i16* [[TMP16]], align 2
5930 // CHECK4-NEXT:    [[CONV_I:%.*]] = bitcast i32* [[AA_CASTED_I]] to i16*
5931 // CHECK4-NEXT:    store i16 [[TMP29]], i16* [[CONV_I]], align 2, !noalias !21
5932 // CHECK4-NEXT:    [[TMP30:%.*]] = load i32, i32* [[AA_CASTED_I]], align 4, !noalias !21
5933 // CHECK4-NEXT:    [[TMP31:%.*]] = load i32, i32* [[TMP23]], align 4
5934 // CHECK4-NEXT:    store i32 [[TMP31]], i32* [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias !21
5935 // CHECK4-NEXT:    [[TMP32:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias !21
5936 // CHECK4-NEXT:    [[TMP33:%.*]] = load i32, i32* [[TMP24]], align 4
5937 // CHECK4-NEXT:    store i32 [[TMP33]], i32* [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias !21
5938 // CHECK4-NEXT:    [[TMP34:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias !21
5939 // CHECK4-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103(i32 [[TMP30]], i32 [[TMP32]], i32 [[TMP34]]) #[[ATTR3]]
5940 // CHECK4-NEXT:    br label [[DOTOMP_OUTLINED__1_EXIT]]
5941 // CHECK4:       .omp_outlined..1.exit:
5942 // CHECK4-NEXT:    ret i32 0
5943 //
5944 //
5945 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l107
5946 // CHECK4-SAME: (i32 [[A:%.*]]) #[[ATTR2]] {
5947 // CHECK4-NEXT:  entry:
5948 // CHECK4-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
5949 // CHECK4-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
5950 // CHECK4-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
5951 // CHECK4-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
5952 // CHECK4-NEXT:    store i32 [[TMP0]], i32* [[A_CASTED]], align 4
5953 // CHECK4-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
5954 // CHECK4-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]])
5955 // CHECK4-NEXT:    ret void
5956 //
5957 //
5958 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..2
5959 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]]) #[[ATTR2]] {
5960 // CHECK4-NEXT:  entry:
5961 // CHECK4-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
5962 // CHECK4-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
5963 // CHECK4-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
5964 // CHECK4-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
5965 // CHECK4-NEXT:    [[TMP:%.*]] = alloca i32, align 4
5966 // CHECK4-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
5967 // CHECK4-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
5968 // CHECK4-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
5969 // CHECK4-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
5970 // CHECK4-NEXT:    [[I:%.*]] = alloca i32, align 4
5971 // CHECK4-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
5972 // CHECK4-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
5973 // CHECK4-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
5974 // CHECK4-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
5975 // CHECK4-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
5976 // CHECK4-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
5977 // CHECK4-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
5978 // CHECK4-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
5979 // CHECK4-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
5980 // CHECK4-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
5981 // CHECK4-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
5982 // CHECK4-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
5983 // CHECK4-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
5984 // CHECK4:       cond.true:
5985 // CHECK4-NEXT:    br label [[COND_END:%.*]]
5986 // CHECK4:       cond.false:
5987 // CHECK4-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
5988 // CHECK4-NEXT:    br label [[COND_END]]
5989 // CHECK4:       cond.end:
5990 // CHECK4-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
5991 // CHECK4-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
5992 // CHECK4-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
5993 // CHECK4-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
5994 // CHECK4-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
5995 // CHECK4:       omp.inner.for.cond:
5996 // CHECK4-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
5997 // CHECK4-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
5998 // CHECK4-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
5999 // CHECK4-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
6000 // CHECK4:       omp.inner.for.body:
6001 // CHECK4-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
6002 // CHECK4-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
6003 // CHECK4-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
6004 // CHECK4-NEXT:    store i32 [[ADD]], i32* [[I]], align 4
6005 // CHECK4-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
6006 // CHECK4-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
6007 // CHECK4-NEXT:    store i32 [[ADD2]], i32* [[A_ADDR]], align 4
6008 // CHECK4-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
6009 // CHECK4:       omp.body.continue:
6010 // CHECK4-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
6011 // CHECK4:       omp.inner.for.inc:
6012 // CHECK4-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
6013 // CHECK4-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1
6014 // CHECK4-NEXT:    store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4
6015 // CHECK4-NEXT:    br label [[OMP_INNER_FOR_COND]]
6016 // CHECK4:       omp.inner.for.end:
6017 // CHECK4-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
6018 // CHECK4:       omp.loop.exit:
6019 // CHECK4-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
6020 // CHECK4-NEXT:    ret void
6021 //
6022 //
6023 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113
6024 // CHECK4-SAME: (i32 [[AA:%.*]]) #[[ATTR2]] {
6025 // CHECK4-NEXT:  entry:
6026 // CHECK4-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
6027 // CHECK4-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
6028 // CHECK4-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
6029 // CHECK4-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
6030 // CHECK4-NEXT:    [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
6031 // CHECK4-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
6032 // CHECK4-NEXT:    store i16 [[TMP0]], i16* [[CONV1]], align 2
6033 // CHECK4-NEXT:    [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
6034 // CHECK4-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP1]])
6035 // CHECK4-NEXT:    ret void
6036 //
6037 //
6038 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..3
6039 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] {
6040 // CHECK4-NEXT:  entry:
6041 // CHECK4-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
6042 // CHECK4-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
6043 // CHECK4-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
6044 // CHECK4-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
6045 // CHECK4-NEXT:    [[TMP:%.*]] = alloca i32, align 4
6046 // CHECK4-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
6047 // CHECK4-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
6048 // CHECK4-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
6049 // CHECK4-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
6050 // CHECK4-NEXT:    [[I:%.*]] = alloca i32, align 4
6051 // CHECK4-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
6052 // CHECK4-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
6053 // CHECK4-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
6054 // CHECK4-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
6055 // CHECK4-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
6056 // CHECK4-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
6057 // CHECK4-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
6058 // CHECK4-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
6059 // CHECK4-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
6060 // CHECK4-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
6061 // CHECK4-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
6062 // CHECK4-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
6063 // CHECK4-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
6064 // CHECK4-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
6065 // CHECK4:       cond.true:
6066 // CHECK4-NEXT:    br label [[COND_END:%.*]]
6067 // CHECK4:       cond.false:
6068 // CHECK4-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
6069 // CHECK4-NEXT:    br label [[COND_END]]
6070 // CHECK4:       cond.end:
6071 // CHECK4-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
6072 // CHECK4-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
6073 // CHECK4-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
6074 // CHECK4-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
6075 // CHECK4-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
6076 // CHECK4:       omp.inner.for.cond:
6077 // CHECK4-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
6078 // CHECK4-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
6079 // CHECK4-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
6080 // CHECK4-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
6081 // CHECK4:       omp.inner.for.body:
6082 // CHECK4-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
6083 // CHECK4-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
6084 // CHECK4-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
6085 // CHECK4-NEXT:    store i32 [[ADD]], i32* [[I]], align 4
6086 // CHECK4-NEXT:    [[TMP8:%.*]] = load i16, i16* [[CONV]], align 4
6087 // CHECK4-NEXT:    [[CONV2:%.*]] = sext i16 [[TMP8]] to i32
6088 // CHECK4-NEXT:    [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
6089 // CHECK4-NEXT:    [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
6090 // CHECK4-NEXT:    store i16 [[CONV4]], i16* [[CONV]], align 4
6091 // CHECK4-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
6092 // CHECK4:       omp.body.continue:
6093 // CHECK4-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
6094 // CHECK4:       omp.inner.for.inc:
6095 // CHECK4-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
6096 // CHECK4-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP9]], 1
6097 // CHECK4-NEXT:    store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4
6098 // CHECK4-NEXT:    br label [[OMP_INNER_FOR_COND]]
6099 // CHECK4:       omp.inner.for.end:
6100 // CHECK4-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
6101 // CHECK4:       omp.loop.exit:
6102 // CHECK4-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
6103 // CHECK4-NEXT:    ret void
6104 //
6105 //
6106 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120
6107 // CHECK4-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] {
6108 // CHECK4-NEXT:  entry:
6109 // CHECK4-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
6110 // CHECK4-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
6111 // CHECK4-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
6112 // CHECK4-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
6113 // CHECK4-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
6114 // CHECK4-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
6115 // CHECK4-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
6116 // CHECK4-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
6117 // CHECK4-NEXT:    store i32 [[TMP0]], i32* [[A_CASTED]], align 4
6118 // CHECK4-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
6119 // CHECK4-NEXT:    [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
6120 // CHECK4-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
6121 // CHECK4-NEXT:    store i16 [[TMP2]], i16* [[CONV1]], align 2
6122 // CHECK4-NEXT:    [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
6123 // CHECK4-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]])
6124 // CHECK4-NEXT:    ret void
6125 //
6126 //
6127 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..6
6128 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] {
6129 // CHECK4-NEXT:  entry:
6130 // CHECK4-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
6131 // CHECK4-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
6132 // CHECK4-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
6133 // CHECK4-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
6134 // CHECK4-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
6135 // CHECK4-NEXT:    [[TMP:%.*]] = alloca i32, align 4
6136 // CHECK4-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
6137 // CHECK4-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
6138 // CHECK4-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
6139 // CHECK4-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
6140 // CHECK4-NEXT:    [[I:%.*]] = alloca i32, align 4
6141 // CHECK4-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
6142 // CHECK4-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
6143 // CHECK4-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
6144 // CHECK4-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
6145 // CHECK4-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
6146 // CHECK4-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
6147 // CHECK4-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
6148 // CHECK4-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
6149 // CHECK4-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
6150 // CHECK4-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
6151 // CHECK4-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
6152 // CHECK4-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
6153 // CHECK4-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
6154 // CHECK4-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
6155 // CHECK4-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
6156 // CHECK4:       cond.true:
6157 // CHECK4-NEXT:    br label [[COND_END:%.*]]
6158 // CHECK4:       cond.false:
6159 // CHECK4-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
6160 // CHECK4-NEXT:    br label [[COND_END]]
6161 // CHECK4:       cond.end:
6162 // CHECK4-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
6163 // CHECK4-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
6164 // CHECK4-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
6165 // CHECK4-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
6166 // CHECK4-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
6167 // CHECK4:       omp.inner.for.cond:
6168 // CHECK4-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
6169 // CHECK4-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
6170 // CHECK4-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
6171 // CHECK4-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
6172 // CHECK4:       omp.inner.for.body:
6173 // CHECK4-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
6174 // CHECK4-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
6175 // CHECK4-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
6176 // CHECK4-NEXT:    store i32 [[ADD]], i32* [[I]], align 4
6177 // CHECK4-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
6178 // CHECK4-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
6179 // CHECK4-NEXT:    store i32 [[ADD2]], i32* [[A_ADDR]], align 4
6180 // CHECK4-NEXT:    [[TMP9:%.*]] = load i16, i16* [[CONV]], align 4
6181 // CHECK4-NEXT:    [[CONV3:%.*]] = sext i16 [[TMP9]] to i32
6182 // CHECK4-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
6183 // CHECK4-NEXT:    [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
6184 // CHECK4-NEXT:    store i16 [[CONV5]], i16* [[CONV]], align 4
6185 // CHECK4-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
6186 // CHECK4:       omp.body.continue:
6187 // CHECK4-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
6188 // CHECK4:       omp.inner.for.inc:
6189 // CHECK4-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
6190 // CHECK4-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP10]], 1
6191 // CHECK4-NEXT:    store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4
6192 // CHECK4-NEXT:    br label [[OMP_INNER_FOR_COND]]
6193 // CHECK4:       omp.inner.for.end:
6194 // CHECK4-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
6195 // CHECK4:       omp.loop.exit:
6196 // CHECK4-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
6197 // CHECK4-NEXT:    ret void
6198 //
6199 //
6200 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145
6201 // CHECK4-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] {
6202 // CHECK4-NEXT:  entry:
6203 // CHECK4-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
6204 // CHECK4-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
6205 // CHECK4-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
6206 // CHECK4-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 4
6207 // CHECK4-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
6208 // CHECK4-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
6209 // CHECK4-NEXT:    [[VLA_ADDR4:%.*]] = alloca i32, align 4
6210 // CHECK4-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 4
6211 // CHECK4-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
6212 // CHECK4-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
6213 // CHECK4-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
6214 // CHECK4-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
6215 // CHECK4-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
6216 // CHECK4-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
6217 // CHECK4-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
6218 // CHECK4-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 4
6219 // CHECK4-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
6220 // CHECK4-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
6221 // CHECK4-NEXT:    store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
6222 // CHECK4-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 4
6223 // CHECK4-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
6224 // CHECK4-NEXT:    store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
6225 // CHECK4-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
6226 // CHECK4-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
6227 // CHECK4-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
6228 // CHECK4-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
6229 // CHECK4-NEXT:    [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
6230 // CHECK4-NEXT:    [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
6231 // CHECK4-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
6232 // CHECK4-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
6233 // CHECK4-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
6234 // CHECK4-NEXT:    store i32 [[TMP8]], i32* [[A_CASTED]], align 4
6235 // CHECK4-NEXT:    [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4
6236 // CHECK4-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
6237 // CHECK4-NEXT:    store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
6238 // CHECK4-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
6239 // CHECK4-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*, i32)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i32 [[TMP11]])
6240 // CHECK4-NEXT:    ret void
6241 //
6242 //
6243 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..9
6244 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] {
6245 // CHECK4-NEXT:  entry:
6246 // CHECK4-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
6247 // CHECK4-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
6248 // CHECK4-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
6249 // CHECK4-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
6250 // CHECK4-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
6251 // CHECK4-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 4
6252 // CHECK4-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
6253 // CHECK4-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
6254 // CHECK4-NEXT:    [[VLA_ADDR4:%.*]] = alloca i32, align 4
6255 // CHECK4-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 4
6256 // CHECK4-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
6257 // CHECK4-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
6258 // CHECK4-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
6259 // CHECK4-NEXT:    [[TMP:%.*]] = alloca i32, align 4
6260 // CHECK4-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
6261 // CHECK4-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
6262 // CHECK4-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
6263 // CHECK4-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
6264 // CHECK4-NEXT:    [[I:%.*]] = alloca i32, align 4
6265 // CHECK4-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
6266 // CHECK4-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
6267 // CHECK4-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
6268 // CHECK4-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
6269 // CHECK4-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
6270 // CHECK4-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 4
6271 // CHECK4-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
6272 // CHECK4-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
6273 // CHECK4-NEXT:    store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
6274 // CHECK4-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 4
6275 // CHECK4-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
6276 // CHECK4-NEXT:    store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
6277 // CHECK4-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
6278 // CHECK4-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
6279 // CHECK4-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
6280 // CHECK4-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
6281 // CHECK4-NEXT:    [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
6282 // CHECK4-NEXT:    [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
6283 // CHECK4-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
6284 // CHECK4-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
6285 // CHECK4-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
6286 // CHECK4-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
6287 // CHECK4-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
6288 // CHECK4-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
6289 // CHECK4-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
6290 // CHECK4-NEXT:    [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
6291 // CHECK4-NEXT:    [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
6292 // CHECK4-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
6293 // CHECK4-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
6294 // CHECK4:       omp.dispatch.cond:
6295 // CHECK4-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
6296 // CHECK4-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 9
6297 // CHECK4-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
6298 // CHECK4:       cond.true:
6299 // CHECK4-NEXT:    br label [[COND_END:%.*]]
6300 // CHECK4:       cond.false:
6301 // CHECK4-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
6302 // CHECK4-NEXT:    br label [[COND_END]]
6303 // CHECK4:       cond.end:
6304 // CHECK4-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
6305 // CHECK4-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
6306 // CHECK4-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
6307 // CHECK4-NEXT:    store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
6308 // CHECK4-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
6309 // CHECK4-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
6310 // CHECK4-NEXT:    [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
6311 // CHECK4-NEXT:    br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
6312 // CHECK4:       omp.dispatch.body:
6313 // CHECK4-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
6314 // CHECK4:       omp.inner.for.cond:
6315 // CHECK4-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
6316 // CHECK4-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !22
6317 // CHECK4-NEXT:    [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
6318 // CHECK4-NEXT:    br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
6319 // CHECK4:       omp.inner.for.body:
6320 // CHECK4-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
6321 // CHECK4-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
6322 // CHECK4-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
6323 // CHECK4-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !22
6324 // CHECK4-NEXT:    [[TMP19:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !22
6325 // CHECK4-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP19]], 1
6326 // CHECK4-NEXT:    store i32 [[ADD7]], i32* [[A_ADDR]], align 4, !llvm.access.group !22
6327 // CHECK4-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2
6328 // CHECK4-NEXT:    [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !22
6329 // CHECK4-NEXT:    [[CONV:%.*]] = fpext float [[TMP20]] to double
6330 // CHECK4-NEXT:    [[ADD8:%.*]] = fadd double [[CONV]], 1.000000e+00
6331 // CHECK4-NEXT:    [[CONV9:%.*]] = fptrunc double [[ADD8]] to float
6332 // CHECK4-NEXT:    store float [[CONV9]], float* [[ARRAYIDX]], align 4, !llvm.access.group !22
6333 // CHECK4-NEXT:    [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3
6334 // CHECK4-NEXT:    [[TMP21:%.*]] = load float, float* [[ARRAYIDX10]], align 4, !llvm.access.group !22
6335 // CHECK4-NEXT:    [[CONV11:%.*]] = fpext float [[TMP21]] to double
6336 // CHECK4-NEXT:    [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00
6337 // CHECK4-NEXT:    [[CONV13:%.*]] = fptrunc double [[ADD12]] to float
6338 // CHECK4-NEXT:    store float [[CONV13]], float* [[ARRAYIDX10]], align 4, !llvm.access.group !22
6339 // CHECK4-NEXT:    [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1
6340 // CHECK4-NEXT:    [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX14]], i32 0, i32 2
6341 // CHECK4-NEXT:    [[TMP22:%.*]] = load double, double* [[ARRAYIDX15]], align 8, !llvm.access.group !22
6342 // CHECK4-NEXT:    [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00
6343 // CHECK4-NEXT:    store double [[ADD16]], double* [[ARRAYIDX15]], align 8, !llvm.access.group !22
6344 // CHECK4-NEXT:    [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]]
6345 // CHECK4-NEXT:    [[ARRAYIDX17:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP23]]
6346 // CHECK4-NEXT:    [[ARRAYIDX18:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX17]], i32 3
6347 // CHECK4-NEXT:    [[TMP24:%.*]] = load double, double* [[ARRAYIDX18]], align 8, !llvm.access.group !22
6348 // CHECK4-NEXT:    [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00
6349 // CHECK4-NEXT:    store double [[ADD19]], double* [[ARRAYIDX18]], align 8, !llvm.access.group !22
6350 // CHECK4-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0
6351 // CHECK4-NEXT:    [[TMP25:%.*]] = load i64, i64* [[X]], align 4, !llvm.access.group !22
6352 // CHECK4-NEXT:    [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1
6353 // CHECK4-NEXT:    store i64 [[ADD20]], i64* [[X]], align 4, !llvm.access.group !22
6354 // CHECK4-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1
6355 // CHECK4-NEXT:    [[TMP26:%.*]] = load i8, i8* [[Y]], align 4, !llvm.access.group !22
6356 // CHECK4-NEXT:    [[CONV21:%.*]] = sext i8 [[TMP26]] to i32
6357 // CHECK4-NEXT:    [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1
6358 // CHECK4-NEXT:    [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8
6359 // CHECK4-NEXT:    store i8 [[CONV23]], i8* [[Y]], align 4, !llvm.access.group !22
6360 // CHECK4-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
6361 // CHECK4:       omp.body.continue:
6362 // CHECK4-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
6363 // CHECK4:       omp.inner.for.inc:
6364 // CHECK4-NEXT:    [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
6365 // CHECK4-NEXT:    [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1
6366 // CHECK4-NEXT:    store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
6367 // CHECK4-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]]
6368 // CHECK4:       omp.inner.for.end:
6369 // CHECK4-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
6370 // CHECK4:       omp.dispatch.inc:
6371 // CHECK4-NEXT:    [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
6372 // CHECK4-NEXT:    [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
6373 // CHECK4-NEXT:    [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]
6374 // CHECK4-NEXT:    store i32 [[ADD25]], i32* [[DOTOMP_LB]], align 4
6375 // CHECK4-NEXT:    [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
6376 // CHECK4-NEXT:    [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
6377 // CHECK4-NEXT:    [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]]
6378 // CHECK4-NEXT:    store i32 [[ADD26]], i32* [[DOTOMP_UB]], align 4
6379 // CHECK4-NEXT:    br label [[OMP_DISPATCH_COND]]
6380 // CHECK4:       omp.dispatch.end:
6381 // CHECK4-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]])
6382 // CHECK4-NEXT:    ret void
6383 //
6384 //
6385 // CHECK4-LABEL: define {{[^@]+}}@_Z3bari
6386 // CHECK4-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
6387 // CHECK4-NEXT:  entry:
6388 // CHECK4-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
6389 // CHECK4-NEXT:    [[A:%.*]] = alloca i32, align 4
6390 // CHECK4-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4
6391 // CHECK4-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
6392 // CHECK4-NEXT:    store i32 0, i32* [[A]], align 4
6393 // CHECK4-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
6394 // CHECK4-NEXT:    [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]])
6395 // CHECK4-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
6396 // CHECK4-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
6397 // CHECK4-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
6398 // CHECK4-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
6399 // CHECK4-NEXT:    [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]])
6400 // CHECK4-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
6401 // CHECK4-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
6402 // CHECK4-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
6403 // CHECK4-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
6404 // CHECK4-NEXT:    [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]])
6405 // CHECK4-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
6406 // CHECK4-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
6407 // CHECK4-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
6408 // CHECK4-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
6409 // CHECK4-NEXT:    [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]])
6410 // CHECK4-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
6411 // CHECK4-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
6412 // CHECK4-NEXT:    store i32 [[ADD6]], i32* [[A]], align 4
6413 // CHECK4-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
6414 // CHECK4-NEXT:    ret i32 [[TMP8]]
6415 //
6416 //
6417 // CHECK4-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
6418 // CHECK4-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 {
6419 // CHECK4-NEXT:  entry:
6420 // CHECK4-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
6421 // CHECK4-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
6422 // CHECK4-NEXT:    [[B:%.*]] = alloca i32, align 4
6423 // CHECK4-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 4
6424 // CHECK4-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 4
6425 // CHECK4-NEXT:    [[B_CASTED:%.*]] = alloca i32, align 4
6426 // CHECK4-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4
6427 // CHECK4-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4
6428 // CHECK4-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4
6429 // CHECK4-NEXT:    [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 4
6430 // CHECK4-NEXT:    [[TMP:%.*]] = alloca i32, align 4
6431 // CHECK4-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
6432 // CHECK4-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
6433 // CHECK4-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
6434 // CHECK4-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
6435 // CHECK4-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
6436 // CHECK4-NEXT:    store i32 [[ADD]], i32* [[B]], align 4
6437 // CHECK4-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
6438 // CHECK4-NEXT:    [[TMP2:%.*]] = call i8* @llvm.stacksave()
6439 // CHECK4-NEXT:    store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4
6440 // CHECK4-NEXT:    [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]
6441 // CHECK4-NEXT:    [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2
6442 // CHECK4-NEXT:    store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
6443 // CHECK4-NEXT:    [[TMP4:%.*]] = load i32, i32* [[B]], align 4
6444 // CHECK4-NEXT:    store i32 [[TMP4]], i32* [[B_CASTED]], align 4
6445 // CHECK4-NEXT:    [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4
6446 // CHECK4-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
6447 // CHECK4-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 60
6448 // CHECK4-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
6449 // CHECK4:       omp_if.then:
6450 // CHECK4-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
6451 // CHECK4-NEXT:    [[TMP7:%.*]] = mul nuw i32 2, [[TMP1]]
6452 // CHECK4-NEXT:    [[TMP8:%.*]] = mul nuw i32 [[TMP7]], 2
6453 // CHECK4-NEXT:    [[TMP9:%.*]] = sext i32 [[TMP8]] to i64
6454 // CHECK4-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
6455 // CHECK4-NEXT:    [[TMP11:%.*]] = bitcast i8** [[TMP10]] to %struct.S1**
6456 // CHECK4-NEXT:    store %struct.S1* [[THIS1]], %struct.S1** [[TMP11]], align 4
6457 // CHECK4-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
6458 // CHECK4-NEXT:    [[TMP13:%.*]] = bitcast i8** [[TMP12]] to double**
6459 // CHECK4-NEXT:    store double* [[A]], double** [[TMP13]], align 4
6460 // CHECK4-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
6461 // CHECK4-NEXT:    store i64 8, i64* [[TMP14]], align 4
6462 // CHECK4-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
6463 // CHECK4-NEXT:    store i8* null, i8** [[TMP15]], align 4
6464 // CHECK4-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
6465 // CHECK4-NEXT:    [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32*
6466 // CHECK4-NEXT:    store i32 [[TMP5]], i32* [[TMP17]], align 4
6467 // CHECK4-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
6468 // CHECK4-NEXT:    [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32*
6469 // CHECK4-NEXT:    store i32 [[TMP5]], i32* [[TMP19]], align 4
6470 // CHECK4-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1
6471 // CHECK4-NEXT:    store i64 4, i64* [[TMP20]], align 4
6472 // CHECK4-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
6473 // CHECK4-NEXT:    store i8* null, i8** [[TMP21]], align 4
6474 // CHECK4-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
6475 // CHECK4-NEXT:    [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i32*
6476 // CHECK4-NEXT:    store i32 2, i32* [[TMP23]], align 4
6477 // CHECK4-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
6478 // CHECK4-NEXT:    [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i32*
6479 // CHECK4-NEXT:    store i32 2, i32* [[TMP25]], align 4
6480 // CHECK4-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2
6481 // CHECK4-NEXT:    store i64 4, i64* [[TMP26]], align 4
6482 // CHECK4-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
6483 // CHECK4-NEXT:    store i8* null, i8** [[TMP27]], align 4
6484 // CHECK4-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
6485 // CHECK4-NEXT:    [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i32*
6486 // CHECK4-NEXT:    store i32 [[TMP1]], i32* [[TMP29]], align 4
6487 // CHECK4-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
6488 // CHECK4-NEXT:    [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i32*
6489 // CHECK4-NEXT:    store i32 [[TMP1]], i32* [[TMP31]], align 4
6490 // CHECK4-NEXT:    [[TMP32:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3
6491 // CHECK4-NEXT:    store i64 4, i64* [[TMP32]], align 4
6492 // CHECK4-NEXT:    [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
6493 // CHECK4-NEXT:    store i8* null, i8** [[TMP33]], align 4
6494 // CHECK4-NEXT:    [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
6495 // CHECK4-NEXT:    [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i16**
6496 // CHECK4-NEXT:    store i16* [[VLA]], i16** [[TMP35]], align 4
6497 // CHECK4-NEXT:    [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
6498 // CHECK4-NEXT:    [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i16**
6499 // CHECK4-NEXT:    store i16* [[VLA]], i16** [[TMP37]], align 4
6500 // CHECK4-NEXT:    [[TMP38:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4
6501 // CHECK4-NEXT:    store i64 [[TMP9]], i64* [[TMP38]], align 4
6502 // CHECK4-NEXT:    [[TMP39:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4
6503 // CHECK4-NEXT:    store i8* null, i8** [[TMP39]], align 4
6504 // CHECK4-NEXT:    [[TMP40:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
6505 // CHECK4-NEXT:    [[TMP41:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
6506 // CHECK4-NEXT:    [[TMP42:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
6507 // CHECK4-NEXT:    call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10)
6508 // CHECK4-NEXT:    [[TMP43:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218.region_id, i32 5, i8** [[TMP40]], i8** [[TMP41]], i64* [[TMP42]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.12, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
6509 // CHECK4-NEXT:    [[TMP44:%.*]] = icmp ne i32 [[TMP43]], 0
6510 // CHECK4-NEXT:    br i1 [[TMP44]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
6511 // CHECK4:       omp_offload.failed:
6512 // CHECK4-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR3]]
6513 // CHECK4-NEXT:    br label [[OMP_OFFLOAD_CONT]]
6514 // CHECK4:       omp_offload.cont:
6515 // CHECK4-NEXT:    br label [[OMP_IF_END:%.*]]
6516 // CHECK4:       omp_if.else:
6517 // CHECK4-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR3]]
6518 // CHECK4-NEXT:    br label [[OMP_IF_END]]
6519 // CHECK4:       omp_if.end:
6520 // CHECK4-NEXT:    [[TMP45:%.*]] = mul nsw i32 1, [[TMP1]]
6521 // CHECK4-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP45]]
6522 // CHECK4-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
6523 // CHECK4-NEXT:    [[TMP46:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2
6524 // CHECK4-NEXT:    [[CONV:%.*]] = sext i16 [[TMP46]] to i32
6525 // CHECK4-NEXT:    [[TMP47:%.*]] = load i32, i32* [[B]], align 4
6526 // CHECK4-NEXT:    [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP47]]
6527 // CHECK4-NEXT:    [[TMP48:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
6528 // CHECK4-NEXT:    call void @llvm.stackrestore(i8* [[TMP48]])
6529 // CHECK4-NEXT:    ret i32 [[ADD3]]
6530 //
6531 //
6532 // CHECK4-LABEL: define {{[^@]+}}@_ZL7fstatici
6533 // CHECK4-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
6534 // CHECK4-NEXT:  entry:
6535 // CHECK4-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
6536 // CHECK4-NEXT:    [[A:%.*]] = alloca i32, align 4
6537 // CHECK4-NEXT:    [[AA:%.*]] = alloca i16, align 2
6538 // CHECK4-NEXT:    [[AAA:%.*]] = alloca i8, align 1
6539 // CHECK4-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
6540 // CHECK4-NEXT:    [[N_CASTED:%.*]] = alloca i32, align 4
6541 // CHECK4-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
6542 // CHECK4-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
6543 // CHECK4-NEXT:    [[AAA_CASTED:%.*]] = alloca i32, align 4
6544 // CHECK4-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4
6545 // CHECK4-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4
6546 // CHECK4-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4
6547 // CHECK4-NEXT:    [[TMP:%.*]] = alloca i32, align 4
6548 // CHECK4-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
6549 // CHECK4-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
6550 // CHECK4-NEXT:    [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4
6551 // CHECK4-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
6552 // CHECK4-NEXT:    store i32 0, i32* [[A]], align 4
6553 // CHECK4-NEXT:    store i16 0, i16* [[AA]], align 2
6554 // CHECK4-NEXT:    store i8 0, i8* [[AAA]], align 1
6555 // CHECK4-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
6556 // CHECK4-NEXT:    store i32 [[TMP0]], i32* [[N_CASTED]], align 4
6557 // CHECK4-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_CASTED]], align 4
6558 // CHECK4-NEXT:    [[TMP2:%.*]] = load i32, i32* [[A]], align 4
6559 // CHECK4-NEXT:    store i32 [[TMP2]], i32* [[A_CASTED]], align 4
6560 // CHECK4-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A_CASTED]], align 4
6561 // CHECK4-NEXT:    [[TMP4:%.*]] = load i16, i16* [[AA]], align 2
6562 // CHECK4-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
6563 // CHECK4-NEXT:    store i16 [[TMP4]], i16* [[CONV]], align 2
6564 // CHECK4-NEXT:    [[TMP5:%.*]] = load i32, i32* [[AA_CASTED]], align 4
6565 // CHECK4-NEXT:    [[TMP6:%.*]] = load i8, i8* [[AAA]], align 1
6566 // CHECK4-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
6567 // CHECK4-NEXT:    store i8 [[TMP6]], i8* [[CONV1]], align 1
6568 // CHECK4-NEXT:    [[TMP7:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
6569 // CHECK4-NEXT:    [[TMP8:%.*]] = load i32, i32* [[N_ADDR]], align 4
6570 // CHECK4-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP8]], 50
6571 // CHECK4-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
6572 // CHECK4:       omp_if.then:
6573 // CHECK4-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
6574 // CHECK4-NEXT:    [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32*
6575 // CHECK4-NEXT:    store i32 [[TMP1]], i32* [[TMP10]], align 4
6576 // CHECK4-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
6577 // CHECK4-NEXT:    [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32*
6578 // CHECK4-NEXT:    store i32 [[TMP1]], i32* [[TMP12]], align 4
6579 // CHECK4-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
6580 // CHECK4-NEXT:    store i8* null, i8** [[TMP13]], align 4
6581 // CHECK4-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
6582 // CHECK4-NEXT:    [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32*
6583 // CHECK4-NEXT:    store i32 [[TMP3]], i32* [[TMP15]], align 4
6584 // CHECK4-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
6585 // CHECK4-NEXT:    [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32*
6586 // CHECK4-NEXT:    store i32 [[TMP3]], i32* [[TMP17]], align 4
6587 // CHECK4-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
6588 // CHECK4-NEXT:    store i8* null, i8** [[TMP18]], align 4
6589 // CHECK4-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
6590 // CHECK4-NEXT:    [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32*
6591 // CHECK4-NEXT:    store i32 [[TMP5]], i32* [[TMP20]], align 4
6592 // CHECK4-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
6593 // CHECK4-NEXT:    [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i32*
6594 // CHECK4-NEXT:    store i32 [[TMP5]], i32* [[TMP22]], align 4
6595 // CHECK4-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
6596 // CHECK4-NEXT:    store i8* null, i8** [[TMP23]], align 4
6597 // CHECK4-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
6598 // CHECK4-NEXT:    [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i32*
6599 // CHECK4-NEXT:    store i32 [[TMP7]], i32* [[TMP25]], align 4
6600 // CHECK4-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
6601 // CHECK4-NEXT:    [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i32*
6602 // CHECK4-NEXT:    store i32 [[TMP7]], i32* [[TMP27]], align 4
6603 // CHECK4-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
6604 // CHECK4-NEXT:    store i8* null, i8** [[TMP28]], align 4
6605 // CHECK4-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
6606 // CHECK4-NEXT:    [[TMP30:%.*]] = bitcast i8** [[TMP29]] to [10 x i32]**
6607 // CHECK4-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP30]], align 4
6608 // CHECK4-NEXT:    [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
6609 // CHECK4-NEXT:    [[TMP32:%.*]] = bitcast i8** [[TMP31]] to [10 x i32]**
6610 // CHECK4-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP32]], align 4
6611 // CHECK4-NEXT:    [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4
6612 // CHECK4-NEXT:    store i8* null, i8** [[TMP33]], align 4
6613 // CHECK4-NEXT:    [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
6614 // CHECK4-NEXT:    [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
6615 // CHECK4-NEXT:    [[TMP36:%.*]] = load i32, i32* [[A]], align 4
6616 // CHECK4-NEXT:    store i32 [[TMP36]], i32* [[DOTCAPTURE_EXPR_]], align 4
6617 // CHECK4-NEXT:    [[TMP37:%.*]] = load i32, i32* [[N_ADDR]], align 4
6618 // CHECK4-NEXT:    store i32 [[TMP37]], i32* [[DOTCAPTURE_EXPR_2]], align 4
6619 // CHECK4-NEXT:    [[TMP38:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
6620 // CHECK4-NEXT:    [[TMP39:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
6621 // CHECK4-NEXT:    [[SUB:%.*]] = sub i32 [[TMP38]], [[TMP39]]
6622 // CHECK4-NEXT:    [[SUB4:%.*]] = sub i32 [[SUB]], 1
6623 // CHECK4-NEXT:    [[ADD:%.*]] = add i32 [[SUB4]], 1
6624 // CHECK4-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], 1
6625 // CHECK4-NEXT:    [[SUB5:%.*]] = sub i32 [[DIV]], 1
6626 // CHECK4-NEXT:    store i32 [[SUB5]], i32* [[DOTCAPTURE_EXPR_3]], align 4
6627 // CHECK4-NEXT:    [[TMP40:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
6628 // CHECK4-NEXT:    [[ADD6:%.*]] = add i32 [[TMP40]], 1
6629 // CHECK4-NEXT:    [[TMP41:%.*]] = zext i32 [[ADD6]] to i64
6630 // CHECK4-NEXT:    call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 [[TMP41]])
6631 // CHECK4-NEXT:    [[TMP42:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200.region_id, i32 5, i8** [[TMP34]], i8** [[TMP35]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes.14, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.15, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
6632 // CHECK4-NEXT:    [[TMP43:%.*]] = icmp ne i32 [[TMP42]], 0
6633 // CHECK4-NEXT:    br i1 [[TMP43]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
6634 // CHECK4:       omp_offload.failed:
6635 // CHECK4-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], i32 [[TMP7]], [10 x i32]* [[B]]) #[[ATTR3]]
6636 // CHECK4-NEXT:    br label [[OMP_OFFLOAD_CONT]]
6637 // CHECK4:       omp_offload.cont:
6638 // CHECK4-NEXT:    br label [[OMP_IF_END:%.*]]
6639 // CHECK4:       omp_if.else:
6640 // CHECK4-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], i32 [[TMP7]], [10 x i32]* [[B]]) #[[ATTR3]]
6641 // CHECK4-NEXT:    br label [[OMP_IF_END]]
6642 // CHECK4:       omp_if.end:
6643 // CHECK4-NEXT:    [[TMP44:%.*]] = load i32, i32* [[A]], align 4
6644 // CHECK4-NEXT:    ret i32 [[TMP44]]
6645 //
6646 //
6647 // CHECK4-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
6648 // CHECK4-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat {
6649 // CHECK4-NEXT:  entry:
6650 // CHECK4-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
6651 // CHECK4-NEXT:    [[A:%.*]] = alloca i32, align 4
6652 // CHECK4-NEXT:    [[AA:%.*]] = alloca i16, align 2
6653 // CHECK4-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
6654 // CHECK4-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
6655 // CHECK4-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
6656 // CHECK4-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4
6657 // CHECK4-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4
6658 // CHECK4-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4
6659 // CHECK4-NEXT:    [[TMP:%.*]] = alloca i32, align 4
6660 // CHECK4-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
6661 // CHECK4-NEXT:    store i32 0, i32* [[A]], align 4
6662 // CHECK4-NEXT:    store i16 0, i16* [[AA]], align 2
6663 // CHECK4-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
6664 // CHECK4-NEXT:    store i32 [[TMP0]], i32* [[A_CASTED]], align 4
6665 // CHECK4-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
6666 // CHECK4-NEXT:    [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
6667 // CHECK4-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
6668 // CHECK4-NEXT:    store i16 [[TMP2]], i16* [[CONV]], align 2
6669 // CHECK4-NEXT:    [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
6670 // CHECK4-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
6671 // CHECK4-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40
6672 // CHECK4-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
6673 // CHECK4:       omp_if.then:
6674 // CHECK4-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
6675 // CHECK4-NEXT:    [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i32*
6676 // CHECK4-NEXT:    store i32 [[TMP1]], i32* [[TMP6]], align 4
6677 // CHECK4-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
6678 // CHECK4-NEXT:    [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32*
6679 // CHECK4-NEXT:    store i32 [[TMP1]], i32* [[TMP8]], align 4
6680 // CHECK4-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
6681 // CHECK4-NEXT:    store i8* null, i8** [[TMP9]], align 4
6682 // CHECK4-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
6683 // CHECK4-NEXT:    [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i32*
6684 // CHECK4-NEXT:    store i32 [[TMP3]], i32* [[TMP11]], align 4
6685 // CHECK4-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
6686 // CHECK4-NEXT:    [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32*
6687 // CHECK4-NEXT:    store i32 [[TMP3]], i32* [[TMP13]], align 4
6688 // CHECK4-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
6689 // CHECK4-NEXT:    store i8* null, i8** [[TMP14]], align 4
6690 // CHECK4-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
6691 // CHECK4-NEXT:    [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]**
6692 // CHECK4-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 4
6693 // CHECK4-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
6694 // CHECK4-NEXT:    [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]**
6695 // CHECK4-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 4
6696 // CHECK4-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
6697 // CHECK4-NEXT:    store i8* null, i8** [[TMP19]], align 4
6698 // CHECK4-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
6699 // CHECK4-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
6700 // CHECK4-NEXT:    call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10)
6701 // CHECK4-NEXT:    [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.17, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.18, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
6702 // CHECK4-NEXT:    [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0
6703 // CHECK4-NEXT:    br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
6704 // CHECK4:       omp_offload.failed:
6705 // CHECK4-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]]
6706 // CHECK4-NEXT:    br label [[OMP_OFFLOAD_CONT]]
6707 // CHECK4:       omp_offload.cont:
6708 // CHECK4-NEXT:    br label [[OMP_IF_END:%.*]]
6709 // CHECK4:       omp_if.else:
6710 // CHECK4-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]]
6711 // CHECK4-NEXT:    br label [[OMP_IF_END]]
6712 // CHECK4:       omp_if.end:
6713 // CHECK4-NEXT:    [[TMP24:%.*]] = load i32, i32* [[A]], align 4
6714 // CHECK4-NEXT:    ret i32 [[TMP24]]
6715 //
6716 //
6717 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218
6718 // CHECK4-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {
6719 // CHECK4-NEXT:  entry:
6720 // CHECK4-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
6721 // CHECK4-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
6722 // CHECK4-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
6723 // CHECK4-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
6724 // CHECK4-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 4
6725 // CHECK4-NEXT:    [[B_CASTED:%.*]] = alloca i32, align 4
6726 // CHECK4-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
6727 // CHECK4-NEXT:    store i32 [[B]], i32* [[B_ADDR]], align 4
6728 // CHECK4-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
6729 // CHECK4-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
6730 // CHECK4-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 4
6731 // CHECK4-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
6732 // CHECK4-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
6733 // CHECK4-NEXT:    [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
6734 // CHECK4-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
6735 // CHECK4-NEXT:    [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4
6736 // CHECK4-NEXT:    store i32 [[TMP4]], i32* [[B_CASTED]], align 4
6737 // CHECK4-NEXT:    [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4
6738 // CHECK4-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]])
6739 // CHECK4-NEXT:    ret void
6740 //
6741 //
6742 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..11
6743 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {
6744 // CHECK4-NEXT:  entry:
6745 // CHECK4-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
6746 // CHECK4-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
6747 // CHECK4-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
6748 // CHECK4-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
6749 // CHECK4-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
6750 // CHECK4-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
6751 // CHECK4-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 4
6752 // CHECK4-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
6753 // CHECK4-NEXT:    [[TMP:%.*]] = alloca i32, align 4
6754 // CHECK4-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
6755 // CHECK4-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
6756 // CHECK4-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
6757 // CHECK4-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
6758 // CHECK4-NEXT:    [[I:%.*]] = alloca i32, align 4
6759 // CHECK4-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
6760 // CHECK4-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
6761 // CHECK4-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
6762 // CHECK4-NEXT:    store i32 [[B]], i32* [[B_ADDR]], align 4
6763 // CHECK4-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
6764 // CHECK4-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
6765 // CHECK4-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 4
6766 // CHECK4-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
6767 // CHECK4-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
6768 // CHECK4-NEXT:    [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
6769 // CHECK4-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
6770 // CHECK4-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
6771 // CHECK4-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
6772 // CHECK4-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
6773 // CHECK4-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
6774 // CHECK4-NEXT:    [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
6775 // CHECK4-NEXT:    [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
6776 // CHECK4-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
6777 // CHECK4-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
6778 // CHECK4-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 9
6779 // CHECK4-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
6780 // CHECK4:       cond.true:
6781 // CHECK4-NEXT:    br label [[COND_END:%.*]]
6782 // CHECK4:       cond.false:
6783 // CHECK4-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
6784 // CHECK4-NEXT:    br label [[COND_END]]
6785 // CHECK4:       cond.end:
6786 // CHECK4-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
6787 // CHECK4-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
6788 // CHECK4-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
6789 // CHECK4-NEXT:    store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
6790 // CHECK4-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
6791 // CHECK4:       omp.inner.for.cond:
6792 // CHECK4-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
6793 // CHECK4-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
6794 // CHECK4-NEXT:    [[CMP3:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
6795 // CHECK4-NEXT:    br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
6796 // CHECK4:       omp.inner.for.body:
6797 // CHECK4-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
6798 // CHECK4-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
6799 // CHECK4-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
6800 // CHECK4-NEXT:    store i32 [[ADD]], i32* [[I]], align 4
6801 // CHECK4-NEXT:    [[TMP12:%.*]] = load i32, i32* [[B_ADDR]], align 4
6802 // CHECK4-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP12]] to double
6803 // CHECK4-NEXT:    [[ADD4:%.*]] = fadd double [[CONV]], 1.500000e+00
6804 // CHECK4-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
6805 // CHECK4-NEXT:    store double [[ADD4]], double* [[A]], align 4
6806 // CHECK4-NEXT:    [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
6807 // CHECK4-NEXT:    [[TMP13:%.*]] = load double, double* [[A5]], align 4
6808 // CHECK4-NEXT:    [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00
6809 // CHECK4-NEXT:    store double [[INC]], double* [[A5]], align 4
6810 // CHECK4-NEXT:    [[CONV6:%.*]] = fptosi double [[INC]] to i16
6811 // CHECK4-NEXT:    [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]]
6812 // CHECK4-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP14]]
6813 // CHECK4-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
6814 // CHECK4-NEXT:    store i16 [[CONV6]], i16* [[ARRAYIDX7]], align 2
6815 // CHECK4-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
6816 // CHECK4:       omp.body.continue:
6817 // CHECK4-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
6818 // CHECK4:       omp.inner.for.inc:
6819 // CHECK4-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
6820 // CHECK4-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP15]], 1
6821 // CHECK4-NEXT:    store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4
6822 // CHECK4-NEXT:    br label [[OMP_INNER_FOR_COND]]
6823 // CHECK4:       omp.inner.for.end:
6824 // CHECK4-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
6825 // CHECK4:       omp.loop.exit:
6826 // CHECK4-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
6827 // CHECK4-NEXT:    ret void
6828 //
6829 //
6830 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200
6831 // CHECK4-SAME: (i32 [[N:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
6832 // CHECK4-NEXT:  entry:
6833 // CHECK4-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
6834 // CHECK4-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
6835 // CHECK4-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
6836 // CHECK4-NEXT:    [[AAA_ADDR:%.*]] = alloca i32, align 4
6837 // CHECK4-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
6838 // CHECK4-NEXT:    [[N_CASTED:%.*]] = alloca i32, align 4
6839 // CHECK4-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
6840 // CHECK4-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
6841 // CHECK4-NEXT:    [[AAA_CASTED:%.*]] = alloca i32, align 4
6842 // CHECK4-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
6843 // CHECK4-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
6844 // CHECK4-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
6845 // CHECK4-NEXT:    store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
6846 // CHECK4-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
6847 // CHECK4-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
6848 // CHECK4-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
6849 // CHECK4-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
6850 // CHECK4-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
6851 // CHECK4-NEXT:    store i32 [[TMP1]], i32* [[N_CASTED]], align 4
6852 // CHECK4-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_CASTED]], align 4
6853 // CHECK4-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4
6854 // CHECK4-NEXT:    store i32 [[TMP3]], i32* [[A_CASTED]], align 4
6855 // CHECK4-NEXT:    [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4
6856 // CHECK4-NEXT:    [[TMP5:%.*]] = load i16, i16* [[CONV]], align 4
6857 // CHECK4-NEXT:    [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
6858 // CHECK4-NEXT:    store i16 [[TMP5]], i16* [[CONV2]], align 2
6859 // CHECK4-NEXT:    [[TMP6:%.*]] = load i32, i32* [[AA_CASTED]], align 4
6860 // CHECK4-NEXT:    [[TMP7:%.*]] = load i8, i8* [[CONV1]], align 4
6861 // CHECK4-NEXT:    [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
6862 // CHECK4-NEXT:    store i8 [[TMP7]], i8* [[CONV3]], align 1
6863 // CHECK4-NEXT:    [[TMP8:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
6864 // CHECK4-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, [10 x i32]*)* @.omp_outlined..13 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP8]], [10 x i32]* [[TMP0]])
6865 // CHECK4-NEXT:    ret void
6866 //
6867 //
6868 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..13
6869 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
6870 // CHECK4-NEXT:  entry:
6871 // CHECK4-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
6872 // CHECK4-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
6873 // CHECK4-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
6874 // CHECK4-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
6875 // CHECK4-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
6876 // CHECK4-NEXT:    [[AAA_ADDR:%.*]] = alloca i32, align 4
6877 // CHECK4-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
6878 // CHECK4-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
6879 // CHECK4-NEXT:    [[TMP:%.*]] = alloca i32, align 4
6880 // CHECK4-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
6881 // CHECK4-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
6882 // CHECK4-NEXT:    [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4
6883 // CHECK4-NEXT:    [[I:%.*]] = alloca i32, align 4
6884 // CHECK4-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
6885 // CHECK4-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
6886 // CHECK4-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
6887 // CHECK4-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
6888 // CHECK4-NEXT:    [[I6:%.*]] = alloca i32, align 4
6889 // CHECK4-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
6890 // CHECK4-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
6891 // CHECK4-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
6892 // CHECK4-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
6893 // CHECK4-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
6894 // CHECK4-NEXT:    store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
6895 // CHECK4-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
6896 // CHECK4-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
6897 // CHECK4-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
6898 // CHECK4-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
6899 // CHECK4-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
6900 // CHECK4-NEXT:    store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
6901 // CHECK4-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
6902 // CHECK4-NEXT:    store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4
6903 // CHECK4-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
6904 // CHECK4-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
6905 // CHECK4-NEXT:    [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]]
6906 // CHECK4-NEXT:    [[SUB4:%.*]] = sub i32 [[SUB]], 1
6907 // CHECK4-NEXT:    [[ADD:%.*]] = add i32 [[SUB4]], 1
6908 // CHECK4-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], 1
6909 // CHECK4-NEXT:    [[SUB5:%.*]] = sub i32 [[DIV]], 1
6910 // CHECK4-NEXT:    store i32 [[SUB5]], i32* [[DOTCAPTURE_EXPR_3]], align 4
6911 // CHECK4-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
6912 // CHECK4-NEXT:    store i32 [[TMP5]], i32* [[I]], align 4
6913 // CHECK4-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
6914 // CHECK4-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
6915 // CHECK4-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]]
6916 // CHECK4-NEXT:    br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
6917 // CHECK4:       omp.precond.then:
6918 // CHECK4-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
6919 // CHECK4-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
6920 // CHECK4-NEXT:    store i32 [[TMP8]], i32* [[DOTOMP_UB]], align 4
6921 // CHECK4-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
6922 // CHECK4-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
6923 // CHECK4-NEXT:    [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
6924 // CHECK4-NEXT:    [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
6925 // CHECK4-NEXT:    call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
6926 // CHECK4-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
6927 // CHECK4-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
6928 // CHECK4-NEXT:    [[CMP7:%.*]] = icmp ugt i32 [[TMP11]], [[TMP12]]
6929 // CHECK4-NEXT:    br i1 [[CMP7]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
6930 // CHECK4:       cond.true:
6931 // CHECK4-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
6932 // CHECK4-NEXT:    br label [[COND_END:%.*]]
6933 // CHECK4:       cond.false:
6934 // CHECK4-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
6935 // CHECK4-NEXT:    br label [[COND_END]]
6936 // CHECK4:       cond.end:
6937 // CHECK4-NEXT:    [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ]
6938 // CHECK4-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
6939 // CHECK4-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
6940 // CHECK4-NEXT:    store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4
6941 // CHECK4-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
6942 // CHECK4:       omp.inner.for.cond:
6943 // CHECK4-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
6944 // CHECK4-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
6945 // CHECK4-NEXT:    [[ADD8:%.*]] = add i32 [[TMP17]], 1
6946 // CHECK4-NEXT:    [[CMP9:%.*]] = icmp ult i32 [[TMP16]], [[ADD8]]
6947 // CHECK4-NEXT:    br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
6948 // CHECK4:       omp.inner.for.body:
6949 // CHECK4-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
6950 // CHECK4-NEXT:    [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
6951 // CHECK4-NEXT:    [[MUL:%.*]] = mul i32 [[TMP19]], 1
6952 // CHECK4-NEXT:    [[ADD10:%.*]] = add i32 [[TMP18]], [[MUL]]
6953 // CHECK4-NEXT:    store i32 [[ADD10]], i32* [[I6]], align 4
6954 // CHECK4-NEXT:    [[TMP20:%.*]] = load i32, i32* [[A_ADDR]], align 4
6955 // CHECK4-NEXT:    [[ADD11:%.*]] = add nsw i32 [[TMP20]], 1
6956 // CHECK4-NEXT:    store i32 [[ADD11]], i32* [[A_ADDR]], align 4
6957 // CHECK4-NEXT:    [[TMP21:%.*]] = load i16, i16* [[CONV]], align 4
6958 // CHECK4-NEXT:    [[CONV12:%.*]] = sext i16 [[TMP21]] to i32
6959 // CHECK4-NEXT:    [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1
6960 // CHECK4-NEXT:    [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16
6961 // CHECK4-NEXT:    store i16 [[CONV14]], i16* [[CONV]], align 4
6962 // CHECK4-NEXT:    [[TMP22:%.*]] = load i8, i8* [[CONV1]], align 4
6963 // CHECK4-NEXT:    [[CONV15:%.*]] = sext i8 [[TMP22]] to i32
6964 // CHECK4-NEXT:    [[ADD16:%.*]] = add nsw i32 [[CONV15]], 1
6965 // CHECK4-NEXT:    [[CONV17:%.*]] = trunc i32 [[ADD16]] to i8
6966 // CHECK4-NEXT:    store i8 [[CONV17]], i8* [[CONV1]], align 4
6967 // CHECK4-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
6968 // CHECK4-NEXT:    [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
6969 // CHECK4-NEXT:    [[ADD18:%.*]] = add nsw i32 [[TMP23]], 1
6970 // CHECK4-NEXT:    store i32 [[ADD18]], i32* [[ARRAYIDX]], align 4
6971 // CHECK4-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
6972 // CHECK4:       omp.body.continue:
6973 // CHECK4-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
6974 // CHECK4:       omp.inner.for.inc:
6975 // CHECK4-NEXT:    [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
6976 // CHECK4-NEXT:    [[ADD19:%.*]] = add i32 [[TMP24]], 1
6977 // CHECK4-NEXT:    store i32 [[ADD19]], i32* [[DOTOMP_IV]], align 4
6978 // CHECK4-NEXT:    br label [[OMP_INNER_FOR_COND]]
6979 // CHECK4:       omp.inner.for.end:
6980 // CHECK4-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
6981 // CHECK4:       omp.loop.exit:
6982 // CHECK4-NEXT:    [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
6983 // CHECK4-NEXT:    [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4
6984 // CHECK4-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]])
6985 // CHECK4-NEXT:    br label [[OMP_PRECOND_END]]
6986 // CHECK4:       omp.precond.end:
6987 // CHECK4-NEXT:    ret void
6988 //
6989 //
6990 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183
6991 // CHECK4-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
6992 // CHECK4-NEXT:  entry:
6993 // CHECK4-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
6994 // CHECK4-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
6995 // CHECK4-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
6996 // CHECK4-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
6997 // CHECK4-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
6998 // CHECK4-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
6999 // CHECK4-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
7000 // CHECK4-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
7001 // CHECK4-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
7002 // CHECK4-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
7003 // CHECK4-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
7004 // CHECK4-NEXT:    store i32 [[TMP1]], i32* [[A_CASTED]], align 4
7005 // CHECK4-NEXT:    [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
7006 // CHECK4-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
7007 // CHECK4-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
7008 // CHECK4-NEXT:    store i16 [[TMP3]], i16* [[CONV1]], align 2
7009 // CHECK4-NEXT:    [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
7010 // CHECK4-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]])
7011 // CHECK4-NEXT:    ret void
7012 //
7013 //
7014 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..16
7015 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
7016 // CHECK4-NEXT:  entry:
7017 // CHECK4-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
7018 // CHECK4-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
7019 // CHECK4-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
7020 // CHECK4-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
7021 // CHECK4-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
7022 // CHECK4-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
7023 // CHECK4-NEXT:    [[TMP:%.*]] = alloca i32, align 4
7024 // CHECK4-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
7025 // CHECK4-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
7026 // CHECK4-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
7027 // CHECK4-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
7028 // CHECK4-NEXT:    [[I:%.*]] = alloca i32, align 4
7029 // CHECK4-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
7030 // CHECK4-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
7031 // CHECK4-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
7032 // CHECK4-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
7033 // CHECK4-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
7034 // CHECK4-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
7035 // CHECK4-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
7036 // CHECK4-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
7037 // CHECK4-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
7038 // CHECK4-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
7039 // CHECK4-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
7040 // CHECK4-NEXT:    [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
7041 // CHECK4-NEXT:    [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
7042 // CHECK4-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
7043 // CHECK4-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
7044 // CHECK4-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9
7045 // CHECK4-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
7046 // CHECK4:       cond.true:
7047 // CHECK4-NEXT:    br label [[COND_END:%.*]]
7048 // CHECK4:       cond.false:
7049 // CHECK4-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
7050 // CHECK4-NEXT:    br label [[COND_END]]
7051 // CHECK4:       cond.end:
7052 // CHECK4-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
7053 // CHECK4-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
7054 // CHECK4-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
7055 // CHECK4-NEXT:    store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
7056 // CHECK4-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
7057 // CHECK4:       omp.inner.for.cond:
7058 // CHECK4-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
7059 // CHECK4-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
7060 // CHECK4-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
7061 // CHECK4-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
7062 // CHECK4:       omp.inner.for.body:
7063 // CHECK4-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
7064 // CHECK4-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
7065 // CHECK4-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
7066 // CHECK4-NEXT:    store i32 [[ADD]], i32* [[I]], align 4
7067 // CHECK4-NEXT:    [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4
7068 // CHECK4-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
7069 // CHECK4-NEXT:    store i32 [[ADD2]], i32* [[A_ADDR]], align 4
7070 // CHECK4-NEXT:    [[TMP10:%.*]] = load i16, i16* [[CONV]], align 4
7071 // CHECK4-NEXT:    [[CONV3:%.*]] = sext i16 [[TMP10]] to i32
7072 // CHECK4-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
7073 // CHECK4-NEXT:    [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
7074 // CHECK4-NEXT:    store i16 [[CONV5]], i16* [[CONV]], align 4
7075 // CHECK4-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
7076 // CHECK4-NEXT:    [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
7077 // CHECK4-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1
7078 // CHECK4-NEXT:    store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4
7079 // CHECK4-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
7080 // CHECK4:       omp.body.continue:
7081 // CHECK4-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
7082 // CHECK4:       omp.inner.for.inc:
7083 // CHECK4-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
7084 // CHECK4-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP12]], 1
7085 // CHECK4-NEXT:    store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4
7086 // CHECK4-NEXT:    br label [[OMP_INNER_FOR_COND]]
7087 // CHECK4:       omp.inner.for.end:
7088 // CHECK4-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
7089 // CHECK4:       omp.loop.exit:
7090 // CHECK4-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
7091 // CHECK4-NEXT:    ret void
7092 //
7093 //
7094 // CHECK4-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
7095 // CHECK4-SAME: () #[[ATTR4]] {
7096 // CHECK4-NEXT:  entry:
7097 // CHECK4-NEXT:    call void @__tgt_register_requires(i64 1)
7098 // CHECK4-NEXT:    ret void
7099 //
7100 //
7101 // CHECK5-LABEL: define {{[^@]+}}@_Z3fooi
7102 // CHECK5-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] {
7103 // CHECK5-NEXT:  entry:
7104 // CHECK5-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
7105 // CHECK5-NEXT:    [[A:%.*]] = alloca i32, align 4
7106 // CHECK5-NEXT:    [[AA:%.*]] = alloca i16, align 2
7107 // CHECK5-NEXT:    [[B:%.*]] = alloca [10 x float], align 4
7108 // CHECK5-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 8
7109 // CHECK5-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
7110 // CHECK5-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 8
7111 // CHECK5-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i64, align 8
7112 // CHECK5-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8
7113 // CHECK5-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
7114 // CHECK5-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
7115 // CHECK5-NEXT:    [[I:%.*]] = alloca i32, align 4
7116 // CHECK5-NEXT:    [[I3:%.*]] = alloca i32, align 4
7117 // CHECK5-NEXT:    [[I10:%.*]] = alloca i32, align 4
7118 // CHECK5-NEXT:    [[I19:%.*]] = alloca i32, align 4
7119 // CHECK5-NEXT:    [[DOTCAPTURE_EXPR_30:%.*]] = alloca i32, align 4
7120 // CHECK5-NEXT:    [[I31:%.*]] = alloca i32, align 4
7121 // CHECK5-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
7122 // CHECK5-NEXT:    store i32 0, i32* [[A]], align 4
7123 // CHECK5-NEXT:    store i16 0, i16* [[AA]], align 2
7124 // CHECK5-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
7125 // CHECK5-NEXT:    [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
7126 // CHECK5-NEXT:    [[TMP2:%.*]] = call i8* @llvm.stacksave()
7127 // CHECK5-NEXT:    store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8
7128 // CHECK5-NEXT:    [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4
7129 // CHECK5-NEXT:    store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8
7130 // CHECK5-NEXT:    [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
7131 // CHECK5-NEXT:    [[TMP4:%.*]] = zext i32 [[TMP3]] to i64
7132 // CHECK5-NEXT:    [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]]
7133 // CHECK5-NEXT:    [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8
7134 // CHECK5-NEXT:    store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8
7135 // CHECK5-NEXT:    [[TMP6:%.*]] = load i32, i32* [[A]], align 4
7136 // CHECK5-NEXT:    store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_]], align 4
7137 // CHECK5-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
7138 // CHECK5-NEXT:    store i32 [[TMP7]], i32* [[DOTCAPTURE_EXPR_2]], align 4
7139 // CHECK5-NEXT:    store i32 0, i32* [[I]], align 4
7140 // CHECK5-NEXT:    br label [[FOR_COND:%.*]]
7141 // CHECK5:       for.cond:
7142 // CHECK5-NEXT:    [[TMP8:%.*]] = load i32, i32* [[I]], align 4
7143 // CHECK5-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP8]], 10
7144 // CHECK5-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
7145 // CHECK5:       for.body:
7146 // CHECK5-NEXT:    br label [[FOR_INC:%.*]]
7147 // CHECK5:       for.inc:
7148 // CHECK5-NEXT:    [[TMP9:%.*]] = load i32, i32* [[I]], align 4
7149 // CHECK5-NEXT:    [[INC:%.*]] = add nsw i32 [[TMP9]], 1
7150 // CHECK5-NEXT:    store i32 [[INC]], i32* [[I]], align 4
7151 // CHECK5-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]]
7152 // CHECK5:       for.end:
7153 // CHECK5-NEXT:    store i32 0, i32* [[I3]], align 4
7154 // CHECK5-NEXT:    br label [[FOR_COND4:%.*]]
7155 // CHECK5:       for.cond4:
7156 // CHECK5-NEXT:    [[TMP10:%.*]] = load i32, i32* [[I3]], align 4
7157 // CHECK5-NEXT:    [[CMP5:%.*]] = icmp slt i32 [[TMP10]], 10
7158 // CHECK5-NEXT:    br i1 [[CMP5]], label [[FOR_BODY6:%.*]], label [[FOR_END9:%.*]]
7159 // CHECK5:       for.body6:
7160 // CHECK5-NEXT:    [[TMP11:%.*]] = load i32, i32* [[A]], align 4
7161 // CHECK5-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP11]], 1
7162 // CHECK5-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
7163 // CHECK5-NEXT:    br label [[FOR_INC7:%.*]]
7164 // CHECK5:       for.inc7:
7165 // CHECK5-NEXT:    [[TMP12:%.*]] = load i32, i32* [[I3]], align 4
7166 // CHECK5-NEXT:    [[INC8:%.*]] = add nsw i32 [[TMP12]], 1
7167 // CHECK5-NEXT:    store i32 [[INC8]], i32* [[I3]], align 4
7168 // CHECK5-NEXT:    br label [[FOR_COND4]], !llvm.loop [[LOOP4:![0-9]+]]
7169 // CHECK5:       for.end9:
7170 // CHECK5-NEXT:    store i32 0, i32* [[I10]], align 4
7171 // CHECK5-NEXT:    br label [[FOR_COND11:%.*]]
7172 // CHECK5:       for.cond11:
7173 // CHECK5-NEXT:    [[TMP13:%.*]] = load i32, i32* [[I10]], align 4
7174 // CHECK5-NEXT:    [[CMP12:%.*]] = icmp slt i32 [[TMP13]], 10
7175 // CHECK5-NEXT:    br i1 [[CMP12]], label [[FOR_BODY13:%.*]], label [[FOR_END18:%.*]]
7176 // CHECK5:       for.body13:
7177 // CHECK5-NEXT:    [[TMP14:%.*]] = load i16, i16* [[AA]], align 2
7178 // CHECK5-NEXT:    [[CONV:%.*]] = sext i16 [[TMP14]] to i32
7179 // CHECK5-NEXT:    [[ADD14:%.*]] = add nsw i32 [[CONV]], 1
7180 // CHECK5-NEXT:    [[CONV15:%.*]] = trunc i32 [[ADD14]] to i16
7181 // CHECK5-NEXT:    store i16 [[CONV15]], i16* [[AA]], align 2
7182 // CHECK5-NEXT:    br label [[FOR_INC16:%.*]]
7183 // CHECK5:       for.inc16:
7184 // CHECK5-NEXT:    [[TMP15:%.*]] = load i32, i32* [[I10]], align 4
7185 // CHECK5-NEXT:    [[INC17:%.*]] = add nsw i32 [[TMP15]], 1
7186 // CHECK5-NEXT:    store i32 [[INC17]], i32* [[I10]], align 4
7187 // CHECK5-NEXT:    br label [[FOR_COND11]], !llvm.loop [[LOOP5:![0-9]+]]
7188 // CHECK5:       for.end18:
7189 // CHECK5-NEXT:    store i32 0, i32* [[I19]], align 4
7190 // CHECK5-NEXT:    br label [[FOR_COND20:%.*]]
7191 // CHECK5:       for.cond20:
7192 // CHECK5-NEXT:    [[TMP16:%.*]] = load i32, i32* [[I19]], align 4
7193 // CHECK5-NEXT:    [[CMP21:%.*]] = icmp slt i32 [[TMP16]], 10
7194 // CHECK5-NEXT:    br i1 [[CMP21]], label [[FOR_BODY22:%.*]], label [[FOR_END29:%.*]]
7195 // CHECK5:       for.body22:
7196 // CHECK5-NEXT:    [[TMP17:%.*]] = load i32, i32* [[A]], align 4
7197 // CHECK5-NEXT:    [[ADD23:%.*]] = add nsw i32 [[TMP17]], 1
7198 // CHECK5-NEXT:    store i32 [[ADD23]], i32* [[A]], align 4
7199 // CHECK5-NEXT:    [[TMP18:%.*]] = load i16, i16* [[AA]], align 2
7200 // CHECK5-NEXT:    [[CONV24:%.*]] = sext i16 [[TMP18]] to i32
7201 // CHECK5-NEXT:    [[ADD25:%.*]] = add nsw i32 [[CONV24]], 1
7202 // CHECK5-NEXT:    [[CONV26:%.*]] = trunc i32 [[ADD25]] to i16
7203 // CHECK5-NEXT:    store i16 [[CONV26]], i16* [[AA]], align 2
7204 // CHECK5-NEXT:    br label [[FOR_INC27:%.*]]
7205 // CHECK5:       for.inc27:
7206 // CHECK5-NEXT:    [[TMP19:%.*]] = load i32, i32* [[I19]], align 4
7207 // CHECK5-NEXT:    [[INC28:%.*]] = add nsw i32 [[TMP19]], 1
7208 // CHECK5-NEXT:    store i32 [[INC28]], i32* [[I19]], align 4
7209 // CHECK5-NEXT:    br label [[FOR_COND20]], !llvm.loop [[LOOP6:![0-9]+]]
7210 // CHECK5:       for.end29:
7211 // CHECK5-NEXT:    [[TMP20:%.*]] = load i32, i32* [[N_ADDR]], align 4
7212 // CHECK5-NEXT:    store i32 [[TMP20]], i32* [[DOTCAPTURE_EXPR_30]], align 4
7213 // CHECK5-NEXT:    store i32 0, i32* [[I31]], align 4
7214 // CHECK5-NEXT:    br label [[FOR_COND32:%.*]]
7215 // CHECK5:       for.cond32:
7216 // CHECK5-NEXT:    [[TMP21:%.*]] = load i32, i32* [[I31]], align 4
7217 // CHECK5-NEXT:    [[CMP33:%.*]] = icmp slt i32 [[TMP21]], 10
7218 // CHECK5-NEXT:    br i1 [[CMP33]], label [[FOR_BODY34:%.*]], label [[FOR_END55:%.*]]
7219 // CHECK5:       for.body34:
7220 // CHECK5-NEXT:    [[TMP22:%.*]] = load i32, i32* [[A]], align 4
7221 // CHECK5-NEXT:    [[ADD35:%.*]] = add nsw i32 [[TMP22]], 1
7222 // CHECK5-NEXT:    store i32 [[ADD35]], i32* [[A]], align 4
7223 // CHECK5-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2
7224 // CHECK5-NEXT:    [[TMP23:%.*]] = load float, float* [[ARRAYIDX]], align 4
7225 // CHECK5-NEXT:    [[CONV36:%.*]] = fpext float [[TMP23]] to double
7226 // CHECK5-NEXT:    [[ADD37:%.*]] = fadd double [[CONV36]], 1.000000e+00
7227 // CHECK5-NEXT:    [[CONV38:%.*]] = fptrunc double [[ADD37]] to float
7228 // CHECK5-NEXT:    store float [[CONV38]], float* [[ARRAYIDX]], align 4
7229 // CHECK5-NEXT:    [[ARRAYIDX39:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3
7230 // CHECK5-NEXT:    [[TMP24:%.*]] = load float, float* [[ARRAYIDX39]], align 4
7231 // CHECK5-NEXT:    [[CONV40:%.*]] = fpext float [[TMP24]] to double
7232 // CHECK5-NEXT:    [[ADD41:%.*]] = fadd double [[CONV40]], 1.000000e+00
7233 // CHECK5-NEXT:    [[CONV42:%.*]] = fptrunc double [[ADD41]] to float
7234 // CHECK5-NEXT:    store float [[CONV42]], float* [[ARRAYIDX39]], align 4
7235 // CHECK5-NEXT:    [[ARRAYIDX43:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1
7236 // CHECK5-NEXT:    [[ARRAYIDX44:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX43]], i64 0, i64 2
7237 // CHECK5-NEXT:    [[TMP25:%.*]] = load double, double* [[ARRAYIDX44]], align 8
7238 // CHECK5-NEXT:    [[ADD45:%.*]] = fadd double [[TMP25]], 1.000000e+00
7239 // CHECK5-NEXT:    store double [[ADD45]], double* [[ARRAYIDX44]], align 8
7240 // CHECK5-NEXT:    [[TMP26:%.*]] = mul nsw i64 1, [[TMP4]]
7241 // CHECK5-NEXT:    [[ARRAYIDX46:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP26]]
7242 // CHECK5-NEXT:    [[ARRAYIDX47:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX46]], i64 3
7243 // CHECK5-NEXT:    [[TMP27:%.*]] = load double, double* [[ARRAYIDX47]], align 8
7244 // CHECK5-NEXT:    [[ADD48:%.*]] = fadd double [[TMP27]], 1.000000e+00
7245 // CHECK5-NEXT:    store double [[ADD48]], double* [[ARRAYIDX47]], align 8
7246 // CHECK5-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0
7247 // CHECK5-NEXT:    [[TMP28:%.*]] = load i64, i64* [[X]], align 8
7248 // CHECK5-NEXT:    [[ADD49:%.*]] = add nsw i64 [[TMP28]], 1
7249 // CHECK5-NEXT:    store i64 [[ADD49]], i64* [[X]], align 8
7250 // CHECK5-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1
7251 // CHECK5-NEXT:    [[TMP29:%.*]] = load i8, i8* [[Y]], align 8
7252 // CHECK5-NEXT:    [[CONV50:%.*]] = sext i8 [[TMP29]] to i32
7253 // CHECK5-NEXT:    [[ADD51:%.*]] = add nsw i32 [[CONV50]], 1
7254 // CHECK5-NEXT:    [[CONV52:%.*]] = trunc i32 [[ADD51]] to i8
7255 // CHECK5-NEXT:    store i8 [[CONV52]], i8* [[Y]], align 8
7256 // CHECK5-NEXT:    br label [[FOR_INC53:%.*]]
7257 // CHECK5:       for.inc53:
7258 // CHECK5-NEXT:    [[TMP30:%.*]] = load i32, i32* [[I31]], align 4
7259 // CHECK5-NEXT:    [[INC54:%.*]] = add nsw i32 [[TMP30]], 1
7260 // CHECK5-NEXT:    store i32 [[INC54]], i32* [[I31]], align 4
7261 // CHECK5-NEXT:    br label [[FOR_COND32]], !llvm.loop [[LOOP7:![0-9]+]]
7262 // CHECK5:       for.end55:
7263 // CHECK5-NEXT:    [[TMP31:%.*]] = load i32, i32* [[A]], align 4
7264 // CHECK5-NEXT:    [[TMP32:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
7265 // CHECK5-NEXT:    call void @llvm.stackrestore(i8* [[TMP32]])
7266 // CHECK5-NEXT:    ret i32 [[TMP31]]
7267 //
7268 //
7269 // CHECK5-LABEL: define {{[^@]+}}@_Z3bari
7270 // CHECK5-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
7271 // CHECK5-NEXT:  entry:
7272 // CHECK5-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
7273 // CHECK5-NEXT:    [[A:%.*]] = alloca i32, align 4
7274 // CHECK5-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8
7275 // CHECK5-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
7276 // CHECK5-NEXT:    store i32 0, i32* [[A]], align 4
7277 // CHECK5-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
7278 // CHECK5-NEXT:    [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]])
7279 // CHECK5-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
7280 // CHECK5-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
7281 // CHECK5-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
7282 // CHECK5-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
7283 // CHECK5-NEXT:    [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]])
7284 // CHECK5-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
7285 // CHECK5-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
7286 // CHECK5-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
7287 // CHECK5-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
7288 // CHECK5-NEXT:    [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]])
7289 // CHECK5-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
7290 // CHECK5-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
7291 // CHECK5-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
7292 // CHECK5-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
7293 // CHECK5-NEXT:    [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]])
7294 // CHECK5-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
7295 // CHECK5-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
7296 // CHECK5-NEXT:    store i32 [[ADD6]], i32* [[A]], align 4
7297 // CHECK5-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
7298 // CHECK5-NEXT:    ret i32 [[TMP8]]
7299 //
7300 //
7301 // CHECK5-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
7302 // CHECK5-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 {
7303 // CHECK5-NEXT:  entry:
7304 // CHECK5-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
7305 // CHECK5-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
7306 // CHECK5-NEXT:    [[B:%.*]] = alloca i32, align 4
7307 // CHECK5-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 8
7308 // CHECK5-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
7309 // CHECK5-NEXT:    [[I:%.*]] = alloca i32, align 4
7310 // CHECK5-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
7311 // CHECK5-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
7312 // CHECK5-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
7313 // CHECK5-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
7314 // CHECK5-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
7315 // CHECK5-NEXT:    store i32 [[ADD]], i32* [[B]], align 4
7316 // CHECK5-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
7317 // CHECK5-NEXT:    [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
7318 // CHECK5-NEXT:    [[TMP3:%.*]] = call i8* @llvm.stacksave()
7319 // CHECK5-NEXT:    store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8
7320 // CHECK5-NEXT:    [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]
7321 // CHECK5-NEXT:    [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2
7322 // CHECK5-NEXT:    store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8
7323 // CHECK5-NEXT:    store i32 0, i32* [[I]], align 4
7324 // CHECK5-NEXT:    br label [[FOR_COND:%.*]]
7325 // CHECK5:       for.cond:
7326 // CHECK5-NEXT:    [[TMP5:%.*]] = load i32, i32* [[I]], align 4
7327 // CHECK5-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP5]], 10
7328 // CHECK5-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
7329 // CHECK5:       for.body:
7330 // CHECK5-NEXT:    [[TMP6:%.*]] = load i32, i32* [[B]], align 4
7331 // CHECK5-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP6]] to double
7332 // CHECK5-NEXT:    [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00
7333 // CHECK5-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
7334 // CHECK5-NEXT:    store double [[ADD2]], double* [[A]], align 8
7335 // CHECK5-NEXT:    [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
7336 // CHECK5-NEXT:    [[TMP7:%.*]] = load double, double* [[A3]], align 8
7337 // CHECK5-NEXT:    [[INC:%.*]] = fadd double [[TMP7]], 1.000000e+00
7338 // CHECK5-NEXT:    store double [[INC]], double* [[A3]], align 8
7339 // CHECK5-NEXT:    [[CONV4:%.*]] = fptosi double [[INC]] to i16
7340 // CHECK5-NEXT:    [[TMP8:%.*]] = mul nsw i64 1, [[TMP2]]
7341 // CHECK5-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP8]]
7342 // CHECK5-NEXT:    [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
7343 // CHECK5-NEXT:    store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2
7344 // CHECK5-NEXT:    br label [[FOR_INC:%.*]]
7345 // CHECK5:       for.inc:
7346 // CHECK5-NEXT:    [[TMP9:%.*]] = load i32, i32* [[I]], align 4
7347 // CHECK5-NEXT:    [[INC6:%.*]] = add nsw i32 [[TMP9]], 1
7348 // CHECK5-NEXT:    store i32 [[INC6]], i32* [[I]], align 4
7349 // CHECK5-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]]
7350 // CHECK5:       for.end:
7351 // CHECK5-NEXT:    [[TMP10:%.*]] = mul nsw i64 1, [[TMP2]]
7352 // CHECK5-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP10]]
7353 // CHECK5-NEXT:    [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX7]], i64 1
7354 // CHECK5-NEXT:    [[TMP11:%.*]] = load i16, i16* [[ARRAYIDX8]], align 2
7355 // CHECK5-NEXT:    [[CONV9:%.*]] = sext i16 [[TMP11]] to i32
7356 // CHECK5-NEXT:    [[TMP12:%.*]] = load i32, i32* [[B]], align 4
7357 // CHECK5-NEXT:    [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[TMP12]]
7358 // CHECK5-NEXT:    [[TMP13:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
7359 // CHECK5-NEXT:    call void @llvm.stackrestore(i8* [[TMP13]])
7360 // CHECK5-NEXT:    ret i32 [[ADD10]]
7361 //
7362 //
7363 // CHECK5-LABEL: define {{[^@]+}}@_ZL7fstatici
7364 // CHECK5-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
7365 // CHECK5-NEXT:  entry:
7366 // CHECK5-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
7367 // CHECK5-NEXT:    [[A:%.*]] = alloca i32, align 4
7368 // CHECK5-NEXT:    [[AA:%.*]] = alloca i16, align 2
7369 // CHECK5-NEXT:    [[AAA:%.*]] = alloca i8, align 1
7370 // CHECK5-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
7371 // CHECK5-NEXT:    [[I:%.*]] = alloca i32, align 4
7372 // CHECK5-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
7373 // CHECK5-NEXT:    store i32 0, i32* [[A]], align 4
7374 // CHECK5-NEXT:    store i16 0, i16* [[AA]], align 2
7375 // CHECK5-NEXT:    store i8 0, i8* [[AAA]], align 1
7376 // CHECK5-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
7377 // CHECK5-NEXT:    store i32 [[TMP0]], i32* [[I]], align 4
7378 // CHECK5-NEXT:    br label [[FOR_COND:%.*]]
7379 // CHECK5:       for.cond:
7380 // CHECK5-NEXT:    [[TMP1:%.*]] = load i32, i32* [[I]], align 4
7381 // CHECK5-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
7382 // CHECK5-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP1]], [[TMP2]]
7383 // CHECK5-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
7384 // CHECK5:       for.body:
7385 // CHECK5-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
7386 // CHECK5-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP3]], 1
7387 // CHECK5-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
7388 // CHECK5-NEXT:    [[TMP4:%.*]] = load i16, i16* [[AA]], align 2
7389 // CHECK5-NEXT:    [[CONV:%.*]] = sext i16 [[TMP4]] to i32
7390 // CHECK5-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
7391 // CHECK5-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
7392 // CHECK5-NEXT:    store i16 [[CONV2]], i16* [[AA]], align 2
7393 // CHECK5-NEXT:    [[TMP5:%.*]] = load i8, i8* [[AAA]], align 1
7394 // CHECK5-NEXT:    [[CONV3:%.*]] = sext i8 [[TMP5]] to i32
7395 // CHECK5-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
7396 // CHECK5-NEXT:    [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8
7397 // CHECK5-NEXT:    store i8 [[CONV5]], i8* [[AAA]], align 1
7398 // CHECK5-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2
7399 // CHECK5-NEXT:    [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
7400 // CHECK5-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP6]], 1
7401 // CHECK5-NEXT:    store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4
7402 // CHECK5-NEXT:    br label [[FOR_INC:%.*]]
7403 // CHECK5:       for.inc:
7404 // CHECK5-NEXT:    [[TMP7:%.*]] = load i32, i32* [[I]], align 4
7405 // CHECK5-NEXT:    [[INC:%.*]] = add nsw i32 [[TMP7]], 1
7406 // CHECK5-NEXT:    store i32 [[INC]], i32* [[I]], align 4
7407 // CHECK5-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]
7408 // CHECK5:       for.end:
7409 // CHECK5-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
7410 // CHECK5-NEXT:    ret i32 [[TMP8]]
7411 //
7412 //
7413 // CHECK5-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
7414 // CHECK5-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat {
7415 // CHECK5-NEXT:  entry:
7416 // CHECK5-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
7417 // CHECK5-NEXT:    [[A:%.*]] = alloca i32, align 4
7418 // CHECK5-NEXT:    [[AA:%.*]] = alloca i16, align 2
7419 // CHECK5-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
7420 // CHECK5-NEXT:    [[I:%.*]] = alloca i32, align 4
7421 // CHECK5-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
7422 // CHECK5-NEXT:    store i32 0, i32* [[A]], align 4
7423 // CHECK5-NEXT:    store i16 0, i16* [[AA]], align 2
7424 // CHECK5-NEXT:    store i32 0, i32* [[I]], align 4
7425 // CHECK5-NEXT:    br label [[FOR_COND:%.*]]
7426 // CHECK5:       for.cond:
7427 // CHECK5-NEXT:    [[TMP0:%.*]] = load i32, i32* [[I]], align 4
7428 // CHECK5-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10
7429 // CHECK5-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
7430 // CHECK5:       for.body:
7431 // CHECK5-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
7432 // CHECK5-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
7433 // CHECK5-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
7434 // CHECK5-NEXT:    [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
7435 // CHECK5-NEXT:    [[CONV:%.*]] = sext i16 [[TMP2]] to i32
7436 // CHECK5-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
7437 // CHECK5-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
7438 // CHECK5-NEXT:    store i16 [[CONV2]], i16* [[AA]], align 2
7439 // CHECK5-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2
7440 // CHECK5-NEXT:    [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
7441 // CHECK5-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1
7442 // CHECK5-NEXT:    store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4
7443 // CHECK5-NEXT:    br label [[FOR_INC:%.*]]
7444 // CHECK5:       for.inc:
7445 // CHECK5-NEXT:    [[TMP4:%.*]] = load i32, i32* [[I]], align 4
7446 // CHECK5-NEXT:    [[INC:%.*]] = add nsw i32 [[TMP4]], 1
7447 // CHECK5-NEXT:    store i32 [[INC]], i32* [[I]], align 4
7448 // CHECK5-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]
7449 // CHECK5:       for.end:
7450 // CHECK5-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
7451 // CHECK5-NEXT:    ret i32 [[TMP5]]
7452 //
7453 //
7454 // CHECK6-LABEL: define {{[^@]+}}@_Z3fooi
7455 // CHECK6-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] {
7456 // CHECK6-NEXT:  entry:
7457 // CHECK6-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
7458 // CHECK6-NEXT:    [[A:%.*]] = alloca i32, align 4
7459 // CHECK6-NEXT:    [[AA:%.*]] = alloca i16, align 2
7460 // CHECK6-NEXT:    [[B:%.*]] = alloca [10 x float], align 4
7461 // CHECK6-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 8
7462 // CHECK6-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
7463 // CHECK6-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 8
7464 // CHECK6-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i64, align 8
7465 // CHECK6-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8
7466 // CHECK6-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
7467 // CHECK6-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
7468 // CHECK6-NEXT:    [[I:%.*]] = alloca i32, align 4
7469 // CHECK6-NEXT:    [[I3:%.*]] = alloca i32, align 4
7470 // CHECK6-NEXT:    [[I10:%.*]] = alloca i32, align 4
7471 // CHECK6-NEXT:    [[I19:%.*]] = alloca i32, align 4
7472 // CHECK6-NEXT:    [[DOTCAPTURE_EXPR_30:%.*]] = alloca i32, align 4
7473 // CHECK6-NEXT:    [[I31:%.*]] = alloca i32, align 4
7474 // CHECK6-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
7475 // CHECK6-NEXT:    store i32 0, i32* [[A]], align 4
7476 // CHECK6-NEXT:    store i16 0, i16* [[AA]], align 2
7477 // CHECK6-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
7478 // CHECK6-NEXT:    [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
7479 // CHECK6-NEXT:    [[TMP2:%.*]] = call i8* @llvm.stacksave()
7480 // CHECK6-NEXT:    store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8
7481 // CHECK6-NEXT:    [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4
7482 // CHECK6-NEXT:    store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8
7483 // CHECK6-NEXT:    [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
7484 // CHECK6-NEXT:    [[TMP4:%.*]] = zext i32 [[TMP3]] to i64
7485 // CHECK6-NEXT:    [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]]
7486 // CHECK6-NEXT:    [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8
7487 // CHECK6-NEXT:    store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8
7488 // CHECK6-NEXT:    [[TMP6:%.*]] = load i32, i32* [[A]], align 4
7489 // CHECK6-NEXT:    store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_]], align 4
7490 // CHECK6-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
7491 // CHECK6-NEXT:    store i32 [[TMP7]], i32* [[DOTCAPTURE_EXPR_2]], align 4
7492 // CHECK6-NEXT:    store i32 0, i32* [[I]], align 4
7493 // CHECK6-NEXT:    br label [[FOR_COND:%.*]]
7494 // CHECK6:       for.cond:
7495 // CHECK6-NEXT:    [[TMP8:%.*]] = load i32, i32* [[I]], align 4
7496 // CHECK6-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP8]], 10
7497 // CHECK6-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
7498 // CHECK6:       for.body:
7499 // CHECK6-NEXT:    br label [[FOR_INC:%.*]]
7500 // CHECK6:       for.inc:
7501 // CHECK6-NEXT:    [[TMP9:%.*]] = load i32, i32* [[I]], align 4
7502 // CHECK6-NEXT:    [[INC:%.*]] = add nsw i32 [[TMP9]], 1
7503 // CHECK6-NEXT:    store i32 [[INC]], i32* [[I]], align 4
7504 // CHECK6-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]]
7505 // CHECK6:       for.end:
7506 // CHECK6-NEXT:    store i32 0, i32* [[I3]], align 4
7507 // CHECK6-NEXT:    br label [[FOR_COND4:%.*]]
7508 // CHECK6:       for.cond4:
7509 // CHECK6-NEXT:    [[TMP10:%.*]] = load i32, i32* [[I3]], align 4
7510 // CHECK6-NEXT:    [[CMP5:%.*]] = icmp slt i32 [[TMP10]], 10
7511 // CHECK6-NEXT:    br i1 [[CMP5]], label [[FOR_BODY6:%.*]], label [[FOR_END9:%.*]]
7512 // CHECK6:       for.body6:
7513 // CHECK6-NEXT:    [[TMP11:%.*]] = load i32, i32* [[A]], align 4
7514 // CHECK6-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP11]], 1
7515 // CHECK6-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
7516 // CHECK6-NEXT:    br label [[FOR_INC7:%.*]]
7517 // CHECK6:       for.inc7:
7518 // CHECK6-NEXT:    [[TMP12:%.*]] = load i32, i32* [[I3]], align 4
7519 // CHECK6-NEXT:    [[INC8:%.*]] = add nsw i32 [[TMP12]], 1
7520 // CHECK6-NEXT:    store i32 [[INC8]], i32* [[I3]], align 4
7521 // CHECK6-NEXT:    br label [[FOR_COND4]], !llvm.loop [[LOOP4:![0-9]+]]
7522 // CHECK6:       for.end9:
7523 // CHECK6-NEXT:    store i32 0, i32* [[I10]], align 4
7524 // CHECK6-NEXT:    br label [[FOR_COND11:%.*]]
7525 // CHECK6:       for.cond11:
7526 // CHECK6-NEXT:    [[TMP13:%.*]] = load i32, i32* [[I10]], align 4
7527 // CHECK6-NEXT:    [[CMP12:%.*]] = icmp slt i32 [[TMP13]], 10
7528 // CHECK6-NEXT:    br i1 [[CMP12]], label [[FOR_BODY13:%.*]], label [[FOR_END18:%.*]]
7529 // CHECK6:       for.body13:
7530 // CHECK6-NEXT:    [[TMP14:%.*]] = load i16, i16* [[AA]], align 2
7531 // CHECK6-NEXT:    [[CONV:%.*]] = sext i16 [[TMP14]] to i32
7532 // CHECK6-NEXT:    [[ADD14:%.*]] = add nsw i32 [[CONV]], 1
7533 // CHECK6-NEXT:    [[CONV15:%.*]] = trunc i32 [[ADD14]] to i16
7534 // CHECK6-NEXT:    store i16 [[CONV15]], i16* [[AA]], align 2
7535 // CHECK6-NEXT:    br label [[FOR_INC16:%.*]]
7536 // CHECK6:       for.inc16:
7537 // CHECK6-NEXT:    [[TMP15:%.*]] = load i32, i32* [[I10]], align 4
7538 // CHECK6-NEXT:    [[INC17:%.*]] = add nsw i32 [[TMP15]], 1
7539 // CHECK6-NEXT:    store i32 [[INC17]], i32* [[I10]], align 4
7540 // CHECK6-NEXT:    br label [[FOR_COND11]], !llvm.loop [[LOOP5:![0-9]+]]
7541 // CHECK6:       for.end18:
7542 // CHECK6-NEXT:    store i32 0, i32* [[I19]], align 4
7543 // CHECK6-NEXT:    br label [[FOR_COND20:%.*]]
7544 // CHECK6:       for.cond20:
7545 // CHECK6-NEXT:    [[TMP16:%.*]] = load i32, i32* [[I19]], align 4
7546 // CHECK6-NEXT:    [[CMP21:%.*]] = icmp slt i32 [[TMP16]], 10
7547 // CHECK6-NEXT:    br i1 [[CMP21]], label [[FOR_BODY22:%.*]], label [[FOR_END29:%.*]]
7548 // CHECK6:       for.body22:
7549 // CHECK6-NEXT:    [[TMP17:%.*]] = load i32, i32* [[A]], align 4
7550 // CHECK6-NEXT:    [[ADD23:%.*]] = add nsw i32 [[TMP17]], 1
7551 // CHECK6-NEXT:    store i32 [[ADD23]], i32* [[A]], align 4
7552 // CHECK6-NEXT:    [[TMP18:%.*]] = load i16, i16* [[AA]], align 2
7553 // CHECK6-NEXT:    [[CONV24:%.*]] = sext i16 [[TMP18]] to i32
7554 // CHECK6-NEXT:    [[ADD25:%.*]] = add nsw i32 [[CONV24]], 1
7555 // CHECK6-NEXT:    [[CONV26:%.*]] = trunc i32 [[ADD25]] to i16
7556 // CHECK6-NEXT:    store i16 [[CONV26]], i16* [[AA]], align 2
7557 // CHECK6-NEXT:    br label [[FOR_INC27:%.*]]
7558 // CHECK6:       for.inc27:
7559 // CHECK6-NEXT:    [[TMP19:%.*]] = load i32, i32* [[I19]], align 4
7560 // CHECK6-NEXT:    [[INC28:%.*]] = add nsw i32 [[TMP19]], 1
7561 // CHECK6-NEXT:    store i32 [[INC28]], i32* [[I19]], align 4
7562 // CHECK6-NEXT:    br label [[FOR_COND20]], !llvm.loop [[LOOP6:![0-9]+]]
7563 // CHECK6:       for.end29:
7564 // CHECK6-NEXT:    [[TMP20:%.*]] = load i32, i32* [[N_ADDR]], align 4
7565 // CHECK6-NEXT:    store i32 [[TMP20]], i32* [[DOTCAPTURE_EXPR_30]], align 4
7566 // CHECK6-NEXT:    store i32 0, i32* [[I31]], align 4
7567 // CHECK6-NEXT:    br label [[FOR_COND32:%.*]]
7568 // CHECK6:       for.cond32:
7569 // CHECK6-NEXT:    [[TMP21:%.*]] = load i32, i32* [[I31]], align 4
7570 // CHECK6-NEXT:    [[CMP33:%.*]] = icmp slt i32 [[TMP21]], 10
7571 // CHECK6-NEXT:    br i1 [[CMP33]], label [[FOR_BODY34:%.*]], label [[FOR_END55:%.*]]
7572 // CHECK6:       for.body34:
7573 // CHECK6-NEXT:    [[TMP22:%.*]] = load i32, i32* [[A]], align 4
7574 // CHECK6-NEXT:    [[ADD35:%.*]] = add nsw i32 [[TMP22]], 1
7575 // CHECK6-NEXT:    store i32 [[ADD35]], i32* [[A]], align 4
7576 // CHECK6-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2
7577 // CHECK6-NEXT:    [[TMP23:%.*]] = load float, float* [[ARRAYIDX]], align 4
7578 // CHECK6-NEXT:    [[CONV36:%.*]] = fpext float [[TMP23]] to double
7579 // CHECK6-NEXT:    [[ADD37:%.*]] = fadd double [[CONV36]], 1.000000e+00
7580 // CHECK6-NEXT:    [[CONV38:%.*]] = fptrunc double [[ADD37]] to float
7581 // CHECK6-NEXT:    store float [[CONV38]], float* [[ARRAYIDX]], align 4
7582 // CHECK6-NEXT:    [[ARRAYIDX39:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3
7583 // CHECK6-NEXT:    [[TMP24:%.*]] = load float, float* [[ARRAYIDX39]], align 4
7584 // CHECK6-NEXT:    [[CONV40:%.*]] = fpext float [[TMP24]] to double
7585 // CHECK6-NEXT:    [[ADD41:%.*]] = fadd double [[CONV40]], 1.000000e+00
7586 // CHECK6-NEXT:    [[CONV42:%.*]] = fptrunc double [[ADD41]] to float
7587 // CHECK6-NEXT:    store float [[CONV42]], float* [[ARRAYIDX39]], align 4
7588 // CHECK6-NEXT:    [[ARRAYIDX43:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1
7589 // CHECK6-NEXT:    [[ARRAYIDX44:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX43]], i64 0, i64 2
7590 // CHECK6-NEXT:    [[TMP25:%.*]] = load double, double* [[ARRAYIDX44]], align 8
7591 // CHECK6-NEXT:    [[ADD45:%.*]] = fadd double [[TMP25]], 1.000000e+00
7592 // CHECK6-NEXT:    store double [[ADD45]], double* [[ARRAYIDX44]], align 8
7593 // CHECK6-NEXT:    [[TMP26:%.*]] = mul nsw i64 1, [[TMP4]]
7594 // CHECK6-NEXT:    [[ARRAYIDX46:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP26]]
7595 // CHECK6-NEXT:    [[ARRAYIDX47:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX46]], i64 3
7596 // CHECK6-NEXT:    [[TMP27:%.*]] = load double, double* [[ARRAYIDX47]], align 8
7597 // CHECK6-NEXT:    [[ADD48:%.*]] = fadd double [[TMP27]], 1.000000e+00
7598 // CHECK6-NEXT:    store double [[ADD48]], double* [[ARRAYIDX47]], align 8
7599 // CHECK6-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0
7600 // CHECK6-NEXT:    [[TMP28:%.*]] = load i64, i64* [[X]], align 8
7601 // CHECK6-NEXT:    [[ADD49:%.*]] = add nsw i64 [[TMP28]], 1
7602 // CHECK6-NEXT:    store i64 [[ADD49]], i64* [[X]], align 8
7603 // CHECK6-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1
7604 // CHECK6-NEXT:    [[TMP29:%.*]] = load i8, i8* [[Y]], align 8
7605 // CHECK6-NEXT:    [[CONV50:%.*]] = sext i8 [[TMP29]] to i32
7606 // CHECK6-NEXT:    [[ADD51:%.*]] = add nsw i32 [[CONV50]], 1
7607 // CHECK6-NEXT:    [[CONV52:%.*]] = trunc i32 [[ADD51]] to i8
7608 // CHECK6-NEXT:    store i8 [[CONV52]], i8* [[Y]], align 8
7609 // CHECK6-NEXT:    br label [[FOR_INC53:%.*]]
7610 // CHECK6:       for.inc53:
7611 // CHECK6-NEXT:    [[TMP30:%.*]] = load i32, i32* [[I31]], align 4
7612 // CHECK6-NEXT:    [[INC54:%.*]] = add nsw i32 [[TMP30]], 1
7613 // CHECK6-NEXT:    store i32 [[INC54]], i32* [[I31]], align 4
7614 // CHECK6-NEXT:    br label [[FOR_COND32]], !llvm.loop [[LOOP7:![0-9]+]]
7615 // CHECK6:       for.end55:
7616 // CHECK6-NEXT:    [[TMP31:%.*]] = load i32, i32* [[A]], align 4
7617 // CHECK6-NEXT:    [[TMP32:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
7618 // CHECK6-NEXT:    call void @llvm.stackrestore(i8* [[TMP32]])
7619 // CHECK6-NEXT:    ret i32 [[TMP31]]
7620 //
7621 //
7622 // CHECK6-LABEL: define {{[^@]+}}@_Z3bari
7623 // CHECK6-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
7624 // CHECK6-NEXT:  entry:
7625 // CHECK6-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
7626 // CHECK6-NEXT:    [[A:%.*]] = alloca i32, align 4
7627 // CHECK6-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8
7628 // CHECK6-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
7629 // CHECK6-NEXT:    store i32 0, i32* [[A]], align 4
7630 // CHECK6-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
7631 // CHECK6-NEXT:    [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]])
7632 // CHECK6-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
7633 // CHECK6-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
7634 // CHECK6-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
7635 // CHECK6-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
7636 // CHECK6-NEXT:    [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]])
7637 // CHECK6-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
7638 // CHECK6-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
7639 // CHECK6-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
7640 // CHECK6-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
7641 // CHECK6-NEXT:    [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]])
7642 // CHECK6-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
7643 // CHECK6-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
7644 // CHECK6-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
7645 // CHECK6-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
7646 // CHECK6-NEXT:    [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]])
7647 // CHECK6-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
7648 // CHECK6-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
7649 // CHECK6-NEXT:    store i32 [[ADD6]], i32* [[A]], align 4
7650 // CHECK6-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
7651 // CHECK6-NEXT:    ret i32 [[TMP8]]
7652 //
7653 //
7654 // CHECK6-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
7655 // CHECK6-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 {
7656 // CHECK6-NEXT:  entry:
7657 // CHECK6-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
7658 // CHECK6-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
7659 // CHECK6-NEXT:    [[B:%.*]] = alloca i32, align 4
7660 // CHECK6-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 8
7661 // CHECK6-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
7662 // CHECK6-NEXT:    [[I:%.*]] = alloca i32, align 4
7663 // CHECK6-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
7664 // CHECK6-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
7665 // CHECK6-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
7666 // CHECK6-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
7667 // CHECK6-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
7668 // CHECK6-NEXT:    store i32 [[ADD]], i32* [[B]], align 4
7669 // CHECK6-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
7670 // CHECK6-NEXT:    [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
7671 // CHECK6-NEXT:    [[TMP3:%.*]] = call i8* @llvm.stacksave()
7672 // CHECK6-NEXT:    store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8
7673 // CHECK6-NEXT:    [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]
7674 // CHECK6-NEXT:    [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2
7675 // CHECK6-NEXT:    store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8
7676 // CHECK6-NEXT:    store i32 0, i32* [[I]], align 4
7677 // CHECK6-NEXT:    br label [[FOR_COND:%.*]]
7678 // CHECK6:       for.cond:
7679 // CHECK6-NEXT:    [[TMP5:%.*]] = load i32, i32* [[I]], align 4
7680 // CHECK6-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP5]], 10
7681 // CHECK6-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
7682 // CHECK6:       for.body:
7683 // CHECK6-NEXT:    [[TMP6:%.*]] = load i32, i32* [[B]], align 4
7684 // CHECK6-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP6]] to double
7685 // CHECK6-NEXT:    [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00
7686 // CHECK6-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
7687 // CHECK6-NEXT:    store double [[ADD2]], double* [[A]], align 8
7688 // CHECK6-NEXT:    [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
7689 // CHECK6-NEXT:    [[TMP7:%.*]] = load double, double* [[A3]], align 8
7690 // CHECK6-NEXT:    [[INC:%.*]] = fadd double [[TMP7]], 1.000000e+00
7691 // CHECK6-NEXT:    store double [[INC]], double* [[A3]], align 8
7692 // CHECK6-NEXT:    [[CONV4:%.*]] = fptosi double [[INC]] to i16
7693 // CHECK6-NEXT:    [[TMP8:%.*]] = mul nsw i64 1, [[TMP2]]
7694 // CHECK6-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP8]]
7695 // CHECK6-NEXT:    [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
7696 // CHECK6-NEXT:    store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2
7697 // CHECK6-NEXT:    br label [[FOR_INC:%.*]]
7698 // CHECK6:       for.inc:
7699 // CHECK6-NEXT:    [[TMP9:%.*]] = load i32, i32* [[I]], align 4
7700 // CHECK6-NEXT:    [[INC6:%.*]] = add nsw i32 [[TMP9]], 1
7701 // CHECK6-NEXT:    store i32 [[INC6]], i32* [[I]], align 4
7702 // CHECK6-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]]
7703 // CHECK6:       for.end:
7704 // CHECK6-NEXT:    [[TMP10:%.*]] = mul nsw i64 1, [[TMP2]]
7705 // CHECK6-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP10]]
7706 // CHECK6-NEXT:    [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX7]], i64 1
7707 // CHECK6-NEXT:    [[TMP11:%.*]] = load i16, i16* [[ARRAYIDX8]], align 2
7708 // CHECK6-NEXT:    [[CONV9:%.*]] = sext i16 [[TMP11]] to i32
7709 // CHECK6-NEXT:    [[TMP12:%.*]] = load i32, i32* [[B]], align 4
7710 // CHECK6-NEXT:    [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[TMP12]]
7711 // CHECK6-NEXT:    [[TMP13:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
7712 // CHECK6-NEXT:    call void @llvm.stackrestore(i8* [[TMP13]])
7713 // CHECK6-NEXT:    ret i32 [[ADD10]]
7714 //
7715 //
7716 // CHECK6-LABEL: define {{[^@]+}}@_ZL7fstatici
7717 // CHECK6-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
7718 // CHECK6-NEXT:  entry:
7719 // CHECK6-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
7720 // CHECK6-NEXT:    [[A:%.*]] = alloca i32, align 4
7721 // CHECK6-NEXT:    [[AA:%.*]] = alloca i16, align 2
7722 // CHECK6-NEXT:    [[AAA:%.*]] = alloca i8, align 1
7723 // CHECK6-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
7724 // CHECK6-NEXT:    [[I:%.*]] = alloca i32, align 4
7725 // CHECK6-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
7726 // CHECK6-NEXT:    store i32 0, i32* [[A]], align 4
7727 // CHECK6-NEXT:    store i16 0, i16* [[AA]], align 2
7728 // CHECK6-NEXT:    store i8 0, i8* [[AAA]], align 1
7729 // CHECK6-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
7730 // CHECK6-NEXT:    store i32 [[TMP0]], i32* [[I]], align 4
7731 // CHECK6-NEXT:    br label [[FOR_COND:%.*]]
7732 // CHECK6:       for.cond:
7733 // CHECK6-NEXT:    [[TMP1:%.*]] = load i32, i32* [[I]], align 4
7734 // CHECK6-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
7735 // CHECK6-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP1]], [[TMP2]]
7736 // CHECK6-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
7737 // CHECK6:       for.body:
7738 // CHECK6-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
7739 // CHECK6-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP3]], 1
7740 // CHECK6-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
7741 // CHECK6-NEXT:    [[TMP4:%.*]] = load i16, i16* [[AA]], align 2
7742 // CHECK6-NEXT:    [[CONV:%.*]] = sext i16 [[TMP4]] to i32
7743 // CHECK6-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
7744 // CHECK6-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
7745 // CHECK6-NEXT:    store i16 [[CONV2]], i16* [[AA]], align 2
7746 // CHECK6-NEXT:    [[TMP5:%.*]] = load i8, i8* [[AAA]], align 1
7747 // CHECK6-NEXT:    [[CONV3:%.*]] = sext i8 [[TMP5]] to i32
7748 // CHECK6-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
7749 // CHECK6-NEXT:    [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8
7750 // CHECK6-NEXT:    store i8 [[CONV5]], i8* [[AAA]], align 1
7751 // CHECK6-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2
7752 // CHECK6-NEXT:    [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
7753 // CHECK6-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP6]], 1
7754 // CHECK6-NEXT:    store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4
7755 // CHECK6-NEXT:    br label [[FOR_INC:%.*]]
7756 // CHECK6:       for.inc:
7757 // CHECK6-NEXT:    [[TMP7:%.*]] = load i32, i32* [[I]], align 4
7758 // CHECK6-NEXT:    [[INC:%.*]] = add nsw i32 [[TMP7]], 1
7759 // CHECK6-NEXT:    store i32 [[INC]], i32* [[I]], align 4
7760 // CHECK6-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]
7761 // CHECK6:       for.end:
7762 // CHECK6-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
7763 // CHECK6-NEXT:    ret i32 [[TMP8]]
7764 //
7765 //
7766 // CHECK6-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
7767 // CHECK6-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat {
7768 // CHECK6-NEXT:  entry:
7769 // CHECK6-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
7770 // CHECK6-NEXT:    [[A:%.*]] = alloca i32, align 4
7771 // CHECK6-NEXT:    [[AA:%.*]] = alloca i16, align 2
7772 // CHECK6-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
7773 // CHECK6-NEXT:    [[I:%.*]] = alloca i32, align 4
7774 // CHECK6-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
7775 // CHECK6-NEXT:    store i32 0, i32* [[A]], align 4
7776 // CHECK6-NEXT:    store i16 0, i16* [[AA]], align 2
7777 // CHECK6-NEXT:    store i32 0, i32* [[I]], align 4
7778 // CHECK6-NEXT:    br label [[FOR_COND:%.*]]
7779 // CHECK6:       for.cond:
7780 // CHECK6-NEXT:    [[TMP0:%.*]] = load i32, i32* [[I]], align 4
7781 // CHECK6-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10
7782 // CHECK6-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
7783 // CHECK6:       for.body:
7784 // CHECK6-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
7785 // CHECK6-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
7786 // CHECK6-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
7787 // CHECK6-NEXT:    [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
7788 // CHECK6-NEXT:    [[CONV:%.*]] = sext i16 [[TMP2]] to i32
7789 // CHECK6-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
7790 // CHECK6-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
7791 // CHECK6-NEXT:    store i16 [[CONV2]], i16* [[AA]], align 2
7792 // CHECK6-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2
7793 // CHECK6-NEXT:    [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
7794 // CHECK6-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1
7795 // CHECK6-NEXT:    store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4
7796 // CHECK6-NEXT:    br label [[FOR_INC:%.*]]
7797 // CHECK6:       for.inc:
7798 // CHECK6-NEXT:    [[TMP4:%.*]] = load i32, i32* [[I]], align 4
7799 // CHECK6-NEXT:    [[INC:%.*]] = add nsw i32 [[TMP4]], 1
7800 // CHECK6-NEXT:    store i32 [[INC]], i32* [[I]], align 4
7801 // CHECK6-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]
7802 // CHECK6:       for.end:
7803 // CHECK6-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
7804 // CHECK6-NEXT:    ret i32 [[TMP5]]
7805 //
7806 //
7807 // CHECK7-LABEL: define {{[^@]+}}@_Z3fooi
7808 // CHECK7-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] {
7809 // CHECK7-NEXT:  entry:
7810 // CHECK7-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
7811 // CHECK7-NEXT:    [[A:%.*]] = alloca i32, align 4
7812 // CHECK7-NEXT:    [[AA:%.*]] = alloca i16, align 2
7813 // CHECK7-NEXT:    [[B:%.*]] = alloca [10 x float], align 4
7814 // CHECK7-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 4
7815 // CHECK7-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 4
7816 // CHECK7-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 8
7817 // CHECK7-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i32, align 4
7818 // CHECK7-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4
7819 // CHECK7-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
7820 // CHECK7-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
7821 // CHECK7-NEXT:    [[I:%.*]] = alloca i32, align 4
7822 // CHECK7-NEXT:    [[I3:%.*]] = alloca i32, align 4
7823 // CHECK7-NEXT:    [[I10:%.*]] = alloca i32, align 4
7824 // CHECK7-NEXT:    [[I19:%.*]] = alloca i32, align 4
7825 // CHECK7-NEXT:    [[DOTCAPTURE_EXPR_30:%.*]] = alloca i32, align 4
7826 // CHECK7-NEXT:    [[I31:%.*]] = alloca i32, align 4
7827 // CHECK7-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
7828 // CHECK7-NEXT:    store i32 0, i32* [[A]], align 4
7829 // CHECK7-NEXT:    store i16 0, i16* [[AA]], align 2
7830 // CHECK7-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
7831 // CHECK7-NEXT:    [[TMP1:%.*]] = call i8* @llvm.stacksave()
7832 // CHECK7-NEXT:    store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4
7833 // CHECK7-NEXT:    [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4
7834 // CHECK7-NEXT:    store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4
7835 // CHECK7-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
7836 // CHECK7-NEXT:    [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]]
7837 // CHECK7-NEXT:    [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8
7838 // CHECK7-NEXT:    store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4
7839 // CHECK7-NEXT:    [[TMP4:%.*]] = load i32, i32* [[A]], align 4
7840 // CHECK7-NEXT:    store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4
7841 // CHECK7-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
7842 // CHECK7-NEXT:    store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_2]], align 4
7843 // CHECK7-NEXT:    store i32 0, i32* [[I]], align 4
7844 // CHECK7-NEXT:    br label [[FOR_COND:%.*]]
7845 // CHECK7:       for.cond:
7846 // CHECK7-NEXT:    [[TMP6:%.*]] = load i32, i32* [[I]], align 4
7847 // CHECK7-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP6]], 10
7848 // CHECK7-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
7849 // CHECK7:       for.body:
7850 // CHECK7-NEXT:    br label [[FOR_INC:%.*]]
7851 // CHECK7:       for.inc:
7852 // CHECK7-NEXT:    [[TMP7:%.*]] = load i32, i32* [[I]], align 4
7853 // CHECK7-NEXT:    [[INC:%.*]] = add nsw i32 [[TMP7]], 1
7854 // CHECK7-NEXT:    store i32 [[INC]], i32* [[I]], align 4
7855 // CHECK7-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]
7856 // CHECK7:       for.end:
7857 // CHECK7-NEXT:    store i32 0, i32* [[I3]], align 4
7858 // CHECK7-NEXT:    br label [[FOR_COND4:%.*]]
7859 // CHECK7:       for.cond4:
7860 // CHECK7-NEXT:    [[TMP8:%.*]] = load i32, i32* [[I3]], align 4
7861 // CHECK7-NEXT:    [[CMP5:%.*]] = icmp slt i32 [[TMP8]], 10
7862 // CHECK7-NEXT:    br i1 [[CMP5]], label [[FOR_BODY6:%.*]], label [[FOR_END9:%.*]]
7863 // CHECK7:       for.body6:
7864 // CHECK7-NEXT:    [[TMP9:%.*]] = load i32, i32* [[A]], align 4
7865 // CHECK7-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP9]], 1
7866 // CHECK7-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
7867 // CHECK7-NEXT:    br label [[FOR_INC7:%.*]]
7868 // CHECK7:       for.inc7:
7869 // CHECK7-NEXT:    [[TMP10:%.*]] = load i32, i32* [[I3]], align 4
7870 // CHECK7-NEXT:    [[INC8:%.*]] = add nsw i32 [[TMP10]], 1
7871 // CHECK7-NEXT:    store i32 [[INC8]], i32* [[I3]], align 4
7872 // CHECK7-NEXT:    br label [[FOR_COND4]], !llvm.loop [[LOOP5:![0-9]+]]
7873 // CHECK7:       for.end9:
7874 // CHECK7-NEXT:    store i32 0, i32* [[I10]], align 4
7875 // CHECK7-NEXT:    br label [[FOR_COND11:%.*]]
7876 // CHECK7:       for.cond11:
7877 // CHECK7-NEXT:    [[TMP11:%.*]] = load i32, i32* [[I10]], align 4
7878 // CHECK7-NEXT:    [[CMP12:%.*]] = icmp slt i32 [[TMP11]], 10
7879 // CHECK7-NEXT:    br i1 [[CMP12]], label [[FOR_BODY13:%.*]], label [[FOR_END18:%.*]]
7880 // CHECK7:       for.body13:
7881 // CHECK7-NEXT:    [[TMP12:%.*]] = load i16, i16* [[AA]], align 2
7882 // CHECK7-NEXT:    [[CONV:%.*]] = sext i16 [[TMP12]] to i32
7883 // CHECK7-NEXT:    [[ADD14:%.*]] = add nsw i32 [[CONV]], 1
7884 // CHECK7-NEXT:    [[CONV15:%.*]] = trunc i32 [[ADD14]] to i16
7885 // CHECK7-NEXT:    store i16 [[CONV15]], i16* [[AA]], align 2
7886 // CHECK7-NEXT:    br label [[FOR_INC16:%.*]]
7887 // CHECK7:       for.inc16:
7888 // CHECK7-NEXT:    [[TMP13:%.*]] = load i32, i32* [[I10]], align 4
7889 // CHECK7-NEXT:    [[INC17:%.*]] = add nsw i32 [[TMP13]], 1
7890 // CHECK7-NEXT:    store i32 [[INC17]], i32* [[I10]], align 4
7891 // CHECK7-NEXT:    br label [[FOR_COND11]], !llvm.loop [[LOOP6:![0-9]+]]
7892 // CHECK7:       for.end18:
7893 // CHECK7-NEXT:    store i32 0, i32* [[I19]], align 4
7894 // CHECK7-NEXT:    br label [[FOR_COND20:%.*]]
7895 // CHECK7:       for.cond20:
7896 // CHECK7-NEXT:    [[TMP14:%.*]] = load i32, i32* [[I19]], align 4
7897 // CHECK7-NEXT:    [[CMP21:%.*]] = icmp slt i32 [[TMP14]], 10
7898 // CHECK7-NEXT:    br i1 [[CMP21]], label [[FOR_BODY22:%.*]], label [[FOR_END29:%.*]]
7899 // CHECK7:       for.body22:
7900 // CHECK7-NEXT:    [[TMP15:%.*]] = load i32, i32* [[A]], align 4
7901 // CHECK7-NEXT:    [[ADD23:%.*]] = add nsw i32 [[TMP15]], 1
7902 // CHECK7-NEXT:    store i32 [[ADD23]], i32* [[A]], align 4
7903 // CHECK7-NEXT:    [[TMP16:%.*]] = load i16, i16* [[AA]], align 2
7904 // CHECK7-NEXT:    [[CONV24:%.*]] = sext i16 [[TMP16]] to i32
7905 // CHECK7-NEXT:    [[ADD25:%.*]] = add nsw i32 [[CONV24]], 1
7906 // CHECK7-NEXT:    [[CONV26:%.*]] = trunc i32 [[ADD25]] to i16
7907 // CHECK7-NEXT:    store i16 [[CONV26]], i16* [[AA]], align 2
7908 // CHECK7-NEXT:    br label [[FOR_INC27:%.*]]
7909 // CHECK7:       for.inc27:
7910 // CHECK7-NEXT:    [[TMP17:%.*]] = load i32, i32* [[I19]], align 4
7911 // CHECK7-NEXT:    [[INC28:%.*]] = add nsw i32 [[TMP17]], 1
7912 // CHECK7-NEXT:    store i32 [[INC28]], i32* [[I19]], align 4
7913 // CHECK7-NEXT:    br label [[FOR_COND20]], !llvm.loop [[LOOP7:![0-9]+]]
7914 // CHECK7:       for.end29:
7915 // CHECK7-NEXT:    [[TMP18:%.*]] = load i32, i32* [[N_ADDR]], align 4
7916 // CHECK7-NEXT:    store i32 [[TMP18]], i32* [[DOTCAPTURE_EXPR_30]], align 4
7917 // CHECK7-NEXT:    store i32 0, i32* [[I31]], align 4
7918 // CHECK7-NEXT:    br label [[FOR_COND32:%.*]]
7919 // CHECK7:       for.cond32:
7920 // CHECK7-NEXT:    [[TMP19:%.*]] = load i32, i32* [[I31]], align 4
7921 // CHECK7-NEXT:    [[CMP33:%.*]] = icmp slt i32 [[TMP19]], 10
7922 // CHECK7-NEXT:    br i1 [[CMP33]], label [[FOR_BODY34:%.*]], label [[FOR_END55:%.*]]
7923 // CHECK7:       for.body34:
7924 // CHECK7-NEXT:    [[TMP20:%.*]] = load i32, i32* [[A]], align 4
7925 // CHECK7-NEXT:    [[ADD35:%.*]] = add nsw i32 [[TMP20]], 1
7926 // CHECK7-NEXT:    store i32 [[ADD35]], i32* [[A]], align 4
7927 // CHECK7-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2
7928 // CHECK7-NEXT:    [[TMP21:%.*]] = load float, float* [[ARRAYIDX]], align 4
7929 // CHECK7-NEXT:    [[CONV36:%.*]] = fpext float [[TMP21]] to double
7930 // CHECK7-NEXT:    [[ADD37:%.*]] = fadd double [[CONV36]], 1.000000e+00
7931 // CHECK7-NEXT:    [[CONV38:%.*]] = fptrunc double [[ADD37]] to float
7932 // CHECK7-NEXT:    store float [[CONV38]], float* [[ARRAYIDX]], align 4
7933 // CHECK7-NEXT:    [[ARRAYIDX39:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3
7934 // CHECK7-NEXT:    [[TMP22:%.*]] = load float, float* [[ARRAYIDX39]], align 4
7935 // CHECK7-NEXT:    [[CONV40:%.*]] = fpext float [[TMP22]] to double
7936 // CHECK7-NEXT:    [[ADD41:%.*]] = fadd double [[CONV40]], 1.000000e+00
7937 // CHECK7-NEXT:    [[CONV42:%.*]] = fptrunc double [[ADD41]] to float
7938 // CHECK7-NEXT:    store float [[CONV42]], float* [[ARRAYIDX39]], align 4
7939 // CHECK7-NEXT:    [[ARRAYIDX43:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1
7940 // CHECK7-NEXT:    [[ARRAYIDX44:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX43]], i32 0, i32 2
7941 // CHECK7-NEXT:    [[TMP23:%.*]] = load double, double* [[ARRAYIDX44]], align 8
7942 // CHECK7-NEXT:    [[ADD45:%.*]] = fadd double [[TMP23]], 1.000000e+00
7943 // CHECK7-NEXT:    store double [[ADD45]], double* [[ARRAYIDX44]], align 8
7944 // CHECK7-NEXT:    [[TMP24:%.*]] = mul nsw i32 1, [[TMP2]]
7945 // CHECK7-NEXT:    [[ARRAYIDX46:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP24]]
7946 // CHECK7-NEXT:    [[ARRAYIDX47:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX46]], i32 3
7947 // CHECK7-NEXT:    [[TMP25:%.*]] = load double, double* [[ARRAYIDX47]], align 8
7948 // CHECK7-NEXT:    [[ADD48:%.*]] = fadd double [[TMP25]], 1.000000e+00
7949 // CHECK7-NEXT:    store double [[ADD48]], double* [[ARRAYIDX47]], align 8
7950 // CHECK7-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0
7951 // CHECK7-NEXT:    [[TMP26:%.*]] = load i64, i64* [[X]], align 4
7952 // CHECK7-NEXT:    [[ADD49:%.*]] = add nsw i64 [[TMP26]], 1
7953 // CHECK7-NEXT:    store i64 [[ADD49]], i64* [[X]], align 4
7954 // CHECK7-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1
7955 // CHECK7-NEXT:    [[TMP27:%.*]] = load i8, i8* [[Y]], align 4
7956 // CHECK7-NEXT:    [[CONV50:%.*]] = sext i8 [[TMP27]] to i32
7957 // CHECK7-NEXT:    [[ADD51:%.*]] = add nsw i32 [[CONV50]], 1
7958 // CHECK7-NEXT:    [[CONV52:%.*]] = trunc i32 [[ADD51]] to i8
7959 // CHECK7-NEXT:    store i8 [[CONV52]], i8* [[Y]], align 4
7960 // CHECK7-NEXT:    br label [[FOR_INC53:%.*]]
7961 // CHECK7:       for.inc53:
7962 // CHECK7-NEXT:    [[TMP28:%.*]] = load i32, i32* [[I31]], align 4
7963 // CHECK7-NEXT:    [[INC54:%.*]] = add nsw i32 [[TMP28]], 1
7964 // CHECK7-NEXT:    store i32 [[INC54]], i32* [[I31]], align 4
7965 // CHECK7-NEXT:    br label [[FOR_COND32]], !llvm.loop [[LOOP8:![0-9]+]]
7966 // CHECK7:       for.end55:
7967 // CHECK7-NEXT:    [[TMP29:%.*]] = load i32, i32* [[A]], align 4
7968 // CHECK7-NEXT:    [[TMP30:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
7969 // CHECK7-NEXT:    call void @llvm.stackrestore(i8* [[TMP30]])
7970 // CHECK7-NEXT:    ret i32 [[TMP29]]
7971 //
7972 //
7973 // CHECK7-LABEL: define {{[^@]+}}@_Z3bari
7974 // CHECK7-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
7975 // CHECK7-NEXT:  entry:
7976 // CHECK7-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
7977 // CHECK7-NEXT:    [[A:%.*]] = alloca i32, align 4
7978 // CHECK7-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4
7979 // CHECK7-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
7980 // CHECK7-NEXT:    store i32 0, i32* [[A]], align 4
7981 // CHECK7-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
7982 // CHECK7-NEXT:    [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]])
7983 // CHECK7-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
7984 // CHECK7-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
7985 // CHECK7-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
7986 // CHECK7-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
7987 // CHECK7-NEXT:    [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]])
7988 // CHECK7-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
7989 // CHECK7-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
7990 // CHECK7-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
7991 // CHECK7-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
7992 // CHECK7-NEXT:    [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]])
7993 // CHECK7-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
7994 // CHECK7-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
7995 // CHECK7-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
7996 // CHECK7-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
7997 // CHECK7-NEXT:    [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]])
7998 // CHECK7-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
7999 // CHECK7-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
8000 // CHECK7-NEXT:    store i32 [[ADD6]], i32* [[A]], align 4
8001 // CHECK7-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
8002 // CHECK7-NEXT:    ret i32 [[TMP8]]
8003 //
8004 //
8005 // CHECK7-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
8006 // CHECK7-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 {
8007 // CHECK7-NEXT:  entry:
8008 // CHECK7-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
8009 // CHECK7-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
8010 // CHECK7-NEXT:    [[B:%.*]] = alloca i32, align 4
8011 // CHECK7-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 4
8012 // CHECK7-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 4
8013 // CHECK7-NEXT:    [[I:%.*]] = alloca i32, align 4
8014 // CHECK7-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
8015 // CHECK7-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
8016 // CHECK7-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
8017 // CHECK7-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
8018 // CHECK7-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
8019 // CHECK7-NEXT:    store i32 [[ADD]], i32* [[B]], align 4
8020 // CHECK7-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
8021 // CHECK7-NEXT:    [[TMP2:%.*]] = call i8* @llvm.stacksave()
8022 // CHECK7-NEXT:    store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4
8023 // CHECK7-NEXT:    [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]
8024 // CHECK7-NEXT:    [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2
8025 // CHECK7-NEXT:    store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
8026 // CHECK7-NEXT:    store i32 0, i32* [[I]], align 4
8027 // CHECK7-NEXT:    br label [[FOR_COND:%.*]]
8028 // CHECK7:       for.cond:
8029 // CHECK7-NEXT:    [[TMP4:%.*]] = load i32, i32* [[I]], align 4
8030 // CHECK7-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP4]], 10
8031 // CHECK7-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
8032 // CHECK7:       for.body:
8033 // CHECK7-NEXT:    [[TMP5:%.*]] = load i32, i32* [[B]], align 4
8034 // CHECK7-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP5]] to double
8035 // CHECK7-NEXT:    [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00
8036 // CHECK7-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
8037 // CHECK7-NEXT:    store double [[ADD2]], double* [[A]], align 4
8038 // CHECK7-NEXT:    [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
8039 // CHECK7-NEXT:    [[TMP6:%.*]] = load double, double* [[A3]], align 4
8040 // CHECK7-NEXT:    [[INC:%.*]] = fadd double [[TMP6]], 1.000000e+00
8041 // CHECK7-NEXT:    store double [[INC]], double* [[A3]], align 4
8042 // CHECK7-NEXT:    [[CONV4:%.*]] = fptosi double [[INC]] to i16
8043 // CHECK7-NEXT:    [[TMP7:%.*]] = mul nsw i32 1, [[TMP1]]
8044 // CHECK7-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP7]]
8045 // CHECK7-NEXT:    [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
8046 // CHECK7-NEXT:    store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2
8047 // CHECK7-NEXT:    br label [[FOR_INC:%.*]]
8048 // CHECK7:       for.inc:
8049 // CHECK7-NEXT:    [[TMP8:%.*]] = load i32, i32* [[I]], align 4
8050 // CHECK7-NEXT:    [[INC6:%.*]] = add nsw i32 [[TMP8]], 1
8051 // CHECK7-NEXT:    store i32 [[INC6]], i32* [[I]], align 4
8052 // CHECK7-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]
8053 // CHECK7:       for.end:
8054 // CHECK7-NEXT:    [[TMP9:%.*]] = mul nsw i32 1, [[TMP1]]
8055 // CHECK7-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP9]]
8056 // CHECK7-NEXT:    [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX7]], i32 1
8057 // CHECK7-NEXT:    [[TMP10:%.*]] = load i16, i16* [[ARRAYIDX8]], align 2
8058 // CHECK7-NEXT:    [[CONV9:%.*]] = sext i16 [[TMP10]] to i32
8059 // CHECK7-NEXT:    [[TMP11:%.*]] = load i32, i32* [[B]], align 4
8060 // CHECK7-NEXT:    [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[TMP11]]
8061 // CHECK7-NEXT:    [[TMP12:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
8062 // CHECK7-NEXT:    call void @llvm.stackrestore(i8* [[TMP12]])
8063 // CHECK7-NEXT:    ret i32 [[ADD10]]
8064 //
8065 //
8066 // CHECK7-LABEL: define {{[^@]+}}@_ZL7fstatici
8067 // CHECK7-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
8068 // CHECK7-NEXT:  entry:
8069 // CHECK7-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
8070 // CHECK7-NEXT:    [[A:%.*]] = alloca i32, align 4
8071 // CHECK7-NEXT:    [[AA:%.*]] = alloca i16, align 2
8072 // CHECK7-NEXT:    [[AAA:%.*]] = alloca i8, align 1
8073 // CHECK7-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
8074 // CHECK7-NEXT:    [[I:%.*]] = alloca i32, align 4
8075 // CHECK7-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
8076 // CHECK7-NEXT:    store i32 0, i32* [[A]], align 4
8077 // CHECK7-NEXT:    store i16 0, i16* [[AA]], align 2
8078 // CHECK7-NEXT:    store i8 0, i8* [[AAA]], align 1
8079 // CHECK7-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
8080 // CHECK7-NEXT:    store i32 [[TMP0]], i32* [[I]], align 4
8081 // CHECK7-NEXT:    br label [[FOR_COND:%.*]]
8082 // CHECK7:       for.cond:
8083 // CHECK7-NEXT:    [[TMP1:%.*]] = load i32, i32* [[I]], align 4
8084 // CHECK7-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
8085 // CHECK7-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP1]], [[TMP2]]
8086 // CHECK7-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
8087 // CHECK7:       for.body:
8088 // CHECK7-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
8089 // CHECK7-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP3]], 1
8090 // CHECK7-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
8091 // CHECK7-NEXT:    [[TMP4:%.*]] = load i16, i16* [[AA]], align 2
8092 // CHECK7-NEXT:    [[CONV:%.*]] = sext i16 [[TMP4]] to i32
8093 // CHECK7-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
8094 // CHECK7-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
8095 // CHECK7-NEXT:    store i16 [[CONV2]], i16* [[AA]], align 2
8096 // CHECK7-NEXT:    [[TMP5:%.*]] = load i8, i8* [[AAA]], align 1
8097 // CHECK7-NEXT:    [[CONV3:%.*]] = sext i8 [[TMP5]] to i32
8098 // CHECK7-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
8099 // CHECK7-NEXT:    [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8
8100 // CHECK7-NEXT:    store i8 [[CONV5]], i8* [[AAA]], align 1
8101 // CHECK7-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2
8102 // CHECK7-NEXT:    [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
8103 // CHECK7-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP6]], 1
8104 // CHECK7-NEXT:    store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4
8105 // CHECK7-NEXT:    br label [[FOR_INC:%.*]]
8106 // CHECK7:       for.inc:
8107 // CHECK7-NEXT:    [[TMP7:%.*]] = load i32, i32* [[I]], align 4
8108 // CHECK7-NEXT:    [[INC:%.*]] = add nsw i32 [[TMP7]], 1
8109 // CHECK7-NEXT:    store i32 [[INC]], i32* [[I]], align 4
8110 // CHECK7-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]
8111 // CHECK7:       for.end:
8112 // CHECK7-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
8113 // CHECK7-NEXT:    ret i32 [[TMP8]]
8114 //
8115 //
8116 // CHECK7-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
8117 // CHECK7-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat {
8118 // CHECK7-NEXT:  entry:
8119 // CHECK7-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
8120 // CHECK7-NEXT:    [[A:%.*]] = alloca i32, align 4
8121 // CHECK7-NEXT:    [[AA:%.*]] = alloca i16, align 2
8122 // CHECK7-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
8123 // CHECK7-NEXT:    [[I:%.*]] = alloca i32, align 4
8124 // CHECK7-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
8125 // CHECK7-NEXT:    store i32 0, i32* [[A]], align 4
8126 // CHECK7-NEXT:    store i16 0, i16* [[AA]], align 2
8127 // CHECK7-NEXT:    store i32 0, i32* [[I]], align 4
8128 // CHECK7-NEXT:    br label [[FOR_COND:%.*]]
8129 // CHECK7:       for.cond:
8130 // CHECK7-NEXT:    [[TMP0:%.*]] = load i32, i32* [[I]], align 4
8131 // CHECK7-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10
8132 // CHECK7-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
8133 // CHECK7:       for.body:
8134 // CHECK7-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
8135 // CHECK7-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
8136 // CHECK7-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
8137 // CHECK7-NEXT:    [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
8138 // CHECK7-NEXT:    [[CONV:%.*]] = sext i16 [[TMP2]] to i32
8139 // CHECK7-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
8140 // CHECK7-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
8141 // CHECK7-NEXT:    store i16 [[CONV2]], i16* [[AA]], align 2
8142 // CHECK7-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2
8143 // CHECK7-NEXT:    [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
8144 // CHECK7-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1
8145 // CHECK7-NEXT:    store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4
8146 // CHECK7-NEXT:    br label [[FOR_INC:%.*]]
8147 // CHECK7:       for.inc:
8148 // CHECK7-NEXT:    [[TMP4:%.*]] = load i32, i32* [[I]], align 4
8149 // CHECK7-NEXT:    [[INC:%.*]] = add nsw i32 [[TMP4]], 1
8150 // CHECK7-NEXT:    store i32 [[INC]], i32* [[I]], align 4
8151 // CHECK7-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]
8152 // CHECK7:       for.end:
8153 // CHECK7-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
8154 // CHECK7-NEXT:    ret i32 [[TMP5]]
8155 //
8156 //
8157 // CHECK8-LABEL: define {{[^@]+}}@_Z3fooi
8158 // CHECK8-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] {
8159 // CHECK8-NEXT:  entry:
8160 // CHECK8-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
8161 // CHECK8-NEXT:    [[A:%.*]] = alloca i32, align 4
8162 // CHECK8-NEXT:    [[AA:%.*]] = alloca i16, align 2
8163 // CHECK8-NEXT:    [[B:%.*]] = alloca [10 x float], align 4
8164 // CHECK8-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 4
8165 // CHECK8-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 4
8166 // CHECK8-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 8
8167 // CHECK8-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i32, align 4
8168 // CHECK8-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4
8169 // CHECK8-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
8170 // CHECK8-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
8171 // CHECK8-NEXT:    [[I:%.*]] = alloca i32, align 4
8172 // CHECK8-NEXT:    [[I3:%.*]] = alloca i32, align 4
8173 // CHECK8-NEXT:    [[I10:%.*]] = alloca i32, align 4
8174 // CHECK8-NEXT:    [[I19:%.*]] = alloca i32, align 4
8175 // CHECK8-NEXT:    [[DOTCAPTURE_EXPR_30:%.*]] = alloca i32, align 4
8176 // CHECK8-NEXT:    [[I31:%.*]] = alloca i32, align 4
8177 // CHECK8-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
8178 // CHECK8-NEXT:    store i32 0, i32* [[A]], align 4
8179 // CHECK8-NEXT:    store i16 0, i16* [[AA]], align 2
8180 // CHECK8-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
8181 // CHECK8-NEXT:    [[TMP1:%.*]] = call i8* @llvm.stacksave()
8182 // CHECK8-NEXT:    store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4
8183 // CHECK8-NEXT:    [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4
8184 // CHECK8-NEXT:    store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4
8185 // CHECK8-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
8186 // CHECK8-NEXT:    [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]]
8187 // CHECK8-NEXT:    [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8
8188 // CHECK8-NEXT:    store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4
8189 // CHECK8-NEXT:    [[TMP4:%.*]] = load i32, i32* [[A]], align 4
8190 // CHECK8-NEXT:    store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4
8191 // CHECK8-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
8192 // CHECK8-NEXT:    store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_2]], align 4
8193 // CHECK8-NEXT:    store i32 0, i32* [[I]], align 4
8194 // CHECK8-NEXT:    br label [[FOR_COND:%.*]]
8195 // CHECK8:       for.cond:
8196 // CHECK8-NEXT:    [[TMP6:%.*]] = load i32, i32* [[I]], align 4
8197 // CHECK8-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP6]], 10
8198 // CHECK8-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
8199 // CHECK8:       for.body:
8200 // CHECK8-NEXT:    br label [[FOR_INC:%.*]]
8201 // CHECK8:       for.inc:
8202 // CHECK8-NEXT:    [[TMP7:%.*]] = load i32, i32* [[I]], align 4
8203 // CHECK8-NEXT:    [[INC:%.*]] = add nsw i32 [[TMP7]], 1
8204 // CHECK8-NEXT:    store i32 [[INC]], i32* [[I]], align 4
8205 // CHECK8-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]
8206 // CHECK8:       for.end:
8207 // CHECK8-NEXT:    store i32 0, i32* [[I3]], align 4
8208 // CHECK8-NEXT:    br label [[FOR_COND4:%.*]]
8209 // CHECK8:       for.cond4:
8210 // CHECK8-NEXT:    [[TMP8:%.*]] = load i32, i32* [[I3]], align 4
8211 // CHECK8-NEXT:    [[CMP5:%.*]] = icmp slt i32 [[TMP8]], 10
8212 // CHECK8-NEXT:    br i1 [[CMP5]], label [[FOR_BODY6:%.*]], label [[FOR_END9:%.*]]
8213 // CHECK8:       for.body6:
8214 // CHECK8-NEXT:    [[TMP9:%.*]] = load i32, i32* [[A]], align 4
8215 // CHECK8-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP9]], 1
8216 // CHECK8-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
8217 // CHECK8-NEXT:    br label [[FOR_INC7:%.*]]
8218 // CHECK8:       for.inc7:
8219 // CHECK8-NEXT:    [[TMP10:%.*]] = load i32, i32* [[I3]], align 4
8220 // CHECK8-NEXT:    [[INC8:%.*]] = add nsw i32 [[TMP10]], 1
8221 // CHECK8-NEXT:    store i32 [[INC8]], i32* [[I3]], align 4
8222 // CHECK8-NEXT:    br label [[FOR_COND4]], !llvm.loop [[LOOP5:![0-9]+]]
8223 // CHECK8:       for.end9:
8224 // CHECK8-NEXT:    store i32 0, i32* [[I10]], align 4
8225 // CHECK8-NEXT:    br label [[FOR_COND11:%.*]]
8226 // CHECK8:       for.cond11:
8227 // CHECK8-NEXT:    [[TMP11:%.*]] = load i32, i32* [[I10]], align 4
8228 // CHECK8-NEXT:    [[CMP12:%.*]] = icmp slt i32 [[TMP11]], 10
8229 // CHECK8-NEXT:    br i1 [[CMP12]], label [[FOR_BODY13:%.*]], label [[FOR_END18:%.*]]
8230 // CHECK8:       for.body13:
8231 // CHECK8-NEXT:    [[TMP12:%.*]] = load i16, i16* [[AA]], align 2
8232 // CHECK8-NEXT:    [[CONV:%.*]] = sext i16 [[TMP12]] to i32
8233 // CHECK8-NEXT:    [[ADD14:%.*]] = add nsw i32 [[CONV]], 1
8234 // CHECK8-NEXT:    [[CONV15:%.*]] = trunc i32 [[ADD14]] to i16
8235 // CHECK8-NEXT:    store i16 [[CONV15]], i16* [[AA]], align 2
8236 // CHECK8-NEXT:    br label [[FOR_INC16:%.*]]
8237 // CHECK8:       for.inc16:
8238 // CHECK8-NEXT:    [[TMP13:%.*]] = load i32, i32* [[I10]], align 4
8239 // CHECK8-NEXT:    [[INC17:%.*]] = add nsw i32 [[TMP13]], 1
8240 // CHECK8-NEXT:    store i32 [[INC17]], i32* [[I10]], align 4
8241 // CHECK8-NEXT:    br label [[FOR_COND11]], !llvm.loop [[LOOP6:![0-9]+]]
8242 // CHECK8:       for.end18:
8243 // CHECK8-NEXT:    store i32 0, i32* [[I19]], align 4
8244 // CHECK8-NEXT:    br label [[FOR_COND20:%.*]]
8245 // CHECK8:       for.cond20:
8246 // CHECK8-NEXT:    [[TMP14:%.*]] = load i32, i32* [[I19]], align 4
8247 // CHECK8-NEXT:    [[CMP21:%.*]] = icmp slt i32 [[TMP14]], 10
8248 // CHECK8-NEXT:    br i1 [[CMP21]], label [[FOR_BODY22:%.*]], label [[FOR_END29:%.*]]
8249 // CHECK8:       for.body22:
8250 // CHECK8-NEXT:    [[TMP15:%.*]] = load i32, i32* [[A]], align 4
8251 // CHECK8-NEXT:    [[ADD23:%.*]] = add nsw i32 [[TMP15]], 1
8252 // CHECK8-NEXT:    store i32 [[ADD23]], i32* [[A]], align 4
8253 // CHECK8-NEXT:    [[TMP16:%.*]] = load i16, i16* [[AA]], align 2
8254 // CHECK8-NEXT:    [[CONV24:%.*]] = sext i16 [[TMP16]] to i32
8255 // CHECK8-NEXT:    [[ADD25:%.*]] = add nsw i32 [[CONV24]], 1
8256 // CHECK8-NEXT:    [[CONV26:%.*]] = trunc i32 [[ADD25]] to i16
8257 // CHECK8-NEXT:    store i16 [[CONV26]], i16* [[AA]], align 2
8258 // CHECK8-NEXT:    br label [[FOR_INC27:%.*]]
8259 // CHECK8:       for.inc27:
8260 // CHECK8-NEXT:    [[TMP17:%.*]] = load i32, i32* [[I19]], align 4
8261 // CHECK8-NEXT:    [[INC28:%.*]] = add nsw i32 [[TMP17]], 1
8262 // CHECK8-NEXT:    store i32 [[INC28]], i32* [[I19]], align 4
8263 // CHECK8-NEXT:    br label [[FOR_COND20]], !llvm.loop [[LOOP7:![0-9]+]]
8264 // CHECK8:       for.end29:
8265 // CHECK8-NEXT:    [[TMP18:%.*]] = load i32, i32* [[N_ADDR]], align 4
8266 // CHECK8-NEXT:    store i32 [[TMP18]], i32* [[DOTCAPTURE_EXPR_30]], align 4
8267 // CHECK8-NEXT:    store i32 0, i32* [[I31]], align 4
8268 // CHECK8-NEXT:    br label [[FOR_COND32:%.*]]
8269 // CHECK8:       for.cond32:
8270 // CHECK8-NEXT:    [[TMP19:%.*]] = load i32, i32* [[I31]], align 4
8271 // CHECK8-NEXT:    [[CMP33:%.*]] = icmp slt i32 [[TMP19]], 10
8272 // CHECK8-NEXT:    br i1 [[CMP33]], label [[FOR_BODY34:%.*]], label [[FOR_END55:%.*]]
8273 // CHECK8:       for.body34:
8274 // CHECK8-NEXT:    [[TMP20:%.*]] = load i32, i32* [[A]], align 4
8275 // CHECK8-NEXT:    [[ADD35:%.*]] = add nsw i32 [[TMP20]], 1
8276 // CHECK8-NEXT:    store i32 [[ADD35]], i32* [[A]], align 4
8277 // CHECK8-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2
8278 // CHECK8-NEXT:    [[TMP21:%.*]] = load float, float* [[ARRAYIDX]], align 4
8279 // CHECK8-NEXT:    [[CONV36:%.*]] = fpext float [[TMP21]] to double
8280 // CHECK8-NEXT:    [[ADD37:%.*]] = fadd double [[CONV36]], 1.000000e+00
8281 // CHECK8-NEXT:    [[CONV38:%.*]] = fptrunc double [[ADD37]] to float
8282 // CHECK8-NEXT:    store float [[CONV38]], float* [[ARRAYIDX]], align 4
8283 // CHECK8-NEXT:    [[ARRAYIDX39:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3
8284 // CHECK8-NEXT:    [[TMP22:%.*]] = load float, float* [[ARRAYIDX39]], align 4
8285 // CHECK8-NEXT:    [[CONV40:%.*]] = fpext float [[TMP22]] to double
8286 // CHECK8-NEXT:    [[ADD41:%.*]] = fadd double [[CONV40]], 1.000000e+00
8287 // CHECK8-NEXT:    [[CONV42:%.*]] = fptrunc double [[ADD41]] to float
8288 // CHECK8-NEXT:    store float [[CONV42]], float* [[ARRAYIDX39]], align 4
8289 // CHECK8-NEXT:    [[ARRAYIDX43:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1
8290 // CHECK8-NEXT:    [[ARRAYIDX44:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX43]], i32 0, i32 2
8291 // CHECK8-NEXT:    [[TMP23:%.*]] = load double, double* [[ARRAYIDX44]], align 8
8292 // CHECK8-NEXT:    [[ADD45:%.*]] = fadd double [[TMP23]], 1.000000e+00
8293 // CHECK8-NEXT:    store double [[ADD45]], double* [[ARRAYIDX44]], align 8
8294 // CHECK8-NEXT:    [[TMP24:%.*]] = mul nsw i32 1, [[TMP2]]
8295 // CHECK8-NEXT:    [[ARRAYIDX46:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP24]]
8296 // CHECK8-NEXT:    [[ARRAYIDX47:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX46]], i32 3
8297 // CHECK8-NEXT:    [[TMP25:%.*]] = load double, double* [[ARRAYIDX47]], align 8
8298 // CHECK8-NEXT:    [[ADD48:%.*]] = fadd double [[TMP25]], 1.000000e+00
8299 // CHECK8-NEXT:    store double [[ADD48]], double* [[ARRAYIDX47]], align 8
8300 // CHECK8-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0
8301 // CHECK8-NEXT:    [[TMP26:%.*]] = load i64, i64* [[X]], align 4
8302 // CHECK8-NEXT:    [[ADD49:%.*]] = add nsw i64 [[TMP26]], 1
8303 // CHECK8-NEXT:    store i64 [[ADD49]], i64* [[X]], align 4
8304 // CHECK8-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1
8305 // CHECK8-NEXT:    [[TMP27:%.*]] = load i8, i8* [[Y]], align 4
8306 // CHECK8-NEXT:    [[CONV50:%.*]] = sext i8 [[TMP27]] to i32
8307 // CHECK8-NEXT:    [[ADD51:%.*]] = add nsw i32 [[CONV50]], 1
8308 // CHECK8-NEXT:    [[CONV52:%.*]] = trunc i32 [[ADD51]] to i8
8309 // CHECK8-NEXT:    store i8 [[CONV52]], i8* [[Y]], align 4
8310 // CHECK8-NEXT:    br label [[FOR_INC53:%.*]]
8311 // CHECK8:       for.inc53:
8312 // CHECK8-NEXT:    [[TMP28:%.*]] = load i32, i32* [[I31]], align 4
8313 // CHECK8-NEXT:    [[INC54:%.*]] = add nsw i32 [[TMP28]], 1
8314 // CHECK8-NEXT:    store i32 [[INC54]], i32* [[I31]], align 4
8315 // CHECK8-NEXT:    br label [[FOR_COND32]], !llvm.loop [[LOOP8:![0-9]+]]
8316 // CHECK8:       for.end55:
8317 // CHECK8-NEXT:    [[TMP29:%.*]] = load i32, i32* [[A]], align 4
8318 // CHECK8-NEXT:    [[TMP30:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
8319 // CHECK8-NEXT:    call void @llvm.stackrestore(i8* [[TMP30]])
8320 // CHECK8-NEXT:    ret i32 [[TMP29]]
8321 //
8322 //
8323 // CHECK8-LABEL: define {{[^@]+}}@_Z3bari
8324 // CHECK8-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
8325 // CHECK8-NEXT:  entry:
8326 // CHECK8-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
8327 // CHECK8-NEXT:    [[A:%.*]] = alloca i32, align 4
8328 // CHECK8-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4
8329 // CHECK8-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
8330 // CHECK8-NEXT:    store i32 0, i32* [[A]], align 4
8331 // CHECK8-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
8332 // CHECK8-NEXT:    [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]])
8333 // CHECK8-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
8334 // CHECK8-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
8335 // CHECK8-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
8336 // CHECK8-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
8337 // CHECK8-NEXT:    [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]])
8338 // CHECK8-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
8339 // CHECK8-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
8340 // CHECK8-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
8341 // CHECK8-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
8342 // CHECK8-NEXT:    [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]])
8343 // CHECK8-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
8344 // CHECK8-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
8345 // CHECK8-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
8346 // CHECK8-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
8347 // CHECK8-NEXT:    [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]])
8348 // CHECK8-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
8349 // CHECK8-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
8350 // CHECK8-NEXT:    store i32 [[ADD6]], i32* [[A]], align 4
8351 // CHECK8-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
8352 // CHECK8-NEXT:    ret i32 [[TMP8]]
8353 //
8354 //
8355 // CHECK8-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
8356 // CHECK8-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 {
8357 // CHECK8-NEXT:  entry:
8358 // CHECK8-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
8359 // CHECK8-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
8360 // CHECK8-NEXT:    [[B:%.*]] = alloca i32, align 4
8361 // CHECK8-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 4
8362 // CHECK8-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 4
8363 // CHECK8-NEXT:    [[I:%.*]] = alloca i32, align 4
8364 // CHECK8-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
8365 // CHECK8-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
8366 // CHECK8-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
8367 // CHECK8-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
8368 // CHECK8-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
8369 // CHECK8-NEXT:    store i32 [[ADD]], i32* [[B]], align 4
8370 // CHECK8-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
8371 // CHECK8-NEXT:    [[TMP2:%.*]] = call i8* @llvm.stacksave()
8372 // CHECK8-NEXT:    store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4
8373 // CHECK8-NEXT:    [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]
8374 // CHECK8-NEXT:    [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2
8375 // CHECK8-NEXT:    store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
8376 // CHECK8-NEXT:    store i32 0, i32* [[I]], align 4
8377 // CHECK8-NEXT:    br label [[FOR_COND:%.*]]
8378 // CHECK8:       for.cond:
8379 // CHECK8-NEXT:    [[TMP4:%.*]] = load i32, i32* [[I]], align 4
8380 // CHECK8-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP4]], 10
8381 // CHECK8-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
8382 // CHECK8:       for.body:
8383 // CHECK8-NEXT:    [[TMP5:%.*]] = load i32, i32* [[B]], align 4
8384 // CHECK8-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP5]] to double
8385 // CHECK8-NEXT:    [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00
8386 // CHECK8-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
8387 // CHECK8-NEXT:    store double [[ADD2]], double* [[A]], align 4
8388 // CHECK8-NEXT:    [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
8389 // CHECK8-NEXT:    [[TMP6:%.*]] = load double, double* [[A3]], align 4
8390 // CHECK8-NEXT:    [[INC:%.*]] = fadd double [[TMP6]], 1.000000e+00
8391 // CHECK8-NEXT:    store double [[INC]], double* [[A3]], align 4
8392 // CHECK8-NEXT:    [[CONV4:%.*]] = fptosi double [[INC]] to i16
8393 // CHECK8-NEXT:    [[TMP7:%.*]] = mul nsw i32 1, [[TMP1]]
8394 // CHECK8-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP7]]
8395 // CHECK8-NEXT:    [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
8396 // CHECK8-NEXT:    store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2
8397 // CHECK8-NEXT:    br label [[FOR_INC:%.*]]
8398 // CHECK8:       for.inc:
8399 // CHECK8-NEXT:    [[TMP8:%.*]] = load i32, i32* [[I]], align 4
8400 // CHECK8-NEXT:    [[INC6:%.*]] = add nsw i32 [[TMP8]], 1
8401 // CHECK8-NEXT:    store i32 [[INC6]], i32* [[I]], align 4
8402 // CHECK8-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]
8403 // CHECK8:       for.end:
8404 // CHECK8-NEXT:    [[TMP9:%.*]] = mul nsw i32 1, [[TMP1]]
8405 // CHECK8-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP9]]
8406 // CHECK8-NEXT:    [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX7]], i32 1
8407 // CHECK8-NEXT:    [[TMP10:%.*]] = load i16, i16* [[ARRAYIDX8]], align 2
8408 // CHECK8-NEXT:    [[CONV9:%.*]] = sext i16 [[TMP10]] to i32
8409 // CHECK8-NEXT:    [[TMP11:%.*]] = load i32, i32* [[B]], align 4
8410 // CHECK8-NEXT:    [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[TMP11]]
8411 // CHECK8-NEXT:    [[TMP12:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
8412 // CHECK8-NEXT:    call void @llvm.stackrestore(i8* [[TMP12]])
8413 // CHECK8-NEXT:    ret i32 [[ADD10]]
8414 //
8415 //
8416 // CHECK8-LABEL: define {{[^@]+}}@_ZL7fstatici
8417 // CHECK8-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
8418 // CHECK8-NEXT:  entry:
8419 // CHECK8-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
8420 // CHECK8-NEXT:    [[A:%.*]] = alloca i32, align 4
8421 // CHECK8-NEXT:    [[AA:%.*]] = alloca i16, align 2
8422 // CHECK8-NEXT:    [[AAA:%.*]] = alloca i8, align 1
8423 // CHECK8-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
8424 // CHECK8-NEXT:    [[I:%.*]] = alloca i32, align 4
8425 // CHECK8-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
8426 // CHECK8-NEXT:    store i32 0, i32* [[A]], align 4
8427 // CHECK8-NEXT:    store i16 0, i16* [[AA]], align 2
8428 // CHECK8-NEXT:    store i8 0, i8* [[AAA]], align 1
8429 // CHECK8-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
8430 // CHECK8-NEXT:    store i32 [[TMP0]], i32* [[I]], align 4
8431 // CHECK8-NEXT:    br label [[FOR_COND:%.*]]
8432 // CHECK8:       for.cond:
8433 // CHECK8-NEXT:    [[TMP1:%.*]] = load i32, i32* [[I]], align 4
8434 // CHECK8-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
8435 // CHECK8-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP1]], [[TMP2]]
8436 // CHECK8-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
8437 // CHECK8:       for.body:
8438 // CHECK8-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
8439 // CHECK8-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP3]], 1
8440 // CHECK8-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
8441 // CHECK8-NEXT:    [[TMP4:%.*]] = load i16, i16* [[AA]], align 2
8442 // CHECK8-NEXT:    [[CONV:%.*]] = sext i16 [[TMP4]] to i32
8443 // CHECK8-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
8444 // CHECK8-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
8445 // CHECK8-NEXT:    store i16 [[CONV2]], i16* [[AA]], align 2
8446 // CHECK8-NEXT:    [[TMP5:%.*]] = load i8, i8* [[AAA]], align 1
8447 // CHECK8-NEXT:    [[CONV3:%.*]] = sext i8 [[TMP5]] to i32
8448 // CHECK8-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
8449 // CHECK8-NEXT:    [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8
8450 // CHECK8-NEXT:    store i8 [[CONV5]], i8* [[AAA]], align 1
8451 // CHECK8-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2
8452 // CHECK8-NEXT:    [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
8453 // CHECK8-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP6]], 1
8454 // CHECK8-NEXT:    store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4
8455 // CHECK8-NEXT:    br label [[FOR_INC:%.*]]
8456 // CHECK8:       for.inc:
8457 // CHECK8-NEXT:    [[TMP7:%.*]] = load i32, i32* [[I]], align 4
8458 // CHECK8-NEXT:    [[INC:%.*]] = add nsw i32 [[TMP7]], 1
8459 // CHECK8-NEXT:    store i32 [[INC]], i32* [[I]], align 4
8460 // CHECK8-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]
8461 // CHECK8:       for.end:
8462 // CHECK8-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
8463 // CHECK8-NEXT:    ret i32 [[TMP8]]
8464 //
8465 //
8466 // CHECK8-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
8467 // CHECK8-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat {
8468 // CHECK8-NEXT:  entry:
8469 // CHECK8-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
8470 // CHECK8-NEXT:    [[A:%.*]] = alloca i32, align 4
8471 // CHECK8-NEXT:    [[AA:%.*]] = alloca i16, align 2
8472 // CHECK8-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
8473 // CHECK8-NEXT:    [[I:%.*]] = alloca i32, align 4
8474 // CHECK8-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
8475 // CHECK8-NEXT:    store i32 0, i32* [[A]], align 4
8476 // CHECK8-NEXT:    store i16 0, i16* [[AA]], align 2
8477 // CHECK8-NEXT:    store i32 0, i32* [[I]], align 4
8478 // CHECK8-NEXT:    br label [[FOR_COND:%.*]]
8479 // CHECK8:       for.cond:
8480 // CHECK8-NEXT:    [[TMP0:%.*]] = load i32, i32* [[I]], align 4
8481 // CHECK8-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10
8482 // CHECK8-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
8483 // CHECK8:       for.body:
8484 // CHECK8-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
8485 // CHECK8-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
8486 // CHECK8-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
8487 // CHECK8-NEXT:    [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
8488 // CHECK8-NEXT:    [[CONV:%.*]] = sext i16 [[TMP2]] to i32
8489 // CHECK8-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
8490 // CHECK8-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
8491 // CHECK8-NEXT:    store i16 [[CONV2]], i16* [[AA]], align 2
8492 // CHECK8-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2
8493 // CHECK8-NEXT:    [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
8494 // CHECK8-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1
8495 // CHECK8-NEXT:    store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4
8496 // CHECK8-NEXT:    br label [[FOR_INC:%.*]]
8497 // CHECK8:       for.inc:
8498 // CHECK8-NEXT:    [[TMP4:%.*]] = load i32, i32* [[I]], align 4
8499 // CHECK8-NEXT:    [[INC:%.*]] = add nsw i32 [[TMP4]], 1
8500 // CHECK8-NEXT:    store i32 [[INC]], i32* [[I]], align 4
8501 // CHECK8-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]
8502 // CHECK8:       for.end:
8503 // CHECK8-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
8504 // CHECK8-NEXT:    ret i32 [[TMP5]]
8505 //
8506 //
8507 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103
8508 // CHECK9-SAME: (i64 [[AA:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] {
8509 // CHECK9-NEXT:  entry:
8510 // CHECK9-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
8511 // CHECK9-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
8512 // CHECK9-NEXT:    [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8
8513 // CHECK9-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
8514 // CHECK9-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]])
8515 // CHECK9-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
8516 // CHECK9-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
8517 // CHECK9-NEXT:    store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8
8518 // CHECK9-NEXT:    [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
8519 // CHECK9-NEXT:    [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
8520 // CHECK9-NEXT:    [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32*
8521 // CHECK9-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 8
8522 // CHECK9-NEXT:    [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 8
8523 // CHECK9-NEXT:    call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
8524 // CHECK9-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV]], align 8
8525 // CHECK9-NEXT:    [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
8526 // CHECK9-NEXT:    store i16 [[TMP3]], i16* [[CONV5]], align 2
8527 // CHECK9-NEXT:    [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
8528 // CHECK9-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]])
8529 // CHECK9-NEXT:    ret void
8530 //
8531 //
8532 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined.
8533 // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] {
8534 // CHECK9-NEXT:  entry:
8535 // CHECK9-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
8536 // CHECK9-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
8537 // CHECK9-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
8538 // CHECK9-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
8539 // CHECK9-NEXT:    [[TMP:%.*]] = alloca i32, align 4
8540 // CHECK9-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
8541 // CHECK9-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
8542 // CHECK9-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
8543 // CHECK9-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
8544 // CHECK9-NEXT:    [[I:%.*]] = alloca i32, align 4
8545 // CHECK9-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
8546 // CHECK9-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
8547 // CHECK9-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
8548 // CHECK9-NEXT:    [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
8549 // CHECK9-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
8550 // CHECK9-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
8551 // CHECK9-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
8552 // CHECK9-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
8553 // CHECK9-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
8554 // CHECK9-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
8555 // CHECK9-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
8556 // CHECK9-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
8557 // CHECK9-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
8558 // CHECK9-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
8559 // CHECK9:       cond.true:
8560 // CHECK9-NEXT:    br label [[COND_END:%.*]]
8561 // CHECK9:       cond.false:
8562 // CHECK9-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
8563 // CHECK9-NEXT:    br label [[COND_END]]
8564 // CHECK9:       cond.end:
8565 // CHECK9-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
8566 // CHECK9-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
8567 // CHECK9-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
8568 // CHECK9-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
8569 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
8570 // CHECK9:       omp.inner.for.cond:
8571 // CHECK9-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
8572 // CHECK9-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
8573 // CHECK9-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
8574 // CHECK9-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
8575 // CHECK9:       omp.inner.for.body:
8576 // CHECK9-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
8577 // CHECK9-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
8578 // CHECK9-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
8579 // CHECK9-NEXT:    store i32 [[ADD]], i32* [[I]], align 4
8580 // CHECK9-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
8581 // CHECK9:       omp.body.continue:
8582 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
8583 // CHECK9:       omp.inner.for.inc:
8584 // CHECK9-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
8585 // CHECK9-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
8586 // CHECK9-NEXT:    store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4
8587 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND]]
8588 // CHECK9:       omp.inner.for.end:
8589 // CHECK9-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
8590 // CHECK9:       omp.loop.exit:
8591 // CHECK9-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
8592 // CHECK9-NEXT:    ret void
8593 //
8594 //
8595 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113
8596 // CHECK9-SAME: (i64 [[AA:%.*]]) #[[ATTR0]] {
8597 // CHECK9-NEXT:  entry:
8598 // CHECK9-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
8599 // CHECK9-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
8600 // CHECK9-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
8601 // CHECK9-NEXT:    [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
8602 // CHECK9-NEXT:    [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8
8603 // CHECK9-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
8604 // CHECK9-NEXT:    store i16 [[TMP0]], i16* [[CONV1]], align 2
8605 // CHECK9-NEXT:    [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
8606 // CHECK9-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]])
8607 // CHECK9-NEXT:    ret void
8608 //
8609 //
8610 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1
8611 // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] {
8612 // CHECK9-NEXT:  entry:
8613 // CHECK9-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
8614 // CHECK9-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
8615 // CHECK9-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
8616 // CHECK9-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
8617 // CHECK9-NEXT:    [[TMP:%.*]] = alloca i32, align 4
8618 // CHECK9-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
8619 // CHECK9-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
8620 // CHECK9-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
8621 // CHECK9-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
8622 // CHECK9-NEXT:    [[I:%.*]] = alloca i32, align 4
8623 // CHECK9-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
8624 // CHECK9-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
8625 // CHECK9-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
8626 // CHECK9-NEXT:    [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
8627 // CHECK9-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
8628 // CHECK9-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
8629 // CHECK9-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
8630 // CHECK9-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
8631 // CHECK9-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
8632 // CHECK9-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
8633 // CHECK9-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
8634 // CHECK9-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
8635 // CHECK9-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
8636 // CHECK9-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
8637 // CHECK9:       cond.true:
8638 // CHECK9-NEXT:    br label [[COND_END:%.*]]
8639 // CHECK9:       cond.false:
8640 // CHECK9-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
8641 // CHECK9-NEXT:    br label [[COND_END]]
8642 // CHECK9:       cond.end:
8643 // CHECK9-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
8644 // CHECK9-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
8645 // CHECK9-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
8646 // CHECK9-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
8647 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
8648 // CHECK9:       omp.inner.for.cond:
8649 // CHECK9-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
8650 // CHECK9-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
8651 // CHECK9-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
8652 // CHECK9-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
8653 // CHECK9:       omp.inner.for.body:
8654 // CHECK9-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
8655 // CHECK9-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
8656 // CHECK9-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
8657 // CHECK9-NEXT:    store i32 [[ADD]], i32* [[I]], align 4
8658 // CHECK9-NEXT:    [[TMP8:%.*]] = load i16, i16* [[CONV]], align 8
8659 // CHECK9-NEXT:    [[CONV2:%.*]] = sext i16 [[TMP8]] to i32
8660 // CHECK9-NEXT:    [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
8661 // CHECK9-NEXT:    [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
8662 // CHECK9-NEXT:    store i16 [[CONV4]], i16* [[CONV]], align 8
8663 // CHECK9-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
8664 // CHECK9:       omp.body.continue:
8665 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
8666 // CHECK9:       omp.inner.for.inc:
8667 // CHECK9-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
8668 // CHECK9-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP9]], 1
8669 // CHECK9-NEXT:    store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4
8670 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND]]
8671 // CHECK9:       omp.inner.for.end:
8672 // CHECK9-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
8673 // CHECK9:       omp.loop.exit:
8674 // CHECK9-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
8675 // CHECK9-NEXT:    ret void
8676 //
8677 //
8678 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120
8679 // CHECK9-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] {
8680 // CHECK9-NEXT:  entry:
8681 // CHECK9-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
8682 // CHECK9-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
8683 // CHECK9-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
8684 // CHECK9-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
8685 // CHECK9-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
8686 // CHECK9-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
8687 // CHECK9-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
8688 // CHECK9-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
8689 // CHECK9-NEXT:    [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
8690 // CHECK9-NEXT:    [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
8691 // CHECK9-NEXT:    store i32 [[TMP0]], i32* [[CONV2]], align 4
8692 // CHECK9-NEXT:    [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
8693 // CHECK9-NEXT:    [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
8694 // CHECK9-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
8695 // CHECK9-NEXT:    store i16 [[TMP2]], i16* [[CONV3]], align 2
8696 // CHECK9-NEXT:    [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
8697 // CHECK9-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
8698 // CHECK9-NEXT:    ret void
8699 //
8700 //
8701 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..2
8702 // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] {
8703 // CHECK9-NEXT:  entry:
8704 // CHECK9-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
8705 // CHECK9-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
8706 // CHECK9-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
8707 // CHECK9-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
8708 // CHECK9-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
8709 // CHECK9-NEXT:    [[TMP:%.*]] = alloca i32, align 4
8710 // CHECK9-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
8711 // CHECK9-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
8712 // CHECK9-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
8713 // CHECK9-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
8714 // CHECK9-NEXT:    [[I:%.*]] = alloca i32, align 4
8715 // CHECK9-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
8716 // CHECK9-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
8717 // CHECK9-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
8718 // CHECK9-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
8719 // CHECK9-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
8720 // CHECK9-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
8721 // CHECK9-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
8722 // CHECK9-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
8723 // CHECK9-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
8724 // CHECK9-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
8725 // CHECK9-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
8726 // CHECK9-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
8727 // CHECK9-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
8728 // CHECK9-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
8729 // CHECK9-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
8730 // CHECK9-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
8731 // CHECK9:       cond.true:
8732 // CHECK9-NEXT:    br label [[COND_END:%.*]]
8733 // CHECK9:       cond.false:
8734 // CHECK9-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
8735 // CHECK9-NEXT:    br label [[COND_END]]
8736 // CHECK9:       cond.end:
8737 // CHECK9-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
8738 // CHECK9-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
8739 // CHECK9-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
8740 // CHECK9-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
8741 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
8742 // CHECK9:       omp.inner.for.cond:
8743 // CHECK9-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
8744 // CHECK9-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
8745 // CHECK9-NEXT:    [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
8746 // CHECK9-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
8747 // CHECK9:       omp.inner.for.body:
8748 // CHECK9-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
8749 // CHECK9-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
8750 // CHECK9-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
8751 // CHECK9-NEXT:    store i32 [[ADD]], i32* [[I]], align 4
8752 // CHECK9-NEXT:    [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
8753 // CHECK9-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
8754 // CHECK9-NEXT:    store i32 [[ADD3]], i32* [[CONV]], align 8
8755 // CHECK9-NEXT:    [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 8
8756 // CHECK9-NEXT:    [[CONV4:%.*]] = sext i16 [[TMP9]] to i32
8757 // CHECK9-NEXT:    [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
8758 // CHECK9-NEXT:    [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
8759 // CHECK9-NEXT:    store i16 [[CONV6]], i16* [[CONV1]], align 8
8760 // CHECK9-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
8761 // CHECK9:       omp.body.continue:
8762 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
8763 // CHECK9:       omp.inner.for.inc:
8764 // CHECK9-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
8765 // CHECK9-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1
8766 // CHECK9-NEXT:    store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4
8767 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND]]
8768 // CHECK9:       omp.inner.for.end:
8769 // CHECK9-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
8770 // CHECK9:       omp.loop.exit:
8771 // CHECK9-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
8772 // CHECK9-NEXT:    ret void
8773 //
8774 //
8775 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145
8776 // CHECK9-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
8777 // CHECK9-NEXT:  entry:
8778 // CHECK9-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
8779 // CHECK9-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
8780 // CHECK9-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
8781 // CHECK9-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 8
8782 // CHECK9-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
8783 // CHECK9-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
8784 // CHECK9-NEXT:    [[VLA_ADDR4:%.*]] = alloca i64, align 8
8785 // CHECK9-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 8
8786 // CHECK9-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
8787 // CHECK9-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
8788 // CHECK9-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
8789 // CHECK9-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
8790 // CHECK9-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
8791 // CHECK9-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
8792 // CHECK9-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
8793 // CHECK9-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 8
8794 // CHECK9-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
8795 // CHECK9-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
8796 // CHECK9-NEXT:    store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
8797 // CHECK9-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 8
8798 // CHECK9-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
8799 // CHECK9-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
8800 // CHECK9-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
8801 // CHECK9-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
8802 // CHECK9-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
8803 // CHECK9-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
8804 // CHECK9-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
8805 // CHECK9-NEXT:    [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
8806 // CHECK9-NEXT:    [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
8807 // CHECK9-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
8808 // CHECK9-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
8809 // CHECK9-NEXT:    [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
8810 // CHECK9-NEXT:    [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
8811 // CHECK9-NEXT:    [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32*
8812 // CHECK9-NEXT:    store i32 [[TMP8]], i32* [[CONV6]], align 4
8813 // CHECK9-NEXT:    [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
8814 // CHECK9-NEXT:    [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 8
8815 // CHECK9-NEXT:    [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
8816 // CHECK9-NEXT:    store i32 [[TMP10]], i32* [[CONV7]], align 4
8817 // CHECK9-NEXT:    [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
8818 // CHECK9-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]])
8819 // CHECK9-NEXT:    ret void
8820 //
8821 //
8822 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..3
8823 // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
8824 // CHECK9-NEXT:  entry:
8825 // CHECK9-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
8826 // CHECK9-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
8827 // CHECK9-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
8828 // CHECK9-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
8829 // CHECK9-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
8830 // CHECK9-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 8
8831 // CHECK9-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
8832 // CHECK9-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
8833 // CHECK9-NEXT:    [[VLA_ADDR4:%.*]] = alloca i64, align 8
8834 // CHECK9-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 8
8835 // CHECK9-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
8836 // CHECK9-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
8837 // CHECK9-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
8838 // CHECK9-NEXT:    [[TMP:%.*]] = alloca i32, align 4
8839 // CHECK9-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
8840 // CHECK9-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
8841 // CHECK9-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
8842 // CHECK9-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
8843 // CHECK9-NEXT:    [[I:%.*]] = alloca i32, align 4
8844 // CHECK9-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
8845 // CHECK9-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
8846 // CHECK9-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
8847 // CHECK9-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
8848 // CHECK9-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
8849 // CHECK9-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 8
8850 // CHECK9-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
8851 // CHECK9-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
8852 // CHECK9-NEXT:    store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
8853 // CHECK9-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 8
8854 // CHECK9-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
8855 // CHECK9-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
8856 // CHECK9-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
8857 // CHECK9-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
8858 // CHECK9-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
8859 // CHECK9-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
8860 // CHECK9-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
8861 // CHECK9-NEXT:    [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
8862 // CHECK9-NEXT:    [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
8863 // CHECK9-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
8864 // CHECK9-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
8865 // CHECK9-NEXT:    [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
8866 // CHECK9-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
8867 // CHECK9-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
8868 // CHECK9-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
8869 // CHECK9-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
8870 // CHECK9-NEXT:    [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 8
8871 // CHECK9-NEXT:    [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
8872 // CHECK9-NEXT:    [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
8873 // CHECK9-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
8874 // CHECK9-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
8875 // CHECK9:       omp.dispatch.cond:
8876 // CHECK9-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
8877 // CHECK9-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 9
8878 // CHECK9-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
8879 // CHECK9:       cond.true:
8880 // CHECK9-NEXT:    br label [[COND_END:%.*]]
8881 // CHECK9:       cond.false:
8882 // CHECK9-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
8883 // CHECK9-NEXT:    br label [[COND_END]]
8884 // CHECK9:       cond.end:
8885 // CHECK9-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
8886 // CHECK9-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
8887 // CHECK9-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
8888 // CHECK9-NEXT:    store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
8889 // CHECK9-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
8890 // CHECK9-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
8891 // CHECK9-NEXT:    [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
8892 // CHECK9-NEXT:    br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
8893 // CHECK9:       omp.dispatch.body:
8894 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
8895 // CHECK9:       omp.inner.for.cond:
8896 // CHECK9-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
8897 // CHECK9-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !11
8898 // CHECK9-NEXT:    [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
8899 // CHECK9-NEXT:    br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
8900 // CHECK9:       omp.inner.for.body:
8901 // CHECK9-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
8902 // CHECK9-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
8903 // CHECK9-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
8904 // CHECK9-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11
8905 // CHECK9-NEXT:    [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !11
8906 // CHECK9-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP19]], 1
8907 // CHECK9-NEXT:    store i32 [[ADD8]], i32* [[CONV]], align 8, !llvm.access.group !11
8908 // CHECK9-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
8909 // CHECK9-NEXT:    [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !11
8910 // CHECK9-NEXT:    [[CONV9:%.*]] = fpext float [[TMP20]] to double
8911 // CHECK9-NEXT:    [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00
8912 // CHECK9-NEXT:    [[CONV11:%.*]] = fptrunc double [[ADD10]] to float
8913 // CHECK9-NEXT:    store float [[CONV11]], float* [[ARRAYIDX]], align 4, !llvm.access.group !11
8914 // CHECK9-NEXT:    [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3
8915 // CHECK9-NEXT:    [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4, !llvm.access.group !11
8916 // CHECK9-NEXT:    [[CONV13:%.*]] = fpext float [[TMP21]] to double
8917 // CHECK9-NEXT:    [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00
8918 // CHECK9-NEXT:    [[CONV15:%.*]] = fptrunc double [[ADD14]] to float
8919 // CHECK9-NEXT:    store float [[CONV15]], float* [[ARRAYIDX12]], align 4, !llvm.access.group !11
8920 // CHECK9-NEXT:    [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1
8921 // CHECK9-NEXT:    [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i64 0, i64 2
8922 // CHECK9-NEXT:    [[TMP22:%.*]] = load double, double* [[ARRAYIDX17]], align 8, !llvm.access.group !11
8923 // CHECK9-NEXT:    [[ADD18:%.*]] = fadd double [[TMP22]], 1.000000e+00
8924 // CHECK9-NEXT:    store double [[ADD18]], double* [[ARRAYIDX17]], align 8, !llvm.access.group !11
8925 // CHECK9-NEXT:    [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]]
8926 // CHECK9-NEXT:    [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP23]]
8927 // CHECK9-NEXT:    [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i64 3
8928 // CHECK9-NEXT:    [[TMP24:%.*]] = load double, double* [[ARRAYIDX20]], align 8, !llvm.access.group !11
8929 // CHECK9-NEXT:    [[ADD21:%.*]] = fadd double [[TMP24]], 1.000000e+00
8930 // CHECK9-NEXT:    store double [[ADD21]], double* [[ARRAYIDX20]], align 8, !llvm.access.group !11
8931 // CHECK9-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0
8932 // CHECK9-NEXT:    [[TMP25:%.*]] = load i64, i64* [[X]], align 8, !llvm.access.group !11
8933 // CHECK9-NEXT:    [[ADD22:%.*]] = add nsw i64 [[TMP25]], 1
8934 // CHECK9-NEXT:    store i64 [[ADD22]], i64* [[X]], align 8, !llvm.access.group !11
8935 // CHECK9-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1
8936 // CHECK9-NEXT:    [[TMP26:%.*]] = load i8, i8* [[Y]], align 8, !llvm.access.group !11
8937 // CHECK9-NEXT:    [[CONV23:%.*]] = sext i8 [[TMP26]] to i32
8938 // CHECK9-NEXT:    [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1
8939 // CHECK9-NEXT:    [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8
8940 // CHECK9-NEXT:    store i8 [[CONV25]], i8* [[Y]], align 8, !llvm.access.group !11
8941 // CHECK9-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
8942 // CHECK9:       omp.body.continue:
8943 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
8944 // CHECK9:       omp.inner.for.inc:
8945 // CHECK9-NEXT:    [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
8946 // CHECK9-NEXT:    [[ADD26:%.*]] = add nsw i32 [[TMP27]], 1
8947 // CHECK9-NEXT:    store i32 [[ADD26]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
8948 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]
8949 // CHECK9:       omp.inner.for.end:
8950 // CHECK9-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
8951 // CHECK9:       omp.dispatch.inc:
8952 // CHECK9-NEXT:    [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
8953 // CHECK9-NEXT:    [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
8954 // CHECK9-NEXT:    [[ADD27:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]
8955 // CHECK9-NEXT:    store i32 [[ADD27]], i32* [[DOTOMP_LB]], align 4
8956 // CHECK9-NEXT:    [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
8957 // CHECK9-NEXT:    [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
8958 // CHECK9-NEXT:    [[ADD28:%.*]] = add nsw i32 [[TMP30]], [[TMP31]]
8959 // CHECK9-NEXT:    store i32 [[ADD28]], i32* [[DOTOMP_UB]], align 4
8960 // CHECK9-NEXT:    br label [[OMP_DISPATCH_COND]]
8961 // CHECK9:       omp.dispatch.end:
8962 // CHECK9-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]])
8963 // CHECK9-NEXT:    ret void
8964 //
8965 //
8966 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200
8967 // CHECK9-SAME: (i64 [[N:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
8968 // CHECK9-NEXT:  entry:
8969 // CHECK9-NEXT:    [[N_ADDR:%.*]] = alloca i64, align 8
8970 // CHECK9-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
8971 // CHECK9-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
8972 // CHECK9-NEXT:    [[AAA_ADDR:%.*]] = alloca i64, align 8
8973 // CHECK9-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
8974 // CHECK9-NEXT:    [[N_CASTED:%.*]] = alloca i64, align 8
8975 // CHECK9-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
8976 // CHECK9-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
8977 // CHECK9-NEXT:    [[AAA_CASTED:%.*]] = alloca i64, align 8
8978 // CHECK9-NEXT:    store i64 [[N]], i64* [[N_ADDR]], align 8
8979 // CHECK9-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
8980 // CHECK9-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
8981 // CHECK9-NEXT:    store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
8982 // CHECK9-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
8983 // CHECK9-NEXT:    [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
8984 // CHECK9-NEXT:    [[CONV1:%.*]] = bitcast i64* [[A_ADDR]] to i32*
8985 // CHECK9-NEXT:    [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
8986 // CHECK9-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
8987 // CHECK9-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
8988 // CHECK9-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
8989 // CHECK9-NEXT:    [[CONV4:%.*]] = bitcast i64* [[N_CASTED]] to i32*
8990 // CHECK9-NEXT:    store i32 [[TMP1]], i32* [[CONV4]], align 4
8991 // CHECK9-NEXT:    [[TMP2:%.*]] = load i64, i64* [[N_CASTED]], align 8
8992 // CHECK9-NEXT:    [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 8
8993 // CHECK9-NEXT:    [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
8994 // CHECK9-NEXT:    store i32 [[TMP3]], i32* [[CONV5]], align 4
8995 // CHECK9-NEXT:    [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8
8996 // CHECK9-NEXT:    [[TMP5:%.*]] = load i16, i16* [[CONV2]], align 8
8997 // CHECK9-NEXT:    [[CONV6:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
8998 // CHECK9-NEXT:    store i16 [[TMP5]], i16* [[CONV6]], align 2
8999 // CHECK9-NEXT:    [[TMP6:%.*]] = load i64, i64* [[AA_CASTED]], align 8
9000 // CHECK9-NEXT:    [[TMP7:%.*]] = load i8, i8* [[CONV3]], align 8
9001 // CHECK9-NEXT:    [[CONV7:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
9002 // CHECK9-NEXT:    store i8 [[TMP7]], i8* [[CONV7]], align 1
9003 // CHECK9-NEXT:    [[TMP8:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
9004 // CHECK9-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]], [10 x i32]* [[TMP0]])
9005 // CHECK9-NEXT:    ret void
9006 //
9007 //
9008 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..4
9009 // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
9010 // CHECK9-NEXT:  entry:
9011 // CHECK9-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
9012 // CHECK9-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
9013 // CHECK9-NEXT:    [[N_ADDR:%.*]] = alloca i64, align 8
9014 // CHECK9-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
9015 // CHECK9-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
9016 // CHECK9-NEXT:    [[AAA_ADDR:%.*]] = alloca i64, align 8
9017 // CHECK9-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
9018 // CHECK9-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
9019 // CHECK9-NEXT:    [[TMP:%.*]] = alloca i32, align 4
9020 // CHECK9-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
9021 // CHECK9-NEXT:    [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4
9022 // CHECK9-NEXT:    [[DOTCAPTURE_EXPR_5:%.*]] = alloca i32, align 4
9023 // CHECK9-NEXT:    [[I:%.*]] = alloca i32, align 4
9024 // CHECK9-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
9025 // CHECK9-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
9026 // CHECK9-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
9027 // CHECK9-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
9028 // CHECK9-NEXT:    [[I8:%.*]] = alloca i32, align 4
9029 // CHECK9-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
9030 // CHECK9-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
9031 // CHECK9-NEXT:    store i64 [[N]], i64* [[N_ADDR]], align 8
9032 // CHECK9-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
9033 // CHECK9-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
9034 // CHECK9-NEXT:    store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
9035 // CHECK9-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
9036 // CHECK9-NEXT:    [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
9037 // CHECK9-NEXT:    [[CONV1:%.*]] = bitcast i64* [[A_ADDR]] to i32*
9038 // CHECK9-NEXT:    [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
9039 // CHECK9-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
9040 // CHECK9-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
9041 // CHECK9-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV1]], align 8
9042 // CHECK9-NEXT:    store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
9043 // CHECK9-NEXT:    [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
9044 // CHECK9-NEXT:    store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_4]], align 4
9045 // CHECK9-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4
9046 // CHECK9-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
9047 // CHECK9-NEXT:    [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]]
9048 // CHECK9-NEXT:    [[SUB6:%.*]] = sub i32 [[SUB]], 1
9049 // CHECK9-NEXT:    [[ADD:%.*]] = add i32 [[SUB6]], 1
9050 // CHECK9-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], 1
9051 // CHECK9-NEXT:    [[SUB7:%.*]] = sub i32 [[DIV]], 1
9052 // CHECK9-NEXT:    store i32 [[SUB7]], i32* [[DOTCAPTURE_EXPR_5]], align 4
9053 // CHECK9-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
9054 // CHECK9-NEXT:    store i32 [[TMP5]], i32* [[I]], align 4
9055 // CHECK9-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
9056 // CHECK9-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4
9057 // CHECK9-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]]
9058 // CHECK9-NEXT:    br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
9059 // CHECK9:       omp.precond.then:
9060 // CHECK9-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
9061 // CHECK9-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4
9062 // CHECK9-NEXT:    store i32 [[TMP8]], i32* [[DOTOMP_UB]], align 4
9063 // CHECK9-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
9064 // CHECK9-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
9065 // CHECK9-NEXT:    [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
9066 // CHECK9-NEXT:    [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
9067 // CHECK9-NEXT:    call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
9068 // CHECK9-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
9069 // CHECK9-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4
9070 // CHECK9-NEXT:    [[CMP9:%.*]] = icmp ugt i32 [[TMP11]], [[TMP12]]
9071 // CHECK9-NEXT:    br i1 [[CMP9]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
9072 // CHECK9:       cond.true:
9073 // CHECK9-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4
9074 // CHECK9-NEXT:    br label [[COND_END:%.*]]
9075 // CHECK9:       cond.false:
9076 // CHECK9-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
9077 // CHECK9-NEXT:    br label [[COND_END]]
9078 // CHECK9:       cond.end:
9079 // CHECK9-NEXT:    [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ]
9080 // CHECK9-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
9081 // CHECK9-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
9082 // CHECK9-NEXT:    store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4
9083 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
9084 // CHECK9:       omp.inner.for.cond:
9085 // CHECK9-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
9086 // CHECK9-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
9087 // CHECK9-NEXT:    [[ADD10:%.*]] = add i32 [[TMP17]], 1
9088 // CHECK9-NEXT:    [[CMP11:%.*]] = icmp ult i32 [[TMP16]], [[ADD10]]
9089 // CHECK9-NEXT:    br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
9090 // CHECK9:       omp.inner.for.body:
9091 // CHECK9-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
9092 // CHECK9-NEXT:    [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
9093 // CHECK9-NEXT:    [[MUL:%.*]] = mul i32 [[TMP19]], 1
9094 // CHECK9-NEXT:    [[ADD12:%.*]] = add i32 [[TMP18]], [[MUL]]
9095 // CHECK9-NEXT:    store i32 [[ADD12]], i32* [[I8]], align 4
9096 // CHECK9-NEXT:    [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 8
9097 // CHECK9-NEXT:    [[ADD13:%.*]] = add nsw i32 [[TMP20]], 1
9098 // CHECK9-NEXT:    store i32 [[ADD13]], i32* [[CONV1]], align 8
9099 // CHECK9-NEXT:    [[TMP21:%.*]] = load i16, i16* [[CONV2]], align 8
9100 // CHECK9-NEXT:    [[CONV14:%.*]] = sext i16 [[TMP21]] to i32
9101 // CHECK9-NEXT:    [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1
9102 // CHECK9-NEXT:    [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16
9103 // CHECK9-NEXT:    store i16 [[CONV16]], i16* [[CONV2]], align 8
9104 // CHECK9-NEXT:    [[TMP22:%.*]] = load i8, i8* [[CONV3]], align 8
9105 // CHECK9-NEXT:    [[CONV17:%.*]] = sext i8 [[TMP22]] to i32
9106 // CHECK9-NEXT:    [[ADD18:%.*]] = add nsw i32 [[CONV17]], 1
9107 // CHECK9-NEXT:    [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8
9108 // CHECK9-NEXT:    store i8 [[CONV19]], i8* [[CONV3]], align 8
9109 // CHECK9-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
9110 // CHECK9-NEXT:    [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
9111 // CHECK9-NEXT:    [[ADD20:%.*]] = add nsw i32 [[TMP23]], 1
9112 // CHECK9-NEXT:    store i32 [[ADD20]], i32* [[ARRAYIDX]], align 4
9113 // CHECK9-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
9114 // CHECK9:       omp.body.continue:
9115 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
9116 // CHECK9:       omp.inner.for.inc:
9117 // CHECK9-NEXT:    [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
9118 // CHECK9-NEXT:    [[ADD21:%.*]] = add i32 [[TMP24]], 1
9119 // CHECK9-NEXT:    store i32 [[ADD21]], i32* [[DOTOMP_IV]], align 4
9120 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND]]
9121 // CHECK9:       omp.inner.for.end:
9122 // CHECK9-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
9123 // CHECK9:       omp.loop.exit:
9124 // CHECK9-NEXT:    [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
9125 // CHECK9-NEXT:    [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4
9126 // CHECK9-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]])
9127 // CHECK9-NEXT:    br label [[OMP_PRECOND_END]]
9128 // CHECK9:       omp.precond.end:
9129 // CHECK9-NEXT:    ret void
9130 //
9131 //
9132 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218
9133 // CHECK9-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {
9134 // CHECK9-NEXT:  entry:
9135 // CHECK9-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
9136 // CHECK9-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
9137 // CHECK9-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
9138 // CHECK9-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
9139 // CHECK9-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 8
9140 // CHECK9-NEXT:    [[B_CASTED:%.*]] = alloca i64, align 8
9141 // CHECK9-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
9142 // CHECK9-NEXT:    store i64 [[B]], i64* [[B_ADDR]], align 8
9143 // CHECK9-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
9144 // CHECK9-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
9145 // CHECK9-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 8
9146 // CHECK9-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
9147 // CHECK9-NEXT:    [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
9148 // CHECK9-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
9149 // CHECK9-NEXT:    [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
9150 // CHECK9-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
9151 // CHECK9-NEXT:    [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
9152 // CHECK9-NEXT:    [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32*
9153 // CHECK9-NEXT:    store i32 [[TMP4]], i32* [[CONV3]], align 4
9154 // CHECK9-NEXT:    [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
9155 // CHECK9-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]])
9156 // CHECK9-NEXT:    ret void
9157 //
9158 //
9159 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..5
9160 // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {
9161 // CHECK9-NEXT:  entry:
9162 // CHECK9-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
9163 // CHECK9-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
9164 // CHECK9-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
9165 // CHECK9-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
9166 // CHECK9-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
9167 // CHECK9-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
9168 // CHECK9-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 8
9169 // CHECK9-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
9170 // CHECK9-NEXT:    [[TMP:%.*]] = alloca i32, align 4
9171 // CHECK9-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
9172 // CHECK9-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
9173 // CHECK9-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
9174 // CHECK9-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
9175 // CHECK9-NEXT:    [[I:%.*]] = alloca i32, align 4
9176 // CHECK9-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
9177 // CHECK9-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
9178 // CHECK9-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
9179 // CHECK9-NEXT:    store i64 [[B]], i64* [[B_ADDR]], align 8
9180 // CHECK9-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
9181 // CHECK9-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
9182 // CHECK9-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 8
9183 // CHECK9-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
9184 // CHECK9-NEXT:    [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
9185 // CHECK9-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
9186 // CHECK9-NEXT:    [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
9187 // CHECK9-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
9188 // CHECK9-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
9189 // CHECK9-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
9190 // CHECK9-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
9191 // CHECK9-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
9192 // CHECK9-NEXT:    [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
9193 // CHECK9-NEXT:    [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
9194 // CHECK9-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
9195 // CHECK9-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
9196 // CHECK9-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 9
9197 // CHECK9-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
9198 // CHECK9:       cond.true:
9199 // CHECK9-NEXT:    br label [[COND_END:%.*]]
9200 // CHECK9:       cond.false:
9201 // CHECK9-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
9202 // CHECK9-NEXT:    br label [[COND_END]]
9203 // CHECK9:       cond.end:
9204 // CHECK9-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
9205 // CHECK9-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
9206 // CHECK9-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
9207 // CHECK9-NEXT:    store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
9208 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
9209 // CHECK9:       omp.inner.for.cond:
9210 // CHECK9-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
9211 // CHECK9-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
9212 // CHECK9-NEXT:    [[CMP3:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
9213 // CHECK9-NEXT:    br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
9214 // CHECK9:       omp.inner.for.body:
9215 // CHECK9-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
9216 // CHECK9-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
9217 // CHECK9-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
9218 // CHECK9-NEXT:    store i32 [[ADD]], i32* [[I]], align 4
9219 // CHECK9-NEXT:    [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8
9220 // CHECK9-NEXT:    [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double
9221 // CHECK9-NEXT:    [[ADD5:%.*]] = fadd double [[CONV4]], 1.500000e+00
9222 // CHECK9-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
9223 // CHECK9-NEXT:    store double [[ADD5]], double* [[A]], align 8
9224 // CHECK9-NEXT:    [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
9225 // CHECK9-NEXT:    [[TMP13:%.*]] = load double, double* [[A6]], align 8
9226 // CHECK9-NEXT:    [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00
9227 // CHECK9-NEXT:    store double [[INC]], double* [[A6]], align 8
9228 // CHECK9-NEXT:    [[CONV7:%.*]] = fptosi double [[INC]] to i16
9229 // CHECK9-NEXT:    [[TMP14:%.*]] = mul nsw i64 1, [[TMP2]]
9230 // CHECK9-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP14]]
9231 // CHECK9-NEXT:    [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
9232 // CHECK9-NEXT:    store i16 [[CONV7]], i16* [[ARRAYIDX8]], align 2
9233 // CHECK9-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
9234 // CHECK9:       omp.body.continue:
9235 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
9236 // CHECK9:       omp.inner.for.inc:
9237 // CHECK9-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
9238 // CHECK9-NEXT:    [[ADD9:%.*]] = add nsw i32 [[TMP15]], 1
9239 // CHECK9-NEXT:    store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4
9240 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND]]
9241 // CHECK9:       omp.inner.for.end:
9242 // CHECK9-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
9243 // CHECK9:       omp.loop.exit:
9244 // CHECK9-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
9245 // CHECK9-NEXT:    ret void
9246 //
9247 //
9248 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183
9249 // CHECK9-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
9250 // CHECK9-NEXT:  entry:
9251 // CHECK9-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
9252 // CHECK9-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
9253 // CHECK9-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
9254 // CHECK9-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
9255 // CHECK9-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
9256 // CHECK9-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
9257 // CHECK9-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
9258 // CHECK9-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
9259 // CHECK9-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
9260 // CHECK9-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
9261 // CHECK9-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
9262 // CHECK9-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
9263 // CHECK9-NEXT:    [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
9264 // CHECK9-NEXT:    store i32 [[TMP1]], i32* [[CONV2]], align 4
9265 // CHECK9-NEXT:    [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
9266 // CHECK9-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
9267 // CHECK9-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
9268 // CHECK9-NEXT:    store i16 [[TMP3]], i16* [[CONV3]], align 2
9269 // CHECK9-NEXT:    [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
9270 // CHECK9-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]])
9271 // CHECK9-NEXT:    ret void
9272 //
9273 //
9274 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..6
9275 // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
9276 // CHECK9-NEXT:  entry:
9277 // CHECK9-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
9278 // CHECK9-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
9279 // CHECK9-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
9280 // CHECK9-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
9281 // CHECK9-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
9282 // CHECK9-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
9283 // CHECK9-NEXT:    [[TMP:%.*]] = alloca i32, align 4
9284 // CHECK9-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
9285 // CHECK9-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
9286 // CHECK9-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
9287 // CHECK9-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
9288 // CHECK9-NEXT:    [[I:%.*]] = alloca i32, align 4
9289 // CHECK9-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
9290 // CHECK9-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
9291 // CHECK9-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
9292 // CHECK9-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
9293 // CHECK9-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
9294 // CHECK9-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
9295 // CHECK9-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
9296 // CHECK9-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
9297 // CHECK9-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
9298 // CHECK9-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
9299 // CHECK9-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
9300 // CHECK9-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
9301 // CHECK9-NEXT:    [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
9302 // CHECK9-NEXT:    [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
9303 // CHECK9-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
9304 // CHECK9-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
9305 // CHECK9-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9
9306 // CHECK9-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
9307 // CHECK9:       cond.true:
9308 // CHECK9-NEXT:    br label [[COND_END:%.*]]
9309 // CHECK9:       cond.false:
9310 // CHECK9-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
9311 // CHECK9-NEXT:    br label [[COND_END]]
9312 // CHECK9:       cond.end:
9313 // CHECK9-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
9314 // CHECK9-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
9315 // CHECK9-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
9316 // CHECK9-NEXT:    store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
9317 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
9318 // CHECK9:       omp.inner.for.cond:
9319 // CHECK9-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
9320 // CHECK9-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
9321 // CHECK9-NEXT:    [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
9322 // CHECK9-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
9323 // CHECK9:       omp.inner.for.body:
9324 // CHECK9-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
9325 // CHECK9-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
9326 // CHECK9-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
9327 // CHECK9-NEXT:    store i32 [[ADD]], i32* [[I]], align 4
9328 // CHECK9-NEXT:    [[TMP9:%.*]] = load i32, i32* [[CONV]], align 8
9329 // CHECK9-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1
9330 // CHECK9-NEXT:    store i32 [[ADD3]], i32* [[CONV]], align 8
9331 // CHECK9-NEXT:    [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 8
9332 // CHECK9-NEXT:    [[CONV4:%.*]] = sext i16 [[TMP10]] to i32
9333 // CHECK9-NEXT:    [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
9334 // CHECK9-NEXT:    [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
9335 // CHECK9-NEXT:    store i16 [[CONV6]], i16* [[CONV1]], align 8
9336 // CHECK9-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
9337 // CHECK9-NEXT:    [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
9338 // CHECK9-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1
9339 // CHECK9-NEXT:    store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4
9340 // CHECK9-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
9341 // CHECK9:       omp.body.continue:
9342 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
9343 // CHECK9:       omp.inner.for.inc:
9344 // CHECK9-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
9345 // CHECK9-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP12]], 1
9346 // CHECK9-NEXT:    store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4
9347 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND]]
9348 // CHECK9:       omp.inner.for.end:
9349 // CHECK9-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
9350 // CHECK9:       omp.loop.exit:
9351 // CHECK9-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
9352 // CHECK9-NEXT:    ret void
9353 //
9354 //
9355 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103
9356 // CHECK10-SAME: (i64 [[AA:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] {
9357 // CHECK10-NEXT:  entry:
9358 // CHECK10-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
9359 // CHECK10-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
9360 // CHECK10-NEXT:    [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8
9361 // CHECK10-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
9362 // CHECK10-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]])
9363 // CHECK10-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
9364 // CHECK10-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
9365 // CHECK10-NEXT:    store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8
9366 // CHECK10-NEXT:    [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
9367 // CHECK10-NEXT:    [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
9368 // CHECK10-NEXT:    [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32*
9369 // CHECK10-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 8
9370 // CHECK10-NEXT:    [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 8
9371 // CHECK10-NEXT:    call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
9372 // CHECK10-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV]], align 8
9373 // CHECK10-NEXT:    [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
9374 // CHECK10-NEXT:    store i16 [[TMP3]], i16* [[CONV5]], align 2
9375 // CHECK10-NEXT:    [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
9376 // CHECK10-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]])
9377 // CHECK10-NEXT:    ret void
9378 //
9379 //
9380 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined.
9381 // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] {
9382 // CHECK10-NEXT:  entry:
9383 // CHECK10-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
9384 // CHECK10-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
9385 // CHECK10-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
9386 // CHECK10-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
9387 // CHECK10-NEXT:    [[TMP:%.*]] = alloca i32, align 4
9388 // CHECK10-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
9389 // CHECK10-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
9390 // CHECK10-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
9391 // CHECK10-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
9392 // CHECK10-NEXT:    [[I:%.*]] = alloca i32, align 4
9393 // CHECK10-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
9394 // CHECK10-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
9395 // CHECK10-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
9396 // CHECK10-NEXT:    [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
9397 // CHECK10-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
9398 // CHECK10-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
9399 // CHECK10-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
9400 // CHECK10-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
9401 // CHECK10-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
9402 // CHECK10-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
9403 // CHECK10-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
9404 // CHECK10-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
9405 // CHECK10-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
9406 // CHECK10-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
9407 // CHECK10:       cond.true:
9408 // CHECK10-NEXT:    br label [[COND_END:%.*]]
9409 // CHECK10:       cond.false:
9410 // CHECK10-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
9411 // CHECK10-NEXT:    br label [[COND_END]]
9412 // CHECK10:       cond.end:
9413 // CHECK10-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
9414 // CHECK10-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
9415 // CHECK10-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
9416 // CHECK10-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
9417 // CHECK10-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
9418 // CHECK10:       omp.inner.for.cond:
9419 // CHECK10-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
9420 // CHECK10-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
9421 // CHECK10-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
9422 // CHECK10-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
9423 // CHECK10:       omp.inner.for.body:
9424 // CHECK10-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
9425 // CHECK10-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
9426 // CHECK10-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
9427 // CHECK10-NEXT:    store i32 [[ADD]], i32* [[I]], align 4
9428 // CHECK10-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
9429 // CHECK10:       omp.body.continue:
9430 // CHECK10-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
9431 // CHECK10:       omp.inner.for.inc:
9432 // CHECK10-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
9433 // CHECK10-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
9434 // CHECK10-NEXT:    store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4
9435 // CHECK10-NEXT:    br label [[OMP_INNER_FOR_COND]]
9436 // CHECK10:       omp.inner.for.end:
9437 // CHECK10-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
9438 // CHECK10:       omp.loop.exit:
9439 // CHECK10-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
9440 // CHECK10-NEXT:    ret void
9441 //
9442 //
9443 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113
9444 // CHECK10-SAME: (i64 [[AA:%.*]]) #[[ATTR0]] {
9445 // CHECK10-NEXT:  entry:
9446 // CHECK10-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
9447 // CHECK10-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
9448 // CHECK10-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
9449 // CHECK10-NEXT:    [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
9450 // CHECK10-NEXT:    [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8
9451 // CHECK10-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
9452 // CHECK10-NEXT:    store i16 [[TMP0]], i16* [[CONV1]], align 2
9453 // CHECK10-NEXT:    [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
9454 // CHECK10-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]])
9455 // CHECK10-NEXT:    ret void
9456 //
9457 //
9458 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1
9459 // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] {
9460 // CHECK10-NEXT:  entry:
9461 // CHECK10-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
9462 // CHECK10-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
9463 // CHECK10-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
9464 // CHECK10-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
9465 // CHECK10-NEXT:    [[TMP:%.*]] = alloca i32, align 4
9466 // CHECK10-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
9467 // CHECK10-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
9468 // CHECK10-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
9469 // CHECK10-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
9470 // CHECK10-NEXT:    [[I:%.*]] = alloca i32, align 4
9471 // CHECK10-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
9472 // CHECK10-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
9473 // CHECK10-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
9474 // CHECK10-NEXT:    [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
9475 // CHECK10-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
9476 // CHECK10-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
9477 // CHECK10-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
9478 // CHECK10-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
9479 // CHECK10-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
9480 // CHECK10-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
9481 // CHECK10-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
9482 // CHECK10-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
9483 // CHECK10-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
9484 // CHECK10-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
9485 // CHECK10:       cond.true:
9486 // CHECK10-NEXT:    br label [[COND_END:%.*]]
9487 // CHECK10:       cond.false:
9488 // CHECK10-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
9489 // CHECK10-NEXT:    br label [[COND_END]]
9490 // CHECK10:       cond.end:
9491 // CHECK10-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
9492 // CHECK10-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
9493 // CHECK10-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
9494 // CHECK10-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
9495 // CHECK10-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
9496 // CHECK10:       omp.inner.for.cond:
9497 // CHECK10-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
9498 // CHECK10-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
9499 // CHECK10-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
9500 // CHECK10-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
9501 // CHECK10:       omp.inner.for.body:
9502 // CHECK10-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
9503 // CHECK10-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
9504 // CHECK10-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
9505 // CHECK10-NEXT:    store i32 [[ADD]], i32* [[I]], align 4
9506 // CHECK10-NEXT:    [[TMP8:%.*]] = load i16, i16* [[CONV]], align 8
9507 // CHECK10-NEXT:    [[CONV2:%.*]] = sext i16 [[TMP8]] to i32
9508 // CHECK10-NEXT:    [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
9509 // CHECK10-NEXT:    [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
9510 // CHECK10-NEXT:    store i16 [[CONV4]], i16* [[CONV]], align 8
9511 // CHECK10-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
9512 // CHECK10:       omp.body.continue:
9513 // CHECK10-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
9514 // CHECK10:       omp.inner.for.inc:
9515 // CHECK10-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
9516 // CHECK10-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP9]], 1
9517 // CHECK10-NEXT:    store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4
9518 // CHECK10-NEXT:    br label [[OMP_INNER_FOR_COND]]
9519 // CHECK10:       omp.inner.for.end:
9520 // CHECK10-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
9521 // CHECK10:       omp.loop.exit:
9522 // CHECK10-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
9523 // CHECK10-NEXT:    ret void
9524 //
9525 //
9526 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120
9527 // CHECK10-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] {
9528 // CHECK10-NEXT:  entry:
9529 // CHECK10-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
9530 // CHECK10-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
9531 // CHECK10-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
9532 // CHECK10-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
9533 // CHECK10-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
9534 // CHECK10-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
9535 // CHECK10-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
9536 // CHECK10-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
9537 // CHECK10-NEXT:    [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
9538 // CHECK10-NEXT:    [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
9539 // CHECK10-NEXT:    store i32 [[TMP0]], i32* [[CONV2]], align 4
9540 // CHECK10-NEXT:    [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
9541 // CHECK10-NEXT:    [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
9542 // CHECK10-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
9543 // CHECK10-NEXT:    store i16 [[TMP2]], i16* [[CONV3]], align 2
9544 // CHECK10-NEXT:    [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
9545 // CHECK10-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
9546 // CHECK10-NEXT:    ret void
9547 //
9548 //
9549 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..2
9550 // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] {
9551 // CHECK10-NEXT:  entry:
9552 // CHECK10-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
9553 // CHECK10-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
9554 // CHECK10-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
9555 // CHECK10-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
9556 // CHECK10-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
9557 // CHECK10-NEXT:    [[TMP:%.*]] = alloca i32, align 4
9558 // CHECK10-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
9559 // CHECK10-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
9560 // CHECK10-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
9561 // CHECK10-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
9562 // CHECK10-NEXT:    [[I:%.*]] = alloca i32, align 4
9563 // CHECK10-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
9564 // CHECK10-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
9565 // CHECK10-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
9566 // CHECK10-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
9567 // CHECK10-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
9568 // CHECK10-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
9569 // CHECK10-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
9570 // CHECK10-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
9571 // CHECK10-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
9572 // CHECK10-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
9573 // CHECK10-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
9574 // CHECK10-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
9575 // CHECK10-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
9576 // CHECK10-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
9577 // CHECK10-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
9578 // CHECK10-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
9579 // CHECK10:       cond.true:
9580 // CHECK10-NEXT:    br label [[COND_END:%.*]]
9581 // CHECK10:       cond.false:
9582 // CHECK10-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
9583 // CHECK10-NEXT:    br label [[COND_END]]
9584 // CHECK10:       cond.end:
9585 // CHECK10-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
9586 // CHECK10-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
9587 // CHECK10-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
9588 // CHECK10-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
9589 // CHECK10-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
9590 // CHECK10:       omp.inner.for.cond:
9591 // CHECK10-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
9592 // CHECK10-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
9593 // CHECK10-NEXT:    [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
9594 // CHECK10-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
9595 // CHECK10:       omp.inner.for.body:
9596 // CHECK10-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
9597 // CHECK10-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
9598 // CHECK10-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
9599 // CHECK10-NEXT:    store i32 [[ADD]], i32* [[I]], align 4
9600 // CHECK10-NEXT:    [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
9601 // CHECK10-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
9602 // CHECK10-NEXT:    store i32 [[ADD3]], i32* [[CONV]], align 8
9603 // CHECK10-NEXT:    [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 8
9604 // CHECK10-NEXT:    [[CONV4:%.*]] = sext i16 [[TMP9]] to i32
9605 // CHECK10-NEXT:    [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
9606 // CHECK10-NEXT:    [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
9607 // CHECK10-NEXT:    store i16 [[CONV6]], i16* [[CONV1]], align 8
9608 // CHECK10-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
9609 // CHECK10:       omp.body.continue:
9610 // CHECK10-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
9611 // CHECK10:       omp.inner.for.inc:
9612 // CHECK10-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
9613 // CHECK10-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1
9614 // CHECK10-NEXT:    store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4
9615 // CHECK10-NEXT:    br label [[OMP_INNER_FOR_COND]]
9616 // CHECK10:       omp.inner.for.end:
9617 // CHECK10-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
9618 // CHECK10:       omp.loop.exit:
9619 // CHECK10-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
9620 // CHECK10-NEXT:    ret void
9621 //
9622 //
9623 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145
9624 // CHECK10-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
9625 // CHECK10-NEXT:  entry:
9626 // CHECK10-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
9627 // CHECK10-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
9628 // CHECK10-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
9629 // CHECK10-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 8
9630 // CHECK10-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
9631 // CHECK10-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
9632 // CHECK10-NEXT:    [[VLA_ADDR4:%.*]] = alloca i64, align 8
9633 // CHECK10-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 8
9634 // CHECK10-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
9635 // CHECK10-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
9636 // CHECK10-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
9637 // CHECK10-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
9638 // CHECK10-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
9639 // CHECK10-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
9640 // CHECK10-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
9641 // CHECK10-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 8
9642 // CHECK10-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
9643 // CHECK10-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
9644 // CHECK10-NEXT:    store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
9645 // CHECK10-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 8
9646 // CHECK10-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
9647 // CHECK10-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
9648 // CHECK10-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
9649 // CHECK10-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
9650 // CHECK10-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
9651 // CHECK10-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
9652 // CHECK10-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
9653 // CHECK10-NEXT:    [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
9654 // CHECK10-NEXT:    [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
9655 // CHECK10-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
9656 // CHECK10-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
9657 // CHECK10-NEXT:    [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
9658 // CHECK10-NEXT:    [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
9659 // CHECK10-NEXT:    [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32*
9660 // CHECK10-NEXT:    store i32 [[TMP8]], i32* [[CONV6]], align 4
9661 // CHECK10-NEXT:    [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
9662 // CHECK10-NEXT:    [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 8
9663 // CHECK10-NEXT:    [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
9664 // CHECK10-NEXT:    store i32 [[TMP10]], i32* [[CONV7]], align 4
9665 // CHECK10-NEXT:    [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
9666 // CHECK10-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]])
9667 // CHECK10-NEXT:    ret void
9668 //
9669 //
9670 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..3
9671 // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
9672 // CHECK10-NEXT:  entry:
9673 // CHECK10-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
9674 // CHECK10-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
9675 // CHECK10-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
9676 // CHECK10-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
9677 // CHECK10-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
9678 // CHECK10-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 8
9679 // CHECK10-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
9680 // CHECK10-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
9681 // CHECK10-NEXT:    [[VLA_ADDR4:%.*]] = alloca i64, align 8
9682 // CHECK10-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 8
9683 // CHECK10-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
9684 // CHECK10-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
9685 // CHECK10-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
9686 // CHECK10-NEXT:    [[TMP:%.*]] = alloca i32, align 4
9687 // CHECK10-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
9688 // CHECK10-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
9689 // CHECK10-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
9690 // CHECK10-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
9691 // CHECK10-NEXT:    [[I:%.*]] = alloca i32, align 4
9692 // CHECK10-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
9693 // CHECK10-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
9694 // CHECK10-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
9695 // CHECK10-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
9696 // CHECK10-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
9697 // CHECK10-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 8
9698 // CHECK10-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
9699 // CHECK10-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
9700 // CHECK10-NEXT:    store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
9701 // CHECK10-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 8
9702 // CHECK10-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
9703 // CHECK10-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
9704 // CHECK10-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
9705 // CHECK10-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
9706 // CHECK10-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
9707 // CHECK10-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
9708 // CHECK10-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
9709 // CHECK10-NEXT:    [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
9710 // CHECK10-NEXT:    [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
9711 // CHECK10-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
9712 // CHECK10-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
9713 // CHECK10-NEXT:    [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
9714 // CHECK10-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
9715 // CHECK10-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
9716 // CHECK10-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
9717 // CHECK10-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
9718 // CHECK10-NEXT:    [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 8
9719 // CHECK10-NEXT:    [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
9720 // CHECK10-NEXT:    [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
9721 // CHECK10-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
9722 // CHECK10-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
9723 // CHECK10:       omp.dispatch.cond:
9724 // CHECK10-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
9725 // CHECK10-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 9
9726 // CHECK10-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
9727 // CHECK10:       cond.true:
9728 // CHECK10-NEXT:    br label [[COND_END:%.*]]
9729 // CHECK10:       cond.false:
9730 // CHECK10-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
9731 // CHECK10-NEXT:    br label [[COND_END]]
9732 // CHECK10:       cond.end:
9733 // CHECK10-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
9734 // CHECK10-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
9735 // CHECK10-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
9736 // CHECK10-NEXT:    store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
9737 // CHECK10-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
9738 // CHECK10-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
9739 // CHECK10-NEXT:    [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
9740 // CHECK10-NEXT:    br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
9741 // CHECK10:       omp.dispatch.body:
9742 // CHECK10-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
9743 // CHECK10:       omp.inner.for.cond:
9744 // CHECK10-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
9745 // CHECK10-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !11
9746 // CHECK10-NEXT:    [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
9747 // CHECK10-NEXT:    br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
9748 // CHECK10:       omp.inner.for.body:
9749 // CHECK10-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
9750 // CHECK10-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
9751 // CHECK10-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
9752 // CHECK10-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11
9753 // CHECK10-NEXT:    [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !11
9754 // CHECK10-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP19]], 1
9755 // CHECK10-NEXT:    store i32 [[ADD8]], i32* [[CONV]], align 8, !llvm.access.group !11
9756 // CHECK10-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
9757 // CHECK10-NEXT:    [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !11
9758 // CHECK10-NEXT:    [[CONV9:%.*]] = fpext float [[TMP20]] to double
9759 // CHECK10-NEXT:    [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00
9760 // CHECK10-NEXT:    [[CONV11:%.*]] = fptrunc double [[ADD10]] to float
9761 // CHECK10-NEXT:    store float [[CONV11]], float* [[ARRAYIDX]], align 4, !llvm.access.group !11
9762 // CHECK10-NEXT:    [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3
9763 // CHECK10-NEXT:    [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4, !llvm.access.group !11
9764 // CHECK10-NEXT:    [[CONV13:%.*]] = fpext float [[TMP21]] to double
9765 // CHECK10-NEXT:    [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00
9766 // CHECK10-NEXT:    [[CONV15:%.*]] = fptrunc double [[ADD14]] to float
9767 // CHECK10-NEXT:    store float [[CONV15]], float* [[ARRAYIDX12]], align 4, !llvm.access.group !11
9768 // CHECK10-NEXT:    [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1
9769 // CHECK10-NEXT:    [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i64 0, i64 2
9770 // CHECK10-NEXT:    [[TMP22:%.*]] = load double, double* [[ARRAYIDX17]], align 8, !llvm.access.group !11
9771 // CHECK10-NEXT:    [[ADD18:%.*]] = fadd double [[TMP22]], 1.000000e+00
9772 // CHECK10-NEXT:    store double [[ADD18]], double* [[ARRAYIDX17]], align 8, !llvm.access.group !11
9773 // CHECK10-NEXT:    [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]]
9774 // CHECK10-NEXT:    [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP23]]
9775 // CHECK10-NEXT:    [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i64 3
9776 // CHECK10-NEXT:    [[TMP24:%.*]] = load double, double* [[ARRAYIDX20]], align 8, !llvm.access.group !11
9777 // CHECK10-NEXT:    [[ADD21:%.*]] = fadd double [[TMP24]], 1.000000e+00
9778 // CHECK10-NEXT:    store double [[ADD21]], double* [[ARRAYIDX20]], align 8, !llvm.access.group !11
9779 // CHECK10-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0
9780 // CHECK10-NEXT:    [[TMP25:%.*]] = load i64, i64* [[X]], align 8, !llvm.access.group !11
9781 // CHECK10-NEXT:    [[ADD22:%.*]] = add nsw i64 [[TMP25]], 1
9782 // CHECK10-NEXT:    store i64 [[ADD22]], i64* [[X]], align 8, !llvm.access.group !11
9783 // CHECK10-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1
9784 // CHECK10-NEXT:    [[TMP26:%.*]] = load i8, i8* [[Y]], align 8, !llvm.access.group !11
9785 // CHECK10-NEXT:    [[CONV23:%.*]] = sext i8 [[TMP26]] to i32
9786 // CHECK10-NEXT:    [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1
9787 // CHECK10-NEXT:    [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8
9788 // CHECK10-NEXT:    store i8 [[CONV25]], i8* [[Y]], align 8, !llvm.access.group !11
9789 // CHECK10-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
9790 // CHECK10:       omp.body.continue:
9791 // CHECK10-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
9792 // CHECK10:       omp.inner.for.inc:
9793 // CHECK10-NEXT:    [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
9794 // CHECK10-NEXT:    [[ADD26:%.*]] = add nsw i32 [[TMP27]], 1
9795 // CHECK10-NEXT:    store i32 [[ADD26]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
9796 // CHECK10-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]
9797 // CHECK10:       omp.inner.for.end:
9798 // CHECK10-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
9799 // CHECK10:       omp.dispatch.inc:
9800 // CHECK10-NEXT:    [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
9801 // CHECK10-NEXT:    [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
9802 // CHECK10-NEXT:    [[ADD27:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]
9803 // CHECK10-NEXT:    store i32 [[ADD27]], i32* [[DOTOMP_LB]], align 4
9804 // CHECK10-NEXT:    [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
9805 // CHECK10-NEXT:    [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
9806 // CHECK10-NEXT:    [[ADD28:%.*]] = add nsw i32 [[TMP30]], [[TMP31]]
9807 // CHECK10-NEXT:    store i32 [[ADD28]], i32* [[DOTOMP_UB]], align 4
9808 // CHECK10-NEXT:    br label [[OMP_DISPATCH_COND]]
9809 // CHECK10:       omp.dispatch.end:
9810 // CHECK10-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]])
9811 // CHECK10-NEXT:    ret void
9812 //
9813 //
9814 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200
9815 // CHECK10-SAME: (i64 [[N:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
9816 // CHECK10-NEXT:  entry:
9817 // CHECK10-NEXT:    [[N_ADDR:%.*]] = alloca i64, align 8
9818 // CHECK10-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
9819 // CHECK10-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
9820 // CHECK10-NEXT:    [[AAA_ADDR:%.*]] = alloca i64, align 8
9821 // CHECK10-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
9822 // CHECK10-NEXT:    [[N_CASTED:%.*]] = alloca i64, align 8
9823 // CHECK10-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
9824 // CHECK10-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
9825 // CHECK10-NEXT:    [[AAA_CASTED:%.*]] = alloca i64, align 8
9826 // CHECK10-NEXT:    store i64 [[N]], i64* [[N_ADDR]], align 8
9827 // CHECK10-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
9828 // CHECK10-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
9829 // CHECK10-NEXT:    store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
9830 // CHECK10-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
9831 // CHECK10-NEXT:    [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
9832 // CHECK10-NEXT:    [[CONV1:%.*]] = bitcast i64* [[A_ADDR]] to i32*
9833 // CHECK10-NEXT:    [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
9834 // CHECK10-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
9835 // CHECK10-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
9836 // CHECK10-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
9837 // CHECK10-NEXT:    [[CONV4:%.*]] = bitcast i64* [[N_CASTED]] to i32*
9838 // CHECK10-NEXT:    store i32 [[TMP1]], i32* [[CONV4]], align 4
9839 // CHECK10-NEXT:    [[TMP2:%.*]] = load i64, i64* [[N_CASTED]], align 8
9840 // CHECK10-NEXT:    [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 8
9841 // CHECK10-NEXT:    [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
9842 // CHECK10-NEXT:    store i32 [[TMP3]], i32* [[CONV5]], align 4
9843 // CHECK10-NEXT:    [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8
9844 // CHECK10-NEXT:    [[TMP5:%.*]] = load i16, i16* [[CONV2]], align 8
9845 // CHECK10-NEXT:    [[CONV6:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
9846 // CHECK10-NEXT:    store i16 [[TMP5]], i16* [[CONV6]], align 2
9847 // CHECK10-NEXT:    [[TMP6:%.*]] = load i64, i64* [[AA_CASTED]], align 8
9848 // CHECK10-NEXT:    [[TMP7:%.*]] = load i8, i8* [[CONV3]], align 8
9849 // CHECK10-NEXT:    [[CONV7:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
9850 // CHECK10-NEXT:    store i8 [[TMP7]], i8* [[CONV7]], align 1
9851 // CHECK10-NEXT:    [[TMP8:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
9852 // CHECK10-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]], [10 x i32]* [[TMP0]])
9853 // CHECK10-NEXT:    ret void
9854 //
9855 //
9856 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..4
9857 // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
9858 // CHECK10-NEXT:  entry:
9859 // CHECK10-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
9860 // CHECK10-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
9861 // CHECK10-NEXT:    [[N_ADDR:%.*]] = alloca i64, align 8
9862 // CHECK10-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
9863 // CHECK10-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
9864 // CHECK10-NEXT:    [[AAA_ADDR:%.*]] = alloca i64, align 8
9865 // CHECK10-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
9866 // CHECK10-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
9867 // CHECK10-NEXT:    [[TMP:%.*]] = alloca i32, align 4
9868 // CHECK10-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
9869 // CHECK10-NEXT:    [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4
9870 // CHECK10-NEXT:    [[DOTCAPTURE_EXPR_5:%.*]] = alloca i32, align 4
9871 // CHECK10-NEXT:    [[I:%.*]] = alloca i32, align 4
9872 // CHECK10-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
9873 // CHECK10-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
9874 // CHECK10-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
9875 // CHECK10-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
9876 // CHECK10-NEXT:    [[I8:%.*]] = alloca i32, align 4
9877 // CHECK10-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
9878 // CHECK10-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
9879 // CHECK10-NEXT:    store i64 [[N]], i64* [[N_ADDR]], align 8
9880 // CHECK10-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
9881 // CHECK10-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
9882 // CHECK10-NEXT:    store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
9883 // CHECK10-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
9884 // CHECK10-NEXT:    [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
9885 // CHECK10-NEXT:    [[CONV1:%.*]] = bitcast i64* [[A_ADDR]] to i32*
9886 // CHECK10-NEXT:    [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
9887 // CHECK10-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
9888 // CHECK10-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
9889 // CHECK10-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV1]], align 8
9890 // CHECK10-NEXT:    store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
9891 // CHECK10-NEXT:    [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
9892 // CHECK10-NEXT:    store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_4]], align 4
9893 // CHECK10-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4
9894 // CHECK10-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
9895 // CHECK10-NEXT:    [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]]
9896 // CHECK10-NEXT:    [[SUB6:%.*]] = sub i32 [[SUB]], 1
9897 // CHECK10-NEXT:    [[ADD:%.*]] = add i32 [[SUB6]], 1
9898 // CHECK10-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], 1
9899 // CHECK10-NEXT:    [[SUB7:%.*]] = sub i32 [[DIV]], 1
9900 // CHECK10-NEXT:    store i32 [[SUB7]], i32* [[DOTCAPTURE_EXPR_5]], align 4
9901 // CHECK10-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
9902 // CHECK10-NEXT:    store i32 [[TMP5]], i32* [[I]], align 4
9903 // CHECK10-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
9904 // CHECK10-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4
9905 // CHECK10-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]]
9906 // CHECK10-NEXT:    br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
9907 // CHECK10:       omp.precond.then:
9908 // CHECK10-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
9909 // CHECK10-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4
9910 // CHECK10-NEXT:    store i32 [[TMP8]], i32* [[DOTOMP_UB]], align 4
9911 // CHECK10-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
9912 // CHECK10-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
9913 // CHECK10-NEXT:    [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
9914 // CHECK10-NEXT:    [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
9915 // CHECK10-NEXT:    call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
9916 // CHECK10-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
9917 // CHECK10-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4
9918 // CHECK10-NEXT:    [[CMP9:%.*]] = icmp ugt i32 [[TMP11]], [[TMP12]]
9919 // CHECK10-NEXT:    br i1 [[CMP9]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
9920 // CHECK10:       cond.true:
9921 // CHECK10-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4
9922 // CHECK10-NEXT:    br label [[COND_END:%.*]]
9923 // CHECK10:       cond.false:
9924 // CHECK10-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
9925 // CHECK10-NEXT:    br label [[COND_END]]
9926 // CHECK10:       cond.end:
9927 // CHECK10-NEXT:    [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ]
9928 // CHECK10-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
9929 // CHECK10-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
9930 // CHECK10-NEXT:    store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4
9931 // CHECK10-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
9932 // CHECK10:       omp.inner.for.cond:
9933 // CHECK10-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
9934 // CHECK10-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
9935 // CHECK10-NEXT:    [[ADD10:%.*]] = add i32 [[TMP17]], 1
9936 // CHECK10-NEXT:    [[CMP11:%.*]] = icmp ult i32 [[TMP16]], [[ADD10]]
9937 // CHECK10-NEXT:    br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
9938 // CHECK10:       omp.inner.for.body:
9939 // CHECK10-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
9940 // CHECK10-NEXT:    [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
9941 // CHECK10-NEXT:    [[MUL:%.*]] = mul i32 [[TMP19]], 1
9942 // CHECK10-NEXT:    [[ADD12:%.*]] = add i32 [[TMP18]], [[MUL]]
9943 // CHECK10-NEXT:    store i32 [[ADD12]], i32* [[I8]], align 4
9944 // CHECK10-NEXT:    [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 8
9945 // CHECK10-NEXT:    [[ADD13:%.*]] = add nsw i32 [[TMP20]], 1
9946 // CHECK10-NEXT:    store i32 [[ADD13]], i32* [[CONV1]], align 8
9947 // CHECK10-NEXT:    [[TMP21:%.*]] = load i16, i16* [[CONV2]], align 8
9948 // CHECK10-NEXT:    [[CONV14:%.*]] = sext i16 [[TMP21]] to i32
9949 // CHECK10-NEXT:    [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1
9950 // CHECK10-NEXT:    [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16
9951 // CHECK10-NEXT:    store i16 [[CONV16]], i16* [[CONV2]], align 8
9952 // CHECK10-NEXT:    [[TMP22:%.*]] = load i8, i8* [[CONV3]], align 8
9953 // CHECK10-NEXT:    [[CONV17:%.*]] = sext i8 [[TMP22]] to i32
9954 // CHECK10-NEXT:    [[ADD18:%.*]] = add nsw i32 [[CONV17]], 1
9955 // CHECK10-NEXT:    [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8
9956 // CHECK10-NEXT:    store i8 [[CONV19]], i8* [[CONV3]], align 8
9957 // CHECK10-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
9958 // CHECK10-NEXT:    [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
9959 // CHECK10-NEXT:    [[ADD20:%.*]] = add nsw i32 [[TMP23]], 1
9960 // CHECK10-NEXT:    store i32 [[ADD20]], i32* [[ARRAYIDX]], align 4
9961 // CHECK10-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
9962 // CHECK10:       omp.body.continue:
9963 // CHECK10-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
9964 // CHECK10:       omp.inner.for.inc:
9965 // CHECK10-NEXT:    [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
9966 // CHECK10-NEXT:    [[ADD21:%.*]] = add i32 [[TMP24]], 1
9967 // CHECK10-NEXT:    store i32 [[ADD21]], i32* [[DOTOMP_IV]], align 4
9968 // CHECK10-NEXT:    br label [[OMP_INNER_FOR_COND]]
9969 // CHECK10:       omp.inner.for.end:
9970 // CHECK10-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
9971 // CHECK10:       omp.loop.exit:
9972 // CHECK10-NEXT:    [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
9973 // CHECK10-NEXT:    [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4
9974 // CHECK10-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]])
9975 // CHECK10-NEXT:    br label [[OMP_PRECOND_END]]
9976 // CHECK10:       omp.precond.end:
9977 // CHECK10-NEXT:    ret void
9978 //
9979 //
9980 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218
9981 // CHECK10-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {
9982 // CHECK10-NEXT:  entry:
9983 // CHECK10-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
9984 // CHECK10-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
9985 // CHECK10-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
9986 // CHECK10-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
9987 // CHECK10-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 8
9988 // CHECK10-NEXT:    [[B_CASTED:%.*]] = alloca i64, align 8
9989 // CHECK10-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
9990 // CHECK10-NEXT:    store i64 [[B]], i64* [[B_ADDR]], align 8
9991 // CHECK10-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
9992 // CHECK10-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
9993 // CHECK10-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 8
9994 // CHECK10-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
9995 // CHECK10-NEXT:    [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
9996 // CHECK10-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
9997 // CHECK10-NEXT:    [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
9998 // CHECK10-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
9999 // CHECK10-NEXT:    [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
10000 // CHECK10-NEXT:    [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32*
10001 // CHECK10-NEXT:    store i32 [[TMP4]], i32* [[CONV3]], align 4
10002 // CHECK10-NEXT:    [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
10003 // CHECK10-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]])
10004 // CHECK10-NEXT:    ret void
10005 //
10006 //
10007 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..5
10008 // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {
10009 // CHECK10-NEXT:  entry:
10010 // CHECK10-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
10011 // CHECK10-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
10012 // CHECK10-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
10013 // CHECK10-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
10014 // CHECK10-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
10015 // CHECK10-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
10016 // CHECK10-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 8
10017 // CHECK10-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
10018 // CHECK10-NEXT:    [[TMP:%.*]] = alloca i32, align 4
10019 // CHECK10-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
10020 // CHECK10-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
10021 // CHECK10-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
10022 // CHECK10-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
10023 // CHECK10-NEXT:    [[I:%.*]] = alloca i32, align 4
10024 // CHECK10-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
10025 // CHECK10-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
10026 // CHECK10-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
10027 // CHECK10-NEXT:    store i64 [[B]], i64* [[B_ADDR]], align 8
10028 // CHECK10-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
10029 // CHECK10-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
10030 // CHECK10-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 8
10031 // CHECK10-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
10032 // CHECK10-NEXT:    [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
10033 // CHECK10-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
10034 // CHECK10-NEXT:    [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
10035 // CHECK10-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
10036 // CHECK10-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
10037 // CHECK10-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
10038 // CHECK10-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
10039 // CHECK10-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
10040 // CHECK10-NEXT:    [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
10041 // CHECK10-NEXT:    [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
10042 // CHECK10-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
10043 // CHECK10-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
10044 // CHECK10-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 9
10045 // CHECK10-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
10046 // CHECK10:       cond.true:
10047 // CHECK10-NEXT:    br label [[COND_END:%.*]]
10048 // CHECK10:       cond.false:
10049 // CHECK10-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
10050 // CHECK10-NEXT:    br label [[COND_END]]
10051 // CHECK10:       cond.end:
10052 // CHECK10-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
10053 // CHECK10-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
10054 // CHECK10-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
10055 // CHECK10-NEXT:    store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
10056 // CHECK10-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
10057 // CHECK10:       omp.inner.for.cond:
10058 // CHECK10-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
10059 // CHECK10-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
10060 // CHECK10-NEXT:    [[CMP3:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
10061 // CHECK10-NEXT:    br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
10062 // CHECK10:       omp.inner.for.body:
10063 // CHECK10-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
10064 // CHECK10-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
10065 // CHECK10-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
10066 // CHECK10-NEXT:    store i32 [[ADD]], i32* [[I]], align 4
10067 // CHECK10-NEXT:    [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8
10068 // CHECK10-NEXT:    [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double
10069 // CHECK10-NEXT:    [[ADD5:%.*]] = fadd double [[CONV4]], 1.500000e+00
10070 // CHECK10-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
10071 // CHECK10-NEXT:    store double [[ADD5]], double* [[A]], align 8
10072 // CHECK10-NEXT:    [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
10073 // CHECK10-NEXT:    [[TMP13:%.*]] = load double, double* [[A6]], align 8
10074 // CHECK10-NEXT:    [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00
10075 // CHECK10-NEXT:    store double [[INC]], double* [[A6]], align 8
10076 // CHECK10-NEXT:    [[CONV7:%.*]] = fptosi double [[INC]] to i16
10077 // CHECK10-NEXT:    [[TMP14:%.*]] = mul nsw i64 1, [[TMP2]]
10078 // CHECK10-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP14]]
10079 // CHECK10-NEXT:    [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
10080 // CHECK10-NEXT:    store i16 [[CONV7]], i16* [[ARRAYIDX8]], align 2
10081 // CHECK10-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
10082 // CHECK10:       omp.body.continue:
10083 // CHECK10-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
10084 // CHECK10:       omp.inner.for.inc:
10085 // CHECK10-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
10086 // CHECK10-NEXT:    [[ADD9:%.*]] = add nsw i32 [[TMP15]], 1
10087 // CHECK10-NEXT:    store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4
10088 // CHECK10-NEXT:    br label [[OMP_INNER_FOR_COND]]
10089 // CHECK10:       omp.inner.for.end:
10090 // CHECK10-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
10091 // CHECK10:       omp.loop.exit:
10092 // CHECK10-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
10093 // CHECK10-NEXT:    ret void
10094 //
10095 //
10096 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183
10097 // CHECK10-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
10098 // CHECK10-NEXT:  entry:
10099 // CHECK10-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
10100 // CHECK10-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
10101 // CHECK10-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
10102 // CHECK10-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
10103 // CHECK10-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
10104 // CHECK10-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
10105 // CHECK10-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
10106 // CHECK10-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
10107 // CHECK10-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
10108 // CHECK10-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
10109 // CHECK10-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
10110 // CHECK10-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
10111 // CHECK10-NEXT:    [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
10112 // CHECK10-NEXT:    store i32 [[TMP1]], i32* [[CONV2]], align 4
10113 // CHECK10-NEXT:    [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
10114 // CHECK10-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
10115 // CHECK10-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
10116 // CHECK10-NEXT:    store i16 [[TMP3]], i16* [[CONV3]], align 2
10117 // CHECK10-NEXT:    [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
10118 // CHECK10-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]])
10119 // CHECK10-NEXT:    ret void
10120 //
10121 //
10122 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..6
10123 // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
10124 // CHECK10-NEXT:  entry:
10125 // CHECK10-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
10126 // CHECK10-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
10127 // CHECK10-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
10128 // CHECK10-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
10129 // CHECK10-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
10130 // CHECK10-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
10131 // CHECK10-NEXT:    [[TMP:%.*]] = alloca i32, align 4
10132 // CHECK10-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
10133 // CHECK10-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
10134 // CHECK10-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
10135 // CHECK10-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
10136 // CHECK10-NEXT:    [[I:%.*]] = alloca i32, align 4
10137 // CHECK10-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
10138 // CHECK10-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
10139 // CHECK10-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
10140 // CHECK10-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
10141 // CHECK10-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
10142 // CHECK10-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
10143 // CHECK10-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
10144 // CHECK10-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
10145 // CHECK10-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
10146 // CHECK10-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
10147 // CHECK10-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
10148 // CHECK10-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
10149 // CHECK10-NEXT:    [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
10150 // CHECK10-NEXT:    [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
10151 // CHECK10-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
10152 // CHECK10-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
10153 // CHECK10-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9
10154 // CHECK10-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
10155 // CHECK10:       cond.true:
10156 // CHECK10-NEXT:    br label [[COND_END:%.*]]
10157 // CHECK10:       cond.false:
10158 // CHECK10-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
10159 // CHECK10-NEXT:    br label [[COND_END]]
10160 // CHECK10:       cond.end:
10161 // CHECK10-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
10162 // CHECK10-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
10163 // CHECK10-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
10164 // CHECK10-NEXT:    store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
10165 // CHECK10-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
10166 // CHECK10:       omp.inner.for.cond:
10167 // CHECK10-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
10168 // CHECK10-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
10169 // CHECK10-NEXT:    [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
10170 // CHECK10-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
10171 // CHECK10:       omp.inner.for.body:
10172 // CHECK10-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
10173 // CHECK10-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
10174 // CHECK10-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
10175 // CHECK10-NEXT:    store i32 [[ADD]], i32* [[I]], align 4
10176 // CHECK10-NEXT:    [[TMP9:%.*]] = load i32, i32* [[CONV]], align 8
10177 // CHECK10-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1
10178 // CHECK10-NEXT:    store i32 [[ADD3]], i32* [[CONV]], align 8
10179 // CHECK10-NEXT:    [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 8
10180 // CHECK10-NEXT:    [[CONV4:%.*]] = sext i16 [[TMP10]] to i32
10181 // CHECK10-NEXT:    [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
10182 // CHECK10-NEXT:    [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
10183 // CHECK10-NEXT:    store i16 [[CONV6]], i16* [[CONV1]], align 8
10184 // CHECK10-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
10185 // CHECK10-NEXT:    [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
10186 // CHECK10-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1
10187 // CHECK10-NEXT:    store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4
10188 // CHECK10-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
10189 // CHECK10:       omp.body.continue:
10190 // CHECK10-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
10191 // CHECK10:       omp.inner.for.inc:
10192 // CHECK10-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
10193 // CHECK10-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP12]], 1
10194 // CHECK10-NEXT:    store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4
10195 // CHECK10-NEXT:    br label [[OMP_INNER_FOR_COND]]
10196 // CHECK10:       omp.inner.for.end:
10197 // CHECK10-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
10198 // CHECK10:       omp.loop.exit:
10199 // CHECK10-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
10200 // CHECK10-NEXT:    ret void
10201 //
10202 //
10203 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103
10204 // CHECK11-SAME: (i32 [[AA:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]], i32 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] {
10205 // CHECK11-NEXT:  entry:
10206 // CHECK11-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
10207 // CHECK11-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
10208 // CHECK11-NEXT:    [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4
10209 // CHECK11-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
10210 // CHECK11-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]])
10211 // CHECK11-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
10212 // CHECK11-NEXT:    store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
10213 // CHECK11-NEXT:    store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4
10214 // CHECK11-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
10215 // CHECK11-NEXT:    [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
10216 // CHECK11-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4
10217 // CHECK11-NEXT:    call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
10218 // CHECK11-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
10219 // CHECK11-NEXT:    [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
10220 // CHECK11-NEXT:    store i16 [[TMP3]], i16* [[CONV3]], align 2
10221 // CHECK11-NEXT:    [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
10222 // CHECK11-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]])
10223 // CHECK11-NEXT:    ret void
10224 //
10225 //
10226 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined.
10227 // CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] {
10228 // CHECK11-NEXT:  entry:
10229 // CHECK11-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
10230 // CHECK11-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
10231 // CHECK11-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
10232 // CHECK11-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
10233 // CHECK11-NEXT:    [[TMP:%.*]] = alloca i32, align 4
10234 // CHECK11-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
10235 // CHECK11-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
10236 // CHECK11-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
10237 // CHECK11-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
10238 // CHECK11-NEXT:    [[I:%.*]] = alloca i32, align 4
10239 // CHECK11-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
10240 // CHECK11-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
10241 // CHECK11-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
10242 // CHECK11-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
10243 // CHECK11-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
10244 // CHECK11-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
10245 // CHECK11-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
10246 // CHECK11-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
10247 // CHECK11-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
10248 // CHECK11-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
10249 // CHECK11-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
10250 // CHECK11-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
10251 // CHECK11-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
10252 // CHECK11-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
10253 // CHECK11:       cond.true:
10254 // CHECK11-NEXT:    br label [[COND_END:%.*]]
10255 // CHECK11:       cond.false:
10256 // CHECK11-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
10257 // CHECK11-NEXT:    br label [[COND_END]]
10258 // CHECK11:       cond.end:
10259 // CHECK11-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
10260 // CHECK11-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
10261 // CHECK11-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
10262 // CHECK11-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
10263 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
10264 // CHECK11:       omp.inner.for.cond:
10265 // CHECK11-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
10266 // CHECK11-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
10267 // CHECK11-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
10268 // CHECK11-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
10269 // CHECK11:       omp.inner.for.body:
10270 // CHECK11-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
10271 // CHECK11-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
10272 // CHECK11-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
10273 // CHECK11-NEXT:    store i32 [[ADD]], i32* [[I]], align 4
10274 // CHECK11-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
10275 // CHECK11:       omp.body.continue:
10276 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
10277 // CHECK11:       omp.inner.for.inc:
10278 // CHECK11-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
10279 // CHECK11-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
10280 // CHECK11-NEXT:    store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4
10281 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_COND]]
10282 // CHECK11:       omp.inner.for.end:
10283 // CHECK11-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
10284 // CHECK11:       omp.loop.exit:
10285 // CHECK11-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
10286 // CHECK11-NEXT:    ret void
10287 //
10288 //
10289 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113
10290 // CHECK11-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] {
10291 // CHECK11-NEXT:  entry:
10292 // CHECK11-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
10293 // CHECK11-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
10294 // CHECK11-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
10295 // CHECK11-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
10296 // CHECK11-NEXT:    [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
10297 // CHECK11-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
10298 // CHECK11-NEXT:    store i16 [[TMP0]], i16* [[CONV1]], align 2
10299 // CHECK11-NEXT:    [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
10300 // CHECK11-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]])
10301 // CHECK11-NEXT:    ret void
10302 //
10303 //
10304 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1
10305 // CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] {
10306 // CHECK11-NEXT:  entry:
10307 // CHECK11-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
10308 // CHECK11-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
10309 // CHECK11-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
10310 // CHECK11-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
10311 // CHECK11-NEXT:    [[TMP:%.*]] = alloca i32, align 4
10312 // CHECK11-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
10313 // CHECK11-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
10314 // CHECK11-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
10315 // CHECK11-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
10316 // CHECK11-NEXT:    [[I:%.*]] = alloca i32, align 4
10317 // CHECK11-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
10318 // CHECK11-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
10319 // CHECK11-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
10320 // CHECK11-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
10321 // CHECK11-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
10322 // CHECK11-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
10323 // CHECK11-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
10324 // CHECK11-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
10325 // CHECK11-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
10326 // CHECK11-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
10327 // CHECK11-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
10328 // CHECK11-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
10329 // CHECK11-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
10330 // CHECK11-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
10331 // CHECK11:       cond.true:
10332 // CHECK11-NEXT:    br label [[COND_END:%.*]]
10333 // CHECK11:       cond.false:
10334 // CHECK11-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
10335 // CHECK11-NEXT:    br label [[COND_END]]
10336 // CHECK11:       cond.end:
10337 // CHECK11-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
10338 // CHECK11-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
10339 // CHECK11-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
10340 // CHECK11-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
10341 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
10342 // CHECK11:       omp.inner.for.cond:
10343 // CHECK11-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
10344 // CHECK11-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
10345 // CHECK11-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
10346 // CHECK11-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
10347 // CHECK11:       omp.inner.for.body:
10348 // CHECK11-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
10349 // CHECK11-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
10350 // CHECK11-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
10351 // CHECK11-NEXT:    store i32 [[ADD]], i32* [[I]], align 4
10352 // CHECK11-NEXT:    [[TMP8:%.*]] = load i16, i16* [[CONV]], align 4
10353 // CHECK11-NEXT:    [[CONV2:%.*]] = sext i16 [[TMP8]] to i32
10354 // CHECK11-NEXT:    [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
10355 // CHECK11-NEXT:    [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
10356 // CHECK11-NEXT:    store i16 [[CONV4]], i16* [[CONV]], align 4
10357 // CHECK11-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
10358 // CHECK11:       omp.body.continue:
10359 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
10360 // CHECK11:       omp.inner.for.inc:
10361 // CHECK11-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
10362 // CHECK11-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP9]], 1
10363 // CHECK11-NEXT:    store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4
10364 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_COND]]
10365 // CHECK11:       omp.inner.for.end:
10366 // CHECK11-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
10367 // CHECK11:       omp.loop.exit:
10368 // CHECK11-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
10369 // CHECK11-NEXT:    ret void
10370 //
10371 //
10372 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120
10373 // CHECK11-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] {
10374 // CHECK11-NEXT:  entry:
10375 // CHECK11-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
10376 // CHECK11-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
10377 // CHECK11-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
10378 // CHECK11-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
10379 // CHECK11-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
10380 // CHECK11-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
10381 // CHECK11-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
10382 // CHECK11-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
10383 // CHECK11-NEXT:    store i32 [[TMP0]], i32* [[A_CASTED]], align 4
10384 // CHECK11-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
10385 // CHECK11-NEXT:    [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
10386 // CHECK11-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
10387 // CHECK11-NEXT:    store i16 [[TMP2]], i16* [[CONV1]], align 2
10388 // CHECK11-NEXT:    [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
10389 // CHECK11-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]])
10390 // CHECK11-NEXT:    ret void
10391 //
10392 //
10393 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..2
10394 // CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] {
10395 // CHECK11-NEXT:  entry:
10396 // CHECK11-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
10397 // CHECK11-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
10398 // CHECK11-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
10399 // CHECK11-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
10400 // CHECK11-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
10401 // CHECK11-NEXT:    [[TMP:%.*]] = alloca i32, align 4
10402 // CHECK11-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
10403 // CHECK11-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
10404 // CHECK11-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
10405 // CHECK11-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
10406 // CHECK11-NEXT:    [[I:%.*]] = alloca i32, align 4
10407 // CHECK11-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
10408 // CHECK11-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
10409 // CHECK11-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
10410 // CHECK11-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
10411 // CHECK11-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
10412 // CHECK11-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
10413 // CHECK11-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
10414 // CHECK11-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
10415 // CHECK11-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
10416 // CHECK11-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
10417 // CHECK11-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
10418 // CHECK11-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
10419 // CHECK11-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
10420 // CHECK11-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
10421 // CHECK11-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
10422 // CHECK11:       cond.true:
10423 // CHECK11-NEXT:    br label [[COND_END:%.*]]
10424 // CHECK11:       cond.false:
10425 // CHECK11-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
10426 // CHECK11-NEXT:    br label [[COND_END]]
10427 // CHECK11:       cond.end:
10428 // CHECK11-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
10429 // CHECK11-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
10430 // CHECK11-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
10431 // CHECK11-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
10432 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
10433 // CHECK11:       omp.inner.for.cond:
10434 // CHECK11-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
10435 // CHECK11-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
10436 // CHECK11-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
10437 // CHECK11-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
10438 // CHECK11:       omp.inner.for.body:
10439 // CHECK11-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
10440 // CHECK11-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
10441 // CHECK11-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
10442 // CHECK11-NEXT:    store i32 [[ADD]], i32* [[I]], align 4
10443 // CHECK11-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
10444 // CHECK11-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
10445 // CHECK11-NEXT:    store i32 [[ADD2]], i32* [[A_ADDR]], align 4
10446 // CHECK11-NEXT:    [[TMP9:%.*]] = load i16, i16* [[CONV]], align 4
10447 // CHECK11-NEXT:    [[CONV3:%.*]] = sext i16 [[TMP9]] to i32
10448 // CHECK11-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
10449 // CHECK11-NEXT:    [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
10450 // CHECK11-NEXT:    store i16 [[CONV5]], i16* [[CONV]], align 4
10451 // CHECK11-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
10452 // CHECK11:       omp.body.continue:
10453 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
10454 // CHECK11:       omp.inner.for.inc:
10455 // CHECK11-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
10456 // CHECK11-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP10]], 1
10457 // CHECK11-NEXT:    store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4
10458 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_COND]]
10459 // CHECK11:       omp.inner.for.end:
10460 // CHECK11-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
10461 // CHECK11:       omp.loop.exit:
10462 // CHECK11-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
10463 // CHECK11-NEXT:    ret void
10464 //
10465 //
10466 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145
10467 // CHECK11-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
10468 // CHECK11-NEXT:  entry:
10469 // CHECK11-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
10470 // CHECK11-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
10471 // CHECK11-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
10472 // CHECK11-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 4
10473 // CHECK11-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
10474 // CHECK11-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
10475 // CHECK11-NEXT:    [[VLA_ADDR4:%.*]] = alloca i32, align 4
10476 // CHECK11-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 4
10477 // CHECK11-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
10478 // CHECK11-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
10479 // CHECK11-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
10480 // CHECK11-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
10481 // CHECK11-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
10482 // CHECK11-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
10483 // CHECK11-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
10484 // CHECK11-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 4
10485 // CHECK11-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
10486 // CHECK11-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
10487 // CHECK11-NEXT:    store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
10488 // CHECK11-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 4
10489 // CHECK11-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
10490 // CHECK11-NEXT:    store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
10491 // CHECK11-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
10492 // CHECK11-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
10493 // CHECK11-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
10494 // CHECK11-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
10495 // CHECK11-NEXT:    [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
10496 // CHECK11-NEXT:    [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
10497 // CHECK11-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
10498 // CHECK11-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
10499 // CHECK11-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
10500 // CHECK11-NEXT:    store i32 [[TMP8]], i32* [[A_CASTED]], align 4
10501 // CHECK11-NEXT:    [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4
10502 // CHECK11-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
10503 // CHECK11-NEXT:    store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
10504 // CHECK11-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
10505 // CHECK11-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i32 [[TMP11]])
10506 // CHECK11-NEXT:    ret void
10507 //
10508 //
10509 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..3
10510 // CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
10511 // CHECK11-NEXT:  entry:
10512 // CHECK11-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
10513 // CHECK11-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
10514 // CHECK11-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
10515 // CHECK11-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
10516 // CHECK11-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
10517 // CHECK11-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 4
10518 // CHECK11-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
10519 // CHECK11-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
10520 // CHECK11-NEXT:    [[VLA_ADDR4:%.*]] = alloca i32, align 4
10521 // CHECK11-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 4
10522 // CHECK11-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
10523 // CHECK11-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
10524 // CHECK11-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
10525 // CHECK11-NEXT:    [[TMP:%.*]] = alloca i32, align 4
10526 // CHECK11-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
10527 // CHECK11-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
10528 // CHECK11-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
10529 // CHECK11-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
10530 // CHECK11-NEXT:    [[I:%.*]] = alloca i32, align 4
10531 // CHECK11-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
10532 // CHECK11-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
10533 // CHECK11-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
10534 // CHECK11-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
10535 // CHECK11-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
10536 // CHECK11-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 4
10537 // CHECK11-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
10538 // CHECK11-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
10539 // CHECK11-NEXT:    store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
10540 // CHECK11-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 4
10541 // CHECK11-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
10542 // CHECK11-NEXT:    store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
10543 // CHECK11-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
10544 // CHECK11-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
10545 // CHECK11-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
10546 // CHECK11-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
10547 // CHECK11-NEXT:    [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
10548 // CHECK11-NEXT:    [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
10549 // CHECK11-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
10550 // CHECK11-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
10551 // CHECK11-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
10552 // CHECK11-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
10553 // CHECK11-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
10554 // CHECK11-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
10555 // CHECK11-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
10556 // CHECK11-NEXT:    [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
10557 // CHECK11-NEXT:    [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
10558 // CHECK11-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
10559 // CHECK11-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
10560 // CHECK11:       omp.dispatch.cond:
10561 // CHECK11-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
10562 // CHECK11-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 9
10563 // CHECK11-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
10564 // CHECK11:       cond.true:
10565 // CHECK11-NEXT:    br label [[COND_END:%.*]]
10566 // CHECK11:       cond.false:
10567 // CHECK11-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
10568 // CHECK11-NEXT:    br label [[COND_END]]
10569 // CHECK11:       cond.end:
10570 // CHECK11-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
10571 // CHECK11-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
10572 // CHECK11-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
10573 // CHECK11-NEXT:    store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
10574 // CHECK11-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
10575 // CHECK11-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
10576 // CHECK11-NEXT:    [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
10577 // CHECK11-NEXT:    br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
10578 // CHECK11:       omp.dispatch.body:
10579 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
10580 // CHECK11:       omp.inner.for.cond:
10581 // CHECK11-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
10582 // CHECK11-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !12
10583 // CHECK11-NEXT:    [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
10584 // CHECK11-NEXT:    br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
10585 // CHECK11:       omp.inner.for.body:
10586 // CHECK11-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
10587 // CHECK11-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
10588 // CHECK11-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
10589 // CHECK11-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !12
10590 // CHECK11-NEXT:    [[TMP19:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !12
10591 // CHECK11-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP19]], 1
10592 // CHECK11-NEXT:    store i32 [[ADD7]], i32* [[A_ADDR]], align 4, !llvm.access.group !12
10593 // CHECK11-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2
10594 // CHECK11-NEXT:    [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !12
10595 // CHECK11-NEXT:    [[CONV:%.*]] = fpext float [[TMP20]] to double
10596 // CHECK11-NEXT:    [[ADD8:%.*]] = fadd double [[CONV]], 1.000000e+00
10597 // CHECK11-NEXT:    [[CONV9:%.*]] = fptrunc double [[ADD8]] to float
10598 // CHECK11-NEXT:    store float [[CONV9]], float* [[ARRAYIDX]], align 4, !llvm.access.group !12
10599 // CHECK11-NEXT:    [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3
10600 // CHECK11-NEXT:    [[TMP21:%.*]] = load float, float* [[ARRAYIDX10]], align 4, !llvm.access.group !12
10601 // CHECK11-NEXT:    [[CONV11:%.*]] = fpext float [[TMP21]] to double
10602 // CHECK11-NEXT:    [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00
10603 // CHECK11-NEXT:    [[CONV13:%.*]] = fptrunc double [[ADD12]] to float
10604 // CHECK11-NEXT:    store float [[CONV13]], float* [[ARRAYIDX10]], align 4, !llvm.access.group !12
10605 // CHECK11-NEXT:    [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1
10606 // CHECK11-NEXT:    [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX14]], i32 0, i32 2
10607 // CHECK11-NEXT:    [[TMP22:%.*]] = load double, double* [[ARRAYIDX15]], align 8, !llvm.access.group !12
10608 // CHECK11-NEXT:    [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00
10609 // CHECK11-NEXT:    store double [[ADD16]], double* [[ARRAYIDX15]], align 8, !llvm.access.group !12
10610 // CHECK11-NEXT:    [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]]
10611 // CHECK11-NEXT:    [[ARRAYIDX17:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP23]]
10612 // CHECK11-NEXT:    [[ARRAYIDX18:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX17]], i32 3
10613 // CHECK11-NEXT:    [[TMP24:%.*]] = load double, double* [[ARRAYIDX18]], align 8, !llvm.access.group !12
10614 // CHECK11-NEXT:    [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00
10615 // CHECK11-NEXT:    store double [[ADD19]], double* [[ARRAYIDX18]], align 8, !llvm.access.group !12
10616 // CHECK11-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0
10617 // CHECK11-NEXT:    [[TMP25:%.*]] = load i64, i64* [[X]], align 4, !llvm.access.group !12
10618 // CHECK11-NEXT:    [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1
10619 // CHECK11-NEXT:    store i64 [[ADD20]], i64* [[X]], align 4, !llvm.access.group !12
10620 // CHECK11-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1
10621 // CHECK11-NEXT:    [[TMP26:%.*]] = load i8, i8* [[Y]], align 4, !llvm.access.group !12
10622 // CHECK11-NEXT:    [[CONV21:%.*]] = sext i8 [[TMP26]] to i32
10623 // CHECK11-NEXT:    [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1
10624 // CHECK11-NEXT:    [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8
10625 // CHECK11-NEXT:    store i8 [[CONV23]], i8* [[Y]], align 4, !llvm.access.group !12
10626 // CHECK11-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
10627 // CHECK11:       omp.body.continue:
10628 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
10629 // CHECK11:       omp.inner.for.inc:
10630 // CHECK11-NEXT:    [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
10631 // CHECK11-NEXT:    [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1
10632 // CHECK11-NEXT:    store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
10633 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]
10634 // CHECK11:       omp.inner.for.end:
10635 // CHECK11-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
10636 // CHECK11:       omp.dispatch.inc:
10637 // CHECK11-NEXT:    [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
10638 // CHECK11-NEXT:    [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
10639 // CHECK11-NEXT:    [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]
10640 // CHECK11-NEXT:    store i32 [[ADD25]], i32* [[DOTOMP_LB]], align 4
10641 // CHECK11-NEXT:    [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
10642 // CHECK11-NEXT:    [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
10643 // CHECK11-NEXT:    [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]]
10644 // CHECK11-NEXT:    store i32 [[ADD26]], i32* [[DOTOMP_UB]], align 4
10645 // CHECK11-NEXT:    br label [[OMP_DISPATCH_COND]]
10646 // CHECK11:       omp.dispatch.end:
10647 // CHECK11-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]])
10648 // CHECK11-NEXT:    ret void
10649 //
10650 //
10651 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200
10652 // CHECK11-SAME: (i32 [[N:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
10653 // CHECK11-NEXT:  entry:
10654 // CHECK11-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
10655 // CHECK11-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
10656 // CHECK11-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
10657 // CHECK11-NEXT:    [[AAA_ADDR:%.*]] = alloca i32, align 4
10658 // CHECK11-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
10659 // CHECK11-NEXT:    [[N_CASTED:%.*]] = alloca i32, align 4
10660 // CHECK11-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
10661 // CHECK11-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
10662 // CHECK11-NEXT:    [[AAA_CASTED:%.*]] = alloca i32, align 4
10663 // CHECK11-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
10664 // CHECK11-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
10665 // CHECK11-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
10666 // CHECK11-NEXT:    store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
10667 // CHECK11-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
10668 // CHECK11-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
10669 // CHECK11-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
10670 // CHECK11-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
10671 // CHECK11-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
10672 // CHECK11-NEXT:    store i32 [[TMP1]], i32* [[N_CASTED]], align 4
10673 // CHECK11-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_CASTED]], align 4
10674 // CHECK11-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4
10675 // CHECK11-NEXT:    store i32 [[TMP3]], i32* [[A_CASTED]], align 4
10676 // CHECK11-NEXT:    [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4
10677 // CHECK11-NEXT:    [[TMP5:%.*]] = load i16, i16* [[CONV]], align 4
10678 // CHECK11-NEXT:    [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
10679 // CHECK11-NEXT:    store i16 [[TMP5]], i16* [[CONV2]], align 2
10680 // CHECK11-NEXT:    [[TMP6:%.*]] = load i32, i32* [[AA_CASTED]], align 4
10681 // CHECK11-NEXT:    [[TMP7:%.*]] = load i8, i8* [[CONV1]], align 4
10682 // CHECK11-NEXT:    [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
10683 // CHECK11-NEXT:    store i8 [[TMP7]], i8* [[CONV3]], align 1
10684 // CHECK11-NEXT:    [[TMP8:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
10685 // CHECK11-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP8]], [10 x i32]* [[TMP0]])
10686 // CHECK11-NEXT:    ret void
10687 //
10688 //
10689 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..4
10690 // CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
10691 // CHECK11-NEXT:  entry:
10692 // CHECK11-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
10693 // CHECK11-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
10694 // CHECK11-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
10695 // CHECK11-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
10696 // CHECK11-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
10697 // CHECK11-NEXT:    [[AAA_ADDR:%.*]] = alloca i32, align 4
10698 // CHECK11-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
10699 // CHECK11-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
10700 // CHECK11-NEXT:    [[TMP:%.*]] = alloca i32, align 4
10701 // CHECK11-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
10702 // CHECK11-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
10703 // CHECK11-NEXT:    [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4
10704 // CHECK11-NEXT:    [[I:%.*]] = alloca i32, align 4
10705 // CHECK11-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
10706 // CHECK11-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
10707 // CHECK11-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
10708 // CHECK11-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
10709 // CHECK11-NEXT:    [[I6:%.*]] = alloca i32, align 4
10710 // CHECK11-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
10711 // CHECK11-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
10712 // CHECK11-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
10713 // CHECK11-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
10714 // CHECK11-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
10715 // CHECK11-NEXT:    store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
10716 // CHECK11-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
10717 // CHECK11-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
10718 // CHECK11-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
10719 // CHECK11-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
10720 // CHECK11-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
10721 // CHECK11-NEXT:    store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
10722 // CHECK11-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
10723 // CHECK11-NEXT:    store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4
10724 // CHECK11-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
10725 // CHECK11-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
10726 // CHECK11-NEXT:    [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]]
10727 // CHECK11-NEXT:    [[SUB4:%.*]] = sub i32 [[SUB]], 1
10728 // CHECK11-NEXT:    [[ADD:%.*]] = add i32 [[SUB4]], 1
10729 // CHECK11-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], 1
10730 // CHECK11-NEXT:    [[SUB5:%.*]] = sub i32 [[DIV]], 1
10731 // CHECK11-NEXT:    store i32 [[SUB5]], i32* [[DOTCAPTURE_EXPR_3]], align 4
10732 // CHECK11-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
10733 // CHECK11-NEXT:    store i32 [[TMP5]], i32* [[I]], align 4
10734 // CHECK11-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
10735 // CHECK11-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
10736 // CHECK11-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]]
10737 // CHECK11-NEXT:    br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
10738 // CHECK11:       omp.precond.then:
10739 // CHECK11-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
10740 // CHECK11-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
10741 // CHECK11-NEXT:    store i32 [[TMP8]], i32* [[DOTOMP_UB]], align 4
10742 // CHECK11-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
10743 // CHECK11-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
10744 // CHECK11-NEXT:    [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
10745 // CHECK11-NEXT:    [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
10746 // CHECK11-NEXT:    call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
10747 // CHECK11-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
10748 // CHECK11-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
10749 // CHECK11-NEXT:    [[CMP7:%.*]] = icmp ugt i32 [[TMP11]], [[TMP12]]
10750 // CHECK11-NEXT:    br i1 [[CMP7]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
10751 // CHECK11:       cond.true:
10752 // CHECK11-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
10753 // CHECK11-NEXT:    br label [[COND_END:%.*]]
10754 // CHECK11:       cond.false:
10755 // CHECK11-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
10756 // CHECK11-NEXT:    br label [[COND_END]]
10757 // CHECK11:       cond.end:
10758 // CHECK11-NEXT:    [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ]
10759 // CHECK11-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
10760 // CHECK11-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
10761 // CHECK11-NEXT:    store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4
10762 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
10763 // CHECK11:       omp.inner.for.cond:
10764 // CHECK11-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
10765 // CHECK11-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
10766 // CHECK11-NEXT:    [[ADD8:%.*]] = add i32 [[TMP17]], 1
10767 // CHECK11-NEXT:    [[CMP9:%.*]] = icmp ult i32 [[TMP16]], [[ADD8]]
10768 // CHECK11-NEXT:    br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
10769 // CHECK11:       omp.inner.for.body:
10770 // CHECK11-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
10771 // CHECK11-NEXT:    [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
10772 // CHECK11-NEXT:    [[MUL:%.*]] = mul i32 [[TMP19]], 1
10773 // CHECK11-NEXT:    [[ADD10:%.*]] = add i32 [[TMP18]], [[MUL]]
10774 // CHECK11-NEXT:    store i32 [[ADD10]], i32* [[I6]], align 4
10775 // CHECK11-NEXT:    [[TMP20:%.*]] = load i32, i32* [[A_ADDR]], align 4
10776 // CHECK11-NEXT:    [[ADD11:%.*]] = add nsw i32 [[TMP20]], 1
10777 // CHECK11-NEXT:    store i32 [[ADD11]], i32* [[A_ADDR]], align 4
10778 // CHECK11-NEXT:    [[TMP21:%.*]] = load i16, i16* [[CONV]], align 4
10779 // CHECK11-NEXT:    [[CONV12:%.*]] = sext i16 [[TMP21]] to i32
10780 // CHECK11-NEXT:    [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1
10781 // CHECK11-NEXT:    [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16
10782 // CHECK11-NEXT:    store i16 [[CONV14]], i16* [[CONV]], align 4
10783 // CHECK11-NEXT:    [[TMP22:%.*]] = load i8, i8* [[CONV1]], align 4
10784 // CHECK11-NEXT:    [[CONV15:%.*]] = sext i8 [[TMP22]] to i32
10785 // CHECK11-NEXT:    [[ADD16:%.*]] = add nsw i32 [[CONV15]], 1
10786 // CHECK11-NEXT:    [[CONV17:%.*]] = trunc i32 [[ADD16]] to i8
10787 // CHECK11-NEXT:    store i8 [[CONV17]], i8* [[CONV1]], align 4
10788 // CHECK11-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
10789 // CHECK11-NEXT:    [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
10790 // CHECK11-NEXT:    [[ADD18:%.*]] = add nsw i32 [[TMP23]], 1
10791 // CHECK11-NEXT:    store i32 [[ADD18]], i32* [[ARRAYIDX]], align 4
10792 // CHECK11-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
10793 // CHECK11:       omp.body.continue:
10794 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
10795 // CHECK11:       omp.inner.for.inc:
10796 // CHECK11-NEXT:    [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
10797 // CHECK11-NEXT:    [[ADD19:%.*]] = add i32 [[TMP24]], 1
10798 // CHECK11-NEXT:    store i32 [[ADD19]], i32* [[DOTOMP_IV]], align 4
10799 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_COND]]
10800 // CHECK11:       omp.inner.for.end:
10801 // CHECK11-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
10802 // CHECK11:       omp.loop.exit:
10803 // CHECK11-NEXT:    [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
10804 // CHECK11-NEXT:    [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4
10805 // CHECK11-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]])
10806 // CHECK11-NEXT:    br label [[OMP_PRECOND_END]]
10807 // CHECK11:       omp.precond.end:
10808 // CHECK11-NEXT:    ret void
10809 //
10810 //
10811 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218
10812 // CHECK11-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {
10813 // CHECK11-NEXT:  entry:
10814 // CHECK11-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
10815 // CHECK11-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
10816 // CHECK11-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
10817 // CHECK11-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
10818 // CHECK11-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 4
10819 // CHECK11-NEXT:    [[B_CASTED:%.*]] = alloca i32, align 4
10820 // CHECK11-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
10821 // CHECK11-NEXT:    store i32 [[B]], i32* [[B_ADDR]], align 4
10822 // CHECK11-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
10823 // CHECK11-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
10824 // CHECK11-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 4
10825 // CHECK11-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
10826 // CHECK11-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
10827 // CHECK11-NEXT:    [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
10828 // CHECK11-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
10829 // CHECK11-NEXT:    [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4
10830 // CHECK11-NEXT:    store i32 [[TMP4]], i32* [[B_CASTED]], align 4
10831 // CHECK11-NEXT:    [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4
10832 // CHECK11-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]])
10833 // CHECK11-NEXT:    ret void
10834 //
10835 //
10836 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..5
10837 // CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {
10838 // CHECK11-NEXT:  entry:
10839 // CHECK11-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
10840 // CHECK11-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
10841 // CHECK11-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
10842 // CHECK11-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
10843 // CHECK11-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
10844 // CHECK11-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
10845 // CHECK11-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 4
10846 // CHECK11-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
10847 // CHECK11-NEXT:    [[TMP:%.*]] = alloca i32, align 4
10848 // CHECK11-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
10849 // CHECK11-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
10850 // CHECK11-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
10851 // CHECK11-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
10852 // CHECK11-NEXT:    [[I:%.*]] = alloca i32, align 4
10853 // CHECK11-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
10854 // CHECK11-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
10855 // CHECK11-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
10856 // CHECK11-NEXT:    store i32 [[B]], i32* [[B_ADDR]], align 4
10857 // CHECK11-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
10858 // CHECK11-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
10859 // CHECK11-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 4
10860 // CHECK11-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
10861 // CHECK11-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
10862 // CHECK11-NEXT:    [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
10863 // CHECK11-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
10864 // CHECK11-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
10865 // CHECK11-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
10866 // CHECK11-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
10867 // CHECK11-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
10868 // CHECK11-NEXT:    [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
10869 // CHECK11-NEXT:    [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
10870 // CHECK11-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
10871 // CHECK11-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
10872 // CHECK11-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 9
10873 // CHECK11-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
10874 // CHECK11:       cond.true:
10875 // CHECK11-NEXT:    br label [[COND_END:%.*]]
10876 // CHECK11:       cond.false:
10877 // CHECK11-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
10878 // CHECK11-NEXT:    br label [[COND_END]]
10879 // CHECK11:       cond.end:
10880 // CHECK11-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
10881 // CHECK11-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
10882 // CHECK11-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
10883 // CHECK11-NEXT:    store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
10884 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
10885 // CHECK11:       omp.inner.for.cond:
10886 // CHECK11-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
10887 // CHECK11-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
10888 // CHECK11-NEXT:    [[CMP3:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
10889 // CHECK11-NEXT:    br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
10890 // CHECK11:       omp.inner.for.body:
10891 // CHECK11-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
10892 // CHECK11-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
10893 // CHECK11-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
10894 // CHECK11-NEXT:    store i32 [[ADD]], i32* [[I]], align 4
10895 // CHECK11-NEXT:    [[TMP12:%.*]] = load i32, i32* [[B_ADDR]], align 4
10896 // CHECK11-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP12]] to double
10897 // CHECK11-NEXT:    [[ADD4:%.*]] = fadd double [[CONV]], 1.500000e+00
10898 // CHECK11-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
10899 // CHECK11-NEXT:    store double [[ADD4]], double* [[A]], align 4
10900 // CHECK11-NEXT:    [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
10901 // CHECK11-NEXT:    [[TMP13:%.*]] = load double, double* [[A5]], align 4
10902 // CHECK11-NEXT:    [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00
10903 // CHECK11-NEXT:    store double [[INC]], double* [[A5]], align 4
10904 // CHECK11-NEXT:    [[CONV6:%.*]] = fptosi double [[INC]] to i16
10905 // CHECK11-NEXT:    [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]]
10906 // CHECK11-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP14]]
10907 // CHECK11-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
10908 // CHECK11-NEXT:    store i16 [[CONV6]], i16* [[ARRAYIDX7]], align 2
10909 // CHECK11-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
10910 // CHECK11:       omp.body.continue:
10911 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
10912 // CHECK11:       omp.inner.for.inc:
10913 // CHECK11-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
10914 // CHECK11-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP15]], 1
10915 // CHECK11-NEXT:    store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4
10916 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_COND]]
10917 // CHECK11:       omp.inner.for.end:
10918 // CHECK11-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
10919 // CHECK11:       omp.loop.exit:
10920 // CHECK11-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
10921 // CHECK11-NEXT:    ret void
10922 //
10923 //
10924 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183
10925 // CHECK11-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
10926 // CHECK11-NEXT:  entry:
10927 // CHECK11-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
10928 // CHECK11-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
10929 // CHECK11-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
10930 // CHECK11-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
10931 // CHECK11-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
10932 // CHECK11-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
10933 // CHECK11-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
10934 // CHECK11-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
10935 // CHECK11-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
10936 // CHECK11-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
10937 // CHECK11-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
10938 // CHECK11-NEXT:    store i32 [[TMP1]], i32* [[A_CASTED]], align 4
10939 // CHECK11-NEXT:    [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
10940 // CHECK11-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
10941 // CHECK11-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
10942 // CHECK11-NEXT:    store i16 [[TMP3]], i16* [[CONV1]], align 2
10943 // CHECK11-NEXT:    [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
10944 // CHECK11-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]])
10945 // CHECK11-NEXT:    ret void
10946 //
10947 //
10948 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..6
10949 // CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
10950 // CHECK11-NEXT:  entry:
10951 // CHECK11-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
10952 // CHECK11-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
10953 // CHECK11-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
10954 // CHECK11-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
10955 // CHECK11-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
10956 // CHECK11-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
10957 // CHECK11-NEXT:    [[TMP:%.*]] = alloca i32, align 4
10958 // CHECK11-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
10959 // CHECK11-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
10960 // CHECK11-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
10961 // CHECK11-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
10962 // CHECK11-NEXT:    [[I:%.*]] = alloca i32, align 4
10963 // CHECK11-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
10964 // CHECK11-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
10965 // CHECK11-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
10966 // CHECK11-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
10967 // CHECK11-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
10968 // CHECK11-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
10969 // CHECK11-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
10970 // CHECK11-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
10971 // CHECK11-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
10972 // CHECK11-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
10973 // CHECK11-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
10974 // CHECK11-NEXT:    [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
10975 // CHECK11-NEXT:    [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
10976 // CHECK11-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
10977 // CHECK11-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
10978 // CHECK11-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9
10979 // CHECK11-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
10980 // CHECK11:       cond.true:
10981 // CHECK11-NEXT:    br label [[COND_END:%.*]]
10982 // CHECK11:       cond.false:
10983 // CHECK11-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
10984 // CHECK11-NEXT:    br label [[COND_END]]
10985 // CHECK11:       cond.end:
10986 // CHECK11-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
10987 // CHECK11-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
10988 // CHECK11-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
10989 // CHECK11-NEXT:    store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
10990 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
10991 // CHECK11:       omp.inner.for.cond:
10992 // CHECK11-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
10993 // CHECK11-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
10994 // CHECK11-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
10995 // CHECK11-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
10996 // CHECK11:       omp.inner.for.body:
10997 // CHECK11-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
10998 // CHECK11-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
10999 // CHECK11-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
11000 // CHECK11-NEXT:    store i32 [[ADD]], i32* [[I]], align 4
11001 // CHECK11-NEXT:    [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4
11002 // CHECK11-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
11003 // CHECK11-NEXT:    store i32 [[ADD2]], i32* [[A_ADDR]], align 4
11004 // CHECK11-NEXT:    [[TMP10:%.*]] = load i16, i16* [[CONV]], align 4
11005 // CHECK11-NEXT:    [[CONV3:%.*]] = sext i16 [[TMP10]] to i32
11006 // CHECK11-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
11007 // CHECK11-NEXT:    [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
11008 // CHECK11-NEXT:    store i16 [[CONV5]], i16* [[CONV]], align 4
11009 // CHECK11-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
11010 // CHECK11-NEXT:    [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
11011 // CHECK11-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1
11012 // CHECK11-NEXT:    store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4
11013 // CHECK11-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
11014 // CHECK11:       omp.body.continue:
11015 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
11016 // CHECK11:       omp.inner.for.inc:
11017 // CHECK11-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
11018 // CHECK11-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP12]], 1
11019 // CHECK11-NEXT:    store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4
11020 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_COND]]
11021 // CHECK11:       omp.inner.for.end:
11022 // CHECK11-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
11023 // CHECK11:       omp.loop.exit:
11024 // CHECK11-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
11025 // CHECK11-NEXT:    ret void
11026 //
11027 //
11028 // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103
11029 // CHECK12-SAME: (i32 [[AA:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]], i32 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] {
11030 // CHECK12-NEXT:  entry:
11031 // CHECK12-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
11032 // CHECK12-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
11033 // CHECK12-NEXT:    [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4
11034 // CHECK12-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
11035 // CHECK12-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]])
11036 // CHECK12-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
11037 // CHECK12-NEXT:    store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
11038 // CHECK12-NEXT:    store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4
11039 // CHECK12-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
11040 // CHECK12-NEXT:    [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
11041 // CHECK12-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4
11042 // CHECK12-NEXT:    call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
11043 // CHECK12-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
11044 // CHECK12-NEXT:    [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
11045 // CHECK12-NEXT:    store i16 [[TMP3]], i16* [[CONV3]], align 2
11046 // CHECK12-NEXT:    [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
11047 // CHECK12-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]])
11048 // CHECK12-NEXT:    ret void
11049 //
11050 //
11051 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined.
11052 // CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] {
11053 // CHECK12-NEXT:  entry:
11054 // CHECK12-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
11055 // CHECK12-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
11056 // CHECK12-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
11057 // CHECK12-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
11058 // CHECK12-NEXT:    [[TMP:%.*]] = alloca i32, align 4
11059 // CHECK12-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
11060 // CHECK12-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
11061 // CHECK12-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
11062 // CHECK12-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
11063 // CHECK12-NEXT:    [[I:%.*]] = alloca i32, align 4
11064 // CHECK12-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
11065 // CHECK12-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
11066 // CHECK12-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
11067 // CHECK12-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
11068 // CHECK12-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
11069 // CHECK12-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
11070 // CHECK12-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
11071 // CHECK12-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
11072 // CHECK12-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
11073 // CHECK12-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
11074 // CHECK12-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
11075 // CHECK12-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
11076 // CHECK12-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
11077 // CHECK12-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
11078 // CHECK12:       cond.true:
11079 // CHECK12-NEXT:    br label [[COND_END:%.*]]
11080 // CHECK12:       cond.false:
11081 // CHECK12-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
11082 // CHECK12-NEXT:    br label [[COND_END]]
11083 // CHECK12:       cond.end:
11084 // CHECK12-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
11085 // CHECK12-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
11086 // CHECK12-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
11087 // CHECK12-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
11088 // CHECK12-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
11089 // CHECK12:       omp.inner.for.cond:
11090 // CHECK12-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
11091 // CHECK12-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
11092 // CHECK12-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
11093 // CHECK12-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
11094 // CHECK12:       omp.inner.for.body:
11095 // CHECK12-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
11096 // CHECK12-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
11097 // CHECK12-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
11098 // CHECK12-NEXT:    store i32 [[ADD]], i32* [[I]], align 4
11099 // CHECK12-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
11100 // CHECK12:       omp.body.continue:
11101 // CHECK12-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
11102 // CHECK12:       omp.inner.for.inc:
11103 // CHECK12-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
11104 // CHECK12-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
11105 // CHECK12-NEXT:    store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4
11106 // CHECK12-NEXT:    br label [[OMP_INNER_FOR_COND]]
11107 // CHECK12:       omp.inner.for.end:
11108 // CHECK12-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
11109 // CHECK12:       omp.loop.exit:
11110 // CHECK12-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
11111 // CHECK12-NEXT:    ret void
11112 //
11113 //
11114 // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113
11115 // CHECK12-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] {
11116 // CHECK12-NEXT:  entry:
11117 // CHECK12-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
11118 // CHECK12-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
11119 // CHECK12-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
11120 // CHECK12-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
11121 // CHECK12-NEXT:    [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
11122 // CHECK12-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
11123 // CHECK12-NEXT:    store i16 [[TMP0]], i16* [[CONV1]], align 2
11124 // CHECK12-NEXT:    [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
11125 // CHECK12-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]])
11126 // CHECK12-NEXT:    ret void
11127 //
11128 //
11129 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..1
11130 // CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] {
11131 // CHECK12-NEXT:  entry:
11132 // CHECK12-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
11133 // CHECK12-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
11134 // CHECK12-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
11135 // CHECK12-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
11136 // CHECK12-NEXT:    [[TMP:%.*]] = alloca i32, align 4
11137 // CHECK12-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
11138 // CHECK12-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
11139 // CHECK12-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
11140 // CHECK12-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
11141 // CHECK12-NEXT:    [[I:%.*]] = alloca i32, align 4
11142 // CHECK12-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
11143 // CHECK12-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
11144 // CHECK12-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
11145 // CHECK12-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
11146 // CHECK12-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
11147 // CHECK12-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
11148 // CHECK12-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
11149 // CHECK12-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
11150 // CHECK12-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
11151 // CHECK12-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
11152 // CHECK12-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
11153 // CHECK12-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
11154 // CHECK12-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
11155 // CHECK12-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
11156 // CHECK12:       cond.true:
11157 // CHECK12-NEXT:    br label [[COND_END:%.*]]
11158 // CHECK12:       cond.false:
11159 // CHECK12-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
11160 // CHECK12-NEXT:    br label [[COND_END]]
11161 // CHECK12:       cond.end:
11162 // CHECK12-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
11163 // CHECK12-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
11164 // CHECK12-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
11165 // CHECK12-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
11166 // CHECK12-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
11167 // CHECK12:       omp.inner.for.cond:
11168 // CHECK12-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
11169 // CHECK12-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
11170 // CHECK12-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
11171 // CHECK12-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
11172 // CHECK12:       omp.inner.for.body:
11173 // CHECK12-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
11174 // CHECK12-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
11175 // CHECK12-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
11176 // CHECK12-NEXT:    store i32 [[ADD]], i32* [[I]], align 4
11177 // CHECK12-NEXT:    [[TMP8:%.*]] = load i16, i16* [[CONV]], align 4
11178 // CHECK12-NEXT:    [[CONV2:%.*]] = sext i16 [[TMP8]] to i32
11179 // CHECK12-NEXT:    [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
11180 // CHECK12-NEXT:    [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
11181 // CHECK12-NEXT:    store i16 [[CONV4]], i16* [[CONV]], align 4
11182 // CHECK12-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
11183 // CHECK12:       omp.body.continue:
11184 // CHECK12-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
11185 // CHECK12:       omp.inner.for.inc:
11186 // CHECK12-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
11187 // CHECK12-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP9]], 1
11188 // CHECK12-NEXT:    store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4
11189 // CHECK12-NEXT:    br label [[OMP_INNER_FOR_COND]]
11190 // CHECK12:       omp.inner.for.end:
11191 // CHECK12-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
11192 // CHECK12:       omp.loop.exit:
11193 // CHECK12-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
11194 // CHECK12-NEXT:    ret void
11195 //
11196 //
11197 // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120
11198 // CHECK12-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] {
11199 // CHECK12-NEXT:  entry:
11200 // CHECK12-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
11201 // CHECK12-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
11202 // CHECK12-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
11203 // CHECK12-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
11204 // CHECK12-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
11205 // CHECK12-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
11206 // CHECK12-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
11207 // CHECK12-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
11208 // CHECK12-NEXT:    store i32 [[TMP0]], i32* [[A_CASTED]], align 4
11209 // CHECK12-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
11210 // CHECK12-NEXT:    [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
11211 // CHECK12-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
11212 // CHECK12-NEXT:    store i16 [[TMP2]], i16* [[CONV1]], align 2
11213 // CHECK12-NEXT:    [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
11214 // CHECK12-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]])
11215 // CHECK12-NEXT:    ret void
11216 //
11217 //
11218 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..2
11219 // CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] {
11220 // CHECK12-NEXT:  entry:
11221 // CHECK12-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
11222 // CHECK12-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
11223 // CHECK12-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
11224 // CHECK12-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
11225 // CHECK12-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
11226 // CHECK12-NEXT:    [[TMP:%.*]] = alloca i32, align 4
11227 // CHECK12-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
11228 // CHECK12-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
11229 // CHECK12-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
11230 // CHECK12-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
11231 // CHECK12-NEXT:    [[I:%.*]] = alloca i32, align 4
11232 // CHECK12-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
11233 // CHECK12-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
11234 // CHECK12-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
11235 // CHECK12-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
11236 // CHECK12-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
11237 // CHECK12-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
11238 // CHECK12-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
11239 // CHECK12-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
11240 // CHECK12-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
11241 // CHECK12-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
11242 // CHECK12-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
11243 // CHECK12-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
11244 // CHECK12-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
11245 // CHECK12-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
11246 // CHECK12-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
11247 // CHECK12:       cond.true:
11248 // CHECK12-NEXT:    br label [[COND_END:%.*]]
11249 // CHECK12:       cond.false:
11250 // CHECK12-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
11251 // CHECK12-NEXT:    br label [[COND_END]]
11252 // CHECK12:       cond.end:
11253 // CHECK12-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
11254 // CHECK12-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
11255 // CHECK12-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
11256 // CHECK12-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
11257 // CHECK12-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
11258 // CHECK12:       omp.inner.for.cond:
11259 // CHECK12-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
11260 // CHECK12-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
11261 // CHECK12-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
11262 // CHECK12-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
11263 // CHECK12:       omp.inner.for.body:
11264 // CHECK12-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
11265 // CHECK12-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
11266 // CHECK12-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
11267 // CHECK12-NEXT:    store i32 [[ADD]], i32* [[I]], align 4
11268 // CHECK12-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
11269 // CHECK12-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
11270 // CHECK12-NEXT:    store i32 [[ADD2]], i32* [[A_ADDR]], align 4
11271 // CHECK12-NEXT:    [[TMP9:%.*]] = load i16, i16* [[CONV]], align 4
11272 // CHECK12-NEXT:    [[CONV3:%.*]] = sext i16 [[TMP9]] to i32
11273 // CHECK12-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
11274 // CHECK12-NEXT:    [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
11275 // CHECK12-NEXT:    store i16 [[CONV5]], i16* [[CONV]], align 4
11276 // CHECK12-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
11277 // CHECK12:       omp.body.continue:
11278 // CHECK12-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
11279 // CHECK12:       omp.inner.for.inc:
11280 // CHECK12-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
11281 // CHECK12-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP10]], 1
11282 // CHECK12-NEXT:    store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4
11283 // CHECK12-NEXT:    br label [[OMP_INNER_FOR_COND]]
11284 // CHECK12:       omp.inner.for.end:
11285 // CHECK12-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
11286 // CHECK12:       omp.loop.exit:
11287 // CHECK12-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
11288 // CHECK12-NEXT:    ret void
11289 //
11290 //
11291 // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145
11292 // CHECK12-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
11293 // CHECK12-NEXT:  entry:
11294 // CHECK12-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
11295 // CHECK12-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
11296 // CHECK12-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
11297 // CHECK12-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 4
11298 // CHECK12-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
11299 // CHECK12-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
11300 // CHECK12-NEXT:    [[VLA_ADDR4:%.*]] = alloca i32, align 4
11301 // CHECK12-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 4
11302 // CHECK12-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
11303 // CHECK12-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
11304 // CHECK12-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
11305 // CHECK12-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
11306 // CHECK12-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
11307 // CHECK12-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
11308 // CHECK12-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
11309 // CHECK12-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 4
11310 // CHECK12-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
11311 // CHECK12-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
11312 // CHECK12-NEXT:    store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
11313 // CHECK12-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 4
11314 // CHECK12-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
11315 // CHECK12-NEXT:    store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
11316 // CHECK12-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
11317 // CHECK12-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
11318 // CHECK12-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
11319 // CHECK12-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
11320 // CHECK12-NEXT:    [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
11321 // CHECK12-NEXT:    [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
11322 // CHECK12-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
11323 // CHECK12-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
11324 // CHECK12-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
11325 // CHECK12-NEXT:    store i32 [[TMP8]], i32* [[A_CASTED]], align 4
11326 // CHECK12-NEXT:    [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4
11327 // CHECK12-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
11328 // CHECK12-NEXT:    store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
11329 // CHECK12-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
11330 // CHECK12-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i32 [[TMP11]])
11331 // CHECK12-NEXT:    ret void
11332 //
11333 //
11334 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..3
11335 // CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
11336 // CHECK12-NEXT:  entry:
11337 // CHECK12-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
11338 // CHECK12-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
11339 // CHECK12-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
11340 // CHECK12-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
11341 // CHECK12-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
11342 // CHECK12-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 4
11343 // CHECK12-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
11344 // CHECK12-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
11345 // CHECK12-NEXT:    [[VLA_ADDR4:%.*]] = alloca i32, align 4
11346 // CHECK12-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 4
11347 // CHECK12-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
11348 // CHECK12-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
11349 // CHECK12-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
11350 // CHECK12-NEXT:    [[TMP:%.*]] = alloca i32, align 4
11351 // CHECK12-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
11352 // CHECK12-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
11353 // CHECK12-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
11354 // CHECK12-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
11355 // CHECK12-NEXT:    [[I:%.*]] = alloca i32, align 4
11356 // CHECK12-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
11357 // CHECK12-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
11358 // CHECK12-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
11359 // CHECK12-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
11360 // CHECK12-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
11361 // CHECK12-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 4
11362 // CHECK12-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
11363 // CHECK12-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
11364 // CHECK12-NEXT:    store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
11365 // CHECK12-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 4
11366 // CHECK12-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
11367 // CHECK12-NEXT:    store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
11368 // CHECK12-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
11369 // CHECK12-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
11370 // CHECK12-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
11371 // CHECK12-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
11372 // CHECK12-NEXT:    [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
11373 // CHECK12-NEXT:    [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
11374 // CHECK12-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
11375 // CHECK12-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
11376 // CHECK12-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
11377 // CHECK12-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
11378 // CHECK12-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
11379 // CHECK12-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
11380 // CHECK12-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
11381 // CHECK12-NEXT:    [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
11382 // CHECK12-NEXT:    [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
11383 // CHECK12-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
11384 // CHECK12-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
11385 // CHECK12:       omp.dispatch.cond:
11386 // CHECK12-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
11387 // CHECK12-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 9
11388 // CHECK12-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
11389 // CHECK12:       cond.true:
11390 // CHECK12-NEXT:    br label [[COND_END:%.*]]
11391 // CHECK12:       cond.false:
11392 // CHECK12-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
11393 // CHECK12-NEXT:    br label [[COND_END]]
11394 // CHECK12:       cond.end:
11395 // CHECK12-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
11396 // CHECK12-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
11397 // CHECK12-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
11398 // CHECK12-NEXT:    store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
11399 // CHECK12-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
11400 // CHECK12-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
11401 // CHECK12-NEXT:    [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
11402 // CHECK12-NEXT:    br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
11403 // CHECK12:       omp.dispatch.body:
11404 // CHECK12-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
11405 // CHECK12:       omp.inner.for.cond:
11406 // CHECK12-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
11407 // CHECK12-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !12
11408 // CHECK12-NEXT:    [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
11409 // CHECK12-NEXT:    br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
11410 // CHECK12:       omp.inner.for.body:
11411 // CHECK12-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
11412 // CHECK12-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
11413 // CHECK12-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
11414 // CHECK12-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !12
11415 // CHECK12-NEXT:    [[TMP19:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !12
11416 // CHECK12-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP19]], 1
11417 // CHECK12-NEXT:    store i32 [[ADD7]], i32* [[A_ADDR]], align 4, !llvm.access.group !12
11418 // CHECK12-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2
11419 // CHECK12-NEXT:    [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !12
11420 // CHECK12-NEXT:    [[CONV:%.*]] = fpext float [[TMP20]] to double
11421 // CHECK12-NEXT:    [[ADD8:%.*]] = fadd double [[CONV]], 1.000000e+00
11422 // CHECK12-NEXT:    [[CONV9:%.*]] = fptrunc double [[ADD8]] to float
11423 // CHECK12-NEXT:    store float [[CONV9]], float* [[ARRAYIDX]], align 4, !llvm.access.group !12
11424 // CHECK12-NEXT:    [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3
11425 // CHECK12-NEXT:    [[TMP21:%.*]] = load float, float* [[ARRAYIDX10]], align 4, !llvm.access.group !12
11426 // CHECK12-NEXT:    [[CONV11:%.*]] = fpext float [[TMP21]] to double
11427 // CHECK12-NEXT:    [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00
11428 // CHECK12-NEXT:    [[CONV13:%.*]] = fptrunc double [[ADD12]] to float
11429 // CHECK12-NEXT:    store float [[CONV13]], float* [[ARRAYIDX10]], align 4, !llvm.access.group !12
11430 // CHECK12-NEXT:    [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1
11431 // CHECK12-NEXT:    [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX14]], i32 0, i32 2
11432 // CHECK12-NEXT:    [[TMP22:%.*]] = load double, double* [[ARRAYIDX15]], align 8, !llvm.access.group !12
11433 // CHECK12-NEXT:    [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00
11434 // CHECK12-NEXT:    store double [[ADD16]], double* [[ARRAYIDX15]], align 8, !llvm.access.group !12
11435 // CHECK12-NEXT:    [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]]
11436 // CHECK12-NEXT:    [[ARRAYIDX17:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP23]]
11437 // CHECK12-NEXT:    [[ARRAYIDX18:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX17]], i32 3
11438 // CHECK12-NEXT:    [[TMP24:%.*]] = load double, double* [[ARRAYIDX18]], align 8, !llvm.access.group !12
11439 // CHECK12-NEXT:    [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00
11440 // CHECK12-NEXT:    store double [[ADD19]], double* [[ARRAYIDX18]], align 8, !llvm.access.group !12
11441 // CHECK12-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0
11442 // CHECK12-NEXT:    [[TMP25:%.*]] = load i64, i64* [[X]], align 4, !llvm.access.group !12
11443 // CHECK12-NEXT:    [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1
11444 // CHECK12-NEXT:    store i64 [[ADD20]], i64* [[X]], align 4, !llvm.access.group !12
11445 // CHECK12-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1
11446 // CHECK12-NEXT:    [[TMP26:%.*]] = load i8, i8* [[Y]], align 4, !llvm.access.group !12
11447 // CHECK12-NEXT:    [[CONV21:%.*]] = sext i8 [[TMP26]] to i32
11448 // CHECK12-NEXT:    [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1
11449 // CHECK12-NEXT:    [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8
11450 // CHECK12-NEXT:    store i8 [[CONV23]], i8* [[Y]], align 4, !llvm.access.group !12
11451 // CHECK12-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
11452 // CHECK12:       omp.body.continue:
11453 // CHECK12-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
11454 // CHECK12:       omp.inner.for.inc:
11455 // CHECK12-NEXT:    [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
11456 // CHECK12-NEXT:    [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1
11457 // CHECK12-NEXT:    store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
11458 // CHECK12-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]
11459 // CHECK12:       omp.inner.for.end:
11460 // CHECK12-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
11461 // CHECK12:       omp.dispatch.inc:
11462 // CHECK12-NEXT:    [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
11463 // CHECK12-NEXT:    [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
11464 // CHECK12-NEXT:    [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]
11465 // CHECK12-NEXT:    store i32 [[ADD25]], i32* [[DOTOMP_LB]], align 4
11466 // CHECK12-NEXT:    [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
11467 // CHECK12-NEXT:    [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
11468 // CHECK12-NEXT:    [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]]
11469 // CHECK12-NEXT:    store i32 [[ADD26]], i32* [[DOTOMP_UB]], align 4
11470 // CHECK12-NEXT:    br label [[OMP_DISPATCH_COND]]
11471 // CHECK12:       omp.dispatch.end:
11472 // CHECK12-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]])
11473 // CHECK12-NEXT:    ret void
11474 //
11475 //
11476 // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200
11477 // CHECK12-SAME: (i32 [[N:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
11478 // CHECK12-NEXT:  entry:
11479 // CHECK12-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
11480 // CHECK12-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
11481 // CHECK12-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
11482 // CHECK12-NEXT:    [[AAA_ADDR:%.*]] = alloca i32, align 4
11483 // CHECK12-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
11484 // CHECK12-NEXT:    [[N_CASTED:%.*]] = alloca i32, align 4
11485 // CHECK12-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
11486 // CHECK12-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
11487 // CHECK12-NEXT:    [[AAA_CASTED:%.*]] = alloca i32, align 4
11488 // CHECK12-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
11489 // CHECK12-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
11490 // CHECK12-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
11491 // CHECK12-NEXT:    store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
11492 // CHECK12-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
11493 // CHECK12-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
11494 // CHECK12-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
11495 // CHECK12-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
11496 // CHECK12-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
11497 // CHECK12-NEXT:    store i32 [[TMP1]], i32* [[N_CASTED]], align 4
11498 // CHECK12-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_CASTED]], align 4
11499 // CHECK12-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4
11500 // CHECK12-NEXT:    store i32 [[TMP3]], i32* [[A_CASTED]], align 4
11501 // CHECK12-NEXT:    [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4
11502 // CHECK12-NEXT:    [[TMP5:%.*]] = load i16, i16* [[CONV]], align 4
11503 // CHECK12-NEXT:    [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
11504 // CHECK12-NEXT:    store i16 [[TMP5]], i16* [[CONV2]], align 2
11505 // CHECK12-NEXT:    [[TMP6:%.*]] = load i32, i32* [[AA_CASTED]], align 4
11506 // CHECK12-NEXT:    [[TMP7:%.*]] = load i8, i8* [[CONV1]], align 4
11507 // CHECK12-NEXT:    [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
11508 // CHECK12-NEXT:    store i8 [[TMP7]], i8* [[CONV3]], align 1
11509 // CHECK12-NEXT:    [[TMP8:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
11510 // CHECK12-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP8]], [10 x i32]* [[TMP0]])
11511 // CHECK12-NEXT:    ret void
11512 //
11513 //
11514 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..4
11515 // CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
11516 // CHECK12-NEXT:  entry:
11517 // CHECK12-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
11518 // CHECK12-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
11519 // CHECK12-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
11520 // CHECK12-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
11521 // CHECK12-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
11522 // CHECK12-NEXT:    [[AAA_ADDR:%.*]] = alloca i32, align 4
11523 // CHECK12-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
11524 // CHECK12-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
11525 // CHECK12-NEXT:    [[TMP:%.*]] = alloca i32, align 4
11526 // CHECK12-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
11527 // CHECK12-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
11528 // CHECK12-NEXT:    [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4
11529 // CHECK12-NEXT:    [[I:%.*]] = alloca i32, align 4
11530 // CHECK12-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
11531 // CHECK12-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
11532 // CHECK12-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
11533 // CHECK12-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
11534 // CHECK12-NEXT:    [[I6:%.*]] = alloca i32, align 4
11535 // CHECK12-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
11536 // CHECK12-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
11537 // CHECK12-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
11538 // CHECK12-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
11539 // CHECK12-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
11540 // CHECK12-NEXT:    store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
11541 // CHECK12-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
11542 // CHECK12-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
11543 // CHECK12-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
11544 // CHECK12-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
11545 // CHECK12-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
11546 // CHECK12-NEXT:    store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
11547 // CHECK12-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
11548 // CHECK12-NEXT:    store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4
11549 // CHECK12-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
11550 // CHECK12-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
11551 // CHECK12-NEXT:    [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]]
11552 // CHECK12-NEXT:    [[SUB4:%.*]] = sub i32 [[SUB]], 1
11553 // CHECK12-NEXT:    [[ADD:%.*]] = add i32 [[SUB4]], 1
11554 // CHECK12-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], 1
11555 // CHECK12-NEXT:    [[SUB5:%.*]] = sub i32 [[DIV]], 1
11556 // CHECK12-NEXT:    store i32 [[SUB5]], i32* [[DOTCAPTURE_EXPR_3]], align 4
11557 // CHECK12-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
11558 // CHECK12-NEXT:    store i32 [[TMP5]], i32* [[I]], align 4
11559 // CHECK12-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
11560 // CHECK12-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
11561 // CHECK12-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]]
11562 // CHECK12-NEXT:    br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
11563 // CHECK12:       omp.precond.then:
11564 // CHECK12-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
11565 // CHECK12-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
11566 // CHECK12-NEXT:    store i32 [[TMP8]], i32* [[DOTOMP_UB]], align 4
11567 // CHECK12-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
11568 // CHECK12-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
11569 // CHECK12-NEXT:    [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
11570 // CHECK12-NEXT:    [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
11571 // CHECK12-NEXT:    call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
11572 // CHECK12-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
11573 // CHECK12-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
11574 // CHECK12-NEXT:    [[CMP7:%.*]] = icmp ugt i32 [[TMP11]], [[TMP12]]
11575 // CHECK12-NEXT:    br i1 [[CMP7]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
11576 // CHECK12:       cond.true:
11577 // CHECK12-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
11578 // CHECK12-NEXT:    br label [[COND_END:%.*]]
11579 // CHECK12:       cond.false:
11580 // CHECK12-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
11581 // CHECK12-NEXT:    br label [[COND_END]]
11582 // CHECK12:       cond.end:
11583 // CHECK12-NEXT:    [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ]
11584 // CHECK12-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
11585 // CHECK12-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
11586 // CHECK12-NEXT:    store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4
11587 // CHECK12-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
11588 // CHECK12:       omp.inner.for.cond:
11589 // CHECK12-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
11590 // CHECK12-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
11591 // CHECK12-NEXT:    [[ADD8:%.*]] = add i32 [[TMP17]], 1
11592 // CHECK12-NEXT:    [[CMP9:%.*]] = icmp ult i32 [[TMP16]], [[ADD8]]
11593 // CHECK12-NEXT:    br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
11594 // CHECK12:       omp.inner.for.body:
11595 // CHECK12-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
11596 // CHECK12-NEXT:    [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
11597 // CHECK12-NEXT:    [[MUL:%.*]] = mul i32 [[TMP19]], 1
11598 // CHECK12-NEXT:    [[ADD10:%.*]] = add i32 [[TMP18]], [[MUL]]
11599 // CHECK12-NEXT:    store i32 [[ADD10]], i32* [[I6]], align 4
11600 // CHECK12-NEXT:    [[TMP20:%.*]] = load i32, i32* [[A_ADDR]], align 4
11601 // CHECK12-NEXT:    [[ADD11:%.*]] = add nsw i32 [[TMP20]], 1
11602 // CHECK12-NEXT:    store i32 [[ADD11]], i32* [[A_ADDR]], align 4
11603 // CHECK12-NEXT:    [[TMP21:%.*]] = load i16, i16* [[CONV]], align 4
11604 // CHECK12-NEXT:    [[CONV12:%.*]] = sext i16 [[TMP21]] to i32
11605 // CHECK12-NEXT:    [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1
11606 // CHECK12-NEXT:    [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16
11607 // CHECK12-NEXT:    store i16 [[CONV14]], i16* [[CONV]], align 4
11608 // CHECK12-NEXT:    [[TMP22:%.*]] = load i8, i8* [[CONV1]], align 4
11609 // CHECK12-NEXT:    [[CONV15:%.*]] = sext i8 [[TMP22]] to i32
11610 // CHECK12-NEXT:    [[ADD16:%.*]] = add nsw i32 [[CONV15]], 1
11611 // CHECK12-NEXT:    [[CONV17:%.*]] = trunc i32 [[ADD16]] to i8
11612 // CHECK12-NEXT:    store i8 [[CONV17]], i8* [[CONV1]], align 4
11613 // CHECK12-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
11614 // CHECK12-NEXT:    [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
11615 // CHECK12-NEXT:    [[ADD18:%.*]] = add nsw i32 [[TMP23]], 1
11616 // CHECK12-NEXT:    store i32 [[ADD18]], i32* [[ARRAYIDX]], align 4
11617 // CHECK12-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
11618 // CHECK12:       omp.body.continue:
11619 // CHECK12-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
11620 // CHECK12:       omp.inner.for.inc:
11621 // CHECK12-NEXT:    [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
11622 // CHECK12-NEXT:    [[ADD19:%.*]] = add i32 [[TMP24]], 1
11623 // CHECK12-NEXT:    store i32 [[ADD19]], i32* [[DOTOMP_IV]], align 4
11624 // CHECK12-NEXT:    br label [[OMP_INNER_FOR_COND]]
11625 // CHECK12:       omp.inner.for.end:
11626 // CHECK12-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
11627 // CHECK12:       omp.loop.exit:
11628 // CHECK12-NEXT:    [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
11629 // CHECK12-NEXT:    [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4
11630 // CHECK12-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]])
11631 // CHECK12-NEXT:    br label [[OMP_PRECOND_END]]
11632 // CHECK12:       omp.precond.end:
11633 // CHECK12-NEXT:    ret void
11634 //
11635 //
11636 // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218
11637 // CHECK12-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {
11638 // CHECK12-NEXT:  entry:
11639 // CHECK12-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
11640 // CHECK12-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
11641 // CHECK12-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
11642 // CHECK12-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
11643 // CHECK12-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 4
11644 // CHECK12-NEXT:    [[B_CASTED:%.*]] = alloca i32, align 4
11645 // CHECK12-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
11646 // CHECK12-NEXT:    store i32 [[B]], i32* [[B_ADDR]], align 4
11647 // CHECK12-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
11648 // CHECK12-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
11649 // CHECK12-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 4
11650 // CHECK12-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
11651 // CHECK12-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
11652 // CHECK12-NEXT:    [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
11653 // CHECK12-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
11654 // CHECK12-NEXT:    [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4
11655 // CHECK12-NEXT:    store i32 [[TMP4]], i32* [[B_CASTED]], align 4
11656 // CHECK12-NEXT:    [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4
11657 // CHECK12-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]])
11658 // CHECK12-NEXT:    ret void
11659 //
11660 //
11661 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..5
11662 // CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {
11663 // CHECK12-NEXT:  entry:
11664 // CHECK12-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
11665 // CHECK12-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
11666 // CHECK12-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
11667 // CHECK12-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
11668 // CHECK12-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
11669 // CHECK12-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
11670 // CHECK12-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 4
11671 // CHECK12-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
11672 // CHECK12-NEXT:    [[TMP:%.*]] = alloca i32, align 4
11673 // CHECK12-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
11674 // CHECK12-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
11675 // CHECK12-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
11676 // CHECK12-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
11677 // CHECK12-NEXT:    [[I:%.*]] = alloca i32, align 4
11678 // CHECK12-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
11679 // CHECK12-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
11680 // CHECK12-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
11681 // CHECK12-NEXT:    store i32 [[B]], i32* [[B_ADDR]], align 4
11682 // CHECK12-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
11683 // CHECK12-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
11684 // CHECK12-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 4
11685 // CHECK12-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
11686 // CHECK12-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
11687 // CHECK12-NEXT:    [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
11688 // CHECK12-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
11689 // CHECK12-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
11690 // CHECK12-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
11691 // CHECK12-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
11692 // CHECK12-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
11693 // CHECK12-NEXT:    [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
11694 // CHECK12-NEXT:    [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
11695 // CHECK12-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
11696 // CHECK12-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
11697 // CHECK12-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 9
11698 // CHECK12-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
11699 // CHECK12:       cond.true:
11700 // CHECK12-NEXT:    br label [[COND_END:%.*]]
11701 // CHECK12:       cond.false:
11702 // CHECK12-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
11703 // CHECK12-NEXT:    br label [[COND_END]]
11704 // CHECK12:       cond.end:
11705 // CHECK12-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
11706 // CHECK12-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
11707 // CHECK12-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
11708 // CHECK12-NEXT:    store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
11709 // CHECK12-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
11710 // CHECK12:       omp.inner.for.cond:
11711 // CHECK12-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
11712 // CHECK12-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
11713 // CHECK12-NEXT:    [[CMP3:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
11714 // CHECK12-NEXT:    br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
11715 // CHECK12:       omp.inner.for.body:
11716 // CHECK12-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
11717 // CHECK12-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
11718 // CHECK12-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
11719 // CHECK12-NEXT:    store i32 [[ADD]], i32* [[I]], align 4
11720 // CHECK12-NEXT:    [[TMP12:%.*]] = load i32, i32* [[B_ADDR]], align 4
11721 // CHECK12-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP12]] to double
11722 // CHECK12-NEXT:    [[ADD4:%.*]] = fadd double [[CONV]], 1.500000e+00
11723 // CHECK12-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
11724 // CHECK12-NEXT:    store double [[ADD4]], double* [[A]], align 4
11725 // CHECK12-NEXT:    [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
11726 // CHECK12-NEXT:    [[TMP13:%.*]] = load double, double* [[A5]], align 4
11727 // CHECK12-NEXT:    [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00
11728 // CHECK12-NEXT:    store double [[INC]], double* [[A5]], align 4
11729 // CHECK12-NEXT:    [[CONV6:%.*]] = fptosi double [[INC]] to i16
11730 // CHECK12-NEXT:    [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]]
11731 // CHECK12-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP14]]
11732 // CHECK12-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
11733 // CHECK12-NEXT:    store i16 [[CONV6]], i16* [[ARRAYIDX7]], align 2
11734 // CHECK12-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
11735 // CHECK12:       omp.body.continue:
11736 // CHECK12-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
11737 // CHECK12:       omp.inner.for.inc:
11738 // CHECK12-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
11739 // CHECK12-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP15]], 1
11740 // CHECK12-NEXT:    store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4
11741 // CHECK12-NEXT:    br label [[OMP_INNER_FOR_COND]]
11742 // CHECK12:       omp.inner.for.end:
11743 // CHECK12-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
11744 // CHECK12:       omp.loop.exit:
11745 // CHECK12-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
11746 // CHECK12-NEXT:    ret void
11747 //
11748 //
11749 // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183
11750 // CHECK12-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
11751 // CHECK12-NEXT:  entry:
11752 // CHECK12-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
11753 // CHECK12-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
11754 // CHECK12-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
11755 // CHECK12-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
11756 // CHECK12-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
11757 // CHECK12-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
11758 // CHECK12-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
11759 // CHECK12-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
11760 // CHECK12-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
11761 // CHECK12-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
11762 // CHECK12-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
11763 // CHECK12-NEXT:    store i32 [[TMP1]], i32* [[A_CASTED]], align 4
11764 // CHECK12-NEXT:    [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
11765 // CHECK12-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
11766 // CHECK12-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
11767 // CHECK12-NEXT:    store i16 [[TMP3]], i16* [[CONV1]], align 2
11768 // CHECK12-NEXT:    [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
11769 // CHECK12-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]])
11770 // CHECK12-NEXT:    ret void
11771 //
11772 //
11773 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..6
11774 // CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
11775 // CHECK12-NEXT:  entry:
11776 // CHECK12-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
11777 // CHECK12-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
11778 // CHECK12-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
11779 // CHECK12-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
11780 // CHECK12-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
11781 // CHECK12-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
11782 // CHECK12-NEXT:    [[TMP:%.*]] = alloca i32, align 4
11783 // CHECK12-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
11784 // CHECK12-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
11785 // CHECK12-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
11786 // CHECK12-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
11787 // CHECK12-NEXT:    [[I:%.*]] = alloca i32, align 4
11788 // CHECK12-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
11789 // CHECK12-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
11790 // CHECK12-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
11791 // CHECK12-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
11792 // CHECK12-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
11793 // CHECK12-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
11794 // CHECK12-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
11795 // CHECK12-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
11796 // CHECK12-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
11797 // CHECK12-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
11798 // CHECK12-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
11799 // CHECK12-NEXT:    [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
11800 // CHECK12-NEXT:    [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
11801 // CHECK12-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
11802 // CHECK12-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
11803 // CHECK12-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9
11804 // CHECK12-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
11805 // CHECK12:       cond.true:
11806 // CHECK12-NEXT:    br label [[COND_END:%.*]]
11807 // CHECK12:       cond.false:
11808 // CHECK12-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
11809 // CHECK12-NEXT:    br label [[COND_END]]
11810 // CHECK12:       cond.end:
11811 // CHECK12-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
11812 // CHECK12-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
11813 // CHECK12-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
11814 // CHECK12-NEXT:    store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
11815 // CHECK12-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
11816 // CHECK12:       omp.inner.for.cond:
11817 // CHECK12-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
11818 // CHECK12-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
11819 // CHECK12-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
11820 // CHECK12-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
11821 // CHECK12:       omp.inner.for.body:
11822 // CHECK12-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
11823 // CHECK12-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
11824 // CHECK12-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
11825 // CHECK12-NEXT:    store i32 [[ADD]], i32* [[I]], align 4
11826 // CHECK12-NEXT:    [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4
11827 // CHECK12-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
11828 // CHECK12-NEXT:    store i32 [[ADD2]], i32* [[A_ADDR]], align 4
11829 // CHECK12-NEXT:    [[TMP10:%.*]] = load i16, i16* [[CONV]], align 4
11830 // CHECK12-NEXT:    [[CONV3:%.*]] = sext i16 [[TMP10]] to i32
11831 // CHECK12-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
11832 // CHECK12-NEXT:    [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
11833 // CHECK12-NEXT:    store i16 [[CONV5]], i16* [[CONV]], align 4
11834 // CHECK12-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
11835 // CHECK12-NEXT:    [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
11836 // CHECK12-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1
11837 // CHECK12-NEXT:    store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4
11838 // CHECK12-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
11839 // CHECK12:       omp.body.continue:
11840 // CHECK12-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
11841 // CHECK12:       omp.inner.for.inc:
11842 // CHECK12-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
11843 // CHECK12-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP12]], 1
11844 // CHECK12-NEXT:    store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4
11845 // CHECK12-NEXT:    br label [[OMP_INNER_FOR_COND]]
11846 // CHECK12:       omp.inner.for.end:
11847 // CHECK12-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
11848 // CHECK12:       omp.loop.exit:
11849 // CHECK12-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
11850 // CHECK12-NEXT:    ret void
11851 //
11852 //
11853 // CHECK13-LABEL: define {{[^@]+}}@_Z3fooi
11854 // CHECK13-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] {
11855 // CHECK13-NEXT:  entry:
11856 // CHECK13-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
11857 // CHECK13-NEXT:    [[A:%.*]] = alloca i32, align 4
11858 // CHECK13-NEXT:    [[AA:%.*]] = alloca i16, align 2
11859 // CHECK13-NEXT:    [[B:%.*]] = alloca [10 x float], align 4
11860 // CHECK13-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 8
11861 // CHECK13-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
11862 // CHECK13-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 8
11863 // CHECK13-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i64, align 8
11864 // CHECK13-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8
11865 // CHECK13-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
11866 // CHECK13-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
11867 // CHECK13-NEXT:    [[I:%.*]] = alloca i32, align 4
11868 // CHECK13-NEXT:    [[I3:%.*]] = alloca i32, align 4
11869 // CHECK13-NEXT:    [[I10:%.*]] = alloca i32, align 4
11870 // CHECK13-NEXT:    [[I19:%.*]] = alloca i32, align 4
11871 // CHECK13-NEXT:    [[DOTCAPTURE_EXPR_30:%.*]] = alloca i32, align 4
11872 // CHECK13-NEXT:    [[I31:%.*]] = alloca i32, align 4
11873 // CHECK13-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
11874 // CHECK13-NEXT:    store i32 0, i32* [[A]], align 4
11875 // CHECK13-NEXT:    store i16 0, i16* [[AA]], align 2
11876 // CHECK13-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
11877 // CHECK13-NEXT:    [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
11878 // CHECK13-NEXT:    [[TMP2:%.*]] = call i8* @llvm.stacksave()
11879 // CHECK13-NEXT:    store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8
11880 // CHECK13-NEXT:    [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4
11881 // CHECK13-NEXT:    store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8
11882 // CHECK13-NEXT:    [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
11883 // CHECK13-NEXT:    [[TMP4:%.*]] = zext i32 [[TMP3]] to i64
11884 // CHECK13-NEXT:    [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]]
11885 // CHECK13-NEXT:    [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8
11886 // CHECK13-NEXT:    store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8
11887 // CHECK13-NEXT:    [[TMP6:%.*]] = load i32, i32* [[A]], align 4
11888 // CHECK13-NEXT:    store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_]], align 4
11889 // CHECK13-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
11890 // CHECK13-NEXT:    store i32 [[TMP7]], i32* [[DOTCAPTURE_EXPR_2]], align 4
11891 // CHECK13-NEXT:    store i32 0, i32* [[I]], align 4
11892 // CHECK13-NEXT:    br label [[FOR_COND:%.*]]
11893 // CHECK13:       for.cond:
11894 // CHECK13-NEXT:    [[TMP8:%.*]] = load i32, i32* [[I]], align 4
11895 // CHECK13-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP8]], 10
11896 // CHECK13-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
11897 // CHECK13:       for.body:
11898 // CHECK13-NEXT:    br label [[FOR_INC:%.*]]
11899 // CHECK13:       for.inc:
11900 // CHECK13-NEXT:    [[TMP9:%.*]] = load i32, i32* [[I]], align 4
11901 // CHECK13-NEXT:    [[INC:%.*]] = add nsw i32 [[TMP9]], 1
11902 // CHECK13-NEXT:    store i32 [[INC]], i32* [[I]], align 4
11903 // CHECK13-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]]
11904 // CHECK13:       for.end:
11905 // CHECK13-NEXT:    store i32 0, i32* [[I3]], align 4
11906 // CHECK13-NEXT:    br label [[FOR_COND4:%.*]]
11907 // CHECK13:       for.cond4:
11908 // CHECK13-NEXT:    [[TMP10:%.*]] = load i32, i32* [[I3]], align 4
11909 // CHECK13-NEXT:    [[CMP5:%.*]] = icmp slt i32 [[TMP10]], 10
11910 // CHECK13-NEXT:    br i1 [[CMP5]], label [[FOR_BODY6:%.*]], label [[FOR_END9:%.*]]
11911 // CHECK13:       for.body6:
11912 // CHECK13-NEXT:    [[TMP11:%.*]] = load i32, i32* [[A]], align 4
11913 // CHECK13-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP11]], 1
11914 // CHECK13-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
11915 // CHECK13-NEXT:    br label [[FOR_INC7:%.*]]
11916 // CHECK13:       for.inc7:
11917 // CHECK13-NEXT:    [[TMP12:%.*]] = load i32, i32* [[I3]], align 4
11918 // CHECK13-NEXT:    [[INC8:%.*]] = add nsw i32 [[TMP12]], 1
11919 // CHECK13-NEXT:    store i32 [[INC8]], i32* [[I3]], align 4
11920 // CHECK13-NEXT:    br label [[FOR_COND4]], !llvm.loop [[LOOP4:![0-9]+]]
11921 // CHECK13:       for.end9:
11922 // CHECK13-NEXT:    store i32 0, i32* [[I10]], align 4
11923 // CHECK13-NEXT:    br label [[FOR_COND11:%.*]]
11924 // CHECK13:       for.cond11:
11925 // CHECK13-NEXT:    [[TMP13:%.*]] = load i32, i32* [[I10]], align 4
11926 // CHECK13-NEXT:    [[CMP12:%.*]] = icmp slt i32 [[TMP13]], 10
11927 // CHECK13-NEXT:    br i1 [[CMP12]], label [[FOR_BODY13:%.*]], label [[FOR_END18:%.*]]
11928 // CHECK13:       for.body13:
11929 // CHECK13-NEXT:    [[TMP14:%.*]] = load i16, i16* [[AA]], align 2
11930 // CHECK13-NEXT:    [[CONV:%.*]] = sext i16 [[TMP14]] to i32
11931 // CHECK13-NEXT:    [[ADD14:%.*]] = add nsw i32 [[CONV]], 1
11932 // CHECK13-NEXT:    [[CONV15:%.*]] = trunc i32 [[ADD14]] to i16
11933 // CHECK13-NEXT:    store i16 [[CONV15]], i16* [[AA]], align 2
11934 // CHECK13-NEXT:    br label [[FOR_INC16:%.*]]
11935 // CHECK13:       for.inc16:
11936 // CHECK13-NEXT:    [[TMP15:%.*]] = load i32, i32* [[I10]], align 4
11937 // CHECK13-NEXT:    [[INC17:%.*]] = add nsw i32 [[TMP15]], 1
11938 // CHECK13-NEXT:    store i32 [[INC17]], i32* [[I10]], align 4
11939 // CHECK13-NEXT:    br label [[FOR_COND11]], !llvm.loop [[LOOP5:![0-9]+]]
11940 // CHECK13:       for.end18:
11941 // CHECK13-NEXT:    store i32 0, i32* [[I19]], align 4
11942 // CHECK13-NEXT:    br label [[FOR_COND20:%.*]]
11943 // CHECK13:       for.cond20:
11944 // CHECK13-NEXT:    [[TMP16:%.*]] = load i32, i32* [[I19]], align 4
11945 // CHECK13-NEXT:    [[CMP21:%.*]] = icmp slt i32 [[TMP16]], 10
11946 // CHECK13-NEXT:    br i1 [[CMP21]], label [[FOR_BODY22:%.*]], label [[FOR_END29:%.*]]
11947 // CHECK13:       for.body22:
11948 // CHECK13-NEXT:    [[TMP17:%.*]] = load i32, i32* [[A]], align 4
11949 // CHECK13-NEXT:    [[ADD23:%.*]] = add nsw i32 [[TMP17]], 1
11950 // CHECK13-NEXT:    store i32 [[ADD23]], i32* [[A]], align 4
11951 // CHECK13-NEXT:    [[TMP18:%.*]] = load i16, i16* [[AA]], align 2
11952 // CHECK13-NEXT:    [[CONV24:%.*]] = sext i16 [[TMP18]] to i32
11953 // CHECK13-NEXT:    [[ADD25:%.*]] = add nsw i32 [[CONV24]], 1
11954 // CHECK13-NEXT:    [[CONV26:%.*]] = trunc i32 [[ADD25]] to i16
11955 // CHECK13-NEXT:    store i16 [[CONV26]], i16* [[AA]], align 2
11956 // CHECK13-NEXT:    br label [[FOR_INC27:%.*]]
11957 // CHECK13:       for.inc27:
11958 // CHECK13-NEXT:    [[TMP19:%.*]] = load i32, i32* [[I19]], align 4
11959 // CHECK13-NEXT:    [[INC28:%.*]] = add nsw i32 [[TMP19]], 1
11960 // CHECK13-NEXT:    store i32 [[INC28]], i32* [[I19]], align 4
11961 // CHECK13-NEXT:    br label [[FOR_COND20]], !llvm.loop [[LOOP6:![0-9]+]]
11962 // CHECK13:       for.end29:
11963 // CHECK13-NEXT:    [[TMP20:%.*]] = load i32, i32* [[N_ADDR]], align 4
11964 // CHECK13-NEXT:    store i32 [[TMP20]], i32* [[DOTCAPTURE_EXPR_30]], align 4
11965 // CHECK13-NEXT:    store i32 0, i32* [[I31]], align 4
11966 // CHECK13-NEXT:    br label [[FOR_COND32:%.*]]
11967 // CHECK13:       for.cond32:
11968 // CHECK13-NEXT:    [[TMP21:%.*]] = load i32, i32* [[I31]], align 4
11969 // CHECK13-NEXT:    [[CMP33:%.*]] = icmp slt i32 [[TMP21]], 10
11970 // CHECK13-NEXT:    br i1 [[CMP33]], label [[FOR_BODY34:%.*]], label [[FOR_END55:%.*]]
11971 // CHECK13:       for.body34:
11972 // CHECK13-NEXT:    [[TMP22:%.*]] = load i32, i32* [[A]], align 4
11973 // CHECK13-NEXT:    [[ADD35:%.*]] = add nsw i32 [[TMP22]], 1
11974 // CHECK13-NEXT:    store i32 [[ADD35]], i32* [[A]], align 4
11975 // CHECK13-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2
11976 // CHECK13-NEXT:    [[TMP23:%.*]] = load float, float* [[ARRAYIDX]], align 4
11977 // CHECK13-NEXT:    [[CONV36:%.*]] = fpext float [[TMP23]] to double
11978 // CHECK13-NEXT:    [[ADD37:%.*]] = fadd double [[CONV36]], 1.000000e+00
11979 // CHECK13-NEXT:    [[CONV38:%.*]] = fptrunc double [[ADD37]] to float
11980 // CHECK13-NEXT:    store float [[CONV38]], float* [[ARRAYIDX]], align 4
11981 // CHECK13-NEXT:    [[ARRAYIDX39:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3
11982 // CHECK13-NEXT:    [[TMP24:%.*]] = load float, float* [[ARRAYIDX39]], align 4
11983 // CHECK13-NEXT:    [[CONV40:%.*]] = fpext float [[TMP24]] to double
11984 // CHECK13-NEXT:    [[ADD41:%.*]] = fadd double [[CONV40]], 1.000000e+00
11985 // CHECK13-NEXT:    [[CONV42:%.*]] = fptrunc double [[ADD41]] to float
11986 // CHECK13-NEXT:    store float [[CONV42]], float* [[ARRAYIDX39]], align 4
11987 // CHECK13-NEXT:    [[ARRAYIDX43:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1
11988 // CHECK13-NEXT:    [[ARRAYIDX44:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX43]], i64 0, i64 2
11989 // CHECK13-NEXT:    [[TMP25:%.*]] = load double, double* [[ARRAYIDX44]], align 8
11990 // CHECK13-NEXT:    [[ADD45:%.*]] = fadd double [[TMP25]], 1.000000e+00
11991 // CHECK13-NEXT:    store double [[ADD45]], double* [[ARRAYIDX44]], align 8
11992 // CHECK13-NEXT:    [[TMP26:%.*]] = mul nsw i64 1, [[TMP4]]
11993 // CHECK13-NEXT:    [[ARRAYIDX46:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP26]]
11994 // CHECK13-NEXT:    [[ARRAYIDX47:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX46]], i64 3
11995 // CHECK13-NEXT:    [[TMP27:%.*]] = load double, double* [[ARRAYIDX47]], align 8
11996 // CHECK13-NEXT:    [[ADD48:%.*]] = fadd double [[TMP27]], 1.000000e+00
11997 // CHECK13-NEXT:    store double [[ADD48]], double* [[ARRAYIDX47]], align 8
11998 // CHECK13-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0
11999 // CHECK13-NEXT:    [[TMP28:%.*]] = load i64, i64* [[X]], align 8
12000 // CHECK13-NEXT:    [[ADD49:%.*]] = add nsw i64 [[TMP28]], 1
12001 // CHECK13-NEXT:    store i64 [[ADD49]], i64* [[X]], align 8
12002 // CHECK13-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1
12003 // CHECK13-NEXT:    [[TMP29:%.*]] = load i8, i8* [[Y]], align 8
12004 // CHECK13-NEXT:    [[CONV50:%.*]] = sext i8 [[TMP29]] to i32
12005 // CHECK13-NEXT:    [[ADD51:%.*]] = add nsw i32 [[CONV50]], 1
12006 // CHECK13-NEXT:    [[CONV52:%.*]] = trunc i32 [[ADD51]] to i8
12007 // CHECK13-NEXT:    store i8 [[CONV52]], i8* [[Y]], align 8
12008 // CHECK13-NEXT:    br label [[FOR_INC53:%.*]]
12009 // CHECK13:       for.inc53:
12010 // CHECK13-NEXT:    [[TMP30:%.*]] = load i32, i32* [[I31]], align 4
12011 // CHECK13-NEXT:    [[INC54:%.*]] = add nsw i32 [[TMP30]], 1
12012 // CHECK13-NEXT:    store i32 [[INC54]], i32* [[I31]], align 4
12013 // CHECK13-NEXT:    br label [[FOR_COND32]], !llvm.loop [[LOOP7:![0-9]+]]
12014 // CHECK13:       for.end55:
12015 // CHECK13-NEXT:    [[TMP31:%.*]] = load i32, i32* [[A]], align 4
12016 // CHECK13-NEXT:    [[TMP32:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
12017 // CHECK13-NEXT:    call void @llvm.stackrestore(i8* [[TMP32]])
12018 // CHECK13-NEXT:    ret i32 [[TMP31]]
12019 //
12020 //
12021 // CHECK13-LABEL: define {{[^@]+}}@_Z3bari
12022 // CHECK13-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
12023 // CHECK13-NEXT:  entry:
12024 // CHECK13-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
12025 // CHECK13-NEXT:    [[A:%.*]] = alloca i32, align 4
12026 // CHECK13-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8
12027 // CHECK13-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
12028 // CHECK13-NEXT:    store i32 0, i32* [[A]], align 4
12029 // CHECK13-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
12030 // CHECK13-NEXT:    [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]])
12031 // CHECK13-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
12032 // CHECK13-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
12033 // CHECK13-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
12034 // CHECK13-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
12035 // CHECK13-NEXT:    [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]])
12036 // CHECK13-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
12037 // CHECK13-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
12038 // CHECK13-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
12039 // CHECK13-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
12040 // CHECK13-NEXT:    [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]])
12041 // CHECK13-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
12042 // CHECK13-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
12043 // CHECK13-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
12044 // CHECK13-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
12045 // CHECK13-NEXT:    [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]])
12046 // CHECK13-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
12047 // CHECK13-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
12048 // CHECK13-NEXT:    store i32 [[ADD6]], i32* [[A]], align 4
12049 // CHECK13-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
12050 // CHECK13-NEXT:    ret i32 [[TMP8]]
12051 //
12052 //
12053 // CHECK13-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
12054 // CHECK13-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 {
12055 // CHECK13-NEXT:  entry:
12056 // CHECK13-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
12057 // CHECK13-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
12058 // CHECK13-NEXT:    [[B:%.*]] = alloca i32, align 4
12059 // CHECK13-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 8
12060 // CHECK13-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
12061 // CHECK13-NEXT:    [[I:%.*]] = alloca i32, align 4
12062 // CHECK13-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
12063 // CHECK13-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
12064 // CHECK13-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
12065 // CHECK13-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
12066 // CHECK13-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
12067 // CHECK13-NEXT:    store i32 [[ADD]], i32* [[B]], align 4
12068 // CHECK13-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
12069 // CHECK13-NEXT:    [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
12070 // CHECK13-NEXT:    [[TMP3:%.*]] = call i8* @llvm.stacksave()
12071 // CHECK13-NEXT:    store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8
12072 // CHECK13-NEXT:    [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]
12073 // CHECK13-NEXT:    [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2
12074 // CHECK13-NEXT:    store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8
12075 // CHECK13-NEXT:    store i32 0, i32* [[I]], align 4
12076 // CHECK13-NEXT:    br label [[FOR_COND:%.*]]
12077 // CHECK13:       for.cond:
12078 // CHECK13-NEXT:    [[TMP5:%.*]] = load i32, i32* [[I]], align 4
12079 // CHECK13-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP5]], 10
12080 // CHECK13-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
12081 // CHECK13:       for.body:
12082 // CHECK13-NEXT:    [[TMP6:%.*]] = load i32, i32* [[B]], align 4
12083 // CHECK13-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP6]] to double
12084 // CHECK13-NEXT:    [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00
12085 // CHECK13-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
12086 // CHECK13-NEXT:    store double [[ADD2]], double* [[A]], align 8
12087 // CHECK13-NEXT:    [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
12088 // CHECK13-NEXT:    [[TMP7:%.*]] = load double, double* [[A3]], align 8
12089 // CHECK13-NEXT:    [[INC:%.*]] = fadd double [[TMP7]], 1.000000e+00
12090 // CHECK13-NEXT:    store double [[INC]], double* [[A3]], align 8
12091 // CHECK13-NEXT:    [[CONV4:%.*]] = fptosi double [[INC]] to i16
12092 // CHECK13-NEXT:    [[TMP8:%.*]] = mul nsw i64 1, [[TMP2]]
12093 // CHECK13-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP8]]
12094 // CHECK13-NEXT:    [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
12095 // CHECK13-NEXT:    store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2
12096 // CHECK13-NEXT:    br label [[FOR_INC:%.*]]
12097 // CHECK13:       for.inc:
12098 // CHECK13-NEXT:    [[TMP9:%.*]] = load i32, i32* [[I]], align 4
12099 // CHECK13-NEXT:    [[INC6:%.*]] = add nsw i32 [[TMP9]], 1
12100 // CHECK13-NEXT:    store i32 [[INC6]], i32* [[I]], align 4
12101 // CHECK13-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]]
12102 // CHECK13:       for.end:
12103 // CHECK13-NEXT:    [[TMP10:%.*]] = mul nsw i64 1, [[TMP2]]
12104 // CHECK13-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP10]]
12105 // CHECK13-NEXT:    [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX7]], i64 1
12106 // CHECK13-NEXT:    [[TMP11:%.*]] = load i16, i16* [[ARRAYIDX8]], align 2
12107 // CHECK13-NEXT:    [[CONV9:%.*]] = sext i16 [[TMP11]] to i32
12108 // CHECK13-NEXT:    [[TMP12:%.*]] = load i32, i32* [[B]], align 4
12109 // CHECK13-NEXT:    [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[TMP12]]
12110 // CHECK13-NEXT:    [[TMP13:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
12111 // CHECK13-NEXT:    call void @llvm.stackrestore(i8* [[TMP13]])
12112 // CHECK13-NEXT:    ret i32 [[ADD10]]
12113 //
12114 //
12115 // CHECK13-LABEL: define {{[^@]+}}@_ZL7fstatici
12116 // CHECK13-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
12117 // CHECK13-NEXT:  entry:
12118 // CHECK13-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
12119 // CHECK13-NEXT:    [[A:%.*]] = alloca i32, align 4
12120 // CHECK13-NEXT:    [[AA:%.*]] = alloca i16, align 2
12121 // CHECK13-NEXT:    [[AAA:%.*]] = alloca i8, align 1
12122 // CHECK13-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
12123 // CHECK13-NEXT:    [[I:%.*]] = alloca i32, align 4
12124 // CHECK13-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
12125 // CHECK13-NEXT:    store i32 0, i32* [[A]], align 4
12126 // CHECK13-NEXT:    store i16 0, i16* [[AA]], align 2
12127 // CHECK13-NEXT:    store i8 0, i8* [[AAA]], align 1
12128 // CHECK13-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
12129 // CHECK13-NEXT:    store i32 [[TMP0]], i32* [[I]], align 4
12130 // CHECK13-NEXT:    br label [[FOR_COND:%.*]]
12131 // CHECK13:       for.cond:
12132 // CHECK13-NEXT:    [[TMP1:%.*]] = load i32, i32* [[I]], align 4
12133 // CHECK13-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
12134 // CHECK13-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP1]], [[TMP2]]
12135 // CHECK13-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
12136 // CHECK13:       for.body:
12137 // CHECK13-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
12138 // CHECK13-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP3]], 1
12139 // CHECK13-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
12140 // CHECK13-NEXT:    [[TMP4:%.*]] = load i16, i16* [[AA]], align 2
12141 // CHECK13-NEXT:    [[CONV:%.*]] = sext i16 [[TMP4]] to i32
12142 // CHECK13-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
12143 // CHECK13-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
12144 // CHECK13-NEXT:    store i16 [[CONV2]], i16* [[AA]], align 2
12145 // CHECK13-NEXT:    [[TMP5:%.*]] = load i8, i8* [[AAA]], align 1
12146 // CHECK13-NEXT:    [[CONV3:%.*]] = sext i8 [[TMP5]] to i32
12147 // CHECK13-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
12148 // CHECK13-NEXT:    [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8
12149 // CHECK13-NEXT:    store i8 [[CONV5]], i8* [[AAA]], align 1
12150 // CHECK13-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2
12151 // CHECK13-NEXT:    [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
12152 // CHECK13-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP6]], 1
12153 // CHECK13-NEXT:    store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4
12154 // CHECK13-NEXT:    br label [[FOR_INC:%.*]]
12155 // CHECK13:       for.inc:
12156 // CHECK13-NEXT:    [[TMP7:%.*]] = load i32, i32* [[I]], align 4
12157 // CHECK13-NEXT:    [[INC:%.*]] = add nsw i32 [[TMP7]], 1
12158 // CHECK13-NEXT:    store i32 [[INC]], i32* [[I]], align 4
12159 // CHECK13-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]
12160 // CHECK13:       for.end:
12161 // CHECK13-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
12162 // CHECK13-NEXT:    ret i32 [[TMP8]]
12163 //
12164 //
12165 // CHECK13-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
12166 // CHECK13-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat {
12167 // CHECK13-NEXT:  entry:
12168 // CHECK13-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
12169 // CHECK13-NEXT:    [[A:%.*]] = alloca i32, align 4
12170 // CHECK13-NEXT:    [[AA:%.*]] = alloca i16, align 2
12171 // CHECK13-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
12172 // CHECK13-NEXT:    [[I:%.*]] = alloca i32, align 4
12173 // CHECK13-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
12174 // CHECK13-NEXT:    store i32 0, i32* [[A]], align 4
12175 // CHECK13-NEXT:    store i16 0, i16* [[AA]], align 2
12176 // CHECK13-NEXT:    store i32 0, i32* [[I]], align 4
12177 // CHECK13-NEXT:    br label [[FOR_COND:%.*]]
12178 // CHECK13:       for.cond:
12179 // CHECK13-NEXT:    [[TMP0:%.*]] = load i32, i32* [[I]], align 4
12180 // CHECK13-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10
12181 // CHECK13-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
12182 // CHECK13:       for.body:
12183 // CHECK13-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
12184 // CHECK13-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
12185 // CHECK13-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
12186 // CHECK13-NEXT:    [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
12187 // CHECK13-NEXT:    [[CONV:%.*]] = sext i16 [[TMP2]] to i32
12188 // CHECK13-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
12189 // CHECK13-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
12190 // CHECK13-NEXT:    store i16 [[CONV2]], i16* [[AA]], align 2
12191 // CHECK13-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2
12192 // CHECK13-NEXT:    [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
12193 // CHECK13-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1
12194 // CHECK13-NEXT:    store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4
12195 // CHECK13-NEXT:    br label [[FOR_INC:%.*]]
12196 // CHECK13:       for.inc:
12197 // CHECK13-NEXT:    [[TMP4:%.*]] = load i32, i32* [[I]], align 4
12198 // CHECK13-NEXT:    [[INC:%.*]] = add nsw i32 [[TMP4]], 1
12199 // CHECK13-NEXT:    store i32 [[INC]], i32* [[I]], align 4
12200 // CHECK13-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]
12201 // CHECK13:       for.end:
12202 // CHECK13-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
12203 // CHECK13-NEXT:    ret i32 [[TMP5]]
12204 //
12205 //
12206 // CHECK14-LABEL: define {{[^@]+}}@_Z3fooi
12207 // CHECK14-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] {
12208 // CHECK14-NEXT:  entry:
12209 // CHECK14-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
12210 // CHECK14-NEXT:    [[A:%.*]] = alloca i32, align 4
12211 // CHECK14-NEXT:    [[AA:%.*]] = alloca i16, align 2
12212 // CHECK14-NEXT:    [[B:%.*]] = alloca [10 x float], align 4
12213 // CHECK14-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 8
12214 // CHECK14-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
12215 // CHECK14-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 8
12216 // CHECK14-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i64, align 8
12217 // CHECK14-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8
12218 // CHECK14-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
12219 // CHECK14-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
12220 // CHECK14-NEXT:    [[I:%.*]] = alloca i32, align 4
12221 // CHECK14-NEXT:    [[I3:%.*]] = alloca i32, align 4
12222 // CHECK14-NEXT:    [[I10:%.*]] = alloca i32, align 4
12223 // CHECK14-NEXT:    [[I19:%.*]] = alloca i32, align 4
12224 // CHECK14-NEXT:    [[DOTCAPTURE_EXPR_30:%.*]] = alloca i32, align 4
12225 // CHECK14-NEXT:    [[I31:%.*]] = alloca i32, align 4
12226 // CHECK14-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
12227 // CHECK14-NEXT:    store i32 0, i32* [[A]], align 4
12228 // CHECK14-NEXT:    store i16 0, i16* [[AA]], align 2
12229 // CHECK14-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
12230 // CHECK14-NEXT:    [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
12231 // CHECK14-NEXT:    [[TMP2:%.*]] = call i8* @llvm.stacksave()
12232 // CHECK14-NEXT:    store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8
12233 // CHECK14-NEXT:    [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4
12234 // CHECK14-NEXT:    store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8
12235 // CHECK14-NEXT:    [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
12236 // CHECK14-NEXT:    [[TMP4:%.*]] = zext i32 [[TMP3]] to i64
12237 // CHECK14-NEXT:    [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]]
12238 // CHECK14-NEXT:    [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8
12239 // CHECK14-NEXT:    store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8
12240 // CHECK14-NEXT:    [[TMP6:%.*]] = load i32, i32* [[A]], align 4
12241 // CHECK14-NEXT:    store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_]], align 4
12242 // CHECK14-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
12243 // CHECK14-NEXT:    store i32 [[TMP7]], i32* [[DOTCAPTURE_EXPR_2]], align 4
12244 // CHECK14-NEXT:    store i32 0, i32* [[I]], align 4
12245 // CHECK14-NEXT:    br label [[FOR_COND:%.*]]
12246 // CHECK14:       for.cond:
12247 // CHECK14-NEXT:    [[TMP8:%.*]] = load i32, i32* [[I]], align 4
12248 // CHECK14-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP8]], 10
12249 // CHECK14-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
12250 // CHECK14:       for.body:
12251 // CHECK14-NEXT:    br label [[FOR_INC:%.*]]
12252 // CHECK14:       for.inc:
12253 // CHECK14-NEXT:    [[TMP9:%.*]] = load i32, i32* [[I]], align 4
12254 // CHECK14-NEXT:    [[INC:%.*]] = add nsw i32 [[TMP9]], 1
12255 // CHECK14-NEXT:    store i32 [[INC]], i32* [[I]], align 4
12256 // CHECK14-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]]
12257 // CHECK14:       for.end:
12258 // CHECK14-NEXT:    store i32 0, i32* [[I3]], align 4
12259 // CHECK14-NEXT:    br label [[FOR_COND4:%.*]]
12260 // CHECK14:       for.cond4:
12261 // CHECK14-NEXT:    [[TMP10:%.*]] = load i32, i32* [[I3]], align 4
12262 // CHECK14-NEXT:    [[CMP5:%.*]] = icmp slt i32 [[TMP10]], 10
12263 // CHECK14-NEXT:    br i1 [[CMP5]], label [[FOR_BODY6:%.*]], label [[FOR_END9:%.*]]
12264 // CHECK14:       for.body6:
12265 // CHECK14-NEXT:    [[TMP11:%.*]] = load i32, i32* [[A]], align 4
12266 // CHECK14-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP11]], 1
12267 // CHECK14-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
12268 // CHECK14-NEXT:    br label [[FOR_INC7:%.*]]
12269 // CHECK14:       for.inc7:
12270 // CHECK14-NEXT:    [[TMP12:%.*]] = load i32, i32* [[I3]], align 4
12271 // CHECK14-NEXT:    [[INC8:%.*]] = add nsw i32 [[TMP12]], 1
12272 // CHECK14-NEXT:    store i32 [[INC8]], i32* [[I3]], align 4
12273 // CHECK14-NEXT:    br label [[FOR_COND4]], !llvm.loop [[LOOP4:![0-9]+]]
12274 // CHECK14:       for.end9:
12275 // CHECK14-NEXT:    store i32 0, i32* [[I10]], align 4
12276 // CHECK14-NEXT:    br label [[FOR_COND11:%.*]]
12277 // CHECK14:       for.cond11:
12278 // CHECK14-NEXT:    [[TMP13:%.*]] = load i32, i32* [[I10]], align 4
12279 // CHECK14-NEXT:    [[CMP12:%.*]] = icmp slt i32 [[TMP13]], 10
12280 // CHECK14-NEXT:    br i1 [[CMP12]], label [[FOR_BODY13:%.*]], label [[FOR_END18:%.*]]
12281 // CHECK14:       for.body13:
12282 // CHECK14-NEXT:    [[TMP14:%.*]] = load i16, i16* [[AA]], align 2
12283 // CHECK14-NEXT:    [[CONV:%.*]] = sext i16 [[TMP14]] to i32
12284 // CHECK14-NEXT:    [[ADD14:%.*]] = add nsw i32 [[CONV]], 1
12285 // CHECK14-NEXT:    [[CONV15:%.*]] = trunc i32 [[ADD14]] to i16
12286 // CHECK14-NEXT:    store i16 [[CONV15]], i16* [[AA]], align 2
12287 // CHECK14-NEXT:    br label [[FOR_INC16:%.*]]
12288 // CHECK14:       for.inc16:
12289 // CHECK14-NEXT:    [[TMP15:%.*]] = load i32, i32* [[I10]], align 4
12290 // CHECK14-NEXT:    [[INC17:%.*]] = add nsw i32 [[TMP15]], 1
12291 // CHECK14-NEXT:    store i32 [[INC17]], i32* [[I10]], align 4
12292 // CHECK14-NEXT:    br label [[FOR_COND11]], !llvm.loop [[LOOP5:![0-9]+]]
12293 // CHECK14:       for.end18:
12294 // CHECK14-NEXT:    store i32 0, i32* [[I19]], align 4
12295 // CHECK14-NEXT:    br label [[FOR_COND20:%.*]]
12296 // CHECK14:       for.cond20:
12297 // CHECK14-NEXT:    [[TMP16:%.*]] = load i32, i32* [[I19]], align 4
12298 // CHECK14-NEXT:    [[CMP21:%.*]] = icmp slt i32 [[TMP16]], 10
12299 // CHECK14-NEXT:    br i1 [[CMP21]], label [[FOR_BODY22:%.*]], label [[FOR_END29:%.*]]
12300 // CHECK14:       for.body22:
12301 // CHECK14-NEXT:    [[TMP17:%.*]] = load i32, i32* [[A]], align 4
12302 // CHECK14-NEXT:    [[ADD23:%.*]] = add nsw i32 [[TMP17]], 1
12303 // CHECK14-NEXT:    store i32 [[ADD23]], i32* [[A]], align 4
12304 // CHECK14-NEXT:    [[TMP18:%.*]] = load i16, i16* [[AA]], align 2
12305 // CHECK14-NEXT:    [[CONV24:%.*]] = sext i16 [[TMP18]] to i32
12306 // CHECK14-NEXT:    [[ADD25:%.*]] = add nsw i32 [[CONV24]], 1
12307 // CHECK14-NEXT:    [[CONV26:%.*]] = trunc i32 [[ADD25]] to i16
12308 // CHECK14-NEXT:    store i16 [[CONV26]], i16* [[AA]], align 2
12309 // CHECK14-NEXT:    br label [[FOR_INC27:%.*]]
12310 // CHECK14:       for.inc27:
12311 // CHECK14-NEXT:    [[TMP19:%.*]] = load i32, i32* [[I19]], align 4
12312 // CHECK14-NEXT:    [[INC28:%.*]] = add nsw i32 [[TMP19]], 1
12313 // CHECK14-NEXT:    store i32 [[INC28]], i32* [[I19]], align 4
12314 // CHECK14-NEXT:    br label [[FOR_COND20]], !llvm.loop [[LOOP6:![0-9]+]]
12315 // CHECK14:       for.end29:
12316 // CHECK14-NEXT:    [[TMP20:%.*]] = load i32, i32* [[N_ADDR]], align 4
12317 // CHECK14-NEXT:    store i32 [[TMP20]], i32* [[DOTCAPTURE_EXPR_30]], align 4
12318 // CHECK14-NEXT:    store i32 0, i32* [[I31]], align 4
12319 // CHECK14-NEXT:    br label [[FOR_COND32:%.*]]
12320 // CHECK14:       for.cond32:
12321 // CHECK14-NEXT:    [[TMP21:%.*]] = load i32, i32* [[I31]], align 4
12322 // CHECK14-NEXT:    [[CMP33:%.*]] = icmp slt i32 [[TMP21]], 10
12323 // CHECK14-NEXT:    br i1 [[CMP33]], label [[FOR_BODY34:%.*]], label [[FOR_END55:%.*]]
12324 // CHECK14:       for.body34:
12325 // CHECK14-NEXT:    [[TMP22:%.*]] = load i32, i32* [[A]], align 4
12326 // CHECK14-NEXT:    [[ADD35:%.*]] = add nsw i32 [[TMP22]], 1
12327 // CHECK14-NEXT:    store i32 [[ADD35]], i32* [[A]], align 4
12328 // CHECK14-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2
12329 // CHECK14-NEXT:    [[TMP23:%.*]] = load float, float* [[ARRAYIDX]], align 4
12330 // CHECK14-NEXT:    [[CONV36:%.*]] = fpext float [[TMP23]] to double
12331 // CHECK14-NEXT:    [[ADD37:%.*]] = fadd double [[CONV36]], 1.000000e+00
12332 // CHECK14-NEXT:    [[CONV38:%.*]] = fptrunc double [[ADD37]] to float
12333 // CHECK14-NEXT:    store float [[CONV38]], float* [[ARRAYIDX]], align 4
12334 // CHECK14-NEXT:    [[ARRAYIDX39:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3
12335 // CHECK14-NEXT:    [[TMP24:%.*]] = load float, float* [[ARRAYIDX39]], align 4
12336 // CHECK14-NEXT:    [[CONV40:%.*]] = fpext float [[TMP24]] to double
12337 // CHECK14-NEXT:    [[ADD41:%.*]] = fadd double [[CONV40]], 1.000000e+00
12338 // CHECK14-NEXT:    [[CONV42:%.*]] = fptrunc double [[ADD41]] to float
12339 // CHECK14-NEXT:    store float [[CONV42]], float* [[ARRAYIDX39]], align 4
12340 // CHECK14-NEXT:    [[ARRAYIDX43:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1
12341 // CHECK14-NEXT:    [[ARRAYIDX44:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX43]], i64 0, i64 2
12342 // CHECK14-NEXT:    [[TMP25:%.*]] = load double, double* [[ARRAYIDX44]], align 8
12343 // CHECK14-NEXT:    [[ADD45:%.*]] = fadd double [[TMP25]], 1.000000e+00
12344 // CHECK14-NEXT:    store double [[ADD45]], double* [[ARRAYIDX44]], align 8
12345 // CHECK14-NEXT:    [[TMP26:%.*]] = mul nsw i64 1, [[TMP4]]
12346 // CHECK14-NEXT:    [[ARRAYIDX46:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP26]]
12347 // CHECK14-NEXT:    [[ARRAYIDX47:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX46]], i64 3
12348 // CHECK14-NEXT:    [[TMP27:%.*]] = load double, double* [[ARRAYIDX47]], align 8
12349 // CHECK14-NEXT:    [[ADD48:%.*]] = fadd double [[TMP27]], 1.000000e+00
12350 // CHECK14-NEXT:    store double [[ADD48]], double* [[ARRAYIDX47]], align 8
12351 // CHECK14-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0
12352 // CHECK14-NEXT:    [[TMP28:%.*]] = load i64, i64* [[X]], align 8
12353 // CHECK14-NEXT:    [[ADD49:%.*]] = add nsw i64 [[TMP28]], 1
12354 // CHECK14-NEXT:    store i64 [[ADD49]], i64* [[X]], align 8
12355 // CHECK14-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1
12356 // CHECK14-NEXT:    [[TMP29:%.*]] = load i8, i8* [[Y]], align 8
12357 // CHECK14-NEXT:    [[CONV50:%.*]] = sext i8 [[TMP29]] to i32
12358 // CHECK14-NEXT:    [[ADD51:%.*]] = add nsw i32 [[CONV50]], 1
12359 // CHECK14-NEXT:    [[CONV52:%.*]] = trunc i32 [[ADD51]] to i8
12360 // CHECK14-NEXT:    store i8 [[CONV52]], i8* [[Y]], align 8
12361 // CHECK14-NEXT:    br label [[FOR_INC53:%.*]]
12362 // CHECK14:       for.inc53:
12363 // CHECK14-NEXT:    [[TMP30:%.*]] = load i32, i32* [[I31]], align 4
12364 // CHECK14-NEXT:    [[INC54:%.*]] = add nsw i32 [[TMP30]], 1
12365 // CHECK14-NEXT:    store i32 [[INC54]], i32* [[I31]], align 4
12366 // CHECK14-NEXT:    br label [[FOR_COND32]], !llvm.loop [[LOOP7:![0-9]+]]
12367 // CHECK14:       for.end55:
12368 // CHECK14-NEXT:    [[TMP31:%.*]] = load i32, i32* [[A]], align 4
12369 // CHECK14-NEXT:    [[TMP32:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
12370 // CHECK14-NEXT:    call void @llvm.stackrestore(i8* [[TMP32]])
12371 // CHECK14-NEXT:    ret i32 [[TMP31]]
12372 //
12373 //
12374 // CHECK14-LABEL: define {{[^@]+}}@_Z3bari
12375 // CHECK14-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
12376 // CHECK14-NEXT:  entry:
12377 // CHECK14-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
12378 // CHECK14-NEXT:    [[A:%.*]] = alloca i32, align 4
12379 // CHECK14-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8
12380 // CHECK14-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
12381 // CHECK14-NEXT:    store i32 0, i32* [[A]], align 4
12382 // CHECK14-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
12383 // CHECK14-NEXT:    [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]])
12384 // CHECK14-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
12385 // CHECK14-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
12386 // CHECK14-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
12387 // CHECK14-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
12388 // CHECK14-NEXT:    [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]])
12389 // CHECK14-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
12390 // CHECK14-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
12391 // CHECK14-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
12392 // CHECK14-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
12393 // CHECK14-NEXT:    [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]])
12394 // CHECK14-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
12395 // CHECK14-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
12396 // CHECK14-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
12397 // CHECK14-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
12398 // CHECK14-NEXT:    [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]])
12399 // CHECK14-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
12400 // CHECK14-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
12401 // CHECK14-NEXT:    store i32 [[ADD6]], i32* [[A]], align 4
12402 // CHECK14-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
12403 // CHECK14-NEXT:    ret i32 [[TMP8]]
12404 //
12405 //
12406 // CHECK14-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
12407 // CHECK14-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 {
12408 // CHECK14-NEXT:  entry:
12409 // CHECK14-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
12410 // CHECK14-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
12411 // CHECK14-NEXT:    [[B:%.*]] = alloca i32, align 4
12412 // CHECK14-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 8
12413 // CHECK14-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
12414 // CHECK14-NEXT:    [[I:%.*]] = alloca i32, align 4
12415 // CHECK14-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
12416 // CHECK14-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
12417 // CHECK14-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
12418 // CHECK14-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
12419 // CHECK14-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
12420 // CHECK14-NEXT:    store i32 [[ADD]], i32* [[B]], align 4
12421 // CHECK14-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
12422 // CHECK14-NEXT:    [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
12423 // CHECK14-NEXT:    [[TMP3:%.*]] = call i8* @llvm.stacksave()
12424 // CHECK14-NEXT:    store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8
12425 // CHECK14-NEXT:    [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]
12426 // CHECK14-NEXT:    [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2
12427 // CHECK14-NEXT:    store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8
12428 // CHECK14-NEXT:    store i32 0, i32* [[I]], align 4
12429 // CHECK14-NEXT:    br label [[FOR_COND:%.*]]
12430 // CHECK14:       for.cond:
12431 // CHECK14-NEXT:    [[TMP5:%.*]] = load i32, i32* [[I]], align 4
12432 // CHECK14-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP5]], 10
12433 // CHECK14-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
12434 // CHECK14:       for.body:
12435 // CHECK14-NEXT:    [[TMP6:%.*]] = load i32, i32* [[B]], align 4
12436 // CHECK14-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP6]] to double
12437 // CHECK14-NEXT:    [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00
12438 // CHECK14-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
12439 // CHECK14-NEXT:    store double [[ADD2]], double* [[A]], align 8
12440 // CHECK14-NEXT:    [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
12441 // CHECK14-NEXT:    [[TMP7:%.*]] = load double, double* [[A3]], align 8
12442 // CHECK14-NEXT:    [[INC:%.*]] = fadd double [[TMP7]], 1.000000e+00
12443 // CHECK14-NEXT:    store double [[INC]], double* [[A3]], align 8
12444 // CHECK14-NEXT:    [[CONV4:%.*]] = fptosi double [[INC]] to i16
12445 // CHECK14-NEXT:    [[TMP8:%.*]] = mul nsw i64 1, [[TMP2]]
12446 // CHECK14-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP8]]
12447 // CHECK14-NEXT:    [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
12448 // CHECK14-NEXT:    store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2
12449 // CHECK14-NEXT:    br label [[FOR_INC:%.*]]
12450 // CHECK14:       for.inc:
12451 // CHECK14-NEXT:    [[TMP9:%.*]] = load i32, i32* [[I]], align 4
12452 // CHECK14-NEXT:    [[INC6:%.*]] = add nsw i32 [[TMP9]], 1
12453 // CHECK14-NEXT:    store i32 [[INC6]], i32* [[I]], align 4
12454 // CHECK14-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]]
12455 // CHECK14:       for.end:
12456 // CHECK14-NEXT:    [[TMP10:%.*]] = mul nsw i64 1, [[TMP2]]
12457 // CHECK14-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP10]]
12458 // CHECK14-NEXT:    [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX7]], i64 1
12459 // CHECK14-NEXT:    [[TMP11:%.*]] = load i16, i16* [[ARRAYIDX8]], align 2
12460 // CHECK14-NEXT:    [[CONV9:%.*]] = sext i16 [[TMP11]] to i32
12461 // CHECK14-NEXT:    [[TMP12:%.*]] = load i32, i32* [[B]], align 4
12462 // CHECK14-NEXT:    [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[TMP12]]
12463 // CHECK14-NEXT:    [[TMP13:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
12464 // CHECK14-NEXT:    call void @llvm.stackrestore(i8* [[TMP13]])
12465 // CHECK14-NEXT:    ret i32 [[ADD10]]
12466 //
12467 //
12468 // CHECK14-LABEL: define {{[^@]+}}@_ZL7fstatici
12469 // CHECK14-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
12470 // CHECK14-NEXT:  entry:
12471 // CHECK14-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
12472 // CHECK14-NEXT:    [[A:%.*]] = alloca i32, align 4
12473 // CHECK14-NEXT:    [[AA:%.*]] = alloca i16, align 2
12474 // CHECK14-NEXT:    [[AAA:%.*]] = alloca i8, align 1
12475 // CHECK14-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
12476 // CHECK14-NEXT:    [[I:%.*]] = alloca i32, align 4
12477 // CHECK14-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
12478 // CHECK14-NEXT:    store i32 0, i32* [[A]], align 4
12479 // CHECK14-NEXT:    store i16 0, i16* [[AA]], align 2
12480 // CHECK14-NEXT:    store i8 0, i8* [[AAA]], align 1
12481 // CHECK14-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
12482 // CHECK14-NEXT:    store i32 [[TMP0]], i32* [[I]], align 4
12483 // CHECK14-NEXT:    br label [[FOR_COND:%.*]]
12484 // CHECK14:       for.cond:
12485 // CHECK14-NEXT:    [[TMP1:%.*]] = load i32, i32* [[I]], align 4
12486 // CHECK14-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
12487 // CHECK14-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP1]], [[TMP2]]
12488 // CHECK14-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
12489 // CHECK14:       for.body:
12490 // CHECK14-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
12491 // CHECK14-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP3]], 1
12492 // CHECK14-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
12493 // CHECK14-NEXT:    [[TMP4:%.*]] = load i16, i16* [[AA]], align 2
12494 // CHECK14-NEXT:    [[CONV:%.*]] = sext i16 [[TMP4]] to i32
12495 // CHECK14-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
12496 // CHECK14-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
12497 // CHECK14-NEXT:    store i16 [[CONV2]], i16* [[AA]], align 2
12498 // CHECK14-NEXT:    [[TMP5:%.*]] = load i8, i8* [[AAA]], align 1
12499 // CHECK14-NEXT:    [[CONV3:%.*]] = sext i8 [[TMP5]] to i32
12500 // CHECK14-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
12501 // CHECK14-NEXT:    [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8
12502 // CHECK14-NEXT:    store i8 [[CONV5]], i8* [[AAA]], align 1
12503 // CHECK14-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2
12504 // CHECK14-NEXT:    [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
12505 // CHECK14-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP6]], 1
12506 // CHECK14-NEXT:    store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4
12507 // CHECK14-NEXT:    br label [[FOR_INC:%.*]]
12508 // CHECK14:       for.inc:
12509 // CHECK14-NEXT:    [[TMP7:%.*]] = load i32, i32* [[I]], align 4
12510 // CHECK14-NEXT:    [[INC:%.*]] = add nsw i32 [[TMP7]], 1
12511 // CHECK14-NEXT:    store i32 [[INC]], i32* [[I]], align 4
12512 // CHECK14-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]
12513 // CHECK14:       for.end:
12514 // CHECK14-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
12515 // CHECK14-NEXT:    ret i32 [[TMP8]]
12516 //
12517 //
12518 // CHECK14-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
12519 // CHECK14-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat {
12520 // CHECK14-NEXT:  entry:
12521 // CHECK14-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
12522 // CHECK14-NEXT:    [[A:%.*]] = alloca i32, align 4
12523 // CHECK14-NEXT:    [[AA:%.*]] = alloca i16, align 2
12524 // CHECK14-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
12525 // CHECK14-NEXT:    [[I:%.*]] = alloca i32, align 4
12526 // CHECK14-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
12527 // CHECK14-NEXT:    store i32 0, i32* [[A]], align 4
12528 // CHECK14-NEXT:    store i16 0, i16* [[AA]], align 2
12529 // CHECK14-NEXT:    store i32 0, i32* [[I]], align 4
12530 // CHECK14-NEXT:    br label [[FOR_COND:%.*]]
12531 // CHECK14:       for.cond:
12532 // CHECK14-NEXT:    [[TMP0:%.*]] = load i32, i32* [[I]], align 4
12533 // CHECK14-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10
12534 // CHECK14-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
12535 // CHECK14:       for.body:
12536 // CHECK14-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
12537 // CHECK14-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
12538 // CHECK14-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
12539 // CHECK14-NEXT:    [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
12540 // CHECK14-NEXT:    [[CONV:%.*]] = sext i16 [[TMP2]] to i32
12541 // CHECK14-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
12542 // CHECK14-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
12543 // CHECK14-NEXT:    store i16 [[CONV2]], i16* [[AA]], align 2
12544 // CHECK14-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2
12545 // CHECK14-NEXT:    [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
12546 // CHECK14-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1
12547 // CHECK14-NEXT:    store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4
12548 // CHECK14-NEXT:    br label [[FOR_INC:%.*]]
12549 // CHECK14:       for.inc:
12550 // CHECK14-NEXT:    [[TMP4:%.*]] = load i32, i32* [[I]], align 4
12551 // CHECK14-NEXT:    [[INC:%.*]] = add nsw i32 [[TMP4]], 1
12552 // CHECK14-NEXT:    store i32 [[INC]], i32* [[I]], align 4
12553 // CHECK14-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]
12554 // CHECK14:       for.end:
12555 // CHECK14-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
12556 // CHECK14-NEXT:    ret i32 [[TMP5]]
12557 //
12558 //
12559 // CHECK15-LABEL: define {{[^@]+}}@_Z3fooi
12560 // CHECK15-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] {
12561 // CHECK15-NEXT:  entry:
12562 // CHECK15-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
12563 // CHECK15-NEXT:    [[A:%.*]] = alloca i32, align 4
12564 // CHECK15-NEXT:    [[AA:%.*]] = alloca i16, align 2
12565 // CHECK15-NEXT:    [[B:%.*]] = alloca [10 x float], align 4
12566 // CHECK15-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 4
12567 // CHECK15-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 4
12568 // CHECK15-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 8
12569 // CHECK15-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i32, align 4
12570 // CHECK15-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4
12571 // CHECK15-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
12572 // CHECK15-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
12573 // CHECK15-NEXT:    [[I:%.*]] = alloca i32, align 4
12574 // CHECK15-NEXT:    [[I3:%.*]] = alloca i32, align 4
12575 // CHECK15-NEXT:    [[I10:%.*]] = alloca i32, align 4
12576 // CHECK15-NEXT:    [[I19:%.*]] = alloca i32, align 4
12577 // CHECK15-NEXT:    [[DOTCAPTURE_EXPR_30:%.*]] = alloca i32, align 4
12578 // CHECK15-NEXT:    [[I31:%.*]] = alloca i32, align 4
12579 // CHECK15-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
12580 // CHECK15-NEXT:    store i32 0, i32* [[A]], align 4
12581 // CHECK15-NEXT:    store i16 0, i16* [[AA]], align 2
12582 // CHECK15-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
12583 // CHECK15-NEXT:    [[TMP1:%.*]] = call i8* @llvm.stacksave()
12584 // CHECK15-NEXT:    store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4
12585 // CHECK15-NEXT:    [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4
12586 // CHECK15-NEXT:    store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4
12587 // CHECK15-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
12588 // CHECK15-NEXT:    [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]]
12589 // CHECK15-NEXT:    [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8
12590 // CHECK15-NEXT:    store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4
12591 // CHECK15-NEXT:    [[TMP4:%.*]] = load i32, i32* [[A]], align 4
12592 // CHECK15-NEXT:    store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4
12593 // CHECK15-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
12594 // CHECK15-NEXT:    store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_2]], align 4
12595 // CHECK15-NEXT:    store i32 0, i32* [[I]], align 4
12596 // CHECK15-NEXT:    br label [[FOR_COND:%.*]]
12597 // CHECK15:       for.cond:
12598 // CHECK15-NEXT:    [[TMP6:%.*]] = load i32, i32* [[I]], align 4
12599 // CHECK15-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP6]], 10
12600 // CHECK15-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
12601 // CHECK15:       for.body:
12602 // CHECK15-NEXT:    br label [[FOR_INC:%.*]]
12603 // CHECK15:       for.inc:
12604 // CHECK15-NEXT:    [[TMP7:%.*]] = load i32, i32* [[I]], align 4
12605 // CHECK15-NEXT:    [[INC:%.*]] = add nsw i32 [[TMP7]], 1
12606 // CHECK15-NEXT:    store i32 [[INC]], i32* [[I]], align 4
12607 // CHECK15-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]
12608 // CHECK15:       for.end:
12609 // CHECK15-NEXT:    store i32 0, i32* [[I3]], align 4
12610 // CHECK15-NEXT:    br label [[FOR_COND4:%.*]]
12611 // CHECK15:       for.cond4:
12612 // CHECK15-NEXT:    [[TMP8:%.*]] = load i32, i32* [[I3]], align 4
12613 // CHECK15-NEXT:    [[CMP5:%.*]] = icmp slt i32 [[TMP8]], 10
12614 // CHECK15-NEXT:    br i1 [[CMP5]], label [[FOR_BODY6:%.*]], label [[FOR_END9:%.*]]
12615 // CHECK15:       for.body6:
12616 // CHECK15-NEXT:    [[TMP9:%.*]] = load i32, i32* [[A]], align 4
12617 // CHECK15-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP9]], 1
12618 // CHECK15-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
12619 // CHECK15-NEXT:    br label [[FOR_INC7:%.*]]
12620 // CHECK15:       for.inc7:
12621 // CHECK15-NEXT:    [[TMP10:%.*]] = load i32, i32* [[I3]], align 4
12622 // CHECK15-NEXT:    [[INC8:%.*]] = add nsw i32 [[TMP10]], 1
12623 // CHECK15-NEXT:    store i32 [[INC8]], i32* [[I3]], align 4
12624 // CHECK15-NEXT:    br label [[FOR_COND4]], !llvm.loop [[LOOP5:![0-9]+]]
12625 // CHECK15:       for.end9:
12626 // CHECK15-NEXT:    store i32 0, i32* [[I10]], align 4
12627 // CHECK15-NEXT:    br label [[FOR_COND11:%.*]]
12628 // CHECK15:       for.cond11:
12629 // CHECK15-NEXT:    [[TMP11:%.*]] = load i32, i32* [[I10]], align 4
12630 // CHECK15-NEXT:    [[CMP12:%.*]] = icmp slt i32 [[TMP11]], 10
12631 // CHECK15-NEXT:    br i1 [[CMP12]], label [[FOR_BODY13:%.*]], label [[FOR_END18:%.*]]
12632 // CHECK15:       for.body13:
12633 // CHECK15-NEXT:    [[TMP12:%.*]] = load i16, i16* [[AA]], align 2
12634 // CHECK15-NEXT:    [[CONV:%.*]] = sext i16 [[TMP12]] to i32
12635 // CHECK15-NEXT:    [[ADD14:%.*]] = add nsw i32 [[CONV]], 1
12636 // CHECK15-NEXT:    [[CONV15:%.*]] = trunc i32 [[ADD14]] to i16
12637 // CHECK15-NEXT:    store i16 [[CONV15]], i16* [[AA]], align 2
12638 // CHECK15-NEXT:    br label [[FOR_INC16:%.*]]
12639 // CHECK15:       for.inc16:
12640 // CHECK15-NEXT:    [[TMP13:%.*]] = load i32, i32* [[I10]], align 4
12641 // CHECK15-NEXT:    [[INC17:%.*]] = add nsw i32 [[TMP13]], 1
12642 // CHECK15-NEXT:    store i32 [[INC17]], i32* [[I10]], align 4
12643 // CHECK15-NEXT:    br label [[FOR_COND11]], !llvm.loop [[LOOP6:![0-9]+]]
12644 // CHECK15:       for.end18:
12645 // CHECK15-NEXT:    store i32 0, i32* [[I19]], align 4
12646 // CHECK15-NEXT:    br label [[FOR_COND20:%.*]]
12647 // CHECK15:       for.cond20:
12648 // CHECK15-NEXT:    [[TMP14:%.*]] = load i32, i32* [[I19]], align 4
12649 // CHECK15-NEXT:    [[CMP21:%.*]] = icmp slt i32 [[TMP14]], 10
12650 // CHECK15-NEXT:    br i1 [[CMP21]], label [[FOR_BODY22:%.*]], label [[FOR_END29:%.*]]
12651 // CHECK15:       for.body22:
12652 // CHECK15-NEXT:    [[TMP15:%.*]] = load i32, i32* [[A]], align 4
12653 // CHECK15-NEXT:    [[ADD23:%.*]] = add nsw i32 [[TMP15]], 1
12654 // CHECK15-NEXT:    store i32 [[ADD23]], i32* [[A]], align 4
12655 // CHECK15-NEXT:    [[TMP16:%.*]] = load i16, i16* [[AA]], align 2
12656 // CHECK15-NEXT:    [[CONV24:%.*]] = sext i16 [[TMP16]] to i32
12657 // CHECK15-NEXT:    [[ADD25:%.*]] = add nsw i32 [[CONV24]], 1
12658 // CHECK15-NEXT:    [[CONV26:%.*]] = trunc i32 [[ADD25]] to i16
12659 // CHECK15-NEXT:    store i16 [[CONV26]], i16* [[AA]], align 2
12660 // CHECK15-NEXT:    br label [[FOR_INC27:%.*]]
12661 // CHECK15:       for.inc27:
12662 // CHECK15-NEXT:    [[TMP17:%.*]] = load i32, i32* [[I19]], align 4
12663 // CHECK15-NEXT:    [[INC28:%.*]] = add nsw i32 [[TMP17]], 1
12664 // CHECK15-NEXT:    store i32 [[INC28]], i32* [[I19]], align 4
12665 // CHECK15-NEXT:    br label [[FOR_COND20]], !llvm.loop [[LOOP7:![0-9]+]]
12666 // CHECK15:       for.end29:
12667 // CHECK15-NEXT:    [[TMP18:%.*]] = load i32, i32* [[N_ADDR]], align 4
12668 // CHECK15-NEXT:    store i32 [[TMP18]], i32* [[DOTCAPTURE_EXPR_30]], align 4
12669 // CHECK15-NEXT:    store i32 0, i32* [[I31]], align 4
12670 // CHECK15-NEXT:    br label [[FOR_COND32:%.*]]
12671 // CHECK15:       for.cond32:
12672 // CHECK15-NEXT:    [[TMP19:%.*]] = load i32, i32* [[I31]], align 4
12673 // CHECK15-NEXT:    [[CMP33:%.*]] = icmp slt i32 [[TMP19]], 10
12674 // CHECK15-NEXT:    br i1 [[CMP33]], label [[FOR_BODY34:%.*]], label [[FOR_END55:%.*]]
12675 // CHECK15:       for.body34:
12676 // CHECK15-NEXT:    [[TMP20:%.*]] = load i32, i32* [[A]], align 4
12677 // CHECK15-NEXT:    [[ADD35:%.*]] = add nsw i32 [[TMP20]], 1
12678 // CHECK15-NEXT:    store i32 [[ADD35]], i32* [[A]], align 4
12679 // CHECK15-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2
12680 // CHECK15-NEXT:    [[TMP21:%.*]] = load float, float* [[ARRAYIDX]], align 4
12681 // CHECK15-NEXT:    [[CONV36:%.*]] = fpext float [[TMP21]] to double
12682 // CHECK15-NEXT:    [[ADD37:%.*]] = fadd double [[CONV36]], 1.000000e+00
12683 // CHECK15-NEXT:    [[CONV38:%.*]] = fptrunc double [[ADD37]] to float
12684 // CHECK15-NEXT:    store float [[CONV38]], float* [[ARRAYIDX]], align 4
12685 // CHECK15-NEXT:    [[ARRAYIDX39:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3
12686 // CHECK15-NEXT:    [[TMP22:%.*]] = load float, float* [[ARRAYIDX39]], align 4
12687 // CHECK15-NEXT:    [[CONV40:%.*]] = fpext float [[TMP22]] to double
12688 // CHECK15-NEXT:    [[ADD41:%.*]] = fadd double [[CONV40]], 1.000000e+00
12689 // CHECK15-NEXT:    [[CONV42:%.*]] = fptrunc double [[ADD41]] to float
12690 // CHECK15-NEXT:    store float [[CONV42]], float* [[ARRAYIDX39]], align 4
12691 // CHECK15-NEXT:    [[ARRAYIDX43:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1
12692 // CHECK15-NEXT:    [[ARRAYIDX44:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX43]], i32 0, i32 2
12693 // CHECK15-NEXT:    [[TMP23:%.*]] = load double, double* [[ARRAYIDX44]], align 8
12694 // CHECK15-NEXT:    [[ADD45:%.*]] = fadd double [[TMP23]], 1.000000e+00
12695 // CHECK15-NEXT:    store double [[ADD45]], double* [[ARRAYIDX44]], align 8
12696 // CHECK15-NEXT:    [[TMP24:%.*]] = mul nsw i32 1, [[TMP2]]
12697 // CHECK15-NEXT:    [[ARRAYIDX46:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP24]]
12698 // CHECK15-NEXT:    [[ARRAYIDX47:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX46]], i32 3
12699 // CHECK15-NEXT:    [[TMP25:%.*]] = load double, double* [[ARRAYIDX47]], align 8
12700 // CHECK15-NEXT:    [[ADD48:%.*]] = fadd double [[TMP25]], 1.000000e+00
12701 // CHECK15-NEXT:    store double [[ADD48]], double* [[ARRAYIDX47]], align 8
12702 // CHECK15-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0
12703 // CHECK15-NEXT:    [[TMP26:%.*]] = load i64, i64* [[X]], align 4
12704 // CHECK15-NEXT:    [[ADD49:%.*]] = add nsw i64 [[TMP26]], 1
12705 // CHECK15-NEXT:    store i64 [[ADD49]], i64* [[X]], align 4
12706 // CHECK15-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1
12707 // CHECK15-NEXT:    [[TMP27:%.*]] = load i8, i8* [[Y]], align 4
12708 // CHECK15-NEXT:    [[CONV50:%.*]] = sext i8 [[TMP27]] to i32
12709 // CHECK15-NEXT:    [[ADD51:%.*]] = add nsw i32 [[CONV50]], 1
12710 // CHECK15-NEXT:    [[CONV52:%.*]] = trunc i32 [[ADD51]] to i8
12711 // CHECK15-NEXT:    store i8 [[CONV52]], i8* [[Y]], align 4
12712 // CHECK15-NEXT:    br label [[FOR_INC53:%.*]]
12713 // CHECK15:       for.inc53:
12714 // CHECK15-NEXT:    [[TMP28:%.*]] = load i32, i32* [[I31]], align 4
12715 // CHECK15-NEXT:    [[INC54:%.*]] = add nsw i32 [[TMP28]], 1
12716 // CHECK15-NEXT:    store i32 [[INC54]], i32* [[I31]], align 4
12717 // CHECK15-NEXT:    br label [[FOR_COND32]], !llvm.loop [[LOOP8:![0-9]+]]
12718 // CHECK15:       for.end55:
12719 // CHECK15-NEXT:    [[TMP29:%.*]] = load i32, i32* [[A]], align 4
12720 // CHECK15-NEXT:    [[TMP30:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
12721 // CHECK15-NEXT:    call void @llvm.stackrestore(i8* [[TMP30]])
12722 // CHECK15-NEXT:    ret i32 [[TMP29]]
12723 //
12724 //
12725 // CHECK15-LABEL: define {{[^@]+}}@_Z3bari
12726 // CHECK15-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
12727 // CHECK15-NEXT:  entry:
12728 // CHECK15-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
12729 // CHECK15-NEXT:    [[A:%.*]] = alloca i32, align 4
12730 // CHECK15-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4
12731 // CHECK15-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
12732 // CHECK15-NEXT:    store i32 0, i32* [[A]], align 4
12733 // CHECK15-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
12734 // CHECK15-NEXT:    [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]])
12735 // CHECK15-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
12736 // CHECK15-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
12737 // CHECK15-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
12738 // CHECK15-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
12739 // CHECK15-NEXT:    [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]])
12740 // CHECK15-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
12741 // CHECK15-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
12742 // CHECK15-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
12743 // CHECK15-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
12744 // CHECK15-NEXT:    [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]])
12745 // CHECK15-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
12746 // CHECK15-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
12747 // CHECK15-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
12748 // CHECK15-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
12749 // CHECK15-NEXT:    [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]])
12750 // CHECK15-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
12751 // CHECK15-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
12752 // CHECK15-NEXT:    store i32 [[ADD6]], i32* [[A]], align 4
12753 // CHECK15-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
12754 // CHECK15-NEXT:    ret i32 [[TMP8]]
12755 //
12756 //
12757 // CHECK15-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
12758 // CHECK15-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 {
12759 // CHECK15-NEXT:  entry:
12760 // CHECK15-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
12761 // CHECK15-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
12762 // CHECK15-NEXT:    [[B:%.*]] = alloca i32, align 4
12763 // CHECK15-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 4
12764 // CHECK15-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 4
12765 // CHECK15-NEXT:    [[I:%.*]] = alloca i32, align 4
12766 // CHECK15-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
12767 // CHECK15-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
12768 // CHECK15-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
12769 // CHECK15-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
12770 // CHECK15-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
12771 // CHECK15-NEXT:    store i32 [[ADD]], i32* [[B]], align 4
12772 // CHECK15-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
12773 // CHECK15-NEXT:    [[TMP2:%.*]] = call i8* @llvm.stacksave()
12774 // CHECK15-NEXT:    store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4
12775 // CHECK15-NEXT:    [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]
12776 // CHECK15-NEXT:    [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2
12777 // CHECK15-NEXT:    store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
12778 // CHECK15-NEXT:    store i32 0, i32* [[I]], align 4
12779 // CHECK15-NEXT:    br label [[FOR_COND:%.*]]
12780 // CHECK15:       for.cond:
12781 // CHECK15-NEXT:    [[TMP4:%.*]] = load i32, i32* [[I]], align 4
12782 // CHECK15-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP4]], 10
12783 // CHECK15-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
12784 // CHECK15:       for.body:
12785 // CHECK15-NEXT:    [[TMP5:%.*]] = load i32, i32* [[B]], align 4
12786 // CHECK15-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP5]] to double
12787 // CHECK15-NEXT:    [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00
12788 // CHECK15-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
12789 // CHECK15-NEXT:    store double [[ADD2]], double* [[A]], align 4
12790 // CHECK15-NEXT:    [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
12791 // CHECK15-NEXT:    [[TMP6:%.*]] = load double, double* [[A3]], align 4
12792 // CHECK15-NEXT:    [[INC:%.*]] = fadd double [[TMP6]], 1.000000e+00
12793 // CHECK15-NEXT:    store double [[INC]], double* [[A3]], align 4
12794 // CHECK15-NEXT:    [[CONV4:%.*]] = fptosi double [[INC]] to i16
12795 // CHECK15-NEXT:    [[TMP7:%.*]] = mul nsw i32 1, [[TMP1]]
12796 // CHECK15-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP7]]
12797 // CHECK15-NEXT:    [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
12798 // CHECK15-NEXT:    store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2
12799 // CHECK15-NEXT:    br label [[FOR_INC:%.*]]
12800 // CHECK15:       for.inc:
12801 // CHECK15-NEXT:    [[TMP8:%.*]] = load i32, i32* [[I]], align 4
12802 // CHECK15-NEXT:    [[INC6:%.*]] = add nsw i32 [[TMP8]], 1
12803 // CHECK15-NEXT:    store i32 [[INC6]], i32* [[I]], align 4
12804 // CHECK15-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]
12805 // CHECK15:       for.end:
12806 // CHECK15-NEXT:    [[TMP9:%.*]] = mul nsw i32 1, [[TMP1]]
12807 // CHECK15-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP9]]
12808 // CHECK15-NEXT:    [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX7]], i32 1
12809 // CHECK15-NEXT:    [[TMP10:%.*]] = load i16, i16* [[ARRAYIDX8]], align 2
12810 // CHECK15-NEXT:    [[CONV9:%.*]] = sext i16 [[TMP10]] to i32
12811 // CHECK15-NEXT:    [[TMP11:%.*]] = load i32, i32* [[B]], align 4
12812 // CHECK15-NEXT:    [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[TMP11]]
12813 // CHECK15-NEXT:    [[TMP12:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
12814 // CHECK15-NEXT:    call void @llvm.stackrestore(i8* [[TMP12]])
12815 // CHECK15-NEXT:    ret i32 [[ADD10]]
12816 //
12817 //
12818 // CHECK15-LABEL: define {{[^@]+}}@_ZL7fstatici
12819 // CHECK15-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
12820 // CHECK15-NEXT:  entry:
12821 // CHECK15-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
12822 // CHECK15-NEXT:    [[A:%.*]] = alloca i32, align 4
12823 // CHECK15-NEXT:    [[AA:%.*]] = alloca i16, align 2
12824 // CHECK15-NEXT:    [[AAA:%.*]] = alloca i8, align 1
12825 // CHECK15-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
12826 // CHECK15-NEXT:    [[I:%.*]] = alloca i32, align 4
12827 // CHECK15-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
12828 // CHECK15-NEXT:    store i32 0, i32* [[A]], align 4
12829 // CHECK15-NEXT:    store i16 0, i16* [[AA]], align 2
12830 // CHECK15-NEXT:    store i8 0, i8* [[AAA]], align 1
12831 // CHECK15-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
12832 // CHECK15-NEXT:    store i32 [[TMP0]], i32* [[I]], align 4
12833 // CHECK15-NEXT:    br label [[FOR_COND:%.*]]
12834 // CHECK15:       for.cond:
12835 // CHECK15-NEXT:    [[TMP1:%.*]] = load i32, i32* [[I]], align 4
12836 // CHECK15-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
12837 // CHECK15-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP1]], [[TMP2]]
12838 // CHECK15-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
12839 // CHECK15:       for.body:
12840 // CHECK15-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
12841 // CHECK15-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP3]], 1
12842 // CHECK15-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
12843 // CHECK15-NEXT:    [[TMP4:%.*]] = load i16, i16* [[AA]], align 2
12844 // CHECK15-NEXT:    [[CONV:%.*]] = sext i16 [[TMP4]] to i32
12845 // CHECK15-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
12846 // CHECK15-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
12847 // CHECK15-NEXT:    store i16 [[CONV2]], i16* [[AA]], align 2
12848 // CHECK15-NEXT:    [[TMP5:%.*]] = load i8, i8* [[AAA]], align 1
12849 // CHECK15-NEXT:    [[CONV3:%.*]] = sext i8 [[TMP5]] to i32
12850 // CHECK15-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
12851 // CHECK15-NEXT:    [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8
12852 // CHECK15-NEXT:    store i8 [[CONV5]], i8* [[AAA]], align 1
12853 // CHECK15-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2
12854 // CHECK15-NEXT:    [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
12855 // CHECK15-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP6]], 1
12856 // CHECK15-NEXT:    store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4
12857 // CHECK15-NEXT:    br label [[FOR_INC:%.*]]
12858 // CHECK15:       for.inc:
12859 // CHECK15-NEXT:    [[TMP7:%.*]] = load i32, i32* [[I]], align 4
12860 // CHECK15-NEXT:    [[INC:%.*]] = add nsw i32 [[TMP7]], 1
12861 // CHECK15-NEXT:    store i32 [[INC]], i32* [[I]], align 4
12862 // CHECK15-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]
12863 // CHECK15:       for.end:
12864 // CHECK15-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
12865 // CHECK15-NEXT:    ret i32 [[TMP8]]
12866 //
12867 //
12868 // CHECK15-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
12869 // CHECK15-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat {
12870 // CHECK15-NEXT:  entry:
12871 // CHECK15-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
12872 // CHECK15-NEXT:    [[A:%.*]] = alloca i32, align 4
12873 // CHECK15-NEXT:    [[AA:%.*]] = alloca i16, align 2
12874 // CHECK15-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
12875 // CHECK15-NEXT:    [[I:%.*]] = alloca i32, align 4
12876 // CHECK15-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
12877 // CHECK15-NEXT:    store i32 0, i32* [[A]], align 4
12878 // CHECK15-NEXT:    store i16 0, i16* [[AA]], align 2
12879 // CHECK15-NEXT:    store i32 0, i32* [[I]], align 4
12880 // CHECK15-NEXT:    br label [[FOR_COND:%.*]]
12881 // CHECK15:       for.cond:
12882 // CHECK15-NEXT:    [[TMP0:%.*]] = load i32, i32* [[I]], align 4
12883 // CHECK15-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10
12884 // CHECK15-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
12885 // CHECK15:       for.body:
12886 // CHECK15-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
12887 // CHECK15-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
12888 // CHECK15-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
12889 // CHECK15-NEXT:    [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
12890 // CHECK15-NEXT:    [[CONV:%.*]] = sext i16 [[TMP2]] to i32
12891 // CHECK15-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
12892 // CHECK15-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
12893 // CHECK15-NEXT:    store i16 [[CONV2]], i16* [[AA]], align 2
12894 // CHECK15-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2
12895 // CHECK15-NEXT:    [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
12896 // CHECK15-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1
12897 // CHECK15-NEXT:    store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4
12898 // CHECK15-NEXT:    br label [[FOR_INC:%.*]]
12899 // CHECK15:       for.inc:
12900 // CHECK15-NEXT:    [[TMP4:%.*]] = load i32, i32* [[I]], align 4
12901 // CHECK15-NEXT:    [[INC:%.*]] = add nsw i32 [[TMP4]], 1
12902 // CHECK15-NEXT:    store i32 [[INC]], i32* [[I]], align 4
12903 // CHECK15-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]
12904 // CHECK15:       for.end:
12905 // CHECK15-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
12906 // CHECK15-NEXT:    ret i32 [[TMP5]]
12907 //
12908 //
12909 // CHECK16-LABEL: define {{[^@]+}}@_Z3fooi
12910 // CHECK16-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] {
12911 // CHECK16-NEXT:  entry:
12912 // CHECK16-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
12913 // CHECK16-NEXT:    [[A:%.*]] = alloca i32, align 4
12914 // CHECK16-NEXT:    [[AA:%.*]] = alloca i16, align 2
12915 // CHECK16-NEXT:    [[B:%.*]] = alloca [10 x float], align 4
12916 // CHECK16-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 4
12917 // CHECK16-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 4
12918 // CHECK16-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 8
12919 // CHECK16-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i32, align 4
12920 // CHECK16-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4
12921 // CHECK16-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
12922 // CHECK16-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
12923 // CHECK16-NEXT:    [[I:%.*]] = alloca i32, align 4
12924 // CHECK16-NEXT:    [[I3:%.*]] = alloca i32, align 4
12925 // CHECK16-NEXT:    [[I10:%.*]] = alloca i32, align 4
12926 // CHECK16-NEXT:    [[I19:%.*]] = alloca i32, align 4
12927 // CHECK16-NEXT:    [[DOTCAPTURE_EXPR_30:%.*]] = alloca i32, align 4
12928 // CHECK16-NEXT:    [[I31:%.*]] = alloca i32, align 4
12929 // CHECK16-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
12930 // CHECK16-NEXT:    store i32 0, i32* [[A]], align 4
12931 // CHECK16-NEXT:    store i16 0, i16* [[AA]], align 2
12932 // CHECK16-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
12933 // CHECK16-NEXT:    [[TMP1:%.*]] = call i8* @llvm.stacksave()
12934 // CHECK16-NEXT:    store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4
12935 // CHECK16-NEXT:    [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4
12936 // CHECK16-NEXT:    store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4
12937 // CHECK16-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
12938 // CHECK16-NEXT:    [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]]
12939 // CHECK16-NEXT:    [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8
12940 // CHECK16-NEXT:    store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4
12941 // CHECK16-NEXT:    [[TMP4:%.*]] = load i32, i32* [[A]], align 4
12942 // CHECK16-NEXT:    store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4
12943 // CHECK16-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
12944 // CHECK16-NEXT:    store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_2]], align 4
12945 // CHECK16-NEXT:    store i32 0, i32* [[I]], align 4
12946 // CHECK16-NEXT:    br label [[FOR_COND:%.*]]
12947 // CHECK16:       for.cond:
12948 // CHECK16-NEXT:    [[TMP6:%.*]] = load i32, i32* [[I]], align 4
12949 // CHECK16-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP6]], 10
12950 // CHECK16-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
12951 // CHECK16:       for.body:
12952 // CHECK16-NEXT:    br label [[FOR_INC:%.*]]
12953 // CHECK16:       for.inc:
12954 // CHECK16-NEXT:    [[TMP7:%.*]] = load i32, i32* [[I]], align 4
12955 // CHECK16-NEXT:    [[INC:%.*]] = add nsw i32 [[TMP7]], 1
12956 // CHECK16-NEXT:    store i32 [[INC]], i32* [[I]], align 4
12957 // CHECK16-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]
12958 // CHECK16:       for.end:
12959 // CHECK16-NEXT:    store i32 0, i32* [[I3]], align 4
12960 // CHECK16-NEXT:    br label [[FOR_COND4:%.*]]
12961 // CHECK16:       for.cond4:
12962 // CHECK16-NEXT:    [[TMP8:%.*]] = load i32, i32* [[I3]], align 4
12963 // CHECK16-NEXT:    [[CMP5:%.*]] = icmp slt i32 [[TMP8]], 10
12964 // CHECK16-NEXT:    br i1 [[CMP5]], label [[FOR_BODY6:%.*]], label [[FOR_END9:%.*]]
12965 // CHECK16:       for.body6:
12966 // CHECK16-NEXT:    [[TMP9:%.*]] = load i32, i32* [[A]], align 4
12967 // CHECK16-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP9]], 1
12968 // CHECK16-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
12969 // CHECK16-NEXT:    br label [[FOR_INC7:%.*]]
12970 // CHECK16:       for.inc7:
12971 // CHECK16-NEXT:    [[TMP10:%.*]] = load i32, i32* [[I3]], align 4
12972 // CHECK16-NEXT:    [[INC8:%.*]] = add nsw i32 [[TMP10]], 1
12973 // CHECK16-NEXT:    store i32 [[INC8]], i32* [[I3]], align 4
12974 // CHECK16-NEXT:    br label [[FOR_COND4]], !llvm.loop [[LOOP5:![0-9]+]]
12975 // CHECK16:       for.end9:
12976 // CHECK16-NEXT:    store i32 0, i32* [[I10]], align 4
12977 // CHECK16-NEXT:    br label [[FOR_COND11:%.*]]
12978 // CHECK16:       for.cond11:
12979 // CHECK16-NEXT:    [[TMP11:%.*]] = load i32, i32* [[I10]], align 4
12980 // CHECK16-NEXT:    [[CMP12:%.*]] = icmp slt i32 [[TMP11]], 10
12981 // CHECK16-NEXT:    br i1 [[CMP12]], label [[FOR_BODY13:%.*]], label [[FOR_END18:%.*]]
12982 // CHECK16:       for.body13:
12983 // CHECK16-NEXT:    [[TMP12:%.*]] = load i16, i16* [[AA]], align 2
12984 // CHECK16-NEXT:    [[CONV:%.*]] = sext i16 [[TMP12]] to i32
12985 // CHECK16-NEXT:    [[ADD14:%.*]] = add nsw i32 [[CONV]], 1
12986 // CHECK16-NEXT:    [[CONV15:%.*]] = trunc i32 [[ADD14]] to i16
12987 // CHECK16-NEXT:    store i16 [[CONV15]], i16* [[AA]], align 2
12988 // CHECK16-NEXT:    br label [[FOR_INC16:%.*]]
12989 // CHECK16:       for.inc16:
12990 // CHECK16-NEXT:    [[TMP13:%.*]] = load i32, i32* [[I10]], align 4
12991 // CHECK16-NEXT:    [[INC17:%.*]] = add nsw i32 [[TMP13]], 1
12992 // CHECK16-NEXT:    store i32 [[INC17]], i32* [[I10]], align 4
12993 // CHECK16-NEXT:    br label [[FOR_COND11]], !llvm.loop [[LOOP6:![0-9]+]]
12994 // CHECK16:       for.end18:
12995 // CHECK16-NEXT:    store i32 0, i32* [[I19]], align 4
12996 // CHECK16-NEXT:    br label [[FOR_COND20:%.*]]
12997 // CHECK16:       for.cond20:
12998 // CHECK16-NEXT:    [[TMP14:%.*]] = load i32, i32* [[I19]], align 4
12999 // CHECK16-NEXT:    [[CMP21:%.*]] = icmp slt i32 [[TMP14]], 10
13000 // CHECK16-NEXT:    br i1 [[CMP21]], label [[FOR_BODY22:%.*]], label [[FOR_END29:%.*]]
13001 // CHECK16:       for.body22:
13002 // CHECK16-NEXT:    [[TMP15:%.*]] = load i32, i32* [[A]], align 4
13003 // CHECK16-NEXT:    [[ADD23:%.*]] = add nsw i32 [[TMP15]], 1
13004 // CHECK16-NEXT:    store i32 [[ADD23]], i32* [[A]], align 4
13005 // CHECK16-NEXT:    [[TMP16:%.*]] = load i16, i16* [[AA]], align 2
13006 // CHECK16-NEXT:    [[CONV24:%.*]] = sext i16 [[TMP16]] to i32
13007 // CHECK16-NEXT:    [[ADD25:%.*]] = add nsw i32 [[CONV24]], 1
13008 // CHECK16-NEXT:    [[CONV26:%.*]] = trunc i32 [[ADD25]] to i16
13009 // CHECK16-NEXT:    store i16 [[CONV26]], i16* [[AA]], align 2
13010 // CHECK16-NEXT:    br label [[FOR_INC27:%.*]]
13011 // CHECK16:       for.inc27:
13012 // CHECK16-NEXT:    [[TMP17:%.*]] = load i32, i32* [[I19]], align 4
13013 // CHECK16-NEXT:    [[INC28:%.*]] = add nsw i32 [[TMP17]], 1
13014 // CHECK16-NEXT:    store i32 [[INC28]], i32* [[I19]], align 4
13015 // CHECK16-NEXT:    br label [[FOR_COND20]], !llvm.loop [[LOOP7:![0-9]+]]
13016 // CHECK16:       for.end29:
13017 // CHECK16-NEXT:    [[TMP18:%.*]] = load i32, i32* [[N_ADDR]], align 4
13018 // CHECK16-NEXT:    store i32 [[TMP18]], i32* [[DOTCAPTURE_EXPR_30]], align 4
13019 // CHECK16-NEXT:    store i32 0, i32* [[I31]], align 4
13020 // CHECK16-NEXT:    br label [[FOR_COND32:%.*]]
13021 // CHECK16:       for.cond32:
13022 // CHECK16-NEXT:    [[TMP19:%.*]] = load i32, i32* [[I31]], align 4
13023 // CHECK16-NEXT:    [[CMP33:%.*]] = icmp slt i32 [[TMP19]], 10
13024 // CHECK16-NEXT:    br i1 [[CMP33]], label [[FOR_BODY34:%.*]], label [[FOR_END55:%.*]]
13025 // CHECK16:       for.body34:
13026 // CHECK16-NEXT:    [[TMP20:%.*]] = load i32, i32* [[A]], align 4
13027 // CHECK16-NEXT:    [[ADD35:%.*]] = add nsw i32 [[TMP20]], 1
13028 // CHECK16-NEXT:    store i32 [[ADD35]], i32* [[A]], align 4
13029 // CHECK16-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2
13030 // CHECK16-NEXT:    [[TMP21:%.*]] = load float, float* [[ARRAYIDX]], align 4
13031 // CHECK16-NEXT:    [[CONV36:%.*]] = fpext float [[TMP21]] to double
13032 // CHECK16-NEXT:    [[ADD37:%.*]] = fadd double [[CONV36]], 1.000000e+00
13033 // CHECK16-NEXT:    [[CONV38:%.*]] = fptrunc double [[ADD37]] to float
13034 // CHECK16-NEXT:    store float [[CONV38]], float* [[ARRAYIDX]], align 4
13035 // CHECK16-NEXT:    [[ARRAYIDX39:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3
13036 // CHECK16-NEXT:    [[TMP22:%.*]] = load float, float* [[ARRAYIDX39]], align 4
13037 // CHECK16-NEXT:    [[CONV40:%.*]] = fpext float [[TMP22]] to double
13038 // CHECK16-NEXT:    [[ADD41:%.*]] = fadd double [[CONV40]], 1.000000e+00
13039 // CHECK16-NEXT:    [[CONV42:%.*]] = fptrunc double [[ADD41]] to float
13040 // CHECK16-NEXT:    store float [[CONV42]], float* [[ARRAYIDX39]], align 4
13041 // CHECK16-NEXT:    [[ARRAYIDX43:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1
13042 // CHECK16-NEXT:    [[ARRAYIDX44:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX43]], i32 0, i32 2
13043 // CHECK16-NEXT:    [[TMP23:%.*]] = load double, double* [[ARRAYIDX44]], align 8
13044 // CHECK16-NEXT:    [[ADD45:%.*]] = fadd double [[TMP23]], 1.000000e+00
13045 // CHECK16-NEXT:    store double [[ADD45]], double* [[ARRAYIDX44]], align 8
13046 // CHECK16-NEXT:    [[TMP24:%.*]] = mul nsw i32 1, [[TMP2]]
13047 // CHECK16-NEXT:    [[ARRAYIDX46:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP24]]
13048 // CHECK16-NEXT:    [[ARRAYIDX47:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX46]], i32 3
13049 // CHECK16-NEXT:    [[TMP25:%.*]] = load double, double* [[ARRAYIDX47]], align 8
13050 // CHECK16-NEXT:    [[ADD48:%.*]] = fadd double [[TMP25]], 1.000000e+00
13051 // CHECK16-NEXT:    store double [[ADD48]], double* [[ARRAYIDX47]], align 8
13052 // CHECK16-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0
13053 // CHECK16-NEXT:    [[TMP26:%.*]] = load i64, i64* [[X]], align 4
13054 // CHECK16-NEXT:    [[ADD49:%.*]] = add nsw i64 [[TMP26]], 1
13055 // CHECK16-NEXT:    store i64 [[ADD49]], i64* [[X]], align 4
13056 // CHECK16-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1
13057 // CHECK16-NEXT:    [[TMP27:%.*]] = load i8, i8* [[Y]], align 4
13058 // CHECK16-NEXT:    [[CONV50:%.*]] = sext i8 [[TMP27]] to i32
13059 // CHECK16-NEXT:    [[ADD51:%.*]] = add nsw i32 [[CONV50]], 1
13060 // CHECK16-NEXT:    [[CONV52:%.*]] = trunc i32 [[ADD51]] to i8
13061 // CHECK16-NEXT:    store i8 [[CONV52]], i8* [[Y]], align 4
13062 // CHECK16-NEXT:    br label [[FOR_INC53:%.*]]
13063 // CHECK16:       for.inc53:
13064 // CHECK16-NEXT:    [[TMP28:%.*]] = load i32, i32* [[I31]], align 4
13065 // CHECK16-NEXT:    [[INC54:%.*]] = add nsw i32 [[TMP28]], 1
13066 // CHECK16-NEXT:    store i32 [[INC54]], i32* [[I31]], align 4
13067 // CHECK16-NEXT:    br label [[FOR_COND32]], !llvm.loop [[LOOP8:![0-9]+]]
13068 // CHECK16:       for.end55:
13069 // CHECK16-NEXT:    [[TMP29:%.*]] = load i32, i32* [[A]], align 4
13070 // CHECK16-NEXT:    [[TMP30:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
13071 // CHECK16-NEXT:    call void @llvm.stackrestore(i8* [[TMP30]])
13072 // CHECK16-NEXT:    ret i32 [[TMP29]]
13073 //
13074 //
13075 // CHECK16-LABEL: define {{[^@]+}}@_Z3bari
13076 // CHECK16-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
13077 // CHECK16-NEXT:  entry:
13078 // CHECK16-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
13079 // CHECK16-NEXT:    [[A:%.*]] = alloca i32, align 4
13080 // CHECK16-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4
13081 // CHECK16-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
13082 // CHECK16-NEXT:    store i32 0, i32* [[A]], align 4
13083 // CHECK16-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
13084 // CHECK16-NEXT:    [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]])
13085 // CHECK16-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
13086 // CHECK16-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
13087 // CHECK16-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
13088 // CHECK16-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
13089 // CHECK16-NEXT:    [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]])
13090 // CHECK16-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
13091 // CHECK16-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
13092 // CHECK16-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
13093 // CHECK16-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
13094 // CHECK16-NEXT:    [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]])
13095 // CHECK16-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
13096 // CHECK16-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
13097 // CHECK16-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
13098 // CHECK16-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
13099 // CHECK16-NEXT:    [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]])
13100 // CHECK16-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
13101 // CHECK16-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
13102 // CHECK16-NEXT:    store i32 [[ADD6]], i32* [[A]], align 4
13103 // CHECK16-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
13104 // CHECK16-NEXT:    ret i32 [[TMP8]]
13105 //
13106 //
13107 // CHECK16-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
13108 // CHECK16-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 {
13109 // CHECK16-NEXT:  entry:
13110 // CHECK16-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
13111 // CHECK16-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
13112 // CHECK16-NEXT:    [[B:%.*]] = alloca i32, align 4
13113 // CHECK16-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 4
13114 // CHECK16-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 4
13115 // CHECK16-NEXT:    [[I:%.*]] = alloca i32, align 4
13116 // CHECK16-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
13117 // CHECK16-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
13118 // CHECK16-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
13119 // CHECK16-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
13120 // CHECK16-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
13121 // CHECK16-NEXT:    store i32 [[ADD]], i32* [[B]], align 4
13122 // CHECK16-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
13123 // CHECK16-NEXT:    [[TMP2:%.*]] = call i8* @llvm.stacksave()
13124 // CHECK16-NEXT:    store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4
13125 // CHECK16-NEXT:    [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]
13126 // CHECK16-NEXT:    [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2
13127 // CHECK16-NEXT:    store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
13128 // CHECK16-NEXT:    store i32 0, i32* [[I]], align 4
13129 // CHECK16-NEXT:    br label [[FOR_COND:%.*]]
13130 // CHECK16:       for.cond:
13131 // CHECK16-NEXT:    [[TMP4:%.*]] = load i32, i32* [[I]], align 4
13132 // CHECK16-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP4]], 10
13133 // CHECK16-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
13134 // CHECK16:       for.body:
13135 // CHECK16-NEXT:    [[TMP5:%.*]] = load i32, i32* [[B]], align 4
13136 // CHECK16-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP5]] to double
13137 // CHECK16-NEXT:    [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00
13138 // CHECK16-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
13139 // CHECK16-NEXT:    store double [[ADD2]], double* [[A]], align 4
13140 // CHECK16-NEXT:    [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
13141 // CHECK16-NEXT:    [[TMP6:%.*]] = load double, double* [[A3]], align 4
13142 // CHECK16-NEXT:    [[INC:%.*]] = fadd double [[TMP6]], 1.000000e+00
13143 // CHECK16-NEXT:    store double [[INC]], double* [[A3]], align 4
13144 // CHECK16-NEXT:    [[CONV4:%.*]] = fptosi double [[INC]] to i16
13145 // CHECK16-NEXT:    [[TMP7:%.*]] = mul nsw i32 1, [[TMP1]]
13146 // CHECK16-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP7]]
13147 // CHECK16-NEXT:    [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
13148 // CHECK16-NEXT:    store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2
13149 // CHECK16-NEXT:    br label [[FOR_INC:%.*]]
13150 // CHECK16:       for.inc:
13151 // CHECK16-NEXT:    [[TMP8:%.*]] = load i32, i32* [[I]], align 4
13152 // CHECK16-NEXT:    [[INC6:%.*]] = add nsw i32 [[TMP8]], 1
13153 // CHECK16-NEXT:    store i32 [[INC6]], i32* [[I]], align 4
13154 // CHECK16-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]
13155 // CHECK16:       for.end:
13156 // CHECK16-NEXT:    [[TMP9:%.*]] = mul nsw i32 1, [[TMP1]]
13157 // CHECK16-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP9]]
13158 // CHECK16-NEXT:    [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX7]], i32 1
13159 // CHECK16-NEXT:    [[TMP10:%.*]] = load i16, i16* [[ARRAYIDX8]], align 2
13160 // CHECK16-NEXT:    [[CONV9:%.*]] = sext i16 [[TMP10]] to i32
13161 // CHECK16-NEXT:    [[TMP11:%.*]] = load i32, i32* [[B]], align 4
13162 // CHECK16-NEXT:    [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[TMP11]]
13163 // CHECK16-NEXT:    [[TMP12:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
13164 // CHECK16-NEXT:    call void @llvm.stackrestore(i8* [[TMP12]])
13165 // CHECK16-NEXT:    ret i32 [[ADD10]]
13166 //
13167 //
13168 // CHECK16-LABEL: define {{[^@]+}}@_ZL7fstatici
13169 // CHECK16-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
13170 // CHECK16-NEXT:  entry:
13171 // CHECK16-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
13172 // CHECK16-NEXT:    [[A:%.*]] = alloca i32, align 4
13173 // CHECK16-NEXT:    [[AA:%.*]] = alloca i16, align 2
13174 // CHECK16-NEXT:    [[AAA:%.*]] = alloca i8, align 1
13175 // CHECK16-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
13176 // CHECK16-NEXT:    [[I:%.*]] = alloca i32, align 4
13177 // CHECK16-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
13178 // CHECK16-NEXT:    store i32 0, i32* [[A]], align 4
13179 // CHECK16-NEXT:    store i16 0, i16* [[AA]], align 2
13180 // CHECK16-NEXT:    store i8 0, i8* [[AAA]], align 1
13181 // CHECK16-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
13182 // CHECK16-NEXT:    store i32 [[TMP0]], i32* [[I]], align 4
13183 // CHECK16-NEXT:    br label [[FOR_COND:%.*]]
13184 // CHECK16:       for.cond:
13185 // CHECK16-NEXT:    [[TMP1:%.*]] = load i32, i32* [[I]], align 4
13186 // CHECK16-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
13187 // CHECK16-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP1]], [[TMP2]]
13188 // CHECK16-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
13189 // CHECK16:       for.body:
13190 // CHECK16-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
13191 // CHECK16-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP3]], 1
13192 // CHECK16-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
13193 // CHECK16-NEXT:    [[TMP4:%.*]] = load i16, i16* [[AA]], align 2
13194 // CHECK16-NEXT:    [[CONV:%.*]] = sext i16 [[TMP4]] to i32
13195 // CHECK16-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
13196 // CHECK16-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
13197 // CHECK16-NEXT:    store i16 [[CONV2]], i16* [[AA]], align 2
13198 // CHECK16-NEXT:    [[TMP5:%.*]] = load i8, i8* [[AAA]], align 1
13199 // CHECK16-NEXT:    [[CONV3:%.*]] = sext i8 [[TMP5]] to i32
13200 // CHECK16-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
13201 // CHECK16-NEXT:    [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8
13202 // CHECK16-NEXT:    store i8 [[CONV5]], i8* [[AAA]], align 1
13203 // CHECK16-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2
13204 // CHECK16-NEXT:    [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
13205 // CHECK16-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP6]], 1
13206 // CHECK16-NEXT:    store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4
13207 // CHECK16-NEXT:    br label [[FOR_INC:%.*]]
13208 // CHECK16:       for.inc:
13209 // CHECK16-NEXT:    [[TMP7:%.*]] = load i32, i32* [[I]], align 4
13210 // CHECK16-NEXT:    [[INC:%.*]] = add nsw i32 [[TMP7]], 1
13211 // CHECK16-NEXT:    store i32 [[INC]], i32* [[I]], align 4
13212 // CHECK16-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]
13213 // CHECK16:       for.end:
13214 // CHECK16-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
13215 // CHECK16-NEXT:    ret i32 [[TMP8]]
13216 //
13217 //
13218 // CHECK16-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
13219 // CHECK16-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat {
13220 // CHECK16-NEXT:  entry:
13221 // CHECK16-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
13222 // CHECK16-NEXT:    [[A:%.*]] = alloca i32, align 4
13223 // CHECK16-NEXT:    [[AA:%.*]] = alloca i16, align 2
13224 // CHECK16-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
13225 // CHECK16-NEXT:    [[I:%.*]] = alloca i32, align 4
13226 // CHECK16-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
13227 // CHECK16-NEXT:    store i32 0, i32* [[A]], align 4
13228 // CHECK16-NEXT:    store i16 0, i16* [[AA]], align 2
13229 // CHECK16-NEXT:    store i32 0, i32* [[I]], align 4
13230 // CHECK16-NEXT:    br label [[FOR_COND:%.*]]
13231 // CHECK16:       for.cond:
13232 // CHECK16-NEXT:    [[TMP0:%.*]] = load i32, i32* [[I]], align 4
13233 // CHECK16-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10
13234 // CHECK16-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
13235 // CHECK16:       for.body:
13236 // CHECK16-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
13237 // CHECK16-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
13238 // CHECK16-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
13239 // CHECK16-NEXT:    [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
13240 // CHECK16-NEXT:    [[CONV:%.*]] = sext i16 [[TMP2]] to i32
13241 // CHECK16-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
13242 // CHECK16-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
13243 // CHECK16-NEXT:    store i16 [[CONV2]], i16* [[AA]], align 2
13244 // CHECK16-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2
13245 // CHECK16-NEXT:    [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
13246 // CHECK16-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1
13247 // CHECK16-NEXT:    store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4
13248 // CHECK16-NEXT:    br label [[FOR_INC:%.*]]
13249 // CHECK16:       for.inc:
13250 // CHECK16-NEXT:    [[TMP4:%.*]] = load i32, i32* [[I]], align 4
13251 // CHECK16-NEXT:    [[INC:%.*]] = add nsw i32 [[TMP4]], 1
13252 // CHECK16-NEXT:    store i32 [[INC]], i32* [[I]], align 4
13253 // CHECK16-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]
13254 // CHECK16:       for.end:
13255 // CHECK16-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
13256 // CHECK16-NEXT:    ret i32 [[TMP5]]
13257 //
13258 //
13259 // CHECK17-LABEL: define {{[^@]+}}@_Z3fooi
13260 // CHECK17-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] {
13261 // CHECK17-NEXT:  entry:
13262 // CHECK17-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
13263 // CHECK17-NEXT:    [[A:%.*]] = alloca i32, align 4
13264 // CHECK17-NEXT:    [[AA:%.*]] = alloca i16, align 2
13265 // CHECK17-NEXT:    [[B:%.*]] = alloca [10 x float], align 4
13266 // CHECK17-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 8
13267 // CHECK17-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
13268 // CHECK17-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 8
13269 // CHECK17-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i64, align 8
13270 // CHECK17-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8
13271 // CHECK17-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
13272 // CHECK17-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
13273 // CHECK17-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
13274 // CHECK17-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
13275 // CHECK17-NEXT:    [[DOTCAPTURE_EXPR__CASTED4:%.*]] = alloca i64, align 8
13276 // CHECK17-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8
13277 // CHECK17-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8
13278 // CHECK17-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8
13279 // CHECK17-NEXT:    [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4
13280 // CHECK17-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
13281 // CHECK17-NEXT:    [[AA_CASTED7:%.*]] = alloca i64, align 8
13282 // CHECK17-NEXT:    [[DOTOFFLOAD_BASEPTRS9:%.*]] = alloca [1 x i8*], align 8
13283 // CHECK17-NEXT:    [[DOTOFFLOAD_PTRS10:%.*]] = alloca [1 x i8*], align 8
13284 // CHECK17-NEXT:    [[DOTOFFLOAD_MAPPERS11:%.*]] = alloca [1 x i8*], align 8
13285 // CHECK17-NEXT:    [[TMP:%.*]] = alloca i32, align 4
13286 // CHECK17-NEXT:    [[A_CASTED12:%.*]] = alloca i64, align 8
13287 // CHECK17-NEXT:    [[AA_CASTED14:%.*]] = alloca i64, align 8
13288 // CHECK17-NEXT:    [[DOTOFFLOAD_BASEPTRS16:%.*]] = alloca [2 x i8*], align 8
13289 // CHECK17-NEXT:    [[DOTOFFLOAD_PTRS17:%.*]] = alloca [2 x i8*], align 8
13290 // CHECK17-NEXT:    [[DOTOFFLOAD_MAPPERS18:%.*]] = alloca [2 x i8*], align 8
13291 // CHECK17-NEXT:    [[_TMP19:%.*]] = alloca i32, align 4
13292 // CHECK17-NEXT:    [[DOTCAPTURE_EXPR_22:%.*]] = alloca i32, align 4
13293 // CHECK17-NEXT:    [[A_CASTED23:%.*]] = alloca i64, align 8
13294 // CHECK17-NEXT:    [[DOTCAPTURE_EXPR__CASTED25:%.*]] = alloca i64, align 8
13295 // CHECK17-NEXT:    [[DOTOFFLOAD_BASEPTRS29:%.*]] = alloca [10 x i8*], align 8
13296 // CHECK17-NEXT:    [[DOTOFFLOAD_PTRS30:%.*]] = alloca [10 x i8*], align 8
13297 // CHECK17-NEXT:    [[DOTOFFLOAD_MAPPERS31:%.*]] = alloca [10 x i8*], align 8
13298 // CHECK17-NEXT:    [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 8
13299 // CHECK17-NEXT:    [[_TMP32:%.*]] = alloca i32, align 4
13300 // CHECK17-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]])
13301 // CHECK17-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
13302 // CHECK17-NEXT:    store i32 0, i32* [[A]], align 4
13303 // CHECK17-NEXT:    store i16 0, i16* [[AA]], align 2
13304 // CHECK17-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
13305 // CHECK17-NEXT:    [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
13306 // CHECK17-NEXT:    [[TMP3:%.*]] = call i8* @llvm.stacksave()
13307 // CHECK17-NEXT:    store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8
13308 // CHECK17-NEXT:    [[VLA:%.*]] = alloca float, i64 [[TMP2]], align 4
13309 // CHECK17-NEXT:    store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8
13310 // CHECK17-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
13311 // CHECK17-NEXT:    [[TMP5:%.*]] = zext i32 [[TMP4]] to i64
13312 // CHECK17-NEXT:    [[TMP6:%.*]] = mul nuw i64 5, [[TMP5]]
13313 // CHECK17-NEXT:    [[VLA1:%.*]] = alloca double, i64 [[TMP6]], align 8
13314 // CHECK17-NEXT:    store i64 [[TMP5]], i64* [[__VLA_EXPR1]], align 8
13315 // CHECK17-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
13316 // CHECK17-NEXT:    store i32 [[TMP7]], i32* [[DOTCAPTURE_EXPR_]], align 4
13317 // CHECK17-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
13318 // CHECK17-NEXT:    store i32 [[TMP8]], i32* [[DOTCAPTURE_EXPR_2]], align 4
13319 // CHECK17-NEXT:    [[TMP9:%.*]] = load i16, i16* [[AA]], align 2
13320 // CHECK17-NEXT:    [[CONV:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
13321 // CHECK17-NEXT:    store i16 [[TMP9]], i16* [[CONV]], align 2
13322 // CHECK17-NEXT:    [[TMP10:%.*]] = load i64, i64* [[AA_CASTED]], align 8
13323 // CHECK17-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
13324 // CHECK17-NEXT:    [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
13325 // CHECK17-NEXT:    store i32 [[TMP11]], i32* [[CONV3]], align 4
13326 // CHECK17-NEXT:    [[TMP12:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
13327 // CHECK17-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
13328 // CHECK17-NEXT:    [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED4]] to i32*
13329 // CHECK17-NEXT:    store i32 [[TMP13]], i32* [[CONV5]], align 4
13330 // CHECK17-NEXT:    [[TMP14:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED4]], align 8
13331 // CHECK17-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
13332 // CHECK17-NEXT:    [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i64*
13333 // CHECK17-NEXT:    store i64 [[TMP10]], i64* [[TMP16]], align 8
13334 // CHECK17-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
13335 // CHECK17-NEXT:    [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64*
13336 // CHECK17-NEXT:    store i64 [[TMP10]], i64* [[TMP18]], align 8
13337 // CHECK17-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
13338 // CHECK17-NEXT:    store i8* null, i8** [[TMP19]], align 8
13339 // CHECK17-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
13340 // CHECK17-NEXT:    [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i64*
13341 // CHECK17-NEXT:    store i64 [[TMP12]], i64* [[TMP21]], align 8
13342 // CHECK17-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
13343 // CHECK17-NEXT:    [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i64*
13344 // CHECK17-NEXT:    store i64 [[TMP12]], i64* [[TMP23]], align 8
13345 // CHECK17-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
13346 // CHECK17-NEXT:    store i8* null, i8** [[TMP24]], align 8
13347 // CHECK17-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
13348 // CHECK17-NEXT:    [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i64*
13349 // CHECK17-NEXT:    store i64 [[TMP14]], i64* [[TMP26]], align 8
13350 // CHECK17-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
13351 // CHECK17-NEXT:    [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i64*
13352 // CHECK17-NEXT:    store i64 [[TMP14]], i64* [[TMP28]], align 8
13353 // CHECK17-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
13354 // CHECK17-NEXT:    store i8* null, i8** [[TMP29]], align 8
13355 // CHECK17-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
13356 // CHECK17-NEXT:    [[TMP31:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
13357 // CHECK17-NEXT:    [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 0
13358 // CHECK17-NEXT:    [[TMP33:%.*]] = load i16, i16* [[AA]], align 2
13359 // CHECK17-NEXT:    store i16 [[TMP33]], i16* [[TMP32]], align 4
13360 // CHECK17-NEXT:    [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 1
13361 // CHECK17-NEXT:    [[TMP35:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
13362 // CHECK17-NEXT:    store i32 [[TMP35]], i32* [[TMP34]], align 4
13363 // CHECK17-NEXT:    [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 2
13364 // CHECK17-NEXT:    [[TMP37:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
13365 // CHECK17-NEXT:    store i32 [[TMP37]], i32* [[TMP36]], align 4
13366 // CHECK17-NEXT:    [[TMP38:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 1, i64 120, i64 12, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1)
13367 // CHECK17-NEXT:    [[TMP39:%.*]] = bitcast i8* [[TMP38]] to %struct.kmp_task_t_with_privates*
13368 // CHECK17-NEXT:    [[TMP40:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP39]], i32 0, i32 0
13369 // CHECK17-NEXT:    [[TMP41:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP40]], i32 0, i32 0
13370 // CHECK17-NEXT:    [[TMP42:%.*]] = load i8*, i8** [[TMP41]], align 8
13371 // CHECK17-NEXT:    [[TMP43:%.*]] = bitcast %struct.anon* [[AGG_CAPTURED]] to i8*
13372 // CHECK17-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP42]], i8* align 4 [[TMP43]], i64 12, i1 false)
13373 // CHECK17-NEXT:    [[TMP44:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP39]], i32 0, i32 1
13374 // CHECK17-NEXT:    [[TMP45:%.*]] = bitcast i8* [[TMP42]] to %struct.anon*
13375 // CHECK17-NEXT:    [[TMP46:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 0
13376 // CHECK17-NEXT:    [[TMP47:%.*]] = bitcast [3 x i8*]* [[TMP46]] to i8*
13377 // CHECK17-NEXT:    [[TMP48:%.*]] = bitcast i8** [[TMP30]] to i8*
13378 // CHECK17-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP47]], i8* align 8 [[TMP48]], i64 24, i1 false)
13379 // CHECK17-NEXT:    [[TMP49:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 1
13380 // CHECK17-NEXT:    [[TMP50:%.*]] = bitcast [3 x i8*]* [[TMP49]] to i8*
13381 // CHECK17-NEXT:    [[TMP51:%.*]] = bitcast i8** [[TMP31]] to i8*
13382 // CHECK17-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP50]], i8* align 8 [[TMP51]], i64 24, i1 false)
13383 // CHECK17-NEXT:    [[TMP52:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 2
13384 // CHECK17-NEXT:    [[TMP53:%.*]] = bitcast [3 x i64]* [[TMP52]] to i8*
13385 // CHECK17-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP53]], i8* align 8 bitcast ([3 x i64]* @.offload_sizes to i8*), i64 24, i1 false)
13386 // CHECK17-NEXT:    [[TMP54:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 3
13387 // CHECK17-NEXT:    [[TMP55:%.*]] = load i16, i16* [[AA]], align 2
13388 // CHECK17-NEXT:    store i16 [[TMP55]], i16* [[TMP54]], align 8
13389 // CHECK17-NEXT:    [[TMP56:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i8* [[TMP38]])
13390 // CHECK17-NEXT:    [[TMP57:%.*]] = load i32, i32* [[A]], align 4
13391 // CHECK17-NEXT:    [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32*
13392 // CHECK17-NEXT:    store i32 [[TMP57]], i32* [[CONV6]], align 4
13393 // CHECK17-NEXT:    [[TMP58:%.*]] = load i64, i64* [[A_CASTED]], align 8
13394 // CHECK17-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l107(i64 [[TMP58]]) #[[ATTR3:[0-9]+]]
13395 // CHECK17-NEXT:    [[TMP59:%.*]] = load i16, i16* [[AA]], align 2
13396 // CHECK17-NEXT:    [[CONV8:%.*]] = bitcast i64* [[AA_CASTED7]] to i16*
13397 // CHECK17-NEXT:    store i16 [[TMP59]], i16* [[CONV8]], align 2
13398 // CHECK17-NEXT:    [[TMP60:%.*]] = load i64, i64* [[AA_CASTED7]], align 8
13399 // CHECK17-NEXT:    [[TMP61:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS9]], i32 0, i32 0
13400 // CHECK17-NEXT:    [[TMP62:%.*]] = bitcast i8** [[TMP61]] to i64*
13401 // CHECK17-NEXT:    store i64 [[TMP60]], i64* [[TMP62]], align 8
13402 // CHECK17-NEXT:    [[TMP63:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS10]], i32 0, i32 0
13403 // CHECK17-NEXT:    [[TMP64:%.*]] = bitcast i8** [[TMP63]] to i64*
13404 // CHECK17-NEXT:    store i64 [[TMP60]], i64* [[TMP64]], align 8
13405 // CHECK17-NEXT:    [[TMP65:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS11]], i64 0, i64 0
13406 // CHECK17-NEXT:    store i8* null, i8** [[TMP65]], align 8
13407 // CHECK17-NEXT:    [[TMP66:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS9]], i32 0, i32 0
13408 // CHECK17-NEXT:    [[TMP67:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS10]], i32 0, i32 0
13409 // CHECK17-NEXT:    call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10)
13410 // CHECK17-NEXT:    [[TMP68:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113.region_id, i32 1, i8** [[TMP66]], i8** [[TMP67]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.4, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.5, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
13411 // CHECK17-NEXT:    [[TMP69:%.*]] = icmp ne i32 [[TMP68]], 0
13412 // CHECK17-NEXT:    br i1 [[TMP69]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
13413 // CHECK17:       omp_offload.failed:
13414 // CHECK17-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113(i64 [[TMP60]]) #[[ATTR3]]
13415 // CHECK17-NEXT:    br label [[OMP_OFFLOAD_CONT]]
13416 // CHECK17:       omp_offload.cont:
13417 // CHECK17-NEXT:    [[TMP70:%.*]] = load i32, i32* [[A]], align 4
13418 // CHECK17-NEXT:    [[CONV13:%.*]] = bitcast i64* [[A_CASTED12]] to i32*
13419 // CHECK17-NEXT:    store i32 [[TMP70]], i32* [[CONV13]], align 4
13420 // CHECK17-NEXT:    [[TMP71:%.*]] = load i64, i64* [[A_CASTED12]], align 8
13421 // CHECK17-NEXT:    [[TMP72:%.*]] = load i16, i16* [[AA]], align 2
13422 // CHECK17-NEXT:    [[CONV15:%.*]] = bitcast i64* [[AA_CASTED14]] to i16*
13423 // CHECK17-NEXT:    store i16 [[TMP72]], i16* [[CONV15]], align 2
13424 // CHECK17-NEXT:    [[TMP73:%.*]] = load i64, i64* [[AA_CASTED14]], align 8
13425 // CHECK17-NEXT:    [[TMP74:%.*]] = load i32, i32* [[N_ADDR]], align 4
13426 // CHECK17-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP74]], 10
13427 // CHECK17-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
13428 // CHECK17:       omp_if.then:
13429 // CHECK17-NEXT:    [[TMP75:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 0
13430 // CHECK17-NEXT:    [[TMP76:%.*]] = bitcast i8** [[TMP75]] to i64*
13431 // CHECK17-NEXT:    store i64 [[TMP71]], i64* [[TMP76]], align 8
13432 // CHECK17-NEXT:    [[TMP77:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 0
13433 // CHECK17-NEXT:    [[TMP78:%.*]] = bitcast i8** [[TMP77]] to i64*
13434 // CHECK17-NEXT:    store i64 [[TMP71]], i64* [[TMP78]], align 8
13435 // CHECK17-NEXT:    [[TMP79:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 0
13436 // CHECK17-NEXT:    store i8* null, i8** [[TMP79]], align 8
13437 // CHECK17-NEXT:    [[TMP80:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 1
13438 // CHECK17-NEXT:    [[TMP81:%.*]] = bitcast i8** [[TMP80]] to i64*
13439 // CHECK17-NEXT:    store i64 [[TMP73]], i64* [[TMP81]], align 8
13440 // CHECK17-NEXT:    [[TMP82:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 1
13441 // CHECK17-NEXT:    [[TMP83:%.*]] = bitcast i8** [[TMP82]] to i64*
13442 // CHECK17-NEXT:    store i64 [[TMP73]], i64* [[TMP83]], align 8
13443 // CHECK17-NEXT:    [[TMP84:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 1
13444 // CHECK17-NEXT:    store i8* null, i8** [[TMP84]], align 8
13445 // CHECK17-NEXT:    [[TMP85:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 0
13446 // CHECK17-NEXT:    [[TMP86:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 0
13447 // CHECK17-NEXT:    call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10)
13448 // CHECK17-NEXT:    [[TMP87:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120.region_id, i32 2, i8** [[TMP85]], i8** [[TMP86]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.7, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.8, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
13449 // CHECK17-NEXT:    [[TMP88:%.*]] = icmp ne i32 [[TMP87]], 0
13450 // CHECK17-NEXT:    br i1 [[TMP88]], label [[OMP_OFFLOAD_FAILED20:%.*]], label [[OMP_OFFLOAD_CONT21:%.*]]
13451 // CHECK17:       omp_offload.failed20:
13452 // CHECK17-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120(i64 [[TMP71]], i64 [[TMP73]]) #[[ATTR3]]
13453 // CHECK17-NEXT:    br label [[OMP_OFFLOAD_CONT21]]
13454 // CHECK17:       omp_offload.cont21:
13455 // CHECK17-NEXT:    br label [[OMP_IF_END:%.*]]
13456 // CHECK17:       omp_if.else:
13457 // CHECK17-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120(i64 [[TMP71]], i64 [[TMP73]]) #[[ATTR3]]
13458 // CHECK17-NEXT:    br label [[OMP_IF_END]]
13459 // CHECK17:       omp_if.end:
13460 // CHECK17-NEXT:    [[TMP89:%.*]] = load i32, i32* [[N_ADDR]], align 4
13461 // CHECK17-NEXT:    store i32 [[TMP89]], i32* [[DOTCAPTURE_EXPR_22]], align 4
13462 // CHECK17-NEXT:    [[TMP90:%.*]] = load i32, i32* [[A]], align 4
13463 // CHECK17-NEXT:    [[CONV24:%.*]] = bitcast i64* [[A_CASTED23]] to i32*
13464 // CHECK17-NEXT:    store i32 [[TMP90]], i32* [[CONV24]], align 4
13465 // CHECK17-NEXT:    [[TMP91:%.*]] = load i64, i64* [[A_CASTED23]], align 8
13466 // CHECK17-NEXT:    [[TMP92:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_22]], align 4
13467 // CHECK17-NEXT:    [[CONV26:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED25]] to i32*
13468 // CHECK17-NEXT:    store i32 [[TMP92]], i32* [[CONV26]], align 4
13469 // CHECK17-NEXT:    [[TMP93:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED25]], align 8
13470 // CHECK17-NEXT:    [[TMP94:%.*]] = load i32, i32* [[N_ADDR]], align 4
13471 // CHECK17-NEXT:    [[CMP27:%.*]] = icmp sgt i32 [[TMP94]], 20
13472 // CHECK17-NEXT:    br i1 [[CMP27]], label [[OMP_IF_THEN28:%.*]], label [[OMP_IF_ELSE35:%.*]]
13473 // CHECK17:       omp_if.then28:
13474 // CHECK17-NEXT:    [[TMP95:%.*]] = mul nuw i64 [[TMP2]], 4
13475 // CHECK17-NEXT:    [[TMP96:%.*]] = mul nuw i64 5, [[TMP5]]
13476 // CHECK17-NEXT:    [[TMP97:%.*]] = mul nuw i64 [[TMP96]], 8
13477 // CHECK17-NEXT:    [[TMP98:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS29]], i32 0, i32 0
13478 // CHECK17-NEXT:    [[TMP99:%.*]] = bitcast i8** [[TMP98]] to i64*
13479 // CHECK17-NEXT:    store i64 [[TMP91]], i64* [[TMP99]], align 8
13480 // CHECK17-NEXT:    [[TMP100:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS30]], i32 0, i32 0
13481 // CHECK17-NEXT:    [[TMP101:%.*]] = bitcast i8** [[TMP100]] to i64*
13482 // CHECK17-NEXT:    store i64 [[TMP91]], i64* [[TMP101]], align 8
13483 // CHECK17-NEXT:    [[TMP102:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
13484 // CHECK17-NEXT:    store i64 4, i64* [[TMP102]], align 8
13485 // CHECK17-NEXT:    [[TMP103:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS31]], i64 0, i64 0
13486 // CHECK17-NEXT:    store i8* null, i8** [[TMP103]], align 8
13487 // CHECK17-NEXT:    [[TMP104:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS29]], i32 0, i32 1
13488 // CHECK17-NEXT:    [[TMP105:%.*]] = bitcast i8** [[TMP104]] to [10 x float]**
13489 // CHECK17-NEXT:    store [10 x float]* [[B]], [10 x float]** [[TMP105]], align 8
13490 // CHECK17-NEXT:    [[TMP106:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS30]], i32 0, i32 1
13491 // CHECK17-NEXT:    [[TMP107:%.*]] = bitcast i8** [[TMP106]] to [10 x float]**
13492 // CHECK17-NEXT:    store [10 x float]* [[B]], [10 x float]** [[TMP107]], align 8
13493 // CHECK17-NEXT:    [[TMP108:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1
13494 // CHECK17-NEXT:    store i64 40, i64* [[TMP108]], align 8
13495 // CHECK17-NEXT:    [[TMP109:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS31]], i64 0, i64 1
13496 // CHECK17-NEXT:    store i8* null, i8** [[TMP109]], align 8
13497 // CHECK17-NEXT:    [[TMP110:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS29]], i32 0, i32 2
13498 // CHECK17-NEXT:    [[TMP111:%.*]] = bitcast i8** [[TMP110]] to i64*
13499 // CHECK17-NEXT:    store i64 [[TMP2]], i64* [[TMP111]], align 8
13500 // CHECK17-NEXT:    [[TMP112:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS30]], i32 0, i32 2
13501 // CHECK17-NEXT:    [[TMP113:%.*]] = bitcast i8** [[TMP112]] to i64*
13502 // CHECK17-NEXT:    store i64 [[TMP2]], i64* [[TMP113]], align 8
13503 // CHECK17-NEXT:    [[TMP114:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2
13504 // CHECK17-NEXT:    store i64 8, i64* [[TMP114]], align 8
13505 // CHECK17-NEXT:    [[TMP115:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS31]], i64 0, i64 2
13506 // CHECK17-NEXT:    store i8* null, i8** [[TMP115]], align 8
13507 // CHECK17-NEXT:    [[TMP116:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS29]], i32 0, i32 3
13508 // CHECK17-NEXT:    [[TMP117:%.*]] = bitcast i8** [[TMP116]] to float**
13509 // CHECK17-NEXT:    store float* [[VLA]], float** [[TMP117]], align 8
13510 // CHECK17-NEXT:    [[TMP118:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS30]], i32 0, i32 3
13511 // CHECK17-NEXT:    [[TMP119:%.*]] = bitcast i8** [[TMP118]] to float**
13512 // CHECK17-NEXT:    store float* [[VLA]], float** [[TMP119]], align 8
13513 // CHECK17-NEXT:    [[TMP120:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3
13514 // CHECK17-NEXT:    store i64 [[TMP95]], i64* [[TMP120]], align 8
13515 // CHECK17-NEXT:    [[TMP121:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS31]], i64 0, i64 3
13516 // CHECK17-NEXT:    store i8* null, i8** [[TMP121]], align 8
13517 // CHECK17-NEXT:    [[TMP122:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS29]], i32 0, i32 4
13518 // CHECK17-NEXT:    [[TMP123:%.*]] = bitcast i8** [[TMP122]] to [5 x [10 x double]]**
13519 // CHECK17-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP123]], align 8
13520 // CHECK17-NEXT:    [[TMP124:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS30]], i32 0, i32 4
13521 // CHECK17-NEXT:    [[TMP125:%.*]] = bitcast i8** [[TMP124]] to [5 x [10 x double]]**
13522 // CHECK17-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP125]], align 8
13523 // CHECK17-NEXT:    [[TMP126:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4
13524 // CHECK17-NEXT:    store i64 400, i64* [[TMP126]], align 8
13525 // CHECK17-NEXT:    [[TMP127:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS31]], i64 0, i64 4
13526 // CHECK17-NEXT:    store i8* null, i8** [[TMP127]], align 8
13527 // CHECK17-NEXT:    [[TMP128:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS29]], i32 0, i32 5
13528 // CHECK17-NEXT:    [[TMP129:%.*]] = bitcast i8** [[TMP128]] to i64*
13529 // CHECK17-NEXT:    store i64 5, i64* [[TMP129]], align 8
13530 // CHECK17-NEXT:    [[TMP130:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS30]], i32 0, i32 5
13531 // CHECK17-NEXT:    [[TMP131:%.*]] = bitcast i8** [[TMP130]] to i64*
13532 // CHECK17-NEXT:    store i64 5, i64* [[TMP131]], align 8
13533 // CHECK17-NEXT:    [[TMP132:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 5
13534 // CHECK17-NEXT:    store i64 8, i64* [[TMP132]], align 8
13535 // CHECK17-NEXT:    [[TMP133:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS31]], i64 0, i64 5
13536 // CHECK17-NEXT:    store i8* null, i8** [[TMP133]], align 8
13537 // CHECK17-NEXT:    [[TMP134:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS29]], i32 0, i32 6
13538 // CHECK17-NEXT:    [[TMP135:%.*]] = bitcast i8** [[TMP134]] to i64*
13539 // CHECK17-NEXT:    store i64 [[TMP5]], i64* [[TMP135]], align 8
13540 // CHECK17-NEXT:    [[TMP136:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS30]], i32 0, i32 6
13541 // CHECK17-NEXT:    [[TMP137:%.*]] = bitcast i8** [[TMP136]] to i64*
13542 // CHECK17-NEXT:    store i64 [[TMP5]], i64* [[TMP137]], align 8
13543 // CHECK17-NEXT:    [[TMP138:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 6
13544 // CHECK17-NEXT:    store i64 8, i64* [[TMP138]], align 8
13545 // CHECK17-NEXT:    [[TMP139:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS31]], i64 0, i64 6
13546 // CHECK17-NEXT:    store i8* null, i8** [[TMP139]], align 8
13547 // CHECK17-NEXT:    [[TMP140:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS29]], i32 0, i32 7
13548 // CHECK17-NEXT:    [[TMP141:%.*]] = bitcast i8** [[TMP140]] to double**
13549 // CHECK17-NEXT:    store double* [[VLA1]], double** [[TMP141]], align 8
13550 // CHECK17-NEXT:    [[TMP142:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS30]], i32 0, i32 7
13551 // CHECK17-NEXT:    [[TMP143:%.*]] = bitcast i8** [[TMP142]] to double**
13552 // CHECK17-NEXT:    store double* [[VLA1]], double** [[TMP143]], align 8
13553 // CHECK17-NEXT:    [[TMP144:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7
13554 // CHECK17-NEXT:    store i64 [[TMP97]], i64* [[TMP144]], align 8
13555 // CHECK17-NEXT:    [[TMP145:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS31]], i64 0, i64 7
13556 // CHECK17-NEXT:    store i8* null, i8** [[TMP145]], align 8
13557 // CHECK17-NEXT:    [[TMP146:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS29]], i32 0, i32 8
13558 // CHECK17-NEXT:    [[TMP147:%.*]] = bitcast i8** [[TMP146]] to %struct.TT**
13559 // CHECK17-NEXT:    store %struct.TT* [[D]], %struct.TT** [[TMP147]], align 8
13560 // CHECK17-NEXT:    [[TMP148:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS30]], i32 0, i32 8
13561 // CHECK17-NEXT:    [[TMP149:%.*]] = bitcast i8** [[TMP148]] to %struct.TT**
13562 // CHECK17-NEXT:    store %struct.TT* [[D]], %struct.TT** [[TMP149]], align 8
13563 // CHECK17-NEXT:    [[TMP150:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 8
13564 // CHECK17-NEXT:    store i64 16, i64* [[TMP150]], align 8
13565 // CHECK17-NEXT:    [[TMP151:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS31]], i64 0, i64 8
13566 // CHECK17-NEXT:    store i8* null, i8** [[TMP151]], align 8
13567 // CHECK17-NEXT:    [[TMP152:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS29]], i32 0, i32 9
13568 // CHECK17-NEXT:    [[TMP153:%.*]] = bitcast i8** [[TMP152]] to i64*
13569 // CHECK17-NEXT:    store i64 [[TMP93]], i64* [[TMP153]], align 8
13570 // CHECK17-NEXT:    [[TMP154:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS30]], i32 0, i32 9
13571 // CHECK17-NEXT:    [[TMP155:%.*]] = bitcast i8** [[TMP154]] to i64*
13572 // CHECK17-NEXT:    store i64 [[TMP93]], i64* [[TMP155]], align 8
13573 // CHECK17-NEXT:    [[TMP156:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 9
13574 // CHECK17-NEXT:    store i64 4, i64* [[TMP156]], align 8
13575 // CHECK17-NEXT:    [[TMP157:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS31]], i64 0, i64 9
13576 // CHECK17-NEXT:    store i8* null, i8** [[TMP157]], align 8
13577 // CHECK17-NEXT:    [[TMP158:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS29]], i32 0, i32 0
13578 // CHECK17-NEXT:    [[TMP159:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS30]], i32 0, i32 0
13579 // CHECK17-NEXT:    [[TMP160:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
13580 // CHECK17-NEXT:    call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10)
13581 // CHECK17-NEXT:    [[TMP161:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145.region_id, i32 10, i8** [[TMP158]], i8** [[TMP159]], i64* [[TMP160]], i64* getelementptr inbounds ([10 x i64], [10 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
13582 // CHECK17-NEXT:    [[TMP162:%.*]] = icmp ne i32 [[TMP161]], 0
13583 // CHECK17-NEXT:    br i1 [[TMP162]], label [[OMP_OFFLOAD_FAILED33:%.*]], label [[OMP_OFFLOAD_CONT34:%.*]]
13584 // CHECK17:       omp_offload.failed33:
13585 // CHECK17-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145(i64 [[TMP91]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]], i64 [[TMP93]]) #[[ATTR3]]
13586 // CHECK17-NEXT:    br label [[OMP_OFFLOAD_CONT34]]
13587 // CHECK17:       omp_offload.cont34:
13588 // CHECK17-NEXT:    br label [[OMP_IF_END36:%.*]]
13589 // CHECK17:       omp_if.else35:
13590 // CHECK17-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145(i64 [[TMP91]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]], i64 [[TMP93]]) #[[ATTR3]]
13591 // CHECK17-NEXT:    br label [[OMP_IF_END36]]
13592 // CHECK17:       omp_if.end36:
13593 // CHECK17-NEXT:    [[TMP163:%.*]] = load i32, i32* [[A]], align 4
13594 // CHECK17-NEXT:    [[TMP164:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
13595 // CHECK17-NEXT:    call void @llvm.stackrestore(i8* [[TMP164]])
13596 // CHECK17-NEXT:    ret i32 [[TMP163]]
13597 //
13598 //
13599 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103
13600 // CHECK17-SAME: (i64 [[AA:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] {
13601 // CHECK17-NEXT:  entry:
13602 // CHECK17-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
13603 // CHECK17-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
13604 // CHECK17-NEXT:    [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8
13605 // CHECK17-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
13606 // CHECK17-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]])
13607 // CHECK17-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
13608 // CHECK17-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
13609 // CHECK17-NEXT:    store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8
13610 // CHECK17-NEXT:    [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
13611 // CHECK17-NEXT:    [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
13612 // CHECK17-NEXT:    [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32*
13613 // CHECK17-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 8
13614 // CHECK17-NEXT:    [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 8
13615 // CHECK17-NEXT:    call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
13616 // CHECK17-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV]], align 8
13617 // CHECK17-NEXT:    [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
13618 // CHECK17-NEXT:    store i16 [[TMP3]], i16* [[CONV5]], align 2
13619 // CHECK17-NEXT:    [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
13620 // CHECK17-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]])
13621 // CHECK17-NEXT:    ret void
13622 //
13623 //
13624 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined.
13625 // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] {
13626 // CHECK17-NEXT:  entry:
13627 // CHECK17-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
13628 // CHECK17-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
13629 // CHECK17-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
13630 // CHECK17-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
13631 // CHECK17-NEXT:    [[TMP:%.*]] = alloca i32, align 4
13632 // CHECK17-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
13633 // CHECK17-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
13634 // CHECK17-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
13635 // CHECK17-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
13636 // CHECK17-NEXT:    [[I:%.*]] = alloca i32, align 4
13637 // CHECK17-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
13638 // CHECK17-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
13639 // CHECK17-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
13640 // CHECK17-NEXT:    [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
13641 // CHECK17-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
13642 // CHECK17-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
13643 // CHECK17-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
13644 // CHECK17-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
13645 // CHECK17-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
13646 // CHECK17-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
13647 // CHECK17-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
13648 // CHECK17-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
13649 // CHECK17-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
13650 // CHECK17-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
13651 // CHECK17:       cond.true:
13652 // CHECK17-NEXT:    br label [[COND_END:%.*]]
13653 // CHECK17:       cond.false:
13654 // CHECK17-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
13655 // CHECK17-NEXT:    br label [[COND_END]]
13656 // CHECK17:       cond.end:
13657 // CHECK17-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
13658 // CHECK17-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
13659 // CHECK17-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
13660 // CHECK17-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
13661 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
13662 // CHECK17:       omp.inner.for.cond:
13663 // CHECK17-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
13664 // CHECK17-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
13665 // CHECK17-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
13666 // CHECK17-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
13667 // CHECK17:       omp.inner.for.body:
13668 // CHECK17-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
13669 // CHECK17-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
13670 // CHECK17-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
13671 // CHECK17-NEXT:    store i32 [[ADD]], i32* [[I]], align 4
13672 // CHECK17-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
13673 // CHECK17:       omp.body.continue:
13674 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
13675 // CHECK17:       omp.inner.for.inc:
13676 // CHECK17-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
13677 // CHECK17-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
13678 // CHECK17-NEXT:    store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4
13679 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_COND]]
13680 // CHECK17:       omp.inner.for.end:
13681 // CHECK17-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
13682 // CHECK17:       omp.loop.exit:
13683 // CHECK17-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
13684 // CHECK17-NEXT:    ret void
13685 //
13686 //
13687 // CHECK17-LABEL: define {{[^@]+}}@.omp_task_privates_map.
13688 // CHECK17-SAME: (%struct..kmp_privates.t* noalias [[TMP0:%.*]], i16** noalias [[TMP1:%.*]], [3 x i8*]** noalias [[TMP2:%.*]], [3 x i8*]** noalias [[TMP3:%.*]], [3 x i64]** noalias [[TMP4:%.*]]) #[[ATTR4:[0-9]+]] {
13689 // CHECK17-NEXT:  entry:
13690 // CHECK17-NEXT:    [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 8
13691 // CHECK17-NEXT:    [[DOTADDR1:%.*]] = alloca i16**, align 8
13692 // CHECK17-NEXT:    [[DOTADDR2:%.*]] = alloca [3 x i8*]**, align 8
13693 // CHECK17-NEXT:    [[DOTADDR3:%.*]] = alloca [3 x i8*]**, align 8
13694 // CHECK17-NEXT:    [[DOTADDR4:%.*]] = alloca [3 x i64]**, align 8
13695 // CHECK17-NEXT:    store %struct..kmp_privates.t* [[TMP0]], %struct..kmp_privates.t** [[DOTADDR]], align 8
13696 // CHECK17-NEXT:    store i16** [[TMP1]], i16*** [[DOTADDR1]], align 8
13697 // CHECK17-NEXT:    store [3 x i8*]** [[TMP2]], [3 x i8*]*** [[DOTADDR2]], align 8
13698 // CHECK17-NEXT:    store [3 x i8*]** [[TMP3]], [3 x i8*]*** [[DOTADDR3]], align 8
13699 // CHECK17-NEXT:    store [3 x i64]** [[TMP4]], [3 x i64]*** [[DOTADDR4]], align 8
13700 // CHECK17-NEXT:    [[TMP5:%.*]] = load %struct..kmp_privates.t*, %struct..kmp_privates.t** [[DOTADDR]], align 8
13701 // CHECK17-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 0
13702 // CHECK17-NEXT:    [[TMP7:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR2]], align 8
13703 // CHECK17-NEXT:    store [3 x i8*]* [[TMP6]], [3 x i8*]** [[TMP7]], align 8
13704 // CHECK17-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 1
13705 // CHECK17-NEXT:    [[TMP9:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR3]], align 8
13706 // CHECK17-NEXT:    store [3 x i8*]* [[TMP8]], [3 x i8*]** [[TMP9]], align 8
13707 // CHECK17-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 2
13708 // CHECK17-NEXT:    [[TMP11:%.*]] = load [3 x i64]**, [3 x i64]*** [[DOTADDR4]], align 8
13709 // CHECK17-NEXT:    store [3 x i64]* [[TMP10]], [3 x i64]** [[TMP11]], align 8
13710 // CHECK17-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 3
13711 // CHECK17-NEXT:    [[TMP13:%.*]] = load i16**, i16*** [[DOTADDR1]], align 8
13712 // CHECK17-NEXT:    store i16* [[TMP12]], i16** [[TMP13]], align 8
13713 // CHECK17-NEXT:    ret void
13714 //
13715 //
13716 // CHECK17-LABEL: define {{[^@]+}}@.omp_task_entry.
13717 // CHECK17-SAME: (i32 signext [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] {
13718 // CHECK17-NEXT:  entry:
13719 // CHECK17-NEXT:    [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
13720 // CHECK17-NEXT:    [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8
13721 // CHECK17-NEXT:    [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8
13722 // CHECK17-NEXT:    [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8
13723 // CHECK17-NEXT:    [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8
13724 // CHECK17-NEXT:    [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 8
13725 // CHECK17-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca i16*, align 8
13726 // CHECK17-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca [3 x i8*]*, align 8
13727 // CHECK17-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca [3 x i8*]*, align 8
13728 // CHECK17-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca [3 x i64]*, align 8
13729 // CHECK17-NEXT:    [[AA_CASTED_I:%.*]] = alloca i64, align 8
13730 // CHECK17-NEXT:    [[DOTCAPTURE_EXPR__CASTED_I:%.*]] = alloca i64, align 8
13731 // CHECK17-NEXT:    [[DOTCAPTURE_EXPR__CASTED5_I:%.*]] = alloca i64, align 8
13732 // CHECK17-NEXT:    [[DOTADDR:%.*]] = alloca i32, align 4
13733 // CHECK17-NEXT:    [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8
13734 // CHECK17-NEXT:    store i32 [[TMP0]], i32* [[DOTADDR]], align 4
13735 // CHECK17-NEXT:    store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8
13736 // CHECK17-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4
13737 // CHECK17-NEXT:    [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8
13738 // CHECK17-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
13739 // CHECK17-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
13740 // CHECK17-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0
13741 // CHECK17-NEXT:    [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8
13742 // CHECK17-NEXT:    [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon*
13743 // CHECK17-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1
13744 // CHECK17-NEXT:    [[TMP10:%.*]] = bitcast %struct..kmp_privates.t* [[TMP9]] to i8*
13745 // CHECK17-NEXT:    [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8*
13746 // CHECK17-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META11:![0-9]+]])
13747 // CHECK17-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META14:![0-9]+]])
13748 // CHECK17-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META16:![0-9]+]])
13749 // CHECK17-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]])
13750 // CHECK17-NEXT:    store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !20
13751 // CHECK17-NEXT:    store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !20
13752 // CHECK17-NEXT:    store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !20
13753 // CHECK17-NEXT:    store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* @.omp_task_privates_map. to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !20
13754 // CHECK17-NEXT:    store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !20
13755 // CHECK17-NEXT:    store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !20
13756 // CHECK17-NEXT:    [[TMP12:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !20
13757 // CHECK17-NEXT:    [[TMP13:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !20
13758 // CHECK17-NEXT:    [[TMP14:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !20
13759 // CHECK17-NEXT:    [[TMP15:%.*]] = bitcast void (i8*, ...)* [[TMP13]] to void (i8*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)*
13760 // CHECK17-NEXT:    call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]]
13761 // CHECK17-NEXT:    [[TMP16:%.*]] = load i16*, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !20
13762 // CHECK17-NEXT:    [[TMP17:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !20
13763 // CHECK17-NEXT:    [[TMP18:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 8, !noalias !20
13764 // CHECK17-NEXT:    [[TMP19:%.*]] = load [3 x i64]*, [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 8, !noalias !20
13765 // CHECK17-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP17]], i64 0, i64 0
13766 // CHECK17-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP18]], i64 0, i64 0
13767 // CHECK17-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[TMP19]], i64 0, i64 0
13768 // CHECK17-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP12]], i32 0, i32 1
13769 // CHECK17-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[TMP12]], i32 0, i32 2
13770 // CHECK17-NEXT:    [[TMP25:%.*]] = load i32, i32* [[TMP23]], align 4
13771 // CHECK17-NEXT:    [[TMP26:%.*]] = load i32, i32* [[TMP24]], align 4
13772 // CHECK17-NEXT:    call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) #[[ATTR3]]
13773 // CHECK17-NEXT:    [[TMP27:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 [[TMP25]], i32 [[TMP26]]) #[[ATTR3]]
13774 // CHECK17-NEXT:    [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0
13775 // CHECK17-NEXT:    br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]]
13776 // CHECK17:       omp_offload.failed.i:
13777 // CHECK17-NEXT:    [[TMP29:%.*]] = load i16, i16* [[TMP16]], align 2
13778 // CHECK17-NEXT:    [[CONV_I:%.*]] = bitcast i64* [[AA_CASTED_I]] to i16*
13779 // CHECK17-NEXT:    store i16 [[TMP29]], i16* [[CONV_I]], align 2, !noalias !20
13780 // CHECK17-NEXT:    [[TMP30:%.*]] = load i64, i64* [[AA_CASTED_I]], align 8, !noalias !20
13781 // CHECK17-NEXT:    [[TMP31:%.*]] = load i32, i32* [[TMP23]], align 4
13782 // CHECK17-NEXT:    [[CONV4_I:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED_I]] to i32*
13783 // CHECK17-NEXT:    store i32 [[TMP31]], i32* [[CONV4_I]], align 4, !noalias !20
13784 // CHECK17-NEXT:    [[TMP32:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED_I]], align 8, !noalias !20
13785 // CHECK17-NEXT:    [[TMP33:%.*]] = load i32, i32* [[TMP24]], align 4
13786 // CHECK17-NEXT:    [[CONV6_I:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED5_I]] to i32*
13787 // CHECK17-NEXT:    store i32 [[TMP33]], i32* [[CONV6_I]], align 4, !noalias !20
13788 // CHECK17-NEXT:    [[TMP34:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED5_I]], align 8, !noalias !20
13789 // CHECK17-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103(i64 [[TMP30]], i64 [[TMP32]], i64 [[TMP34]]) #[[ATTR3]]
13790 // CHECK17-NEXT:    br label [[DOTOMP_OUTLINED__1_EXIT]]
13791 // CHECK17:       .omp_outlined..1.exit:
13792 // CHECK17-NEXT:    ret i32 0
13793 //
13794 //
13795 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l107
13796 // CHECK17-SAME: (i64 [[A:%.*]]) #[[ATTR2]] {
13797 // CHECK17-NEXT:  entry:
13798 // CHECK17-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
13799 // CHECK17-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
13800 // CHECK17-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
13801 // CHECK17-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
13802 // CHECK17-NEXT:    [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
13803 // CHECK17-NEXT:    [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32*
13804 // CHECK17-NEXT:    store i32 [[TMP0]], i32* [[CONV1]], align 4
13805 // CHECK17-NEXT:    [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
13806 // CHECK17-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]])
13807 // CHECK17-NEXT:    ret void
13808 //
13809 //
13810 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..2
13811 // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]]) #[[ATTR2]] {
13812 // CHECK17-NEXT:  entry:
13813 // CHECK17-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
13814 // CHECK17-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
13815 // CHECK17-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
13816 // CHECK17-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
13817 // CHECK17-NEXT:    [[TMP:%.*]] = alloca i32, align 4
13818 // CHECK17-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
13819 // CHECK17-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
13820 // CHECK17-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
13821 // CHECK17-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
13822 // CHECK17-NEXT:    [[I:%.*]] = alloca i32, align 4
13823 // CHECK17-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
13824 // CHECK17-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
13825 // CHECK17-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
13826 // CHECK17-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
13827 // CHECK17-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
13828 // CHECK17-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
13829 // CHECK17-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
13830 // CHECK17-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
13831 // CHECK17-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
13832 // CHECK17-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
13833 // CHECK17-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
13834 // CHECK17-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
13835 // CHECK17-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
13836 // CHECK17-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
13837 // CHECK17:       cond.true:
13838 // CHECK17-NEXT:    br label [[COND_END:%.*]]
13839 // CHECK17:       cond.false:
13840 // CHECK17-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
13841 // CHECK17-NEXT:    br label [[COND_END]]
13842 // CHECK17:       cond.end:
13843 // CHECK17-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
13844 // CHECK17-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
13845 // CHECK17-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
13846 // CHECK17-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
13847 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
13848 // CHECK17:       omp.inner.for.cond:
13849 // CHECK17-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
13850 // CHECK17-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
13851 // CHECK17-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
13852 // CHECK17-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
13853 // CHECK17:       omp.inner.for.body:
13854 // CHECK17-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
13855 // CHECK17-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
13856 // CHECK17-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
13857 // CHECK17-NEXT:    store i32 [[ADD]], i32* [[I]], align 4
13858 // CHECK17-NEXT:    [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
13859 // CHECK17-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
13860 // CHECK17-NEXT:    store i32 [[ADD2]], i32* [[CONV]], align 8
13861 // CHECK17-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
13862 // CHECK17:       omp.body.continue:
13863 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
13864 // CHECK17:       omp.inner.for.inc:
13865 // CHECK17-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
13866 // CHECK17-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1
13867 // CHECK17-NEXT:    store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4
13868 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_COND]]
13869 // CHECK17:       omp.inner.for.end:
13870 // CHECK17-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
13871 // CHECK17:       omp.loop.exit:
13872 // CHECK17-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
13873 // CHECK17-NEXT:    ret void
13874 //
13875 //
13876 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113
13877 // CHECK17-SAME: (i64 [[AA:%.*]]) #[[ATTR2]] {
13878 // CHECK17-NEXT:  entry:
13879 // CHECK17-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
13880 // CHECK17-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
13881 // CHECK17-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
13882 // CHECK17-NEXT:    [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
13883 // CHECK17-NEXT:    [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8
13884 // CHECK17-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
13885 // CHECK17-NEXT:    store i16 [[TMP0]], i16* [[CONV1]], align 2
13886 // CHECK17-NEXT:    [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
13887 // CHECK17-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP1]])
13888 // CHECK17-NEXT:    ret void
13889 //
13890 //
13891 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..3
13892 // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] {
13893 // CHECK17-NEXT:  entry:
13894 // CHECK17-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
13895 // CHECK17-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
13896 // CHECK17-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
13897 // CHECK17-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
13898 // CHECK17-NEXT:    [[TMP:%.*]] = alloca i32, align 4
13899 // CHECK17-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
13900 // CHECK17-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
13901 // CHECK17-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
13902 // CHECK17-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
13903 // CHECK17-NEXT:    [[I:%.*]] = alloca i32, align 4
13904 // CHECK17-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
13905 // CHECK17-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
13906 // CHECK17-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
13907 // CHECK17-NEXT:    [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
13908 // CHECK17-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
13909 // CHECK17-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
13910 // CHECK17-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
13911 // CHECK17-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
13912 // CHECK17-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
13913 // CHECK17-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
13914 // CHECK17-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
13915 // CHECK17-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
13916 // CHECK17-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
13917 // CHECK17-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
13918 // CHECK17:       cond.true:
13919 // CHECK17-NEXT:    br label [[COND_END:%.*]]
13920 // CHECK17:       cond.false:
13921 // CHECK17-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
13922 // CHECK17-NEXT:    br label [[COND_END]]
13923 // CHECK17:       cond.end:
13924 // CHECK17-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
13925 // CHECK17-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
13926 // CHECK17-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
13927 // CHECK17-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
13928 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
13929 // CHECK17:       omp.inner.for.cond:
13930 // CHECK17-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
13931 // CHECK17-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
13932 // CHECK17-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
13933 // CHECK17-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
13934 // CHECK17:       omp.inner.for.body:
13935 // CHECK17-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
13936 // CHECK17-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
13937 // CHECK17-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
13938 // CHECK17-NEXT:    store i32 [[ADD]], i32* [[I]], align 4
13939 // CHECK17-NEXT:    [[TMP8:%.*]] = load i16, i16* [[CONV]], align 8
13940 // CHECK17-NEXT:    [[CONV2:%.*]] = sext i16 [[TMP8]] to i32
13941 // CHECK17-NEXT:    [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
13942 // CHECK17-NEXT:    [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
13943 // CHECK17-NEXT:    store i16 [[CONV4]], i16* [[CONV]], align 8
13944 // CHECK17-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
13945 // CHECK17:       omp.body.continue:
13946 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
13947 // CHECK17:       omp.inner.for.inc:
13948 // CHECK17-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
13949 // CHECK17-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP9]], 1
13950 // CHECK17-NEXT:    store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4
13951 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_COND]]
13952 // CHECK17:       omp.inner.for.end:
13953 // CHECK17-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
13954 // CHECK17:       omp.loop.exit:
13955 // CHECK17-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
13956 // CHECK17-NEXT:    ret void
13957 //
13958 //
13959 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120
13960 // CHECK17-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] {
13961 // CHECK17-NEXT:  entry:
13962 // CHECK17-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
13963 // CHECK17-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
13964 // CHECK17-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
13965 // CHECK17-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
13966 // CHECK17-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
13967 // CHECK17-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
13968 // CHECK17-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
13969 // CHECK17-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
13970 // CHECK17-NEXT:    [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
13971 // CHECK17-NEXT:    [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
13972 // CHECK17-NEXT:    store i32 [[TMP0]], i32* [[CONV2]], align 4
13973 // CHECK17-NEXT:    [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
13974 // CHECK17-NEXT:    [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
13975 // CHECK17-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
13976 // CHECK17-NEXT:    store i16 [[TMP2]], i16* [[CONV3]], align 2
13977 // CHECK17-NEXT:    [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
13978 // CHECK17-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
13979 // CHECK17-NEXT:    ret void
13980 //
13981 //
13982 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..6
13983 // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] {
13984 // CHECK17-NEXT:  entry:
13985 // CHECK17-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
13986 // CHECK17-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
13987 // CHECK17-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
13988 // CHECK17-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
13989 // CHECK17-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
13990 // CHECK17-NEXT:    [[TMP:%.*]] = alloca i32, align 4
13991 // CHECK17-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
13992 // CHECK17-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
13993 // CHECK17-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
13994 // CHECK17-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
13995 // CHECK17-NEXT:    [[I:%.*]] = alloca i32, align 4
13996 // CHECK17-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
13997 // CHECK17-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
13998 // CHECK17-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
13999 // CHECK17-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
14000 // CHECK17-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
14001 // CHECK17-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
14002 // CHECK17-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
14003 // CHECK17-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
14004 // CHECK17-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
14005 // CHECK17-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
14006 // CHECK17-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
14007 // CHECK17-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
14008 // CHECK17-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
14009 // CHECK17-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
14010 // CHECK17-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
14011 // CHECK17-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
14012 // CHECK17:       cond.true:
14013 // CHECK17-NEXT:    br label [[COND_END:%.*]]
14014 // CHECK17:       cond.false:
14015 // CHECK17-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
14016 // CHECK17-NEXT:    br label [[COND_END]]
14017 // CHECK17:       cond.end:
14018 // CHECK17-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
14019 // CHECK17-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
14020 // CHECK17-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
14021 // CHECK17-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
14022 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
14023 // CHECK17:       omp.inner.for.cond:
14024 // CHECK17-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
14025 // CHECK17-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
14026 // CHECK17-NEXT:    [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
14027 // CHECK17-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
14028 // CHECK17:       omp.inner.for.body:
14029 // CHECK17-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
14030 // CHECK17-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
14031 // CHECK17-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
14032 // CHECK17-NEXT:    store i32 [[ADD]], i32* [[I]], align 4
14033 // CHECK17-NEXT:    [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
14034 // CHECK17-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
14035 // CHECK17-NEXT:    store i32 [[ADD3]], i32* [[CONV]], align 8
14036 // CHECK17-NEXT:    [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 8
14037 // CHECK17-NEXT:    [[CONV4:%.*]] = sext i16 [[TMP9]] to i32
14038 // CHECK17-NEXT:    [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
14039 // CHECK17-NEXT:    [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
14040 // CHECK17-NEXT:    store i16 [[CONV6]], i16* [[CONV1]], align 8
14041 // CHECK17-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
14042 // CHECK17:       omp.body.continue:
14043 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
14044 // CHECK17:       omp.inner.for.inc:
14045 // CHECK17-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
14046 // CHECK17-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1
14047 // CHECK17-NEXT:    store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4
14048 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_COND]]
14049 // CHECK17:       omp.inner.for.end:
14050 // CHECK17-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
14051 // CHECK17:       omp.loop.exit:
14052 // CHECK17-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
14053 // CHECK17-NEXT:    ret void
14054 //
14055 //
14056 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145
14057 // CHECK17-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] {
14058 // CHECK17-NEXT:  entry:
14059 // CHECK17-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
14060 // CHECK17-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
14061 // CHECK17-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
14062 // CHECK17-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 8
14063 // CHECK17-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
14064 // CHECK17-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
14065 // CHECK17-NEXT:    [[VLA_ADDR4:%.*]] = alloca i64, align 8
14066 // CHECK17-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 8
14067 // CHECK17-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
14068 // CHECK17-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
14069 // CHECK17-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
14070 // CHECK17-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
14071 // CHECK17-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
14072 // CHECK17-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
14073 // CHECK17-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
14074 // CHECK17-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 8
14075 // CHECK17-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
14076 // CHECK17-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
14077 // CHECK17-NEXT:    store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
14078 // CHECK17-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 8
14079 // CHECK17-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
14080 // CHECK17-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
14081 // CHECK17-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
14082 // CHECK17-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
14083 // CHECK17-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
14084 // CHECK17-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
14085 // CHECK17-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
14086 // CHECK17-NEXT:    [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
14087 // CHECK17-NEXT:    [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
14088 // CHECK17-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
14089 // CHECK17-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
14090 // CHECK17-NEXT:    [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
14091 // CHECK17-NEXT:    [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
14092 // CHECK17-NEXT:    [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32*
14093 // CHECK17-NEXT:    store i32 [[TMP8]], i32* [[CONV6]], align 4
14094 // CHECK17-NEXT:    [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
14095 // CHECK17-NEXT:    [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 8
14096 // CHECK17-NEXT:    [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
14097 // CHECK17-NEXT:    store i32 [[TMP10]], i32* [[CONV7]], align 4
14098 // CHECK17-NEXT:    [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
14099 // CHECK17-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]])
14100 // CHECK17-NEXT:    ret void
14101 //
14102 //
14103 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..9
14104 // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] {
14105 // CHECK17-NEXT:  entry:
14106 // CHECK17-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
14107 // CHECK17-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
14108 // CHECK17-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
14109 // CHECK17-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
14110 // CHECK17-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
14111 // CHECK17-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 8
14112 // CHECK17-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
14113 // CHECK17-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
14114 // CHECK17-NEXT:    [[VLA_ADDR4:%.*]] = alloca i64, align 8
14115 // CHECK17-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 8
14116 // CHECK17-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
14117 // CHECK17-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
14118 // CHECK17-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
14119 // CHECK17-NEXT:    [[TMP:%.*]] = alloca i32, align 4
14120 // CHECK17-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
14121 // CHECK17-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
14122 // CHECK17-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
14123 // CHECK17-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
14124 // CHECK17-NEXT:    [[I:%.*]] = alloca i32, align 4
14125 // CHECK17-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
14126 // CHECK17-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
14127 // CHECK17-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
14128 // CHECK17-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
14129 // CHECK17-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
14130 // CHECK17-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 8
14131 // CHECK17-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
14132 // CHECK17-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
14133 // CHECK17-NEXT:    store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
14134 // CHECK17-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 8
14135 // CHECK17-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
14136 // CHECK17-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
14137 // CHECK17-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
14138 // CHECK17-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
14139 // CHECK17-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
14140 // CHECK17-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
14141 // CHECK17-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
14142 // CHECK17-NEXT:    [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
14143 // CHECK17-NEXT:    [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
14144 // CHECK17-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
14145 // CHECK17-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
14146 // CHECK17-NEXT:    [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
14147 // CHECK17-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
14148 // CHECK17-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
14149 // CHECK17-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
14150 // CHECK17-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
14151 // CHECK17-NEXT:    [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 8
14152 // CHECK17-NEXT:    [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
14153 // CHECK17-NEXT:    [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
14154 // CHECK17-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
14155 // CHECK17-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
14156 // CHECK17:       omp.dispatch.cond:
14157 // CHECK17-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
14158 // CHECK17-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 9
14159 // CHECK17-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
14160 // CHECK17:       cond.true:
14161 // CHECK17-NEXT:    br label [[COND_END:%.*]]
14162 // CHECK17:       cond.false:
14163 // CHECK17-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
14164 // CHECK17-NEXT:    br label [[COND_END]]
14165 // CHECK17:       cond.end:
14166 // CHECK17-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
14167 // CHECK17-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
14168 // CHECK17-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
14169 // CHECK17-NEXT:    store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
14170 // CHECK17-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
14171 // CHECK17-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
14172 // CHECK17-NEXT:    [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
14173 // CHECK17-NEXT:    br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
14174 // CHECK17:       omp.dispatch.body:
14175 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
14176 // CHECK17:       omp.inner.for.cond:
14177 // CHECK17-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
14178 // CHECK17-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !21
14179 // CHECK17-NEXT:    [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
14180 // CHECK17-NEXT:    br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
14181 // CHECK17:       omp.inner.for.body:
14182 // CHECK17-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
14183 // CHECK17-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
14184 // CHECK17-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
14185 // CHECK17-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !21
14186 // CHECK17-NEXT:    [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !21
14187 // CHECK17-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP19]], 1
14188 // CHECK17-NEXT:    store i32 [[ADD8]], i32* [[CONV]], align 8, !llvm.access.group !21
14189 // CHECK17-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
14190 // CHECK17-NEXT:    [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !21
14191 // CHECK17-NEXT:    [[CONV9:%.*]] = fpext float [[TMP20]] to double
14192 // CHECK17-NEXT:    [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00
14193 // CHECK17-NEXT:    [[CONV11:%.*]] = fptrunc double [[ADD10]] to float
14194 // CHECK17-NEXT:    store float [[CONV11]], float* [[ARRAYIDX]], align 4, !llvm.access.group !21
14195 // CHECK17-NEXT:    [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3
14196 // CHECK17-NEXT:    [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4, !llvm.access.group !21
14197 // CHECK17-NEXT:    [[CONV13:%.*]] = fpext float [[TMP21]] to double
14198 // CHECK17-NEXT:    [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00
14199 // CHECK17-NEXT:    [[CONV15:%.*]] = fptrunc double [[ADD14]] to float
14200 // CHECK17-NEXT:    store float [[CONV15]], float* [[ARRAYIDX12]], align 4, !llvm.access.group !21
14201 // CHECK17-NEXT:    [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1
14202 // CHECK17-NEXT:    [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i64 0, i64 2
14203 // CHECK17-NEXT:    [[TMP22:%.*]] = load double, double* [[ARRAYIDX17]], align 8, !llvm.access.group !21
14204 // CHECK17-NEXT:    [[ADD18:%.*]] = fadd double [[TMP22]], 1.000000e+00
14205 // CHECK17-NEXT:    store double [[ADD18]], double* [[ARRAYIDX17]], align 8, !llvm.access.group !21
14206 // CHECK17-NEXT:    [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]]
14207 // CHECK17-NEXT:    [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP23]]
14208 // CHECK17-NEXT:    [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i64 3
14209 // CHECK17-NEXT:    [[TMP24:%.*]] = load double, double* [[ARRAYIDX20]], align 8, !llvm.access.group !21
14210 // CHECK17-NEXT:    [[ADD21:%.*]] = fadd double [[TMP24]], 1.000000e+00
14211 // CHECK17-NEXT:    store double [[ADD21]], double* [[ARRAYIDX20]], align 8, !llvm.access.group !21
14212 // CHECK17-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0
14213 // CHECK17-NEXT:    [[TMP25:%.*]] = load i64, i64* [[X]], align 8, !llvm.access.group !21
14214 // CHECK17-NEXT:    [[ADD22:%.*]] = add nsw i64 [[TMP25]], 1
14215 // CHECK17-NEXT:    store i64 [[ADD22]], i64* [[X]], align 8, !llvm.access.group !21
14216 // CHECK17-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1
14217 // CHECK17-NEXT:    [[TMP26:%.*]] = load i8, i8* [[Y]], align 8, !llvm.access.group !21
14218 // CHECK17-NEXT:    [[CONV23:%.*]] = sext i8 [[TMP26]] to i32
14219 // CHECK17-NEXT:    [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1
14220 // CHECK17-NEXT:    [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8
14221 // CHECK17-NEXT:    store i8 [[CONV25]], i8* [[Y]], align 8, !llvm.access.group !21
14222 // CHECK17-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
14223 // CHECK17:       omp.body.continue:
14224 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
14225 // CHECK17:       omp.inner.for.inc:
14226 // CHECK17-NEXT:    [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
14227 // CHECK17-NEXT:    [[ADD26:%.*]] = add nsw i32 [[TMP27]], 1
14228 // CHECK17-NEXT:    store i32 [[ADD26]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
14229 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]]
14230 // CHECK17:       omp.inner.for.end:
14231 // CHECK17-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
14232 // CHECK17:       omp.dispatch.inc:
14233 // CHECK17-NEXT:    [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
14234 // CHECK17-NEXT:    [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
14235 // CHECK17-NEXT:    [[ADD27:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]
14236 // CHECK17-NEXT:    store i32 [[ADD27]], i32* [[DOTOMP_LB]], align 4
14237 // CHECK17-NEXT:    [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
14238 // CHECK17-NEXT:    [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
14239 // CHECK17-NEXT:    [[ADD28:%.*]] = add nsw i32 [[TMP30]], [[TMP31]]
14240 // CHECK17-NEXT:    store i32 [[ADD28]], i32* [[DOTOMP_UB]], align 4
14241 // CHECK17-NEXT:    br label [[OMP_DISPATCH_COND]]
14242 // CHECK17:       omp.dispatch.end:
14243 // CHECK17-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]])
14244 // CHECK17-NEXT:    ret void
14245 //
14246 //
14247 // CHECK17-LABEL: define {{[^@]+}}@_Z3bari
14248 // CHECK17-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
14249 // CHECK17-NEXT:  entry:
14250 // CHECK17-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
14251 // CHECK17-NEXT:    [[A:%.*]] = alloca i32, align 4
14252 // CHECK17-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8
14253 // CHECK17-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
14254 // CHECK17-NEXT:    store i32 0, i32* [[A]], align 4
14255 // CHECK17-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
14256 // CHECK17-NEXT:    [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]])
14257 // CHECK17-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
14258 // CHECK17-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
14259 // CHECK17-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
14260 // CHECK17-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
14261 // CHECK17-NEXT:    [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]])
14262 // CHECK17-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
14263 // CHECK17-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
14264 // CHECK17-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
14265 // CHECK17-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
14266 // CHECK17-NEXT:    [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]])
14267 // CHECK17-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
14268 // CHECK17-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
14269 // CHECK17-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
14270 // CHECK17-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
14271 // CHECK17-NEXT:    [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]])
14272 // CHECK17-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
14273 // CHECK17-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
14274 // CHECK17-NEXT:    store i32 [[ADD6]], i32* [[A]], align 4
14275 // CHECK17-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
14276 // CHECK17-NEXT:    ret i32 [[TMP8]]
14277 //
14278 //
14279 // CHECK17-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
14280 // CHECK17-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 {
14281 // CHECK17-NEXT:  entry:
14282 // CHECK17-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
14283 // CHECK17-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
14284 // CHECK17-NEXT:    [[B:%.*]] = alloca i32, align 4
14285 // CHECK17-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 8
14286 // CHECK17-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
14287 // CHECK17-NEXT:    [[B_CASTED:%.*]] = alloca i64, align 8
14288 // CHECK17-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8
14289 // CHECK17-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8
14290 // CHECK17-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8
14291 // CHECK17-NEXT:    [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 8
14292 // CHECK17-NEXT:    [[TMP:%.*]] = alloca i32, align 4
14293 // CHECK17-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
14294 // CHECK17-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
14295 // CHECK17-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
14296 // CHECK17-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
14297 // CHECK17-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
14298 // CHECK17-NEXT:    store i32 [[ADD]], i32* [[B]], align 4
14299 // CHECK17-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
14300 // CHECK17-NEXT:    [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
14301 // CHECK17-NEXT:    [[TMP3:%.*]] = call i8* @llvm.stacksave()
14302 // CHECK17-NEXT:    store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8
14303 // CHECK17-NEXT:    [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]
14304 // CHECK17-NEXT:    [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2
14305 // CHECK17-NEXT:    store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8
14306 // CHECK17-NEXT:    [[TMP5:%.*]] = load i32, i32* [[B]], align 4
14307 // CHECK17-NEXT:    [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32*
14308 // CHECK17-NEXT:    store i32 [[TMP5]], i32* [[CONV]], align 4
14309 // CHECK17-NEXT:    [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8
14310 // CHECK17-NEXT:    [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4
14311 // CHECK17-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 60
14312 // CHECK17-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
14313 // CHECK17:       omp_if.then:
14314 // CHECK17-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
14315 // CHECK17-NEXT:    [[TMP8:%.*]] = mul nuw i64 2, [[TMP2]]
14316 // CHECK17-NEXT:    [[TMP9:%.*]] = mul nuw i64 [[TMP8]], 2
14317 // CHECK17-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
14318 // CHECK17-NEXT:    [[TMP11:%.*]] = bitcast i8** [[TMP10]] to %struct.S1**
14319 // CHECK17-NEXT:    store %struct.S1* [[THIS1]], %struct.S1** [[TMP11]], align 8
14320 // CHECK17-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
14321 // CHECK17-NEXT:    [[TMP13:%.*]] = bitcast i8** [[TMP12]] to double**
14322 // CHECK17-NEXT:    store double* [[A]], double** [[TMP13]], align 8
14323 // CHECK17-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
14324 // CHECK17-NEXT:    store i64 8, i64* [[TMP14]], align 8
14325 // CHECK17-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
14326 // CHECK17-NEXT:    store i8* null, i8** [[TMP15]], align 8
14327 // CHECK17-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
14328 // CHECK17-NEXT:    [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64*
14329 // CHECK17-NEXT:    store i64 [[TMP6]], i64* [[TMP17]], align 8
14330 // CHECK17-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
14331 // CHECK17-NEXT:    [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64*
14332 // CHECK17-NEXT:    store i64 [[TMP6]], i64* [[TMP19]], align 8
14333 // CHECK17-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1
14334 // CHECK17-NEXT:    store i64 4, i64* [[TMP20]], align 8
14335 // CHECK17-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
14336 // CHECK17-NEXT:    store i8* null, i8** [[TMP21]], align 8
14337 // CHECK17-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
14338 // CHECK17-NEXT:    [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i64*
14339 // CHECK17-NEXT:    store i64 2, i64* [[TMP23]], align 8
14340 // CHECK17-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
14341 // CHECK17-NEXT:    [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i64*
14342 // CHECK17-NEXT:    store i64 2, i64* [[TMP25]], align 8
14343 // CHECK17-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2
14344 // CHECK17-NEXT:    store i64 8, i64* [[TMP26]], align 8
14345 // CHECK17-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
14346 // CHECK17-NEXT:    store i8* null, i8** [[TMP27]], align 8
14347 // CHECK17-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
14348 // CHECK17-NEXT:    [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i64*
14349 // CHECK17-NEXT:    store i64 [[TMP2]], i64* [[TMP29]], align 8
14350 // CHECK17-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
14351 // CHECK17-NEXT:    [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i64*
14352 // CHECK17-NEXT:    store i64 [[TMP2]], i64* [[TMP31]], align 8
14353 // CHECK17-NEXT:    [[TMP32:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3
14354 // CHECK17-NEXT:    store i64 8, i64* [[TMP32]], align 8
14355 // CHECK17-NEXT:    [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
14356 // CHECK17-NEXT:    store i8* null, i8** [[TMP33]], align 8
14357 // CHECK17-NEXT:    [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
14358 // CHECK17-NEXT:    [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i16**
14359 // CHECK17-NEXT:    store i16* [[VLA]], i16** [[TMP35]], align 8
14360 // CHECK17-NEXT:    [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
14361 // CHECK17-NEXT:    [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i16**
14362 // CHECK17-NEXT:    store i16* [[VLA]], i16** [[TMP37]], align 8
14363 // CHECK17-NEXT:    [[TMP38:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4
14364 // CHECK17-NEXT:    store i64 [[TMP9]], i64* [[TMP38]], align 8
14365 // CHECK17-NEXT:    [[TMP39:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4
14366 // CHECK17-NEXT:    store i8* null, i8** [[TMP39]], align 8
14367 // CHECK17-NEXT:    [[TMP40:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
14368 // CHECK17-NEXT:    [[TMP41:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
14369 // CHECK17-NEXT:    [[TMP42:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
14370 // CHECK17-NEXT:    call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10)
14371 // CHECK17-NEXT:    [[TMP43:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218.region_id, i32 5, i8** [[TMP40]], i8** [[TMP41]], i64* [[TMP42]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.12, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
14372 // CHECK17-NEXT:    [[TMP44:%.*]] = icmp ne i32 [[TMP43]], 0
14373 // CHECK17-NEXT:    br i1 [[TMP44]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
14374 // CHECK17:       omp_offload.failed:
14375 // CHECK17-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR3]]
14376 // CHECK17-NEXT:    br label [[OMP_OFFLOAD_CONT]]
14377 // CHECK17:       omp_offload.cont:
14378 // CHECK17-NEXT:    br label [[OMP_IF_END:%.*]]
14379 // CHECK17:       omp_if.else:
14380 // CHECK17-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR3]]
14381 // CHECK17-NEXT:    br label [[OMP_IF_END]]
14382 // CHECK17:       omp_if.end:
14383 // CHECK17-NEXT:    [[TMP45:%.*]] = mul nsw i64 1, [[TMP2]]
14384 // CHECK17-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP45]]
14385 // CHECK17-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
14386 // CHECK17-NEXT:    [[TMP46:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2
14387 // CHECK17-NEXT:    [[CONV3:%.*]] = sext i16 [[TMP46]] to i32
14388 // CHECK17-NEXT:    [[TMP47:%.*]] = load i32, i32* [[B]], align 4
14389 // CHECK17-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], [[TMP47]]
14390 // CHECK17-NEXT:    [[TMP48:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
14391 // CHECK17-NEXT:    call void @llvm.stackrestore(i8* [[TMP48]])
14392 // CHECK17-NEXT:    ret i32 [[ADD4]]
14393 //
14394 //
14395 // CHECK17-LABEL: define {{[^@]+}}@_ZL7fstatici
14396 // CHECK17-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
14397 // CHECK17-NEXT:  entry:
14398 // CHECK17-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
14399 // CHECK17-NEXT:    [[A:%.*]] = alloca i32, align 4
14400 // CHECK17-NEXT:    [[AA:%.*]] = alloca i16, align 2
14401 // CHECK17-NEXT:    [[AAA:%.*]] = alloca i8, align 1
14402 // CHECK17-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
14403 // CHECK17-NEXT:    [[N_CASTED:%.*]] = alloca i64, align 8
14404 // CHECK17-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
14405 // CHECK17-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
14406 // CHECK17-NEXT:    [[AAA_CASTED:%.*]] = alloca i64, align 8
14407 // CHECK17-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8
14408 // CHECK17-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8
14409 // CHECK17-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8
14410 // CHECK17-NEXT:    [[TMP:%.*]] = alloca i32, align 4
14411 // CHECK17-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
14412 // CHECK17-NEXT:    [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4
14413 // CHECK17-NEXT:    [[DOTCAPTURE_EXPR_5:%.*]] = alloca i32, align 4
14414 // CHECK17-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
14415 // CHECK17-NEXT:    store i32 0, i32* [[A]], align 4
14416 // CHECK17-NEXT:    store i16 0, i16* [[AA]], align 2
14417 // CHECK17-NEXT:    store i8 0, i8* [[AAA]], align 1
14418 // CHECK17-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
14419 // CHECK17-NEXT:    [[CONV:%.*]] = bitcast i64* [[N_CASTED]] to i32*
14420 // CHECK17-NEXT:    store i32 [[TMP0]], i32* [[CONV]], align 4
14421 // CHECK17-NEXT:    [[TMP1:%.*]] = load i64, i64* [[N_CASTED]], align 8
14422 // CHECK17-NEXT:    [[TMP2:%.*]] = load i32, i32* [[A]], align 4
14423 // CHECK17-NEXT:    [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32*
14424 // CHECK17-NEXT:    store i32 [[TMP2]], i32* [[CONV1]], align 4
14425 // CHECK17-NEXT:    [[TMP3:%.*]] = load i64, i64* [[A_CASTED]], align 8
14426 // CHECK17-NEXT:    [[TMP4:%.*]] = load i16, i16* [[AA]], align 2
14427 // CHECK17-NEXT:    [[CONV2:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
14428 // CHECK17-NEXT:    store i16 [[TMP4]], i16* [[CONV2]], align 2
14429 // CHECK17-NEXT:    [[TMP5:%.*]] = load i64, i64* [[AA_CASTED]], align 8
14430 // CHECK17-NEXT:    [[TMP6:%.*]] = load i8, i8* [[AAA]], align 1
14431 // CHECK17-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
14432 // CHECK17-NEXT:    store i8 [[TMP6]], i8* [[CONV3]], align 1
14433 // CHECK17-NEXT:    [[TMP7:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
14434 // CHECK17-NEXT:    [[TMP8:%.*]] = load i32, i32* [[N_ADDR]], align 4
14435 // CHECK17-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP8]], 50
14436 // CHECK17-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
14437 // CHECK17:       omp_if.then:
14438 // CHECK17-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
14439 // CHECK17-NEXT:    [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64*
14440 // CHECK17-NEXT:    store i64 [[TMP1]], i64* [[TMP10]], align 8
14441 // CHECK17-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
14442 // CHECK17-NEXT:    [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64*
14443 // CHECK17-NEXT:    store i64 [[TMP1]], i64* [[TMP12]], align 8
14444 // CHECK17-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
14445 // CHECK17-NEXT:    store i8* null, i8** [[TMP13]], align 8
14446 // CHECK17-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
14447 // CHECK17-NEXT:    [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64*
14448 // CHECK17-NEXT:    store i64 [[TMP3]], i64* [[TMP15]], align 8
14449 // CHECK17-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
14450 // CHECK17-NEXT:    [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64*
14451 // CHECK17-NEXT:    store i64 [[TMP3]], i64* [[TMP17]], align 8
14452 // CHECK17-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
14453 // CHECK17-NEXT:    store i8* null, i8** [[TMP18]], align 8
14454 // CHECK17-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
14455 // CHECK17-NEXT:    [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64*
14456 // CHECK17-NEXT:    store i64 [[TMP5]], i64* [[TMP20]], align 8
14457 // CHECK17-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
14458 // CHECK17-NEXT:    [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i64*
14459 // CHECK17-NEXT:    store i64 [[TMP5]], i64* [[TMP22]], align 8
14460 // CHECK17-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
14461 // CHECK17-NEXT:    store i8* null, i8** [[TMP23]], align 8
14462 // CHECK17-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
14463 // CHECK17-NEXT:    [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i64*
14464 // CHECK17-NEXT:    store i64 [[TMP7]], i64* [[TMP25]], align 8
14465 // CHECK17-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
14466 // CHECK17-NEXT:    [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64*
14467 // CHECK17-NEXT:    store i64 [[TMP7]], i64* [[TMP27]], align 8
14468 // CHECK17-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
14469 // CHECK17-NEXT:    store i8* null, i8** [[TMP28]], align 8
14470 // CHECK17-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
14471 // CHECK17-NEXT:    [[TMP30:%.*]] = bitcast i8** [[TMP29]] to [10 x i32]**
14472 // CHECK17-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP30]], align 8
14473 // CHECK17-NEXT:    [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
14474 // CHECK17-NEXT:    [[TMP32:%.*]] = bitcast i8** [[TMP31]] to [10 x i32]**
14475 // CHECK17-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP32]], align 8
14476 // CHECK17-NEXT:    [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4
14477 // CHECK17-NEXT:    store i8* null, i8** [[TMP33]], align 8
14478 // CHECK17-NEXT:    [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
14479 // CHECK17-NEXT:    [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
14480 // CHECK17-NEXT:    [[TMP36:%.*]] = load i32, i32* [[A]], align 4
14481 // CHECK17-NEXT:    store i32 [[TMP36]], i32* [[DOTCAPTURE_EXPR_]], align 4
14482 // CHECK17-NEXT:    [[TMP37:%.*]] = load i32, i32* [[N_ADDR]], align 4
14483 // CHECK17-NEXT:    store i32 [[TMP37]], i32* [[DOTCAPTURE_EXPR_4]], align 4
14484 // CHECK17-NEXT:    [[TMP38:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4
14485 // CHECK17-NEXT:    [[TMP39:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
14486 // CHECK17-NEXT:    [[SUB:%.*]] = sub i32 [[TMP38]], [[TMP39]]
14487 // CHECK17-NEXT:    [[SUB6:%.*]] = sub i32 [[SUB]], 1
14488 // CHECK17-NEXT:    [[ADD:%.*]] = add i32 [[SUB6]], 1
14489 // CHECK17-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], 1
14490 // CHECK17-NEXT:    [[SUB7:%.*]] = sub i32 [[DIV]], 1
14491 // CHECK17-NEXT:    store i32 [[SUB7]], i32* [[DOTCAPTURE_EXPR_5]], align 4
14492 // CHECK17-NEXT:    [[TMP40:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4
14493 // CHECK17-NEXT:    [[ADD8:%.*]] = add i32 [[TMP40]], 1
14494 // CHECK17-NEXT:    [[TMP41:%.*]] = zext i32 [[ADD8]] to i64
14495 // CHECK17-NEXT:    call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 [[TMP41]])
14496 // CHECK17-NEXT:    [[TMP42:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200.region_id, i32 5, i8** [[TMP34]], i8** [[TMP35]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes.14, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.15, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
14497 // CHECK17-NEXT:    [[TMP43:%.*]] = icmp ne i32 [[TMP42]], 0
14498 // CHECK17-NEXT:    br i1 [[TMP43]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
14499 // CHECK17:       omp_offload.failed:
14500 // CHECK17-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], i64 [[TMP7]], [10 x i32]* [[B]]) #[[ATTR3]]
14501 // CHECK17-NEXT:    br label [[OMP_OFFLOAD_CONT]]
14502 // CHECK17:       omp_offload.cont:
14503 // CHECK17-NEXT:    br label [[OMP_IF_END:%.*]]
14504 // CHECK17:       omp_if.else:
14505 // CHECK17-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], i64 [[TMP7]], [10 x i32]* [[B]]) #[[ATTR3]]
14506 // CHECK17-NEXT:    br label [[OMP_IF_END]]
14507 // CHECK17:       omp_if.end:
14508 // CHECK17-NEXT:    [[TMP44:%.*]] = load i32, i32* [[A]], align 4
14509 // CHECK17-NEXT:    ret i32 [[TMP44]]
14510 //
14511 //
14512 // CHECK17-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
14513 // CHECK17-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat {
14514 // CHECK17-NEXT:  entry:
14515 // CHECK17-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
14516 // CHECK17-NEXT:    [[A:%.*]] = alloca i32, align 4
14517 // CHECK17-NEXT:    [[AA:%.*]] = alloca i16, align 2
14518 // CHECK17-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
14519 // CHECK17-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
14520 // CHECK17-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
14521 // CHECK17-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8
14522 // CHECK17-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8
14523 // CHECK17-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8
14524 // CHECK17-NEXT:    [[TMP:%.*]] = alloca i32, align 4
14525 // CHECK17-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
14526 // CHECK17-NEXT:    store i32 0, i32* [[A]], align 4
14527 // CHECK17-NEXT:    store i16 0, i16* [[AA]], align 2
14528 // CHECK17-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
14529 // CHECK17-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32*
14530 // CHECK17-NEXT:    store i32 [[TMP0]], i32* [[CONV]], align 4
14531 // CHECK17-NEXT:    [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
14532 // CHECK17-NEXT:    [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
14533 // CHECK17-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
14534 // CHECK17-NEXT:    store i16 [[TMP2]], i16* [[CONV1]], align 2
14535 // CHECK17-NEXT:    [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
14536 // CHECK17-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
14537 // CHECK17-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40
14538 // CHECK17-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
14539 // CHECK17:       omp_if.then:
14540 // CHECK17-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
14541 // CHECK17-NEXT:    [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64*
14542 // CHECK17-NEXT:    store i64 [[TMP1]], i64* [[TMP6]], align 8
14543 // CHECK17-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
14544 // CHECK17-NEXT:    [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64*
14545 // CHECK17-NEXT:    store i64 [[TMP1]], i64* [[TMP8]], align 8
14546 // CHECK17-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
14547 // CHECK17-NEXT:    store i8* null, i8** [[TMP9]], align 8
14548 // CHECK17-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
14549 // CHECK17-NEXT:    [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i64*
14550 // CHECK17-NEXT:    store i64 [[TMP3]], i64* [[TMP11]], align 8
14551 // CHECK17-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
14552 // CHECK17-NEXT:    [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64*
14553 // CHECK17-NEXT:    store i64 [[TMP3]], i64* [[TMP13]], align 8
14554 // CHECK17-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
14555 // CHECK17-NEXT:    store i8* null, i8** [[TMP14]], align 8
14556 // CHECK17-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
14557 // CHECK17-NEXT:    [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]**
14558 // CHECK17-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 8
14559 // CHECK17-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
14560 // CHECK17-NEXT:    [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]**
14561 // CHECK17-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 8
14562 // CHECK17-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
14563 // CHECK17-NEXT:    store i8* null, i8** [[TMP19]], align 8
14564 // CHECK17-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
14565 // CHECK17-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
14566 // CHECK17-NEXT:    call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10)
14567 // CHECK17-NEXT:    [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.17, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.18, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
14568 // CHECK17-NEXT:    [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0
14569 // CHECK17-NEXT:    br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
14570 // CHECK17:       omp_offload.failed:
14571 // CHECK17-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]]
14572 // CHECK17-NEXT:    br label [[OMP_OFFLOAD_CONT]]
14573 // CHECK17:       omp_offload.cont:
14574 // CHECK17-NEXT:    br label [[OMP_IF_END:%.*]]
14575 // CHECK17:       omp_if.else:
14576 // CHECK17-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]]
14577 // CHECK17-NEXT:    br label [[OMP_IF_END]]
14578 // CHECK17:       omp_if.end:
14579 // CHECK17-NEXT:    [[TMP24:%.*]] = load i32, i32* [[A]], align 4
14580 // CHECK17-NEXT:    ret i32 [[TMP24]]
14581 //
14582 //
14583 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218
14584 // CHECK17-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {
14585 // CHECK17-NEXT:  entry:
14586 // CHECK17-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
14587 // CHECK17-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
14588 // CHECK17-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
14589 // CHECK17-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
14590 // CHECK17-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 8
14591 // CHECK17-NEXT:    [[B_CASTED:%.*]] = alloca i64, align 8
14592 // CHECK17-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
14593 // CHECK17-NEXT:    store i64 [[B]], i64* [[B_ADDR]], align 8
14594 // CHECK17-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
14595 // CHECK17-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
14596 // CHECK17-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 8
14597 // CHECK17-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
14598 // CHECK17-NEXT:    [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
14599 // CHECK17-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
14600 // CHECK17-NEXT:    [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
14601 // CHECK17-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
14602 // CHECK17-NEXT:    [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
14603 // CHECK17-NEXT:    [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32*
14604 // CHECK17-NEXT:    store i32 [[TMP4]], i32* [[CONV3]], align 4
14605 // CHECK17-NEXT:    [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
14606 // CHECK17-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]])
14607 // CHECK17-NEXT:    ret void
14608 //
14609 //
14610 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..11
14611 // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {
14612 // CHECK17-NEXT:  entry:
14613 // CHECK17-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
14614 // CHECK17-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
14615 // CHECK17-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
14616 // CHECK17-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
14617 // CHECK17-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
14618 // CHECK17-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
14619 // CHECK17-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 8
14620 // CHECK17-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
14621 // CHECK17-NEXT:    [[TMP:%.*]] = alloca i32, align 4
14622 // CHECK17-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
14623 // CHECK17-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
14624 // CHECK17-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
14625 // CHECK17-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
14626 // CHECK17-NEXT:    [[I:%.*]] = alloca i32, align 4
14627 // CHECK17-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
14628 // CHECK17-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
14629 // CHECK17-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
14630 // CHECK17-NEXT:    store i64 [[B]], i64* [[B_ADDR]], align 8
14631 // CHECK17-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
14632 // CHECK17-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
14633 // CHECK17-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 8
14634 // CHECK17-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
14635 // CHECK17-NEXT:    [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
14636 // CHECK17-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
14637 // CHECK17-NEXT:    [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
14638 // CHECK17-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
14639 // CHECK17-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
14640 // CHECK17-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
14641 // CHECK17-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
14642 // CHECK17-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
14643 // CHECK17-NEXT:    [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
14644 // CHECK17-NEXT:    [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
14645 // CHECK17-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
14646 // CHECK17-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
14647 // CHECK17-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 9
14648 // CHECK17-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
14649 // CHECK17:       cond.true:
14650 // CHECK17-NEXT:    br label [[COND_END:%.*]]
14651 // CHECK17:       cond.false:
14652 // CHECK17-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
14653 // CHECK17-NEXT:    br label [[COND_END]]
14654 // CHECK17:       cond.end:
14655 // CHECK17-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
14656 // CHECK17-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
14657 // CHECK17-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
14658 // CHECK17-NEXT:    store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
14659 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
14660 // CHECK17:       omp.inner.for.cond:
14661 // CHECK17-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
14662 // CHECK17-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
14663 // CHECK17-NEXT:    [[CMP3:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
14664 // CHECK17-NEXT:    br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
14665 // CHECK17:       omp.inner.for.body:
14666 // CHECK17-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
14667 // CHECK17-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
14668 // CHECK17-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
14669 // CHECK17-NEXT:    store i32 [[ADD]], i32* [[I]], align 4
14670 // CHECK17-NEXT:    [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8
14671 // CHECK17-NEXT:    [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double
14672 // CHECK17-NEXT:    [[ADD5:%.*]] = fadd double [[CONV4]], 1.500000e+00
14673 // CHECK17-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
14674 // CHECK17-NEXT:    store double [[ADD5]], double* [[A]], align 8
14675 // CHECK17-NEXT:    [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
14676 // CHECK17-NEXT:    [[TMP13:%.*]] = load double, double* [[A6]], align 8
14677 // CHECK17-NEXT:    [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00
14678 // CHECK17-NEXT:    store double [[INC]], double* [[A6]], align 8
14679 // CHECK17-NEXT:    [[CONV7:%.*]] = fptosi double [[INC]] to i16
14680 // CHECK17-NEXT:    [[TMP14:%.*]] = mul nsw i64 1, [[TMP2]]
14681 // CHECK17-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP14]]
14682 // CHECK17-NEXT:    [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
14683 // CHECK17-NEXT:    store i16 [[CONV7]], i16* [[ARRAYIDX8]], align 2
14684 // CHECK17-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
14685 // CHECK17:       omp.body.continue:
14686 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
14687 // CHECK17:       omp.inner.for.inc:
14688 // CHECK17-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
14689 // CHECK17-NEXT:    [[ADD9:%.*]] = add nsw i32 [[TMP15]], 1
14690 // CHECK17-NEXT:    store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4
14691 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_COND]]
14692 // CHECK17:       omp.inner.for.end:
14693 // CHECK17-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
14694 // CHECK17:       omp.loop.exit:
14695 // CHECK17-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
14696 // CHECK17-NEXT:    ret void
14697 //
14698 //
14699 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200
14700 // CHECK17-SAME: (i64 [[N:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
14701 // CHECK17-NEXT:  entry:
14702 // CHECK17-NEXT:    [[N_ADDR:%.*]] = alloca i64, align 8
14703 // CHECK17-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
14704 // CHECK17-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
14705 // CHECK17-NEXT:    [[AAA_ADDR:%.*]] = alloca i64, align 8
14706 // CHECK17-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
14707 // CHECK17-NEXT:    [[N_CASTED:%.*]] = alloca i64, align 8
14708 // CHECK17-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
14709 // CHECK17-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
14710 // CHECK17-NEXT:    [[AAA_CASTED:%.*]] = alloca i64, align 8
14711 // CHECK17-NEXT:    store i64 [[N]], i64* [[N_ADDR]], align 8
14712 // CHECK17-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
14713 // CHECK17-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
14714 // CHECK17-NEXT:    store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
14715 // CHECK17-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
14716 // CHECK17-NEXT:    [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
14717 // CHECK17-NEXT:    [[CONV1:%.*]] = bitcast i64* [[A_ADDR]] to i32*
14718 // CHECK17-NEXT:    [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
14719 // CHECK17-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
14720 // CHECK17-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
14721 // CHECK17-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
14722 // CHECK17-NEXT:    [[CONV4:%.*]] = bitcast i64* [[N_CASTED]] to i32*
14723 // CHECK17-NEXT:    store i32 [[TMP1]], i32* [[CONV4]], align 4
14724 // CHECK17-NEXT:    [[TMP2:%.*]] = load i64, i64* [[N_CASTED]], align 8
14725 // CHECK17-NEXT:    [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 8
14726 // CHECK17-NEXT:    [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
14727 // CHECK17-NEXT:    store i32 [[TMP3]], i32* [[CONV5]], align 4
14728 // CHECK17-NEXT:    [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8
14729 // CHECK17-NEXT:    [[TMP5:%.*]] = load i16, i16* [[CONV2]], align 8
14730 // CHECK17-NEXT:    [[CONV6:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
14731 // CHECK17-NEXT:    store i16 [[TMP5]], i16* [[CONV6]], align 2
14732 // CHECK17-NEXT:    [[TMP6:%.*]] = load i64, i64* [[AA_CASTED]], align 8
14733 // CHECK17-NEXT:    [[TMP7:%.*]] = load i8, i8* [[CONV3]], align 8
14734 // CHECK17-NEXT:    [[CONV7:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
14735 // CHECK17-NEXT:    store i8 [[TMP7]], i8* [[CONV7]], align 1
14736 // CHECK17-NEXT:    [[TMP8:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
14737 // CHECK17-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, [10 x i32]*)* @.omp_outlined..13 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]], [10 x i32]* [[TMP0]])
14738 // CHECK17-NEXT:    ret void
14739 //
14740 //
14741 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..13
14742 // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
14743 // CHECK17-NEXT:  entry:
14744 // CHECK17-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
14745 // CHECK17-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
14746 // CHECK17-NEXT:    [[N_ADDR:%.*]] = alloca i64, align 8
14747 // CHECK17-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
14748 // CHECK17-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
14749 // CHECK17-NEXT:    [[AAA_ADDR:%.*]] = alloca i64, align 8
14750 // CHECK17-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
14751 // CHECK17-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
14752 // CHECK17-NEXT:    [[TMP:%.*]] = alloca i32, align 4
14753 // CHECK17-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
14754 // CHECK17-NEXT:    [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4
14755 // CHECK17-NEXT:    [[DOTCAPTURE_EXPR_5:%.*]] = alloca i32, align 4
14756 // CHECK17-NEXT:    [[I:%.*]] = alloca i32, align 4
14757 // CHECK17-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
14758 // CHECK17-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
14759 // CHECK17-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
14760 // CHECK17-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
14761 // CHECK17-NEXT:    [[I8:%.*]] = alloca i32, align 4
14762 // CHECK17-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
14763 // CHECK17-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
14764 // CHECK17-NEXT:    store i64 [[N]], i64* [[N_ADDR]], align 8
14765 // CHECK17-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
14766 // CHECK17-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
14767 // CHECK17-NEXT:    store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
14768 // CHECK17-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
14769 // CHECK17-NEXT:    [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
14770 // CHECK17-NEXT:    [[CONV1:%.*]] = bitcast i64* [[A_ADDR]] to i32*
14771 // CHECK17-NEXT:    [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
14772 // CHECK17-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
14773 // CHECK17-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
14774 // CHECK17-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV1]], align 8
14775 // CHECK17-NEXT:    store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
14776 // CHECK17-NEXT:    [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
14777 // CHECK17-NEXT:    store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_4]], align 4
14778 // CHECK17-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4
14779 // CHECK17-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
14780 // CHECK17-NEXT:    [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]]
14781 // CHECK17-NEXT:    [[SUB6:%.*]] = sub i32 [[SUB]], 1
14782 // CHECK17-NEXT:    [[ADD:%.*]] = add i32 [[SUB6]], 1
14783 // CHECK17-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], 1
14784 // CHECK17-NEXT:    [[SUB7:%.*]] = sub i32 [[DIV]], 1
14785 // CHECK17-NEXT:    store i32 [[SUB7]], i32* [[DOTCAPTURE_EXPR_5]], align 4
14786 // CHECK17-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
14787 // CHECK17-NEXT:    store i32 [[TMP5]], i32* [[I]], align 4
14788 // CHECK17-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
14789 // CHECK17-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4
14790 // CHECK17-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]]
14791 // CHECK17-NEXT:    br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
14792 // CHECK17:       omp.precond.then:
14793 // CHECK17-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
14794 // CHECK17-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4
14795 // CHECK17-NEXT:    store i32 [[TMP8]], i32* [[DOTOMP_UB]], align 4
14796 // CHECK17-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
14797 // CHECK17-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
14798 // CHECK17-NEXT:    [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
14799 // CHECK17-NEXT:    [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
14800 // CHECK17-NEXT:    call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
14801 // CHECK17-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
14802 // CHECK17-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4
14803 // CHECK17-NEXT:    [[CMP9:%.*]] = icmp ugt i32 [[TMP11]], [[TMP12]]
14804 // CHECK17-NEXT:    br i1 [[CMP9]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
14805 // CHECK17:       cond.true:
14806 // CHECK17-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4
14807 // CHECK17-NEXT:    br label [[COND_END:%.*]]
14808 // CHECK17:       cond.false:
14809 // CHECK17-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
14810 // CHECK17-NEXT:    br label [[COND_END]]
14811 // CHECK17:       cond.end:
14812 // CHECK17-NEXT:    [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ]
14813 // CHECK17-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
14814 // CHECK17-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
14815 // CHECK17-NEXT:    store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4
14816 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
14817 // CHECK17:       omp.inner.for.cond:
14818 // CHECK17-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
14819 // CHECK17-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
14820 // CHECK17-NEXT:    [[ADD10:%.*]] = add i32 [[TMP17]], 1
14821 // CHECK17-NEXT:    [[CMP11:%.*]] = icmp ult i32 [[TMP16]], [[ADD10]]
14822 // CHECK17-NEXT:    br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
14823 // CHECK17:       omp.inner.for.body:
14824 // CHECK17-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
14825 // CHECK17-NEXT:    [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
14826 // CHECK17-NEXT:    [[MUL:%.*]] = mul i32 [[TMP19]], 1
14827 // CHECK17-NEXT:    [[ADD12:%.*]] = add i32 [[TMP18]], [[MUL]]
14828 // CHECK17-NEXT:    store i32 [[ADD12]], i32* [[I8]], align 4
14829 // CHECK17-NEXT:    [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 8
14830 // CHECK17-NEXT:    [[ADD13:%.*]] = add nsw i32 [[TMP20]], 1
14831 // CHECK17-NEXT:    store i32 [[ADD13]], i32* [[CONV1]], align 8
14832 // CHECK17-NEXT:    [[TMP21:%.*]] = load i16, i16* [[CONV2]], align 8
14833 // CHECK17-NEXT:    [[CONV14:%.*]] = sext i16 [[TMP21]] to i32
14834 // CHECK17-NEXT:    [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1
14835 // CHECK17-NEXT:    [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16
14836 // CHECK17-NEXT:    store i16 [[CONV16]], i16* [[CONV2]], align 8
14837 // CHECK17-NEXT:    [[TMP22:%.*]] = load i8, i8* [[CONV3]], align 8
14838 // CHECK17-NEXT:    [[CONV17:%.*]] = sext i8 [[TMP22]] to i32
14839 // CHECK17-NEXT:    [[ADD18:%.*]] = add nsw i32 [[CONV17]], 1
14840 // CHECK17-NEXT:    [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8
14841 // CHECK17-NEXT:    store i8 [[CONV19]], i8* [[CONV3]], align 8
14842 // CHECK17-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
14843 // CHECK17-NEXT:    [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
14844 // CHECK17-NEXT:    [[ADD20:%.*]] = add nsw i32 [[TMP23]], 1
14845 // CHECK17-NEXT:    store i32 [[ADD20]], i32* [[ARRAYIDX]], align 4
14846 // CHECK17-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
14847 // CHECK17:       omp.body.continue:
14848 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
14849 // CHECK17:       omp.inner.for.inc:
14850 // CHECK17-NEXT:    [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
14851 // CHECK17-NEXT:    [[ADD21:%.*]] = add i32 [[TMP24]], 1
14852 // CHECK17-NEXT:    store i32 [[ADD21]], i32* [[DOTOMP_IV]], align 4
14853 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_COND]]
14854 // CHECK17:       omp.inner.for.end:
14855 // CHECK17-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
14856 // CHECK17:       omp.loop.exit:
14857 // CHECK17-NEXT:    [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
14858 // CHECK17-NEXT:    [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4
14859 // CHECK17-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]])
14860 // CHECK17-NEXT:    br label [[OMP_PRECOND_END]]
14861 // CHECK17:       omp.precond.end:
14862 // CHECK17-NEXT:    ret void
14863 //
14864 //
14865 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183
14866 // CHECK17-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
14867 // CHECK17-NEXT:  entry:
14868 // CHECK17-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
14869 // CHECK17-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
14870 // CHECK17-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
14871 // CHECK17-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
14872 // CHECK17-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
14873 // CHECK17-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
14874 // CHECK17-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
14875 // CHECK17-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
14876 // CHECK17-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
14877 // CHECK17-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
14878 // CHECK17-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
14879 // CHECK17-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
14880 // CHECK17-NEXT:    [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
14881 // CHECK17-NEXT:    store i32 [[TMP1]], i32* [[CONV2]], align 4
14882 // CHECK17-NEXT:    [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
14883 // CHECK17-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
14884 // CHECK17-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
14885 // CHECK17-NEXT:    store i16 [[TMP3]], i16* [[CONV3]], align 2
14886 // CHECK17-NEXT:    [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
14887 // CHECK17-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]])
14888 // CHECK17-NEXT:    ret void
14889 //
14890 //
14891 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..16
14892 // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
14893 // CHECK17-NEXT:  entry:
14894 // CHECK17-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
14895 // CHECK17-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
14896 // CHECK17-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
14897 // CHECK17-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
14898 // CHECK17-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
14899 // CHECK17-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
14900 // CHECK17-NEXT:    [[TMP:%.*]] = alloca i32, align 4
14901 // CHECK17-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
14902 // CHECK17-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
14903 // CHECK17-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
14904 // CHECK17-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
14905 // CHECK17-NEXT:    [[I:%.*]] = alloca i32, align 4
14906 // CHECK17-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
14907 // CHECK17-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
14908 // CHECK17-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
14909 // CHECK17-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
14910 // CHECK17-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
14911 // CHECK17-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
14912 // CHECK17-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
14913 // CHECK17-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
14914 // CHECK17-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
14915 // CHECK17-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
14916 // CHECK17-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
14917 // CHECK17-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
14918 // CHECK17-NEXT:    [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
14919 // CHECK17-NEXT:    [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
14920 // CHECK17-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
14921 // CHECK17-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
14922 // CHECK17-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9
14923 // CHECK17-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
14924 // CHECK17:       cond.true:
14925 // CHECK17-NEXT:    br label [[COND_END:%.*]]
14926 // CHECK17:       cond.false:
14927 // CHECK17-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
14928 // CHECK17-NEXT:    br label [[COND_END]]
14929 // CHECK17:       cond.end:
14930 // CHECK17-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
14931 // CHECK17-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
14932 // CHECK17-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
14933 // CHECK17-NEXT:    store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
14934 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
14935 // CHECK17:       omp.inner.for.cond:
14936 // CHECK17-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
14937 // CHECK17-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
14938 // CHECK17-NEXT:    [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
14939 // CHECK17-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
14940 // CHECK17:       omp.inner.for.body:
14941 // CHECK17-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
14942 // CHECK17-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
14943 // CHECK17-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
14944 // CHECK17-NEXT:    store i32 [[ADD]], i32* [[I]], align 4
14945 // CHECK17-NEXT:    [[TMP9:%.*]] = load i32, i32* [[CONV]], align 8
14946 // CHECK17-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1
14947 // CHECK17-NEXT:    store i32 [[ADD3]], i32* [[CONV]], align 8
14948 // CHECK17-NEXT:    [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 8
14949 // CHECK17-NEXT:    [[CONV4:%.*]] = sext i16 [[TMP10]] to i32
14950 // CHECK17-NEXT:    [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
14951 // CHECK17-NEXT:    [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
14952 // CHECK17-NEXT:    store i16 [[CONV6]], i16* [[CONV1]], align 8
14953 // CHECK17-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
14954 // CHECK17-NEXT:    [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
14955 // CHECK17-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1
14956 // CHECK17-NEXT:    store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4
14957 // CHECK17-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
14958 // CHECK17:       omp.body.continue:
14959 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
14960 // CHECK17:       omp.inner.for.inc:
14961 // CHECK17-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
14962 // CHECK17-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP12]], 1
14963 // CHECK17-NEXT:    store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4
14964 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_COND]]
14965 // CHECK17:       omp.inner.for.end:
14966 // CHECK17-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
14967 // CHECK17:       omp.loop.exit:
14968 // CHECK17-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
14969 // CHECK17-NEXT:    ret void
14970 //
14971 //
14972 // CHECK17-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
14973 // CHECK17-SAME: () #[[ATTR4]] {
14974 // CHECK17-NEXT:  entry:
14975 // CHECK17-NEXT:    call void @__tgt_register_requires(i64 1)
14976 // CHECK17-NEXT:    ret void
14977 //
14978 //
14979 // CHECK18-LABEL: define {{[^@]+}}@_Z3fooi
14980 // CHECK18-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] {
14981 // CHECK18-NEXT:  entry:
14982 // CHECK18-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
14983 // CHECK18-NEXT:    [[A:%.*]] = alloca i32, align 4
14984 // CHECK18-NEXT:    [[AA:%.*]] = alloca i16, align 2
14985 // CHECK18-NEXT:    [[B:%.*]] = alloca [10 x float], align 4
14986 // CHECK18-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 8
14987 // CHECK18-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
14988 // CHECK18-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 8
14989 // CHECK18-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i64, align 8
14990 // CHECK18-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8
14991 // CHECK18-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
14992 // CHECK18-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
14993 // CHECK18-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
14994 // CHECK18-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
14995 // CHECK18-NEXT:    [[DOTCAPTURE_EXPR__CASTED4:%.*]] = alloca i64, align 8
14996 // CHECK18-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8
14997 // CHECK18-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8
14998 // CHECK18-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8
14999 // CHECK18-NEXT:    [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4
15000 // CHECK18-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
15001 // CHECK18-NEXT:    [[AA_CASTED7:%.*]] = alloca i64, align 8
15002 // CHECK18-NEXT:    [[DOTOFFLOAD_BASEPTRS9:%.*]] = alloca [1 x i8*], align 8
15003 // CHECK18-NEXT:    [[DOTOFFLOAD_PTRS10:%.*]] = alloca [1 x i8*], align 8
15004 // CHECK18-NEXT:    [[DOTOFFLOAD_MAPPERS11:%.*]] = alloca [1 x i8*], align 8
15005 // CHECK18-NEXT:    [[TMP:%.*]] = alloca i32, align 4
15006 // CHECK18-NEXT:    [[A_CASTED12:%.*]] = alloca i64, align 8
15007 // CHECK18-NEXT:    [[AA_CASTED14:%.*]] = alloca i64, align 8
15008 // CHECK18-NEXT:    [[DOTOFFLOAD_BASEPTRS16:%.*]] = alloca [2 x i8*], align 8
15009 // CHECK18-NEXT:    [[DOTOFFLOAD_PTRS17:%.*]] = alloca [2 x i8*], align 8
15010 // CHECK18-NEXT:    [[DOTOFFLOAD_MAPPERS18:%.*]] = alloca [2 x i8*], align 8
15011 // CHECK18-NEXT:    [[_TMP19:%.*]] = alloca i32, align 4
15012 // CHECK18-NEXT:    [[DOTCAPTURE_EXPR_22:%.*]] = alloca i32, align 4
15013 // CHECK18-NEXT:    [[A_CASTED23:%.*]] = alloca i64, align 8
15014 // CHECK18-NEXT:    [[DOTCAPTURE_EXPR__CASTED25:%.*]] = alloca i64, align 8
15015 // CHECK18-NEXT:    [[DOTOFFLOAD_BASEPTRS29:%.*]] = alloca [10 x i8*], align 8
15016 // CHECK18-NEXT:    [[DOTOFFLOAD_PTRS30:%.*]] = alloca [10 x i8*], align 8
15017 // CHECK18-NEXT:    [[DOTOFFLOAD_MAPPERS31:%.*]] = alloca [10 x i8*], align 8
15018 // CHECK18-NEXT:    [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 8
15019 // CHECK18-NEXT:    [[_TMP32:%.*]] = alloca i32, align 4
15020 // CHECK18-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]])
15021 // CHECK18-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
15022 // CHECK18-NEXT:    store i32 0, i32* [[A]], align 4
15023 // CHECK18-NEXT:    store i16 0, i16* [[AA]], align 2
15024 // CHECK18-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
15025 // CHECK18-NEXT:    [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
15026 // CHECK18-NEXT:    [[TMP3:%.*]] = call i8* @llvm.stacksave()
15027 // CHECK18-NEXT:    store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8
15028 // CHECK18-NEXT:    [[VLA:%.*]] = alloca float, i64 [[TMP2]], align 4
15029 // CHECK18-NEXT:    store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8
15030 // CHECK18-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
15031 // CHECK18-NEXT:    [[TMP5:%.*]] = zext i32 [[TMP4]] to i64
15032 // CHECK18-NEXT:    [[TMP6:%.*]] = mul nuw i64 5, [[TMP5]]
15033 // CHECK18-NEXT:    [[VLA1:%.*]] = alloca double, i64 [[TMP6]], align 8
15034 // CHECK18-NEXT:    store i64 [[TMP5]], i64* [[__VLA_EXPR1]], align 8
15035 // CHECK18-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
15036 // CHECK18-NEXT:    store i32 [[TMP7]], i32* [[DOTCAPTURE_EXPR_]], align 4
15037 // CHECK18-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
15038 // CHECK18-NEXT:    store i32 [[TMP8]], i32* [[DOTCAPTURE_EXPR_2]], align 4
15039 // CHECK18-NEXT:    [[TMP9:%.*]] = load i16, i16* [[AA]], align 2
15040 // CHECK18-NEXT:    [[CONV:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
15041 // CHECK18-NEXT:    store i16 [[TMP9]], i16* [[CONV]], align 2
15042 // CHECK18-NEXT:    [[TMP10:%.*]] = load i64, i64* [[AA_CASTED]], align 8
15043 // CHECK18-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
15044 // CHECK18-NEXT:    [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
15045 // CHECK18-NEXT:    store i32 [[TMP11]], i32* [[CONV3]], align 4
15046 // CHECK18-NEXT:    [[TMP12:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
15047 // CHECK18-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
15048 // CHECK18-NEXT:    [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED4]] to i32*
15049 // CHECK18-NEXT:    store i32 [[TMP13]], i32* [[CONV5]], align 4
15050 // CHECK18-NEXT:    [[TMP14:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED4]], align 8
15051 // CHECK18-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
15052 // CHECK18-NEXT:    [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i64*
15053 // CHECK18-NEXT:    store i64 [[TMP10]], i64* [[TMP16]], align 8
15054 // CHECK18-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
15055 // CHECK18-NEXT:    [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64*
15056 // CHECK18-NEXT:    store i64 [[TMP10]], i64* [[TMP18]], align 8
15057 // CHECK18-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
15058 // CHECK18-NEXT:    store i8* null, i8** [[TMP19]], align 8
15059 // CHECK18-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
15060 // CHECK18-NEXT:    [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i64*
15061 // CHECK18-NEXT:    store i64 [[TMP12]], i64* [[TMP21]], align 8
15062 // CHECK18-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
15063 // CHECK18-NEXT:    [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i64*
15064 // CHECK18-NEXT:    store i64 [[TMP12]], i64* [[TMP23]], align 8
15065 // CHECK18-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
15066 // CHECK18-NEXT:    store i8* null, i8** [[TMP24]], align 8
15067 // CHECK18-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
15068 // CHECK18-NEXT:    [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i64*
15069 // CHECK18-NEXT:    store i64 [[TMP14]], i64* [[TMP26]], align 8
15070 // CHECK18-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
15071 // CHECK18-NEXT:    [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i64*
15072 // CHECK18-NEXT:    store i64 [[TMP14]], i64* [[TMP28]], align 8
15073 // CHECK18-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
15074 // CHECK18-NEXT:    store i8* null, i8** [[TMP29]], align 8
15075 // CHECK18-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
15076 // CHECK18-NEXT:    [[TMP31:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
15077 // CHECK18-NEXT:    [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 0
15078 // CHECK18-NEXT:    [[TMP33:%.*]] = load i16, i16* [[AA]], align 2
15079 // CHECK18-NEXT:    store i16 [[TMP33]], i16* [[TMP32]], align 4
15080 // CHECK18-NEXT:    [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 1
15081 // CHECK18-NEXT:    [[TMP35:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
15082 // CHECK18-NEXT:    store i32 [[TMP35]], i32* [[TMP34]], align 4
15083 // CHECK18-NEXT:    [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 2
15084 // CHECK18-NEXT:    [[TMP37:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
15085 // CHECK18-NEXT:    store i32 [[TMP37]], i32* [[TMP36]], align 4
15086 // CHECK18-NEXT:    [[TMP38:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 1, i64 120, i64 12, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1)
15087 // CHECK18-NEXT:    [[TMP39:%.*]] = bitcast i8* [[TMP38]] to %struct.kmp_task_t_with_privates*
15088 // CHECK18-NEXT:    [[TMP40:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP39]], i32 0, i32 0
15089 // CHECK18-NEXT:    [[TMP41:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP40]], i32 0, i32 0
15090 // CHECK18-NEXT:    [[TMP42:%.*]] = load i8*, i8** [[TMP41]], align 8
15091 // CHECK18-NEXT:    [[TMP43:%.*]] = bitcast %struct.anon* [[AGG_CAPTURED]] to i8*
15092 // CHECK18-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP42]], i8* align 4 [[TMP43]], i64 12, i1 false)
15093 // CHECK18-NEXT:    [[TMP44:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP39]], i32 0, i32 1
15094 // CHECK18-NEXT:    [[TMP45:%.*]] = bitcast i8* [[TMP42]] to %struct.anon*
15095 // CHECK18-NEXT:    [[TMP46:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 0
15096 // CHECK18-NEXT:    [[TMP47:%.*]] = bitcast [3 x i8*]* [[TMP46]] to i8*
15097 // CHECK18-NEXT:    [[TMP48:%.*]] = bitcast i8** [[TMP30]] to i8*
15098 // CHECK18-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP47]], i8* align 8 [[TMP48]], i64 24, i1 false)
15099 // CHECK18-NEXT:    [[TMP49:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 1
15100 // CHECK18-NEXT:    [[TMP50:%.*]] = bitcast [3 x i8*]* [[TMP49]] to i8*
15101 // CHECK18-NEXT:    [[TMP51:%.*]] = bitcast i8** [[TMP31]] to i8*
15102 // CHECK18-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP50]], i8* align 8 [[TMP51]], i64 24, i1 false)
15103 // CHECK18-NEXT:    [[TMP52:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 2
15104 // CHECK18-NEXT:    [[TMP53:%.*]] = bitcast [3 x i64]* [[TMP52]] to i8*
15105 // CHECK18-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP53]], i8* align 8 bitcast ([3 x i64]* @.offload_sizes to i8*), i64 24, i1 false)
15106 // CHECK18-NEXT:    [[TMP54:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 3
15107 // CHECK18-NEXT:    [[TMP55:%.*]] = load i16, i16* [[AA]], align 2
15108 // CHECK18-NEXT:    store i16 [[TMP55]], i16* [[TMP54]], align 8
15109 // CHECK18-NEXT:    [[TMP56:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i8* [[TMP38]])
15110 // CHECK18-NEXT:    [[TMP57:%.*]] = load i32, i32* [[A]], align 4
15111 // CHECK18-NEXT:    [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32*
15112 // CHECK18-NEXT:    store i32 [[TMP57]], i32* [[CONV6]], align 4
15113 // CHECK18-NEXT:    [[TMP58:%.*]] = load i64, i64* [[A_CASTED]], align 8
15114 // CHECK18-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l107(i64 [[TMP58]]) #[[ATTR3:[0-9]+]]
15115 // CHECK18-NEXT:    [[TMP59:%.*]] = load i16, i16* [[AA]], align 2
15116 // CHECK18-NEXT:    [[CONV8:%.*]] = bitcast i64* [[AA_CASTED7]] to i16*
15117 // CHECK18-NEXT:    store i16 [[TMP59]], i16* [[CONV8]], align 2
15118 // CHECK18-NEXT:    [[TMP60:%.*]] = load i64, i64* [[AA_CASTED7]], align 8
15119 // CHECK18-NEXT:    [[TMP61:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS9]], i32 0, i32 0
15120 // CHECK18-NEXT:    [[TMP62:%.*]] = bitcast i8** [[TMP61]] to i64*
15121 // CHECK18-NEXT:    store i64 [[TMP60]], i64* [[TMP62]], align 8
15122 // CHECK18-NEXT:    [[TMP63:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS10]], i32 0, i32 0
15123 // CHECK18-NEXT:    [[TMP64:%.*]] = bitcast i8** [[TMP63]] to i64*
15124 // CHECK18-NEXT:    store i64 [[TMP60]], i64* [[TMP64]], align 8
15125 // CHECK18-NEXT:    [[TMP65:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS11]], i64 0, i64 0
15126 // CHECK18-NEXT:    store i8* null, i8** [[TMP65]], align 8
15127 // CHECK18-NEXT:    [[TMP66:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS9]], i32 0, i32 0
15128 // CHECK18-NEXT:    [[TMP67:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS10]], i32 0, i32 0
15129 // CHECK18-NEXT:    call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10)
15130 // CHECK18-NEXT:    [[TMP68:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113.region_id, i32 1, i8** [[TMP66]], i8** [[TMP67]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.4, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.5, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
15131 // CHECK18-NEXT:    [[TMP69:%.*]] = icmp ne i32 [[TMP68]], 0
15132 // CHECK18-NEXT:    br i1 [[TMP69]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
15133 // CHECK18:       omp_offload.failed:
15134 // CHECK18-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113(i64 [[TMP60]]) #[[ATTR3]]
15135 // CHECK18-NEXT:    br label [[OMP_OFFLOAD_CONT]]
15136 // CHECK18:       omp_offload.cont:
15137 // CHECK18-NEXT:    [[TMP70:%.*]] = load i32, i32* [[A]], align 4
15138 // CHECK18-NEXT:    [[CONV13:%.*]] = bitcast i64* [[A_CASTED12]] to i32*
15139 // CHECK18-NEXT:    store i32 [[TMP70]], i32* [[CONV13]], align 4
15140 // CHECK18-NEXT:    [[TMP71:%.*]] = load i64, i64* [[A_CASTED12]], align 8
15141 // CHECK18-NEXT:    [[TMP72:%.*]] = load i16, i16* [[AA]], align 2
15142 // CHECK18-NEXT:    [[CONV15:%.*]] = bitcast i64* [[AA_CASTED14]] to i16*
15143 // CHECK18-NEXT:    store i16 [[TMP72]], i16* [[CONV15]], align 2
15144 // CHECK18-NEXT:    [[TMP73:%.*]] = load i64, i64* [[AA_CASTED14]], align 8
15145 // CHECK18-NEXT:    [[TMP74:%.*]] = load i32, i32* [[N_ADDR]], align 4
15146 // CHECK18-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP74]], 10
15147 // CHECK18-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
15148 // CHECK18:       omp_if.then:
15149 // CHECK18-NEXT:    [[TMP75:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 0
15150 // CHECK18-NEXT:    [[TMP76:%.*]] = bitcast i8** [[TMP75]] to i64*
15151 // CHECK18-NEXT:    store i64 [[TMP71]], i64* [[TMP76]], align 8
15152 // CHECK18-NEXT:    [[TMP77:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 0
15153 // CHECK18-NEXT:    [[TMP78:%.*]] = bitcast i8** [[TMP77]] to i64*
15154 // CHECK18-NEXT:    store i64 [[TMP71]], i64* [[TMP78]], align 8
15155 // CHECK18-NEXT:    [[TMP79:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 0
15156 // CHECK18-NEXT:    store i8* null, i8** [[TMP79]], align 8
15157 // CHECK18-NEXT:    [[TMP80:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 1
15158 // CHECK18-NEXT:    [[TMP81:%.*]] = bitcast i8** [[TMP80]] to i64*
15159 // CHECK18-NEXT:    store i64 [[TMP73]], i64* [[TMP81]], align 8
15160 // CHECK18-NEXT:    [[TMP82:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 1
15161 // CHECK18-NEXT:    [[TMP83:%.*]] = bitcast i8** [[TMP82]] to i64*
15162 // CHECK18-NEXT:    store i64 [[TMP73]], i64* [[TMP83]], align 8
15163 // CHECK18-NEXT:    [[TMP84:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 1
15164 // CHECK18-NEXT:    store i8* null, i8** [[TMP84]], align 8
15165 // CHECK18-NEXT:    [[TMP85:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 0
15166 // CHECK18-NEXT:    [[TMP86:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 0
15167 // CHECK18-NEXT:    call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10)
15168 // CHECK18-NEXT:    [[TMP87:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120.region_id, i32 2, i8** [[TMP85]], i8** [[TMP86]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.7, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.8, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
15169 // CHECK18-NEXT:    [[TMP88:%.*]] = icmp ne i32 [[TMP87]], 0
15170 // CHECK18-NEXT:    br i1 [[TMP88]], label [[OMP_OFFLOAD_FAILED20:%.*]], label [[OMP_OFFLOAD_CONT21:%.*]]
15171 // CHECK18:       omp_offload.failed20:
15172 // CHECK18-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120(i64 [[TMP71]], i64 [[TMP73]]) #[[ATTR3]]
15173 // CHECK18-NEXT:    br label [[OMP_OFFLOAD_CONT21]]
15174 // CHECK18:       omp_offload.cont21:
15175 // CHECK18-NEXT:    br label [[OMP_IF_END:%.*]]
15176 // CHECK18:       omp_if.else:
15177 // CHECK18-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120(i64 [[TMP71]], i64 [[TMP73]]) #[[ATTR3]]
15178 // CHECK18-NEXT:    br label [[OMP_IF_END]]
15179 // CHECK18:       omp_if.end:
15180 // CHECK18-NEXT:    [[TMP89:%.*]] = load i32, i32* [[N_ADDR]], align 4
15181 // CHECK18-NEXT:    store i32 [[TMP89]], i32* [[DOTCAPTURE_EXPR_22]], align 4
15182 // CHECK18-NEXT:    [[TMP90:%.*]] = load i32, i32* [[A]], align 4
15183 // CHECK18-NEXT:    [[CONV24:%.*]] = bitcast i64* [[A_CASTED23]] to i32*
15184 // CHECK18-NEXT:    store i32 [[TMP90]], i32* [[CONV24]], align 4
15185 // CHECK18-NEXT:    [[TMP91:%.*]] = load i64, i64* [[A_CASTED23]], align 8
15186 // CHECK18-NEXT:    [[TMP92:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_22]], align 4
15187 // CHECK18-NEXT:    [[CONV26:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED25]] to i32*
15188 // CHECK18-NEXT:    store i32 [[TMP92]], i32* [[CONV26]], align 4
15189 // CHECK18-NEXT:    [[TMP93:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED25]], align 8
15190 // CHECK18-NEXT:    [[TMP94:%.*]] = load i32, i32* [[N_ADDR]], align 4
15191 // CHECK18-NEXT:    [[CMP27:%.*]] = icmp sgt i32 [[TMP94]], 20
15192 // CHECK18-NEXT:    br i1 [[CMP27]], label [[OMP_IF_THEN28:%.*]], label [[OMP_IF_ELSE35:%.*]]
15193 // CHECK18:       omp_if.then28:
15194 // CHECK18-NEXT:    [[TMP95:%.*]] = mul nuw i64 [[TMP2]], 4
15195 // CHECK18-NEXT:    [[TMP96:%.*]] = mul nuw i64 5, [[TMP5]]
15196 // CHECK18-NEXT:    [[TMP97:%.*]] = mul nuw i64 [[TMP96]], 8
15197 // CHECK18-NEXT:    [[TMP98:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS29]], i32 0, i32 0
15198 // CHECK18-NEXT:    [[TMP99:%.*]] = bitcast i8** [[TMP98]] to i64*
15199 // CHECK18-NEXT:    store i64 [[TMP91]], i64* [[TMP99]], align 8
15200 // CHECK18-NEXT:    [[TMP100:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS30]], i32 0, i32 0
15201 // CHECK18-NEXT:    [[TMP101:%.*]] = bitcast i8** [[TMP100]] to i64*
15202 // CHECK18-NEXT:    store i64 [[TMP91]], i64* [[TMP101]], align 8
15203 // CHECK18-NEXT:    [[TMP102:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
15204 // CHECK18-NEXT:    store i64 4, i64* [[TMP102]], align 8
15205 // CHECK18-NEXT:    [[TMP103:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS31]], i64 0, i64 0
15206 // CHECK18-NEXT:    store i8* null, i8** [[TMP103]], align 8
15207 // CHECK18-NEXT:    [[TMP104:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS29]], i32 0, i32 1
15208 // CHECK18-NEXT:    [[TMP105:%.*]] = bitcast i8** [[TMP104]] to [10 x float]**
15209 // CHECK18-NEXT:    store [10 x float]* [[B]], [10 x float]** [[TMP105]], align 8
15210 // CHECK18-NEXT:    [[TMP106:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS30]], i32 0, i32 1
15211 // CHECK18-NEXT:    [[TMP107:%.*]] = bitcast i8** [[TMP106]] to [10 x float]**
15212 // CHECK18-NEXT:    store [10 x float]* [[B]], [10 x float]** [[TMP107]], align 8
15213 // CHECK18-NEXT:    [[TMP108:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1
15214 // CHECK18-NEXT:    store i64 40, i64* [[TMP108]], align 8
15215 // CHECK18-NEXT:    [[TMP109:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS31]], i64 0, i64 1
15216 // CHECK18-NEXT:    store i8* null, i8** [[TMP109]], align 8
15217 // CHECK18-NEXT:    [[TMP110:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS29]], i32 0, i32 2
15218 // CHECK18-NEXT:    [[TMP111:%.*]] = bitcast i8** [[TMP110]] to i64*
15219 // CHECK18-NEXT:    store i64 [[TMP2]], i64* [[TMP111]], align 8
15220 // CHECK18-NEXT:    [[TMP112:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS30]], i32 0, i32 2
15221 // CHECK18-NEXT:    [[TMP113:%.*]] = bitcast i8** [[TMP112]] to i64*
15222 // CHECK18-NEXT:    store i64 [[TMP2]], i64* [[TMP113]], align 8
15223 // CHECK18-NEXT:    [[TMP114:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2
15224 // CHECK18-NEXT:    store i64 8, i64* [[TMP114]], align 8
15225 // CHECK18-NEXT:    [[TMP115:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS31]], i64 0, i64 2
15226 // CHECK18-NEXT:    store i8* null, i8** [[TMP115]], align 8
15227 // CHECK18-NEXT:    [[TMP116:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS29]], i32 0, i32 3
15228 // CHECK18-NEXT:    [[TMP117:%.*]] = bitcast i8** [[TMP116]] to float**
15229 // CHECK18-NEXT:    store float* [[VLA]], float** [[TMP117]], align 8
15230 // CHECK18-NEXT:    [[TMP118:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS30]], i32 0, i32 3
15231 // CHECK18-NEXT:    [[TMP119:%.*]] = bitcast i8** [[TMP118]] to float**
15232 // CHECK18-NEXT:    store float* [[VLA]], float** [[TMP119]], align 8
15233 // CHECK18-NEXT:    [[TMP120:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3
15234 // CHECK18-NEXT:    store i64 [[TMP95]], i64* [[TMP120]], align 8
15235 // CHECK18-NEXT:    [[TMP121:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS31]], i64 0, i64 3
15236 // CHECK18-NEXT:    store i8* null, i8** [[TMP121]], align 8
15237 // CHECK18-NEXT:    [[TMP122:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS29]], i32 0, i32 4
15238 // CHECK18-NEXT:    [[TMP123:%.*]] = bitcast i8** [[TMP122]] to [5 x [10 x double]]**
15239 // CHECK18-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP123]], align 8
15240 // CHECK18-NEXT:    [[TMP124:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS30]], i32 0, i32 4
15241 // CHECK18-NEXT:    [[TMP125:%.*]] = bitcast i8** [[TMP124]] to [5 x [10 x double]]**
15242 // CHECK18-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP125]], align 8
15243 // CHECK18-NEXT:    [[TMP126:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4
15244 // CHECK18-NEXT:    store i64 400, i64* [[TMP126]], align 8
15245 // CHECK18-NEXT:    [[TMP127:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS31]], i64 0, i64 4
15246 // CHECK18-NEXT:    store i8* null, i8** [[TMP127]], align 8
15247 // CHECK18-NEXT:    [[TMP128:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS29]], i32 0, i32 5
15248 // CHECK18-NEXT:    [[TMP129:%.*]] = bitcast i8** [[TMP128]] to i64*
15249 // CHECK18-NEXT:    store i64 5, i64* [[TMP129]], align 8
15250 // CHECK18-NEXT:    [[TMP130:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS30]], i32 0, i32 5
15251 // CHECK18-NEXT:    [[TMP131:%.*]] = bitcast i8** [[TMP130]] to i64*
15252 // CHECK18-NEXT:    store i64 5, i64* [[TMP131]], align 8
15253 // CHECK18-NEXT:    [[TMP132:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 5
15254 // CHECK18-NEXT:    store i64 8, i64* [[TMP132]], align 8
15255 // CHECK18-NEXT:    [[TMP133:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS31]], i64 0, i64 5
15256 // CHECK18-NEXT:    store i8* null, i8** [[TMP133]], align 8
15257 // CHECK18-NEXT:    [[TMP134:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS29]], i32 0, i32 6
15258 // CHECK18-NEXT:    [[TMP135:%.*]] = bitcast i8** [[TMP134]] to i64*
15259 // CHECK18-NEXT:    store i64 [[TMP5]], i64* [[TMP135]], align 8
15260 // CHECK18-NEXT:    [[TMP136:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS30]], i32 0, i32 6
15261 // CHECK18-NEXT:    [[TMP137:%.*]] = bitcast i8** [[TMP136]] to i64*
15262 // CHECK18-NEXT:    store i64 [[TMP5]], i64* [[TMP137]], align 8
15263 // CHECK18-NEXT:    [[TMP138:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 6
15264 // CHECK18-NEXT:    store i64 8, i64* [[TMP138]], align 8
15265 // CHECK18-NEXT:    [[TMP139:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS31]], i64 0, i64 6
15266 // CHECK18-NEXT:    store i8* null, i8** [[TMP139]], align 8
15267 // CHECK18-NEXT:    [[TMP140:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS29]], i32 0, i32 7
15268 // CHECK18-NEXT:    [[TMP141:%.*]] = bitcast i8** [[TMP140]] to double**
15269 // CHECK18-NEXT:    store double* [[VLA1]], double** [[TMP141]], align 8
15270 // CHECK18-NEXT:    [[TMP142:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS30]], i32 0, i32 7
15271 // CHECK18-NEXT:    [[TMP143:%.*]] = bitcast i8** [[TMP142]] to double**
15272 // CHECK18-NEXT:    store double* [[VLA1]], double** [[TMP143]], align 8
15273 // CHECK18-NEXT:    [[TMP144:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7
15274 // CHECK18-NEXT:    store i64 [[TMP97]], i64* [[TMP144]], align 8
15275 // CHECK18-NEXT:    [[TMP145:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS31]], i64 0, i64 7
15276 // CHECK18-NEXT:    store i8* null, i8** [[TMP145]], align 8
15277 // CHECK18-NEXT:    [[TMP146:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS29]], i32 0, i32 8
15278 // CHECK18-NEXT:    [[TMP147:%.*]] = bitcast i8** [[TMP146]] to %struct.TT**
15279 // CHECK18-NEXT:    store %struct.TT* [[D]], %struct.TT** [[TMP147]], align 8
15280 // CHECK18-NEXT:    [[TMP148:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS30]], i32 0, i32 8
15281 // CHECK18-NEXT:    [[TMP149:%.*]] = bitcast i8** [[TMP148]] to %struct.TT**
15282 // CHECK18-NEXT:    store %struct.TT* [[D]], %struct.TT** [[TMP149]], align 8
15283 // CHECK18-NEXT:    [[TMP150:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 8
15284 // CHECK18-NEXT:    store i64 16, i64* [[TMP150]], align 8
15285 // CHECK18-NEXT:    [[TMP151:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS31]], i64 0, i64 8
15286 // CHECK18-NEXT:    store i8* null, i8** [[TMP151]], align 8
15287 // CHECK18-NEXT:    [[TMP152:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS29]], i32 0, i32 9
15288 // CHECK18-NEXT:    [[TMP153:%.*]] = bitcast i8** [[TMP152]] to i64*
15289 // CHECK18-NEXT:    store i64 [[TMP93]], i64* [[TMP153]], align 8
15290 // CHECK18-NEXT:    [[TMP154:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS30]], i32 0, i32 9
15291 // CHECK18-NEXT:    [[TMP155:%.*]] = bitcast i8** [[TMP154]] to i64*
15292 // CHECK18-NEXT:    store i64 [[TMP93]], i64* [[TMP155]], align 8
15293 // CHECK18-NEXT:    [[TMP156:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 9
15294 // CHECK18-NEXT:    store i64 4, i64* [[TMP156]], align 8
15295 // CHECK18-NEXT:    [[TMP157:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS31]], i64 0, i64 9
15296 // CHECK18-NEXT:    store i8* null, i8** [[TMP157]], align 8
15297 // CHECK18-NEXT:    [[TMP158:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS29]], i32 0, i32 0
15298 // CHECK18-NEXT:    [[TMP159:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS30]], i32 0, i32 0
15299 // CHECK18-NEXT:    [[TMP160:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
15300 // CHECK18-NEXT:    call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10)
15301 // CHECK18-NEXT:    [[TMP161:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145.region_id, i32 10, i8** [[TMP158]], i8** [[TMP159]], i64* [[TMP160]], i64* getelementptr inbounds ([10 x i64], [10 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
15302 // CHECK18-NEXT:    [[TMP162:%.*]] = icmp ne i32 [[TMP161]], 0
15303 // CHECK18-NEXT:    br i1 [[TMP162]], label [[OMP_OFFLOAD_FAILED33:%.*]], label [[OMP_OFFLOAD_CONT34:%.*]]
15304 // CHECK18:       omp_offload.failed33:
15305 // CHECK18-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145(i64 [[TMP91]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]], i64 [[TMP93]]) #[[ATTR3]]
15306 // CHECK18-NEXT:    br label [[OMP_OFFLOAD_CONT34]]
15307 // CHECK18:       omp_offload.cont34:
15308 // CHECK18-NEXT:    br label [[OMP_IF_END36:%.*]]
15309 // CHECK18:       omp_if.else35:
15310 // CHECK18-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145(i64 [[TMP91]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]], i64 [[TMP93]]) #[[ATTR3]]
15311 // CHECK18-NEXT:    br label [[OMP_IF_END36]]
15312 // CHECK18:       omp_if.end36:
15313 // CHECK18-NEXT:    [[TMP163:%.*]] = load i32, i32* [[A]], align 4
15314 // CHECK18-NEXT:    [[TMP164:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
15315 // CHECK18-NEXT:    call void @llvm.stackrestore(i8* [[TMP164]])
15316 // CHECK18-NEXT:    ret i32 [[TMP163]]
15317 //
15318 //
15319 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103
15320 // CHECK18-SAME: (i64 [[AA:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] {
15321 // CHECK18-NEXT:  entry:
15322 // CHECK18-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
15323 // CHECK18-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
15324 // CHECK18-NEXT:    [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8
15325 // CHECK18-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
15326 // CHECK18-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]])
15327 // CHECK18-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
15328 // CHECK18-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
15329 // CHECK18-NEXT:    store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8
15330 // CHECK18-NEXT:    [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
15331 // CHECK18-NEXT:    [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
15332 // CHECK18-NEXT:    [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32*
15333 // CHECK18-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 8
15334 // CHECK18-NEXT:    [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 8
15335 // CHECK18-NEXT:    call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
15336 // CHECK18-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV]], align 8
15337 // CHECK18-NEXT:    [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
15338 // CHECK18-NEXT:    store i16 [[TMP3]], i16* [[CONV5]], align 2
15339 // CHECK18-NEXT:    [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
15340 // CHECK18-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]])
15341 // CHECK18-NEXT:    ret void
15342 //
15343 //
15344 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined.
15345 // CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] {
15346 // CHECK18-NEXT:  entry:
15347 // CHECK18-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
15348 // CHECK18-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
15349 // CHECK18-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
15350 // CHECK18-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
15351 // CHECK18-NEXT:    [[TMP:%.*]] = alloca i32, align 4
15352 // CHECK18-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
15353 // CHECK18-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
15354 // CHECK18-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
15355 // CHECK18-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
15356 // CHECK18-NEXT:    [[I:%.*]] = alloca i32, align 4
15357 // CHECK18-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
15358 // CHECK18-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
15359 // CHECK18-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
15360 // CHECK18-NEXT:    [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
15361 // CHECK18-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
15362 // CHECK18-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
15363 // CHECK18-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
15364 // CHECK18-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
15365 // CHECK18-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
15366 // CHECK18-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
15367 // CHECK18-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
15368 // CHECK18-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
15369 // CHECK18-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
15370 // CHECK18-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
15371 // CHECK18:       cond.true:
15372 // CHECK18-NEXT:    br label [[COND_END:%.*]]
15373 // CHECK18:       cond.false:
15374 // CHECK18-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
15375 // CHECK18-NEXT:    br label [[COND_END]]
15376 // CHECK18:       cond.end:
15377 // CHECK18-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
15378 // CHECK18-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
15379 // CHECK18-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
15380 // CHECK18-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
15381 // CHECK18-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
15382 // CHECK18:       omp.inner.for.cond:
15383 // CHECK18-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
15384 // CHECK18-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
15385 // CHECK18-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
15386 // CHECK18-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
15387 // CHECK18:       omp.inner.for.body:
15388 // CHECK18-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
15389 // CHECK18-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
15390 // CHECK18-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
15391 // CHECK18-NEXT:    store i32 [[ADD]], i32* [[I]], align 4
15392 // CHECK18-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
15393 // CHECK18:       omp.body.continue:
15394 // CHECK18-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
15395 // CHECK18:       omp.inner.for.inc:
15396 // CHECK18-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
15397 // CHECK18-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
15398 // CHECK18-NEXT:    store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4
15399 // CHECK18-NEXT:    br label [[OMP_INNER_FOR_COND]]
15400 // CHECK18:       omp.inner.for.end:
15401 // CHECK18-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
15402 // CHECK18:       omp.loop.exit:
15403 // CHECK18-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
15404 // CHECK18-NEXT:    ret void
15405 //
15406 //
15407 // CHECK18-LABEL: define {{[^@]+}}@.omp_task_privates_map.
15408 // CHECK18-SAME: (%struct..kmp_privates.t* noalias [[TMP0:%.*]], i16** noalias [[TMP1:%.*]], [3 x i8*]** noalias [[TMP2:%.*]], [3 x i8*]** noalias [[TMP3:%.*]], [3 x i64]** noalias [[TMP4:%.*]]) #[[ATTR4:[0-9]+]] {
15409 // CHECK18-NEXT:  entry:
15410 // CHECK18-NEXT:    [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 8
15411 // CHECK18-NEXT:    [[DOTADDR1:%.*]] = alloca i16**, align 8
15412 // CHECK18-NEXT:    [[DOTADDR2:%.*]] = alloca [3 x i8*]**, align 8
15413 // CHECK18-NEXT:    [[DOTADDR3:%.*]] = alloca [3 x i8*]**, align 8
15414 // CHECK18-NEXT:    [[DOTADDR4:%.*]] = alloca [3 x i64]**, align 8
15415 // CHECK18-NEXT:    store %struct..kmp_privates.t* [[TMP0]], %struct..kmp_privates.t** [[DOTADDR]], align 8
15416 // CHECK18-NEXT:    store i16** [[TMP1]], i16*** [[DOTADDR1]], align 8
15417 // CHECK18-NEXT:    store [3 x i8*]** [[TMP2]], [3 x i8*]*** [[DOTADDR2]], align 8
15418 // CHECK18-NEXT:    store [3 x i8*]** [[TMP3]], [3 x i8*]*** [[DOTADDR3]], align 8
15419 // CHECK18-NEXT:    store [3 x i64]** [[TMP4]], [3 x i64]*** [[DOTADDR4]], align 8
15420 // CHECK18-NEXT:    [[TMP5:%.*]] = load %struct..kmp_privates.t*, %struct..kmp_privates.t** [[DOTADDR]], align 8
15421 // CHECK18-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 0
15422 // CHECK18-NEXT:    [[TMP7:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR2]], align 8
15423 // CHECK18-NEXT:    store [3 x i8*]* [[TMP6]], [3 x i8*]** [[TMP7]], align 8
15424 // CHECK18-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 1
15425 // CHECK18-NEXT:    [[TMP9:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR3]], align 8
15426 // CHECK18-NEXT:    store [3 x i8*]* [[TMP8]], [3 x i8*]** [[TMP9]], align 8
15427 // CHECK18-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 2
15428 // CHECK18-NEXT:    [[TMP11:%.*]] = load [3 x i64]**, [3 x i64]*** [[DOTADDR4]], align 8
15429 // CHECK18-NEXT:    store [3 x i64]* [[TMP10]], [3 x i64]** [[TMP11]], align 8
15430 // CHECK18-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 3
15431 // CHECK18-NEXT:    [[TMP13:%.*]] = load i16**, i16*** [[DOTADDR1]], align 8
15432 // CHECK18-NEXT:    store i16* [[TMP12]], i16** [[TMP13]], align 8
15433 // CHECK18-NEXT:    ret void
15434 //
15435 //
15436 // CHECK18-LABEL: define {{[^@]+}}@.omp_task_entry.
15437 // CHECK18-SAME: (i32 signext [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] {
15438 // CHECK18-NEXT:  entry:
15439 // CHECK18-NEXT:    [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
15440 // CHECK18-NEXT:    [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8
15441 // CHECK18-NEXT:    [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8
15442 // CHECK18-NEXT:    [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8
15443 // CHECK18-NEXT:    [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8
15444 // CHECK18-NEXT:    [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 8
15445 // CHECK18-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca i16*, align 8
15446 // CHECK18-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca [3 x i8*]*, align 8
15447 // CHECK18-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca [3 x i8*]*, align 8
15448 // CHECK18-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca [3 x i64]*, align 8
15449 // CHECK18-NEXT:    [[AA_CASTED_I:%.*]] = alloca i64, align 8
15450 // CHECK18-NEXT:    [[DOTCAPTURE_EXPR__CASTED_I:%.*]] = alloca i64, align 8
15451 // CHECK18-NEXT:    [[DOTCAPTURE_EXPR__CASTED5_I:%.*]] = alloca i64, align 8
15452 // CHECK18-NEXT:    [[DOTADDR:%.*]] = alloca i32, align 4
15453 // CHECK18-NEXT:    [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8
15454 // CHECK18-NEXT:    store i32 [[TMP0]], i32* [[DOTADDR]], align 4
15455 // CHECK18-NEXT:    store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8
15456 // CHECK18-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4
15457 // CHECK18-NEXT:    [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8
15458 // CHECK18-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
15459 // CHECK18-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
15460 // CHECK18-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0
15461 // CHECK18-NEXT:    [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8
15462 // CHECK18-NEXT:    [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon*
15463 // CHECK18-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1
15464 // CHECK18-NEXT:    [[TMP10:%.*]] = bitcast %struct..kmp_privates.t* [[TMP9]] to i8*
15465 // CHECK18-NEXT:    [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8*
15466 // CHECK18-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META11:![0-9]+]])
15467 // CHECK18-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META14:![0-9]+]])
15468 // CHECK18-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META16:![0-9]+]])
15469 // CHECK18-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]])
15470 // CHECK18-NEXT:    store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !20
15471 // CHECK18-NEXT:    store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !20
15472 // CHECK18-NEXT:    store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !20
15473 // CHECK18-NEXT:    store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* @.omp_task_privates_map. to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !20
15474 // CHECK18-NEXT:    store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !20
15475 // CHECK18-NEXT:    store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !20
15476 // CHECK18-NEXT:    [[TMP12:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !20
15477 // CHECK18-NEXT:    [[TMP13:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !20
15478 // CHECK18-NEXT:    [[TMP14:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !20
15479 // CHECK18-NEXT:    [[TMP15:%.*]] = bitcast void (i8*, ...)* [[TMP13]] to void (i8*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)*
15480 // CHECK18-NEXT:    call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]]
15481 // CHECK18-NEXT:    [[TMP16:%.*]] = load i16*, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !20
15482 // CHECK18-NEXT:    [[TMP17:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !20
15483 // CHECK18-NEXT:    [[TMP18:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 8, !noalias !20
15484 // CHECK18-NEXT:    [[TMP19:%.*]] = load [3 x i64]*, [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 8, !noalias !20
15485 // CHECK18-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP17]], i64 0, i64 0
15486 // CHECK18-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP18]], i64 0, i64 0
15487 // CHECK18-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[TMP19]], i64 0, i64 0
15488 // CHECK18-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP12]], i32 0, i32 1
15489 // CHECK18-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[TMP12]], i32 0, i32 2
15490 // CHECK18-NEXT:    [[TMP25:%.*]] = load i32, i32* [[TMP23]], align 4
15491 // CHECK18-NEXT:    [[TMP26:%.*]] = load i32, i32* [[TMP24]], align 4
15492 // CHECK18-NEXT:    call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) #[[ATTR3]]
15493 // CHECK18-NEXT:    [[TMP27:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 [[TMP25]], i32 [[TMP26]]) #[[ATTR3]]
15494 // CHECK18-NEXT:    [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0
15495 // CHECK18-NEXT:    br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]]
15496 // CHECK18:       omp_offload.failed.i:
15497 // CHECK18-NEXT:    [[TMP29:%.*]] = load i16, i16* [[TMP16]], align 2
15498 // CHECK18-NEXT:    [[CONV_I:%.*]] = bitcast i64* [[AA_CASTED_I]] to i16*
15499 // CHECK18-NEXT:    store i16 [[TMP29]], i16* [[CONV_I]], align 2, !noalias !20
15500 // CHECK18-NEXT:    [[TMP30:%.*]] = load i64, i64* [[AA_CASTED_I]], align 8, !noalias !20
15501 // CHECK18-NEXT:    [[TMP31:%.*]] = load i32, i32* [[TMP23]], align 4
15502 // CHECK18-NEXT:    [[CONV4_I:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED_I]] to i32*
15503 // CHECK18-NEXT:    store i32 [[TMP31]], i32* [[CONV4_I]], align 4, !noalias !20
15504 // CHECK18-NEXT:    [[TMP32:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED_I]], align 8, !noalias !20
15505 // CHECK18-NEXT:    [[TMP33:%.*]] = load i32, i32* [[TMP24]], align 4
15506 // CHECK18-NEXT:    [[CONV6_I:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED5_I]] to i32*
15507 // CHECK18-NEXT:    store i32 [[TMP33]], i32* [[CONV6_I]], align 4, !noalias !20
15508 // CHECK18-NEXT:    [[TMP34:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED5_I]], align 8, !noalias !20
15509 // CHECK18-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103(i64 [[TMP30]], i64 [[TMP32]], i64 [[TMP34]]) #[[ATTR3]]
15510 // CHECK18-NEXT:    br label [[DOTOMP_OUTLINED__1_EXIT]]
15511 // CHECK18:       .omp_outlined..1.exit:
15512 // CHECK18-NEXT:    ret i32 0
15513 //
15514 //
15515 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l107
15516 // CHECK18-SAME: (i64 [[A:%.*]]) #[[ATTR2]] {
15517 // CHECK18-NEXT:  entry:
15518 // CHECK18-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
15519 // CHECK18-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
15520 // CHECK18-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
15521 // CHECK18-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
15522 // CHECK18-NEXT:    [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
15523 // CHECK18-NEXT:    [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32*
15524 // CHECK18-NEXT:    store i32 [[TMP0]], i32* [[CONV1]], align 4
15525 // CHECK18-NEXT:    [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
15526 // CHECK18-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]])
15527 // CHECK18-NEXT:    ret void
15528 //
15529 //
15530 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..2
15531 // CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]]) #[[ATTR2]] {
15532 // CHECK18-NEXT:  entry:
15533 // CHECK18-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
15534 // CHECK18-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
15535 // CHECK18-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
15536 // CHECK18-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
15537 // CHECK18-NEXT:    [[TMP:%.*]] = alloca i32, align 4
15538 // CHECK18-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
15539 // CHECK18-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
15540 // CHECK18-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
15541 // CHECK18-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
15542 // CHECK18-NEXT:    [[I:%.*]] = alloca i32, align 4
15543 // CHECK18-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
15544 // CHECK18-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
15545 // CHECK18-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
15546 // CHECK18-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
15547 // CHECK18-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
15548 // CHECK18-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
15549 // CHECK18-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
15550 // CHECK18-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
15551 // CHECK18-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
15552 // CHECK18-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
15553 // CHECK18-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
15554 // CHECK18-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
15555 // CHECK18-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
15556 // CHECK18-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
15557 // CHECK18:       cond.true:
15558 // CHECK18-NEXT:    br label [[COND_END:%.*]]
15559 // CHECK18:       cond.false:
15560 // CHECK18-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
15561 // CHECK18-NEXT:    br label [[COND_END]]
15562 // CHECK18:       cond.end:
15563 // CHECK18-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
15564 // CHECK18-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
15565 // CHECK18-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
15566 // CHECK18-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
15567 // CHECK18-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
15568 // CHECK18:       omp.inner.for.cond:
15569 // CHECK18-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
15570 // CHECK18-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
15571 // CHECK18-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
15572 // CHECK18-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
15573 // CHECK18:       omp.inner.for.body:
15574 // CHECK18-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
15575 // CHECK18-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
15576 // CHECK18-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
15577 // CHECK18-NEXT:    store i32 [[ADD]], i32* [[I]], align 4
15578 // CHECK18-NEXT:    [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
15579 // CHECK18-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
15580 // CHECK18-NEXT:    store i32 [[ADD2]], i32* [[CONV]], align 8
15581 // CHECK18-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
15582 // CHECK18:       omp.body.continue:
15583 // CHECK18-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
15584 // CHECK18:       omp.inner.for.inc:
15585 // CHECK18-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
15586 // CHECK18-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1
15587 // CHECK18-NEXT:    store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4
15588 // CHECK18-NEXT:    br label [[OMP_INNER_FOR_COND]]
15589 // CHECK18:       omp.inner.for.end:
15590 // CHECK18-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
15591 // CHECK18:       omp.loop.exit:
15592 // CHECK18-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
15593 // CHECK18-NEXT:    ret void
15594 //
15595 //
15596 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113
15597 // CHECK18-SAME: (i64 [[AA:%.*]]) #[[ATTR2]] {
15598 // CHECK18-NEXT:  entry:
15599 // CHECK18-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
15600 // CHECK18-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
15601 // CHECK18-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
15602 // CHECK18-NEXT:    [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
15603 // CHECK18-NEXT:    [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8
15604 // CHECK18-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
15605 // CHECK18-NEXT:    store i16 [[TMP0]], i16* [[CONV1]], align 2
15606 // CHECK18-NEXT:    [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
15607 // CHECK18-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP1]])
15608 // CHECK18-NEXT:    ret void
15609 //
15610 //
15611 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..3
15612 // CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] {
15613 // CHECK18-NEXT:  entry:
15614 // CHECK18-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
15615 // CHECK18-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
15616 // CHECK18-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
15617 // CHECK18-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
15618 // CHECK18-NEXT:    [[TMP:%.*]] = alloca i32, align 4
15619 // CHECK18-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
15620 // CHECK18-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
15621 // CHECK18-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
15622 // CHECK18-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
15623 // CHECK18-NEXT:    [[I:%.*]] = alloca i32, align 4
15624 // CHECK18-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
15625 // CHECK18-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
15626 // CHECK18-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
15627 // CHECK18-NEXT:    [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
15628 // CHECK18-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
15629 // CHECK18-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
15630 // CHECK18-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
15631 // CHECK18-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
15632 // CHECK18-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
15633 // CHECK18-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
15634 // CHECK18-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
15635 // CHECK18-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
15636 // CHECK18-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
15637 // CHECK18-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
15638 // CHECK18:       cond.true:
15639 // CHECK18-NEXT:    br label [[COND_END:%.*]]
15640 // CHECK18:       cond.false:
15641 // CHECK18-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
15642 // CHECK18-NEXT:    br label [[COND_END]]
15643 // CHECK18:       cond.end:
15644 // CHECK18-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
15645 // CHECK18-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
15646 // CHECK18-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
15647 // CHECK18-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
15648 // CHECK18-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
15649 // CHECK18:       omp.inner.for.cond:
15650 // CHECK18-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
15651 // CHECK18-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
15652 // CHECK18-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
15653 // CHECK18-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
15654 // CHECK18:       omp.inner.for.body:
15655 // CHECK18-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
15656 // CHECK18-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
15657 // CHECK18-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
15658 // CHECK18-NEXT:    store i32 [[ADD]], i32* [[I]], align 4
15659 // CHECK18-NEXT:    [[TMP8:%.*]] = load i16, i16* [[CONV]], align 8
15660 // CHECK18-NEXT:    [[CONV2:%.*]] = sext i16 [[TMP8]] to i32
15661 // CHECK18-NEXT:    [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
15662 // CHECK18-NEXT:    [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
15663 // CHECK18-NEXT:    store i16 [[CONV4]], i16* [[CONV]], align 8
15664 // CHECK18-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
15665 // CHECK18:       omp.body.continue:
15666 // CHECK18-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
15667 // CHECK18:       omp.inner.for.inc:
15668 // CHECK18-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
15669 // CHECK18-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP9]], 1
15670 // CHECK18-NEXT:    store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4
15671 // CHECK18-NEXT:    br label [[OMP_INNER_FOR_COND]]
15672 // CHECK18:       omp.inner.for.end:
15673 // CHECK18-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
15674 // CHECK18:       omp.loop.exit:
15675 // CHECK18-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
15676 // CHECK18-NEXT:    ret void
15677 //
15678 //
15679 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120
15680 // CHECK18-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] {
15681 // CHECK18-NEXT:  entry:
15682 // CHECK18-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
15683 // CHECK18-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
15684 // CHECK18-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
15685 // CHECK18-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
15686 // CHECK18-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
15687 // CHECK18-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
15688 // CHECK18-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
15689 // CHECK18-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
15690 // CHECK18-NEXT:    [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
15691 // CHECK18-NEXT:    [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
15692 // CHECK18-NEXT:    store i32 [[TMP0]], i32* [[CONV2]], align 4
15693 // CHECK18-NEXT:    [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
15694 // CHECK18-NEXT:    [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
15695 // CHECK18-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
15696 // CHECK18-NEXT:    store i16 [[TMP2]], i16* [[CONV3]], align 2
15697 // CHECK18-NEXT:    [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
15698 // CHECK18-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
15699 // CHECK18-NEXT:    ret void
15700 //
15701 //
15702 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..6
15703 // CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] {
15704 // CHECK18-NEXT:  entry:
15705 // CHECK18-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
15706 // CHECK18-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
15707 // CHECK18-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
15708 // CHECK18-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
15709 // CHECK18-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
15710 // CHECK18-NEXT:    [[TMP:%.*]] = alloca i32, align 4
15711 // CHECK18-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
15712 // CHECK18-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
15713 // CHECK18-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
15714 // CHECK18-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
15715 // CHECK18-NEXT:    [[I:%.*]] = alloca i32, align 4
15716 // CHECK18-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
15717 // CHECK18-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
15718 // CHECK18-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
15719 // CHECK18-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
15720 // CHECK18-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
15721 // CHECK18-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
15722 // CHECK18-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
15723 // CHECK18-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
15724 // CHECK18-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
15725 // CHECK18-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
15726 // CHECK18-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
15727 // CHECK18-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
15728 // CHECK18-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
15729 // CHECK18-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
15730 // CHECK18-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
15731 // CHECK18-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
15732 // CHECK18:       cond.true:
15733 // CHECK18-NEXT:    br label [[COND_END:%.*]]
15734 // CHECK18:       cond.false:
15735 // CHECK18-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
15736 // CHECK18-NEXT:    br label [[COND_END]]
15737 // CHECK18:       cond.end:
15738 // CHECK18-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
15739 // CHECK18-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
15740 // CHECK18-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
15741 // CHECK18-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
15742 // CHECK18-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
15743 // CHECK18:       omp.inner.for.cond:
15744 // CHECK18-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
15745 // CHECK18-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
15746 // CHECK18-NEXT:    [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
15747 // CHECK18-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
15748 // CHECK18:       omp.inner.for.body:
15749 // CHECK18-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
15750 // CHECK18-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
15751 // CHECK18-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
15752 // CHECK18-NEXT:    store i32 [[ADD]], i32* [[I]], align 4
15753 // CHECK18-NEXT:    [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
15754 // CHECK18-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
15755 // CHECK18-NEXT:    store i32 [[ADD3]], i32* [[CONV]], align 8
15756 // CHECK18-NEXT:    [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 8
15757 // CHECK18-NEXT:    [[CONV4:%.*]] = sext i16 [[TMP9]] to i32
15758 // CHECK18-NEXT:    [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
15759 // CHECK18-NEXT:    [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
15760 // CHECK18-NEXT:    store i16 [[CONV6]], i16* [[CONV1]], align 8
15761 // CHECK18-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
15762 // CHECK18:       omp.body.continue:
15763 // CHECK18-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
15764 // CHECK18:       omp.inner.for.inc:
15765 // CHECK18-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
15766 // CHECK18-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1
15767 // CHECK18-NEXT:    store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4
15768 // CHECK18-NEXT:    br label [[OMP_INNER_FOR_COND]]
15769 // CHECK18:       omp.inner.for.end:
15770 // CHECK18-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
15771 // CHECK18:       omp.loop.exit:
15772 // CHECK18-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
15773 // CHECK18-NEXT:    ret void
15774 //
15775 //
15776 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145
15777 // CHECK18-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] {
15778 // CHECK18-NEXT:  entry:
15779 // CHECK18-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
15780 // CHECK18-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
15781 // CHECK18-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
15782 // CHECK18-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 8
15783 // CHECK18-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
15784 // CHECK18-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
15785 // CHECK18-NEXT:    [[VLA_ADDR4:%.*]] = alloca i64, align 8
15786 // CHECK18-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 8
15787 // CHECK18-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
15788 // CHECK18-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
15789 // CHECK18-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
15790 // CHECK18-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
15791 // CHECK18-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
15792 // CHECK18-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
15793 // CHECK18-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
15794 // CHECK18-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 8
15795 // CHECK18-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
15796 // CHECK18-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
15797 // CHECK18-NEXT:    store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
15798 // CHECK18-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 8
15799 // CHECK18-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
15800 // CHECK18-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
15801 // CHECK18-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
15802 // CHECK18-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
15803 // CHECK18-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
15804 // CHECK18-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
15805 // CHECK18-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
15806 // CHECK18-NEXT:    [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
15807 // CHECK18-NEXT:    [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
15808 // CHECK18-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
15809 // CHECK18-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
15810 // CHECK18-NEXT:    [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
15811 // CHECK18-NEXT:    [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
15812 // CHECK18-NEXT:    [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32*
15813 // CHECK18-NEXT:    store i32 [[TMP8]], i32* [[CONV6]], align 4
15814 // CHECK18-NEXT:    [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
15815 // CHECK18-NEXT:    [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 8
15816 // CHECK18-NEXT:    [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
15817 // CHECK18-NEXT:    store i32 [[TMP10]], i32* [[CONV7]], align 4
15818 // CHECK18-NEXT:    [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
15819 // CHECK18-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]])
15820 // CHECK18-NEXT:    ret void
15821 //
15822 //
15823 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..9
15824 // CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] {
15825 // CHECK18-NEXT:  entry:
15826 // CHECK18-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
15827 // CHECK18-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
15828 // CHECK18-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
15829 // CHECK18-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
15830 // CHECK18-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
15831 // CHECK18-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 8
15832 // CHECK18-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
15833 // CHECK18-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
15834 // CHECK18-NEXT:    [[VLA_ADDR4:%.*]] = alloca i64, align 8
15835 // CHECK18-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 8
15836 // CHECK18-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
15837 // CHECK18-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
15838 // CHECK18-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
15839 // CHECK18-NEXT:    [[TMP:%.*]] = alloca i32, align 4
15840 // CHECK18-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
15841 // CHECK18-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
15842 // CHECK18-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
15843 // CHECK18-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
15844 // CHECK18-NEXT:    [[I:%.*]] = alloca i32, align 4
15845 // CHECK18-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
15846 // CHECK18-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
15847 // CHECK18-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
15848 // CHECK18-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
15849 // CHECK18-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
15850 // CHECK18-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 8
15851 // CHECK18-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
15852 // CHECK18-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
15853 // CHECK18-NEXT:    store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
15854 // CHECK18-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 8
15855 // CHECK18-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
15856 // CHECK18-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
15857 // CHECK18-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
15858 // CHECK18-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
15859 // CHECK18-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
15860 // CHECK18-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
15861 // CHECK18-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
15862 // CHECK18-NEXT:    [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
15863 // CHECK18-NEXT:    [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
15864 // CHECK18-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
15865 // CHECK18-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
15866 // CHECK18-NEXT:    [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
15867 // CHECK18-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
15868 // CHECK18-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
15869 // CHECK18-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
15870 // CHECK18-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
15871 // CHECK18-NEXT:    [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 8
15872 // CHECK18-NEXT:    [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
15873 // CHECK18-NEXT:    [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
15874 // CHECK18-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
15875 // CHECK18-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
15876 // CHECK18:       omp.dispatch.cond:
15877 // CHECK18-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
15878 // CHECK18-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 9
15879 // CHECK18-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
15880 // CHECK18:       cond.true:
15881 // CHECK18-NEXT:    br label [[COND_END:%.*]]
15882 // CHECK18:       cond.false:
15883 // CHECK18-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
15884 // CHECK18-NEXT:    br label [[COND_END]]
15885 // CHECK18:       cond.end:
15886 // CHECK18-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
15887 // CHECK18-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
15888 // CHECK18-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
15889 // CHECK18-NEXT:    store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
15890 // CHECK18-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
15891 // CHECK18-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
15892 // CHECK18-NEXT:    [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
15893 // CHECK18-NEXT:    br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
15894 // CHECK18:       omp.dispatch.body:
15895 // CHECK18-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
15896 // CHECK18:       omp.inner.for.cond:
15897 // CHECK18-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
15898 // CHECK18-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !21
15899 // CHECK18-NEXT:    [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
15900 // CHECK18-NEXT:    br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
15901 // CHECK18:       omp.inner.for.body:
15902 // CHECK18-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
15903 // CHECK18-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
15904 // CHECK18-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
15905 // CHECK18-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !21
15906 // CHECK18-NEXT:    [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !21
15907 // CHECK18-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP19]], 1
15908 // CHECK18-NEXT:    store i32 [[ADD8]], i32* [[CONV]], align 8, !llvm.access.group !21
15909 // CHECK18-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
15910 // CHECK18-NEXT:    [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !21
15911 // CHECK18-NEXT:    [[CONV9:%.*]] = fpext float [[TMP20]] to double
15912 // CHECK18-NEXT:    [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00
15913 // CHECK18-NEXT:    [[CONV11:%.*]] = fptrunc double [[ADD10]] to float
15914 // CHECK18-NEXT:    store float [[CONV11]], float* [[ARRAYIDX]], align 4, !llvm.access.group !21
15915 // CHECK18-NEXT:    [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3
15916 // CHECK18-NEXT:    [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4, !llvm.access.group !21
15917 // CHECK18-NEXT:    [[CONV13:%.*]] = fpext float [[TMP21]] to double
15918 // CHECK18-NEXT:    [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00
15919 // CHECK18-NEXT:    [[CONV15:%.*]] = fptrunc double [[ADD14]] to float
15920 // CHECK18-NEXT:    store float [[CONV15]], float* [[ARRAYIDX12]], align 4, !llvm.access.group !21
15921 // CHECK18-NEXT:    [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1
15922 // CHECK18-NEXT:    [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i64 0, i64 2
15923 // CHECK18-NEXT:    [[TMP22:%.*]] = load double, double* [[ARRAYIDX17]], align 8, !llvm.access.group !21
15924 // CHECK18-NEXT:    [[ADD18:%.*]] = fadd double [[TMP22]], 1.000000e+00
15925 // CHECK18-NEXT:    store double [[ADD18]], double* [[ARRAYIDX17]], align 8, !llvm.access.group !21
15926 // CHECK18-NEXT:    [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]]
15927 // CHECK18-NEXT:    [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP23]]
15928 // CHECK18-NEXT:    [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i64 3
15929 // CHECK18-NEXT:    [[TMP24:%.*]] = load double, double* [[ARRAYIDX20]], align 8, !llvm.access.group !21
15930 // CHECK18-NEXT:    [[ADD21:%.*]] = fadd double [[TMP24]], 1.000000e+00
15931 // CHECK18-NEXT:    store double [[ADD21]], double* [[ARRAYIDX20]], align 8, !llvm.access.group !21
15932 // CHECK18-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0
15933 // CHECK18-NEXT:    [[TMP25:%.*]] = load i64, i64* [[X]], align 8, !llvm.access.group !21
15934 // CHECK18-NEXT:    [[ADD22:%.*]] = add nsw i64 [[TMP25]], 1
15935 // CHECK18-NEXT:    store i64 [[ADD22]], i64* [[X]], align 8, !llvm.access.group !21
15936 // CHECK18-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1
15937 // CHECK18-NEXT:    [[TMP26:%.*]] = load i8, i8* [[Y]], align 8, !llvm.access.group !21
15938 // CHECK18-NEXT:    [[CONV23:%.*]] = sext i8 [[TMP26]] to i32
15939 // CHECK18-NEXT:    [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1
15940 // CHECK18-NEXT:    [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8
15941 // CHECK18-NEXT:    store i8 [[CONV25]], i8* [[Y]], align 8, !llvm.access.group !21
15942 // CHECK18-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
15943 // CHECK18:       omp.body.continue:
15944 // CHECK18-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
15945 // CHECK18:       omp.inner.for.inc:
15946 // CHECK18-NEXT:    [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
15947 // CHECK18-NEXT:    [[ADD26:%.*]] = add nsw i32 [[TMP27]], 1
15948 // CHECK18-NEXT:    store i32 [[ADD26]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
15949 // CHECK18-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]]
15950 // CHECK18:       omp.inner.for.end:
15951 // CHECK18-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
15952 // CHECK18:       omp.dispatch.inc:
15953 // CHECK18-NEXT:    [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
15954 // CHECK18-NEXT:    [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
15955 // CHECK18-NEXT:    [[ADD27:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]
15956 // CHECK18-NEXT:    store i32 [[ADD27]], i32* [[DOTOMP_LB]], align 4
15957 // CHECK18-NEXT:    [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
15958 // CHECK18-NEXT:    [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
15959 // CHECK18-NEXT:    [[ADD28:%.*]] = add nsw i32 [[TMP30]], [[TMP31]]
15960 // CHECK18-NEXT:    store i32 [[ADD28]], i32* [[DOTOMP_UB]], align 4
15961 // CHECK18-NEXT:    br label [[OMP_DISPATCH_COND]]
15962 // CHECK18:       omp.dispatch.end:
15963 // CHECK18-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]])
15964 // CHECK18-NEXT:    ret void
15965 //
15966 //
15967 // CHECK18-LABEL: define {{[^@]+}}@_Z3bari
15968 // CHECK18-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
15969 // CHECK18-NEXT:  entry:
15970 // CHECK18-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
15971 // CHECK18-NEXT:    [[A:%.*]] = alloca i32, align 4
15972 // CHECK18-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8
15973 // CHECK18-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
15974 // CHECK18-NEXT:    store i32 0, i32* [[A]], align 4
15975 // CHECK18-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
15976 // CHECK18-NEXT:    [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]])
15977 // CHECK18-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
15978 // CHECK18-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
15979 // CHECK18-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
15980 // CHECK18-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
15981 // CHECK18-NEXT:    [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]])
15982 // CHECK18-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
15983 // CHECK18-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
15984 // CHECK18-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
15985 // CHECK18-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
15986 // CHECK18-NEXT:    [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]])
15987 // CHECK18-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
15988 // CHECK18-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
15989 // CHECK18-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
15990 // CHECK18-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
15991 // CHECK18-NEXT:    [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]])
15992 // CHECK18-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
15993 // CHECK18-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
15994 // CHECK18-NEXT:    store i32 [[ADD6]], i32* [[A]], align 4
15995 // CHECK18-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
15996 // CHECK18-NEXT:    ret i32 [[TMP8]]
15997 //
15998 //
15999 // CHECK18-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
16000 // CHECK18-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 {
16001 // CHECK18-NEXT:  entry:
16002 // CHECK18-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
16003 // CHECK18-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
16004 // CHECK18-NEXT:    [[B:%.*]] = alloca i32, align 4
16005 // CHECK18-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 8
16006 // CHECK18-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
16007 // CHECK18-NEXT:    [[B_CASTED:%.*]] = alloca i64, align 8
16008 // CHECK18-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8
16009 // CHECK18-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8
16010 // CHECK18-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8
16011 // CHECK18-NEXT:    [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 8
16012 // CHECK18-NEXT:    [[TMP:%.*]] = alloca i32, align 4
16013 // CHECK18-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
16014 // CHECK18-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
16015 // CHECK18-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
16016 // CHECK18-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
16017 // CHECK18-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
16018 // CHECK18-NEXT:    store i32 [[ADD]], i32* [[B]], align 4
16019 // CHECK18-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
16020 // CHECK18-NEXT:    [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
16021 // CHECK18-NEXT:    [[TMP3:%.*]] = call i8* @llvm.stacksave()
16022 // CHECK18-NEXT:    store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8
16023 // CHECK18-NEXT:    [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]
16024 // CHECK18-NEXT:    [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2
16025 // CHECK18-NEXT:    store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8
16026 // CHECK18-NEXT:    [[TMP5:%.*]] = load i32, i32* [[B]], align 4
16027 // CHECK18-NEXT:    [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32*
16028 // CHECK18-NEXT:    store i32 [[TMP5]], i32* [[CONV]], align 4
16029 // CHECK18-NEXT:    [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8
16030 // CHECK18-NEXT:    [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4
16031 // CHECK18-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 60
16032 // CHECK18-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
16033 // CHECK18:       omp_if.then:
16034 // CHECK18-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
16035 // CHECK18-NEXT:    [[TMP8:%.*]] = mul nuw i64 2, [[TMP2]]
16036 // CHECK18-NEXT:    [[TMP9:%.*]] = mul nuw i64 [[TMP8]], 2
16037 // CHECK18-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
16038 // CHECK18-NEXT:    [[TMP11:%.*]] = bitcast i8** [[TMP10]] to %struct.S1**
16039 // CHECK18-NEXT:    store %struct.S1* [[THIS1]], %struct.S1** [[TMP11]], align 8
16040 // CHECK18-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
16041 // CHECK18-NEXT:    [[TMP13:%.*]] = bitcast i8** [[TMP12]] to double**
16042 // CHECK18-NEXT:    store double* [[A]], double** [[TMP13]], align 8
16043 // CHECK18-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
16044 // CHECK18-NEXT:    store i64 8, i64* [[TMP14]], align 8
16045 // CHECK18-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
16046 // CHECK18-NEXT:    store i8* null, i8** [[TMP15]], align 8
16047 // CHECK18-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
16048 // CHECK18-NEXT:    [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64*
16049 // CHECK18-NEXT:    store i64 [[TMP6]], i64* [[TMP17]], align 8
16050 // CHECK18-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
16051 // CHECK18-NEXT:    [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64*
16052 // CHECK18-NEXT:    store i64 [[TMP6]], i64* [[TMP19]], align 8
16053 // CHECK18-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1
16054 // CHECK18-NEXT:    store i64 4, i64* [[TMP20]], align 8
16055 // CHECK18-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
16056 // CHECK18-NEXT:    store i8* null, i8** [[TMP21]], align 8
16057 // CHECK18-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
16058 // CHECK18-NEXT:    [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i64*
16059 // CHECK18-NEXT:    store i64 2, i64* [[TMP23]], align 8
16060 // CHECK18-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
16061 // CHECK18-NEXT:    [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i64*
16062 // CHECK18-NEXT:    store i64 2, i64* [[TMP25]], align 8
16063 // CHECK18-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2
16064 // CHECK18-NEXT:    store i64 8, i64* [[TMP26]], align 8
16065 // CHECK18-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
16066 // CHECK18-NEXT:    store i8* null, i8** [[TMP27]], align 8
16067 // CHECK18-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
16068 // CHECK18-NEXT:    [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i64*
16069 // CHECK18-NEXT:    store i64 [[TMP2]], i64* [[TMP29]], align 8
16070 // CHECK18-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
16071 // CHECK18-NEXT:    [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i64*
16072 // CHECK18-NEXT:    store i64 [[TMP2]], i64* [[TMP31]], align 8
16073 // CHECK18-NEXT:    [[TMP32:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3
16074 // CHECK18-NEXT:    store i64 8, i64* [[TMP32]], align 8
16075 // CHECK18-NEXT:    [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
16076 // CHECK18-NEXT:    store i8* null, i8** [[TMP33]], align 8
16077 // CHECK18-NEXT:    [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
16078 // CHECK18-NEXT:    [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i16**
16079 // CHECK18-NEXT:    store i16* [[VLA]], i16** [[TMP35]], align 8
16080 // CHECK18-NEXT:    [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
16081 // CHECK18-NEXT:    [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i16**
16082 // CHECK18-NEXT:    store i16* [[VLA]], i16** [[TMP37]], align 8
16083 // CHECK18-NEXT:    [[TMP38:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4
16084 // CHECK18-NEXT:    store i64 [[TMP9]], i64* [[TMP38]], align 8
16085 // CHECK18-NEXT:    [[TMP39:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4
16086 // CHECK18-NEXT:    store i8* null, i8** [[TMP39]], align 8
16087 // CHECK18-NEXT:    [[TMP40:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
16088 // CHECK18-NEXT:    [[TMP41:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
16089 // CHECK18-NEXT:    [[TMP42:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
16090 // CHECK18-NEXT:    call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10)
16091 // CHECK18-NEXT:    [[TMP43:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218.region_id, i32 5, i8** [[TMP40]], i8** [[TMP41]], i64* [[TMP42]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.12, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
16092 // CHECK18-NEXT:    [[TMP44:%.*]] = icmp ne i32 [[TMP43]], 0
16093 // CHECK18-NEXT:    br i1 [[TMP44]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
16094 // CHECK18:       omp_offload.failed:
16095 // CHECK18-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR3]]
16096 // CHECK18-NEXT:    br label [[OMP_OFFLOAD_CONT]]
16097 // CHECK18:       omp_offload.cont:
16098 // CHECK18-NEXT:    br label [[OMP_IF_END:%.*]]
16099 // CHECK18:       omp_if.else:
16100 // CHECK18-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR3]]
16101 // CHECK18-NEXT:    br label [[OMP_IF_END]]
16102 // CHECK18:       omp_if.end:
16103 // CHECK18-NEXT:    [[TMP45:%.*]] = mul nsw i64 1, [[TMP2]]
16104 // CHECK18-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP45]]
16105 // CHECK18-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
16106 // CHECK18-NEXT:    [[TMP46:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2
16107 // CHECK18-NEXT:    [[CONV3:%.*]] = sext i16 [[TMP46]] to i32
16108 // CHECK18-NEXT:    [[TMP47:%.*]] = load i32, i32* [[B]], align 4
16109 // CHECK18-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], [[TMP47]]
16110 // CHECK18-NEXT:    [[TMP48:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
16111 // CHECK18-NEXT:    call void @llvm.stackrestore(i8* [[TMP48]])
16112 // CHECK18-NEXT:    ret i32 [[ADD4]]
16113 //
16114 //
16115 // CHECK18-LABEL: define {{[^@]+}}@_ZL7fstatici
16116 // CHECK18-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
16117 // CHECK18-NEXT:  entry:
16118 // CHECK18-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
16119 // CHECK18-NEXT:    [[A:%.*]] = alloca i32, align 4
16120 // CHECK18-NEXT:    [[AA:%.*]] = alloca i16, align 2
16121 // CHECK18-NEXT:    [[AAA:%.*]] = alloca i8, align 1
16122 // CHECK18-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
16123 // CHECK18-NEXT:    [[N_CASTED:%.*]] = alloca i64, align 8
16124 // CHECK18-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
16125 // CHECK18-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
16126 // CHECK18-NEXT:    [[AAA_CASTED:%.*]] = alloca i64, align 8
16127 // CHECK18-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8
16128 // CHECK18-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8
16129 // CHECK18-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8
16130 // CHECK18-NEXT:    [[TMP:%.*]] = alloca i32, align 4
16131 // CHECK18-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
16132 // CHECK18-NEXT:    [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4
16133 // CHECK18-NEXT:    [[DOTCAPTURE_EXPR_5:%.*]] = alloca i32, align 4
16134 // CHECK18-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
16135 // CHECK18-NEXT:    store i32 0, i32* [[A]], align 4
16136 // CHECK18-NEXT:    store i16 0, i16* [[AA]], align 2
16137 // CHECK18-NEXT:    store i8 0, i8* [[AAA]], align 1
16138 // CHECK18-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
16139 // CHECK18-NEXT:    [[CONV:%.*]] = bitcast i64* [[N_CASTED]] to i32*
16140 // CHECK18-NEXT:    store i32 [[TMP0]], i32* [[CONV]], align 4
16141 // CHECK18-NEXT:    [[TMP1:%.*]] = load i64, i64* [[N_CASTED]], align 8
16142 // CHECK18-NEXT:    [[TMP2:%.*]] = load i32, i32* [[A]], align 4
16143 // CHECK18-NEXT:    [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32*
16144 // CHECK18-NEXT:    store i32 [[TMP2]], i32* [[CONV1]], align 4
16145 // CHECK18-NEXT:    [[TMP3:%.*]] = load i64, i64* [[A_CASTED]], align 8
16146 // CHECK18-NEXT:    [[TMP4:%.*]] = load i16, i16* [[AA]], align 2
16147 // CHECK18-NEXT:    [[CONV2:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
16148 // CHECK18-NEXT:    store i16 [[TMP4]], i16* [[CONV2]], align 2
16149 // CHECK18-NEXT:    [[TMP5:%.*]] = load i64, i64* [[AA_CASTED]], align 8
16150 // CHECK18-NEXT:    [[TMP6:%.*]] = load i8, i8* [[AAA]], align 1
16151 // CHECK18-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
16152 // CHECK18-NEXT:    store i8 [[TMP6]], i8* [[CONV3]], align 1
16153 // CHECK18-NEXT:    [[TMP7:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
16154 // CHECK18-NEXT:    [[TMP8:%.*]] = load i32, i32* [[N_ADDR]], align 4
16155 // CHECK18-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP8]], 50
16156 // CHECK18-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
16157 // CHECK18:       omp_if.then:
16158 // CHECK18-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
16159 // CHECK18-NEXT:    [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64*
16160 // CHECK18-NEXT:    store i64 [[TMP1]], i64* [[TMP10]], align 8
16161 // CHECK18-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
16162 // CHECK18-NEXT:    [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64*
16163 // CHECK18-NEXT:    store i64 [[TMP1]], i64* [[TMP12]], align 8
16164 // CHECK18-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
16165 // CHECK18-NEXT:    store i8* null, i8** [[TMP13]], align 8
16166 // CHECK18-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
16167 // CHECK18-NEXT:    [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64*
16168 // CHECK18-NEXT:    store i64 [[TMP3]], i64* [[TMP15]], align 8
16169 // CHECK18-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
16170 // CHECK18-NEXT:    [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64*
16171 // CHECK18-NEXT:    store i64 [[TMP3]], i64* [[TMP17]], align 8
16172 // CHECK18-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
16173 // CHECK18-NEXT:    store i8* null, i8** [[TMP18]], align 8
16174 // CHECK18-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
16175 // CHECK18-NEXT:    [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64*
16176 // CHECK18-NEXT:    store i64 [[TMP5]], i64* [[TMP20]], align 8
16177 // CHECK18-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
16178 // CHECK18-NEXT:    [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i64*
16179 // CHECK18-NEXT:    store i64 [[TMP5]], i64* [[TMP22]], align 8
16180 // CHECK18-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
16181 // CHECK18-NEXT:    store i8* null, i8** [[TMP23]], align 8
16182 // CHECK18-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
16183 // CHECK18-NEXT:    [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i64*
16184 // CHECK18-NEXT:    store i64 [[TMP7]], i64* [[TMP25]], align 8
16185 // CHECK18-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
16186 // CHECK18-NEXT:    [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64*
16187 // CHECK18-NEXT:    store i64 [[TMP7]], i64* [[TMP27]], align 8
16188 // CHECK18-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
16189 // CHECK18-NEXT:    store i8* null, i8** [[TMP28]], align 8
16190 // CHECK18-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
16191 // CHECK18-NEXT:    [[TMP30:%.*]] = bitcast i8** [[TMP29]] to [10 x i32]**
16192 // CHECK18-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP30]], align 8
16193 // CHECK18-NEXT:    [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
16194 // CHECK18-NEXT:    [[TMP32:%.*]] = bitcast i8** [[TMP31]] to [10 x i32]**
16195 // CHECK18-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP32]], align 8
16196 // CHECK18-NEXT:    [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4
16197 // CHECK18-NEXT:    store i8* null, i8** [[TMP33]], align 8
16198 // CHECK18-NEXT:    [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
16199 // CHECK18-NEXT:    [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
16200 // CHECK18-NEXT:    [[TMP36:%.*]] = load i32, i32* [[A]], align 4
16201 // CHECK18-NEXT:    store i32 [[TMP36]], i32* [[DOTCAPTURE_EXPR_]], align 4
16202 // CHECK18-NEXT:    [[TMP37:%.*]] = load i32, i32* [[N_ADDR]], align 4
16203 // CHECK18-NEXT:    store i32 [[TMP37]], i32* [[DOTCAPTURE_EXPR_4]], align 4
16204 // CHECK18-NEXT:    [[TMP38:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4
16205 // CHECK18-NEXT:    [[TMP39:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
16206 // CHECK18-NEXT:    [[SUB:%.*]] = sub i32 [[TMP38]], [[TMP39]]
16207 // CHECK18-NEXT:    [[SUB6:%.*]] = sub i32 [[SUB]], 1
16208 // CHECK18-NEXT:    [[ADD:%.*]] = add i32 [[SUB6]], 1
16209 // CHECK18-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], 1
16210 // CHECK18-NEXT:    [[SUB7:%.*]] = sub i32 [[DIV]], 1
16211 // CHECK18-NEXT:    store i32 [[SUB7]], i32* [[DOTCAPTURE_EXPR_5]], align 4
16212 // CHECK18-NEXT:    [[TMP40:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4
16213 // CHECK18-NEXT:    [[ADD8:%.*]] = add i32 [[TMP40]], 1
16214 // CHECK18-NEXT:    [[TMP41:%.*]] = zext i32 [[ADD8]] to i64
16215 // CHECK18-NEXT:    call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 [[TMP41]])
16216 // CHECK18-NEXT:    [[TMP42:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200.region_id, i32 5, i8** [[TMP34]], i8** [[TMP35]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes.14, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.15, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
16217 // CHECK18-NEXT:    [[TMP43:%.*]] = icmp ne i32 [[TMP42]], 0
16218 // CHECK18-NEXT:    br i1 [[TMP43]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
16219 // CHECK18:       omp_offload.failed:
16220 // CHECK18-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], i64 [[TMP7]], [10 x i32]* [[B]]) #[[ATTR3]]
16221 // CHECK18-NEXT:    br label [[OMP_OFFLOAD_CONT]]
16222 // CHECK18:       omp_offload.cont:
16223 // CHECK18-NEXT:    br label [[OMP_IF_END:%.*]]
16224 // CHECK18:       omp_if.else:
16225 // CHECK18-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], i64 [[TMP7]], [10 x i32]* [[B]]) #[[ATTR3]]
16226 // CHECK18-NEXT:    br label [[OMP_IF_END]]
16227 // CHECK18:       omp_if.end:
16228 // CHECK18-NEXT:    [[TMP44:%.*]] = load i32, i32* [[A]], align 4
16229 // CHECK18-NEXT:    ret i32 [[TMP44]]
16230 //
16231 //
16232 // CHECK18-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
16233 // CHECK18-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat {
16234 // CHECK18-NEXT:  entry:
16235 // CHECK18-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
16236 // CHECK18-NEXT:    [[A:%.*]] = alloca i32, align 4
16237 // CHECK18-NEXT:    [[AA:%.*]] = alloca i16, align 2
16238 // CHECK18-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
16239 // CHECK18-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
16240 // CHECK18-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
16241 // CHECK18-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8
16242 // CHECK18-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8
16243 // CHECK18-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8
16244 // CHECK18-NEXT:    [[TMP:%.*]] = alloca i32, align 4
16245 // CHECK18-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
16246 // CHECK18-NEXT:    store i32 0, i32* [[A]], align 4
16247 // CHECK18-NEXT:    store i16 0, i16* [[AA]], align 2
16248 // CHECK18-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
16249 // CHECK18-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32*
16250 // CHECK18-NEXT:    store i32 [[TMP0]], i32* [[CONV]], align 4
16251 // CHECK18-NEXT:    [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
16252 // CHECK18-NEXT:    [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
16253 // CHECK18-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
16254 // CHECK18-NEXT:    store i16 [[TMP2]], i16* [[CONV1]], align 2
16255 // CHECK18-NEXT:    [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
16256 // CHECK18-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
16257 // CHECK18-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40
16258 // CHECK18-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
16259 // CHECK18:       omp_if.then:
16260 // CHECK18-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
16261 // CHECK18-NEXT:    [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64*
16262 // CHECK18-NEXT:    store i64 [[TMP1]], i64* [[TMP6]], align 8
16263 // CHECK18-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
16264 // CHECK18-NEXT:    [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64*
16265 // CHECK18-NEXT:    store i64 [[TMP1]], i64* [[TMP8]], align 8
16266 // CHECK18-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
16267 // CHECK18-NEXT:    store i8* null, i8** [[TMP9]], align 8
16268 // CHECK18-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
16269 // CHECK18-NEXT:    [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i64*
16270 // CHECK18-NEXT:    store i64 [[TMP3]], i64* [[TMP11]], align 8
16271 // CHECK18-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
16272 // CHECK18-NEXT:    [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64*
16273 // CHECK18-NEXT:    store i64 [[TMP3]], i64* [[TMP13]], align 8
16274 // CHECK18-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
16275 // CHECK18-NEXT:    store i8* null, i8** [[TMP14]], align 8
16276 // CHECK18-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
16277 // CHECK18-NEXT:    [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]**
16278 // CHECK18-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 8
16279 // CHECK18-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
16280 // CHECK18-NEXT:    [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]**
16281 // CHECK18-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 8
16282 // CHECK18-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
16283 // CHECK18-NEXT:    store i8* null, i8** [[TMP19]], align 8
16284 // CHECK18-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
16285 // CHECK18-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
16286 // CHECK18-NEXT:    call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10)
16287 // CHECK18-NEXT:    [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.17, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.18, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
16288 // CHECK18-NEXT:    [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0
16289 // CHECK18-NEXT:    br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
16290 // CHECK18:       omp_offload.failed:
16291 // CHECK18-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]]
16292 // CHECK18-NEXT:    br label [[OMP_OFFLOAD_CONT]]
16293 // CHECK18:       omp_offload.cont:
16294 // CHECK18-NEXT:    br label [[OMP_IF_END:%.*]]
16295 // CHECK18:       omp_if.else:
16296 // CHECK18-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]]
16297 // CHECK18-NEXT:    br label [[OMP_IF_END]]
16298 // CHECK18:       omp_if.end:
16299 // CHECK18-NEXT:    [[TMP24:%.*]] = load i32, i32* [[A]], align 4
16300 // CHECK18-NEXT:    ret i32 [[TMP24]]
16301 //
16302 //
16303 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218
16304 // CHECK18-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {
16305 // CHECK18-NEXT:  entry:
16306 // CHECK18-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
16307 // CHECK18-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
16308 // CHECK18-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
16309 // CHECK18-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
16310 // CHECK18-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 8
16311 // CHECK18-NEXT:    [[B_CASTED:%.*]] = alloca i64, align 8
16312 // CHECK18-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
16313 // CHECK18-NEXT:    store i64 [[B]], i64* [[B_ADDR]], align 8
16314 // CHECK18-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
16315 // CHECK18-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
16316 // CHECK18-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 8
16317 // CHECK18-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
16318 // CHECK18-NEXT:    [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
16319 // CHECK18-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
16320 // CHECK18-NEXT:    [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
16321 // CHECK18-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
16322 // CHECK18-NEXT:    [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
16323 // CHECK18-NEXT:    [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32*
16324 // CHECK18-NEXT:    store i32 [[TMP4]], i32* [[CONV3]], align 4
16325 // CHECK18-NEXT:    [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
16326 // CHECK18-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]])
16327 // CHECK18-NEXT:    ret void
16328 //
16329 //
16330 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..11
16331 // CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {
16332 // CHECK18-NEXT:  entry:
16333 // CHECK18-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
16334 // CHECK18-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
16335 // CHECK18-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
16336 // CHECK18-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
16337 // CHECK18-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
16338 // CHECK18-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
16339 // CHECK18-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 8
16340 // CHECK18-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
16341 // CHECK18-NEXT:    [[TMP:%.*]] = alloca i32, align 4
16342 // CHECK18-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
16343 // CHECK18-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
16344 // CHECK18-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
16345 // CHECK18-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
16346 // CHECK18-NEXT:    [[I:%.*]] = alloca i32, align 4
16347 // CHECK18-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
16348 // CHECK18-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
16349 // CHECK18-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
16350 // CHECK18-NEXT:    store i64 [[B]], i64* [[B_ADDR]], align 8
16351 // CHECK18-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
16352 // CHECK18-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
16353 // CHECK18-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 8
16354 // CHECK18-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
16355 // CHECK18-NEXT:    [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
16356 // CHECK18-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
16357 // CHECK18-NEXT:    [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
16358 // CHECK18-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
16359 // CHECK18-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
16360 // CHECK18-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
16361 // CHECK18-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
16362 // CHECK18-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
16363 // CHECK18-NEXT:    [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
16364 // CHECK18-NEXT:    [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
16365 // CHECK18-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
16366 // CHECK18-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
16367 // CHECK18-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 9
16368 // CHECK18-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
16369 // CHECK18:       cond.true:
16370 // CHECK18-NEXT:    br label [[COND_END:%.*]]
16371 // CHECK18:       cond.false:
16372 // CHECK18-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
16373 // CHECK18-NEXT:    br label [[COND_END]]
16374 // CHECK18:       cond.end:
16375 // CHECK18-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
16376 // CHECK18-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
16377 // CHECK18-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
16378 // CHECK18-NEXT:    store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
16379 // CHECK18-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
16380 // CHECK18:       omp.inner.for.cond:
16381 // CHECK18-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
16382 // CHECK18-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
16383 // CHECK18-NEXT:    [[CMP3:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
16384 // CHECK18-NEXT:    br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
16385 // CHECK18:       omp.inner.for.body:
16386 // CHECK18-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
16387 // CHECK18-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
16388 // CHECK18-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
16389 // CHECK18-NEXT:    store i32 [[ADD]], i32* [[I]], align 4
16390 // CHECK18-NEXT:    [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8
16391 // CHECK18-NEXT:    [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double
16392 // CHECK18-NEXT:    [[ADD5:%.*]] = fadd double [[CONV4]], 1.500000e+00
16393 // CHECK18-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
16394 // CHECK18-NEXT:    store double [[ADD5]], double* [[A]], align 8
16395 // CHECK18-NEXT:    [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
16396 // CHECK18-NEXT:    [[TMP13:%.*]] = load double, double* [[A6]], align 8
16397 // CHECK18-NEXT:    [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00
16398 // CHECK18-NEXT:    store double [[INC]], double* [[A6]], align 8
16399 // CHECK18-NEXT:    [[CONV7:%.*]] = fptosi double [[INC]] to i16
16400 // CHECK18-NEXT:    [[TMP14:%.*]] = mul nsw i64 1, [[TMP2]]
16401 // CHECK18-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP14]]
16402 // CHECK18-NEXT:    [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
16403 // CHECK18-NEXT:    store i16 [[CONV7]], i16* [[ARRAYIDX8]], align 2
16404 // CHECK18-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
16405 // CHECK18:       omp.body.continue:
16406 // CHECK18-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
16407 // CHECK18:       omp.inner.for.inc:
16408 // CHECK18-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
16409 // CHECK18-NEXT:    [[ADD9:%.*]] = add nsw i32 [[TMP15]], 1
16410 // CHECK18-NEXT:    store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4
16411 // CHECK18-NEXT:    br label [[OMP_INNER_FOR_COND]]
16412 // CHECK18:       omp.inner.for.end:
16413 // CHECK18-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
16414 // CHECK18:       omp.loop.exit:
16415 // CHECK18-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
16416 // CHECK18-NEXT:    ret void
16417 //
16418 //
16419 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200
16420 // CHECK18-SAME: (i64 [[N:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
16421 // CHECK18-NEXT:  entry:
16422 // CHECK18-NEXT:    [[N_ADDR:%.*]] = alloca i64, align 8
16423 // CHECK18-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
16424 // CHECK18-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
16425 // CHECK18-NEXT:    [[AAA_ADDR:%.*]] = alloca i64, align 8
16426 // CHECK18-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
16427 // CHECK18-NEXT:    [[N_CASTED:%.*]] = alloca i64, align 8
16428 // CHECK18-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
16429 // CHECK18-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
16430 // CHECK18-NEXT:    [[AAA_CASTED:%.*]] = alloca i64, align 8
16431 // CHECK18-NEXT:    store i64 [[N]], i64* [[N_ADDR]], align 8
16432 // CHECK18-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
16433 // CHECK18-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
16434 // CHECK18-NEXT:    store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
16435 // CHECK18-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
16436 // CHECK18-NEXT:    [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
16437 // CHECK18-NEXT:    [[CONV1:%.*]] = bitcast i64* [[A_ADDR]] to i32*
16438 // CHECK18-NEXT:    [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
16439 // CHECK18-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
16440 // CHECK18-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
16441 // CHECK18-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
16442 // CHECK18-NEXT:    [[CONV4:%.*]] = bitcast i64* [[N_CASTED]] to i32*
16443 // CHECK18-NEXT:    store i32 [[TMP1]], i32* [[CONV4]], align 4
16444 // CHECK18-NEXT:    [[TMP2:%.*]] = load i64, i64* [[N_CASTED]], align 8
16445 // CHECK18-NEXT:    [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 8
16446 // CHECK18-NEXT:    [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
16447 // CHECK18-NEXT:    store i32 [[TMP3]], i32* [[CONV5]], align 4
16448 // CHECK18-NEXT:    [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8
16449 // CHECK18-NEXT:    [[TMP5:%.*]] = load i16, i16* [[CONV2]], align 8
16450 // CHECK18-NEXT:    [[CONV6:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
16451 // CHECK18-NEXT:    store i16 [[TMP5]], i16* [[CONV6]], align 2
16452 // CHECK18-NEXT:    [[TMP6:%.*]] = load i64, i64* [[AA_CASTED]], align 8
16453 // CHECK18-NEXT:    [[TMP7:%.*]] = load i8, i8* [[CONV3]], align 8
16454 // CHECK18-NEXT:    [[CONV7:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
16455 // CHECK18-NEXT:    store i8 [[TMP7]], i8* [[CONV7]], align 1
16456 // CHECK18-NEXT:    [[TMP8:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
16457 // CHECK18-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, [10 x i32]*)* @.omp_outlined..13 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]], [10 x i32]* [[TMP0]])
16458 // CHECK18-NEXT:    ret void
16459 //
16460 //
16461 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..13
16462 // CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
16463 // CHECK18-NEXT:  entry:
16464 // CHECK18-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
16465 // CHECK18-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
16466 // CHECK18-NEXT:    [[N_ADDR:%.*]] = alloca i64, align 8
16467 // CHECK18-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
16468 // CHECK18-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
16469 // CHECK18-NEXT:    [[AAA_ADDR:%.*]] = alloca i64, align 8
16470 // CHECK18-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
16471 // CHECK18-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
16472 // CHECK18-NEXT:    [[TMP:%.*]] = alloca i32, align 4
16473 // CHECK18-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
16474 // CHECK18-NEXT:    [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4
16475 // CHECK18-NEXT:    [[DOTCAPTURE_EXPR_5:%.*]] = alloca i32, align 4
16476 // CHECK18-NEXT:    [[I:%.*]] = alloca i32, align 4
16477 // CHECK18-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
16478 // CHECK18-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
16479 // CHECK18-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
16480 // CHECK18-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
16481 // CHECK18-NEXT:    [[I8:%.*]] = alloca i32, align 4
16482 // CHECK18-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
16483 // CHECK18-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
16484 // CHECK18-NEXT:    store i64 [[N]], i64* [[N_ADDR]], align 8
16485 // CHECK18-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
16486 // CHECK18-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
16487 // CHECK18-NEXT:    store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
16488 // CHECK18-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
16489 // CHECK18-NEXT:    [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
16490 // CHECK18-NEXT:    [[CONV1:%.*]] = bitcast i64* [[A_ADDR]] to i32*
16491 // CHECK18-NEXT:    [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
16492 // CHECK18-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
16493 // CHECK18-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
16494 // CHECK18-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV1]], align 8
16495 // CHECK18-NEXT:    store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
16496 // CHECK18-NEXT:    [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
16497 // CHECK18-NEXT:    store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_4]], align 4
16498 // CHECK18-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4
16499 // CHECK18-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
16500 // CHECK18-NEXT:    [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]]
16501 // CHECK18-NEXT:    [[SUB6:%.*]] = sub i32 [[SUB]], 1
16502 // CHECK18-NEXT:    [[ADD:%.*]] = add i32 [[SUB6]], 1
16503 // CHECK18-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], 1
16504 // CHECK18-NEXT:    [[SUB7:%.*]] = sub i32 [[DIV]], 1
16505 // CHECK18-NEXT:    store i32 [[SUB7]], i32* [[DOTCAPTURE_EXPR_5]], align 4
16506 // CHECK18-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
16507 // CHECK18-NEXT:    store i32 [[TMP5]], i32* [[I]], align 4
16508 // CHECK18-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
16509 // CHECK18-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4
16510 // CHECK18-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]]
16511 // CHECK18-NEXT:    br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
16512 // CHECK18:       omp.precond.then:
16513 // CHECK18-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
16514 // CHECK18-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4
16515 // CHECK18-NEXT:    store i32 [[TMP8]], i32* [[DOTOMP_UB]], align 4
16516 // CHECK18-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
16517 // CHECK18-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
16518 // CHECK18-NEXT:    [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
16519 // CHECK18-NEXT:    [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
16520 // CHECK18-NEXT:    call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
16521 // CHECK18-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
16522 // CHECK18-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4
16523 // CHECK18-NEXT:    [[CMP9:%.*]] = icmp ugt i32 [[TMP11]], [[TMP12]]
16524 // CHECK18-NEXT:    br i1 [[CMP9]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
16525 // CHECK18:       cond.true:
16526 // CHECK18-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4
16527 // CHECK18-NEXT:    br label [[COND_END:%.*]]
16528 // CHECK18:       cond.false:
16529 // CHECK18-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
16530 // CHECK18-NEXT:    br label [[COND_END]]
16531 // CHECK18:       cond.end:
16532 // CHECK18-NEXT:    [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ]
16533 // CHECK18-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
16534 // CHECK18-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
16535 // CHECK18-NEXT:    store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4
16536 // CHECK18-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
16537 // CHECK18:       omp.inner.for.cond:
16538 // CHECK18-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
16539 // CHECK18-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
16540 // CHECK18-NEXT:    [[ADD10:%.*]] = add i32 [[TMP17]], 1
16541 // CHECK18-NEXT:    [[CMP11:%.*]] = icmp ult i32 [[TMP16]], [[ADD10]]
16542 // CHECK18-NEXT:    br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
16543 // CHECK18:       omp.inner.for.body:
16544 // CHECK18-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
16545 // CHECK18-NEXT:    [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
16546 // CHECK18-NEXT:    [[MUL:%.*]] = mul i32 [[TMP19]], 1
16547 // CHECK18-NEXT:    [[ADD12:%.*]] = add i32 [[TMP18]], [[MUL]]
16548 // CHECK18-NEXT:    store i32 [[ADD12]], i32* [[I8]], align 4
16549 // CHECK18-NEXT:    [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 8
16550 // CHECK18-NEXT:    [[ADD13:%.*]] = add nsw i32 [[TMP20]], 1
16551 // CHECK18-NEXT:    store i32 [[ADD13]], i32* [[CONV1]], align 8
16552 // CHECK18-NEXT:    [[TMP21:%.*]] = load i16, i16* [[CONV2]], align 8
16553 // CHECK18-NEXT:    [[CONV14:%.*]] = sext i16 [[TMP21]] to i32
16554 // CHECK18-NEXT:    [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1
16555 // CHECK18-NEXT:    [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16
16556 // CHECK18-NEXT:    store i16 [[CONV16]], i16* [[CONV2]], align 8
16557 // CHECK18-NEXT:    [[TMP22:%.*]] = load i8, i8* [[CONV3]], align 8
16558 // CHECK18-NEXT:    [[CONV17:%.*]] = sext i8 [[TMP22]] to i32
16559 // CHECK18-NEXT:    [[ADD18:%.*]] = add nsw i32 [[CONV17]], 1
16560 // CHECK18-NEXT:    [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8
16561 // CHECK18-NEXT:    store i8 [[CONV19]], i8* [[CONV3]], align 8
16562 // CHECK18-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
16563 // CHECK18-NEXT:    [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
16564 // CHECK18-NEXT:    [[ADD20:%.*]] = add nsw i32 [[TMP23]], 1
16565 // CHECK18-NEXT:    store i32 [[ADD20]], i32* [[ARRAYIDX]], align 4
16566 // CHECK18-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
16567 // CHECK18:       omp.body.continue:
16568 // CHECK18-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
16569 // CHECK18:       omp.inner.for.inc:
16570 // CHECK18-NEXT:    [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
16571 // CHECK18-NEXT:    [[ADD21:%.*]] = add i32 [[TMP24]], 1
16572 // CHECK18-NEXT:    store i32 [[ADD21]], i32* [[DOTOMP_IV]], align 4
16573 // CHECK18-NEXT:    br label [[OMP_INNER_FOR_COND]]
16574 // CHECK18:       omp.inner.for.end:
16575 // CHECK18-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
16576 // CHECK18:       omp.loop.exit:
16577 // CHECK18-NEXT:    [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
16578 // CHECK18-NEXT:    [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4
16579 // CHECK18-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]])
16580 // CHECK18-NEXT:    br label [[OMP_PRECOND_END]]
16581 // CHECK18:       omp.precond.end:
16582 // CHECK18-NEXT:    ret void
16583 //
16584 //
16585 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183
16586 // CHECK18-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
16587 // CHECK18-NEXT:  entry:
16588 // CHECK18-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
16589 // CHECK18-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
16590 // CHECK18-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
16591 // CHECK18-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
16592 // CHECK18-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
16593 // CHECK18-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
16594 // CHECK18-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
16595 // CHECK18-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
16596 // CHECK18-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
16597 // CHECK18-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
16598 // CHECK18-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
16599 // CHECK18-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
16600 // CHECK18-NEXT:    [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
16601 // CHECK18-NEXT:    store i32 [[TMP1]], i32* [[CONV2]], align 4
16602 // CHECK18-NEXT:    [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
16603 // CHECK18-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
16604 // CHECK18-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
16605 // CHECK18-NEXT:    store i16 [[TMP3]], i16* [[CONV3]], align 2
16606 // CHECK18-NEXT:    [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
16607 // CHECK18-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]])
16608 // CHECK18-NEXT:    ret void
16609 //
16610 //
16611 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..16
16612 // CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
16613 // CHECK18-NEXT:  entry:
16614 // CHECK18-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
16615 // CHECK18-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
16616 // CHECK18-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
16617 // CHECK18-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
16618 // CHECK18-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
16619 // CHECK18-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
16620 // CHECK18-NEXT:    [[TMP:%.*]] = alloca i32, align 4
16621 // CHECK18-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
16622 // CHECK18-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
16623 // CHECK18-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
16624 // CHECK18-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
16625 // CHECK18-NEXT:    [[I:%.*]] = alloca i32, align 4
16626 // CHECK18-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
16627 // CHECK18-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
16628 // CHECK18-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
16629 // CHECK18-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
16630 // CHECK18-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
16631 // CHECK18-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
16632 // CHECK18-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
16633 // CHECK18-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
16634 // CHECK18-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
16635 // CHECK18-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
16636 // CHECK18-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
16637 // CHECK18-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
16638 // CHECK18-NEXT:    [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
16639 // CHECK18-NEXT:    [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
16640 // CHECK18-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
16641 // CHECK18-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
16642 // CHECK18-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9
16643 // CHECK18-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
16644 // CHECK18:       cond.true:
16645 // CHECK18-NEXT:    br label [[COND_END:%.*]]
16646 // CHECK18:       cond.false:
16647 // CHECK18-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
16648 // CHECK18-NEXT:    br label [[COND_END]]
16649 // CHECK18:       cond.end:
16650 // CHECK18-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
16651 // CHECK18-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
16652 // CHECK18-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
16653 // CHECK18-NEXT:    store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
16654 // CHECK18-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
16655 // CHECK18:       omp.inner.for.cond:
16656 // CHECK18-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
16657 // CHECK18-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
16658 // CHECK18-NEXT:    [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
16659 // CHECK18-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
16660 // CHECK18:       omp.inner.for.body:
16661 // CHECK18-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
16662 // CHECK18-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
16663 // CHECK18-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
16664 // CHECK18-NEXT:    store i32 [[ADD]], i32* [[I]], align 4
16665 // CHECK18-NEXT:    [[TMP9:%.*]] = load i32, i32* [[CONV]], align 8
16666 // CHECK18-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1
16667 // CHECK18-NEXT:    store i32 [[ADD3]], i32* [[CONV]], align 8
16668 // CHECK18-NEXT:    [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 8
16669 // CHECK18-NEXT:    [[CONV4:%.*]] = sext i16 [[TMP10]] to i32
16670 // CHECK18-NEXT:    [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
16671 // CHECK18-NEXT:    [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
16672 // CHECK18-NEXT:    store i16 [[CONV6]], i16* [[CONV1]], align 8
16673 // CHECK18-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
16674 // CHECK18-NEXT:    [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
16675 // CHECK18-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1
16676 // CHECK18-NEXT:    store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4
16677 // CHECK18-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
16678 // CHECK18:       omp.body.continue:
16679 // CHECK18-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
16680 // CHECK18:       omp.inner.for.inc:
16681 // CHECK18-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
16682 // CHECK18-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP12]], 1
16683 // CHECK18-NEXT:    store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4
16684 // CHECK18-NEXT:    br label [[OMP_INNER_FOR_COND]]
16685 // CHECK18:       omp.inner.for.end:
16686 // CHECK18-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
16687 // CHECK18:       omp.loop.exit:
16688 // CHECK18-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
16689 // CHECK18-NEXT:    ret void
16690 //
16691 //
16692 // CHECK18-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
16693 // CHECK18-SAME: () #[[ATTR4]] {
16694 // CHECK18-NEXT:  entry:
16695 // CHECK18-NEXT:    call void @__tgt_register_requires(i64 1)
16696 // CHECK18-NEXT:    ret void
16697 //
16698 //
16699 // CHECK19-LABEL: define {{[^@]+}}@_Z3fooi
16700 // CHECK19-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] {
16701 // CHECK19-NEXT:  entry:
16702 // CHECK19-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
16703 // CHECK19-NEXT:    [[A:%.*]] = alloca i32, align 4
16704 // CHECK19-NEXT:    [[AA:%.*]] = alloca i16, align 2
16705 // CHECK19-NEXT:    [[B:%.*]] = alloca [10 x float], align 4
16706 // CHECK19-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 4
16707 // CHECK19-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 4
16708 // CHECK19-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 8
16709 // CHECK19-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i32, align 4
16710 // CHECK19-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4
16711 // CHECK19-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
16712 // CHECK19-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
16713 // CHECK19-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
16714 // CHECK19-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
16715 // CHECK19-NEXT:    [[DOTCAPTURE_EXPR__CASTED3:%.*]] = alloca i32, align 4
16716 // CHECK19-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4
16717 // CHECK19-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4
16718 // CHECK19-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4
16719 // CHECK19-NEXT:    [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4
16720 // CHECK19-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
16721 // CHECK19-NEXT:    [[AA_CASTED4:%.*]] = alloca i32, align 4
16722 // CHECK19-NEXT:    [[DOTOFFLOAD_BASEPTRS6:%.*]] = alloca [1 x i8*], align 4
16723 // CHECK19-NEXT:    [[DOTOFFLOAD_PTRS7:%.*]] = alloca [1 x i8*], align 4
16724 // CHECK19-NEXT:    [[DOTOFFLOAD_MAPPERS8:%.*]] = alloca [1 x i8*], align 4
16725 // CHECK19-NEXT:    [[TMP:%.*]] = alloca i32, align 4
16726 // CHECK19-NEXT:    [[A_CASTED9:%.*]] = alloca i32, align 4
16727 // CHECK19-NEXT:    [[AA_CASTED10:%.*]] = alloca i32, align 4
16728 // CHECK19-NEXT:    [[DOTOFFLOAD_BASEPTRS12:%.*]] = alloca [2 x i8*], align 4
16729 // CHECK19-NEXT:    [[DOTOFFLOAD_PTRS13:%.*]] = alloca [2 x i8*], align 4
16730 // CHECK19-NEXT:    [[DOTOFFLOAD_MAPPERS14:%.*]] = alloca [2 x i8*], align 4
16731 // CHECK19-NEXT:    [[_TMP15:%.*]] = alloca i32, align 4
16732 // CHECK19-NEXT:    [[DOTCAPTURE_EXPR_18:%.*]] = alloca i32, align 4
16733 // CHECK19-NEXT:    [[A_CASTED19:%.*]] = alloca i32, align 4
16734 // CHECK19-NEXT:    [[DOTCAPTURE_EXPR__CASTED20:%.*]] = alloca i32, align 4
16735 // CHECK19-NEXT:    [[DOTOFFLOAD_BASEPTRS23:%.*]] = alloca [10 x i8*], align 4
16736 // CHECK19-NEXT:    [[DOTOFFLOAD_PTRS24:%.*]] = alloca [10 x i8*], align 4
16737 // CHECK19-NEXT:    [[DOTOFFLOAD_MAPPERS25:%.*]] = alloca [10 x i8*], align 4
16738 // CHECK19-NEXT:    [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 4
16739 // CHECK19-NEXT:    [[_TMP26:%.*]] = alloca i32, align 4
16740 // CHECK19-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]])
16741 // CHECK19-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
16742 // CHECK19-NEXT:    store i32 0, i32* [[A]], align 4
16743 // CHECK19-NEXT:    store i16 0, i16* [[AA]], align 2
16744 // CHECK19-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
16745 // CHECK19-NEXT:    [[TMP2:%.*]] = call i8* @llvm.stacksave()
16746 // CHECK19-NEXT:    store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4
16747 // CHECK19-NEXT:    [[VLA:%.*]] = alloca float, i32 [[TMP1]], align 4
16748 // CHECK19-NEXT:    store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
16749 // CHECK19-NEXT:    [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
16750 // CHECK19-NEXT:    [[TMP4:%.*]] = mul nuw i32 5, [[TMP3]]
16751 // CHECK19-NEXT:    [[VLA1:%.*]] = alloca double, i32 [[TMP4]], align 8
16752 // CHECK19-NEXT:    store i32 [[TMP3]], i32* [[__VLA_EXPR1]], align 4
16753 // CHECK19-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
16754 // CHECK19-NEXT:    store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_]], align 4
16755 // CHECK19-NEXT:    [[TMP6:%.*]] = load i32, i32* [[A]], align 4
16756 // CHECK19-NEXT:    store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_2]], align 4
16757 // CHECK19-NEXT:    [[TMP7:%.*]] = load i16, i16* [[AA]], align 2
16758 // CHECK19-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
16759 // CHECK19-NEXT:    store i16 [[TMP7]], i16* [[CONV]], align 2
16760 // CHECK19-NEXT:    [[TMP8:%.*]] = load i32, i32* [[AA_CASTED]], align 4
16761 // CHECK19-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
16762 // CHECK19-NEXT:    store i32 [[TMP9]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
16763 // CHECK19-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
16764 // CHECK19-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
16765 // CHECK19-NEXT:    store i32 [[TMP11]], i32* [[DOTCAPTURE_EXPR__CASTED3]], align 4
16766 // CHECK19-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED3]], align 4
16767 // CHECK19-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
16768 // CHECK19-NEXT:    [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i32*
16769 // CHECK19-NEXT:    store i32 [[TMP8]], i32* [[TMP14]], align 4
16770 // CHECK19-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
16771 // CHECK19-NEXT:    [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i32*
16772 // CHECK19-NEXT:    store i32 [[TMP8]], i32* [[TMP16]], align 4
16773 // CHECK19-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
16774 // CHECK19-NEXT:    store i8* null, i8** [[TMP17]], align 4
16775 // CHECK19-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
16776 // CHECK19-NEXT:    [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32*
16777 // CHECK19-NEXT:    store i32 [[TMP10]], i32* [[TMP19]], align 4
16778 // CHECK19-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
16779 // CHECK19-NEXT:    [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32*
16780 // CHECK19-NEXT:    store i32 [[TMP10]], i32* [[TMP21]], align 4
16781 // CHECK19-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
16782 // CHECK19-NEXT:    store i8* null, i8** [[TMP22]], align 4
16783 // CHECK19-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
16784 // CHECK19-NEXT:    [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i32*
16785 // CHECK19-NEXT:    store i32 [[TMP12]], i32* [[TMP24]], align 4
16786 // CHECK19-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
16787 // CHECK19-NEXT:    [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i32*
16788 // CHECK19-NEXT:    store i32 [[TMP12]], i32* [[TMP26]], align 4
16789 // CHECK19-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
16790 // CHECK19-NEXT:    store i8* null, i8** [[TMP27]], align 4
16791 // CHECK19-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
16792 // CHECK19-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
16793 // CHECK19-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 0
16794 // CHECK19-NEXT:    [[TMP31:%.*]] = load i16, i16* [[AA]], align 2
16795 // CHECK19-NEXT:    store i16 [[TMP31]], i16* [[TMP30]], align 4
16796 // CHECK19-NEXT:    [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 1
16797 // CHECK19-NEXT:    [[TMP33:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
16798 // CHECK19-NEXT:    store i32 [[TMP33]], i32* [[TMP32]], align 4
16799 // CHECK19-NEXT:    [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 2
16800 // CHECK19-NEXT:    [[TMP35:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
16801 // CHECK19-NEXT:    store i32 [[TMP35]], i32* [[TMP34]], align 4
16802 // CHECK19-NEXT:    [[TMP36:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 1, i32 72, i32 12, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1)
16803 // CHECK19-NEXT:    [[TMP37:%.*]] = bitcast i8* [[TMP36]] to %struct.kmp_task_t_with_privates*
16804 // CHECK19-NEXT:    [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP37]], i32 0, i32 0
16805 // CHECK19-NEXT:    [[TMP39:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP38]], i32 0, i32 0
16806 // CHECK19-NEXT:    [[TMP40:%.*]] = load i8*, i8** [[TMP39]], align 4
16807 // CHECK19-NEXT:    [[TMP41:%.*]] = bitcast %struct.anon* [[AGG_CAPTURED]] to i8*
16808 // CHECK19-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP40]], i8* align 4 [[TMP41]], i32 12, i1 false)
16809 // CHECK19-NEXT:    [[TMP42:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP37]], i32 0, i32 1
16810 // CHECK19-NEXT:    [[TMP43:%.*]] = bitcast i8* [[TMP40]] to %struct.anon*
16811 // CHECK19-NEXT:    [[TMP44:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 0
16812 // CHECK19-NEXT:    [[TMP45:%.*]] = bitcast [3 x i64]* [[TMP44]] to i8*
16813 // CHECK19-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP45]], i8* align 4 bitcast ([3 x i64]* @.offload_sizes to i8*), i32 24, i1 false)
16814 // CHECK19-NEXT:    [[TMP46:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 1
16815 // CHECK19-NEXT:    [[TMP47:%.*]] = bitcast [3 x i8*]* [[TMP46]] to i8*
16816 // CHECK19-NEXT:    [[TMP48:%.*]] = bitcast i8** [[TMP28]] to i8*
16817 // CHECK19-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP47]], i8* align 4 [[TMP48]], i32 12, i1 false)
16818 // CHECK19-NEXT:    [[TMP49:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 2
16819 // CHECK19-NEXT:    [[TMP50:%.*]] = bitcast [3 x i8*]* [[TMP49]] to i8*
16820 // CHECK19-NEXT:    [[TMP51:%.*]] = bitcast i8** [[TMP29]] to i8*
16821 // CHECK19-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP50]], i8* align 4 [[TMP51]], i32 12, i1 false)
16822 // CHECK19-NEXT:    [[TMP52:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 3
16823 // CHECK19-NEXT:    [[TMP53:%.*]] = load i16, i16* [[AA]], align 2
16824 // CHECK19-NEXT:    store i16 [[TMP53]], i16* [[TMP52]], align 4
16825 // CHECK19-NEXT:    [[TMP54:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i8* [[TMP36]])
16826 // CHECK19-NEXT:    [[TMP55:%.*]] = load i32, i32* [[A]], align 4
16827 // CHECK19-NEXT:    store i32 [[TMP55]], i32* [[A_CASTED]], align 4
16828 // CHECK19-NEXT:    [[TMP56:%.*]] = load i32, i32* [[A_CASTED]], align 4
16829 // CHECK19-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l107(i32 [[TMP56]]) #[[ATTR3:[0-9]+]]
16830 // CHECK19-NEXT:    [[TMP57:%.*]] = load i16, i16* [[AA]], align 2
16831 // CHECK19-NEXT:    [[CONV5:%.*]] = bitcast i32* [[AA_CASTED4]] to i16*
16832 // CHECK19-NEXT:    store i16 [[TMP57]], i16* [[CONV5]], align 2
16833 // CHECK19-NEXT:    [[TMP58:%.*]] = load i32, i32* [[AA_CASTED4]], align 4
16834 // CHECK19-NEXT:    [[TMP59:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0
16835 // CHECK19-NEXT:    [[TMP60:%.*]] = bitcast i8** [[TMP59]] to i32*
16836 // CHECK19-NEXT:    store i32 [[TMP58]], i32* [[TMP60]], align 4
16837 // CHECK19-NEXT:    [[TMP61:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0
16838 // CHECK19-NEXT:    [[TMP62:%.*]] = bitcast i8** [[TMP61]] to i32*
16839 // CHECK19-NEXT:    store i32 [[TMP58]], i32* [[TMP62]], align 4
16840 // CHECK19-NEXT:    [[TMP63:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS8]], i32 0, i32 0
16841 // CHECK19-NEXT:    store i8* null, i8** [[TMP63]], align 4
16842 // CHECK19-NEXT:    [[TMP64:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0
16843 // CHECK19-NEXT:    [[TMP65:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0
16844 // CHECK19-NEXT:    call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10)
16845 // CHECK19-NEXT:    [[TMP66:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113.region_id, i32 1, i8** [[TMP64]], i8** [[TMP65]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.4, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.5, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
16846 // CHECK19-NEXT:    [[TMP67:%.*]] = icmp ne i32 [[TMP66]], 0
16847 // CHECK19-NEXT:    br i1 [[TMP67]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
16848 // CHECK19:       omp_offload.failed:
16849 // CHECK19-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113(i32 [[TMP58]]) #[[ATTR3]]
16850 // CHECK19-NEXT:    br label [[OMP_OFFLOAD_CONT]]
16851 // CHECK19:       omp_offload.cont:
16852 // CHECK19-NEXT:    [[TMP68:%.*]] = load i32, i32* [[A]], align 4
16853 // CHECK19-NEXT:    store i32 [[TMP68]], i32* [[A_CASTED9]], align 4
16854 // CHECK19-NEXT:    [[TMP69:%.*]] = load i32, i32* [[A_CASTED9]], align 4
16855 // CHECK19-NEXT:    [[TMP70:%.*]] = load i16, i16* [[AA]], align 2
16856 // CHECK19-NEXT:    [[CONV11:%.*]] = bitcast i32* [[AA_CASTED10]] to i16*
16857 // CHECK19-NEXT:    store i16 [[TMP70]], i16* [[CONV11]], align 2
16858 // CHECK19-NEXT:    [[TMP71:%.*]] = load i32, i32* [[AA_CASTED10]], align 4
16859 // CHECK19-NEXT:    [[TMP72:%.*]] = load i32, i32* [[N_ADDR]], align 4
16860 // CHECK19-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP72]], 10
16861 // CHECK19-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
16862 // CHECK19:       omp_if.then:
16863 // CHECK19-NEXT:    [[TMP73:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS12]], i32 0, i32 0
16864 // CHECK19-NEXT:    [[TMP74:%.*]] = bitcast i8** [[TMP73]] to i32*
16865 // CHECK19-NEXT:    store i32 [[TMP69]], i32* [[TMP74]], align 4
16866 // CHECK19-NEXT:    [[TMP75:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS13]], i32 0, i32 0
16867 // CHECK19-NEXT:    [[TMP76:%.*]] = bitcast i8** [[TMP75]] to i32*
16868 // CHECK19-NEXT:    store i32 [[TMP69]], i32* [[TMP76]], align 4
16869 // CHECK19-NEXT:    [[TMP77:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS14]], i32 0, i32 0
16870 // CHECK19-NEXT:    store i8* null, i8** [[TMP77]], align 4
16871 // CHECK19-NEXT:    [[TMP78:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS12]], i32 0, i32 1
16872 // CHECK19-NEXT:    [[TMP79:%.*]] = bitcast i8** [[TMP78]] to i32*
16873 // CHECK19-NEXT:    store i32 [[TMP71]], i32* [[TMP79]], align 4
16874 // CHECK19-NEXT:    [[TMP80:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS13]], i32 0, i32 1
16875 // CHECK19-NEXT:    [[TMP81:%.*]] = bitcast i8** [[TMP80]] to i32*
16876 // CHECK19-NEXT:    store i32 [[TMP71]], i32* [[TMP81]], align 4
16877 // CHECK19-NEXT:    [[TMP82:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS14]], i32 0, i32 1
16878 // CHECK19-NEXT:    store i8* null, i8** [[TMP82]], align 4
16879 // CHECK19-NEXT:    [[TMP83:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS12]], i32 0, i32 0
16880 // CHECK19-NEXT:    [[TMP84:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS13]], i32 0, i32 0
16881 // CHECK19-NEXT:    call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10)
16882 // CHECK19-NEXT:    [[TMP85:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120.region_id, i32 2, i8** [[TMP83]], i8** [[TMP84]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.7, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.8, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
16883 // CHECK19-NEXT:    [[TMP86:%.*]] = icmp ne i32 [[TMP85]], 0
16884 // CHECK19-NEXT:    br i1 [[TMP86]], label [[OMP_OFFLOAD_FAILED16:%.*]], label [[OMP_OFFLOAD_CONT17:%.*]]
16885 // CHECK19:       omp_offload.failed16:
16886 // CHECK19-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120(i32 [[TMP69]], i32 [[TMP71]]) #[[ATTR3]]
16887 // CHECK19-NEXT:    br label [[OMP_OFFLOAD_CONT17]]
16888 // CHECK19:       omp_offload.cont17:
16889 // CHECK19-NEXT:    br label [[OMP_IF_END:%.*]]
16890 // CHECK19:       omp_if.else:
16891 // CHECK19-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120(i32 [[TMP69]], i32 [[TMP71]]) #[[ATTR3]]
16892 // CHECK19-NEXT:    br label [[OMP_IF_END]]
16893 // CHECK19:       omp_if.end:
16894 // CHECK19-NEXT:    [[TMP87:%.*]] = load i32, i32* [[N_ADDR]], align 4
16895 // CHECK19-NEXT:    store i32 [[TMP87]], i32* [[DOTCAPTURE_EXPR_18]], align 4
16896 // CHECK19-NEXT:    [[TMP88:%.*]] = load i32, i32* [[A]], align 4
16897 // CHECK19-NEXT:    store i32 [[TMP88]], i32* [[A_CASTED19]], align 4
16898 // CHECK19-NEXT:    [[TMP89:%.*]] = load i32, i32* [[A_CASTED19]], align 4
16899 // CHECK19-NEXT:    [[TMP90:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_18]], align 4
16900 // CHECK19-NEXT:    store i32 [[TMP90]], i32* [[DOTCAPTURE_EXPR__CASTED20]], align 4
16901 // CHECK19-NEXT:    [[TMP91:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED20]], align 4
16902 // CHECK19-NEXT:    [[TMP92:%.*]] = load i32, i32* [[N_ADDR]], align 4
16903 // CHECK19-NEXT:    [[CMP21:%.*]] = icmp sgt i32 [[TMP92]], 20
16904 // CHECK19-NEXT:    br i1 [[CMP21]], label [[OMP_IF_THEN22:%.*]], label [[OMP_IF_ELSE29:%.*]]
16905 // CHECK19:       omp_if.then22:
16906 // CHECK19-NEXT:    [[TMP93:%.*]] = mul nuw i32 [[TMP1]], 4
16907 // CHECK19-NEXT:    [[TMP94:%.*]] = sext i32 [[TMP93]] to i64
16908 // CHECK19-NEXT:    [[TMP95:%.*]] = mul nuw i32 5, [[TMP3]]
16909 // CHECK19-NEXT:    [[TMP96:%.*]] = mul nuw i32 [[TMP95]], 8
16910 // CHECK19-NEXT:    [[TMP97:%.*]] = sext i32 [[TMP96]] to i64
16911 // CHECK19-NEXT:    [[TMP98:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS23]], i32 0, i32 0
16912 // CHECK19-NEXT:    [[TMP99:%.*]] = bitcast i8** [[TMP98]] to i32*
16913 // CHECK19-NEXT:    store i32 [[TMP89]], i32* [[TMP99]], align 4
16914 // CHECK19-NEXT:    [[TMP100:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS24]], i32 0, i32 0
16915 // CHECK19-NEXT:    [[TMP101:%.*]] = bitcast i8** [[TMP100]] to i32*
16916 // CHECK19-NEXT:    store i32 [[TMP89]], i32* [[TMP101]], align 4
16917 // CHECK19-NEXT:    [[TMP102:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
16918 // CHECK19-NEXT:    store i64 4, i64* [[TMP102]], align 4
16919 // CHECK19-NEXT:    [[TMP103:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS25]], i32 0, i32 0
16920 // CHECK19-NEXT:    store i8* null, i8** [[TMP103]], align 4
16921 // CHECK19-NEXT:    [[TMP104:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS23]], i32 0, i32 1
16922 // CHECK19-NEXT:    [[TMP105:%.*]] = bitcast i8** [[TMP104]] to [10 x float]**
16923 // CHECK19-NEXT:    store [10 x float]* [[B]], [10 x float]** [[TMP105]], align 4
16924 // CHECK19-NEXT:    [[TMP106:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS24]], i32 0, i32 1
16925 // CHECK19-NEXT:    [[TMP107:%.*]] = bitcast i8** [[TMP106]] to [10 x float]**
16926 // CHECK19-NEXT:    store [10 x float]* [[B]], [10 x float]** [[TMP107]], align 4
16927 // CHECK19-NEXT:    [[TMP108:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1
16928 // CHECK19-NEXT:    store i64 40, i64* [[TMP108]], align 4
16929 // CHECK19-NEXT:    [[TMP109:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS25]], i32 0, i32 1
16930 // CHECK19-NEXT:    store i8* null, i8** [[TMP109]], align 4
16931 // CHECK19-NEXT:    [[TMP110:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS23]], i32 0, i32 2
16932 // CHECK19-NEXT:    [[TMP111:%.*]] = bitcast i8** [[TMP110]] to i32*
16933 // CHECK19-NEXT:    store i32 [[TMP1]], i32* [[TMP111]], align 4
16934 // CHECK19-NEXT:    [[TMP112:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS24]], i32 0, i32 2
16935 // CHECK19-NEXT:    [[TMP113:%.*]] = bitcast i8** [[TMP112]] to i32*
16936 // CHECK19-NEXT:    store i32 [[TMP1]], i32* [[TMP113]], align 4
16937 // CHECK19-NEXT:    [[TMP114:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2
16938 // CHECK19-NEXT:    store i64 4, i64* [[TMP114]], align 4
16939 // CHECK19-NEXT:    [[TMP115:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS25]], i32 0, i32 2
16940 // CHECK19-NEXT:    store i8* null, i8** [[TMP115]], align 4
16941 // CHECK19-NEXT:    [[TMP116:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS23]], i32 0, i32 3
16942 // CHECK19-NEXT:    [[TMP117:%.*]] = bitcast i8** [[TMP116]] to float**
16943 // CHECK19-NEXT:    store float* [[VLA]], float** [[TMP117]], align 4
16944 // CHECK19-NEXT:    [[TMP118:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS24]], i32 0, i32 3
16945 // CHECK19-NEXT:    [[TMP119:%.*]] = bitcast i8** [[TMP118]] to float**
16946 // CHECK19-NEXT:    store float* [[VLA]], float** [[TMP119]], align 4
16947 // CHECK19-NEXT:    [[TMP120:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3
16948 // CHECK19-NEXT:    store i64 [[TMP94]], i64* [[TMP120]], align 4
16949 // CHECK19-NEXT:    [[TMP121:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS25]], i32 0, i32 3
16950 // CHECK19-NEXT:    store i8* null, i8** [[TMP121]], align 4
16951 // CHECK19-NEXT:    [[TMP122:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS23]], i32 0, i32 4
16952 // CHECK19-NEXT:    [[TMP123:%.*]] = bitcast i8** [[TMP122]] to [5 x [10 x double]]**
16953 // CHECK19-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP123]], align 4
16954 // CHECK19-NEXT:    [[TMP124:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS24]], i32 0, i32 4
16955 // CHECK19-NEXT:    [[TMP125:%.*]] = bitcast i8** [[TMP124]] to [5 x [10 x double]]**
16956 // CHECK19-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP125]], align 4
16957 // CHECK19-NEXT:    [[TMP126:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4
16958 // CHECK19-NEXT:    store i64 400, i64* [[TMP126]], align 4
16959 // CHECK19-NEXT:    [[TMP127:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS25]], i32 0, i32 4
16960 // CHECK19-NEXT:    store i8* null, i8** [[TMP127]], align 4
16961 // CHECK19-NEXT:    [[TMP128:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS23]], i32 0, i32 5
16962 // CHECK19-NEXT:    [[TMP129:%.*]] = bitcast i8** [[TMP128]] to i32*
16963 // CHECK19-NEXT:    store i32 5, i32* [[TMP129]], align 4
16964 // CHECK19-NEXT:    [[TMP130:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS24]], i32 0, i32 5
16965 // CHECK19-NEXT:    [[TMP131:%.*]] = bitcast i8** [[TMP130]] to i32*
16966 // CHECK19-NEXT:    store i32 5, i32* [[TMP131]], align 4
16967 // CHECK19-NEXT:    [[TMP132:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 5
16968 // CHECK19-NEXT:    store i64 4, i64* [[TMP132]], align 4
16969 // CHECK19-NEXT:    [[TMP133:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS25]], i32 0, i32 5
16970 // CHECK19-NEXT:    store i8* null, i8** [[TMP133]], align 4
16971 // CHECK19-NEXT:    [[TMP134:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS23]], i32 0, i32 6
16972 // CHECK19-NEXT:    [[TMP135:%.*]] = bitcast i8** [[TMP134]] to i32*
16973 // CHECK19-NEXT:    store i32 [[TMP3]], i32* [[TMP135]], align 4
16974 // CHECK19-NEXT:    [[TMP136:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS24]], i32 0, i32 6
16975 // CHECK19-NEXT:    [[TMP137:%.*]] = bitcast i8** [[TMP136]] to i32*
16976 // CHECK19-NEXT:    store i32 [[TMP3]], i32* [[TMP137]], align 4
16977 // CHECK19-NEXT:    [[TMP138:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 6
16978 // CHECK19-NEXT:    store i64 4, i64* [[TMP138]], align 4
16979 // CHECK19-NEXT:    [[TMP139:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS25]], i32 0, i32 6
16980 // CHECK19-NEXT:    store i8* null, i8** [[TMP139]], align 4
16981 // CHECK19-NEXT:    [[TMP140:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS23]], i32 0, i32 7
16982 // CHECK19-NEXT:    [[TMP141:%.*]] = bitcast i8** [[TMP140]] to double**
16983 // CHECK19-NEXT:    store double* [[VLA1]], double** [[TMP141]], align 4
16984 // CHECK19-NEXT:    [[TMP142:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS24]], i32 0, i32 7
16985 // CHECK19-NEXT:    [[TMP143:%.*]] = bitcast i8** [[TMP142]] to double**
16986 // CHECK19-NEXT:    store double* [[VLA1]], double** [[TMP143]], align 4
16987 // CHECK19-NEXT:    [[TMP144:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7
16988 // CHECK19-NEXT:    store i64 [[TMP97]], i64* [[TMP144]], align 4
16989 // CHECK19-NEXT:    [[TMP145:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS25]], i32 0, i32 7
16990 // CHECK19-NEXT:    store i8* null, i8** [[TMP145]], align 4
16991 // CHECK19-NEXT:    [[TMP146:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS23]], i32 0, i32 8
16992 // CHECK19-NEXT:    [[TMP147:%.*]] = bitcast i8** [[TMP146]] to %struct.TT**
16993 // CHECK19-NEXT:    store %struct.TT* [[D]], %struct.TT** [[TMP147]], align 4
16994 // CHECK19-NEXT:    [[TMP148:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS24]], i32 0, i32 8
16995 // CHECK19-NEXT:    [[TMP149:%.*]] = bitcast i8** [[TMP148]] to %struct.TT**
16996 // CHECK19-NEXT:    store %struct.TT* [[D]], %struct.TT** [[TMP149]], align 4
16997 // CHECK19-NEXT:    [[TMP150:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 8
16998 // CHECK19-NEXT:    store i64 12, i64* [[TMP150]], align 4
16999 // CHECK19-NEXT:    [[TMP151:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS25]], i32 0, i32 8
17000 // CHECK19-NEXT:    store i8* null, i8** [[TMP151]], align 4
17001 // CHECK19-NEXT:    [[TMP152:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS23]], i32 0, i32 9
17002 // CHECK19-NEXT:    [[TMP153:%.*]] = bitcast i8** [[TMP152]] to i32*
17003 // CHECK19-NEXT:    store i32 [[TMP91]], i32* [[TMP153]], align 4
17004 // CHECK19-NEXT:    [[TMP154:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS24]], i32 0, i32 9
17005 // CHECK19-NEXT:    [[TMP155:%.*]] = bitcast i8** [[TMP154]] to i32*
17006 // CHECK19-NEXT:    store i32 [[TMP91]], i32* [[TMP155]], align 4
17007 // CHECK19-NEXT:    [[TMP156:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 9
17008 // CHECK19-NEXT:    store i64 4, i64* [[TMP156]], align 4
17009 // CHECK19-NEXT:    [[TMP157:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS25]], i32 0, i32 9
17010 // CHECK19-NEXT:    store i8* null, i8** [[TMP157]], align 4
17011 // CHECK19-NEXT:    [[TMP158:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS23]], i32 0, i32 0
17012 // CHECK19-NEXT:    [[TMP159:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS24]], i32 0, i32 0
17013 // CHECK19-NEXT:    [[TMP160:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
17014 // CHECK19-NEXT:    call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10)
17015 // CHECK19-NEXT:    [[TMP161:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145.region_id, i32 10, i8** [[TMP158]], i8** [[TMP159]], i64* [[TMP160]], i64* getelementptr inbounds ([10 x i64], [10 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
17016 // CHECK19-NEXT:    [[TMP162:%.*]] = icmp ne i32 [[TMP161]], 0
17017 // CHECK19-NEXT:    br i1 [[TMP162]], label [[OMP_OFFLOAD_FAILED27:%.*]], label [[OMP_OFFLOAD_CONT28:%.*]]
17018 // CHECK19:       omp_offload.failed27:
17019 // CHECK19-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145(i32 [[TMP89]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]], i32 [[TMP91]]) #[[ATTR3]]
17020 // CHECK19-NEXT:    br label [[OMP_OFFLOAD_CONT28]]
17021 // CHECK19:       omp_offload.cont28:
17022 // CHECK19-NEXT:    br label [[OMP_IF_END30:%.*]]
17023 // CHECK19:       omp_if.else29:
17024 // CHECK19-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145(i32 [[TMP89]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]], i32 [[TMP91]]) #[[ATTR3]]
17025 // CHECK19-NEXT:    br label [[OMP_IF_END30]]
17026 // CHECK19:       omp_if.end30:
17027 // CHECK19-NEXT:    [[TMP163:%.*]] = load i32, i32* [[A]], align 4
17028 // CHECK19-NEXT:    [[TMP164:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
17029 // CHECK19-NEXT:    call void @llvm.stackrestore(i8* [[TMP164]])
17030 // CHECK19-NEXT:    ret i32 [[TMP163]]
17031 //
17032 //
17033 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103
17034 // CHECK19-SAME: (i32 [[AA:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]], i32 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] {
17035 // CHECK19-NEXT:  entry:
17036 // CHECK19-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
17037 // CHECK19-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
17038 // CHECK19-NEXT:    [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4
17039 // CHECK19-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
17040 // CHECK19-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]])
17041 // CHECK19-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
17042 // CHECK19-NEXT:    store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
17043 // CHECK19-NEXT:    store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4
17044 // CHECK19-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
17045 // CHECK19-NEXT:    [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
17046 // CHECK19-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4
17047 // CHECK19-NEXT:    call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
17048 // CHECK19-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
17049 // CHECK19-NEXT:    [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
17050 // CHECK19-NEXT:    store i16 [[TMP3]], i16* [[CONV3]], align 2
17051 // CHECK19-NEXT:    [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
17052 // CHECK19-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]])
17053 // CHECK19-NEXT:    ret void
17054 //
17055 //
17056 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined.
17057 // CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] {
17058 // CHECK19-NEXT:  entry:
17059 // CHECK19-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
17060 // CHECK19-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
17061 // CHECK19-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
17062 // CHECK19-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
17063 // CHECK19-NEXT:    [[TMP:%.*]] = alloca i32, align 4
17064 // CHECK19-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
17065 // CHECK19-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
17066 // CHECK19-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
17067 // CHECK19-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
17068 // CHECK19-NEXT:    [[I:%.*]] = alloca i32, align 4
17069 // CHECK19-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
17070 // CHECK19-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
17071 // CHECK19-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
17072 // CHECK19-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
17073 // CHECK19-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
17074 // CHECK19-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
17075 // CHECK19-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
17076 // CHECK19-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
17077 // CHECK19-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
17078 // CHECK19-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
17079 // CHECK19-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
17080 // CHECK19-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
17081 // CHECK19-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
17082 // CHECK19-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
17083 // CHECK19:       cond.true:
17084 // CHECK19-NEXT:    br label [[COND_END:%.*]]
17085 // CHECK19:       cond.false:
17086 // CHECK19-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
17087 // CHECK19-NEXT:    br label [[COND_END]]
17088 // CHECK19:       cond.end:
17089 // CHECK19-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
17090 // CHECK19-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
17091 // CHECK19-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
17092 // CHECK19-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
17093 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
17094 // CHECK19:       omp.inner.for.cond:
17095 // CHECK19-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
17096 // CHECK19-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
17097 // CHECK19-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
17098 // CHECK19-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
17099 // CHECK19:       omp.inner.for.body:
17100 // CHECK19-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
17101 // CHECK19-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
17102 // CHECK19-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
17103 // CHECK19-NEXT:    store i32 [[ADD]], i32* [[I]], align 4
17104 // CHECK19-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
17105 // CHECK19:       omp.body.continue:
17106 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
17107 // CHECK19:       omp.inner.for.inc:
17108 // CHECK19-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
17109 // CHECK19-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
17110 // CHECK19-NEXT:    store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4
17111 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_COND]]
17112 // CHECK19:       omp.inner.for.end:
17113 // CHECK19-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
17114 // CHECK19:       omp.loop.exit:
17115 // CHECK19-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
17116 // CHECK19-NEXT:    ret void
17117 //
17118 //
17119 // CHECK19-LABEL: define {{[^@]+}}@.omp_task_privates_map.
17120 // CHECK19-SAME: (%struct..kmp_privates.t* noalias [[TMP0:%.*]], i16** noalias [[TMP1:%.*]], [3 x i8*]** noalias [[TMP2:%.*]], [3 x i8*]** noalias [[TMP3:%.*]], [3 x i64]** noalias [[TMP4:%.*]]) #[[ATTR4:[0-9]+]] {
17121 // CHECK19-NEXT:  entry:
17122 // CHECK19-NEXT:    [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 4
17123 // CHECK19-NEXT:    [[DOTADDR1:%.*]] = alloca i16**, align 4
17124 // CHECK19-NEXT:    [[DOTADDR2:%.*]] = alloca [3 x i8*]**, align 4
17125 // CHECK19-NEXT:    [[DOTADDR3:%.*]] = alloca [3 x i8*]**, align 4
17126 // CHECK19-NEXT:    [[DOTADDR4:%.*]] = alloca [3 x i64]**, align 4
17127 // CHECK19-NEXT:    store %struct..kmp_privates.t* [[TMP0]], %struct..kmp_privates.t** [[DOTADDR]], align 4
17128 // CHECK19-NEXT:    store i16** [[TMP1]], i16*** [[DOTADDR1]], align 4
17129 // CHECK19-NEXT:    store [3 x i8*]** [[TMP2]], [3 x i8*]*** [[DOTADDR2]], align 4
17130 // CHECK19-NEXT:    store [3 x i8*]** [[TMP3]], [3 x i8*]*** [[DOTADDR3]], align 4
17131 // CHECK19-NEXT:    store [3 x i64]** [[TMP4]], [3 x i64]*** [[DOTADDR4]], align 4
17132 // CHECK19-NEXT:    [[TMP5:%.*]] = load %struct..kmp_privates.t*, %struct..kmp_privates.t** [[DOTADDR]], align 4
17133 // CHECK19-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 0
17134 // CHECK19-NEXT:    [[TMP7:%.*]] = load [3 x i64]**, [3 x i64]*** [[DOTADDR4]], align 4
17135 // CHECK19-NEXT:    store [3 x i64]* [[TMP6]], [3 x i64]** [[TMP7]], align 4
17136 // CHECK19-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 1
17137 // CHECK19-NEXT:    [[TMP9:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR2]], align 4
17138 // CHECK19-NEXT:    store [3 x i8*]* [[TMP8]], [3 x i8*]** [[TMP9]], align 4
17139 // CHECK19-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 2
17140 // CHECK19-NEXT:    [[TMP11:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR3]], align 4
17141 // CHECK19-NEXT:    store [3 x i8*]* [[TMP10]], [3 x i8*]** [[TMP11]], align 4
17142 // CHECK19-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 3
17143 // CHECK19-NEXT:    [[TMP13:%.*]] = load i16**, i16*** [[DOTADDR1]], align 4
17144 // CHECK19-NEXT:    store i16* [[TMP12]], i16** [[TMP13]], align 4
17145 // CHECK19-NEXT:    ret void
17146 //
17147 //
17148 // CHECK19-LABEL: define {{[^@]+}}@.omp_task_entry.
17149 // CHECK19-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] {
17150 // CHECK19-NEXT:  entry:
17151 // CHECK19-NEXT:    [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
17152 // CHECK19-NEXT:    [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 4
17153 // CHECK19-NEXT:    [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 4
17154 // CHECK19-NEXT:    [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 4
17155 // CHECK19-NEXT:    [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 4
17156 // CHECK19-NEXT:    [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 4
17157 // CHECK19-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca i16*, align 4
17158 // CHECK19-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca [3 x i8*]*, align 4
17159 // CHECK19-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca [3 x i8*]*, align 4
17160 // CHECK19-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca [3 x i64]*, align 4
17161 // CHECK19-NEXT:    [[AA_CASTED_I:%.*]] = alloca i32, align 4
17162 // CHECK19-NEXT:    [[DOTCAPTURE_EXPR__CASTED_I:%.*]] = alloca i32, align 4
17163 // CHECK19-NEXT:    [[DOTCAPTURE_EXPR__CASTED4_I:%.*]] = alloca i32, align 4
17164 // CHECK19-NEXT:    [[DOTADDR:%.*]] = alloca i32, align 4
17165 // CHECK19-NEXT:    [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 4
17166 // CHECK19-NEXT:    store i32 [[TMP0]], i32* [[DOTADDR]], align 4
17167 // CHECK19-NEXT:    store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4
17168 // CHECK19-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4
17169 // CHECK19-NEXT:    [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4
17170 // CHECK19-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
17171 // CHECK19-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
17172 // CHECK19-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0
17173 // CHECK19-NEXT:    [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 4
17174 // CHECK19-NEXT:    [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon*
17175 // CHECK19-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1
17176 // CHECK19-NEXT:    [[TMP10:%.*]] = bitcast %struct..kmp_privates.t* [[TMP9]] to i8*
17177 // CHECK19-NEXT:    [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8*
17178 // CHECK19-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META12:![0-9]+]])
17179 // CHECK19-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]])
17180 // CHECK19-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META17:![0-9]+]])
17181 // CHECK19-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]])
17182 // CHECK19-NEXT:    store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !21
17183 // CHECK19-NEXT:    store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 4, !noalias !21
17184 // CHECK19-NEXT:    store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !21
17185 // CHECK19-NEXT:    store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* @.omp_task_privates_map. to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !21
17186 // CHECK19-NEXT:    store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 4, !noalias !21
17187 // CHECK19-NEXT:    store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !21
17188 // CHECK19-NEXT:    [[TMP12:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !21
17189 // CHECK19-NEXT:    [[TMP13:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !21
17190 // CHECK19-NEXT:    [[TMP14:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !21
17191 // CHECK19-NEXT:    [[TMP15:%.*]] = bitcast void (i8*, ...)* [[TMP13]] to void (i8*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)*
17192 // CHECK19-NEXT:    call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]]
17193 // CHECK19-NEXT:    [[TMP16:%.*]] = load i16*, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 4, !noalias !21
17194 // CHECK19-NEXT:    [[TMP17:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 4, !noalias !21
17195 // CHECK19-NEXT:    [[TMP18:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 4, !noalias !21
17196 // CHECK19-NEXT:    [[TMP19:%.*]] = load [3 x i64]*, [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 4, !noalias !21
17197 // CHECK19-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP17]], i32 0, i32 0
17198 // CHECK19-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP18]], i32 0, i32 0
17199 // CHECK19-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[TMP19]], i32 0, i32 0
17200 // CHECK19-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP12]], i32 0, i32 1
17201 // CHECK19-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[TMP12]], i32 0, i32 2
17202 // CHECK19-NEXT:    [[TMP25:%.*]] = load i32, i32* [[TMP23]], align 4
17203 // CHECK19-NEXT:    [[TMP26:%.*]] = load i32, i32* [[TMP24]], align 4
17204 // CHECK19-NEXT:    call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) #[[ATTR3]]
17205 // CHECK19-NEXT:    [[TMP27:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 [[TMP25]], i32 [[TMP26]]) #[[ATTR3]]
17206 // CHECK19-NEXT:    [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0
17207 // CHECK19-NEXT:    br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]]
17208 // CHECK19:       omp_offload.failed.i:
17209 // CHECK19-NEXT:    [[TMP29:%.*]] = load i16, i16* [[TMP16]], align 2
17210 // CHECK19-NEXT:    [[CONV_I:%.*]] = bitcast i32* [[AA_CASTED_I]] to i16*
17211 // CHECK19-NEXT:    store i16 [[TMP29]], i16* [[CONV_I]], align 2, !noalias !21
17212 // CHECK19-NEXT:    [[TMP30:%.*]] = load i32, i32* [[AA_CASTED_I]], align 4, !noalias !21
17213 // CHECK19-NEXT:    [[TMP31:%.*]] = load i32, i32* [[TMP23]], align 4
17214 // CHECK19-NEXT:    store i32 [[TMP31]], i32* [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias !21
17215 // CHECK19-NEXT:    [[TMP32:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias !21
17216 // CHECK19-NEXT:    [[TMP33:%.*]] = load i32, i32* [[TMP24]], align 4
17217 // CHECK19-NEXT:    store i32 [[TMP33]], i32* [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias !21
17218 // CHECK19-NEXT:    [[TMP34:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias !21
17219 // CHECK19-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103(i32 [[TMP30]], i32 [[TMP32]], i32 [[TMP34]]) #[[ATTR3]]
17220 // CHECK19-NEXT:    br label [[DOTOMP_OUTLINED__1_EXIT]]
17221 // CHECK19:       .omp_outlined..1.exit:
17222 // CHECK19-NEXT:    ret i32 0
17223 //
17224 //
17225 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l107
17226 // CHECK19-SAME: (i32 [[A:%.*]]) #[[ATTR2]] {
17227 // CHECK19-NEXT:  entry:
17228 // CHECK19-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
17229 // CHECK19-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
17230 // CHECK19-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
17231 // CHECK19-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
17232 // CHECK19-NEXT:    store i32 [[TMP0]], i32* [[A_CASTED]], align 4
17233 // CHECK19-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
17234 // CHECK19-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]])
17235 // CHECK19-NEXT:    ret void
17236 //
17237 //
17238 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..2
17239 // CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]]) #[[ATTR2]] {
17240 // CHECK19-NEXT:  entry:
17241 // CHECK19-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
17242 // CHECK19-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
17243 // CHECK19-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
17244 // CHECK19-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
17245 // CHECK19-NEXT:    [[TMP:%.*]] = alloca i32, align 4
17246 // CHECK19-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
17247 // CHECK19-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
17248 // CHECK19-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
17249 // CHECK19-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
17250 // CHECK19-NEXT:    [[I:%.*]] = alloca i32, align 4
17251 // CHECK19-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
17252 // CHECK19-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
17253 // CHECK19-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
17254 // CHECK19-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
17255 // CHECK19-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
17256 // CHECK19-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
17257 // CHECK19-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
17258 // CHECK19-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
17259 // CHECK19-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
17260 // CHECK19-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
17261 // CHECK19-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
17262 // CHECK19-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
17263 // CHECK19-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
17264 // CHECK19:       cond.true:
17265 // CHECK19-NEXT:    br label [[COND_END:%.*]]
17266 // CHECK19:       cond.false:
17267 // CHECK19-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
17268 // CHECK19-NEXT:    br label [[COND_END]]
17269 // CHECK19:       cond.end:
17270 // CHECK19-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
17271 // CHECK19-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
17272 // CHECK19-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
17273 // CHECK19-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
17274 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
17275 // CHECK19:       omp.inner.for.cond:
17276 // CHECK19-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
17277 // CHECK19-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
17278 // CHECK19-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
17279 // CHECK19-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
17280 // CHECK19:       omp.inner.for.body:
17281 // CHECK19-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
17282 // CHECK19-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
17283 // CHECK19-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
17284 // CHECK19-NEXT:    store i32 [[ADD]], i32* [[I]], align 4
17285 // CHECK19-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
17286 // CHECK19-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
17287 // CHECK19-NEXT:    store i32 [[ADD2]], i32* [[A_ADDR]], align 4
17288 // CHECK19-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
17289 // CHECK19:       omp.body.continue:
17290 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
17291 // CHECK19:       omp.inner.for.inc:
17292 // CHECK19-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
17293 // CHECK19-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1
17294 // CHECK19-NEXT:    store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4
17295 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_COND]]
17296 // CHECK19:       omp.inner.for.end:
17297 // CHECK19-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
17298 // CHECK19:       omp.loop.exit:
17299 // CHECK19-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
17300 // CHECK19-NEXT:    ret void
17301 //
17302 //
17303 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113
17304 // CHECK19-SAME: (i32 [[AA:%.*]]) #[[ATTR2]] {
17305 // CHECK19-NEXT:  entry:
17306 // CHECK19-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
17307 // CHECK19-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
17308 // CHECK19-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
17309 // CHECK19-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
17310 // CHECK19-NEXT:    [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
17311 // CHECK19-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
17312 // CHECK19-NEXT:    store i16 [[TMP0]], i16* [[CONV1]], align 2
17313 // CHECK19-NEXT:    [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
17314 // CHECK19-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP1]])
17315 // CHECK19-NEXT:    ret void
17316 //
17317 //
17318 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..3
17319 // CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] {
17320 // CHECK19-NEXT:  entry:
17321 // CHECK19-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
17322 // CHECK19-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
17323 // CHECK19-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
17324 // CHECK19-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
17325 // CHECK19-NEXT:    [[TMP:%.*]] = alloca i32, align 4
17326 // CHECK19-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
17327 // CHECK19-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
17328 // CHECK19-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
17329 // CHECK19-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
17330 // CHECK19-NEXT:    [[I:%.*]] = alloca i32, align 4
17331 // CHECK19-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
17332 // CHECK19-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
17333 // CHECK19-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
17334 // CHECK19-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
17335 // CHECK19-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
17336 // CHECK19-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
17337 // CHECK19-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
17338 // CHECK19-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
17339 // CHECK19-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
17340 // CHECK19-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
17341 // CHECK19-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
17342 // CHECK19-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
17343 // CHECK19-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
17344 // CHECK19-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
17345 // CHECK19:       cond.true:
17346 // CHECK19-NEXT:    br label [[COND_END:%.*]]
17347 // CHECK19:       cond.false:
17348 // CHECK19-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
17349 // CHECK19-NEXT:    br label [[COND_END]]
17350 // CHECK19:       cond.end:
17351 // CHECK19-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
17352 // CHECK19-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
17353 // CHECK19-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
17354 // CHECK19-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
17355 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
17356 // CHECK19:       omp.inner.for.cond:
17357 // CHECK19-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
17358 // CHECK19-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
17359 // CHECK19-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
17360 // CHECK19-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
17361 // CHECK19:       omp.inner.for.body:
17362 // CHECK19-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
17363 // CHECK19-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
17364 // CHECK19-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
17365 // CHECK19-NEXT:    store i32 [[ADD]], i32* [[I]], align 4
17366 // CHECK19-NEXT:    [[TMP8:%.*]] = load i16, i16* [[CONV]], align 4
17367 // CHECK19-NEXT:    [[CONV2:%.*]] = sext i16 [[TMP8]] to i32
17368 // CHECK19-NEXT:    [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
17369 // CHECK19-NEXT:    [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
17370 // CHECK19-NEXT:    store i16 [[CONV4]], i16* [[CONV]], align 4
17371 // CHECK19-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
17372 // CHECK19:       omp.body.continue:
17373 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
17374 // CHECK19:       omp.inner.for.inc:
17375 // CHECK19-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
17376 // CHECK19-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP9]], 1
17377 // CHECK19-NEXT:    store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4
17378 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_COND]]
17379 // CHECK19:       omp.inner.for.end:
17380 // CHECK19-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
17381 // CHECK19:       omp.loop.exit:
17382 // CHECK19-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
17383 // CHECK19-NEXT:    ret void
17384 //
17385 //
17386 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120
17387 // CHECK19-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] {
17388 // CHECK19-NEXT:  entry:
17389 // CHECK19-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
17390 // CHECK19-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
17391 // CHECK19-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
17392 // CHECK19-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
17393 // CHECK19-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
17394 // CHECK19-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
17395 // CHECK19-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
17396 // CHECK19-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
17397 // CHECK19-NEXT:    store i32 [[TMP0]], i32* [[A_CASTED]], align 4
17398 // CHECK19-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
17399 // CHECK19-NEXT:    [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
17400 // CHECK19-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
17401 // CHECK19-NEXT:    store i16 [[TMP2]], i16* [[CONV1]], align 2
17402 // CHECK19-NEXT:    [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
17403 // CHECK19-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]])
17404 // CHECK19-NEXT:    ret void
17405 //
17406 //
17407 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..6
17408 // CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] {
17409 // CHECK19-NEXT:  entry:
17410 // CHECK19-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
17411 // CHECK19-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
17412 // CHECK19-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
17413 // CHECK19-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
17414 // CHECK19-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
17415 // CHECK19-NEXT:    [[TMP:%.*]] = alloca i32, align 4
17416 // CHECK19-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
17417 // CHECK19-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
17418 // CHECK19-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
17419 // CHECK19-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
17420 // CHECK19-NEXT:    [[I:%.*]] = alloca i32, align 4
17421 // CHECK19-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
17422 // CHECK19-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
17423 // CHECK19-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
17424 // CHECK19-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
17425 // CHECK19-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
17426 // CHECK19-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
17427 // CHECK19-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
17428 // CHECK19-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
17429 // CHECK19-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
17430 // CHECK19-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
17431 // CHECK19-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
17432 // CHECK19-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
17433 // CHECK19-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
17434 // CHECK19-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
17435 // CHECK19-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
17436 // CHECK19:       cond.true:
17437 // CHECK19-NEXT:    br label [[COND_END:%.*]]
17438 // CHECK19:       cond.false:
17439 // CHECK19-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
17440 // CHECK19-NEXT:    br label [[COND_END]]
17441 // CHECK19:       cond.end:
17442 // CHECK19-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
17443 // CHECK19-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
17444 // CHECK19-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
17445 // CHECK19-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
17446 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
17447 // CHECK19:       omp.inner.for.cond:
17448 // CHECK19-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
17449 // CHECK19-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
17450 // CHECK19-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
17451 // CHECK19-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
17452 // CHECK19:       omp.inner.for.body:
17453 // CHECK19-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
17454 // CHECK19-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
17455 // CHECK19-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
17456 // CHECK19-NEXT:    store i32 [[ADD]], i32* [[I]], align 4
17457 // CHECK19-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
17458 // CHECK19-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
17459 // CHECK19-NEXT:    store i32 [[ADD2]], i32* [[A_ADDR]], align 4
17460 // CHECK19-NEXT:    [[TMP9:%.*]] = load i16, i16* [[CONV]], align 4
17461 // CHECK19-NEXT:    [[CONV3:%.*]] = sext i16 [[TMP9]] to i32
17462 // CHECK19-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
17463 // CHECK19-NEXT:    [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
17464 // CHECK19-NEXT:    store i16 [[CONV5]], i16* [[CONV]], align 4
17465 // CHECK19-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
17466 // CHECK19:       omp.body.continue:
17467 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
17468 // CHECK19:       omp.inner.for.inc:
17469 // CHECK19-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
17470 // CHECK19-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP10]], 1
17471 // CHECK19-NEXT:    store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4
17472 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_COND]]
17473 // CHECK19:       omp.inner.for.end:
17474 // CHECK19-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
17475 // CHECK19:       omp.loop.exit:
17476 // CHECK19-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
17477 // CHECK19-NEXT:    ret void
17478 //
17479 //
17480 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145
17481 // CHECK19-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] {
17482 // CHECK19-NEXT:  entry:
17483 // CHECK19-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
17484 // CHECK19-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
17485 // CHECK19-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
17486 // CHECK19-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 4
17487 // CHECK19-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
17488 // CHECK19-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
17489 // CHECK19-NEXT:    [[VLA_ADDR4:%.*]] = alloca i32, align 4
17490 // CHECK19-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 4
17491 // CHECK19-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
17492 // CHECK19-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
17493 // CHECK19-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
17494 // CHECK19-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
17495 // CHECK19-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
17496 // CHECK19-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
17497 // CHECK19-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
17498 // CHECK19-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 4
17499 // CHECK19-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
17500 // CHECK19-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
17501 // CHECK19-NEXT:    store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
17502 // CHECK19-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 4
17503 // CHECK19-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
17504 // CHECK19-NEXT:    store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
17505 // CHECK19-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
17506 // CHECK19-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
17507 // CHECK19-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
17508 // CHECK19-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
17509 // CHECK19-NEXT:    [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
17510 // CHECK19-NEXT:    [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
17511 // CHECK19-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
17512 // CHECK19-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
17513 // CHECK19-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
17514 // CHECK19-NEXT:    store i32 [[TMP8]], i32* [[A_CASTED]], align 4
17515 // CHECK19-NEXT:    [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4
17516 // CHECK19-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
17517 // CHECK19-NEXT:    store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
17518 // CHECK19-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
17519 // CHECK19-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*, i32)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i32 [[TMP11]])
17520 // CHECK19-NEXT:    ret void
17521 //
17522 //
17523 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..9
17524 // CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] {
17525 // CHECK19-NEXT:  entry:
17526 // CHECK19-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
17527 // CHECK19-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
17528 // CHECK19-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
17529 // CHECK19-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
17530 // CHECK19-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
17531 // CHECK19-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 4
17532 // CHECK19-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
17533 // CHECK19-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
17534 // CHECK19-NEXT:    [[VLA_ADDR4:%.*]] = alloca i32, align 4
17535 // CHECK19-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 4
17536 // CHECK19-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
17537 // CHECK19-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
17538 // CHECK19-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
17539 // CHECK19-NEXT:    [[TMP:%.*]] = alloca i32, align 4
17540 // CHECK19-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
17541 // CHECK19-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
17542 // CHECK19-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
17543 // CHECK19-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
17544 // CHECK19-NEXT:    [[I:%.*]] = alloca i32, align 4
17545 // CHECK19-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
17546 // CHECK19-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
17547 // CHECK19-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
17548 // CHECK19-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
17549 // CHECK19-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
17550 // CHECK19-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 4
17551 // CHECK19-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
17552 // CHECK19-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
17553 // CHECK19-NEXT:    store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
17554 // CHECK19-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 4
17555 // CHECK19-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
17556 // CHECK19-NEXT:    store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
17557 // CHECK19-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
17558 // CHECK19-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
17559 // CHECK19-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
17560 // CHECK19-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
17561 // CHECK19-NEXT:    [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
17562 // CHECK19-NEXT:    [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
17563 // CHECK19-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
17564 // CHECK19-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
17565 // CHECK19-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
17566 // CHECK19-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
17567 // CHECK19-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
17568 // CHECK19-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
17569 // CHECK19-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
17570 // CHECK19-NEXT:    [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
17571 // CHECK19-NEXT:    [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
17572 // CHECK19-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
17573 // CHECK19-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
17574 // CHECK19:       omp.dispatch.cond:
17575 // CHECK19-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
17576 // CHECK19-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 9
17577 // CHECK19-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
17578 // CHECK19:       cond.true:
17579 // CHECK19-NEXT:    br label [[COND_END:%.*]]
17580 // CHECK19:       cond.false:
17581 // CHECK19-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
17582 // CHECK19-NEXT:    br label [[COND_END]]
17583 // CHECK19:       cond.end:
17584 // CHECK19-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
17585 // CHECK19-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
17586 // CHECK19-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
17587 // CHECK19-NEXT:    store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
17588 // CHECK19-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
17589 // CHECK19-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
17590 // CHECK19-NEXT:    [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
17591 // CHECK19-NEXT:    br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
17592 // CHECK19:       omp.dispatch.body:
17593 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
17594 // CHECK19:       omp.inner.for.cond:
17595 // CHECK19-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
17596 // CHECK19-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !22
17597 // CHECK19-NEXT:    [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
17598 // CHECK19-NEXT:    br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
17599 // CHECK19:       omp.inner.for.body:
17600 // CHECK19-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
17601 // CHECK19-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
17602 // CHECK19-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
17603 // CHECK19-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !22
17604 // CHECK19-NEXT:    [[TMP19:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !22
17605 // CHECK19-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP19]], 1
17606 // CHECK19-NEXT:    store i32 [[ADD7]], i32* [[A_ADDR]], align 4, !llvm.access.group !22
17607 // CHECK19-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2
17608 // CHECK19-NEXT:    [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !22
17609 // CHECK19-NEXT:    [[CONV:%.*]] = fpext float [[TMP20]] to double
17610 // CHECK19-NEXT:    [[ADD8:%.*]] = fadd double [[CONV]], 1.000000e+00
17611 // CHECK19-NEXT:    [[CONV9:%.*]] = fptrunc double [[ADD8]] to float
17612 // CHECK19-NEXT:    store float [[CONV9]], float* [[ARRAYIDX]], align 4, !llvm.access.group !22
17613 // CHECK19-NEXT:    [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3
17614 // CHECK19-NEXT:    [[TMP21:%.*]] = load float, float* [[ARRAYIDX10]], align 4, !llvm.access.group !22
17615 // CHECK19-NEXT:    [[CONV11:%.*]] = fpext float [[TMP21]] to double
17616 // CHECK19-NEXT:    [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00
17617 // CHECK19-NEXT:    [[CONV13:%.*]] = fptrunc double [[ADD12]] to float
17618 // CHECK19-NEXT:    store float [[CONV13]], float* [[ARRAYIDX10]], align 4, !llvm.access.group !22
17619 // CHECK19-NEXT:    [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1
17620 // CHECK19-NEXT:    [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX14]], i32 0, i32 2
17621 // CHECK19-NEXT:    [[TMP22:%.*]] = load double, double* [[ARRAYIDX15]], align 8, !llvm.access.group !22
17622 // CHECK19-NEXT:    [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00
17623 // CHECK19-NEXT:    store double [[ADD16]], double* [[ARRAYIDX15]], align 8, !llvm.access.group !22
17624 // CHECK19-NEXT:    [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]]
17625 // CHECK19-NEXT:    [[ARRAYIDX17:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP23]]
17626 // CHECK19-NEXT:    [[ARRAYIDX18:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX17]], i32 3
17627 // CHECK19-NEXT:    [[TMP24:%.*]] = load double, double* [[ARRAYIDX18]], align 8, !llvm.access.group !22
17628 // CHECK19-NEXT:    [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00
17629 // CHECK19-NEXT:    store double [[ADD19]], double* [[ARRAYIDX18]], align 8, !llvm.access.group !22
17630 // CHECK19-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0
17631 // CHECK19-NEXT:    [[TMP25:%.*]] = load i64, i64* [[X]], align 4, !llvm.access.group !22
17632 // CHECK19-NEXT:    [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1
17633 // CHECK19-NEXT:    store i64 [[ADD20]], i64* [[X]], align 4, !llvm.access.group !22
17634 // CHECK19-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1
17635 // CHECK19-NEXT:    [[TMP26:%.*]] = load i8, i8* [[Y]], align 4, !llvm.access.group !22
17636 // CHECK19-NEXT:    [[CONV21:%.*]] = sext i8 [[TMP26]] to i32
17637 // CHECK19-NEXT:    [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1
17638 // CHECK19-NEXT:    [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8
17639 // CHECK19-NEXT:    store i8 [[CONV23]], i8* [[Y]], align 4, !llvm.access.group !22
17640 // CHECK19-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
17641 // CHECK19:       omp.body.continue:
17642 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
17643 // CHECK19:       omp.inner.for.inc:
17644 // CHECK19-NEXT:    [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
17645 // CHECK19-NEXT:    [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1
17646 // CHECK19-NEXT:    store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
17647 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]]
17648 // CHECK19:       omp.inner.for.end:
17649 // CHECK19-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
17650 // CHECK19:       omp.dispatch.inc:
17651 // CHECK19-NEXT:    [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
17652 // CHECK19-NEXT:    [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
17653 // CHECK19-NEXT:    [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]
17654 // CHECK19-NEXT:    store i32 [[ADD25]], i32* [[DOTOMP_LB]], align 4
17655 // CHECK19-NEXT:    [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
17656 // CHECK19-NEXT:    [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
17657 // CHECK19-NEXT:    [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]]
17658 // CHECK19-NEXT:    store i32 [[ADD26]], i32* [[DOTOMP_UB]], align 4
17659 // CHECK19-NEXT:    br label [[OMP_DISPATCH_COND]]
17660 // CHECK19:       omp.dispatch.end:
17661 // CHECK19-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]])
17662 // CHECK19-NEXT:    ret void
17663 //
17664 //
17665 // CHECK19-LABEL: define {{[^@]+}}@_Z3bari
17666 // CHECK19-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
17667 // CHECK19-NEXT:  entry:
17668 // CHECK19-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
17669 // CHECK19-NEXT:    [[A:%.*]] = alloca i32, align 4
17670 // CHECK19-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4
17671 // CHECK19-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
17672 // CHECK19-NEXT:    store i32 0, i32* [[A]], align 4
17673 // CHECK19-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
17674 // CHECK19-NEXT:    [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]])
17675 // CHECK19-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
17676 // CHECK19-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
17677 // CHECK19-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
17678 // CHECK19-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
17679 // CHECK19-NEXT:    [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]])
17680 // CHECK19-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
17681 // CHECK19-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
17682 // CHECK19-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
17683 // CHECK19-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
17684 // CHECK19-NEXT:    [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]])
17685 // CHECK19-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
17686 // CHECK19-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
17687 // CHECK19-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
17688 // CHECK19-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
17689 // CHECK19-NEXT:    [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]])
17690 // CHECK19-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
17691 // CHECK19-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
17692 // CHECK19-NEXT:    store i32 [[ADD6]], i32* [[A]], align 4
17693 // CHECK19-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
17694 // CHECK19-NEXT:    ret i32 [[TMP8]]
17695 //
17696 //
17697 // CHECK19-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
17698 // CHECK19-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 {
17699 // CHECK19-NEXT:  entry:
17700 // CHECK19-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
17701 // CHECK19-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
17702 // CHECK19-NEXT:    [[B:%.*]] = alloca i32, align 4
17703 // CHECK19-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 4
17704 // CHECK19-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 4
17705 // CHECK19-NEXT:    [[B_CASTED:%.*]] = alloca i32, align 4
17706 // CHECK19-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4
17707 // CHECK19-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4
17708 // CHECK19-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4
17709 // CHECK19-NEXT:    [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 4
17710 // CHECK19-NEXT:    [[TMP:%.*]] = alloca i32, align 4
17711 // CHECK19-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
17712 // CHECK19-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
17713 // CHECK19-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
17714 // CHECK19-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
17715 // CHECK19-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
17716 // CHECK19-NEXT:    store i32 [[ADD]], i32* [[B]], align 4
17717 // CHECK19-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
17718 // CHECK19-NEXT:    [[TMP2:%.*]] = call i8* @llvm.stacksave()
17719 // CHECK19-NEXT:    store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4
17720 // CHECK19-NEXT:    [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]
17721 // CHECK19-NEXT:    [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2
17722 // CHECK19-NEXT:    store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
17723 // CHECK19-NEXT:    [[TMP4:%.*]] = load i32, i32* [[B]], align 4
17724 // CHECK19-NEXT:    store i32 [[TMP4]], i32* [[B_CASTED]], align 4
17725 // CHECK19-NEXT:    [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4
17726 // CHECK19-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
17727 // CHECK19-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 60
17728 // CHECK19-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
17729 // CHECK19:       omp_if.then:
17730 // CHECK19-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
17731 // CHECK19-NEXT:    [[TMP7:%.*]] = mul nuw i32 2, [[TMP1]]
17732 // CHECK19-NEXT:    [[TMP8:%.*]] = mul nuw i32 [[TMP7]], 2
17733 // CHECK19-NEXT:    [[TMP9:%.*]] = sext i32 [[TMP8]] to i64
17734 // CHECK19-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
17735 // CHECK19-NEXT:    [[TMP11:%.*]] = bitcast i8** [[TMP10]] to %struct.S1**
17736 // CHECK19-NEXT:    store %struct.S1* [[THIS1]], %struct.S1** [[TMP11]], align 4
17737 // CHECK19-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
17738 // CHECK19-NEXT:    [[TMP13:%.*]] = bitcast i8** [[TMP12]] to double**
17739 // CHECK19-NEXT:    store double* [[A]], double** [[TMP13]], align 4
17740 // CHECK19-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
17741 // CHECK19-NEXT:    store i64 8, i64* [[TMP14]], align 4
17742 // CHECK19-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
17743 // CHECK19-NEXT:    store i8* null, i8** [[TMP15]], align 4
17744 // CHECK19-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
17745 // CHECK19-NEXT:    [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32*
17746 // CHECK19-NEXT:    store i32 [[TMP5]], i32* [[TMP17]], align 4
17747 // CHECK19-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
17748 // CHECK19-NEXT:    [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32*
17749 // CHECK19-NEXT:    store i32 [[TMP5]], i32* [[TMP19]], align 4
17750 // CHECK19-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1
17751 // CHECK19-NEXT:    store i64 4, i64* [[TMP20]], align 4
17752 // CHECK19-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
17753 // CHECK19-NEXT:    store i8* null, i8** [[TMP21]], align 4
17754 // CHECK19-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
17755 // CHECK19-NEXT:    [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i32*
17756 // CHECK19-NEXT:    store i32 2, i32* [[TMP23]], align 4
17757 // CHECK19-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
17758 // CHECK19-NEXT:    [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i32*
17759 // CHECK19-NEXT:    store i32 2, i32* [[TMP25]], align 4
17760 // CHECK19-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2
17761 // CHECK19-NEXT:    store i64 4, i64* [[TMP26]], align 4
17762 // CHECK19-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
17763 // CHECK19-NEXT:    store i8* null, i8** [[TMP27]], align 4
17764 // CHECK19-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
17765 // CHECK19-NEXT:    [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i32*
17766 // CHECK19-NEXT:    store i32 [[TMP1]], i32* [[TMP29]], align 4
17767 // CHECK19-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
17768 // CHECK19-NEXT:    [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i32*
17769 // CHECK19-NEXT:    store i32 [[TMP1]], i32* [[TMP31]], align 4
17770 // CHECK19-NEXT:    [[TMP32:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3
17771 // CHECK19-NEXT:    store i64 4, i64* [[TMP32]], align 4
17772 // CHECK19-NEXT:    [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
17773 // CHECK19-NEXT:    store i8* null, i8** [[TMP33]], align 4
17774 // CHECK19-NEXT:    [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
17775 // CHECK19-NEXT:    [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i16**
17776 // CHECK19-NEXT:    store i16* [[VLA]], i16** [[TMP35]], align 4
17777 // CHECK19-NEXT:    [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
17778 // CHECK19-NEXT:    [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i16**
17779 // CHECK19-NEXT:    store i16* [[VLA]], i16** [[TMP37]], align 4
17780 // CHECK19-NEXT:    [[TMP38:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4
17781 // CHECK19-NEXT:    store i64 [[TMP9]], i64* [[TMP38]], align 4
17782 // CHECK19-NEXT:    [[TMP39:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4
17783 // CHECK19-NEXT:    store i8* null, i8** [[TMP39]], align 4
17784 // CHECK19-NEXT:    [[TMP40:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
17785 // CHECK19-NEXT:    [[TMP41:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
17786 // CHECK19-NEXT:    [[TMP42:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
17787 // CHECK19-NEXT:    call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10)
17788 // CHECK19-NEXT:    [[TMP43:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218.region_id, i32 5, i8** [[TMP40]], i8** [[TMP41]], i64* [[TMP42]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.12, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
17789 // CHECK19-NEXT:    [[TMP44:%.*]] = icmp ne i32 [[TMP43]], 0
17790 // CHECK19-NEXT:    br i1 [[TMP44]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
17791 // CHECK19:       omp_offload.failed:
17792 // CHECK19-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR3]]
17793 // CHECK19-NEXT:    br label [[OMP_OFFLOAD_CONT]]
17794 // CHECK19:       omp_offload.cont:
17795 // CHECK19-NEXT:    br label [[OMP_IF_END:%.*]]
17796 // CHECK19:       omp_if.else:
17797 // CHECK19-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR3]]
17798 // CHECK19-NEXT:    br label [[OMP_IF_END]]
17799 // CHECK19:       omp_if.end:
17800 // CHECK19-NEXT:    [[TMP45:%.*]] = mul nsw i32 1, [[TMP1]]
17801 // CHECK19-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP45]]
17802 // CHECK19-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
17803 // CHECK19-NEXT:    [[TMP46:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2
17804 // CHECK19-NEXT:    [[CONV:%.*]] = sext i16 [[TMP46]] to i32
17805 // CHECK19-NEXT:    [[TMP47:%.*]] = load i32, i32* [[B]], align 4
17806 // CHECK19-NEXT:    [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP47]]
17807 // CHECK19-NEXT:    [[TMP48:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
17808 // CHECK19-NEXT:    call void @llvm.stackrestore(i8* [[TMP48]])
17809 // CHECK19-NEXT:    ret i32 [[ADD3]]
17810 //
17811 //
17812 // CHECK19-LABEL: define {{[^@]+}}@_ZL7fstatici
17813 // CHECK19-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
17814 // CHECK19-NEXT:  entry:
17815 // CHECK19-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
17816 // CHECK19-NEXT:    [[A:%.*]] = alloca i32, align 4
17817 // CHECK19-NEXT:    [[AA:%.*]] = alloca i16, align 2
17818 // CHECK19-NEXT:    [[AAA:%.*]] = alloca i8, align 1
17819 // CHECK19-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
17820 // CHECK19-NEXT:    [[N_CASTED:%.*]] = alloca i32, align 4
17821 // CHECK19-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
17822 // CHECK19-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
17823 // CHECK19-NEXT:    [[AAA_CASTED:%.*]] = alloca i32, align 4
17824 // CHECK19-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4
17825 // CHECK19-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4
17826 // CHECK19-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4
17827 // CHECK19-NEXT:    [[TMP:%.*]] = alloca i32, align 4
17828 // CHECK19-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
17829 // CHECK19-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
17830 // CHECK19-NEXT:    [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4
17831 // CHECK19-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
17832 // CHECK19-NEXT:    store i32 0, i32* [[A]], align 4
17833 // CHECK19-NEXT:    store i16 0, i16* [[AA]], align 2
17834 // CHECK19-NEXT:    store i8 0, i8* [[AAA]], align 1
17835 // CHECK19-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
17836 // CHECK19-NEXT:    store i32 [[TMP0]], i32* [[N_CASTED]], align 4
17837 // CHECK19-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_CASTED]], align 4
17838 // CHECK19-NEXT:    [[TMP2:%.*]] = load i32, i32* [[A]], align 4
17839 // CHECK19-NEXT:    store i32 [[TMP2]], i32* [[A_CASTED]], align 4
17840 // CHECK19-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A_CASTED]], align 4
17841 // CHECK19-NEXT:    [[TMP4:%.*]] = load i16, i16* [[AA]], align 2
17842 // CHECK19-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
17843 // CHECK19-NEXT:    store i16 [[TMP4]], i16* [[CONV]], align 2
17844 // CHECK19-NEXT:    [[TMP5:%.*]] = load i32, i32* [[AA_CASTED]], align 4
17845 // CHECK19-NEXT:    [[TMP6:%.*]] = load i8, i8* [[AAA]], align 1
17846 // CHECK19-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
17847 // CHECK19-NEXT:    store i8 [[TMP6]], i8* [[CONV1]], align 1
17848 // CHECK19-NEXT:    [[TMP7:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
17849 // CHECK19-NEXT:    [[TMP8:%.*]] = load i32, i32* [[N_ADDR]], align 4
17850 // CHECK19-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP8]], 50
17851 // CHECK19-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
17852 // CHECK19:       omp_if.then:
17853 // CHECK19-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
17854 // CHECK19-NEXT:    [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32*
17855 // CHECK19-NEXT:    store i32 [[TMP1]], i32* [[TMP10]], align 4
17856 // CHECK19-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
17857 // CHECK19-NEXT:    [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32*
17858 // CHECK19-NEXT:    store i32 [[TMP1]], i32* [[TMP12]], align 4
17859 // CHECK19-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
17860 // CHECK19-NEXT:    store i8* null, i8** [[TMP13]], align 4
17861 // CHECK19-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
17862 // CHECK19-NEXT:    [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32*
17863 // CHECK19-NEXT:    store i32 [[TMP3]], i32* [[TMP15]], align 4
17864 // CHECK19-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
17865 // CHECK19-NEXT:    [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32*
17866 // CHECK19-NEXT:    store i32 [[TMP3]], i32* [[TMP17]], align 4
17867 // CHECK19-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
17868 // CHECK19-NEXT:    store i8* null, i8** [[TMP18]], align 4
17869 // CHECK19-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
17870 // CHECK19-NEXT:    [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32*
17871 // CHECK19-NEXT:    store i32 [[TMP5]], i32* [[TMP20]], align 4
17872 // CHECK19-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
17873 // CHECK19-NEXT:    [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i32*
17874 // CHECK19-NEXT:    store i32 [[TMP5]], i32* [[TMP22]], align 4
17875 // CHECK19-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
17876 // CHECK19-NEXT:    store i8* null, i8** [[TMP23]], align 4
17877 // CHECK19-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
17878 // CHECK19-NEXT:    [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i32*
17879 // CHECK19-NEXT:    store i32 [[TMP7]], i32* [[TMP25]], align 4
17880 // CHECK19-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
17881 // CHECK19-NEXT:    [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i32*
17882 // CHECK19-NEXT:    store i32 [[TMP7]], i32* [[TMP27]], align 4
17883 // CHECK19-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
17884 // CHECK19-NEXT:    store i8* null, i8** [[TMP28]], align 4
17885 // CHECK19-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
17886 // CHECK19-NEXT:    [[TMP30:%.*]] = bitcast i8** [[TMP29]] to [10 x i32]**
17887 // CHECK19-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP30]], align 4
17888 // CHECK19-NEXT:    [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
17889 // CHECK19-NEXT:    [[TMP32:%.*]] = bitcast i8** [[TMP31]] to [10 x i32]**
17890 // CHECK19-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP32]], align 4
17891 // CHECK19-NEXT:    [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4
17892 // CHECK19-NEXT:    store i8* null, i8** [[TMP33]], align 4
17893 // CHECK19-NEXT:    [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
17894 // CHECK19-NEXT:    [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
17895 // CHECK19-NEXT:    [[TMP36:%.*]] = load i32, i32* [[A]], align 4
17896 // CHECK19-NEXT:    store i32 [[TMP36]], i32* [[DOTCAPTURE_EXPR_]], align 4
17897 // CHECK19-NEXT:    [[TMP37:%.*]] = load i32, i32* [[N_ADDR]], align 4
17898 // CHECK19-NEXT:    store i32 [[TMP37]], i32* [[DOTCAPTURE_EXPR_2]], align 4
17899 // CHECK19-NEXT:    [[TMP38:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
17900 // CHECK19-NEXT:    [[TMP39:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
17901 // CHECK19-NEXT:    [[SUB:%.*]] = sub i32 [[TMP38]], [[TMP39]]
17902 // CHECK19-NEXT:    [[SUB4:%.*]] = sub i32 [[SUB]], 1
17903 // CHECK19-NEXT:    [[ADD:%.*]] = add i32 [[SUB4]], 1
17904 // CHECK19-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], 1
17905 // CHECK19-NEXT:    [[SUB5:%.*]] = sub i32 [[DIV]], 1
17906 // CHECK19-NEXT:    store i32 [[SUB5]], i32* [[DOTCAPTURE_EXPR_3]], align 4
17907 // CHECK19-NEXT:    [[TMP40:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
17908 // CHECK19-NEXT:    [[ADD6:%.*]] = add i32 [[TMP40]], 1
17909 // CHECK19-NEXT:    [[TMP41:%.*]] = zext i32 [[ADD6]] to i64
17910 // CHECK19-NEXT:    call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 [[TMP41]])
17911 // CHECK19-NEXT:    [[TMP42:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200.region_id, i32 5, i8** [[TMP34]], i8** [[TMP35]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes.14, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.15, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
17912 // CHECK19-NEXT:    [[TMP43:%.*]] = icmp ne i32 [[TMP42]], 0
17913 // CHECK19-NEXT:    br i1 [[TMP43]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
17914 // CHECK19:       omp_offload.failed:
17915 // CHECK19-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], i32 [[TMP7]], [10 x i32]* [[B]]) #[[ATTR3]]
17916 // CHECK19-NEXT:    br label [[OMP_OFFLOAD_CONT]]
17917 // CHECK19:       omp_offload.cont:
17918 // CHECK19-NEXT:    br label [[OMP_IF_END:%.*]]
17919 // CHECK19:       omp_if.else:
17920 // CHECK19-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], i32 [[TMP7]], [10 x i32]* [[B]]) #[[ATTR3]]
17921 // CHECK19-NEXT:    br label [[OMP_IF_END]]
17922 // CHECK19:       omp_if.end:
17923 // CHECK19-NEXT:    [[TMP44:%.*]] = load i32, i32* [[A]], align 4
17924 // CHECK19-NEXT:    ret i32 [[TMP44]]
17925 //
17926 //
17927 // CHECK19-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
17928 // CHECK19-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat {
17929 // CHECK19-NEXT:  entry:
17930 // CHECK19-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
17931 // CHECK19-NEXT:    [[A:%.*]] = alloca i32, align 4
17932 // CHECK19-NEXT:    [[AA:%.*]] = alloca i16, align 2
17933 // CHECK19-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
17934 // CHECK19-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
17935 // CHECK19-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
17936 // CHECK19-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4
17937 // CHECK19-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4
17938 // CHECK19-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4
17939 // CHECK19-NEXT:    [[TMP:%.*]] = alloca i32, align 4
17940 // CHECK19-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
17941 // CHECK19-NEXT:    store i32 0, i32* [[A]], align 4
17942 // CHECK19-NEXT:    store i16 0, i16* [[AA]], align 2
17943 // CHECK19-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
17944 // CHECK19-NEXT:    store i32 [[TMP0]], i32* [[A_CASTED]], align 4
17945 // CHECK19-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
17946 // CHECK19-NEXT:    [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
17947 // CHECK19-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
17948 // CHECK19-NEXT:    store i16 [[TMP2]], i16* [[CONV]], align 2
17949 // CHECK19-NEXT:    [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
17950 // CHECK19-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
17951 // CHECK19-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40
17952 // CHECK19-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
17953 // CHECK19:       omp_if.then:
17954 // CHECK19-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
17955 // CHECK19-NEXT:    [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i32*
17956 // CHECK19-NEXT:    store i32 [[TMP1]], i32* [[TMP6]], align 4
17957 // CHECK19-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
17958 // CHECK19-NEXT:    [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32*
17959 // CHECK19-NEXT:    store i32 [[TMP1]], i32* [[TMP8]], align 4
17960 // CHECK19-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
17961 // CHECK19-NEXT:    store i8* null, i8** [[TMP9]], align 4
17962 // CHECK19-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
17963 // CHECK19-NEXT:    [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i32*
17964 // CHECK19-NEXT:    store i32 [[TMP3]], i32* [[TMP11]], align 4
17965 // CHECK19-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
17966 // CHECK19-NEXT:    [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32*
17967 // CHECK19-NEXT:    store i32 [[TMP3]], i32* [[TMP13]], align 4
17968 // CHECK19-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
17969 // CHECK19-NEXT:    store i8* null, i8** [[TMP14]], align 4
17970 // CHECK19-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
17971 // CHECK19-NEXT:    [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]**
17972 // CHECK19-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 4
17973 // CHECK19-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
17974 // CHECK19-NEXT:    [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]**
17975 // CHECK19-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 4
17976 // CHECK19-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
17977 // CHECK19-NEXT:    store i8* null, i8** [[TMP19]], align 4
17978 // CHECK19-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
17979 // CHECK19-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
17980 // CHECK19-NEXT:    call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10)
17981 // CHECK19-NEXT:    [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.17, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.18, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
17982 // CHECK19-NEXT:    [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0
17983 // CHECK19-NEXT:    br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
17984 // CHECK19:       omp_offload.failed:
17985 // CHECK19-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]]
17986 // CHECK19-NEXT:    br label [[OMP_OFFLOAD_CONT]]
17987 // CHECK19:       omp_offload.cont:
17988 // CHECK19-NEXT:    br label [[OMP_IF_END:%.*]]
17989 // CHECK19:       omp_if.else:
17990 // CHECK19-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]]
17991 // CHECK19-NEXT:    br label [[OMP_IF_END]]
17992 // CHECK19:       omp_if.end:
17993 // CHECK19-NEXT:    [[TMP24:%.*]] = load i32, i32* [[A]], align 4
17994 // CHECK19-NEXT:    ret i32 [[TMP24]]
17995 //
17996 //
17997 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218
17998 // CHECK19-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {
17999 // CHECK19-NEXT:  entry:
18000 // CHECK19-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
18001 // CHECK19-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
18002 // CHECK19-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
18003 // CHECK19-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
18004 // CHECK19-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 4
18005 // CHECK19-NEXT:    [[B_CASTED:%.*]] = alloca i32, align 4
18006 // CHECK19-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
18007 // CHECK19-NEXT:    store i32 [[B]], i32* [[B_ADDR]], align 4
18008 // CHECK19-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
18009 // CHECK19-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
18010 // CHECK19-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 4
18011 // CHECK19-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
18012 // CHECK19-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
18013 // CHECK19-NEXT:    [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
18014 // CHECK19-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
18015 // CHECK19-NEXT:    [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4
18016 // CHECK19-NEXT:    store i32 [[TMP4]], i32* [[B_CASTED]], align 4
18017 // CHECK19-NEXT:    [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4
18018 // CHECK19-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]])
18019 // CHECK19-NEXT:    ret void
18020 //
18021 //
18022 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..11
18023 // CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {
18024 // CHECK19-NEXT:  entry:
18025 // CHECK19-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
18026 // CHECK19-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
18027 // CHECK19-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
18028 // CHECK19-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
18029 // CHECK19-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
18030 // CHECK19-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
18031 // CHECK19-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 4
18032 // CHECK19-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
18033 // CHECK19-NEXT:    [[TMP:%.*]] = alloca i32, align 4
18034 // CHECK19-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
18035 // CHECK19-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
18036 // CHECK19-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
18037 // CHECK19-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
18038 // CHECK19-NEXT:    [[I:%.*]] = alloca i32, align 4
18039 // CHECK19-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
18040 // CHECK19-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
18041 // CHECK19-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
18042 // CHECK19-NEXT:    store i32 [[B]], i32* [[B_ADDR]], align 4
18043 // CHECK19-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
18044 // CHECK19-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
18045 // CHECK19-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 4
18046 // CHECK19-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
18047 // CHECK19-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
18048 // CHECK19-NEXT:    [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
18049 // CHECK19-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
18050 // CHECK19-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
18051 // CHECK19-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
18052 // CHECK19-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
18053 // CHECK19-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
18054 // CHECK19-NEXT:    [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
18055 // CHECK19-NEXT:    [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
18056 // CHECK19-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
18057 // CHECK19-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
18058 // CHECK19-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 9
18059 // CHECK19-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
18060 // CHECK19:       cond.true:
18061 // CHECK19-NEXT:    br label [[COND_END:%.*]]
18062 // CHECK19:       cond.false:
18063 // CHECK19-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
18064 // CHECK19-NEXT:    br label [[COND_END]]
18065 // CHECK19:       cond.end:
18066 // CHECK19-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
18067 // CHECK19-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
18068 // CHECK19-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
18069 // CHECK19-NEXT:    store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
18070 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
18071 // CHECK19:       omp.inner.for.cond:
18072 // CHECK19-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
18073 // CHECK19-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
18074 // CHECK19-NEXT:    [[CMP3:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
18075 // CHECK19-NEXT:    br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
18076 // CHECK19:       omp.inner.for.body:
18077 // CHECK19-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
18078 // CHECK19-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
18079 // CHECK19-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
18080 // CHECK19-NEXT:    store i32 [[ADD]], i32* [[I]], align 4
18081 // CHECK19-NEXT:    [[TMP12:%.*]] = load i32, i32* [[B_ADDR]], align 4
18082 // CHECK19-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP12]] to double
18083 // CHECK19-NEXT:    [[ADD4:%.*]] = fadd double [[CONV]], 1.500000e+00
18084 // CHECK19-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
18085 // CHECK19-NEXT:    store double [[ADD4]], double* [[A]], align 4
18086 // CHECK19-NEXT:    [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
18087 // CHECK19-NEXT:    [[TMP13:%.*]] = load double, double* [[A5]], align 4
18088 // CHECK19-NEXT:    [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00
18089 // CHECK19-NEXT:    store double [[INC]], double* [[A5]], align 4
18090 // CHECK19-NEXT:    [[CONV6:%.*]] = fptosi double [[INC]] to i16
18091 // CHECK19-NEXT:    [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]]
18092 // CHECK19-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP14]]
18093 // CHECK19-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
18094 // CHECK19-NEXT:    store i16 [[CONV6]], i16* [[ARRAYIDX7]], align 2
18095 // CHECK19-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
18096 // CHECK19:       omp.body.continue:
18097 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
18098 // CHECK19:       omp.inner.for.inc:
18099 // CHECK19-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
18100 // CHECK19-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP15]], 1
18101 // CHECK19-NEXT:    store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4
18102 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_COND]]
18103 // CHECK19:       omp.inner.for.end:
18104 // CHECK19-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
18105 // CHECK19:       omp.loop.exit:
18106 // CHECK19-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
18107 // CHECK19-NEXT:    ret void
18108 //
18109 //
18110 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200
18111 // CHECK19-SAME: (i32 [[N:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
18112 // CHECK19-NEXT:  entry:
18113 // CHECK19-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
18114 // CHECK19-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
18115 // CHECK19-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
18116 // CHECK19-NEXT:    [[AAA_ADDR:%.*]] = alloca i32, align 4
18117 // CHECK19-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
18118 // CHECK19-NEXT:    [[N_CASTED:%.*]] = alloca i32, align 4
18119 // CHECK19-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
18120 // CHECK19-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
18121 // CHECK19-NEXT:    [[AAA_CASTED:%.*]] = alloca i32, align 4
18122 // CHECK19-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
18123 // CHECK19-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
18124 // CHECK19-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
18125 // CHECK19-NEXT:    store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
18126 // CHECK19-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
18127 // CHECK19-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
18128 // CHECK19-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
18129 // CHECK19-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
18130 // CHECK19-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
18131 // CHECK19-NEXT:    store i32 [[TMP1]], i32* [[N_CASTED]], align 4
18132 // CHECK19-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_CASTED]], align 4
18133 // CHECK19-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4
18134 // CHECK19-NEXT:    store i32 [[TMP3]], i32* [[A_CASTED]], align 4
18135 // CHECK19-NEXT:    [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4
18136 // CHECK19-NEXT:    [[TMP5:%.*]] = load i16, i16* [[CONV]], align 4
18137 // CHECK19-NEXT:    [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
18138 // CHECK19-NEXT:    store i16 [[TMP5]], i16* [[CONV2]], align 2
18139 // CHECK19-NEXT:    [[TMP6:%.*]] = load i32, i32* [[AA_CASTED]], align 4
18140 // CHECK19-NEXT:    [[TMP7:%.*]] = load i8, i8* [[CONV1]], align 4
18141 // CHECK19-NEXT:    [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
18142 // CHECK19-NEXT:    store i8 [[TMP7]], i8* [[CONV3]], align 1
18143 // CHECK19-NEXT:    [[TMP8:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
18144 // CHECK19-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, [10 x i32]*)* @.omp_outlined..13 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP8]], [10 x i32]* [[TMP0]])
18145 // CHECK19-NEXT:    ret void
18146 //
18147 //
18148 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..13
18149 // CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
18150 // CHECK19-NEXT:  entry:
18151 // CHECK19-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
18152 // CHECK19-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
18153 // CHECK19-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
18154 // CHECK19-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
18155 // CHECK19-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
18156 // CHECK19-NEXT:    [[AAA_ADDR:%.*]] = alloca i32, align 4
18157 // CHECK19-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
18158 // CHECK19-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
18159 // CHECK19-NEXT:    [[TMP:%.*]] = alloca i32, align 4
18160 // CHECK19-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
18161 // CHECK19-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
18162 // CHECK19-NEXT:    [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4
18163 // CHECK19-NEXT:    [[I:%.*]] = alloca i32, align 4
18164 // CHECK19-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
18165 // CHECK19-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
18166 // CHECK19-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
18167 // CHECK19-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
18168 // CHECK19-NEXT:    [[I6:%.*]] = alloca i32, align 4
18169 // CHECK19-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
18170 // CHECK19-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
18171 // CHECK19-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
18172 // CHECK19-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
18173 // CHECK19-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
18174 // CHECK19-NEXT:    store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
18175 // CHECK19-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
18176 // CHECK19-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
18177 // CHECK19-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
18178 // CHECK19-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
18179 // CHECK19-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
18180 // CHECK19-NEXT:    store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
18181 // CHECK19-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
18182 // CHECK19-NEXT:    store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4
18183 // CHECK19-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
18184 // CHECK19-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
18185 // CHECK19-NEXT:    [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]]
18186 // CHECK19-NEXT:    [[SUB4:%.*]] = sub i32 [[SUB]], 1
18187 // CHECK19-NEXT:    [[ADD:%.*]] = add i32 [[SUB4]], 1
18188 // CHECK19-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], 1
18189 // CHECK19-NEXT:    [[SUB5:%.*]] = sub i32 [[DIV]], 1
18190 // CHECK19-NEXT:    store i32 [[SUB5]], i32* [[DOTCAPTURE_EXPR_3]], align 4
18191 // CHECK19-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
18192 // CHECK19-NEXT:    store i32 [[TMP5]], i32* [[I]], align 4
18193 // CHECK19-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
18194 // CHECK19-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
18195 // CHECK19-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]]
18196 // CHECK19-NEXT:    br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
18197 // CHECK19:       omp.precond.then:
18198 // CHECK19-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
18199 // CHECK19-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
18200 // CHECK19-NEXT:    store i32 [[TMP8]], i32* [[DOTOMP_UB]], align 4
18201 // CHECK19-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
18202 // CHECK19-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
18203 // CHECK19-NEXT:    [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
18204 // CHECK19-NEXT:    [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
18205 // CHECK19-NEXT:    call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
18206 // CHECK19-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
18207 // CHECK19-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
18208 // CHECK19-NEXT:    [[CMP7:%.*]] = icmp ugt i32 [[TMP11]], [[TMP12]]
18209 // CHECK19-NEXT:    br i1 [[CMP7]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
18210 // CHECK19:       cond.true:
18211 // CHECK19-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
18212 // CHECK19-NEXT:    br label [[COND_END:%.*]]
18213 // CHECK19:       cond.false:
18214 // CHECK19-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
18215 // CHECK19-NEXT:    br label [[COND_END]]
18216 // CHECK19:       cond.end:
18217 // CHECK19-NEXT:    [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ]
18218 // CHECK19-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
18219 // CHECK19-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
18220 // CHECK19-NEXT:    store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4
18221 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
18222 // CHECK19:       omp.inner.for.cond:
18223 // CHECK19-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
18224 // CHECK19-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
18225 // CHECK19-NEXT:    [[ADD8:%.*]] = add i32 [[TMP17]], 1
18226 // CHECK19-NEXT:    [[CMP9:%.*]] = icmp ult i32 [[TMP16]], [[ADD8]]
18227 // CHECK19-NEXT:    br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
18228 // CHECK19:       omp.inner.for.body:
18229 // CHECK19-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
18230 // CHECK19-NEXT:    [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
18231 // CHECK19-NEXT:    [[MUL:%.*]] = mul i32 [[TMP19]], 1
18232 // CHECK19-NEXT:    [[ADD10:%.*]] = add i32 [[TMP18]], [[MUL]]
18233 // CHECK19-NEXT:    store i32 [[ADD10]], i32* [[I6]], align 4
18234 // CHECK19-NEXT:    [[TMP20:%.*]] = load i32, i32* [[A_ADDR]], align 4
18235 // CHECK19-NEXT:    [[ADD11:%.*]] = add nsw i32 [[TMP20]], 1
18236 // CHECK19-NEXT:    store i32 [[ADD11]], i32* [[A_ADDR]], align 4
18237 // CHECK19-NEXT:    [[TMP21:%.*]] = load i16, i16* [[CONV]], align 4
18238 // CHECK19-NEXT:    [[CONV12:%.*]] = sext i16 [[TMP21]] to i32
18239 // CHECK19-NEXT:    [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1
18240 // CHECK19-NEXT:    [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16
18241 // CHECK19-NEXT:    store i16 [[CONV14]], i16* [[CONV]], align 4
18242 // CHECK19-NEXT:    [[TMP22:%.*]] = load i8, i8* [[CONV1]], align 4
18243 // CHECK19-NEXT:    [[CONV15:%.*]] = sext i8 [[TMP22]] to i32
18244 // CHECK19-NEXT:    [[ADD16:%.*]] = add nsw i32 [[CONV15]], 1
18245 // CHECK19-NEXT:    [[CONV17:%.*]] = trunc i32 [[ADD16]] to i8
18246 // CHECK19-NEXT:    store i8 [[CONV17]], i8* [[CONV1]], align 4
18247 // CHECK19-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
18248 // CHECK19-NEXT:    [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
18249 // CHECK19-NEXT:    [[ADD18:%.*]] = add nsw i32 [[TMP23]], 1
18250 // CHECK19-NEXT:    store i32 [[ADD18]], i32* [[ARRAYIDX]], align 4
18251 // CHECK19-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
18252 // CHECK19:       omp.body.continue:
18253 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
18254 // CHECK19:       omp.inner.for.inc:
18255 // CHECK19-NEXT:    [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
18256 // CHECK19-NEXT:    [[ADD19:%.*]] = add i32 [[TMP24]], 1
18257 // CHECK19-NEXT:    store i32 [[ADD19]], i32* [[DOTOMP_IV]], align 4
18258 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_COND]]
18259 // CHECK19:       omp.inner.for.end:
18260 // CHECK19-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
18261 // CHECK19:       omp.loop.exit:
18262 // CHECK19-NEXT:    [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
18263 // CHECK19-NEXT:    [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4
18264 // CHECK19-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]])
18265 // CHECK19-NEXT:    br label [[OMP_PRECOND_END]]
18266 // CHECK19:       omp.precond.end:
18267 // CHECK19-NEXT:    ret void
18268 //
18269 //
18270 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183
18271 // CHECK19-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
18272 // CHECK19-NEXT:  entry:
18273 // CHECK19-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
18274 // CHECK19-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
18275 // CHECK19-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
18276 // CHECK19-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
18277 // CHECK19-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
18278 // CHECK19-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
18279 // CHECK19-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
18280 // CHECK19-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
18281 // CHECK19-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
18282 // CHECK19-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
18283 // CHECK19-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
18284 // CHECK19-NEXT:    store i32 [[TMP1]], i32* [[A_CASTED]], align 4
18285 // CHECK19-NEXT:    [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
18286 // CHECK19-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
18287 // CHECK19-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
18288 // CHECK19-NEXT:    store i16 [[TMP3]], i16* [[CONV1]], align 2
18289 // CHECK19-NEXT:    [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
18290 // CHECK19-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]])
18291 // CHECK19-NEXT:    ret void
18292 //
18293 //
18294 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..16
18295 // CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
18296 // CHECK19-NEXT:  entry:
18297 // CHECK19-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
18298 // CHECK19-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
18299 // CHECK19-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
18300 // CHECK19-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
18301 // CHECK19-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
18302 // CHECK19-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
18303 // CHECK19-NEXT:    [[TMP:%.*]] = alloca i32, align 4
18304 // CHECK19-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
18305 // CHECK19-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
18306 // CHECK19-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
18307 // CHECK19-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
18308 // CHECK19-NEXT:    [[I:%.*]] = alloca i32, align 4
18309 // CHECK19-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
18310 // CHECK19-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
18311 // CHECK19-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
18312 // CHECK19-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
18313 // CHECK19-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
18314 // CHECK19-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
18315 // CHECK19-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
18316 // CHECK19-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
18317 // CHECK19-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
18318 // CHECK19-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
18319 // CHECK19-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
18320 // CHECK19-NEXT:    [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
18321 // CHECK19-NEXT:    [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
18322 // CHECK19-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
18323 // CHECK19-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
18324 // CHECK19-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9
18325 // CHECK19-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
18326 // CHECK19:       cond.true:
18327 // CHECK19-NEXT:    br label [[COND_END:%.*]]
18328 // CHECK19:       cond.false:
18329 // CHECK19-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
18330 // CHECK19-NEXT:    br label [[COND_END]]
18331 // CHECK19:       cond.end:
18332 // CHECK19-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
18333 // CHECK19-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
18334 // CHECK19-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
18335 // CHECK19-NEXT:    store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
18336 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
18337 // CHECK19:       omp.inner.for.cond:
18338 // CHECK19-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
18339 // CHECK19-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
18340 // CHECK19-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
18341 // CHECK19-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
18342 // CHECK19:       omp.inner.for.body:
18343 // CHECK19-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
18344 // CHECK19-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
18345 // CHECK19-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
18346 // CHECK19-NEXT:    store i32 [[ADD]], i32* [[I]], align 4
18347 // CHECK19-NEXT:    [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4
18348 // CHECK19-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
18349 // CHECK19-NEXT:    store i32 [[ADD2]], i32* [[A_ADDR]], align 4
18350 // CHECK19-NEXT:    [[TMP10:%.*]] = load i16, i16* [[CONV]], align 4
18351 // CHECK19-NEXT:    [[CONV3:%.*]] = sext i16 [[TMP10]] to i32
18352 // CHECK19-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
18353 // CHECK19-NEXT:    [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
18354 // CHECK19-NEXT:    store i16 [[CONV5]], i16* [[CONV]], align 4
18355 // CHECK19-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
18356 // CHECK19-NEXT:    [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
18357 // CHECK19-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1
18358 // CHECK19-NEXT:    store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4
18359 // CHECK19-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
18360 // CHECK19:       omp.body.continue:
18361 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
18362 // CHECK19:       omp.inner.for.inc:
18363 // CHECK19-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
18364 // CHECK19-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP12]], 1
18365 // CHECK19-NEXT:    store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4
18366 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_COND]]
18367 // CHECK19:       omp.inner.for.end:
18368 // CHECK19-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
18369 // CHECK19:       omp.loop.exit:
18370 // CHECK19-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
18371 // CHECK19-NEXT:    ret void
18372 //
18373 //
18374 // CHECK19-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
18375 // CHECK19-SAME: () #[[ATTR4]] {
18376 // CHECK19-NEXT:  entry:
18377 // CHECK19-NEXT:    call void @__tgt_register_requires(i64 1)
18378 // CHECK19-NEXT:    ret void
18379 //
18380 //
18381 // CHECK20-LABEL: define {{[^@]+}}@_Z3fooi
18382 // CHECK20-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] {
18383 // CHECK20-NEXT:  entry:
18384 // CHECK20-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
18385 // CHECK20-NEXT:    [[A:%.*]] = alloca i32, align 4
18386 // CHECK20-NEXT:    [[AA:%.*]] = alloca i16, align 2
18387 // CHECK20-NEXT:    [[B:%.*]] = alloca [10 x float], align 4
18388 // CHECK20-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 4
18389 // CHECK20-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 4
18390 // CHECK20-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 8
18391 // CHECK20-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i32, align 4
18392 // CHECK20-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4
18393 // CHECK20-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
18394 // CHECK20-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
18395 // CHECK20-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
18396 // CHECK20-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
18397 // CHECK20-NEXT:    [[DOTCAPTURE_EXPR__CASTED3:%.*]] = alloca i32, align 4
18398 // CHECK20-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4
18399 // CHECK20-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4
18400 // CHECK20-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4
18401 // CHECK20-NEXT:    [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4
18402 // CHECK20-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
18403 // CHECK20-NEXT:    [[AA_CASTED4:%.*]] = alloca i32, align 4
18404 // CHECK20-NEXT:    [[DOTOFFLOAD_BASEPTRS6:%.*]] = alloca [1 x i8*], align 4
18405 // CHECK20-NEXT:    [[DOTOFFLOAD_PTRS7:%.*]] = alloca [1 x i8*], align 4
18406 // CHECK20-NEXT:    [[DOTOFFLOAD_MAPPERS8:%.*]] = alloca [1 x i8*], align 4
18407 // CHECK20-NEXT:    [[TMP:%.*]] = alloca i32, align 4
18408 // CHECK20-NEXT:    [[A_CASTED9:%.*]] = alloca i32, align 4
18409 // CHECK20-NEXT:    [[AA_CASTED10:%.*]] = alloca i32, align 4
18410 // CHECK20-NEXT:    [[DOTOFFLOAD_BASEPTRS12:%.*]] = alloca [2 x i8*], align 4
18411 // CHECK20-NEXT:    [[DOTOFFLOAD_PTRS13:%.*]] = alloca [2 x i8*], align 4
18412 // CHECK20-NEXT:    [[DOTOFFLOAD_MAPPERS14:%.*]] = alloca [2 x i8*], align 4
18413 // CHECK20-NEXT:    [[_TMP15:%.*]] = alloca i32, align 4
18414 // CHECK20-NEXT:    [[DOTCAPTURE_EXPR_18:%.*]] = alloca i32, align 4
18415 // CHECK20-NEXT:    [[A_CASTED19:%.*]] = alloca i32, align 4
18416 // CHECK20-NEXT:    [[DOTCAPTURE_EXPR__CASTED20:%.*]] = alloca i32, align 4
18417 // CHECK20-NEXT:    [[DOTOFFLOAD_BASEPTRS23:%.*]] = alloca [10 x i8*], align 4
18418 // CHECK20-NEXT:    [[DOTOFFLOAD_PTRS24:%.*]] = alloca [10 x i8*], align 4
18419 // CHECK20-NEXT:    [[DOTOFFLOAD_MAPPERS25:%.*]] = alloca [10 x i8*], align 4
18420 // CHECK20-NEXT:    [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 4
18421 // CHECK20-NEXT:    [[_TMP26:%.*]] = alloca i32, align 4
18422 // CHECK20-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]])
18423 // CHECK20-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
18424 // CHECK20-NEXT:    store i32 0, i32* [[A]], align 4
18425 // CHECK20-NEXT:    store i16 0, i16* [[AA]], align 2
18426 // CHECK20-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
18427 // CHECK20-NEXT:    [[TMP2:%.*]] = call i8* @llvm.stacksave()
18428 // CHECK20-NEXT:    store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4
18429 // CHECK20-NEXT:    [[VLA:%.*]] = alloca float, i32 [[TMP1]], align 4
18430 // CHECK20-NEXT:    store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
18431 // CHECK20-NEXT:    [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
18432 // CHECK20-NEXT:    [[TMP4:%.*]] = mul nuw i32 5, [[TMP3]]
18433 // CHECK20-NEXT:    [[VLA1:%.*]] = alloca double, i32 [[TMP4]], align 8
18434 // CHECK20-NEXT:    store i32 [[TMP3]], i32* [[__VLA_EXPR1]], align 4
18435 // CHECK20-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
18436 // CHECK20-NEXT:    store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_]], align 4
18437 // CHECK20-NEXT:    [[TMP6:%.*]] = load i32, i32* [[A]], align 4
18438 // CHECK20-NEXT:    store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_2]], align 4
18439 // CHECK20-NEXT:    [[TMP7:%.*]] = load i16, i16* [[AA]], align 2
18440 // CHECK20-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
18441 // CHECK20-NEXT:    store i16 [[TMP7]], i16* [[CONV]], align 2
18442 // CHECK20-NEXT:    [[TMP8:%.*]] = load i32, i32* [[AA_CASTED]], align 4
18443 // CHECK20-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
18444 // CHECK20-NEXT:    store i32 [[TMP9]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
18445 // CHECK20-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
18446 // CHECK20-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
18447 // CHECK20-NEXT:    store i32 [[TMP11]], i32* [[DOTCAPTURE_EXPR__CASTED3]], align 4
18448 // CHECK20-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED3]], align 4
18449 // CHECK20-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
18450 // CHECK20-NEXT:    [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i32*
18451 // CHECK20-NEXT:    store i32 [[TMP8]], i32* [[TMP14]], align 4
18452 // CHECK20-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
18453 // CHECK20-NEXT:    [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i32*
18454 // CHECK20-NEXT:    store i32 [[TMP8]], i32* [[TMP16]], align 4
18455 // CHECK20-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
18456 // CHECK20-NEXT:    store i8* null, i8** [[TMP17]], align 4
18457 // CHECK20-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
18458 // CHECK20-NEXT:    [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32*
18459 // CHECK20-NEXT:    store i32 [[TMP10]], i32* [[TMP19]], align 4
18460 // CHECK20-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
18461 // CHECK20-NEXT:    [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32*
18462 // CHECK20-NEXT:    store i32 [[TMP10]], i32* [[TMP21]], align 4
18463 // CHECK20-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
18464 // CHECK20-NEXT:    store i8* null, i8** [[TMP22]], align 4
18465 // CHECK20-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
18466 // CHECK20-NEXT:    [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i32*
18467 // CHECK20-NEXT:    store i32 [[TMP12]], i32* [[TMP24]], align 4
18468 // CHECK20-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
18469 // CHECK20-NEXT:    [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i32*
18470 // CHECK20-NEXT:    store i32 [[TMP12]], i32* [[TMP26]], align 4
18471 // CHECK20-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
18472 // CHECK20-NEXT:    store i8* null, i8** [[TMP27]], align 4
18473 // CHECK20-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
18474 // CHECK20-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
18475 // CHECK20-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 0
18476 // CHECK20-NEXT:    [[TMP31:%.*]] = load i16, i16* [[AA]], align 2
18477 // CHECK20-NEXT:    store i16 [[TMP31]], i16* [[TMP30]], align 4
18478 // CHECK20-NEXT:    [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 1
18479 // CHECK20-NEXT:    [[TMP33:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
18480 // CHECK20-NEXT:    store i32 [[TMP33]], i32* [[TMP32]], align 4
18481 // CHECK20-NEXT:    [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 2
18482 // CHECK20-NEXT:    [[TMP35:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
18483 // CHECK20-NEXT:    store i32 [[TMP35]], i32* [[TMP34]], align 4
18484 // CHECK20-NEXT:    [[TMP36:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 1, i32 72, i32 12, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1)
18485 // CHECK20-NEXT:    [[TMP37:%.*]] = bitcast i8* [[TMP36]] to %struct.kmp_task_t_with_privates*
18486 // CHECK20-NEXT:    [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP37]], i32 0, i32 0
18487 // CHECK20-NEXT:    [[TMP39:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP38]], i32 0, i32 0
18488 // CHECK20-NEXT:    [[TMP40:%.*]] = load i8*, i8** [[TMP39]], align 4
18489 // CHECK20-NEXT:    [[TMP41:%.*]] = bitcast %struct.anon* [[AGG_CAPTURED]] to i8*
18490 // CHECK20-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP40]], i8* align 4 [[TMP41]], i32 12, i1 false)
18491 // CHECK20-NEXT:    [[TMP42:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP37]], i32 0, i32 1
18492 // CHECK20-NEXT:    [[TMP43:%.*]] = bitcast i8* [[TMP40]] to %struct.anon*
18493 // CHECK20-NEXT:    [[TMP44:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 0
18494 // CHECK20-NEXT:    [[TMP45:%.*]] = bitcast [3 x i64]* [[TMP44]] to i8*
18495 // CHECK20-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP45]], i8* align 4 bitcast ([3 x i64]* @.offload_sizes to i8*), i32 24, i1 false)
18496 // CHECK20-NEXT:    [[TMP46:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 1
18497 // CHECK20-NEXT:    [[TMP47:%.*]] = bitcast [3 x i8*]* [[TMP46]] to i8*
18498 // CHECK20-NEXT:    [[TMP48:%.*]] = bitcast i8** [[TMP28]] to i8*
18499 // CHECK20-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP47]], i8* align 4 [[TMP48]], i32 12, i1 false)
18500 // CHECK20-NEXT:    [[TMP49:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 2
18501 // CHECK20-NEXT:    [[TMP50:%.*]] = bitcast [3 x i8*]* [[TMP49]] to i8*
18502 // CHECK20-NEXT:    [[TMP51:%.*]] = bitcast i8** [[TMP29]] to i8*
18503 // CHECK20-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP50]], i8* align 4 [[TMP51]], i32 12, i1 false)
18504 // CHECK20-NEXT:    [[TMP52:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 3
18505 // CHECK20-NEXT:    [[TMP53:%.*]] = load i16, i16* [[AA]], align 2
18506 // CHECK20-NEXT:    store i16 [[TMP53]], i16* [[TMP52]], align 4
18507 // CHECK20-NEXT:    [[TMP54:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i8* [[TMP36]])
18508 // CHECK20-NEXT:    [[TMP55:%.*]] = load i32, i32* [[A]], align 4
18509 // CHECK20-NEXT:    store i32 [[TMP55]], i32* [[A_CASTED]], align 4
18510 // CHECK20-NEXT:    [[TMP56:%.*]] = load i32, i32* [[A_CASTED]], align 4
18511 // CHECK20-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l107(i32 [[TMP56]]) #[[ATTR3:[0-9]+]]
18512 // CHECK20-NEXT:    [[TMP57:%.*]] = load i16, i16* [[AA]], align 2
18513 // CHECK20-NEXT:    [[CONV5:%.*]] = bitcast i32* [[AA_CASTED4]] to i16*
18514 // CHECK20-NEXT:    store i16 [[TMP57]], i16* [[CONV5]], align 2
18515 // CHECK20-NEXT:    [[TMP58:%.*]] = load i32, i32* [[AA_CASTED4]], align 4
18516 // CHECK20-NEXT:    [[TMP59:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0
18517 // CHECK20-NEXT:    [[TMP60:%.*]] = bitcast i8** [[TMP59]] to i32*
18518 // CHECK20-NEXT:    store i32 [[TMP58]], i32* [[TMP60]], align 4
18519 // CHECK20-NEXT:    [[TMP61:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0
18520 // CHECK20-NEXT:    [[TMP62:%.*]] = bitcast i8** [[TMP61]] to i32*
18521 // CHECK20-NEXT:    store i32 [[TMP58]], i32* [[TMP62]], align 4
18522 // CHECK20-NEXT:    [[TMP63:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS8]], i32 0, i32 0
18523 // CHECK20-NEXT:    store i8* null, i8** [[TMP63]], align 4
18524 // CHECK20-NEXT:    [[TMP64:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0
18525 // CHECK20-NEXT:    [[TMP65:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0
18526 // CHECK20-NEXT:    call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10)
18527 // CHECK20-NEXT:    [[TMP66:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113.region_id, i32 1, i8** [[TMP64]], i8** [[TMP65]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.4, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.5, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
18528 // CHECK20-NEXT:    [[TMP67:%.*]] = icmp ne i32 [[TMP66]], 0
18529 // CHECK20-NEXT:    br i1 [[TMP67]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
18530 // CHECK20:       omp_offload.failed:
18531 // CHECK20-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113(i32 [[TMP58]]) #[[ATTR3]]
18532 // CHECK20-NEXT:    br label [[OMP_OFFLOAD_CONT]]
18533 // CHECK20:       omp_offload.cont:
18534 // CHECK20-NEXT:    [[TMP68:%.*]] = load i32, i32* [[A]], align 4
18535 // CHECK20-NEXT:    store i32 [[TMP68]], i32* [[A_CASTED9]], align 4
18536 // CHECK20-NEXT:    [[TMP69:%.*]] = load i32, i32* [[A_CASTED9]], align 4
18537 // CHECK20-NEXT:    [[TMP70:%.*]] = load i16, i16* [[AA]], align 2
18538 // CHECK20-NEXT:    [[CONV11:%.*]] = bitcast i32* [[AA_CASTED10]] to i16*
18539 // CHECK20-NEXT:    store i16 [[TMP70]], i16* [[CONV11]], align 2
18540 // CHECK20-NEXT:    [[TMP71:%.*]] = load i32, i32* [[AA_CASTED10]], align 4
18541 // CHECK20-NEXT:    [[TMP72:%.*]] = load i32, i32* [[N_ADDR]], align 4
18542 // CHECK20-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP72]], 10
18543 // CHECK20-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
18544 // CHECK20:       omp_if.then:
18545 // CHECK20-NEXT:    [[TMP73:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS12]], i32 0, i32 0
18546 // CHECK20-NEXT:    [[TMP74:%.*]] = bitcast i8** [[TMP73]] to i32*
18547 // CHECK20-NEXT:    store i32 [[TMP69]], i32* [[TMP74]], align 4
18548 // CHECK20-NEXT:    [[TMP75:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS13]], i32 0, i32 0
18549 // CHECK20-NEXT:    [[TMP76:%.*]] = bitcast i8** [[TMP75]] to i32*
18550 // CHECK20-NEXT:    store i32 [[TMP69]], i32* [[TMP76]], align 4
18551 // CHECK20-NEXT:    [[TMP77:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS14]], i32 0, i32 0
18552 // CHECK20-NEXT:    store i8* null, i8** [[TMP77]], align 4
18553 // CHECK20-NEXT:    [[TMP78:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS12]], i32 0, i32 1
18554 // CHECK20-NEXT:    [[TMP79:%.*]] = bitcast i8** [[TMP78]] to i32*
18555 // CHECK20-NEXT:    store i32 [[TMP71]], i32* [[TMP79]], align 4
18556 // CHECK20-NEXT:    [[TMP80:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS13]], i32 0, i32 1
18557 // CHECK20-NEXT:    [[TMP81:%.*]] = bitcast i8** [[TMP80]] to i32*
18558 // CHECK20-NEXT:    store i32 [[TMP71]], i32* [[TMP81]], align 4
18559 // CHECK20-NEXT:    [[TMP82:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS14]], i32 0, i32 1
18560 // CHECK20-NEXT:    store i8* null, i8** [[TMP82]], align 4
18561 // CHECK20-NEXT:    [[TMP83:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS12]], i32 0, i32 0
18562 // CHECK20-NEXT:    [[TMP84:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS13]], i32 0, i32 0
18563 // CHECK20-NEXT:    call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10)
18564 // CHECK20-NEXT:    [[TMP85:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120.region_id, i32 2, i8** [[TMP83]], i8** [[TMP84]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.7, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.8, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
18565 // CHECK20-NEXT:    [[TMP86:%.*]] = icmp ne i32 [[TMP85]], 0
18566 // CHECK20-NEXT:    br i1 [[TMP86]], label [[OMP_OFFLOAD_FAILED16:%.*]], label [[OMP_OFFLOAD_CONT17:%.*]]
18567 // CHECK20:       omp_offload.failed16:
18568 // CHECK20-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120(i32 [[TMP69]], i32 [[TMP71]]) #[[ATTR3]]
18569 // CHECK20-NEXT:    br label [[OMP_OFFLOAD_CONT17]]
18570 // CHECK20:       omp_offload.cont17:
18571 // CHECK20-NEXT:    br label [[OMP_IF_END:%.*]]
18572 // CHECK20:       omp_if.else:
18573 // CHECK20-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120(i32 [[TMP69]], i32 [[TMP71]]) #[[ATTR3]]
18574 // CHECK20-NEXT:    br label [[OMP_IF_END]]
18575 // CHECK20:       omp_if.end:
18576 // CHECK20-NEXT:    [[TMP87:%.*]] = load i32, i32* [[N_ADDR]], align 4
18577 // CHECK20-NEXT:    store i32 [[TMP87]], i32* [[DOTCAPTURE_EXPR_18]], align 4
18578 // CHECK20-NEXT:    [[TMP88:%.*]] = load i32, i32* [[A]], align 4
18579 // CHECK20-NEXT:    store i32 [[TMP88]], i32* [[A_CASTED19]], align 4
18580 // CHECK20-NEXT:    [[TMP89:%.*]] = load i32, i32* [[A_CASTED19]], align 4
18581 // CHECK20-NEXT:    [[TMP90:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_18]], align 4
18582 // CHECK20-NEXT:    store i32 [[TMP90]], i32* [[DOTCAPTURE_EXPR__CASTED20]], align 4
18583 // CHECK20-NEXT:    [[TMP91:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED20]], align 4
18584 // CHECK20-NEXT:    [[TMP92:%.*]] = load i32, i32* [[N_ADDR]], align 4
18585 // CHECK20-NEXT:    [[CMP21:%.*]] = icmp sgt i32 [[TMP92]], 20
18586 // CHECK20-NEXT:    br i1 [[CMP21]], label [[OMP_IF_THEN22:%.*]], label [[OMP_IF_ELSE29:%.*]]
18587 // CHECK20:       omp_if.then22:
18588 // CHECK20-NEXT:    [[TMP93:%.*]] = mul nuw i32 [[TMP1]], 4
18589 // CHECK20-NEXT:    [[TMP94:%.*]] = sext i32 [[TMP93]] to i64
18590 // CHECK20-NEXT:    [[TMP95:%.*]] = mul nuw i32 5, [[TMP3]]
18591 // CHECK20-NEXT:    [[TMP96:%.*]] = mul nuw i32 [[TMP95]], 8
18592 // CHECK20-NEXT:    [[TMP97:%.*]] = sext i32 [[TMP96]] to i64
18593 // CHECK20-NEXT:    [[TMP98:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS23]], i32 0, i32 0
18594 // CHECK20-NEXT:    [[TMP99:%.*]] = bitcast i8** [[TMP98]] to i32*
18595 // CHECK20-NEXT:    store i32 [[TMP89]], i32* [[TMP99]], align 4
18596 // CHECK20-NEXT:    [[TMP100:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS24]], i32 0, i32 0
18597 // CHECK20-NEXT:    [[TMP101:%.*]] = bitcast i8** [[TMP100]] to i32*
18598 // CHECK20-NEXT:    store i32 [[TMP89]], i32* [[TMP101]], align 4
18599 // CHECK20-NEXT:    [[TMP102:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
18600 // CHECK20-NEXT:    store i64 4, i64* [[TMP102]], align 4
18601 // CHECK20-NEXT:    [[TMP103:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS25]], i32 0, i32 0
18602 // CHECK20-NEXT:    store i8* null, i8** [[TMP103]], align 4
18603 // CHECK20-NEXT:    [[TMP104:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS23]], i32 0, i32 1
18604 // CHECK20-NEXT:    [[TMP105:%.*]] = bitcast i8** [[TMP104]] to [10 x float]**
18605 // CHECK20-NEXT:    store [10 x float]* [[B]], [10 x float]** [[TMP105]], align 4
18606 // CHECK20-NEXT:    [[TMP106:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS24]], i32 0, i32 1
18607 // CHECK20-NEXT:    [[TMP107:%.*]] = bitcast i8** [[TMP106]] to [10 x float]**
18608 // CHECK20-NEXT:    store [10 x float]* [[B]], [10 x float]** [[TMP107]], align 4
18609 // CHECK20-NEXT:    [[TMP108:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1
18610 // CHECK20-NEXT:    store i64 40, i64* [[TMP108]], align 4
18611 // CHECK20-NEXT:    [[TMP109:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS25]], i32 0, i32 1
18612 // CHECK20-NEXT:    store i8* null, i8** [[TMP109]], align 4
18613 // CHECK20-NEXT:    [[TMP110:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS23]], i32 0, i32 2
18614 // CHECK20-NEXT:    [[TMP111:%.*]] = bitcast i8** [[TMP110]] to i32*
18615 // CHECK20-NEXT:    store i32 [[TMP1]], i32* [[TMP111]], align 4
18616 // CHECK20-NEXT:    [[TMP112:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS24]], i32 0, i32 2
18617 // CHECK20-NEXT:    [[TMP113:%.*]] = bitcast i8** [[TMP112]] to i32*
18618 // CHECK20-NEXT:    store i32 [[TMP1]], i32* [[TMP113]], align 4
18619 // CHECK20-NEXT:    [[TMP114:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2
18620 // CHECK20-NEXT:    store i64 4, i64* [[TMP114]], align 4
18621 // CHECK20-NEXT:    [[TMP115:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS25]], i32 0, i32 2
18622 // CHECK20-NEXT:    store i8* null, i8** [[TMP115]], align 4
18623 // CHECK20-NEXT:    [[TMP116:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS23]], i32 0, i32 3
18624 // CHECK20-NEXT:    [[TMP117:%.*]] = bitcast i8** [[TMP116]] to float**
18625 // CHECK20-NEXT:    store float* [[VLA]], float** [[TMP117]], align 4
18626 // CHECK20-NEXT:    [[TMP118:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS24]], i32 0, i32 3
18627 // CHECK20-NEXT:    [[TMP119:%.*]] = bitcast i8** [[TMP118]] to float**
18628 // CHECK20-NEXT:    store float* [[VLA]], float** [[TMP119]], align 4
18629 // CHECK20-NEXT:    [[TMP120:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3
18630 // CHECK20-NEXT:    store i64 [[TMP94]], i64* [[TMP120]], align 4
18631 // CHECK20-NEXT:    [[TMP121:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS25]], i32 0, i32 3
18632 // CHECK20-NEXT:    store i8* null, i8** [[TMP121]], align 4
18633 // CHECK20-NEXT:    [[TMP122:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS23]], i32 0, i32 4
18634 // CHECK20-NEXT:    [[TMP123:%.*]] = bitcast i8** [[TMP122]] to [5 x [10 x double]]**
18635 // CHECK20-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP123]], align 4
18636 // CHECK20-NEXT:    [[TMP124:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS24]], i32 0, i32 4
18637 // CHECK20-NEXT:    [[TMP125:%.*]] = bitcast i8** [[TMP124]] to [5 x [10 x double]]**
18638 // CHECK20-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP125]], align 4
18639 // CHECK20-NEXT:    [[TMP126:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4
18640 // CHECK20-NEXT:    store i64 400, i64* [[TMP126]], align 4
18641 // CHECK20-NEXT:    [[TMP127:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS25]], i32 0, i32 4
18642 // CHECK20-NEXT:    store i8* null, i8** [[TMP127]], align 4
18643 // CHECK20-NEXT:    [[TMP128:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS23]], i32 0, i32 5
18644 // CHECK20-NEXT:    [[TMP129:%.*]] = bitcast i8** [[TMP128]] to i32*
18645 // CHECK20-NEXT:    store i32 5, i32* [[TMP129]], align 4
18646 // CHECK20-NEXT:    [[TMP130:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS24]], i32 0, i32 5
18647 // CHECK20-NEXT:    [[TMP131:%.*]] = bitcast i8** [[TMP130]] to i32*
18648 // CHECK20-NEXT:    store i32 5, i32* [[TMP131]], align 4
18649 // CHECK20-NEXT:    [[TMP132:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 5
18650 // CHECK20-NEXT:    store i64 4, i64* [[TMP132]], align 4
18651 // CHECK20-NEXT:    [[TMP133:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS25]], i32 0, i32 5
18652 // CHECK20-NEXT:    store i8* null, i8** [[TMP133]], align 4
18653 // CHECK20-NEXT:    [[TMP134:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS23]], i32 0, i32 6
18654 // CHECK20-NEXT:    [[TMP135:%.*]] = bitcast i8** [[TMP134]] to i32*
18655 // CHECK20-NEXT:    store i32 [[TMP3]], i32* [[TMP135]], align 4
18656 // CHECK20-NEXT:    [[TMP136:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS24]], i32 0, i32 6
18657 // CHECK20-NEXT:    [[TMP137:%.*]] = bitcast i8** [[TMP136]] to i32*
18658 // CHECK20-NEXT:    store i32 [[TMP3]], i32* [[TMP137]], align 4
18659 // CHECK20-NEXT:    [[TMP138:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 6
18660 // CHECK20-NEXT:    store i64 4, i64* [[TMP138]], align 4
18661 // CHECK20-NEXT:    [[TMP139:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS25]], i32 0, i32 6
18662 // CHECK20-NEXT:    store i8* null, i8** [[TMP139]], align 4
18663 // CHECK20-NEXT:    [[TMP140:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS23]], i32 0, i32 7
18664 // CHECK20-NEXT:    [[TMP141:%.*]] = bitcast i8** [[TMP140]] to double**
18665 // CHECK20-NEXT:    store double* [[VLA1]], double** [[TMP141]], align 4
18666 // CHECK20-NEXT:    [[TMP142:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS24]], i32 0, i32 7
18667 // CHECK20-NEXT:    [[TMP143:%.*]] = bitcast i8** [[TMP142]] to double**
18668 // CHECK20-NEXT:    store double* [[VLA1]], double** [[TMP143]], align 4
18669 // CHECK20-NEXT:    [[TMP144:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7
18670 // CHECK20-NEXT:    store i64 [[TMP97]], i64* [[TMP144]], align 4
18671 // CHECK20-NEXT:    [[TMP145:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS25]], i32 0, i32 7
18672 // CHECK20-NEXT:    store i8* null, i8** [[TMP145]], align 4
18673 // CHECK20-NEXT:    [[TMP146:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS23]], i32 0, i32 8
18674 // CHECK20-NEXT:    [[TMP147:%.*]] = bitcast i8** [[TMP146]] to %struct.TT**
18675 // CHECK20-NEXT:    store %struct.TT* [[D]], %struct.TT** [[TMP147]], align 4
18676 // CHECK20-NEXT:    [[TMP148:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS24]], i32 0, i32 8
18677 // CHECK20-NEXT:    [[TMP149:%.*]] = bitcast i8** [[TMP148]] to %struct.TT**
18678 // CHECK20-NEXT:    store %struct.TT* [[D]], %struct.TT** [[TMP149]], align 4
18679 // CHECK20-NEXT:    [[TMP150:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 8
18680 // CHECK20-NEXT:    store i64 12, i64* [[TMP150]], align 4
18681 // CHECK20-NEXT:    [[TMP151:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS25]], i32 0, i32 8
18682 // CHECK20-NEXT:    store i8* null, i8** [[TMP151]], align 4
18683 // CHECK20-NEXT:    [[TMP152:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS23]], i32 0, i32 9
18684 // CHECK20-NEXT:    [[TMP153:%.*]] = bitcast i8** [[TMP152]] to i32*
18685 // CHECK20-NEXT:    store i32 [[TMP91]], i32* [[TMP153]], align 4
18686 // CHECK20-NEXT:    [[TMP154:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS24]], i32 0, i32 9
18687 // CHECK20-NEXT:    [[TMP155:%.*]] = bitcast i8** [[TMP154]] to i32*
18688 // CHECK20-NEXT:    store i32 [[TMP91]], i32* [[TMP155]], align 4
18689 // CHECK20-NEXT:    [[TMP156:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 9
18690 // CHECK20-NEXT:    store i64 4, i64* [[TMP156]], align 4
18691 // CHECK20-NEXT:    [[TMP157:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS25]], i32 0, i32 9
18692 // CHECK20-NEXT:    store i8* null, i8** [[TMP157]], align 4
18693 // CHECK20-NEXT:    [[TMP158:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS23]], i32 0, i32 0
18694 // CHECK20-NEXT:    [[TMP159:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS24]], i32 0, i32 0
18695 // CHECK20-NEXT:    [[TMP160:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
18696 // CHECK20-NEXT:    call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10)
18697 // CHECK20-NEXT:    [[TMP161:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145.region_id, i32 10, i8** [[TMP158]], i8** [[TMP159]], i64* [[TMP160]], i64* getelementptr inbounds ([10 x i64], [10 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
18698 // CHECK20-NEXT:    [[TMP162:%.*]] = icmp ne i32 [[TMP161]], 0
18699 // CHECK20-NEXT:    br i1 [[TMP162]], label [[OMP_OFFLOAD_FAILED27:%.*]], label [[OMP_OFFLOAD_CONT28:%.*]]
18700 // CHECK20:       omp_offload.failed27:
18701 // CHECK20-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145(i32 [[TMP89]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]], i32 [[TMP91]]) #[[ATTR3]]
18702 // CHECK20-NEXT:    br label [[OMP_OFFLOAD_CONT28]]
18703 // CHECK20:       omp_offload.cont28:
18704 // CHECK20-NEXT:    br label [[OMP_IF_END30:%.*]]
18705 // CHECK20:       omp_if.else29:
18706 // CHECK20-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145(i32 [[TMP89]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]], i32 [[TMP91]]) #[[ATTR3]]
18707 // CHECK20-NEXT:    br label [[OMP_IF_END30]]
18708 // CHECK20:       omp_if.end30:
18709 // CHECK20-NEXT:    [[TMP163:%.*]] = load i32, i32* [[A]], align 4
18710 // CHECK20-NEXT:    [[TMP164:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
18711 // CHECK20-NEXT:    call void @llvm.stackrestore(i8* [[TMP164]])
18712 // CHECK20-NEXT:    ret i32 [[TMP163]]
18713 //
18714 //
18715 // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103
18716 // CHECK20-SAME: (i32 [[AA:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]], i32 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] {
18717 // CHECK20-NEXT:  entry:
18718 // CHECK20-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
18719 // CHECK20-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
18720 // CHECK20-NEXT:    [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4
18721 // CHECK20-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
18722 // CHECK20-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]])
18723 // CHECK20-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
18724 // CHECK20-NEXT:    store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
18725 // CHECK20-NEXT:    store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4
18726 // CHECK20-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
18727 // CHECK20-NEXT:    [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
18728 // CHECK20-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4
18729 // CHECK20-NEXT:    call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
18730 // CHECK20-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
18731 // CHECK20-NEXT:    [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
18732 // CHECK20-NEXT:    store i16 [[TMP3]], i16* [[CONV3]], align 2
18733 // CHECK20-NEXT:    [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
18734 // CHECK20-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]])
18735 // CHECK20-NEXT:    ret void
18736 //
18737 //
18738 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined.
18739 // CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] {
18740 // CHECK20-NEXT:  entry:
18741 // CHECK20-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
18742 // CHECK20-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
18743 // CHECK20-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
18744 // CHECK20-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
18745 // CHECK20-NEXT:    [[TMP:%.*]] = alloca i32, align 4
18746 // CHECK20-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
18747 // CHECK20-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
18748 // CHECK20-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
18749 // CHECK20-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
18750 // CHECK20-NEXT:    [[I:%.*]] = alloca i32, align 4
18751 // CHECK20-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
18752 // CHECK20-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
18753 // CHECK20-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
18754 // CHECK20-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
18755 // CHECK20-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
18756 // CHECK20-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
18757 // CHECK20-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
18758 // CHECK20-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
18759 // CHECK20-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
18760 // CHECK20-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
18761 // CHECK20-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
18762 // CHECK20-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
18763 // CHECK20-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
18764 // CHECK20-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
18765 // CHECK20:       cond.true:
18766 // CHECK20-NEXT:    br label [[COND_END:%.*]]
18767 // CHECK20:       cond.false:
18768 // CHECK20-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
18769 // CHECK20-NEXT:    br label [[COND_END]]
18770 // CHECK20:       cond.end:
18771 // CHECK20-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
18772 // CHECK20-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
18773 // CHECK20-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
18774 // CHECK20-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
18775 // CHECK20-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
18776 // CHECK20:       omp.inner.for.cond:
18777 // CHECK20-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
18778 // CHECK20-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
18779 // CHECK20-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
18780 // CHECK20-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
18781 // CHECK20:       omp.inner.for.body:
18782 // CHECK20-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
18783 // CHECK20-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
18784 // CHECK20-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
18785 // CHECK20-NEXT:    store i32 [[ADD]], i32* [[I]], align 4
18786 // CHECK20-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
18787 // CHECK20:       omp.body.continue:
18788 // CHECK20-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
18789 // CHECK20:       omp.inner.for.inc:
18790 // CHECK20-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
18791 // CHECK20-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
18792 // CHECK20-NEXT:    store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4
18793 // CHECK20-NEXT:    br label [[OMP_INNER_FOR_COND]]
18794 // CHECK20:       omp.inner.for.end:
18795 // CHECK20-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
18796 // CHECK20:       omp.loop.exit:
18797 // CHECK20-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
18798 // CHECK20-NEXT:    ret void
18799 //
18800 //
18801 // CHECK20-LABEL: define {{[^@]+}}@.omp_task_privates_map.
18802 // CHECK20-SAME: (%struct..kmp_privates.t* noalias [[TMP0:%.*]], i16** noalias [[TMP1:%.*]], [3 x i8*]** noalias [[TMP2:%.*]], [3 x i8*]** noalias [[TMP3:%.*]], [3 x i64]** noalias [[TMP4:%.*]]) #[[ATTR4:[0-9]+]] {
18803 // CHECK20-NEXT:  entry:
18804 // CHECK20-NEXT:    [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 4
18805 // CHECK20-NEXT:    [[DOTADDR1:%.*]] = alloca i16**, align 4
18806 // CHECK20-NEXT:    [[DOTADDR2:%.*]] = alloca [3 x i8*]**, align 4
18807 // CHECK20-NEXT:    [[DOTADDR3:%.*]] = alloca [3 x i8*]**, align 4
18808 // CHECK20-NEXT:    [[DOTADDR4:%.*]] = alloca [3 x i64]**, align 4
18809 // CHECK20-NEXT:    store %struct..kmp_privates.t* [[TMP0]], %struct..kmp_privates.t** [[DOTADDR]], align 4
18810 // CHECK20-NEXT:    store i16** [[TMP1]], i16*** [[DOTADDR1]], align 4
18811 // CHECK20-NEXT:    store [3 x i8*]** [[TMP2]], [3 x i8*]*** [[DOTADDR2]], align 4
18812 // CHECK20-NEXT:    store [3 x i8*]** [[TMP3]], [3 x i8*]*** [[DOTADDR3]], align 4
18813 // CHECK20-NEXT:    store [3 x i64]** [[TMP4]], [3 x i64]*** [[DOTADDR4]], align 4
18814 // CHECK20-NEXT:    [[TMP5:%.*]] = load %struct..kmp_privates.t*, %struct..kmp_privates.t** [[DOTADDR]], align 4
18815 // CHECK20-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 0
18816 // CHECK20-NEXT:    [[TMP7:%.*]] = load [3 x i64]**, [3 x i64]*** [[DOTADDR4]], align 4
18817 // CHECK20-NEXT:    store [3 x i64]* [[TMP6]], [3 x i64]** [[TMP7]], align 4
18818 // CHECK20-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 1
18819 // CHECK20-NEXT:    [[TMP9:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR2]], align 4
18820 // CHECK20-NEXT:    store [3 x i8*]* [[TMP8]], [3 x i8*]** [[TMP9]], align 4
18821 // CHECK20-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 2
18822 // CHECK20-NEXT:    [[TMP11:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR3]], align 4
18823 // CHECK20-NEXT:    store [3 x i8*]* [[TMP10]], [3 x i8*]** [[TMP11]], align 4
18824 // CHECK20-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 3
18825 // CHECK20-NEXT:    [[TMP13:%.*]] = load i16**, i16*** [[DOTADDR1]], align 4
18826 // CHECK20-NEXT:    store i16* [[TMP12]], i16** [[TMP13]], align 4
18827 // CHECK20-NEXT:    ret void
18828 //
18829 //
18830 // CHECK20-LABEL: define {{[^@]+}}@.omp_task_entry.
18831 // CHECK20-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] {
18832 // CHECK20-NEXT:  entry:
18833 // CHECK20-NEXT:    [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
18834 // CHECK20-NEXT:    [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 4
18835 // CHECK20-NEXT:    [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 4
18836 // CHECK20-NEXT:    [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 4
18837 // CHECK20-NEXT:    [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 4
18838 // CHECK20-NEXT:    [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 4
18839 // CHECK20-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca i16*, align 4
18840 // CHECK20-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca [3 x i8*]*, align 4
18841 // CHECK20-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca [3 x i8*]*, align 4
18842 // CHECK20-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca [3 x i64]*, align 4
18843 // CHECK20-NEXT:    [[AA_CASTED_I:%.*]] = alloca i32, align 4
18844 // CHECK20-NEXT:    [[DOTCAPTURE_EXPR__CASTED_I:%.*]] = alloca i32, align 4
18845 // CHECK20-NEXT:    [[DOTCAPTURE_EXPR__CASTED4_I:%.*]] = alloca i32, align 4
18846 // CHECK20-NEXT:    [[DOTADDR:%.*]] = alloca i32, align 4
18847 // CHECK20-NEXT:    [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 4
18848 // CHECK20-NEXT:    store i32 [[TMP0]], i32* [[DOTADDR]], align 4
18849 // CHECK20-NEXT:    store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4
18850 // CHECK20-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4
18851 // CHECK20-NEXT:    [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4
18852 // CHECK20-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
18853 // CHECK20-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
18854 // CHECK20-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0
18855 // CHECK20-NEXT:    [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 4
18856 // CHECK20-NEXT:    [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon*
18857 // CHECK20-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1
18858 // CHECK20-NEXT:    [[TMP10:%.*]] = bitcast %struct..kmp_privates.t* [[TMP9]] to i8*
18859 // CHECK20-NEXT:    [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8*
18860 // CHECK20-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META12:![0-9]+]])
18861 // CHECK20-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]])
18862 // CHECK20-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META17:![0-9]+]])
18863 // CHECK20-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]])
18864 // CHECK20-NEXT:    store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !21
18865 // CHECK20-NEXT:    store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 4, !noalias !21
18866 // CHECK20-NEXT:    store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !21
18867 // CHECK20-NEXT:    store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* @.omp_task_privates_map. to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !21
18868 // CHECK20-NEXT:    store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 4, !noalias !21
18869 // CHECK20-NEXT:    store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !21
18870 // CHECK20-NEXT:    [[TMP12:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !21
18871 // CHECK20-NEXT:    [[TMP13:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !21
18872 // CHECK20-NEXT:    [[TMP14:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !21
18873 // CHECK20-NEXT:    [[TMP15:%.*]] = bitcast void (i8*, ...)* [[TMP13]] to void (i8*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)*
18874 // CHECK20-NEXT:    call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]]
18875 // CHECK20-NEXT:    [[TMP16:%.*]] = load i16*, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 4, !noalias !21
18876 // CHECK20-NEXT:    [[TMP17:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 4, !noalias !21
18877 // CHECK20-NEXT:    [[TMP18:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 4, !noalias !21
18878 // CHECK20-NEXT:    [[TMP19:%.*]] = load [3 x i64]*, [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 4, !noalias !21
18879 // CHECK20-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP17]], i32 0, i32 0
18880 // CHECK20-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP18]], i32 0, i32 0
18881 // CHECK20-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[TMP19]], i32 0, i32 0
18882 // CHECK20-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP12]], i32 0, i32 1
18883 // CHECK20-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[TMP12]], i32 0, i32 2
18884 // CHECK20-NEXT:    [[TMP25:%.*]] = load i32, i32* [[TMP23]], align 4
18885 // CHECK20-NEXT:    [[TMP26:%.*]] = load i32, i32* [[TMP24]], align 4
18886 // CHECK20-NEXT:    call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) #[[ATTR3]]
18887 // CHECK20-NEXT:    [[TMP27:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 [[TMP25]], i32 [[TMP26]]) #[[ATTR3]]
18888 // CHECK20-NEXT:    [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0
18889 // CHECK20-NEXT:    br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]]
18890 // CHECK20:       omp_offload.failed.i:
18891 // CHECK20-NEXT:    [[TMP29:%.*]] = load i16, i16* [[TMP16]], align 2
18892 // CHECK20-NEXT:    [[CONV_I:%.*]] = bitcast i32* [[AA_CASTED_I]] to i16*
18893 // CHECK20-NEXT:    store i16 [[TMP29]], i16* [[CONV_I]], align 2, !noalias !21
18894 // CHECK20-NEXT:    [[TMP30:%.*]] = load i32, i32* [[AA_CASTED_I]], align 4, !noalias !21
18895 // CHECK20-NEXT:    [[TMP31:%.*]] = load i32, i32* [[TMP23]], align 4
18896 // CHECK20-NEXT:    store i32 [[TMP31]], i32* [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias !21
18897 // CHECK20-NEXT:    [[TMP32:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias !21
18898 // CHECK20-NEXT:    [[TMP33:%.*]] = load i32, i32* [[TMP24]], align 4
18899 // CHECK20-NEXT:    store i32 [[TMP33]], i32* [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias !21
18900 // CHECK20-NEXT:    [[TMP34:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias !21
18901 // CHECK20-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103(i32 [[TMP30]], i32 [[TMP32]], i32 [[TMP34]]) #[[ATTR3]]
18902 // CHECK20-NEXT:    br label [[DOTOMP_OUTLINED__1_EXIT]]
18903 // CHECK20:       .omp_outlined..1.exit:
18904 // CHECK20-NEXT:    ret i32 0
18905 //
18906 //
18907 // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l107
18908 // CHECK20-SAME: (i32 [[A:%.*]]) #[[ATTR2]] {
18909 // CHECK20-NEXT:  entry:
18910 // CHECK20-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
18911 // CHECK20-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
18912 // CHECK20-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
18913 // CHECK20-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
18914 // CHECK20-NEXT:    store i32 [[TMP0]], i32* [[A_CASTED]], align 4
18915 // CHECK20-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
18916 // CHECK20-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]])
18917 // CHECK20-NEXT:    ret void
18918 //
18919 //
18920 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..2
18921 // CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]]) #[[ATTR2]] {
18922 // CHECK20-NEXT:  entry:
18923 // CHECK20-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
18924 // CHECK20-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
18925 // CHECK20-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
18926 // CHECK20-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
18927 // CHECK20-NEXT:    [[TMP:%.*]] = alloca i32, align 4
18928 // CHECK20-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
18929 // CHECK20-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
18930 // CHECK20-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
18931 // CHECK20-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
18932 // CHECK20-NEXT:    [[I:%.*]] = alloca i32, align 4
18933 // CHECK20-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
18934 // CHECK20-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
18935 // CHECK20-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
18936 // CHECK20-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
18937 // CHECK20-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
18938 // CHECK20-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
18939 // CHECK20-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
18940 // CHECK20-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
18941 // CHECK20-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
18942 // CHECK20-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
18943 // CHECK20-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
18944 // CHECK20-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
18945 // CHECK20-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
18946 // CHECK20:       cond.true:
18947 // CHECK20-NEXT:    br label [[COND_END:%.*]]
18948 // CHECK20:       cond.false:
18949 // CHECK20-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
18950 // CHECK20-NEXT:    br label [[COND_END]]
18951 // CHECK20:       cond.end:
18952 // CHECK20-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
18953 // CHECK20-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
18954 // CHECK20-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
18955 // CHECK20-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
18956 // CHECK20-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
18957 // CHECK20:       omp.inner.for.cond:
18958 // CHECK20-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
18959 // CHECK20-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
18960 // CHECK20-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
18961 // CHECK20-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
18962 // CHECK20:       omp.inner.for.body:
18963 // CHECK20-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
18964 // CHECK20-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
18965 // CHECK20-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
18966 // CHECK20-NEXT:    store i32 [[ADD]], i32* [[I]], align 4
18967 // CHECK20-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
18968 // CHECK20-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
18969 // CHECK20-NEXT:    store i32 [[ADD2]], i32* [[A_ADDR]], align 4
18970 // CHECK20-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
18971 // CHECK20:       omp.body.continue:
18972 // CHECK20-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
18973 // CHECK20:       omp.inner.for.inc:
18974 // CHECK20-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
18975 // CHECK20-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1
18976 // CHECK20-NEXT:    store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4
18977 // CHECK20-NEXT:    br label [[OMP_INNER_FOR_COND]]
18978 // CHECK20:       omp.inner.for.end:
18979 // CHECK20-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
18980 // CHECK20:       omp.loop.exit:
18981 // CHECK20-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
18982 // CHECK20-NEXT:    ret void
18983 //
18984 //
18985 // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113
18986 // CHECK20-SAME: (i32 [[AA:%.*]]) #[[ATTR2]] {
18987 // CHECK20-NEXT:  entry:
18988 // CHECK20-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
18989 // CHECK20-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
18990 // CHECK20-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
18991 // CHECK20-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
18992 // CHECK20-NEXT:    [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
18993 // CHECK20-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
18994 // CHECK20-NEXT:    store i16 [[TMP0]], i16* [[CONV1]], align 2
18995 // CHECK20-NEXT:    [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
18996 // CHECK20-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP1]])
18997 // CHECK20-NEXT:    ret void
18998 //
18999 //
19000 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..3
19001 // CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] {
19002 // CHECK20-NEXT:  entry:
19003 // CHECK20-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
19004 // CHECK20-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
19005 // CHECK20-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
19006 // CHECK20-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
19007 // CHECK20-NEXT:    [[TMP:%.*]] = alloca i32, align 4
19008 // CHECK20-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
19009 // CHECK20-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
19010 // CHECK20-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
19011 // CHECK20-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
19012 // CHECK20-NEXT:    [[I:%.*]] = alloca i32, align 4
19013 // CHECK20-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
19014 // CHECK20-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
19015 // CHECK20-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
19016 // CHECK20-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
19017 // CHECK20-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
19018 // CHECK20-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
19019 // CHECK20-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
19020 // CHECK20-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
19021 // CHECK20-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
19022 // CHECK20-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
19023 // CHECK20-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
19024 // CHECK20-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
19025 // CHECK20-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
19026 // CHECK20-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
19027 // CHECK20:       cond.true:
19028 // CHECK20-NEXT:    br label [[COND_END:%.*]]
19029 // CHECK20:       cond.false:
19030 // CHECK20-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
19031 // CHECK20-NEXT:    br label [[COND_END]]
19032 // CHECK20:       cond.end:
19033 // CHECK20-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
19034 // CHECK20-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
19035 // CHECK20-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
19036 // CHECK20-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
19037 // CHECK20-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
19038 // CHECK20:       omp.inner.for.cond:
19039 // CHECK20-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
19040 // CHECK20-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
19041 // CHECK20-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
19042 // CHECK20-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
19043 // CHECK20:       omp.inner.for.body:
19044 // CHECK20-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
19045 // CHECK20-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
19046 // CHECK20-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
19047 // CHECK20-NEXT:    store i32 [[ADD]], i32* [[I]], align 4
19048 // CHECK20-NEXT:    [[TMP8:%.*]] = load i16, i16* [[CONV]], align 4
19049 // CHECK20-NEXT:    [[CONV2:%.*]] = sext i16 [[TMP8]] to i32
19050 // CHECK20-NEXT:    [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
19051 // CHECK20-NEXT:    [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
19052 // CHECK20-NEXT:    store i16 [[CONV4]], i16* [[CONV]], align 4
19053 // CHECK20-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
19054 // CHECK20:       omp.body.continue:
19055 // CHECK20-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
19056 // CHECK20:       omp.inner.for.inc:
19057 // CHECK20-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
19058 // CHECK20-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP9]], 1
19059 // CHECK20-NEXT:    store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4
19060 // CHECK20-NEXT:    br label [[OMP_INNER_FOR_COND]]
19061 // CHECK20:       omp.inner.for.end:
19062 // CHECK20-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
19063 // CHECK20:       omp.loop.exit:
19064 // CHECK20-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
19065 // CHECK20-NEXT:    ret void
19066 //
19067 //
19068 // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120
19069 // CHECK20-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] {
19070 // CHECK20-NEXT:  entry:
19071 // CHECK20-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
19072 // CHECK20-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
19073 // CHECK20-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
19074 // CHECK20-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
19075 // CHECK20-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
19076 // CHECK20-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
19077 // CHECK20-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
19078 // CHECK20-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
19079 // CHECK20-NEXT:    store i32 [[TMP0]], i32* [[A_CASTED]], align 4
19080 // CHECK20-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
19081 // CHECK20-NEXT:    [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
19082 // CHECK20-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
19083 // CHECK20-NEXT:    store i16 [[TMP2]], i16* [[CONV1]], align 2
19084 // CHECK20-NEXT:    [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
19085 // CHECK20-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]])
19086 // CHECK20-NEXT:    ret void
19087 //
19088 //
19089 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..6
19090 // CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] {
19091 // CHECK20-NEXT:  entry:
19092 // CHECK20-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
19093 // CHECK20-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
19094 // CHECK20-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
19095 // CHECK20-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
19096 // CHECK20-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
19097 // CHECK20-NEXT:    [[TMP:%.*]] = alloca i32, align 4
19098 // CHECK20-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
19099 // CHECK20-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
19100 // CHECK20-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
19101 // CHECK20-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
19102 // CHECK20-NEXT:    [[I:%.*]] = alloca i32, align 4
19103 // CHECK20-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
19104 // CHECK20-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
19105 // CHECK20-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
19106 // CHECK20-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
19107 // CHECK20-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
19108 // CHECK20-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
19109 // CHECK20-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
19110 // CHECK20-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
19111 // CHECK20-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
19112 // CHECK20-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
19113 // CHECK20-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
19114 // CHECK20-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
19115 // CHECK20-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
19116 // CHECK20-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
19117 // CHECK20-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
19118 // CHECK20:       cond.true:
19119 // CHECK20-NEXT:    br label [[COND_END:%.*]]
19120 // CHECK20:       cond.false:
19121 // CHECK20-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
19122 // CHECK20-NEXT:    br label [[COND_END]]
19123 // CHECK20:       cond.end:
19124 // CHECK20-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
19125 // CHECK20-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
19126 // CHECK20-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
19127 // CHECK20-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
19128 // CHECK20-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
19129 // CHECK20:       omp.inner.for.cond:
19130 // CHECK20-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
19131 // CHECK20-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
19132 // CHECK20-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
19133 // CHECK20-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
19134 // CHECK20:       omp.inner.for.body:
19135 // CHECK20-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
19136 // CHECK20-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
19137 // CHECK20-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
19138 // CHECK20-NEXT:    store i32 [[ADD]], i32* [[I]], align 4
19139 // CHECK20-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
19140 // CHECK20-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
19141 // CHECK20-NEXT:    store i32 [[ADD2]], i32* [[A_ADDR]], align 4
19142 // CHECK20-NEXT:    [[TMP9:%.*]] = load i16, i16* [[CONV]], align 4
19143 // CHECK20-NEXT:    [[CONV3:%.*]] = sext i16 [[TMP9]] to i32
19144 // CHECK20-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
19145 // CHECK20-NEXT:    [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
19146 // CHECK20-NEXT:    store i16 [[CONV5]], i16* [[CONV]], align 4
19147 // CHECK20-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
19148 // CHECK20:       omp.body.continue:
19149 // CHECK20-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
19150 // CHECK20:       omp.inner.for.inc:
19151 // CHECK20-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
19152 // CHECK20-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP10]], 1
19153 // CHECK20-NEXT:    store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4
19154 // CHECK20-NEXT:    br label [[OMP_INNER_FOR_COND]]
19155 // CHECK20:       omp.inner.for.end:
19156 // CHECK20-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
19157 // CHECK20:       omp.loop.exit:
19158 // CHECK20-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
19159 // CHECK20-NEXT:    ret void
19160 //
19161 //
19162 // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145
19163 // CHECK20-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] {
19164 // CHECK20-NEXT:  entry:
19165 // CHECK20-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
19166 // CHECK20-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
19167 // CHECK20-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
19168 // CHECK20-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 4
19169 // CHECK20-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
19170 // CHECK20-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
19171 // CHECK20-NEXT:    [[VLA_ADDR4:%.*]] = alloca i32, align 4
19172 // CHECK20-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 4
19173 // CHECK20-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
19174 // CHECK20-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
19175 // CHECK20-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
19176 // CHECK20-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
19177 // CHECK20-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
19178 // CHECK20-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
19179 // CHECK20-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
19180 // CHECK20-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 4
19181 // CHECK20-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
19182 // CHECK20-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
19183 // CHECK20-NEXT:    store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
19184 // CHECK20-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 4
19185 // CHECK20-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
19186 // CHECK20-NEXT:    store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
19187 // CHECK20-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
19188 // CHECK20-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
19189 // CHECK20-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
19190 // CHECK20-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
19191 // CHECK20-NEXT:    [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
19192 // CHECK20-NEXT:    [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
19193 // CHECK20-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
19194 // CHECK20-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
19195 // CHECK20-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
19196 // CHECK20-NEXT:    store i32 [[TMP8]], i32* [[A_CASTED]], align 4
19197 // CHECK20-NEXT:    [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4
19198 // CHECK20-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
19199 // CHECK20-NEXT:    store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
19200 // CHECK20-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
19201 // CHECK20-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*, i32)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i32 [[TMP11]])
19202 // CHECK20-NEXT:    ret void
19203 //
19204 //
19205 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..9
19206 // CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] {
19207 // CHECK20-NEXT:  entry:
19208 // CHECK20-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
19209 // CHECK20-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
19210 // CHECK20-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
19211 // CHECK20-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
19212 // CHECK20-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
19213 // CHECK20-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 4
19214 // CHECK20-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
19215 // CHECK20-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
19216 // CHECK20-NEXT:    [[VLA_ADDR4:%.*]] = alloca i32, align 4
19217 // CHECK20-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 4
19218 // CHECK20-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
19219 // CHECK20-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
19220 // CHECK20-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
19221 // CHECK20-NEXT:    [[TMP:%.*]] = alloca i32, align 4
19222 // CHECK20-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
19223 // CHECK20-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
19224 // CHECK20-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
19225 // CHECK20-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
19226 // CHECK20-NEXT:    [[I:%.*]] = alloca i32, align 4
19227 // CHECK20-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
19228 // CHECK20-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
19229 // CHECK20-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
19230 // CHECK20-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
19231 // CHECK20-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
19232 // CHECK20-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 4
19233 // CHECK20-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
19234 // CHECK20-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
19235 // CHECK20-NEXT:    store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
19236 // CHECK20-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 4
19237 // CHECK20-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
19238 // CHECK20-NEXT:    store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
19239 // CHECK20-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
19240 // CHECK20-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
19241 // CHECK20-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
19242 // CHECK20-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
19243 // CHECK20-NEXT:    [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
19244 // CHECK20-NEXT:    [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
19245 // CHECK20-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
19246 // CHECK20-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
19247 // CHECK20-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
19248 // CHECK20-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
19249 // CHECK20-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
19250 // CHECK20-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
19251 // CHECK20-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
19252 // CHECK20-NEXT:    [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
19253 // CHECK20-NEXT:    [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
19254 // CHECK20-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
19255 // CHECK20-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
19256 // CHECK20:       omp.dispatch.cond:
19257 // CHECK20-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
19258 // CHECK20-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 9
19259 // CHECK20-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
19260 // CHECK20:       cond.true:
19261 // CHECK20-NEXT:    br label [[COND_END:%.*]]
19262 // CHECK20:       cond.false:
19263 // CHECK20-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
19264 // CHECK20-NEXT:    br label [[COND_END]]
19265 // CHECK20:       cond.end:
19266 // CHECK20-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
19267 // CHECK20-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
19268 // CHECK20-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
19269 // CHECK20-NEXT:    store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
19270 // CHECK20-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
19271 // CHECK20-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
19272 // CHECK20-NEXT:    [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
19273 // CHECK20-NEXT:    br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
19274 // CHECK20:       omp.dispatch.body:
19275 // CHECK20-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
19276 // CHECK20:       omp.inner.for.cond:
19277 // CHECK20-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
19278 // CHECK20-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !22
19279 // CHECK20-NEXT:    [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
19280 // CHECK20-NEXT:    br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
19281 // CHECK20:       omp.inner.for.body:
19282 // CHECK20-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
19283 // CHECK20-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
19284 // CHECK20-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
19285 // CHECK20-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !22
19286 // CHECK20-NEXT:    [[TMP19:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !22
19287 // CHECK20-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP19]], 1
19288 // CHECK20-NEXT:    store i32 [[ADD7]], i32* [[A_ADDR]], align 4, !llvm.access.group !22
19289 // CHECK20-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2
19290 // CHECK20-NEXT:    [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !22
19291 // CHECK20-NEXT:    [[CONV:%.*]] = fpext float [[TMP20]] to double
19292 // CHECK20-NEXT:    [[ADD8:%.*]] = fadd double [[CONV]], 1.000000e+00
19293 // CHECK20-NEXT:    [[CONV9:%.*]] = fptrunc double [[ADD8]] to float
19294 // CHECK20-NEXT:    store float [[CONV9]], float* [[ARRAYIDX]], align 4, !llvm.access.group !22
19295 // CHECK20-NEXT:    [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3
19296 // CHECK20-NEXT:    [[TMP21:%.*]] = load float, float* [[ARRAYIDX10]], align 4, !llvm.access.group !22
19297 // CHECK20-NEXT:    [[CONV11:%.*]] = fpext float [[TMP21]] to double
19298 // CHECK20-NEXT:    [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00
19299 // CHECK20-NEXT:    [[CONV13:%.*]] = fptrunc double [[ADD12]] to float
19300 // CHECK20-NEXT:    store float [[CONV13]], float* [[ARRAYIDX10]], align 4, !llvm.access.group !22
19301 // CHECK20-NEXT:    [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1
19302 // CHECK20-NEXT:    [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX14]], i32 0, i32 2
19303 // CHECK20-NEXT:    [[TMP22:%.*]] = load double, double* [[ARRAYIDX15]], align 8, !llvm.access.group !22
19304 // CHECK20-NEXT:    [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00
19305 // CHECK20-NEXT:    store double [[ADD16]], double* [[ARRAYIDX15]], align 8, !llvm.access.group !22
19306 // CHECK20-NEXT:    [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]]
19307 // CHECK20-NEXT:    [[ARRAYIDX17:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP23]]
19308 // CHECK20-NEXT:    [[ARRAYIDX18:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX17]], i32 3
19309 // CHECK20-NEXT:    [[TMP24:%.*]] = load double, double* [[ARRAYIDX18]], align 8, !llvm.access.group !22
19310 // CHECK20-NEXT:    [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00
19311 // CHECK20-NEXT:    store double [[ADD19]], double* [[ARRAYIDX18]], align 8, !llvm.access.group !22
19312 // CHECK20-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0
19313 // CHECK20-NEXT:    [[TMP25:%.*]] = load i64, i64* [[X]], align 4, !llvm.access.group !22
19314 // CHECK20-NEXT:    [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1
19315 // CHECK20-NEXT:    store i64 [[ADD20]], i64* [[X]], align 4, !llvm.access.group !22
19316 // CHECK20-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1
19317 // CHECK20-NEXT:    [[TMP26:%.*]] = load i8, i8* [[Y]], align 4, !llvm.access.group !22
19318 // CHECK20-NEXT:    [[CONV21:%.*]] = sext i8 [[TMP26]] to i32
19319 // CHECK20-NEXT:    [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1
19320 // CHECK20-NEXT:    [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8
19321 // CHECK20-NEXT:    store i8 [[CONV23]], i8* [[Y]], align 4, !llvm.access.group !22
19322 // CHECK20-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
19323 // CHECK20:       omp.body.continue:
19324 // CHECK20-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
19325 // CHECK20:       omp.inner.for.inc:
19326 // CHECK20-NEXT:    [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
19327 // CHECK20-NEXT:    [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1
19328 // CHECK20-NEXT:    store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
19329 // CHECK20-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]]
19330 // CHECK20:       omp.inner.for.end:
19331 // CHECK20-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
19332 // CHECK20:       omp.dispatch.inc:
19333 // CHECK20-NEXT:    [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
19334 // CHECK20-NEXT:    [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
19335 // CHECK20-NEXT:    [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]
19336 // CHECK20-NEXT:    store i32 [[ADD25]], i32* [[DOTOMP_LB]], align 4
19337 // CHECK20-NEXT:    [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
19338 // CHECK20-NEXT:    [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
19339 // CHECK20-NEXT:    [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]]
19340 // CHECK20-NEXT:    store i32 [[ADD26]], i32* [[DOTOMP_UB]], align 4
19341 // CHECK20-NEXT:    br label [[OMP_DISPATCH_COND]]
19342 // CHECK20:       omp.dispatch.end:
19343 // CHECK20-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]])
19344 // CHECK20-NEXT:    ret void
19345 //
19346 //
19347 // CHECK20-LABEL: define {{[^@]+}}@_Z3bari
19348 // CHECK20-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
19349 // CHECK20-NEXT:  entry:
19350 // CHECK20-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
19351 // CHECK20-NEXT:    [[A:%.*]] = alloca i32, align 4
19352 // CHECK20-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4
19353 // CHECK20-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
19354 // CHECK20-NEXT:    store i32 0, i32* [[A]], align 4
19355 // CHECK20-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
19356 // CHECK20-NEXT:    [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]])
19357 // CHECK20-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
19358 // CHECK20-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
19359 // CHECK20-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
19360 // CHECK20-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
19361 // CHECK20-NEXT:    [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]])
19362 // CHECK20-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
19363 // CHECK20-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
19364 // CHECK20-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
19365 // CHECK20-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
19366 // CHECK20-NEXT:    [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]])
19367 // CHECK20-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
19368 // CHECK20-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
19369 // CHECK20-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
19370 // CHECK20-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
19371 // CHECK20-NEXT:    [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]])
19372 // CHECK20-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
19373 // CHECK20-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
19374 // CHECK20-NEXT:    store i32 [[ADD6]], i32* [[A]], align 4
19375 // CHECK20-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
19376 // CHECK20-NEXT:    ret i32 [[TMP8]]
19377 //
19378 //
19379 // CHECK20-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
19380 // CHECK20-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 {
19381 // CHECK20-NEXT:  entry:
19382 // CHECK20-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
19383 // CHECK20-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
19384 // CHECK20-NEXT:    [[B:%.*]] = alloca i32, align 4
19385 // CHECK20-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 4
19386 // CHECK20-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 4
19387 // CHECK20-NEXT:    [[B_CASTED:%.*]] = alloca i32, align 4
19388 // CHECK20-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4
19389 // CHECK20-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4
19390 // CHECK20-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4
19391 // CHECK20-NEXT:    [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 4
19392 // CHECK20-NEXT:    [[TMP:%.*]] = alloca i32, align 4
19393 // CHECK20-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
19394 // CHECK20-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
19395 // CHECK20-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
19396 // CHECK20-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
19397 // CHECK20-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
19398 // CHECK20-NEXT:    store i32 [[ADD]], i32* [[B]], align 4
19399 // CHECK20-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
19400 // CHECK20-NEXT:    [[TMP2:%.*]] = call i8* @llvm.stacksave()
19401 // CHECK20-NEXT:    store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4
19402 // CHECK20-NEXT:    [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]
19403 // CHECK20-NEXT:    [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2
19404 // CHECK20-NEXT:    store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
19405 // CHECK20-NEXT:    [[TMP4:%.*]] = load i32, i32* [[B]], align 4
19406 // CHECK20-NEXT:    store i32 [[TMP4]], i32* [[B_CASTED]], align 4
19407 // CHECK20-NEXT:    [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4
19408 // CHECK20-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
19409 // CHECK20-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 60
19410 // CHECK20-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
19411 // CHECK20:       omp_if.then:
19412 // CHECK20-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
19413 // CHECK20-NEXT:    [[TMP7:%.*]] = mul nuw i32 2, [[TMP1]]
19414 // CHECK20-NEXT:    [[TMP8:%.*]] = mul nuw i32 [[TMP7]], 2
19415 // CHECK20-NEXT:    [[TMP9:%.*]] = sext i32 [[TMP8]] to i64
19416 // CHECK20-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
19417 // CHECK20-NEXT:    [[TMP11:%.*]] = bitcast i8** [[TMP10]] to %struct.S1**
19418 // CHECK20-NEXT:    store %struct.S1* [[THIS1]], %struct.S1** [[TMP11]], align 4
19419 // CHECK20-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
19420 // CHECK20-NEXT:    [[TMP13:%.*]] = bitcast i8** [[TMP12]] to double**
19421 // CHECK20-NEXT:    store double* [[A]], double** [[TMP13]], align 4
19422 // CHECK20-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
19423 // CHECK20-NEXT:    store i64 8, i64* [[TMP14]], align 4
19424 // CHECK20-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
19425 // CHECK20-NEXT:    store i8* null, i8** [[TMP15]], align 4
19426 // CHECK20-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
19427 // CHECK20-NEXT:    [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32*
19428 // CHECK20-NEXT:    store i32 [[TMP5]], i32* [[TMP17]], align 4
19429 // CHECK20-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
19430 // CHECK20-NEXT:    [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32*
19431 // CHECK20-NEXT:    store i32 [[TMP5]], i32* [[TMP19]], align 4
19432 // CHECK20-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1
19433 // CHECK20-NEXT:    store i64 4, i64* [[TMP20]], align 4
19434 // CHECK20-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
19435 // CHECK20-NEXT:    store i8* null, i8** [[TMP21]], align 4
19436 // CHECK20-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
19437 // CHECK20-NEXT:    [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i32*
19438 // CHECK20-NEXT:    store i32 2, i32* [[TMP23]], align 4
19439 // CHECK20-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
19440 // CHECK20-NEXT:    [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i32*
19441 // CHECK20-NEXT:    store i32 2, i32* [[TMP25]], align 4
19442 // CHECK20-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2
19443 // CHECK20-NEXT:    store i64 4, i64* [[TMP26]], align 4
19444 // CHECK20-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
19445 // CHECK20-NEXT:    store i8* null, i8** [[TMP27]], align 4
19446 // CHECK20-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
19447 // CHECK20-NEXT:    [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i32*
19448 // CHECK20-NEXT:    store i32 [[TMP1]], i32* [[TMP29]], align 4
19449 // CHECK20-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
19450 // CHECK20-NEXT:    [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i32*
19451 // CHECK20-NEXT:    store i32 [[TMP1]], i32* [[TMP31]], align 4
19452 // CHECK20-NEXT:    [[TMP32:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3
19453 // CHECK20-NEXT:    store i64 4, i64* [[TMP32]], align 4
19454 // CHECK20-NEXT:    [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
19455 // CHECK20-NEXT:    store i8* null, i8** [[TMP33]], align 4
19456 // CHECK20-NEXT:    [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
19457 // CHECK20-NEXT:    [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i16**
19458 // CHECK20-NEXT:    store i16* [[VLA]], i16** [[TMP35]], align 4
19459 // CHECK20-NEXT:    [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
19460 // CHECK20-NEXT:    [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i16**
19461 // CHECK20-NEXT:    store i16* [[VLA]], i16** [[TMP37]], align 4
19462 // CHECK20-NEXT:    [[TMP38:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4
19463 // CHECK20-NEXT:    store i64 [[TMP9]], i64* [[TMP38]], align 4
19464 // CHECK20-NEXT:    [[TMP39:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4
19465 // CHECK20-NEXT:    store i8* null, i8** [[TMP39]], align 4
19466 // CHECK20-NEXT:    [[TMP40:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
19467 // CHECK20-NEXT:    [[TMP41:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
19468 // CHECK20-NEXT:    [[TMP42:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
19469 // CHECK20-NEXT:    call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10)
19470 // CHECK20-NEXT:    [[TMP43:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218.region_id, i32 5, i8** [[TMP40]], i8** [[TMP41]], i64* [[TMP42]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.12, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
19471 // CHECK20-NEXT:    [[TMP44:%.*]] = icmp ne i32 [[TMP43]], 0
19472 // CHECK20-NEXT:    br i1 [[TMP44]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
19473 // CHECK20:       omp_offload.failed:
19474 // CHECK20-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR3]]
19475 // CHECK20-NEXT:    br label [[OMP_OFFLOAD_CONT]]
19476 // CHECK20:       omp_offload.cont:
19477 // CHECK20-NEXT:    br label [[OMP_IF_END:%.*]]
19478 // CHECK20:       omp_if.else:
19479 // CHECK20-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR3]]
19480 // CHECK20-NEXT:    br label [[OMP_IF_END]]
19481 // CHECK20:       omp_if.end:
19482 // CHECK20-NEXT:    [[TMP45:%.*]] = mul nsw i32 1, [[TMP1]]
19483 // CHECK20-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP45]]
19484 // CHECK20-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
19485 // CHECK20-NEXT:    [[TMP46:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2
19486 // CHECK20-NEXT:    [[CONV:%.*]] = sext i16 [[TMP46]] to i32
19487 // CHECK20-NEXT:    [[TMP47:%.*]] = load i32, i32* [[B]], align 4
19488 // CHECK20-NEXT:    [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP47]]
19489 // CHECK20-NEXT:    [[TMP48:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
19490 // CHECK20-NEXT:    call void @llvm.stackrestore(i8* [[TMP48]])
19491 // CHECK20-NEXT:    ret i32 [[ADD3]]
19492 //
19493 //
19494 // CHECK20-LABEL: define {{[^@]+}}@_ZL7fstatici
19495 // CHECK20-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
19496 // CHECK20-NEXT:  entry:
19497 // CHECK20-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
19498 // CHECK20-NEXT:    [[A:%.*]] = alloca i32, align 4
19499 // CHECK20-NEXT:    [[AA:%.*]] = alloca i16, align 2
19500 // CHECK20-NEXT:    [[AAA:%.*]] = alloca i8, align 1
19501 // CHECK20-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
19502 // CHECK20-NEXT:    [[N_CASTED:%.*]] = alloca i32, align 4
19503 // CHECK20-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
19504 // CHECK20-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
19505 // CHECK20-NEXT:    [[AAA_CASTED:%.*]] = alloca i32, align 4
19506 // CHECK20-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4
19507 // CHECK20-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4
19508 // CHECK20-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4
19509 // CHECK20-NEXT:    [[TMP:%.*]] = alloca i32, align 4
19510 // CHECK20-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
19511 // CHECK20-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
19512 // CHECK20-NEXT:    [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4
19513 // CHECK20-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
19514 // CHECK20-NEXT:    store i32 0, i32* [[A]], align 4
19515 // CHECK20-NEXT:    store i16 0, i16* [[AA]], align 2
19516 // CHECK20-NEXT:    store i8 0, i8* [[AAA]], align 1
19517 // CHECK20-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
19518 // CHECK20-NEXT:    store i32 [[TMP0]], i32* [[N_CASTED]], align 4
19519 // CHECK20-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_CASTED]], align 4
19520 // CHECK20-NEXT:    [[TMP2:%.*]] = load i32, i32* [[A]], align 4
19521 // CHECK20-NEXT:    store i32 [[TMP2]], i32* [[A_CASTED]], align 4
19522 // CHECK20-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A_CASTED]], align 4
19523 // CHECK20-NEXT:    [[TMP4:%.*]] = load i16, i16* [[AA]], align 2
19524 // CHECK20-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
19525 // CHECK20-NEXT:    store i16 [[TMP4]], i16* [[CONV]], align 2
19526 // CHECK20-NEXT:    [[TMP5:%.*]] = load i32, i32* [[AA_CASTED]], align 4
19527 // CHECK20-NEXT:    [[TMP6:%.*]] = load i8, i8* [[AAA]], align 1
19528 // CHECK20-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
19529 // CHECK20-NEXT:    store i8 [[TMP6]], i8* [[CONV1]], align 1
19530 // CHECK20-NEXT:    [[TMP7:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
19531 // CHECK20-NEXT:    [[TMP8:%.*]] = load i32, i32* [[N_ADDR]], align 4
19532 // CHECK20-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP8]], 50
19533 // CHECK20-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
19534 // CHECK20:       omp_if.then:
19535 // CHECK20-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
19536 // CHECK20-NEXT:    [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32*
19537 // CHECK20-NEXT:    store i32 [[TMP1]], i32* [[TMP10]], align 4
19538 // CHECK20-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
19539 // CHECK20-NEXT:    [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32*
19540 // CHECK20-NEXT:    store i32 [[TMP1]], i32* [[TMP12]], align 4
19541 // CHECK20-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
19542 // CHECK20-NEXT:    store i8* null, i8** [[TMP13]], align 4
19543 // CHECK20-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
19544 // CHECK20-NEXT:    [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32*
19545 // CHECK20-NEXT:    store i32 [[TMP3]], i32* [[TMP15]], align 4
19546 // CHECK20-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
19547 // CHECK20-NEXT:    [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32*
19548 // CHECK20-NEXT:    store i32 [[TMP3]], i32* [[TMP17]], align 4
19549 // CHECK20-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
19550 // CHECK20-NEXT:    store i8* null, i8** [[TMP18]], align 4
19551 // CHECK20-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
19552 // CHECK20-NEXT:    [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32*
19553 // CHECK20-NEXT:    store i32 [[TMP5]], i32* [[TMP20]], align 4
19554 // CHECK20-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
19555 // CHECK20-NEXT:    [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i32*
19556 // CHECK20-NEXT:    store i32 [[TMP5]], i32* [[TMP22]], align 4
19557 // CHECK20-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
19558 // CHECK20-NEXT:    store i8* null, i8** [[TMP23]], align 4
19559 // CHECK20-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
19560 // CHECK20-NEXT:    [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i32*
19561 // CHECK20-NEXT:    store i32 [[TMP7]], i32* [[TMP25]], align 4
19562 // CHECK20-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
19563 // CHECK20-NEXT:    [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i32*
19564 // CHECK20-NEXT:    store i32 [[TMP7]], i32* [[TMP27]], align 4
19565 // CHECK20-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
19566 // CHECK20-NEXT:    store i8* null, i8** [[TMP28]], align 4
19567 // CHECK20-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
19568 // CHECK20-NEXT:    [[TMP30:%.*]] = bitcast i8** [[TMP29]] to [10 x i32]**
19569 // CHECK20-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP30]], align 4
19570 // CHECK20-NEXT:    [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
19571 // CHECK20-NEXT:    [[TMP32:%.*]] = bitcast i8** [[TMP31]] to [10 x i32]**
19572 // CHECK20-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP32]], align 4
19573 // CHECK20-NEXT:    [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4
19574 // CHECK20-NEXT:    store i8* null, i8** [[TMP33]], align 4
19575 // CHECK20-NEXT:    [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
19576 // CHECK20-NEXT:    [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
19577 // CHECK20-NEXT:    [[TMP36:%.*]] = load i32, i32* [[A]], align 4
19578 // CHECK20-NEXT:    store i32 [[TMP36]], i32* [[DOTCAPTURE_EXPR_]], align 4
19579 // CHECK20-NEXT:    [[TMP37:%.*]] = load i32, i32* [[N_ADDR]], align 4
19580 // CHECK20-NEXT:    store i32 [[TMP37]], i32* [[DOTCAPTURE_EXPR_2]], align 4
19581 // CHECK20-NEXT:    [[TMP38:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
19582 // CHECK20-NEXT:    [[TMP39:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
19583 // CHECK20-NEXT:    [[SUB:%.*]] = sub i32 [[TMP38]], [[TMP39]]
19584 // CHECK20-NEXT:    [[SUB4:%.*]] = sub i32 [[SUB]], 1
19585 // CHECK20-NEXT:    [[ADD:%.*]] = add i32 [[SUB4]], 1
19586 // CHECK20-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], 1
19587 // CHECK20-NEXT:    [[SUB5:%.*]] = sub i32 [[DIV]], 1
19588 // CHECK20-NEXT:    store i32 [[SUB5]], i32* [[DOTCAPTURE_EXPR_3]], align 4
19589 // CHECK20-NEXT:    [[TMP40:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
19590 // CHECK20-NEXT:    [[ADD6:%.*]] = add i32 [[TMP40]], 1
19591 // CHECK20-NEXT:    [[TMP41:%.*]] = zext i32 [[ADD6]] to i64
19592 // CHECK20-NEXT:    call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 [[TMP41]])
19593 // CHECK20-NEXT:    [[TMP42:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200.region_id, i32 5, i8** [[TMP34]], i8** [[TMP35]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes.14, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.15, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
19594 // CHECK20-NEXT:    [[TMP43:%.*]] = icmp ne i32 [[TMP42]], 0
19595 // CHECK20-NEXT:    br i1 [[TMP43]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
19596 // CHECK20:       omp_offload.failed:
19597 // CHECK20-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], i32 [[TMP7]], [10 x i32]* [[B]]) #[[ATTR3]]
19598 // CHECK20-NEXT:    br label [[OMP_OFFLOAD_CONT]]
19599 // CHECK20:       omp_offload.cont:
19600 // CHECK20-NEXT:    br label [[OMP_IF_END:%.*]]
19601 // CHECK20:       omp_if.else:
19602 // CHECK20-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], i32 [[TMP7]], [10 x i32]* [[B]]) #[[ATTR3]]
19603 // CHECK20-NEXT:    br label [[OMP_IF_END]]
19604 // CHECK20:       omp_if.end:
19605 // CHECK20-NEXT:    [[TMP44:%.*]] = load i32, i32* [[A]], align 4
19606 // CHECK20-NEXT:    ret i32 [[TMP44]]
19607 //
19608 //
19609 // CHECK20-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
19610 // CHECK20-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat {
19611 // CHECK20-NEXT:  entry:
19612 // CHECK20-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
19613 // CHECK20-NEXT:    [[A:%.*]] = alloca i32, align 4
19614 // CHECK20-NEXT:    [[AA:%.*]] = alloca i16, align 2
19615 // CHECK20-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
19616 // CHECK20-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
19617 // CHECK20-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
19618 // CHECK20-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4
19619 // CHECK20-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4
19620 // CHECK20-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4
19621 // CHECK20-NEXT:    [[TMP:%.*]] = alloca i32, align 4
19622 // CHECK20-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
19623 // CHECK20-NEXT:    store i32 0, i32* [[A]], align 4
19624 // CHECK20-NEXT:    store i16 0, i16* [[AA]], align 2
19625 // CHECK20-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
19626 // CHECK20-NEXT:    store i32 [[TMP0]], i32* [[A_CASTED]], align 4
19627 // CHECK20-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
19628 // CHECK20-NEXT:    [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
19629 // CHECK20-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
19630 // CHECK20-NEXT:    store i16 [[TMP2]], i16* [[CONV]], align 2
19631 // CHECK20-NEXT:    [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
19632 // CHECK20-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
19633 // CHECK20-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40
19634 // CHECK20-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
19635 // CHECK20:       omp_if.then:
19636 // CHECK20-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
19637 // CHECK20-NEXT:    [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i32*
19638 // CHECK20-NEXT:    store i32 [[TMP1]], i32* [[TMP6]], align 4
19639 // CHECK20-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
19640 // CHECK20-NEXT:    [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32*
19641 // CHECK20-NEXT:    store i32 [[TMP1]], i32* [[TMP8]], align 4
19642 // CHECK20-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
19643 // CHECK20-NEXT:    store i8* null, i8** [[TMP9]], align 4
19644 // CHECK20-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
19645 // CHECK20-NEXT:    [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i32*
19646 // CHECK20-NEXT:    store i32 [[TMP3]], i32* [[TMP11]], align 4
19647 // CHECK20-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
19648 // CHECK20-NEXT:    [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32*
19649 // CHECK20-NEXT:    store i32 [[TMP3]], i32* [[TMP13]], align 4
19650 // CHECK20-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
19651 // CHECK20-NEXT:    store i8* null, i8** [[TMP14]], align 4
19652 // CHECK20-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
19653 // CHECK20-NEXT:    [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]**
19654 // CHECK20-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 4
19655 // CHECK20-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
19656 // CHECK20-NEXT:    [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]**
19657 // CHECK20-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 4
19658 // CHECK20-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
19659 // CHECK20-NEXT:    store i8* null, i8** [[TMP19]], align 4
19660 // CHECK20-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
19661 // CHECK20-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
19662 // CHECK20-NEXT:    call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10)
19663 // CHECK20-NEXT:    [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.17, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.18, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
19664 // CHECK20-NEXT:    [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0
19665 // CHECK20-NEXT:    br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
19666 // CHECK20:       omp_offload.failed:
19667 // CHECK20-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]]
19668 // CHECK20-NEXT:    br label [[OMP_OFFLOAD_CONT]]
19669 // CHECK20:       omp_offload.cont:
19670 // CHECK20-NEXT:    br label [[OMP_IF_END:%.*]]
19671 // CHECK20:       omp_if.else:
19672 // CHECK20-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]]
19673 // CHECK20-NEXT:    br label [[OMP_IF_END]]
19674 // CHECK20:       omp_if.end:
19675 // CHECK20-NEXT:    [[TMP24:%.*]] = load i32, i32* [[A]], align 4
19676 // CHECK20-NEXT:    ret i32 [[TMP24]]
19677 //
19678 //
19679 // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218
19680 // CHECK20-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {
19681 // CHECK20-NEXT:  entry:
19682 // CHECK20-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
19683 // CHECK20-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
19684 // CHECK20-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
19685 // CHECK20-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
19686 // CHECK20-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 4
19687 // CHECK20-NEXT:    [[B_CASTED:%.*]] = alloca i32, align 4
19688 // CHECK20-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
19689 // CHECK20-NEXT:    store i32 [[B]], i32* [[B_ADDR]], align 4
19690 // CHECK20-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
19691 // CHECK20-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
19692 // CHECK20-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 4
19693 // CHECK20-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
19694 // CHECK20-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
19695 // CHECK20-NEXT:    [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
19696 // CHECK20-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
19697 // CHECK20-NEXT:    [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4
19698 // CHECK20-NEXT:    store i32 [[TMP4]], i32* [[B_CASTED]], align 4
19699 // CHECK20-NEXT:    [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4
19700 // CHECK20-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]])
19701 // CHECK20-NEXT:    ret void
19702 //
19703 //
19704 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..11
19705 // CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {
19706 // CHECK20-NEXT:  entry:
19707 // CHECK20-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
19708 // CHECK20-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
19709 // CHECK20-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
19710 // CHECK20-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
19711 // CHECK20-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
19712 // CHECK20-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
19713 // CHECK20-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 4
19714 // CHECK20-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
19715 // CHECK20-NEXT:    [[TMP:%.*]] = alloca i32, align 4
19716 // CHECK20-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
19717 // CHECK20-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
19718 // CHECK20-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
19719 // CHECK20-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
19720 // CHECK20-NEXT:    [[I:%.*]] = alloca i32, align 4
19721 // CHECK20-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
19722 // CHECK20-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
19723 // CHECK20-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
19724 // CHECK20-NEXT:    store i32 [[B]], i32* [[B_ADDR]], align 4
19725 // CHECK20-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
19726 // CHECK20-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
19727 // CHECK20-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 4
19728 // CHECK20-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
19729 // CHECK20-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
19730 // CHECK20-NEXT:    [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
19731 // CHECK20-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
19732 // CHECK20-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
19733 // CHECK20-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
19734 // CHECK20-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
19735 // CHECK20-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
19736 // CHECK20-NEXT:    [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
19737 // CHECK20-NEXT:    [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
19738 // CHECK20-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
19739 // CHECK20-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
19740 // CHECK20-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 9
19741 // CHECK20-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
19742 // CHECK20:       cond.true:
19743 // CHECK20-NEXT:    br label [[COND_END:%.*]]
19744 // CHECK20:       cond.false:
19745 // CHECK20-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
19746 // CHECK20-NEXT:    br label [[COND_END]]
19747 // CHECK20:       cond.end:
19748 // CHECK20-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
19749 // CHECK20-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
19750 // CHECK20-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
19751 // CHECK20-NEXT:    store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
19752 // CHECK20-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
19753 // CHECK20:       omp.inner.for.cond:
19754 // CHECK20-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
19755 // CHECK20-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
19756 // CHECK20-NEXT:    [[CMP3:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
19757 // CHECK20-NEXT:    br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
19758 // CHECK20:       omp.inner.for.body:
19759 // CHECK20-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
19760 // CHECK20-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
19761 // CHECK20-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
19762 // CHECK20-NEXT:    store i32 [[ADD]], i32* [[I]], align 4
19763 // CHECK20-NEXT:    [[TMP12:%.*]] = load i32, i32* [[B_ADDR]], align 4
19764 // CHECK20-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP12]] to double
19765 // CHECK20-NEXT:    [[ADD4:%.*]] = fadd double [[CONV]], 1.500000e+00
19766 // CHECK20-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
19767 // CHECK20-NEXT:    store double [[ADD4]], double* [[A]], align 4
19768 // CHECK20-NEXT:    [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
19769 // CHECK20-NEXT:    [[TMP13:%.*]] = load double, double* [[A5]], align 4
19770 // CHECK20-NEXT:    [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00
19771 // CHECK20-NEXT:    store double [[INC]], double* [[A5]], align 4
19772 // CHECK20-NEXT:    [[CONV6:%.*]] = fptosi double [[INC]] to i16
19773 // CHECK20-NEXT:    [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]]
19774 // CHECK20-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP14]]
19775 // CHECK20-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
19776 // CHECK20-NEXT:    store i16 [[CONV6]], i16* [[ARRAYIDX7]], align 2
19777 // CHECK20-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
19778 // CHECK20:       omp.body.continue:
19779 // CHECK20-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
19780 // CHECK20:       omp.inner.for.inc:
19781 // CHECK20-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
19782 // CHECK20-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP15]], 1
19783 // CHECK20-NEXT:    store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4
19784 // CHECK20-NEXT:    br label [[OMP_INNER_FOR_COND]]
19785 // CHECK20:       omp.inner.for.end:
19786 // CHECK20-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
19787 // CHECK20:       omp.loop.exit:
19788 // CHECK20-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
19789 // CHECK20-NEXT:    ret void
19790 //
19791 //
19792 // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200
19793 // CHECK20-SAME: (i32 [[N:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
19794 // CHECK20-NEXT:  entry:
19795 // CHECK20-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
19796 // CHECK20-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
19797 // CHECK20-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
19798 // CHECK20-NEXT:    [[AAA_ADDR:%.*]] = alloca i32, align 4
19799 // CHECK20-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
19800 // CHECK20-NEXT:    [[N_CASTED:%.*]] = alloca i32, align 4
19801 // CHECK20-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
19802 // CHECK20-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
19803 // CHECK20-NEXT:    [[AAA_CASTED:%.*]] = alloca i32, align 4
19804 // CHECK20-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
19805 // CHECK20-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
19806 // CHECK20-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
19807 // CHECK20-NEXT:    store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
19808 // CHECK20-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
19809 // CHECK20-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
19810 // CHECK20-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
19811 // CHECK20-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
19812 // CHECK20-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
19813 // CHECK20-NEXT:    store i32 [[TMP1]], i32* [[N_CASTED]], align 4
19814 // CHECK20-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_CASTED]], align 4
19815 // CHECK20-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4
19816 // CHECK20-NEXT:    store i32 [[TMP3]], i32* [[A_CASTED]], align 4
19817 // CHECK20-NEXT:    [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4
19818 // CHECK20-NEXT:    [[TMP5:%.*]] = load i16, i16* [[CONV]], align 4
19819 // CHECK20-NEXT:    [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
19820 // CHECK20-NEXT:    store i16 [[TMP5]], i16* [[CONV2]], align 2
19821 // CHECK20-NEXT:    [[TMP6:%.*]] = load i32, i32* [[AA_CASTED]], align 4
19822 // CHECK20-NEXT:    [[TMP7:%.*]] = load i8, i8* [[CONV1]], align 4
19823 // CHECK20-NEXT:    [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
19824 // CHECK20-NEXT:    store i8 [[TMP7]], i8* [[CONV3]], align 1
19825 // CHECK20-NEXT:    [[TMP8:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
19826 // CHECK20-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, [10 x i32]*)* @.omp_outlined..13 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP8]], [10 x i32]* [[TMP0]])
19827 // CHECK20-NEXT:    ret void
19828 //
19829 //
19830 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..13
19831 // CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
19832 // CHECK20-NEXT:  entry:
19833 // CHECK20-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
19834 // CHECK20-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
19835 // CHECK20-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
19836 // CHECK20-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
19837 // CHECK20-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
19838 // CHECK20-NEXT:    [[AAA_ADDR:%.*]] = alloca i32, align 4
19839 // CHECK20-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
19840 // CHECK20-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
19841 // CHECK20-NEXT:    [[TMP:%.*]] = alloca i32, align 4
19842 // CHECK20-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
19843 // CHECK20-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
19844 // CHECK20-NEXT:    [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4
19845 // CHECK20-NEXT:    [[I:%.*]] = alloca i32, align 4
19846 // CHECK20-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
19847 // CHECK20-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
19848 // CHECK20-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
19849 // CHECK20-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
19850 // CHECK20-NEXT:    [[I6:%.*]] = alloca i32, align 4
19851 // CHECK20-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
19852 // CHECK20-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
19853 // CHECK20-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
19854 // CHECK20-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
19855 // CHECK20-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
19856 // CHECK20-NEXT:    store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
19857 // CHECK20-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
19858 // CHECK20-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
19859 // CHECK20-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
19860 // CHECK20-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
19861 // CHECK20-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
19862 // CHECK20-NEXT:    store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
19863 // CHECK20-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
19864 // CHECK20-NEXT:    store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4
19865 // CHECK20-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
19866 // CHECK20-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
19867 // CHECK20-NEXT:    [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]]
19868 // CHECK20-NEXT:    [[SUB4:%.*]] = sub i32 [[SUB]], 1
19869 // CHECK20-NEXT:    [[ADD:%.*]] = add i32 [[SUB4]], 1
19870 // CHECK20-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], 1
19871 // CHECK20-NEXT:    [[SUB5:%.*]] = sub i32 [[DIV]], 1
19872 // CHECK20-NEXT:    store i32 [[SUB5]], i32* [[DOTCAPTURE_EXPR_3]], align 4
19873 // CHECK20-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
19874 // CHECK20-NEXT:    store i32 [[TMP5]], i32* [[I]], align 4
19875 // CHECK20-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
19876 // CHECK20-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
19877 // CHECK20-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]]
19878 // CHECK20-NEXT:    br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
19879 // CHECK20:       omp.precond.then:
19880 // CHECK20-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
19881 // CHECK20-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
19882 // CHECK20-NEXT:    store i32 [[TMP8]], i32* [[DOTOMP_UB]], align 4
19883 // CHECK20-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
19884 // CHECK20-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
19885 // CHECK20-NEXT:    [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
19886 // CHECK20-NEXT:    [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
19887 // CHECK20-NEXT:    call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
19888 // CHECK20-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
19889 // CHECK20-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
19890 // CHECK20-NEXT:    [[CMP7:%.*]] = icmp ugt i32 [[TMP11]], [[TMP12]]
19891 // CHECK20-NEXT:    br i1 [[CMP7]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
19892 // CHECK20:       cond.true:
19893 // CHECK20-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
19894 // CHECK20-NEXT:    br label [[COND_END:%.*]]
19895 // CHECK20:       cond.false:
19896 // CHECK20-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
19897 // CHECK20-NEXT:    br label [[COND_END]]
19898 // CHECK20:       cond.end:
19899 // CHECK20-NEXT:    [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ]
19900 // CHECK20-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
19901 // CHECK20-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
19902 // CHECK20-NEXT:    store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4
19903 // CHECK20-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
19904 // CHECK20:       omp.inner.for.cond:
19905 // CHECK20-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
19906 // CHECK20-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
19907 // CHECK20-NEXT:    [[ADD8:%.*]] = add i32 [[TMP17]], 1
19908 // CHECK20-NEXT:    [[CMP9:%.*]] = icmp ult i32 [[TMP16]], [[ADD8]]
19909 // CHECK20-NEXT:    br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
19910 // CHECK20:       omp.inner.for.body:
19911 // CHECK20-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
19912 // CHECK20-NEXT:    [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
19913 // CHECK20-NEXT:    [[MUL:%.*]] = mul i32 [[TMP19]], 1
19914 // CHECK20-NEXT:    [[ADD10:%.*]] = add i32 [[TMP18]], [[MUL]]
19915 // CHECK20-NEXT:    store i32 [[ADD10]], i32* [[I6]], align 4
19916 // CHECK20-NEXT:    [[TMP20:%.*]] = load i32, i32* [[A_ADDR]], align 4
19917 // CHECK20-NEXT:    [[ADD11:%.*]] = add nsw i32 [[TMP20]], 1
19918 // CHECK20-NEXT:    store i32 [[ADD11]], i32* [[A_ADDR]], align 4
19919 // CHECK20-NEXT:    [[TMP21:%.*]] = load i16, i16* [[CONV]], align 4
19920 // CHECK20-NEXT:    [[CONV12:%.*]] = sext i16 [[TMP21]] to i32
19921 // CHECK20-NEXT:    [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1
19922 // CHECK20-NEXT:    [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16
19923 // CHECK20-NEXT:    store i16 [[CONV14]], i16* [[CONV]], align 4
19924 // CHECK20-NEXT:    [[TMP22:%.*]] = load i8, i8* [[CONV1]], align 4
19925 // CHECK20-NEXT:    [[CONV15:%.*]] = sext i8 [[TMP22]] to i32
19926 // CHECK20-NEXT:    [[ADD16:%.*]] = add nsw i32 [[CONV15]], 1
19927 // CHECK20-NEXT:    [[CONV17:%.*]] = trunc i32 [[ADD16]] to i8
19928 // CHECK20-NEXT:    store i8 [[CONV17]], i8* [[CONV1]], align 4
19929 // CHECK20-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
19930 // CHECK20-NEXT:    [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
19931 // CHECK20-NEXT:    [[ADD18:%.*]] = add nsw i32 [[TMP23]], 1
19932 // CHECK20-NEXT:    store i32 [[ADD18]], i32* [[ARRAYIDX]], align 4
19933 // CHECK20-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
19934 // CHECK20:       omp.body.continue:
19935 // CHECK20-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
19936 // CHECK20:       omp.inner.for.inc:
19937 // CHECK20-NEXT:    [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
19938 // CHECK20-NEXT:    [[ADD19:%.*]] = add i32 [[TMP24]], 1
19939 // CHECK20-NEXT:    store i32 [[ADD19]], i32* [[DOTOMP_IV]], align 4
19940 // CHECK20-NEXT:    br label [[OMP_INNER_FOR_COND]]
19941 // CHECK20:       omp.inner.for.end:
19942 // CHECK20-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
19943 // CHECK20:       omp.loop.exit:
19944 // CHECK20-NEXT:    [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
19945 // CHECK20-NEXT:    [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4
19946 // CHECK20-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]])
19947 // CHECK20-NEXT:    br label [[OMP_PRECOND_END]]
19948 // CHECK20:       omp.precond.end:
19949 // CHECK20-NEXT:    ret void
19950 //
19951 //
19952 // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183
19953 // CHECK20-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
19954 // CHECK20-NEXT:  entry:
19955 // CHECK20-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
19956 // CHECK20-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
19957 // CHECK20-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
19958 // CHECK20-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
19959 // CHECK20-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
19960 // CHECK20-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
19961 // CHECK20-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
19962 // CHECK20-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
19963 // CHECK20-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
19964 // CHECK20-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
19965 // CHECK20-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
19966 // CHECK20-NEXT:    store i32 [[TMP1]], i32* [[A_CASTED]], align 4
19967 // CHECK20-NEXT:    [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
19968 // CHECK20-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
19969 // CHECK20-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
19970 // CHECK20-NEXT:    store i16 [[TMP3]], i16* [[CONV1]], align 2
19971 // CHECK20-NEXT:    [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
19972 // CHECK20-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]])
19973 // CHECK20-NEXT:    ret void
19974 //
19975 //
19976 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..16
19977 // CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
19978 // CHECK20-NEXT:  entry:
19979 // CHECK20-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
19980 // CHECK20-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
19981 // CHECK20-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
19982 // CHECK20-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
19983 // CHECK20-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
19984 // CHECK20-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
19985 // CHECK20-NEXT:    [[TMP:%.*]] = alloca i32, align 4
19986 // CHECK20-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
19987 // CHECK20-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
19988 // CHECK20-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
19989 // CHECK20-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
19990 // CHECK20-NEXT:    [[I:%.*]] = alloca i32, align 4
19991 // CHECK20-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
19992 // CHECK20-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
19993 // CHECK20-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
19994 // CHECK20-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
19995 // CHECK20-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
19996 // CHECK20-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
19997 // CHECK20-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
19998 // CHECK20-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
19999 // CHECK20-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
20000 // CHECK20-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
20001 // CHECK20-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
20002 // CHECK20-NEXT:    [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
20003 // CHECK20-NEXT:    [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
20004 // CHECK20-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
20005 // CHECK20-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
20006 // CHECK20-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9
20007 // CHECK20-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
20008 // CHECK20:       cond.true:
20009 // CHECK20-NEXT:    br label [[COND_END:%.*]]
20010 // CHECK20:       cond.false:
20011 // CHECK20-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
20012 // CHECK20-NEXT:    br label [[COND_END]]
20013 // CHECK20:       cond.end:
20014 // CHECK20-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
20015 // CHECK20-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
20016 // CHECK20-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
20017 // CHECK20-NEXT:    store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
20018 // CHECK20-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
20019 // CHECK20:       omp.inner.for.cond:
20020 // CHECK20-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
20021 // CHECK20-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
20022 // CHECK20-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
20023 // CHECK20-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
20024 // CHECK20:       omp.inner.for.body:
20025 // CHECK20-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
20026 // CHECK20-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
20027 // CHECK20-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
20028 // CHECK20-NEXT:    store i32 [[ADD]], i32* [[I]], align 4
20029 // CHECK20-NEXT:    [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4
20030 // CHECK20-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
20031 // CHECK20-NEXT:    store i32 [[ADD2]], i32* [[A_ADDR]], align 4
20032 // CHECK20-NEXT:    [[TMP10:%.*]] = load i16, i16* [[CONV]], align 4
20033 // CHECK20-NEXT:    [[CONV3:%.*]] = sext i16 [[TMP10]] to i32
20034 // CHECK20-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
20035 // CHECK20-NEXT:    [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
20036 // CHECK20-NEXT:    store i16 [[CONV5]], i16* [[CONV]], align 4
20037 // CHECK20-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
20038 // CHECK20-NEXT:    [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
20039 // CHECK20-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1
20040 // CHECK20-NEXT:    store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4
20041 // CHECK20-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
20042 // CHECK20:       omp.body.continue:
20043 // CHECK20-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
20044 // CHECK20:       omp.inner.for.inc:
20045 // CHECK20-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
20046 // CHECK20-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP12]], 1
20047 // CHECK20-NEXT:    store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4
20048 // CHECK20-NEXT:    br label [[OMP_INNER_FOR_COND]]
20049 // CHECK20:       omp.inner.for.end:
20050 // CHECK20-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
20051 // CHECK20:       omp.loop.exit:
20052 // CHECK20-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
20053 // CHECK20-NEXT:    ret void
20054 //
20055 //
20056 // CHECK20-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
20057 // CHECK20-SAME: () #[[ATTR4]] {
20058 // CHECK20-NEXT:  entry:
20059 // CHECK20-NEXT:    call void @__tgt_register_requires(i64 1)
20060 // CHECK20-NEXT:    ret void
20061 //
20062 //
20063 // CHECK21-LABEL: define {{[^@]+}}@_Z3fooi
20064 // CHECK21-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] {
20065 // CHECK21-NEXT:  entry:
20066 // CHECK21-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
20067 // CHECK21-NEXT:    [[A:%.*]] = alloca i32, align 4
20068 // CHECK21-NEXT:    [[AA:%.*]] = alloca i16, align 2
20069 // CHECK21-NEXT:    [[B:%.*]] = alloca [10 x float], align 4
20070 // CHECK21-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 8
20071 // CHECK21-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
20072 // CHECK21-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 8
20073 // CHECK21-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i64, align 8
20074 // CHECK21-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8
20075 // CHECK21-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
20076 // CHECK21-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
20077 // CHECK21-NEXT:    [[I:%.*]] = alloca i32, align 4
20078 // CHECK21-NEXT:    [[I3:%.*]] = alloca i32, align 4
20079 // CHECK21-NEXT:    [[I10:%.*]] = alloca i32, align 4
20080 // CHECK21-NEXT:    [[I19:%.*]] = alloca i32, align 4
20081 // CHECK21-NEXT:    [[DOTCAPTURE_EXPR_30:%.*]] = alloca i32, align 4
20082 // CHECK21-NEXT:    [[I31:%.*]] = alloca i32, align 4
20083 // CHECK21-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
20084 // CHECK21-NEXT:    store i32 0, i32* [[A]], align 4
20085 // CHECK21-NEXT:    store i16 0, i16* [[AA]], align 2
20086 // CHECK21-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
20087 // CHECK21-NEXT:    [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
20088 // CHECK21-NEXT:    [[TMP2:%.*]] = call i8* @llvm.stacksave()
20089 // CHECK21-NEXT:    store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8
20090 // CHECK21-NEXT:    [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4
20091 // CHECK21-NEXT:    store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8
20092 // CHECK21-NEXT:    [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
20093 // CHECK21-NEXT:    [[TMP4:%.*]] = zext i32 [[TMP3]] to i64
20094 // CHECK21-NEXT:    [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]]
20095 // CHECK21-NEXT:    [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8
20096 // CHECK21-NEXT:    store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8
20097 // CHECK21-NEXT:    [[TMP6:%.*]] = load i32, i32* [[A]], align 4
20098 // CHECK21-NEXT:    store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_]], align 4
20099 // CHECK21-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
20100 // CHECK21-NEXT:    store i32 [[TMP7]], i32* [[DOTCAPTURE_EXPR_2]], align 4
20101 // CHECK21-NEXT:    store i32 0, i32* [[I]], align 4
20102 // CHECK21-NEXT:    br label [[FOR_COND:%.*]]
20103 // CHECK21:       for.cond:
20104 // CHECK21-NEXT:    [[TMP8:%.*]] = load i32, i32* [[I]], align 4
20105 // CHECK21-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP8]], 10
20106 // CHECK21-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
20107 // CHECK21:       for.body:
20108 // CHECK21-NEXT:    br label [[FOR_INC:%.*]]
20109 // CHECK21:       for.inc:
20110 // CHECK21-NEXT:    [[TMP9:%.*]] = load i32, i32* [[I]], align 4
20111 // CHECK21-NEXT:    [[INC:%.*]] = add nsw i32 [[TMP9]], 1
20112 // CHECK21-NEXT:    store i32 [[INC]], i32* [[I]], align 4
20113 // CHECK21-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]]
20114 // CHECK21:       for.end:
20115 // CHECK21-NEXT:    store i32 0, i32* [[I3]], align 4
20116 // CHECK21-NEXT:    br label [[FOR_COND4:%.*]]
20117 // CHECK21:       for.cond4:
20118 // CHECK21-NEXT:    [[TMP10:%.*]] = load i32, i32* [[I3]], align 4
20119 // CHECK21-NEXT:    [[CMP5:%.*]] = icmp slt i32 [[TMP10]], 10
20120 // CHECK21-NEXT:    br i1 [[CMP5]], label [[FOR_BODY6:%.*]], label [[FOR_END9:%.*]]
20121 // CHECK21:       for.body6:
20122 // CHECK21-NEXT:    [[TMP11:%.*]] = load i32, i32* [[A]], align 4
20123 // CHECK21-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP11]], 1
20124 // CHECK21-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
20125 // CHECK21-NEXT:    br label [[FOR_INC7:%.*]]
20126 // CHECK21:       for.inc7:
20127 // CHECK21-NEXT:    [[TMP12:%.*]] = load i32, i32* [[I3]], align 4
20128 // CHECK21-NEXT:    [[INC8:%.*]] = add nsw i32 [[TMP12]], 1
20129 // CHECK21-NEXT:    store i32 [[INC8]], i32* [[I3]], align 4
20130 // CHECK21-NEXT:    br label [[FOR_COND4]], !llvm.loop [[LOOP4:![0-9]+]]
20131 // CHECK21:       for.end9:
20132 // CHECK21-NEXT:    store i32 0, i32* [[I10]], align 4
20133 // CHECK21-NEXT:    br label [[FOR_COND11:%.*]]
20134 // CHECK21:       for.cond11:
20135 // CHECK21-NEXT:    [[TMP13:%.*]] = load i32, i32* [[I10]], align 4
20136 // CHECK21-NEXT:    [[CMP12:%.*]] = icmp slt i32 [[TMP13]], 10
20137 // CHECK21-NEXT:    br i1 [[CMP12]], label [[FOR_BODY13:%.*]], label [[FOR_END18:%.*]]
20138 // CHECK21:       for.body13:
20139 // CHECK21-NEXT:    [[TMP14:%.*]] = load i16, i16* [[AA]], align 2
20140 // CHECK21-NEXT:    [[CONV:%.*]] = sext i16 [[TMP14]] to i32
20141 // CHECK21-NEXT:    [[ADD14:%.*]] = add nsw i32 [[CONV]], 1
20142 // CHECK21-NEXT:    [[CONV15:%.*]] = trunc i32 [[ADD14]] to i16
20143 // CHECK21-NEXT:    store i16 [[CONV15]], i16* [[AA]], align 2
20144 // CHECK21-NEXT:    br label [[FOR_INC16:%.*]]
20145 // CHECK21:       for.inc16:
20146 // CHECK21-NEXT:    [[TMP15:%.*]] = load i32, i32* [[I10]], align 4
20147 // CHECK21-NEXT:    [[INC17:%.*]] = add nsw i32 [[TMP15]], 1
20148 // CHECK21-NEXT:    store i32 [[INC17]], i32* [[I10]], align 4
20149 // CHECK21-NEXT:    br label [[FOR_COND11]], !llvm.loop [[LOOP5:![0-9]+]]
20150 // CHECK21:       for.end18:
20151 // CHECK21-NEXT:    store i32 0, i32* [[I19]], align 4
20152 // CHECK21-NEXT:    br label [[FOR_COND20:%.*]]
20153 // CHECK21:       for.cond20:
20154 // CHECK21-NEXT:    [[TMP16:%.*]] = load i32, i32* [[I19]], align 4
20155 // CHECK21-NEXT:    [[CMP21:%.*]] = icmp slt i32 [[TMP16]], 10
20156 // CHECK21-NEXT:    br i1 [[CMP21]], label [[FOR_BODY22:%.*]], label [[FOR_END29:%.*]]
20157 // CHECK21:       for.body22:
20158 // CHECK21-NEXT:    [[TMP17:%.*]] = load i32, i32* [[A]], align 4
20159 // CHECK21-NEXT:    [[ADD23:%.*]] = add nsw i32 [[TMP17]], 1
20160 // CHECK21-NEXT:    store i32 [[ADD23]], i32* [[A]], align 4
20161 // CHECK21-NEXT:    [[TMP18:%.*]] = load i16, i16* [[AA]], align 2
20162 // CHECK21-NEXT:    [[CONV24:%.*]] = sext i16 [[TMP18]] to i32
20163 // CHECK21-NEXT:    [[ADD25:%.*]] = add nsw i32 [[CONV24]], 1
20164 // CHECK21-NEXT:    [[CONV26:%.*]] = trunc i32 [[ADD25]] to i16
20165 // CHECK21-NEXT:    store i16 [[CONV26]], i16* [[AA]], align 2
20166 // CHECK21-NEXT:    br label [[FOR_INC27:%.*]]
20167 // CHECK21:       for.inc27:
20168 // CHECK21-NEXT:    [[TMP19:%.*]] = load i32, i32* [[I19]], align 4
20169 // CHECK21-NEXT:    [[INC28:%.*]] = add nsw i32 [[TMP19]], 1
20170 // CHECK21-NEXT:    store i32 [[INC28]], i32* [[I19]], align 4
20171 // CHECK21-NEXT:    br label [[FOR_COND20]], !llvm.loop [[LOOP6:![0-9]+]]
20172 // CHECK21:       for.end29:
20173 // CHECK21-NEXT:    [[TMP20:%.*]] = load i32, i32* [[N_ADDR]], align 4
20174 // CHECK21-NEXT:    store i32 [[TMP20]], i32* [[DOTCAPTURE_EXPR_30]], align 4
20175 // CHECK21-NEXT:    store i32 0, i32* [[I31]], align 4
20176 // CHECK21-NEXT:    br label [[FOR_COND32:%.*]]
20177 // CHECK21:       for.cond32:
20178 // CHECK21-NEXT:    [[TMP21:%.*]] = load i32, i32* [[I31]], align 4
20179 // CHECK21-NEXT:    [[CMP33:%.*]] = icmp slt i32 [[TMP21]], 10
20180 // CHECK21-NEXT:    br i1 [[CMP33]], label [[FOR_BODY34:%.*]], label [[FOR_END55:%.*]]
20181 // CHECK21:       for.body34:
20182 // CHECK21-NEXT:    [[TMP22:%.*]] = load i32, i32* [[A]], align 4
20183 // CHECK21-NEXT:    [[ADD35:%.*]] = add nsw i32 [[TMP22]], 1
20184 // CHECK21-NEXT:    store i32 [[ADD35]], i32* [[A]], align 4
20185 // CHECK21-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2
20186 // CHECK21-NEXT:    [[TMP23:%.*]] = load float, float* [[ARRAYIDX]], align 4
20187 // CHECK21-NEXT:    [[CONV36:%.*]] = fpext float [[TMP23]] to double
20188 // CHECK21-NEXT:    [[ADD37:%.*]] = fadd double [[CONV36]], 1.000000e+00
20189 // CHECK21-NEXT:    [[CONV38:%.*]] = fptrunc double [[ADD37]] to float
20190 // CHECK21-NEXT:    store float [[CONV38]], float* [[ARRAYIDX]], align 4
20191 // CHECK21-NEXT:    [[ARRAYIDX39:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3
20192 // CHECK21-NEXT:    [[TMP24:%.*]] = load float, float* [[ARRAYIDX39]], align 4
20193 // CHECK21-NEXT:    [[CONV40:%.*]] = fpext float [[TMP24]] to double
20194 // CHECK21-NEXT:    [[ADD41:%.*]] = fadd double [[CONV40]], 1.000000e+00
20195 // CHECK21-NEXT:    [[CONV42:%.*]] = fptrunc double [[ADD41]] to float
20196 // CHECK21-NEXT:    store float [[CONV42]], float* [[ARRAYIDX39]], align 4
20197 // CHECK21-NEXT:    [[ARRAYIDX43:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1
20198 // CHECK21-NEXT:    [[ARRAYIDX44:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX43]], i64 0, i64 2
20199 // CHECK21-NEXT:    [[TMP25:%.*]] = load double, double* [[ARRAYIDX44]], align 8
20200 // CHECK21-NEXT:    [[ADD45:%.*]] = fadd double [[TMP25]], 1.000000e+00
20201 // CHECK21-NEXT:    store double [[ADD45]], double* [[ARRAYIDX44]], align 8
20202 // CHECK21-NEXT:    [[TMP26:%.*]] = mul nsw i64 1, [[TMP4]]
20203 // CHECK21-NEXT:    [[ARRAYIDX46:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP26]]
20204 // CHECK21-NEXT:    [[ARRAYIDX47:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX46]], i64 3
20205 // CHECK21-NEXT:    [[TMP27:%.*]] = load double, double* [[ARRAYIDX47]], align 8
20206 // CHECK21-NEXT:    [[ADD48:%.*]] = fadd double [[TMP27]], 1.000000e+00
20207 // CHECK21-NEXT:    store double [[ADD48]], double* [[ARRAYIDX47]], align 8
20208 // CHECK21-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0
20209 // CHECK21-NEXT:    [[TMP28:%.*]] = load i64, i64* [[X]], align 8
20210 // CHECK21-NEXT:    [[ADD49:%.*]] = add nsw i64 [[TMP28]], 1
20211 // CHECK21-NEXT:    store i64 [[ADD49]], i64* [[X]], align 8
20212 // CHECK21-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1
20213 // CHECK21-NEXT:    [[TMP29:%.*]] = load i8, i8* [[Y]], align 8
20214 // CHECK21-NEXT:    [[CONV50:%.*]] = sext i8 [[TMP29]] to i32
20215 // CHECK21-NEXT:    [[ADD51:%.*]] = add nsw i32 [[CONV50]], 1
20216 // CHECK21-NEXT:    [[CONV52:%.*]] = trunc i32 [[ADD51]] to i8
20217 // CHECK21-NEXT:    store i8 [[CONV52]], i8* [[Y]], align 8
20218 // CHECK21-NEXT:    br label [[FOR_INC53:%.*]]
20219 // CHECK21:       for.inc53:
20220 // CHECK21-NEXT:    [[TMP30:%.*]] = load i32, i32* [[I31]], align 4
20221 // CHECK21-NEXT:    [[INC54:%.*]] = add nsw i32 [[TMP30]], 1
20222 // CHECK21-NEXT:    store i32 [[INC54]], i32* [[I31]], align 4
20223 // CHECK21-NEXT:    br label [[FOR_COND32]], !llvm.loop [[LOOP7:![0-9]+]]
20224 // CHECK21:       for.end55:
20225 // CHECK21-NEXT:    [[TMP31:%.*]] = load i32, i32* [[A]], align 4
20226 // CHECK21-NEXT:    [[TMP32:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
20227 // CHECK21-NEXT:    call void @llvm.stackrestore(i8* [[TMP32]])
20228 // CHECK21-NEXT:    ret i32 [[TMP31]]
20229 //
20230 //
20231 // CHECK21-LABEL: define {{[^@]+}}@_Z3bari
20232 // CHECK21-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
20233 // CHECK21-NEXT:  entry:
20234 // CHECK21-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
20235 // CHECK21-NEXT:    [[A:%.*]] = alloca i32, align 4
20236 // CHECK21-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8
20237 // CHECK21-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
20238 // CHECK21-NEXT:    store i32 0, i32* [[A]], align 4
20239 // CHECK21-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
20240 // CHECK21-NEXT:    [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]])
20241 // CHECK21-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
20242 // CHECK21-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
20243 // CHECK21-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
20244 // CHECK21-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
20245 // CHECK21-NEXT:    [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]])
20246 // CHECK21-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
20247 // CHECK21-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
20248 // CHECK21-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
20249 // CHECK21-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
20250 // CHECK21-NEXT:    [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]])
20251 // CHECK21-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
20252 // CHECK21-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
20253 // CHECK21-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
20254 // CHECK21-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
20255 // CHECK21-NEXT:    [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]])
20256 // CHECK21-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
20257 // CHECK21-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
20258 // CHECK21-NEXT:    store i32 [[ADD6]], i32* [[A]], align 4
20259 // CHECK21-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
20260 // CHECK21-NEXT:    ret i32 [[TMP8]]
20261 //
20262 //
20263 // CHECK21-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
20264 // CHECK21-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 {
20265 // CHECK21-NEXT:  entry:
20266 // CHECK21-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
20267 // CHECK21-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
20268 // CHECK21-NEXT:    [[B:%.*]] = alloca i32, align 4
20269 // CHECK21-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 8
20270 // CHECK21-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
20271 // CHECK21-NEXT:    [[I:%.*]] = alloca i32, align 4
20272 // CHECK21-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
20273 // CHECK21-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
20274 // CHECK21-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
20275 // CHECK21-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
20276 // CHECK21-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
20277 // CHECK21-NEXT:    store i32 [[ADD]], i32* [[B]], align 4
20278 // CHECK21-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
20279 // CHECK21-NEXT:    [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
20280 // CHECK21-NEXT:    [[TMP3:%.*]] = call i8* @llvm.stacksave()
20281 // CHECK21-NEXT:    store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8
20282 // CHECK21-NEXT:    [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]
20283 // CHECK21-NEXT:    [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2
20284 // CHECK21-NEXT:    store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8
20285 // CHECK21-NEXT:    store i32 0, i32* [[I]], align 4
20286 // CHECK21-NEXT:    br label [[FOR_COND:%.*]]
20287 // CHECK21:       for.cond:
20288 // CHECK21-NEXT:    [[TMP5:%.*]] = load i32, i32* [[I]], align 4
20289 // CHECK21-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP5]], 10
20290 // CHECK21-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
20291 // CHECK21:       for.body:
20292 // CHECK21-NEXT:    [[TMP6:%.*]] = load i32, i32* [[B]], align 4
20293 // CHECK21-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP6]] to double
20294 // CHECK21-NEXT:    [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00
20295 // CHECK21-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
20296 // CHECK21-NEXT:    store double [[ADD2]], double* [[A]], align 8
20297 // CHECK21-NEXT:    [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
20298 // CHECK21-NEXT:    [[TMP7:%.*]] = load double, double* [[A3]], align 8
20299 // CHECK21-NEXT:    [[INC:%.*]] = fadd double [[TMP7]], 1.000000e+00
20300 // CHECK21-NEXT:    store double [[INC]], double* [[A3]], align 8
20301 // CHECK21-NEXT:    [[CONV4:%.*]] = fptosi double [[INC]] to i16
20302 // CHECK21-NEXT:    [[TMP8:%.*]] = mul nsw i64 1, [[TMP2]]
20303 // CHECK21-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP8]]
20304 // CHECK21-NEXT:    [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
20305 // CHECK21-NEXT:    store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2
20306 // CHECK21-NEXT:    br label [[FOR_INC:%.*]]
20307 // CHECK21:       for.inc:
20308 // CHECK21-NEXT:    [[TMP9:%.*]] = load i32, i32* [[I]], align 4
20309 // CHECK21-NEXT:    [[INC6:%.*]] = add nsw i32 [[TMP9]], 1
20310 // CHECK21-NEXT:    store i32 [[INC6]], i32* [[I]], align 4
20311 // CHECK21-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]]
20312 // CHECK21:       for.end:
20313 // CHECK21-NEXT:    [[TMP10:%.*]] = mul nsw i64 1, [[TMP2]]
20314 // CHECK21-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP10]]
20315 // CHECK21-NEXT:    [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX7]], i64 1
20316 // CHECK21-NEXT:    [[TMP11:%.*]] = load i16, i16* [[ARRAYIDX8]], align 2
20317 // CHECK21-NEXT:    [[CONV9:%.*]] = sext i16 [[TMP11]] to i32
20318 // CHECK21-NEXT:    [[TMP12:%.*]] = load i32, i32* [[B]], align 4
20319 // CHECK21-NEXT:    [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[TMP12]]
20320 // CHECK21-NEXT:    [[TMP13:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
20321 // CHECK21-NEXT:    call void @llvm.stackrestore(i8* [[TMP13]])
20322 // CHECK21-NEXT:    ret i32 [[ADD10]]
20323 //
20324 //
20325 // CHECK21-LABEL: define {{[^@]+}}@_ZL7fstatici
20326 // CHECK21-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
20327 // CHECK21-NEXT:  entry:
20328 // CHECK21-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
20329 // CHECK21-NEXT:    [[A:%.*]] = alloca i32, align 4
20330 // CHECK21-NEXT:    [[AA:%.*]] = alloca i16, align 2
20331 // CHECK21-NEXT:    [[AAA:%.*]] = alloca i8, align 1
20332 // CHECK21-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
20333 // CHECK21-NEXT:    [[I:%.*]] = alloca i32, align 4
20334 // CHECK21-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
20335 // CHECK21-NEXT:    store i32 0, i32* [[A]], align 4
20336 // CHECK21-NEXT:    store i16 0, i16* [[AA]], align 2
20337 // CHECK21-NEXT:    store i8 0, i8* [[AAA]], align 1
20338 // CHECK21-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
20339 // CHECK21-NEXT:    store i32 [[TMP0]], i32* [[I]], align 4
20340 // CHECK21-NEXT:    br label [[FOR_COND:%.*]]
20341 // CHECK21:       for.cond:
20342 // CHECK21-NEXT:    [[TMP1:%.*]] = load i32, i32* [[I]], align 4
20343 // CHECK21-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
20344 // CHECK21-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP1]], [[TMP2]]
20345 // CHECK21-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
20346 // CHECK21:       for.body:
20347 // CHECK21-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
20348 // CHECK21-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP3]], 1
20349 // CHECK21-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
20350 // CHECK21-NEXT:    [[TMP4:%.*]] = load i16, i16* [[AA]], align 2
20351 // CHECK21-NEXT:    [[CONV:%.*]] = sext i16 [[TMP4]] to i32
20352 // CHECK21-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
20353 // CHECK21-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
20354 // CHECK21-NEXT:    store i16 [[CONV2]], i16* [[AA]], align 2
20355 // CHECK21-NEXT:    [[TMP5:%.*]] = load i8, i8* [[AAA]], align 1
20356 // CHECK21-NEXT:    [[CONV3:%.*]] = sext i8 [[TMP5]] to i32
20357 // CHECK21-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
20358 // CHECK21-NEXT:    [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8
20359 // CHECK21-NEXT:    store i8 [[CONV5]], i8* [[AAA]], align 1
20360 // CHECK21-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2
20361 // CHECK21-NEXT:    [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
20362 // CHECK21-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP6]], 1
20363 // CHECK21-NEXT:    store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4
20364 // CHECK21-NEXT:    br label [[FOR_INC:%.*]]
20365 // CHECK21:       for.inc:
20366 // CHECK21-NEXT:    [[TMP7:%.*]] = load i32, i32* [[I]], align 4
20367 // CHECK21-NEXT:    [[INC:%.*]] = add nsw i32 [[TMP7]], 1
20368 // CHECK21-NEXT:    store i32 [[INC]], i32* [[I]], align 4
20369 // CHECK21-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]
20370 // CHECK21:       for.end:
20371 // CHECK21-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
20372 // CHECK21-NEXT:    ret i32 [[TMP8]]
20373 //
20374 //
20375 // CHECK21-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
20376 // CHECK21-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat {
20377 // CHECK21-NEXT:  entry:
20378 // CHECK21-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
20379 // CHECK21-NEXT:    [[A:%.*]] = alloca i32, align 4
20380 // CHECK21-NEXT:    [[AA:%.*]] = alloca i16, align 2
20381 // CHECK21-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
20382 // CHECK21-NEXT:    [[I:%.*]] = alloca i32, align 4
20383 // CHECK21-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
20384 // CHECK21-NEXT:    store i32 0, i32* [[A]], align 4
20385 // CHECK21-NEXT:    store i16 0, i16* [[AA]], align 2
20386 // CHECK21-NEXT:    store i32 0, i32* [[I]], align 4
20387 // CHECK21-NEXT:    br label [[FOR_COND:%.*]]
20388 // CHECK21:       for.cond:
20389 // CHECK21-NEXT:    [[TMP0:%.*]] = load i32, i32* [[I]], align 4
20390 // CHECK21-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10
20391 // CHECK21-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
20392 // CHECK21:       for.body:
20393 // CHECK21-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
20394 // CHECK21-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
20395 // CHECK21-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
20396 // CHECK21-NEXT:    [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
20397 // CHECK21-NEXT:    [[CONV:%.*]] = sext i16 [[TMP2]] to i32
20398 // CHECK21-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
20399 // CHECK21-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
20400 // CHECK21-NEXT:    store i16 [[CONV2]], i16* [[AA]], align 2
20401 // CHECK21-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2
20402 // CHECK21-NEXT:    [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
20403 // CHECK21-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1
20404 // CHECK21-NEXT:    store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4
20405 // CHECK21-NEXT:    br label [[FOR_INC:%.*]]
20406 // CHECK21:       for.inc:
20407 // CHECK21-NEXT:    [[TMP4:%.*]] = load i32, i32* [[I]], align 4
20408 // CHECK21-NEXT:    [[INC:%.*]] = add nsw i32 [[TMP4]], 1
20409 // CHECK21-NEXT:    store i32 [[INC]], i32* [[I]], align 4
20410 // CHECK21-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]
20411 // CHECK21:       for.end:
20412 // CHECK21-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
20413 // CHECK21-NEXT:    ret i32 [[TMP5]]
20414 //
20415 //
20416 // CHECK22-LABEL: define {{[^@]+}}@_Z3fooi
20417 // CHECK22-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] {
20418 // CHECK22-NEXT:  entry:
20419 // CHECK22-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
20420 // CHECK22-NEXT:    [[A:%.*]] = alloca i32, align 4
20421 // CHECK22-NEXT:    [[AA:%.*]] = alloca i16, align 2
20422 // CHECK22-NEXT:    [[B:%.*]] = alloca [10 x float], align 4
20423 // CHECK22-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 8
20424 // CHECK22-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
20425 // CHECK22-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 8
20426 // CHECK22-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i64, align 8
20427 // CHECK22-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8
20428 // CHECK22-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
20429 // CHECK22-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
20430 // CHECK22-NEXT:    [[I:%.*]] = alloca i32, align 4
20431 // CHECK22-NEXT:    [[I3:%.*]] = alloca i32, align 4
20432 // CHECK22-NEXT:    [[I10:%.*]] = alloca i32, align 4
20433 // CHECK22-NEXT:    [[I19:%.*]] = alloca i32, align 4
20434 // CHECK22-NEXT:    [[DOTCAPTURE_EXPR_30:%.*]] = alloca i32, align 4
20435 // CHECK22-NEXT:    [[I31:%.*]] = alloca i32, align 4
20436 // CHECK22-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
20437 // CHECK22-NEXT:    store i32 0, i32* [[A]], align 4
20438 // CHECK22-NEXT:    store i16 0, i16* [[AA]], align 2
20439 // CHECK22-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
20440 // CHECK22-NEXT:    [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
20441 // CHECK22-NEXT:    [[TMP2:%.*]] = call i8* @llvm.stacksave()
20442 // CHECK22-NEXT:    store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8
20443 // CHECK22-NEXT:    [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4
20444 // CHECK22-NEXT:    store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8
20445 // CHECK22-NEXT:    [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
20446 // CHECK22-NEXT:    [[TMP4:%.*]] = zext i32 [[TMP3]] to i64
20447 // CHECK22-NEXT:    [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]]
20448 // CHECK22-NEXT:    [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8
20449 // CHECK22-NEXT:    store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8
20450 // CHECK22-NEXT:    [[TMP6:%.*]] = load i32, i32* [[A]], align 4
20451 // CHECK22-NEXT:    store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_]], align 4
20452 // CHECK22-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
20453 // CHECK22-NEXT:    store i32 [[TMP7]], i32* [[DOTCAPTURE_EXPR_2]], align 4
20454 // CHECK22-NEXT:    store i32 0, i32* [[I]], align 4
20455 // CHECK22-NEXT:    br label [[FOR_COND:%.*]]
20456 // CHECK22:       for.cond:
20457 // CHECK22-NEXT:    [[TMP8:%.*]] = load i32, i32* [[I]], align 4
20458 // CHECK22-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP8]], 10
20459 // CHECK22-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
20460 // CHECK22:       for.body:
20461 // CHECK22-NEXT:    br label [[FOR_INC:%.*]]
20462 // CHECK22:       for.inc:
20463 // CHECK22-NEXT:    [[TMP9:%.*]] = load i32, i32* [[I]], align 4
20464 // CHECK22-NEXT:    [[INC:%.*]] = add nsw i32 [[TMP9]], 1
20465 // CHECK22-NEXT:    store i32 [[INC]], i32* [[I]], align 4
20466 // CHECK22-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]]
20467 // CHECK22:       for.end:
20468 // CHECK22-NEXT:    store i32 0, i32* [[I3]], align 4
20469 // CHECK22-NEXT:    br label [[FOR_COND4:%.*]]
20470 // CHECK22:       for.cond4:
20471 // CHECK22-NEXT:    [[TMP10:%.*]] = load i32, i32* [[I3]], align 4
20472 // CHECK22-NEXT:    [[CMP5:%.*]] = icmp slt i32 [[TMP10]], 10
20473 // CHECK22-NEXT:    br i1 [[CMP5]], label [[FOR_BODY6:%.*]], label [[FOR_END9:%.*]]
20474 // CHECK22:       for.body6:
20475 // CHECK22-NEXT:    [[TMP11:%.*]] = load i32, i32* [[A]], align 4
20476 // CHECK22-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP11]], 1
20477 // CHECK22-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
20478 // CHECK22-NEXT:    br label [[FOR_INC7:%.*]]
20479 // CHECK22:       for.inc7:
20480 // CHECK22-NEXT:    [[TMP12:%.*]] = load i32, i32* [[I3]], align 4
20481 // CHECK22-NEXT:    [[INC8:%.*]] = add nsw i32 [[TMP12]], 1
20482 // CHECK22-NEXT:    store i32 [[INC8]], i32* [[I3]], align 4
20483 // CHECK22-NEXT:    br label [[FOR_COND4]], !llvm.loop [[LOOP4:![0-9]+]]
20484 // CHECK22:       for.end9:
20485 // CHECK22-NEXT:    store i32 0, i32* [[I10]], align 4
20486 // CHECK22-NEXT:    br label [[FOR_COND11:%.*]]
20487 // CHECK22:       for.cond11:
20488 // CHECK22-NEXT:    [[TMP13:%.*]] = load i32, i32* [[I10]], align 4
20489 // CHECK22-NEXT:    [[CMP12:%.*]] = icmp slt i32 [[TMP13]], 10
20490 // CHECK22-NEXT:    br i1 [[CMP12]], label [[FOR_BODY13:%.*]], label [[FOR_END18:%.*]]
20491 // CHECK22:       for.body13:
20492 // CHECK22-NEXT:    [[TMP14:%.*]] = load i16, i16* [[AA]], align 2
20493 // CHECK22-NEXT:    [[CONV:%.*]] = sext i16 [[TMP14]] to i32
20494 // CHECK22-NEXT:    [[ADD14:%.*]] = add nsw i32 [[CONV]], 1
20495 // CHECK22-NEXT:    [[CONV15:%.*]] = trunc i32 [[ADD14]] to i16
20496 // CHECK22-NEXT:    store i16 [[CONV15]], i16* [[AA]], align 2
20497 // CHECK22-NEXT:    br label [[FOR_INC16:%.*]]
20498 // CHECK22:       for.inc16:
20499 // CHECK22-NEXT:    [[TMP15:%.*]] = load i32, i32* [[I10]], align 4
20500 // CHECK22-NEXT:    [[INC17:%.*]] = add nsw i32 [[TMP15]], 1
20501 // CHECK22-NEXT:    store i32 [[INC17]], i32* [[I10]], align 4
20502 // CHECK22-NEXT:    br label [[FOR_COND11]], !llvm.loop [[LOOP5:![0-9]+]]
20503 // CHECK22:       for.end18:
20504 // CHECK22-NEXT:    store i32 0, i32* [[I19]], align 4
20505 // CHECK22-NEXT:    br label [[FOR_COND20:%.*]]
20506 // CHECK22:       for.cond20:
20507 // CHECK22-NEXT:    [[TMP16:%.*]] = load i32, i32* [[I19]], align 4
20508 // CHECK22-NEXT:    [[CMP21:%.*]] = icmp slt i32 [[TMP16]], 10
20509 // CHECK22-NEXT:    br i1 [[CMP21]], label [[FOR_BODY22:%.*]], label [[FOR_END29:%.*]]
20510 // CHECK22:       for.body22:
20511 // CHECK22-NEXT:    [[TMP17:%.*]] = load i32, i32* [[A]], align 4
20512 // CHECK22-NEXT:    [[ADD23:%.*]] = add nsw i32 [[TMP17]], 1
20513 // CHECK22-NEXT:    store i32 [[ADD23]], i32* [[A]], align 4
20514 // CHECK22-NEXT:    [[TMP18:%.*]] = load i16, i16* [[AA]], align 2
20515 // CHECK22-NEXT:    [[CONV24:%.*]] = sext i16 [[TMP18]] to i32
20516 // CHECK22-NEXT:    [[ADD25:%.*]] = add nsw i32 [[CONV24]], 1
20517 // CHECK22-NEXT:    [[CONV26:%.*]] = trunc i32 [[ADD25]] to i16
20518 // CHECK22-NEXT:    store i16 [[CONV26]], i16* [[AA]], align 2
20519 // CHECK22-NEXT:    br label [[FOR_INC27:%.*]]
20520 // CHECK22:       for.inc27:
20521 // CHECK22-NEXT:    [[TMP19:%.*]] = load i32, i32* [[I19]], align 4
20522 // CHECK22-NEXT:    [[INC28:%.*]] = add nsw i32 [[TMP19]], 1
20523 // CHECK22-NEXT:    store i32 [[INC28]], i32* [[I19]], align 4
20524 // CHECK22-NEXT:    br label [[FOR_COND20]], !llvm.loop [[LOOP6:![0-9]+]]
20525 // CHECK22:       for.end29:
20526 // CHECK22-NEXT:    [[TMP20:%.*]] = load i32, i32* [[N_ADDR]], align 4
20527 // CHECK22-NEXT:    store i32 [[TMP20]], i32* [[DOTCAPTURE_EXPR_30]], align 4
20528 // CHECK22-NEXT:    store i32 0, i32* [[I31]], align 4
20529 // CHECK22-NEXT:    br label [[FOR_COND32:%.*]]
20530 // CHECK22:       for.cond32:
20531 // CHECK22-NEXT:    [[TMP21:%.*]] = load i32, i32* [[I31]], align 4
20532 // CHECK22-NEXT:    [[CMP33:%.*]] = icmp slt i32 [[TMP21]], 10
20533 // CHECK22-NEXT:    br i1 [[CMP33]], label [[FOR_BODY34:%.*]], label [[FOR_END55:%.*]]
20534 // CHECK22:       for.body34:
20535 // CHECK22-NEXT:    [[TMP22:%.*]] = load i32, i32* [[A]], align 4
20536 // CHECK22-NEXT:    [[ADD35:%.*]] = add nsw i32 [[TMP22]], 1
20537 // CHECK22-NEXT:    store i32 [[ADD35]], i32* [[A]], align 4
20538 // CHECK22-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2
20539 // CHECK22-NEXT:    [[TMP23:%.*]] = load float, float* [[ARRAYIDX]], align 4
20540 // CHECK22-NEXT:    [[CONV36:%.*]] = fpext float [[TMP23]] to double
20541 // CHECK22-NEXT:    [[ADD37:%.*]] = fadd double [[CONV36]], 1.000000e+00
20542 // CHECK22-NEXT:    [[CONV38:%.*]] = fptrunc double [[ADD37]] to float
20543 // CHECK22-NEXT:    store float [[CONV38]], float* [[ARRAYIDX]], align 4
20544 // CHECK22-NEXT:    [[ARRAYIDX39:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3
20545 // CHECK22-NEXT:    [[TMP24:%.*]] = load float, float* [[ARRAYIDX39]], align 4
20546 // CHECK22-NEXT:    [[CONV40:%.*]] = fpext float [[TMP24]] to double
20547 // CHECK22-NEXT:    [[ADD41:%.*]] = fadd double [[CONV40]], 1.000000e+00
20548 // CHECK22-NEXT:    [[CONV42:%.*]] = fptrunc double [[ADD41]] to float
20549 // CHECK22-NEXT:    store float [[CONV42]], float* [[ARRAYIDX39]], align 4
20550 // CHECK22-NEXT:    [[ARRAYIDX43:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1
20551 // CHECK22-NEXT:    [[ARRAYIDX44:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX43]], i64 0, i64 2
20552 // CHECK22-NEXT:    [[TMP25:%.*]] = load double, double* [[ARRAYIDX44]], align 8
20553 // CHECK22-NEXT:    [[ADD45:%.*]] = fadd double [[TMP25]], 1.000000e+00
20554 // CHECK22-NEXT:    store double [[ADD45]], double* [[ARRAYIDX44]], align 8
20555 // CHECK22-NEXT:    [[TMP26:%.*]] = mul nsw i64 1, [[TMP4]]
20556 // CHECK22-NEXT:    [[ARRAYIDX46:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP26]]
20557 // CHECK22-NEXT:    [[ARRAYIDX47:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX46]], i64 3
20558 // CHECK22-NEXT:    [[TMP27:%.*]] = load double, double* [[ARRAYIDX47]], align 8
20559 // CHECK22-NEXT:    [[ADD48:%.*]] = fadd double [[TMP27]], 1.000000e+00
20560 // CHECK22-NEXT:    store double [[ADD48]], double* [[ARRAYIDX47]], align 8
20561 // CHECK22-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0
20562 // CHECK22-NEXT:    [[TMP28:%.*]] = load i64, i64* [[X]], align 8
20563 // CHECK22-NEXT:    [[ADD49:%.*]] = add nsw i64 [[TMP28]], 1
20564 // CHECK22-NEXT:    store i64 [[ADD49]], i64* [[X]], align 8
20565 // CHECK22-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1
20566 // CHECK22-NEXT:    [[TMP29:%.*]] = load i8, i8* [[Y]], align 8
20567 // CHECK22-NEXT:    [[CONV50:%.*]] = sext i8 [[TMP29]] to i32
20568 // CHECK22-NEXT:    [[ADD51:%.*]] = add nsw i32 [[CONV50]], 1
20569 // CHECK22-NEXT:    [[CONV52:%.*]] = trunc i32 [[ADD51]] to i8
20570 // CHECK22-NEXT:    store i8 [[CONV52]], i8* [[Y]], align 8
20571 // CHECK22-NEXT:    br label [[FOR_INC53:%.*]]
20572 // CHECK22:       for.inc53:
20573 // CHECK22-NEXT:    [[TMP30:%.*]] = load i32, i32* [[I31]], align 4
20574 // CHECK22-NEXT:    [[INC54:%.*]] = add nsw i32 [[TMP30]], 1
20575 // CHECK22-NEXT:    store i32 [[INC54]], i32* [[I31]], align 4
20576 // CHECK22-NEXT:    br label [[FOR_COND32]], !llvm.loop [[LOOP7:![0-9]+]]
20577 // CHECK22:       for.end55:
20578 // CHECK22-NEXT:    [[TMP31:%.*]] = load i32, i32* [[A]], align 4
20579 // CHECK22-NEXT:    [[TMP32:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
20580 // CHECK22-NEXT:    call void @llvm.stackrestore(i8* [[TMP32]])
20581 // CHECK22-NEXT:    ret i32 [[TMP31]]
20582 //
20583 //
20584 // CHECK22-LABEL: define {{[^@]+}}@_Z3bari
20585 // CHECK22-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
20586 // CHECK22-NEXT:  entry:
20587 // CHECK22-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
20588 // CHECK22-NEXT:    [[A:%.*]] = alloca i32, align 4
20589 // CHECK22-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8
20590 // CHECK22-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
20591 // CHECK22-NEXT:    store i32 0, i32* [[A]], align 4
20592 // CHECK22-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
20593 // CHECK22-NEXT:    [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]])
20594 // CHECK22-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
20595 // CHECK22-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
20596 // CHECK22-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
20597 // CHECK22-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
20598 // CHECK22-NEXT:    [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]])
20599 // CHECK22-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
20600 // CHECK22-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
20601 // CHECK22-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
20602 // CHECK22-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
20603 // CHECK22-NEXT:    [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]])
20604 // CHECK22-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
20605 // CHECK22-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
20606 // CHECK22-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
20607 // CHECK22-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
20608 // CHECK22-NEXT:    [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]])
20609 // CHECK22-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
20610 // CHECK22-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
20611 // CHECK22-NEXT:    store i32 [[ADD6]], i32* [[A]], align 4
20612 // CHECK22-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
20613 // CHECK22-NEXT:    ret i32 [[TMP8]]
20614 //
20615 //
20616 // CHECK22-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
20617 // CHECK22-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 {
20618 // CHECK22-NEXT:  entry:
20619 // CHECK22-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
20620 // CHECK22-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
20621 // CHECK22-NEXT:    [[B:%.*]] = alloca i32, align 4
20622 // CHECK22-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 8
20623 // CHECK22-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
20624 // CHECK22-NEXT:    [[I:%.*]] = alloca i32, align 4
20625 // CHECK22-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
20626 // CHECK22-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
20627 // CHECK22-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
20628 // CHECK22-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
20629 // CHECK22-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
20630 // CHECK22-NEXT:    store i32 [[ADD]], i32* [[B]], align 4
20631 // CHECK22-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
20632 // CHECK22-NEXT:    [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
20633 // CHECK22-NEXT:    [[TMP3:%.*]] = call i8* @llvm.stacksave()
20634 // CHECK22-NEXT:    store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8
20635 // CHECK22-NEXT:    [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]
20636 // CHECK22-NEXT:    [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2
20637 // CHECK22-NEXT:    store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8
20638 // CHECK22-NEXT:    store i32 0, i32* [[I]], align 4
20639 // CHECK22-NEXT:    br label [[FOR_COND:%.*]]
20640 // CHECK22:       for.cond:
20641 // CHECK22-NEXT:    [[TMP5:%.*]] = load i32, i32* [[I]], align 4
20642 // CHECK22-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP5]], 10
20643 // CHECK22-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
20644 // CHECK22:       for.body:
20645 // CHECK22-NEXT:    [[TMP6:%.*]] = load i32, i32* [[B]], align 4
20646 // CHECK22-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP6]] to double
20647 // CHECK22-NEXT:    [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00
20648 // CHECK22-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
20649 // CHECK22-NEXT:    store double [[ADD2]], double* [[A]], align 8
20650 // CHECK22-NEXT:    [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
20651 // CHECK22-NEXT:    [[TMP7:%.*]] = load double, double* [[A3]], align 8
20652 // CHECK22-NEXT:    [[INC:%.*]] = fadd double [[TMP7]], 1.000000e+00
20653 // CHECK22-NEXT:    store double [[INC]], double* [[A3]], align 8
20654 // CHECK22-NEXT:    [[CONV4:%.*]] = fptosi double [[INC]] to i16
20655 // CHECK22-NEXT:    [[TMP8:%.*]] = mul nsw i64 1, [[TMP2]]
20656 // CHECK22-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP8]]
20657 // CHECK22-NEXT:    [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
20658 // CHECK22-NEXT:    store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2
20659 // CHECK22-NEXT:    br label [[FOR_INC:%.*]]
20660 // CHECK22:       for.inc:
20661 // CHECK22-NEXT:    [[TMP9:%.*]] = load i32, i32* [[I]], align 4
20662 // CHECK22-NEXT:    [[INC6:%.*]] = add nsw i32 [[TMP9]], 1
20663 // CHECK22-NEXT:    store i32 [[INC6]], i32* [[I]], align 4
20664 // CHECK22-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]]
20665 // CHECK22:       for.end:
20666 // CHECK22-NEXT:    [[TMP10:%.*]] = mul nsw i64 1, [[TMP2]]
20667 // CHECK22-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP10]]
20668 // CHECK22-NEXT:    [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX7]], i64 1
20669 // CHECK22-NEXT:    [[TMP11:%.*]] = load i16, i16* [[ARRAYIDX8]], align 2
20670 // CHECK22-NEXT:    [[CONV9:%.*]] = sext i16 [[TMP11]] to i32
20671 // CHECK22-NEXT:    [[TMP12:%.*]] = load i32, i32* [[B]], align 4
20672 // CHECK22-NEXT:    [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[TMP12]]
20673 // CHECK22-NEXT:    [[TMP13:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
20674 // CHECK22-NEXT:    call void @llvm.stackrestore(i8* [[TMP13]])
20675 // CHECK22-NEXT:    ret i32 [[ADD10]]
20676 //
20677 //
20678 // CHECK22-LABEL: define {{[^@]+}}@_ZL7fstatici
20679 // CHECK22-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
20680 // CHECK22-NEXT:  entry:
20681 // CHECK22-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
20682 // CHECK22-NEXT:    [[A:%.*]] = alloca i32, align 4
20683 // CHECK22-NEXT:    [[AA:%.*]] = alloca i16, align 2
20684 // CHECK22-NEXT:    [[AAA:%.*]] = alloca i8, align 1
20685 // CHECK22-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
20686 // CHECK22-NEXT:    [[I:%.*]] = alloca i32, align 4
20687 // CHECK22-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
20688 // CHECK22-NEXT:    store i32 0, i32* [[A]], align 4
20689 // CHECK22-NEXT:    store i16 0, i16* [[AA]], align 2
20690 // CHECK22-NEXT:    store i8 0, i8* [[AAA]], align 1
20691 // CHECK22-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
20692 // CHECK22-NEXT:    store i32 [[TMP0]], i32* [[I]], align 4
20693 // CHECK22-NEXT:    br label [[FOR_COND:%.*]]
20694 // CHECK22:       for.cond:
20695 // CHECK22-NEXT:    [[TMP1:%.*]] = load i32, i32* [[I]], align 4
20696 // CHECK22-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
20697 // CHECK22-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP1]], [[TMP2]]
20698 // CHECK22-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
20699 // CHECK22:       for.body:
20700 // CHECK22-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
20701 // CHECK22-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP3]], 1
20702 // CHECK22-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
20703 // CHECK22-NEXT:    [[TMP4:%.*]] = load i16, i16* [[AA]], align 2
20704 // CHECK22-NEXT:    [[CONV:%.*]] = sext i16 [[TMP4]] to i32
20705 // CHECK22-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
20706 // CHECK22-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
20707 // CHECK22-NEXT:    store i16 [[CONV2]], i16* [[AA]], align 2
20708 // CHECK22-NEXT:    [[TMP5:%.*]] = load i8, i8* [[AAA]], align 1
20709 // CHECK22-NEXT:    [[CONV3:%.*]] = sext i8 [[TMP5]] to i32
20710 // CHECK22-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
20711 // CHECK22-NEXT:    [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8
20712 // CHECK22-NEXT:    store i8 [[CONV5]], i8* [[AAA]], align 1
20713 // CHECK22-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2
20714 // CHECK22-NEXT:    [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
20715 // CHECK22-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP6]], 1
20716 // CHECK22-NEXT:    store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4
20717 // CHECK22-NEXT:    br label [[FOR_INC:%.*]]
20718 // CHECK22:       for.inc:
20719 // CHECK22-NEXT:    [[TMP7:%.*]] = load i32, i32* [[I]], align 4
20720 // CHECK22-NEXT:    [[INC:%.*]] = add nsw i32 [[TMP7]], 1
20721 // CHECK22-NEXT:    store i32 [[INC]], i32* [[I]], align 4
20722 // CHECK22-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]
20723 // CHECK22:       for.end:
20724 // CHECK22-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
20725 // CHECK22-NEXT:    ret i32 [[TMP8]]
20726 //
20727 //
20728 // CHECK22-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
20729 // CHECK22-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat {
20730 // CHECK22-NEXT:  entry:
20731 // CHECK22-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
20732 // CHECK22-NEXT:    [[A:%.*]] = alloca i32, align 4
20733 // CHECK22-NEXT:    [[AA:%.*]] = alloca i16, align 2
20734 // CHECK22-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
20735 // CHECK22-NEXT:    [[I:%.*]] = alloca i32, align 4
20736 // CHECK22-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
20737 // CHECK22-NEXT:    store i32 0, i32* [[A]], align 4
20738 // CHECK22-NEXT:    store i16 0, i16* [[AA]], align 2
20739 // CHECK22-NEXT:    store i32 0, i32* [[I]], align 4
20740 // CHECK22-NEXT:    br label [[FOR_COND:%.*]]
20741 // CHECK22:       for.cond:
20742 // CHECK22-NEXT:    [[TMP0:%.*]] = load i32, i32* [[I]], align 4
20743 // CHECK22-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10
20744 // CHECK22-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
20745 // CHECK22:       for.body:
20746 // CHECK22-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
20747 // CHECK22-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
20748 // CHECK22-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
20749 // CHECK22-NEXT:    [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
20750 // CHECK22-NEXT:    [[CONV:%.*]] = sext i16 [[TMP2]] to i32
20751 // CHECK22-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
20752 // CHECK22-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
20753 // CHECK22-NEXT:    store i16 [[CONV2]], i16* [[AA]], align 2
20754 // CHECK22-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2
20755 // CHECK22-NEXT:    [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
20756 // CHECK22-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1
20757 // CHECK22-NEXT:    store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4
20758 // CHECK22-NEXT:    br label [[FOR_INC:%.*]]
20759 // CHECK22:       for.inc:
20760 // CHECK22-NEXT:    [[TMP4:%.*]] = load i32, i32* [[I]], align 4
20761 // CHECK22-NEXT:    [[INC:%.*]] = add nsw i32 [[TMP4]], 1
20762 // CHECK22-NEXT:    store i32 [[INC]], i32* [[I]], align 4
20763 // CHECK22-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]
20764 // CHECK22:       for.end:
20765 // CHECK22-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
20766 // CHECK22-NEXT:    ret i32 [[TMP5]]
20767 //
20768 //
20769 // CHECK23-LABEL: define {{[^@]+}}@_Z3fooi
20770 // CHECK23-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] {
20771 // CHECK23-NEXT:  entry:
20772 // CHECK23-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
20773 // CHECK23-NEXT:    [[A:%.*]] = alloca i32, align 4
20774 // CHECK23-NEXT:    [[AA:%.*]] = alloca i16, align 2
20775 // CHECK23-NEXT:    [[B:%.*]] = alloca [10 x float], align 4
20776 // CHECK23-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 4
20777 // CHECK23-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 4
20778 // CHECK23-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 8
20779 // CHECK23-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i32, align 4
20780 // CHECK23-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4
20781 // CHECK23-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
20782 // CHECK23-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
20783 // CHECK23-NEXT:    [[I:%.*]] = alloca i32, align 4
20784 // CHECK23-NEXT:    [[I3:%.*]] = alloca i32, align 4
20785 // CHECK23-NEXT:    [[I10:%.*]] = alloca i32, align 4
20786 // CHECK23-NEXT:    [[I19:%.*]] = alloca i32, align 4
20787 // CHECK23-NEXT:    [[DOTCAPTURE_EXPR_30:%.*]] = alloca i32, align 4
20788 // CHECK23-NEXT:    [[I31:%.*]] = alloca i32, align 4
20789 // CHECK23-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
20790 // CHECK23-NEXT:    store i32 0, i32* [[A]], align 4
20791 // CHECK23-NEXT:    store i16 0, i16* [[AA]], align 2
20792 // CHECK23-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
20793 // CHECK23-NEXT:    [[TMP1:%.*]] = call i8* @llvm.stacksave()
20794 // CHECK23-NEXT:    store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4
20795 // CHECK23-NEXT:    [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4
20796 // CHECK23-NEXT:    store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4
20797 // CHECK23-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
20798 // CHECK23-NEXT:    [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]]
20799 // CHECK23-NEXT:    [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8
20800 // CHECK23-NEXT:    store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4
20801 // CHECK23-NEXT:    [[TMP4:%.*]] = load i32, i32* [[A]], align 4
20802 // CHECK23-NEXT:    store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4
20803 // CHECK23-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
20804 // CHECK23-NEXT:    store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_2]], align 4
20805 // CHECK23-NEXT:    store i32 0, i32* [[I]], align 4
20806 // CHECK23-NEXT:    br label [[FOR_COND:%.*]]
20807 // CHECK23:       for.cond:
20808 // CHECK23-NEXT:    [[TMP6:%.*]] = load i32, i32* [[I]], align 4
20809 // CHECK23-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP6]], 10
20810 // CHECK23-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
20811 // CHECK23:       for.body:
20812 // CHECK23-NEXT:    br label [[FOR_INC:%.*]]
20813 // CHECK23:       for.inc:
20814 // CHECK23-NEXT:    [[TMP7:%.*]] = load i32, i32* [[I]], align 4
20815 // CHECK23-NEXT:    [[INC:%.*]] = add nsw i32 [[TMP7]], 1
20816 // CHECK23-NEXT:    store i32 [[INC]], i32* [[I]], align 4
20817 // CHECK23-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]
20818 // CHECK23:       for.end:
20819 // CHECK23-NEXT:    store i32 0, i32* [[I3]], align 4
20820 // CHECK23-NEXT:    br label [[FOR_COND4:%.*]]
20821 // CHECK23:       for.cond4:
20822 // CHECK23-NEXT:    [[TMP8:%.*]] = load i32, i32* [[I3]], align 4
20823 // CHECK23-NEXT:    [[CMP5:%.*]] = icmp slt i32 [[TMP8]], 10
20824 // CHECK23-NEXT:    br i1 [[CMP5]], label [[FOR_BODY6:%.*]], label [[FOR_END9:%.*]]
20825 // CHECK23:       for.body6:
20826 // CHECK23-NEXT:    [[TMP9:%.*]] = load i32, i32* [[A]], align 4
20827 // CHECK23-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP9]], 1
20828 // CHECK23-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
20829 // CHECK23-NEXT:    br label [[FOR_INC7:%.*]]
20830 // CHECK23:       for.inc7:
20831 // CHECK23-NEXT:    [[TMP10:%.*]] = load i32, i32* [[I3]], align 4
20832 // CHECK23-NEXT:    [[INC8:%.*]] = add nsw i32 [[TMP10]], 1
20833 // CHECK23-NEXT:    store i32 [[INC8]], i32* [[I3]], align 4
20834 // CHECK23-NEXT:    br label [[FOR_COND4]], !llvm.loop [[LOOP5:![0-9]+]]
20835 // CHECK23:       for.end9:
20836 // CHECK23-NEXT:    store i32 0, i32* [[I10]], align 4
20837 // CHECK23-NEXT:    br label [[FOR_COND11:%.*]]
20838 // CHECK23:       for.cond11:
20839 // CHECK23-NEXT:    [[TMP11:%.*]] = load i32, i32* [[I10]], align 4
20840 // CHECK23-NEXT:    [[CMP12:%.*]] = icmp slt i32 [[TMP11]], 10
20841 // CHECK23-NEXT:    br i1 [[CMP12]], label [[FOR_BODY13:%.*]], label [[FOR_END18:%.*]]
20842 // CHECK23:       for.body13:
20843 // CHECK23-NEXT:    [[TMP12:%.*]] = load i16, i16* [[AA]], align 2
20844 // CHECK23-NEXT:    [[CONV:%.*]] = sext i16 [[TMP12]] to i32
20845 // CHECK23-NEXT:    [[ADD14:%.*]] = add nsw i32 [[CONV]], 1
20846 // CHECK23-NEXT:    [[CONV15:%.*]] = trunc i32 [[ADD14]] to i16
20847 // CHECK23-NEXT:    store i16 [[CONV15]], i16* [[AA]], align 2
20848 // CHECK23-NEXT:    br label [[FOR_INC16:%.*]]
20849 // CHECK23:       for.inc16:
20850 // CHECK23-NEXT:    [[TMP13:%.*]] = load i32, i32* [[I10]], align 4
20851 // CHECK23-NEXT:    [[INC17:%.*]] = add nsw i32 [[TMP13]], 1
20852 // CHECK23-NEXT:    store i32 [[INC17]], i32* [[I10]], align 4
20853 // CHECK23-NEXT:    br label [[FOR_COND11]], !llvm.loop [[LOOP6:![0-9]+]]
20854 // CHECK23:       for.end18:
20855 // CHECK23-NEXT:    store i32 0, i32* [[I19]], align 4
20856 // CHECK23-NEXT:    br label [[FOR_COND20:%.*]]
20857 // CHECK23:       for.cond20:
20858 // CHECK23-NEXT:    [[TMP14:%.*]] = load i32, i32* [[I19]], align 4
20859 // CHECK23-NEXT:    [[CMP21:%.*]] = icmp slt i32 [[TMP14]], 10
20860 // CHECK23-NEXT:    br i1 [[CMP21]], label [[FOR_BODY22:%.*]], label [[FOR_END29:%.*]]
20861 // CHECK23:       for.body22:
20862 // CHECK23-NEXT:    [[TMP15:%.*]] = load i32, i32* [[A]], align 4
20863 // CHECK23-NEXT:    [[ADD23:%.*]] = add nsw i32 [[TMP15]], 1
20864 // CHECK23-NEXT:    store i32 [[ADD23]], i32* [[A]], align 4
20865 // CHECK23-NEXT:    [[TMP16:%.*]] = load i16, i16* [[AA]], align 2
20866 // CHECK23-NEXT:    [[CONV24:%.*]] = sext i16 [[TMP16]] to i32
20867 // CHECK23-NEXT:    [[ADD25:%.*]] = add nsw i32 [[CONV24]], 1
20868 // CHECK23-NEXT:    [[CONV26:%.*]] = trunc i32 [[ADD25]] to i16
20869 // CHECK23-NEXT:    store i16 [[CONV26]], i16* [[AA]], align 2
20870 // CHECK23-NEXT:    br label [[FOR_INC27:%.*]]
20871 // CHECK23:       for.inc27:
20872 // CHECK23-NEXT:    [[TMP17:%.*]] = load i32, i32* [[I19]], align 4
20873 // CHECK23-NEXT:    [[INC28:%.*]] = add nsw i32 [[TMP17]], 1
20874 // CHECK23-NEXT:    store i32 [[INC28]], i32* [[I19]], align 4
20875 // CHECK23-NEXT:    br label [[FOR_COND20]], !llvm.loop [[LOOP7:![0-9]+]]
20876 // CHECK23:       for.end29:
20877 // CHECK23-NEXT:    [[TMP18:%.*]] = load i32, i32* [[N_ADDR]], align 4
20878 // CHECK23-NEXT:    store i32 [[TMP18]], i32* [[DOTCAPTURE_EXPR_30]], align 4
20879 // CHECK23-NEXT:    store i32 0, i32* [[I31]], align 4
20880 // CHECK23-NEXT:    br label [[FOR_COND32:%.*]]
20881 // CHECK23:       for.cond32:
20882 // CHECK23-NEXT:    [[TMP19:%.*]] = load i32, i32* [[I31]], align 4
20883 // CHECK23-NEXT:    [[CMP33:%.*]] = icmp slt i32 [[TMP19]], 10
20884 // CHECK23-NEXT:    br i1 [[CMP33]], label [[FOR_BODY34:%.*]], label [[FOR_END55:%.*]]
20885 // CHECK23:       for.body34:
20886 // CHECK23-NEXT:    [[TMP20:%.*]] = load i32, i32* [[A]], align 4
20887 // CHECK23-NEXT:    [[ADD35:%.*]] = add nsw i32 [[TMP20]], 1
20888 // CHECK23-NEXT:    store i32 [[ADD35]], i32* [[A]], align 4
20889 // CHECK23-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2
20890 // CHECK23-NEXT:    [[TMP21:%.*]] = load float, float* [[ARRAYIDX]], align 4
20891 // CHECK23-NEXT:    [[CONV36:%.*]] = fpext float [[TMP21]] to double
20892 // CHECK23-NEXT:    [[ADD37:%.*]] = fadd double [[CONV36]], 1.000000e+00
20893 // CHECK23-NEXT:    [[CONV38:%.*]] = fptrunc double [[ADD37]] to float
20894 // CHECK23-NEXT:    store float [[CONV38]], float* [[ARRAYIDX]], align 4
20895 // CHECK23-NEXT:    [[ARRAYIDX39:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3
20896 // CHECK23-NEXT:    [[TMP22:%.*]] = load float, float* [[ARRAYIDX39]], align 4
20897 // CHECK23-NEXT:    [[CONV40:%.*]] = fpext float [[TMP22]] to double
20898 // CHECK23-NEXT:    [[ADD41:%.*]] = fadd double [[CONV40]], 1.000000e+00
20899 // CHECK23-NEXT:    [[CONV42:%.*]] = fptrunc double [[ADD41]] to float
20900 // CHECK23-NEXT:    store float [[CONV42]], float* [[ARRAYIDX39]], align 4
20901 // CHECK23-NEXT:    [[ARRAYIDX43:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1
20902 // CHECK23-NEXT:    [[ARRAYIDX44:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX43]], i32 0, i32 2
20903 // CHECK23-NEXT:    [[TMP23:%.*]] = load double, double* [[ARRAYIDX44]], align 8
20904 // CHECK23-NEXT:    [[ADD45:%.*]] = fadd double [[TMP23]], 1.000000e+00
20905 // CHECK23-NEXT:    store double [[ADD45]], double* [[ARRAYIDX44]], align 8
20906 // CHECK23-NEXT:    [[TMP24:%.*]] = mul nsw i32 1, [[TMP2]]
20907 // CHECK23-NEXT:    [[ARRAYIDX46:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP24]]
20908 // CHECK23-NEXT:    [[ARRAYIDX47:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX46]], i32 3
20909 // CHECK23-NEXT:    [[TMP25:%.*]] = load double, double* [[ARRAYIDX47]], align 8
20910 // CHECK23-NEXT:    [[ADD48:%.*]] = fadd double [[TMP25]], 1.000000e+00
20911 // CHECK23-NEXT:    store double [[ADD48]], double* [[ARRAYIDX47]], align 8
20912 // CHECK23-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0
20913 // CHECK23-NEXT:    [[TMP26:%.*]] = load i64, i64* [[X]], align 4
20914 // CHECK23-NEXT:    [[ADD49:%.*]] = add nsw i64 [[TMP26]], 1
20915 // CHECK23-NEXT:    store i64 [[ADD49]], i64* [[X]], align 4
20916 // CHECK23-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1
20917 // CHECK23-NEXT:    [[TMP27:%.*]] = load i8, i8* [[Y]], align 4
20918 // CHECK23-NEXT:    [[CONV50:%.*]] = sext i8 [[TMP27]] to i32
20919 // CHECK23-NEXT:    [[ADD51:%.*]] = add nsw i32 [[CONV50]], 1
20920 // CHECK23-NEXT:    [[CONV52:%.*]] = trunc i32 [[ADD51]] to i8
20921 // CHECK23-NEXT:    store i8 [[CONV52]], i8* [[Y]], align 4
20922 // CHECK23-NEXT:    br label [[FOR_INC53:%.*]]
20923 // CHECK23:       for.inc53:
20924 // CHECK23-NEXT:    [[TMP28:%.*]] = load i32, i32* [[I31]], align 4
20925 // CHECK23-NEXT:    [[INC54:%.*]] = add nsw i32 [[TMP28]], 1
20926 // CHECK23-NEXT:    store i32 [[INC54]], i32* [[I31]], align 4
20927 // CHECK23-NEXT:    br label [[FOR_COND32]], !llvm.loop [[LOOP8:![0-9]+]]
20928 // CHECK23:       for.end55:
20929 // CHECK23-NEXT:    [[TMP29:%.*]] = load i32, i32* [[A]], align 4
20930 // CHECK23-NEXT:    [[TMP30:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
20931 // CHECK23-NEXT:    call void @llvm.stackrestore(i8* [[TMP30]])
20932 // CHECK23-NEXT:    ret i32 [[TMP29]]
20933 //
20934 //
20935 // CHECK23-LABEL: define {{[^@]+}}@_Z3bari
20936 // CHECK23-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
20937 // CHECK23-NEXT:  entry:
20938 // CHECK23-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
20939 // CHECK23-NEXT:    [[A:%.*]] = alloca i32, align 4
20940 // CHECK23-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4
20941 // CHECK23-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
20942 // CHECK23-NEXT:    store i32 0, i32* [[A]], align 4
20943 // CHECK23-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
20944 // CHECK23-NEXT:    [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]])
20945 // CHECK23-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
20946 // CHECK23-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
20947 // CHECK23-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
20948 // CHECK23-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
20949 // CHECK23-NEXT:    [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]])
20950 // CHECK23-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
20951 // CHECK23-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
20952 // CHECK23-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
20953 // CHECK23-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
20954 // CHECK23-NEXT:    [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]])
20955 // CHECK23-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
20956 // CHECK23-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
20957 // CHECK23-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
20958 // CHECK23-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
20959 // CHECK23-NEXT:    [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]])
20960 // CHECK23-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
20961 // CHECK23-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
20962 // CHECK23-NEXT:    store i32 [[ADD6]], i32* [[A]], align 4
20963 // CHECK23-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
20964 // CHECK23-NEXT:    ret i32 [[TMP8]]
20965 //
20966 //
20967 // CHECK23-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
20968 // CHECK23-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 {
20969 // CHECK23-NEXT:  entry:
20970 // CHECK23-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
20971 // CHECK23-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
20972 // CHECK23-NEXT:    [[B:%.*]] = alloca i32, align 4
20973 // CHECK23-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 4
20974 // CHECK23-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 4
20975 // CHECK23-NEXT:    [[I:%.*]] = alloca i32, align 4
20976 // CHECK23-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
20977 // CHECK23-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
20978 // CHECK23-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
20979 // CHECK23-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
20980 // CHECK23-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
20981 // CHECK23-NEXT:    store i32 [[ADD]], i32* [[B]], align 4
20982 // CHECK23-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
20983 // CHECK23-NEXT:    [[TMP2:%.*]] = call i8* @llvm.stacksave()
20984 // CHECK23-NEXT:    store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4
20985 // CHECK23-NEXT:    [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]
20986 // CHECK23-NEXT:    [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2
20987 // CHECK23-NEXT:    store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
20988 // CHECK23-NEXT:    store i32 0, i32* [[I]], align 4
20989 // CHECK23-NEXT:    br label [[FOR_COND:%.*]]
20990 // CHECK23:       for.cond:
20991 // CHECK23-NEXT:    [[TMP4:%.*]] = load i32, i32* [[I]], align 4
20992 // CHECK23-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP4]], 10
20993 // CHECK23-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
20994 // CHECK23:       for.body:
20995 // CHECK23-NEXT:    [[TMP5:%.*]] = load i32, i32* [[B]], align 4
20996 // CHECK23-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP5]] to double
20997 // CHECK23-NEXT:    [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00
20998 // CHECK23-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
20999 // CHECK23-NEXT:    store double [[ADD2]], double* [[A]], align 4
21000 // CHECK23-NEXT:    [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
21001 // CHECK23-NEXT:    [[TMP6:%.*]] = load double, double* [[A3]], align 4
21002 // CHECK23-NEXT:    [[INC:%.*]] = fadd double [[TMP6]], 1.000000e+00
21003 // CHECK23-NEXT:    store double [[INC]], double* [[A3]], align 4
21004 // CHECK23-NEXT:    [[CONV4:%.*]] = fptosi double [[INC]] to i16
21005 // CHECK23-NEXT:    [[TMP7:%.*]] = mul nsw i32 1, [[TMP1]]
21006 // CHECK23-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP7]]
21007 // CHECK23-NEXT:    [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
21008 // CHECK23-NEXT:    store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2
21009 // CHECK23-NEXT:    br label [[FOR_INC:%.*]]
21010 // CHECK23:       for.inc:
21011 // CHECK23-NEXT:    [[TMP8:%.*]] = load i32, i32* [[I]], align 4
21012 // CHECK23-NEXT:    [[INC6:%.*]] = add nsw i32 [[TMP8]], 1
21013 // CHECK23-NEXT:    store i32 [[INC6]], i32* [[I]], align 4
21014 // CHECK23-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]
21015 // CHECK23:       for.end:
21016 // CHECK23-NEXT:    [[TMP9:%.*]] = mul nsw i32 1, [[TMP1]]
21017 // CHECK23-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP9]]
21018 // CHECK23-NEXT:    [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX7]], i32 1
21019 // CHECK23-NEXT:    [[TMP10:%.*]] = load i16, i16* [[ARRAYIDX8]], align 2
21020 // CHECK23-NEXT:    [[CONV9:%.*]] = sext i16 [[TMP10]] to i32
21021 // CHECK23-NEXT:    [[TMP11:%.*]] = load i32, i32* [[B]], align 4
21022 // CHECK23-NEXT:    [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[TMP11]]
21023 // CHECK23-NEXT:    [[TMP12:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
21024 // CHECK23-NEXT:    call void @llvm.stackrestore(i8* [[TMP12]])
21025 // CHECK23-NEXT:    ret i32 [[ADD10]]
21026 //
21027 //
21028 // CHECK23-LABEL: define {{[^@]+}}@_ZL7fstatici
21029 // CHECK23-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
21030 // CHECK23-NEXT:  entry:
21031 // CHECK23-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
21032 // CHECK23-NEXT:    [[A:%.*]] = alloca i32, align 4
21033 // CHECK23-NEXT:    [[AA:%.*]] = alloca i16, align 2
21034 // CHECK23-NEXT:    [[AAA:%.*]] = alloca i8, align 1
21035 // CHECK23-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
21036 // CHECK23-NEXT:    [[I:%.*]] = alloca i32, align 4
21037 // CHECK23-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
21038 // CHECK23-NEXT:    store i32 0, i32* [[A]], align 4
21039 // CHECK23-NEXT:    store i16 0, i16* [[AA]], align 2
21040 // CHECK23-NEXT:    store i8 0, i8* [[AAA]], align 1
21041 // CHECK23-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
21042 // CHECK23-NEXT:    store i32 [[TMP0]], i32* [[I]], align 4
21043 // CHECK23-NEXT:    br label [[FOR_COND:%.*]]
21044 // CHECK23:       for.cond:
21045 // CHECK23-NEXT:    [[TMP1:%.*]] = load i32, i32* [[I]], align 4
21046 // CHECK23-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
21047 // CHECK23-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP1]], [[TMP2]]
21048 // CHECK23-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
21049 // CHECK23:       for.body:
21050 // CHECK23-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
21051 // CHECK23-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP3]], 1
21052 // CHECK23-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
21053 // CHECK23-NEXT:    [[TMP4:%.*]] = load i16, i16* [[AA]], align 2
21054 // CHECK23-NEXT:    [[CONV:%.*]] = sext i16 [[TMP4]] to i32
21055 // CHECK23-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
21056 // CHECK23-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
21057 // CHECK23-NEXT:    store i16 [[CONV2]], i16* [[AA]], align 2
21058 // CHECK23-NEXT:    [[TMP5:%.*]] = load i8, i8* [[AAA]], align 1
21059 // CHECK23-NEXT:    [[CONV3:%.*]] = sext i8 [[TMP5]] to i32
21060 // CHECK23-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
21061 // CHECK23-NEXT:    [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8
21062 // CHECK23-NEXT:    store i8 [[CONV5]], i8* [[AAA]], align 1
21063 // CHECK23-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2
21064 // CHECK23-NEXT:    [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
21065 // CHECK23-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP6]], 1
21066 // CHECK23-NEXT:    store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4
21067 // CHECK23-NEXT:    br label [[FOR_INC:%.*]]
21068 // CHECK23:       for.inc:
21069 // CHECK23-NEXT:    [[TMP7:%.*]] = load i32, i32* [[I]], align 4
21070 // CHECK23-NEXT:    [[INC:%.*]] = add nsw i32 [[TMP7]], 1
21071 // CHECK23-NEXT:    store i32 [[INC]], i32* [[I]], align 4
21072 // CHECK23-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]
21073 // CHECK23:       for.end:
21074 // CHECK23-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
21075 // CHECK23-NEXT:    ret i32 [[TMP8]]
21076 //
21077 //
21078 // CHECK23-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
21079 // CHECK23-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat {
21080 // CHECK23-NEXT:  entry:
21081 // CHECK23-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
21082 // CHECK23-NEXT:    [[A:%.*]] = alloca i32, align 4
21083 // CHECK23-NEXT:    [[AA:%.*]] = alloca i16, align 2
21084 // CHECK23-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
21085 // CHECK23-NEXT:    [[I:%.*]] = alloca i32, align 4
21086 // CHECK23-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
21087 // CHECK23-NEXT:    store i32 0, i32* [[A]], align 4
21088 // CHECK23-NEXT:    store i16 0, i16* [[AA]], align 2
21089 // CHECK23-NEXT:    store i32 0, i32* [[I]], align 4
21090 // CHECK23-NEXT:    br label [[FOR_COND:%.*]]
21091 // CHECK23:       for.cond:
21092 // CHECK23-NEXT:    [[TMP0:%.*]] = load i32, i32* [[I]], align 4
21093 // CHECK23-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10
21094 // CHECK23-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
21095 // CHECK23:       for.body:
21096 // CHECK23-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
21097 // CHECK23-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
21098 // CHECK23-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
21099 // CHECK23-NEXT:    [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
21100 // CHECK23-NEXT:    [[CONV:%.*]] = sext i16 [[TMP2]] to i32
21101 // CHECK23-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
21102 // CHECK23-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
21103 // CHECK23-NEXT:    store i16 [[CONV2]], i16* [[AA]], align 2
21104 // CHECK23-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2
21105 // CHECK23-NEXT:    [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
21106 // CHECK23-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1
21107 // CHECK23-NEXT:    store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4
21108 // CHECK23-NEXT:    br label [[FOR_INC:%.*]]
21109 // CHECK23:       for.inc:
21110 // CHECK23-NEXT:    [[TMP4:%.*]] = load i32, i32* [[I]], align 4
21111 // CHECK23-NEXT:    [[INC:%.*]] = add nsw i32 [[TMP4]], 1
21112 // CHECK23-NEXT:    store i32 [[INC]], i32* [[I]], align 4
21113 // CHECK23-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]
21114 // CHECK23:       for.end:
21115 // CHECK23-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
21116 // CHECK23-NEXT:    ret i32 [[TMP5]]
21117 //
21118 //
21119 // CHECK24-LABEL: define {{[^@]+}}@_Z3fooi
21120 // CHECK24-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] {
21121 // CHECK24-NEXT:  entry:
21122 // CHECK24-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
21123 // CHECK24-NEXT:    [[A:%.*]] = alloca i32, align 4
21124 // CHECK24-NEXT:    [[AA:%.*]] = alloca i16, align 2
21125 // CHECK24-NEXT:    [[B:%.*]] = alloca [10 x float], align 4
21126 // CHECK24-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 4
21127 // CHECK24-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 4
21128 // CHECK24-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 8
21129 // CHECK24-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i32, align 4
21130 // CHECK24-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4
21131 // CHECK24-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
21132 // CHECK24-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
21133 // CHECK24-NEXT:    [[I:%.*]] = alloca i32, align 4
21134 // CHECK24-NEXT:    [[I3:%.*]] = alloca i32, align 4
21135 // CHECK24-NEXT:    [[I10:%.*]] = alloca i32, align 4
21136 // CHECK24-NEXT:    [[I19:%.*]] = alloca i32, align 4
21137 // CHECK24-NEXT:    [[DOTCAPTURE_EXPR_30:%.*]] = alloca i32, align 4
21138 // CHECK24-NEXT:    [[I31:%.*]] = alloca i32, align 4
21139 // CHECK24-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
21140 // CHECK24-NEXT:    store i32 0, i32* [[A]], align 4
21141 // CHECK24-NEXT:    store i16 0, i16* [[AA]], align 2
21142 // CHECK24-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
21143 // CHECK24-NEXT:    [[TMP1:%.*]] = call i8* @llvm.stacksave()
21144 // CHECK24-NEXT:    store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4
21145 // CHECK24-NEXT:    [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4
21146 // CHECK24-NEXT:    store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4
21147 // CHECK24-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
21148 // CHECK24-NEXT:    [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]]
21149 // CHECK24-NEXT:    [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8
21150 // CHECK24-NEXT:    store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4
21151 // CHECK24-NEXT:    [[TMP4:%.*]] = load i32, i32* [[A]], align 4
21152 // CHECK24-NEXT:    store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4
21153 // CHECK24-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
21154 // CHECK24-NEXT:    store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_2]], align 4
21155 // CHECK24-NEXT:    store i32 0, i32* [[I]], align 4
21156 // CHECK24-NEXT:    br label [[FOR_COND:%.*]]
21157 // CHECK24:       for.cond:
21158 // CHECK24-NEXT:    [[TMP6:%.*]] = load i32, i32* [[I]], align 4
21159 // CHECK24-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP6]], 10
21160 // CHECK24-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
21161 // CHECK24:       for.body:
21162 // CHECK24-NEXT:    br label [[FOR_INC:%.*]]
21163 // CHECK24:       for.inc:
21164 // CHECK24-NEXT:    [[TMP7:%.*]] = load i32, i32* [[I]], align 4
21165 // CHECK24-NEXT:    [[INC:%.*]] = add nsw i32 [[TMP7]], 1
21166 // CHECK24-NEXT:    store i32 [[INC]], i32* [[I]], align 4
21167 // CHECK24-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]
21168 // CHECK24:       for.end:
21169 // CHECK24-NEXT:    store i32 0, i32* [[I3]], align 4
21170 // CHECK24-NEXT:    br label [[FOR_COND4:%.*]]
21171 // CHECK24:       for.cond4:
21172 // CHECK24-NEXT:    [[TMP8:%.*]] = load i32, i32* [[I3]], align 4
21173 // CHECK24-NEXT:    [[CMP5:%.*]] = icmp slt i32 [[TMP8]], 10
21174 // CHECK24-NEXT:    br i1 [[CMP5]], label [[FOR_BODY6:%.*]], label [[FOR_END9:%.*]]
21175 // CHECK24:       for.body6:
21176 // CHECK24-NEXT:    [[TMP9:%.*]] = load i32, i32* [[A]], align 4
21177 // CHECK24-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP9]], 1
21178 // CHECK24-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
21179 // CHECK24-NEXT:    br label [[FOR_INC7:%.*]]
21180 // CHECK24:       for.inc7:
21181 // CHECK24-NEXT:    [[TMP10:%.*]] = load i32, i32* [[I3]], align 4
21182 // CHECK24-NEXT:    [[INC8:%.*]] = add nsw i32 [[TMP10]], 1
21183 // CHECK24-NEXT:    store i32 [[INC8]], i32* [[I3]], align 4
21184 // CHECK24-NEXT:    br label [[FOR_COND4]], !llvm.loop [[LOOP5:![0-9]+]]
21185 // CHECK24:       for.end9:
21186 // CHECK24-NEXT:    store i32 0, i32* [[I10]], align 4
21187 // CHECK24-NEXT:    br label [[FOR_COND11:%.*]]
21188 // CHECK24:       for.cond11:
21189 // CHECK24-NEXT:    [[TMP11:%.*]] = load i32, i32* [[I10]], align 4
21190 // CHECK24-NEXT:    [[CMP12:%.*]] = icmp slt i32 [[TMP11]], 10
21191 // CHECK24-NEXT:    br i1 [[CMP12]], label [[FOR_BODY13:%.*]], label [[FOR_END18:%.*]]
21192 // CHECK24:       for.body13:
21193 // CHECK24-NEXT:    [[TMP12:%.*]] = load i16, i16* [[AA]], align 2
21194 // CHECK24-NEXT:    [[CONV:%.*]] = sext i16 [[TMP12]] to i32
21195 // CHECK24-NEXT:    [[ADD14:%.*]] = add nsw i32 [[CONV]], 1
21196 // CHECK24-NEXT:    [[CONV15:%.*]] = trunc i32 [[ADD14]] to i16
21197 // CHECK24-NEXT:    store i16 [[CONV15]], i16* [[AA]], align 2
21198 // CHECK24-NEXT:    br label [[FOR_INC16:%.*]]
21199 // CHECK24:       for.inc16:
21200 // CHECK24-NEXT:    [[TMP13:%.*]] = load i32, i32* [[I10]], align 4
21201 // CHECK24-NEXT:    [[INC17:%.*]] = add nsw i32 [[TMP13]], 1
21202 // CHECK24-NEXT:    store i32 [[INC17]], i32* [[I10]], align 4
21203 // CHECK24-NEXT:    br label [[FOR_COND11]], !llvm.loop [[LOOP6:![0-9]+]]
21204 // CHECK24:       for.end18:
21205 // CHECK24-NEXT:    store i32 0, i32* [[I19]], align 4
21206 // CHECK24-NEXT:    br label [[FOR_COND20:%.*]]
21207 // CHECK24:       for.cond20:
21208 // CHECK24-NEXT:    [[TMP14:%.*]] = load i32, i32* [[I19]], align 4
21209 // CHECK24-NEXT:    [[CMP21:%.*]] = icmp slt i32 [[TMP14]], 10
21210 // CHECK24-NEXT:    br i1 [[CMP21]], label [[FOR_BODY22:%.*]], label [[FOR_END29:%.*]]
21211 // CHECK24:       for.body22:
21212 // CHECK24-NEXT:    [[TMP15:%.*]] = load i32, i32* [[A]], align 4
21213 // CHECK24-NEXT:    [[ADD23:%.*]] = add nsw i32 [[TMP15]], 1
21214 // CHECK24-NEXT:    store i32 [[ADD23]], i32* [[A]], align 4
21215 // CHECK24-NEXT:    [[TMP16:%.*]] = load i16, i16* [[AA]], align 2
21216 // CHECK24-NEXT:    [[CONV24:%.*]] = sext i16 [[TMP16]] to i32
21217 // CHECK24-NEXT:    [[ADD25:%.*]] = add nsw i32 [[CONV24]], 1
21218 // CHECK24-NEXT:    [[CONV26:%.*]] = trunc i32 [[ADD25]] to i16
21219 // CHECK24-NEXT:    store i16 [[CONV26]], i16* [[AA]], align 2
21220 // CHECK24-NEXT:    br label [[FOR_INC27:%.*]]
21221 // CHECK24:       for.inc27:
21222 // CHECK24-NEXT:    [[TMP17:%.*]] = load i32, i32* [[I19]], align 4
21223 // CHECK24-NEXT:    [[INC28:%.*]] = add nsw i32 [[TMP17]], 1
21224 // CHECK24-NEXT:    store i32 [[INC28]], i32* [[I19]], align 4
21225 // CHECK24-NEXT:    br label [[FOR_COND20]], !llvm.loop [[LOOP7:![0-9]+]]
21226 // CHECK24:       for.end29:
21227 // CHECK24-NEXT:    [[TMP18:%.*]] = load i32, i32* [[N_ADDR]], align 4
21228 // CHECK24-NEXT:    store i32 [[TMP18]], i32* [[DOTCAPTURE_EXPR_30]], align 4
21229 // CHECK24-NEXT:    store i32 0, i32* [[I31]], align 4
21230 // CHECK24-NEXT:    br label [[FOR_COND32:%.*]]
21231 // CHECK24:       for.cond32:
21232 // CHECK24-NEXT:    [[TMP19:%.*]] = load i32, i32* [[I31]], align 4
21233 // CHECK24-NEXT:    [[CMP33:%.*]] = icmp slt i32 [[TMP19]], 10
21234 // CHECK24-NEXT:    br i1 [[CMP33]], label [[FOR_BODY34:%.*]], label [[FOR_END55:%.*]]
21235 // CHECK24:       for.body34:
21236 // CHECK24-NEXT:    [[TMP20:%.*]] = load i32, i32* [[A]], align 4
21237 // CHECK24-NEXT:    [[ADD35:%.*]] = add nsw i32 [[TMP20]], 1
21238 // CHECK24-NEXT:    store i32 [[ADD35]], i32* [[A]], align 4
21239 // CHECK24-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2
21240 // CHECK24-NEXT:    [[TMP21:%.*]] = load float, float* [[ARRAYIDX]], align 4
21241 // CHECK24-NEXT:    [[CONV36:%.*]] = fpext float [[TMP21]] to double
21242 // CHECK24-NEXT:    [[ADD37:%.*]] = fadd double [[CONV36]], 1.000000e+00
21243 // CHECK24-NEXT:    [[CONV38:%.*]] = fptrunc double [[ADD37]] to float
21244 // CHECK24-NEXT:    store float [[CONV38]], float* [[ARRAYIDX]], align 4
21245 // CHECK24-NEXT:    [[ARRAYIDX39:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3
21246 // CHECK24-NEXT:    [[TMP22:%.*]] = load float, float* [[ARRAYIDX39]], align 4
21247 // CHECK24-NEXT:    [[CONV40:%.*]] = fpext float [[TMP22]] to double
21248 // CHECK24-NEXT:    [[ADD41:%.*]] = fadd double [[CONV40]], 1.000000e+00
21249 // CHECK24-NEXT:    [[CONV42:%.*]] = fptrunc double [[ADD41]] to float
21250 // CHECK24-NEXT:    store float [[CONV42]], float* [[ARRAYIDX39]], align 4
21251 // CHECK24-NEXT:    [[ARRAYIDX43:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1
21252 // CHECK24-NEXT:    [[ARRAYIDX44:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX43]], i32 0, i32 2
21253 // CHECK24-NEXT:    [[TMP23:%.*]] = load double, double* [[ARRAYIDX44]], align 8
21254 // CHECK24-NEXT:    [[ADD45:%.*]] = fadd double [[TMP23]], 1.000000e+00
21255 // CHECK24-NEXT:    store double [[ADD45]], double* [[ARRAYIDX44]], align 8
21256 // CHECK24-NEXT:    [[TMP24:%.*]] = mul nsw i32 1, [[TMP2]]
21257 // CHECK24-NEXT:    [[ARRAYIDX46:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP24]]
21258 // CHECK24-NEXT:    [[ARRAYIDX47:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX46]], i32 3
21259 // CHECK24-NEXT:    [[TMP25:%.*]] = load double, double* [[ARRAYIDX47]], align 8
21260 // CHECK24-NEXT:    [[ADD48:%.*]] = fadd double [[TMP25]], 1.000000e+00
21261 // CHECK24-NEXT:    store double [[ADD48]], double* [[ARRAYIDX47]], align 8
21262 // CHECK24-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0
21263 // CHECK24-NEXT:    [[TMP26:%.*]] = load i64, i64* [[X]], align 4
21264 // CHECK24-NEXT:    [[ADD49:%.*]] = add nsw i64 [[TMP26]], 1
21265 // CHECK24-NEXT:    store i64 [[ADD49]], i64* [[X]], align 4
21266 // CHECK24-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1
21267 // CHECK24-NEXT:    [[TMP27:%.*]] = load i8, i8* [[Y]], align 4
21268 // CHECK24-NEXT:    [[CONV50:%.*]] = sext i8 [[TMP27]] to i32
21269 // CHECK24-NEXT:    [[ADD51:%.*]] = add nsw i32 [[CONV50]], 1
21270 // CHECK24-NEXT:    [[CONV52:%.*]] = trunc i32 [[ADD51]] to i8
21271 // CHECK24-NEXT:    store i8 [[CONV52]], i8* [[Y]], align 4
21272 // CHECK24-NEXT:    br label [[FOR_INC53:%.*]]
21273 // CHECK24:       for.inc53:
21274 // CHECK24-NEXT:    [[TMP28:%.*]] = load i32, i32* [[I31]], align 4
21275 // CHECK24-NEXT:    [[INC54:%.*]] = add nsw i32 [[TMP28]], 1
21276 // CHECK24-NEXT:    store i32 [[INC54]], i32* [[I31]], align 4
21277 // CHECK24-NEXT:    br label [[FOR_COND32]], !llvm.loop [[LOOP8:![0-9]+]]
21278 // CHECK24:       for.end55:
21279 // CHECK24-NEXT:    [[TMP29:%.*]] = load i32, i32* [[A]], align 4
21280 // CHECK24-NEXT:    [[TMP30:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
21281 // CHECK24-NEXT:    call void @llvm.stackrestore(i8* [[TMP30]])
21282 // CHECK24-NEXT:    ret i32 [[TMP29]]
21283 //
21284 //
21285 // CHECK24-LABEL: define {{[^@]+}}@_Z3bari
21286 // CHECK24-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
21287 // CHECK24-NEXT:  entry:
21288 // CHECK24-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
21289 // CHECK24-NEXT:    [[A:%.*]] = alloca i32, align 4
21290 // CHECK24-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4
21291 // CHECK24-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
21292 // CHECK24-NEXT:    store i32 0, i32* [[A]], align 4
21293 // CHECK24-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
21294 // CHECK24-NEXT:    [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]])
21295 // CHECK24-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
21296 // CHECK24-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
21297 // CHECK24-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
21298 // CHECK24-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
21299 // CHECK24-NEXT:    [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]])
21300 // CHECK24-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
21301 // CHECK24-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
21302 // CHECK24-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
21303 // CHECK24-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
21304 // CHECK24-NEXT:    [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]])
21305 // CHECK24-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
21306 // CHECK24-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
21307 // CHECK24-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
21308 // CHECK24-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
21309 // CHECK24-NEXT:    [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]])
21310 // CHECK24-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
21311 // CHECK24-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
21312 // CHECK24-NEXT:    store i32 [[ADD6]], i32* [[A]], align 4
21313 // CHECK24-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
21314 // CHECK24-NEXT:    ret i32 [[TMP8]]
21315 //
21316 //
21317 // CHECK24-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
21318 // CHECK24-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 {
21319 // CHECK24-NEXT:  entry:
21320 // CHECK24-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
21321 // CHECK24-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
21322 // CHECK24-NEXT:    [[B:%.*]] = alloca i32, align 4
21323 // CHECK24-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 4
21324 // CHECK24-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 4
21325 // CHECK24-NEXT:    [[I:%.*]] = alloca i32, align 4
21326 // CHECK24-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
21327 // CHECK24-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
21328 // CHECK24-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
21329 // CHECK24-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
21330 // CHECK24-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
21331 // CHECK24-NEXT:    store i32 [[ADD]], i32* [[B]], align 4
21332 // CHECK24-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
21333 // CHECK24-NEXT:    [[TMP2:%.*]] = call i8* @llvm.stacksave()
21334 // CHECK24-NEXT:    store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4
21335 // CHECK24-NEXT:    [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]
21336 // CHECK24-NEXT:    [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2
21337 // CHECK24-NEXT:    store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
21338 // CHECK24-NEXT:    store i32 0, i32* [[I]], align 4
21339 // CHECK24-NEXT:    br label [[FOR_COND:%.*]]
21340 // CHECK24:       for.cond:
21341 // CHECK24-NEXT:    [[TMP4:%.*]] = load i32, i32* [[I]], align 4
21342 // CHECK24-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP4]], 10
21343 // CHECK24-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
21344 // CHECK24:       for.body:
21345 // CHECK24-NEXT:    [[TMP5:%.*]] = load i32, i32* [[B]], align 4
21346 // CHECK24-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP5]] to double
21347 // CHECK24-NEXT:    [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00
21348 // CHECK24-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
21349 // CHECK24-NEXT:    store double [[ADD2]], double* [[A]], align 4
21350 // CHECK24-NEXT:    [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
21351 // CHECK24-NEXT:    [[TMP6:%.*]] = load double, double* [[A3]], align 4
21352 // CHECK24-NEXT:    [[INC:%.*]] = fadd double [[TMP6]], 1.000000e+00
21353 // CHECK24-NEXT:    store double [[INC]], double* [[A3]], align 4
21354 // CHECK24-NEXT:    [[CONV4:%.*]] = fptosi double [[INC]] to i16
21355 // CHECK24-NEXT:    [[TMP7:%.*]] = mul nsw i32 1, [[TMP1]]
21356 // CHECK24-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP7]]
21357 // CHECK24-NEXT:    [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
21358 // CHECK24-NEXT:    store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2
21359 // CHECK24-NEXT:    br label [[FOR_INC:%.*]]
21360 // CHECK24:       for.inc:
21361 // CHECK24-NEXT:    [[TMP8:%.*]] = load i32, i32* [[I]], align 4
21362 // CHECK24-NEXT:    [[INC6:%.*]] = add nsw i32 [[TMP8]], 1
21363 // CHECK24-NEXT:    store i32 [[INC6]], i32* [[I]], align 4
21364 // CHECK24-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]
21365 // CHECK24:       for.end:
21366 // CHECK24-NEXT:    [[TMP9:%.*]] = mul nsw i32 1, [[TMP1]]
21367 // CHECK24-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP9]]
21368 // CHECK24-NEXT:    [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX7]], i32 1
21369 // CHECK24-NEXT:    [[TMP10:%.*]] = load i16, i16* [[ARRAYIDX8]], align 2
21370 // CHECK24-NEXT:    [[CONV9:%.*]] = sext i16 [[TMP10]] to i32
21371 // CHECK24-NEXT:    [[TMP11:%.*]] = load i32, i32* [[B]], align 4
21372 // CHECK24-NEXT:    [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[TMP11]]
21373 // CHECK24-NEXT:    [[TMP12:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
21374 // CHECK24-NEXT:    call void @llvm.stackrestore(i8* [[TMP12]])
21375 // CHECK24-NEXT:    ret i32 [[ADD10]]
21376 //
21377 //
21378 // CHECK24-LABEL: define {{[^@]+}}@_ZL7fstatici
21379 // CHECK24-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
21380 // CHECK24-NEXT:  entry:
21381 // CHECK24-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
21382 // CHECK24-NEXT:    [[A:%.*]] = alloca i32, align 4
21383 // CHECK24-NEXT:    [[AA:%.*]] = alloca i16, align 2
21384 // CHECK24-NEXT:    [[AAA:%.*]] = alloca i8, align 1
21385 // CHECK24-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
21386 // CHECK24-NEXT:    [[I:%.*]] = alloca i32, align 4
21387 // CHECK24-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
21388 // CHECK24-NEXT:    store i32 0, i32* [[A]], align 4
21389 // CHECK24-NEXT:    store i16 0, i16* [[AA]], align 2
21390 // CHECK24-NEXT:    store i8 0, i8* [[AAA]], align 1
21391 // CHECK24-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
21392 // CHECK24-NEXT:    store i32 [[TMP0]], i32* [[I]], align 4
21393 // CHECK24-NEXT:    br label [[FOR_COND:%.*]]
21394 // CHECK24:       for.cond:
21395 // CHECK24-NEXT:    [[TMP1:%.*]] = load i32, i32* [[I]], align 4
21396 // CHECK24-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
21397 // CHECK24-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP1]], [[TMP2]]
21398 // CHECK24-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
21399 // CHECK24:       for.body:
21400 // CHECK24-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
21401 // CHECK24-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP3]], 1
21402 // CHECK24-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
21403 // CHECK24-NEXT:    [[TMP4:%.*]] = load i16, i16* [[AA]], align 2
21404 // CHECK24-NEXT:    [[CONV:%.*]] = sext i16 [[TMP4]] to i32
21405 // CHECK24-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
21406 // CHECK24-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
21407 // CHECK24-NEXT:    store i16 [[CONV2]], i16* [[AA]], align 2
21408 // CHECK24-NEXT:    [[TMP5:%.*]] = load i8, i8* [[AAA]], align 1
21409 // CHECK24-NEXT:    [[CONV3:%.*]] = sext i8 [[TMP5]] to i32
21410 // CHECK24-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
21411 // CHECK24-NEXT:    [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8
21412 // CHECK24-NEXT:    store i8 [[CONV5]], i8* [[AAA]], align 1
21413 // CHECK24-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2
21414 // CHECK24-NEXT:    [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
21415 // CHECK24-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP6]], 1
21416 // CHECK24-NEXT:    store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4
21417 // CHECK24-NEXT:    br label [[FOR_INC:%.*]]
21418 // CHECK24:       for.inc:
21419 // CHECK24-NEXT:    [[TMP7:%.*]] = load i32, i32* [[I]], align 4
21420 // CHECK24-NEXT:    [[INC:%.*]] = add nsw i32 [[TMP7]], 1
21421 // CHECK24-NEXT:    store i32 [[INC]], i32* [[I]], align 4
21422 // CHECK24-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]
21423 // CHECK24:       for.end:
21424 // CHECK24-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
21425 // CHECK24-NEXT:    ret i32 [[TMP8]]
21426 //
21427 //
21428 // CHECK24-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
21429 // CHECK24-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat {
21430 // CHECK24-NEXT:  entry:
21431 // CHECK24-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
21432 // CHECK24-NEXT:    [[A:%.*]] = alloca i32, align 4
21433 // CHECK24-NEXT:    [[AA:%.*]] = alloca i16, align 2
21434 // CHECK24-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
21435 // CHECK24-NEXT:    [[I:%.*]] = alloca i32, align 4
21436 // CHECK24-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
21437 // CHECK24-NEXT:    store i32 0, i32* [[A]], align 4
21438 // CHECK24-NEXT:    store i16 0, i16* [[AA]], align 2
21439 // CHECK24-NEXT:    store i32 0, i32* [[I]], align 4
21440 // CHECK24-NEXT:    br label [[FOR_COND:%.*]]
21441 // CHECK24:       for.cond:
21442 // CHECK24-NEXT:    [[TMP0:%.*]] = load i32, i32* [[I]], align 4
21443 // CHECK24-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10
21444 // CHECK24-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
21445 // CHECK24:       for.body:
21446 // CHECK24-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
21447 // CHECK24-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
21448 // CHECK24-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
21449 // CHECK24-NEXT:    [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
21450 // CHECK24-NEXT:    [[CONV:%.*]] = sext i16 [[TMP2]] to i32
21451 // CHECK24-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
21452 // CHECK24-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
21453 // CHECK24-NEXT:    store i16 [[CONV2]], i16* [[AA]], align 2
21454 // CHECK24-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2
21455 // CHECK24-NEXT:    [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
21456 // CHECK24-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1
21457 // CHECK24-NEXT:    store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4
21458 // CHECK24-NEXT:    br label [[FOR_INC:%.*]]
21459 // CHECK24:       for.inc:
21460 // CHECK24-NEXT:    [[TMP4:%.*]] = load i32, i32* [[I]], align 4
21461 // CHECK24-NEXT:    [[INC:%.*]] = add nsw i32 [[TMP4]], 1
21462 // CHECK24-NEXT:    store i32 [[INC]], i32* [[I]], align 4
21463 // CHECK24-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]
21464 // CHECK24:       for.end:
21465 // CHECK24-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
21466 // CHECK24-NEXT:    ret i32 [[TMP5]]
21467 //
21468 //
21469 // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103
21470 // CHECK25-SAME: (i64 [[AA:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] {
21471 // CHECK25-NEXT:  entry:
21472 // CHECK25-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
21473 // CHECK25-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
21474 // CHECK25-NEXT:    [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8
21475 // CHECK25-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
21476 // CHECK25-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]])
21477 // CHECK25-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
21478 // CHECK25-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
21479 // CHECK25-NEXT:    store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8
21480 // CHECK25-NEXT:    [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
21481 // CHECK25-NEXT:    [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
21482 // CHECK25-NEXT:    [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32*
21483 // CHECK25-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 8
21484 // CHECK25-NEXT:    [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 8
21485 // CHECK25-NEXT:    call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
21486 // CHECK25-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV]], align 8
21487 // CHECK25-NEXT:    [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
21488 // CHECK25-NEXT:    store i16 [[TMP3]], i16* [[CONV5]], align 2
21489 // CHECK25-NEXT:    [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
21490 // CHECK25-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]])
21491 // CHECK25-NEXT:    ret void
21492 //
21493 //
21494 // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined.
21495 // CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] {
21496 // CHECK25-NEXT:  entry:
21497 // CHECK25-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
21498 // CHECK25-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
21499 // CHECK25-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
21500 // CHECK25-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
21501 // CHECK25-NEXT:    [[TMP:%.*]] = alloca i32, align 4
21502 // CHECK25-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
21503 // CHECK25-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
21504 // CHECK25-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
21505 // CHECK25-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
21506 // CHECK25-NEXT:    [[I:%.*]] = alloca i32, align 4
21507 // CHECK25-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
21508 // CHECK25-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
21509 // CHECK25-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
21510 // CHECK25-NEXT:    [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
21511 // CHECK25-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
21512 // CHECK25-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
21513 // CHECK25-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
21514 // CHECK25-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
21515 // CHECK25-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
21516 // CHECK25-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
21517 // CHECK25-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
21518 // CHECK25-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
21519 // CHECK25-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
21520 // CHECK25-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
21521 // CHECK25:       cond.true:
21522 // CHECK25-NEXT:    br label [[COND_END:%.*]]
21523 // CHECK25:       cond.false:
21524 // CHECK25-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
21525 // CHECK25-NEXT:    br label [[COND_END]]
21526 // CHECK25:       cond.end:
21527 // CHECK25-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
21528 // CHECK25-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
21529 // CHECK25-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
21530 // CHECK25-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
21531 // CHECK25-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
21532 // CHECK25:       omp.inner.for.cond:
21533 // CHECK25-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
21534 // CHECK25-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
21535 // CHECK25-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
21536 // CHECK25-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
21537 // CHECK25:       omp.inner.for.body:
21538 // CHECK25-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
21539 // CHECK25-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
21540 // CHECK25-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
21541 // CHECK25-NEXT:    store i32 [[ADD]], i32* [[I]], align 4
21542 // CHECK25-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
21543 // CHECK25:       omp.body.continue:
21544 // CHECK25-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
21545 // CHECK25:       omp.inner.for.inc:
21546 // CHECK25-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
21547 // CHECK25-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
21548 // CHECK25-NEXT:    store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4
21549 // CHECK25-NEXT:    br label [[OMP_INNER_FOR_COND]]
21550 // CHECK25:       omp.inner.for.end:
21551 // CHECK25-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
21552 // CHECK25:       omp.loop.exit:
21553 // CHECK25-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
21554 // CHECK25-NEXT:    ret void
21555 //
21556 //
21557 // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113
21558 // CHECK25-SAME: (i64 [[AA:%.*]]) #[[ATTR0]] {
21559 // CHECK25-NEXT:  entry:
21560 // CHECK25-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
21561 // CHECK25-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
21562 // CHECK25-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
21563 // CHECK25-NEXT:    [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
21564 // CHECK25-NEXT:    [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8
21565 // CHECK25-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
21566 // CHECK25-NEXT:    store i16 [[TMP0]], i16* [[CONV1]], align 2
21567 // CHECK25-NEXT:    [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
21568 // CHECK25-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]])
21569 // CHECK25-NEXT:    ret void
21570 //
21571 //
21572 // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..1
21573 // CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] {
21574 // CHECK25-NEXT:  entry:
21575 // CHECK25-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
21576 // CHECK25-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
21577 // CHECK25-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
21578 // CHECK25-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
21579 // CHECK25-NEXT:    [[TMP:%.*]] = alloca i32, align 4
21580 // CHECK25-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
21581 // CHECK25-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
21582 // CHECK25-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
21583 // CHECK25-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
21584 // CHECK25-NEXT:    [[I:%.*]] = alloca i32, align 4
21585 // CHECK25-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
21586 // CHECK25-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
21587 // CHECK25-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
21588 // CHECK25-NEXT:    [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
21589 // CHECK25-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
21590 // CHECK25-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
21591 // CHECK25-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
21592 // CHECK25-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
21593 // CHECK25-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
21594 // CHECK25-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
21595 // CHECK25-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
21596 // CHECK25-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
21597 // CHECK25-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
21598 // CHECK25-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
21599 // CHECK25:       cond.true:
21600 // CHECK25-NEXT:    br label [[COND_END:%.*]]
21601 // CHECK25:       cond.false:
21602 // CHECK25-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
21603 // CHECK25-NEXT:    br label [[COND_END]]
21604 // CHECK25:       cond.end:
21605 // CHECK25-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
21606 // CHECK25-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
21607 // CHECK25-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
21608 // CHECK25-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
21609 // CHECK25-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
21610 // CHECK25:       omp.inner.for.cond:
21611 // CHECK25-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
21612 // CHECK25-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
21613 // CHECK25-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
21614 // CHECK25-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
21615 // CHECK25:       omp.inner.for.body:
21616 // CHECK25-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
21617 // CHECK25-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
21618 // CHECK25-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
21619 // CHECK25-NEXT:    store i32 [[ADD]], i32* [[I]], align 4
21620 // CHECK25-NEXT:    [[TMP8:%.*]] = load i16, i16* [[CONV]], align 8
21621 // CHECK25-NEXT:    [[CONV2:%.*]] = sext i16 [[TMP8]] to i32
21622 // CHECK25-NEXT:    [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
21623 // CHECK25-NEXT:    [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
21624 // CHECK25-NEXT:    store i16 [[CONV4]], i16* [[CONV]], align 8
21625 // CHECK25-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
21626 // CHECK25:       omp.body.continue:
21627 // CHECK25-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
21628 // CHECK25:       omp.inner.for.inc:
21629 // CHECK25-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
21630 // CHECK25-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP9]], 1
21631 // CHECK25-NEXT:    store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4
21632 // CHECK25-NEXT:    br label [[OMP_INNER_FOR_COND]]
21633 // CHECK25:       omp.inner.for.end:
21634 // CHECK25-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
21635 // CHECK25:       omp.loop.exit:
21636 // CHECK25-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
21637 // CHECK25-NEXT:    ret void
21638 //
21639 //
21640 // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120
21641 // CHECK25-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] {
21642 // CHECK25-NEXT:  entry:
21643 // CHECK25-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
21644 // CHECK25-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
21645 // CHECK25-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
21646 // CHECK25-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
21647 // CHECK25-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
21648 // CHECK25-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
21649 // CHECK25-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
21650 // CHECK25-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
21651 // CHECK25-NEXT:    [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
21652 // CHECK25-NEXT:    [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
21653 // CHECK25-NEXT:    store i32 [[TMP0]], i32* [[CONV2]], align 4
21654 // CHECK25-NEXT:    [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
21655 // CHECK25-NEXT:    [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
21656 // CHECK25-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
21657 // CHECK25-NEXT:    store i16 [[TMP2]], i16* [[CONV3]], align 2
21658 // CHECK25-NEXT:    [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
21659 // CHECK25-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
21660 // CHECK25-NEXT:    ret void
21661 //
21662 //
21663 // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..2
21664 // CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] {
21665 // CHECK25-NEXT:  entry:
21666 // CHECK25-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
21667 // CHECK25-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
21668 // CHECK25-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
21669 // CHECK25-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
21670 // CHECK25-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
21671 // CHECK25-NEXT:    [[TMP:%.*]] = alloca i32, align 4
21672 // CHECK25-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
21673 // CHECK25-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
21674 // CHECK25-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
21675 // CHECK25-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
21676 // CHECK25-NEXT:    [[I:%.*]] = alloca i32, align 4
21677 // CHECK25-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
21678 // CHECK25-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
21679 // CHECK25-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
21680 // CHECK25-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
21681 // CHECK25-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
21682 // CHECK25-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
21683 // CHECK25-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
21684 // CHECK25-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
21685 // CHECK25-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
21686 // CHECK25-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
21687 // CHECK25-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
21688 // CHECK25-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
21689 // CHECK25-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
21690 // CHECK25-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
21691 // CHECK25-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
21692 // CHECK25-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
21693 // CHECK25:       cond.true:
21694 // CHECK25-NEXT:    br label [[COND_END:%.*]]
21695 // CHECK25:       cond.false:
21696 // CHECK25-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
21697 // CHECK25-NEXT:    br label [[COND_END]]
21698 // CHECK25:       cond.end:
21699 // CHECK25-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
21700 // CHECK25-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
21701 // CHECK25-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
21702 // CHECK25-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
21703 // CHECK25-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
21704 // CHECK25:       omp.inner.for.cond:
21705 // CHECK25-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
21706 // CHECK25-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
21707 // CHECK25-NEXT:    [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
21708 // CHECK25-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
21709 // CHECK25:       omp.inner.for.body:
21710 // CHECK25-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
21711 // CHECK25-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
21712 // CHECK25-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
21713 // CHECK25-NEXT:    store i32 [[ADD]], i32* [[I]], align 4
21714 // CHECK25-NEXT:    [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
21715 // CHECK25-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
21716 // CHECK25-NEXT:    store i32 [[ADD3]], i32* [[CONV]], align 8
21717 // CHECK25-NEXT:    [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 8
21718 // CHECK25-NEXT:    [[CONV4:%.*]] = sext i16 [[TMP9]] to i32
21719 // CHECK25-NEXT:    [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
21720 // CHECK25-NEXT:    [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
21721 // CHECK25-NEXT:    store i16 [[CONV6]], i16* [[CONV1]], align 8
21722 // CHECK25-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
21723 // CHECK25:       omp.body.continue:
21724 // CHECK25-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
21725 // CHECK25:       omp.inner.for.inc:
21726 // CHECK25-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
21727 // CHECK25-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1
21728 // CHECK25-NEXT:    store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4
21729 // CHECK25-NEXT:    br label [[OMP_INNER_FOR_COND]]
21730 // CHECK25:       omp.inner.for.end:
21731 // CHECK25-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
21732 // CHECK25:       omp.loop.exit:
21733 // CHECK25-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
21734 // CHECK25-NEXT:    ret void
21735 //
21736 //
21737 // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145
21738 // CHECK25-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
21739 // CHECK25-NEXT:  entry:
21740 // CHECK25-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
21741 // CHECK25-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
21742 // CHECK25-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
21743 // CHECK25-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 8
21744 // CHECK25-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
21745 // CHECK25-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
21746 // CHECK25-NEXT:    [[VLA_ADDR4:%.*]] = alloca i64, align 8
21747 // CHECK25-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 8
21748 // CHECK25-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
21749 // CHECK25-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
21750 // CHECK25-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
21751 // CHECK25-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
21752 // CHECK25-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
21753 // CHECK25-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
21754 // CHECK25-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
21755 // CHECK25-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 8
21756 // CHECK25-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
21757 // CHECK25-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
21758 // CHECK25-NEXT:    store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
21759 // CHECK25-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 8
21760 // CHECK25-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
21761 // CHECK25-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
21762 // CHECK25-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
21763 // CHECK25-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
21764 // CHECK25-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
21765 // CHECK25-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
21766 // CHECK25-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
21767 // CHECK25-NEXT:    [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
21768 // CHECK25-NEXT:    [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
21769 // CHECK25-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
21770 // CHECK25-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
21771 // CHECK25-NEXT:    [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
21772 // CHECK25-NEXT:    [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
21773 // CHECK25-NEXT:    [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32*
21774 // CHECK25-NEXT:    store i32 [[TMP8]], i32* [[CONV6]], align 4
21775 // CHECK25-NEXT:    [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
21776 // CHECK25-NEXT:    [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 8
21777 // CHECK25-NEXT:    [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
21778 // CHECK25-NEXT:    store i32 [[TMP10]], i32* [[CONV7]], align 4
21779 // CHECK25-NEXT:    [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
21780 // CHECK25-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]])
21781 // CHECK25-NEXT:    ret void
21782 //
21783 //
21784 // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..3
21785 // CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
21786 // CHECK25-NEXT:  entry:
21787 // CHECK25-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
21788 // CHECK25-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
21789 // CHECK25-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
21790 // CHECK25-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
21791 // CHECK25-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
21792 // CHECK25-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 8
21793 // CHECK25-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
21794 // CHECK25-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
21795 // CHECK25-NEXT:    [[VLA_ADDR4:%.*]] = alloca i64, align 8
21796 // CHECK25-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 8
21797 // CHECK25-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
21798 // CHECK25-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
21799 // CHECK25-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
21800 // CHECK25-NEXT:    [[TMP:%.*]] = alloca i32, align 4
21801 // CHECK25-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
21802 // CHECK25-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
21803 // CHECK25-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
21804 // CHECK25-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
21805 // CHECK25-NEXT:    [[I:%.*]] = alloca i32, align 4
21806 // CHECK25-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
21807 // CHECK25-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
21808 // CHECK25-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
21809 // CHECK25-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
21810 // CHECK25-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
21811 // CHECK25-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 8
21812 // CHECK25-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
21813 // CHECK25-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
21814 // CHECK25-NEXT:    store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
21815 // CHECK25-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 8
21816 // CHECK25-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
21817 // CHECK25-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
21818 // CHECK25-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
21819 // CHECK25-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
21820 // CHECK25-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
21821 // CHECK25-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
21822 // CHECK25-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
21823 // CHECK25-NEXT:    [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
21824 // CHECK25-NEXT:    [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
21825 // CHECK25-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
21826 // CHECK25-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
21827 // CHECK25-NEXT:    [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
21828 // CHECK25-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
21829 // CHECK25-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
21830 // CHECK25-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
21831 // CHECK25-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
21832 // CHECK25-NEXT:    [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 8
21833 // CHECK25-NEXT:    [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
21834 // CHECK25-NEXT:    [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
21835 // CHECK25-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
21836 // CHECK25-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
21837 // CHECK25:       omp.dispatch.cond:
21838 // CHECK25-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
21839 // CHECK25-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 9
21840 // CHECK25-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
21841 // CHECK25:       cond.true:
21842 // CHECK25-NEXT:    br label [[COND_END:%.*]]
21843 // CHECK25:       cond.false:
21844 // CHECK25-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
21845 // CHECK25-NEXT:    br label [[COND_END]]
21846 // CHECK25:       cond.end:
21847 // CHECK25-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
21848 // CHECK25-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
21849 // CHECK25-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
21850 // CHECK25-NEXT:    store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
21851 // CHECK25-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
21852 // CHECK25-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
21853 // CHECK25-NEXT:    [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
21854 // CHECK25-NEXT:    br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
21855 // CHECK25:       omp.dispatch.body:
21856 // CHECK25-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
21857 // CHECK25:       omp.inner.for.cond:
21858 // CHECK25-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
21859 // CHECK25-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !11
21860 // CHECK25-NEXT:    [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
21861 // CHECK25-NEXT:    br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
21862 // CHECK25:       omp.inner.for.body:
21863 // CHECK25-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
21864 // CHECK25-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
21865 // CHECK25-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
21866 // CHECK25-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11
21867 // CHECK25-NEXT:    [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !11
21868 // CHECK25-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP19]], 1
21869 // CHECK25-NEXT:    store i32 [[ADD8]], i32* [[CONV]], align 8, !llvm.access.group !11
21870 // CHECK25-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
21871 // CHECK25-NEXT:    [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !11
21872 // CHECK25-NEXT:    [[CONV9:%.*]] = fpext float [[TMP20]] to double
21873 // CHECK25-NEXT:    [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00
21874 // CHECK25-NEXT:    [[CONV11:%.*]] = fptrunc double [[ADD10]] to float
21875 // CHECK25-NEXT:    store float [[CONV11]], float* [[ARRAYIDX]], align 4, !llvm.access.group !11
21876 // CHECK25-NEXT:    [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3
21877 // CHECK25-NEXT:    [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4, !llvm.access.group !11
21878 // CHECK25-NEXT:    [[CONV13:%.*]] = fpext float [[TMP21]] to double
21879 // CHECK25-NEXT:    [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00
21880 // CHECK25-NEXT:    [[CONV15:%.*]] = fptrunc double [[ADD14]] to float
21881 // CHECK25-NEXT:    store float [[CONV15]], float* [[ARRAYIDX12]], align 4, !llvm.access.group !11
21882 // CHECK25-NEXT:    [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1
21883 // CHECK25-NEXT:    [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i64 0, i64 2
21884 // CHECK25-NEXT:    [[TMP22:%.*]] = load double, double* [[ARRAYIDX17]], align 8, !llvm.access.group !11
21885 // CHECK25-NEXT:    [[ADD18:%.*]] = fadd double [[TMP22]], 1.000000e+00
21886 // CHECK25-NEXT:    store double [[ADD18]], double* [[ARRAYIDX17]], align 8, !llvm.access.group !11
21887 // CHECK25-NEXT:    [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]]
21888 // CHECK25-NEXT:    [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP23]]
21889 // CHECK25-NEXT:    [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i64 3
21890 // CHECK25-NEXT:    [[TMP24:%.*]] = load double, double* [[ARRAYIDX20]], align 8, !llvm.access.group !11
21891 // CHECK25-NEXT:    [[ADD21:%.*]] = fadd double [[TMP24]], 1.000000e+00
21892 // CHECK25-NEXT:    store double [[ADD21]], double* [[ARRAYIDX20]], align 8, !llvm.access.group !11
21893 // CHECK25-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0
21894 // CHECK25-NEXT:    [[TMP25:%.*]] = load i64, i64* [[X]], align 8, !llvm.access.group !11
21895 // CHECK25-NEXT:    [[ADD22:%.*]] = add nsw i64 [[TMP25]], 1
21896 // CHECK25-NEXT:    store i64 [[ADD22]], i64* [[X]], align 8, !llvm.access.group !11
21897 // CHECK25-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1
21898 // CHECK25-NEXT:    [[TMP26:%.*]] = load i8, i8* [[Y]], align 8, !llvm.access.group !11
21899 // CHECK25-NEXT:    [[CONV23:%.*]] = sext i8 [[TMP26]] to i32
21900 // CHECK25-NEXT:    [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1
21901 // CHECK25-NEXT:    [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8
21902 // CHECK25-NEXT:    store i8 [[CONV25]], i8* [[Y]], align 8, !llvm.access.group !11
21903 // CHECK25-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
21904 // CHECK25:       omp.body.continue:
21905 // CHECK25-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
21906 // CHECK25:       omp.inner.for.inc:
21907 // CHECK25-NEXT:    [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
21908 // CHECK25-NEXT:    [[ADD26:%.*]] = add nsw i32 [[TMP27]], 1
21909 // CHECK25-NEXT:    store i32 [[ADD26]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
21910 // CHECK25-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]
21911 // CHECK25:       omp.inner.for.end:
21912 // CHECK25-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
21913 // CHECK25:       omp.dispatch.inc:
21914 // CHECK25-NEXT:    [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
21915 // CHECK25-NEXT:    [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
21916 // CHECK25-NEXT:    [[ADD27:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]
21917 // CHECK25-NEXT:    store i32 [[ADD27]], i32* [[DOTOMP_LB]], align 4
21918 // CHECK25-NEXT:    [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
21919 // CHECK25-NEXT:    [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
21920 // CHECK25-NEXT:    [[ADD28:%.*]] = add nsw i32 [[TMP30]], [[TMP31]]
21921 // CHECK25-NEXT:    store i32 [[ADD28]], i32* [[DOTOMP_UB]], align 4
21922 // CHECK25-NEXT:    br label [[OMP_DISPATCH_COND]]
21923 // CHECK25:       omp.dispatch.end:
21924 // CHECK25-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]])
21925 // CHECK25-NEXT:    ret void
21926 //
21927 //
21928 // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200
21929 // CHECK25-SAME: (i64 [[N:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
21930 // CHECK25-NEXT:  entry:
21931 // CHECK25-NEXT:    [[N_ADDR:%.*]] = alloca i64, align 8
21932 // CHECK25-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
21933 // CHECK25-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
21934 // CHECK25-NEXT:    [[AAA_ADDR:%.*]] = alloca i64, align 8
21935 // CHECK25-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
21936 // CHECK25-NEXT:    [[N_CASTED:%.*]] = alloca i64, align 8
21937 // CHECK25-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
21938 // CHECK25-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
21939 // CHECK25-NEXT:    [[AAA_CASTED:%.*]] = alloca i64, align 8
21940 // CHECK25-NEXT:    store i64 [[N]], i64* [[N_ADDR]], align 8
21941 // CHECK25-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
21942 // CHECK25-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
21943 // CHECK25-NEXT:    store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
21944 // CHECK25-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
21945 // CHECK25-NEXT:    [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
21946 // CHECK25-NEXT:    [[CONV1:%.*]] = bitcast i64* [[A_ADDR]] to i32*
21947 // CHECK25-NEXT:    [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
21948 // CHECK25-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
21949 // CHECK25-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
21950 // CHECK25-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
21951 // CHECK25-NEXT:    [[CONV4:%.*]] = bitcast i64* [[N_CASTED]] to i32*
21952 // CHECK25-NEXT:    store i32 [[TMP1]], i32* [[CONV4]], align 4
21953 // CHECK25-NEXT:    [[TMP2:%.*]] = load i64, i64* [[N_CASTED]], align 8
21954 // CHECK25-NEXT:    [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 8
21955 // CHECK25-NEXT:    [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
21956 // CHECK25-NEXT:    store i32 [[TMP3]], i32* [[CONV5]], align 4
21957 // CHECK25-NEXT:    [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8
21958 // CHECK25-NEXT:    [[TMP5:%.*]] = load i16, i16* [[CONV2]], align 8
21959 // CHECK25-NEXT:    [[CONV6:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
21960 // CHECK25-NEXT:    store i16 [[TMP5]], i16* [[CONV6]], align 2
21961 // CHECK25-NEXT:    [[TMP6:%.*]] = load i64, i64* [[AA_CASTED]], align 8
21962 // CHECK25-NEXT:    [[TMP7:%.*]] = load i8, i8* [[CONV3]], align 8
21963 // CHECK25-NEXT:    [[CONV7:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
21964 // CHECK25-NEXT:    store i8 [[TMP7]], i8* [[CONV7]], align 1
21965 // CHECK25-NEXT:    [[TMP8:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
21966 // CHECK25-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]], [10 x i32]* [[TMP0]])
21967 // CHECK25-NEXT:    ret void
21968 //
21969 //
21970 // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..4
21971 // CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
21972 // CHECK25-NEXT:  entry:
21973 // CHECK25-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
21974 // CHECK25-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
21975 // CHECK25-NEXT:    [[N_ADDR:%.*]] = alloca i64, align 8
21976 // CHECK25-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
21977 // CHECK25-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
21978 // CHECK25-NEXT:    [[AAA_ADDR:%.*]] = alloca i64, align 8
21979 // CHECK25-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
21980 // CHECK25-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
21981 // CHECK25-NEXT:    [[TMP:%.*]] = alloca i32, align 4
21982 // CHECK25-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
21983 // CHECK25-NEXT:    [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4
21984 // CHECK25-NEXT:    [[DOTCAPTURE_EXPR_5:%.*]] = alloca i32, align 4
21985 // CHECK25-NEXT:    [[I:%.*]] = alloca i32, align 4
21986 // CHECK25-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
21987 // CHECK25-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
21988 // CHECK25-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
21989 // CHECK25-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
21990 // CHECK25-NEXT:    [[I8:%.*]] = alloca i32, align 4
21991 // CHECK25-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
21992 // CHECK25-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
21993 // CHECK25-NEXT:    store i64 [[N]], i64* [[N_ADDR]], align 8
21994 // CHECK25-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
21995 // CHECK25-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
21996 // CHECK25-NEXT:    store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
21997 // CHECK25-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
21998 // CHECK25-NEXT:    [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
21999 // CHECK25-NEXT:    [[CONV1:%.*]] = bitcast i64* [[A_ADDR]] to i32*
22000 // CHECK25-NEXT:    [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
22001 // CHECK25-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
22002 // CHECK25-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
22003 // CHECK25-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV1]], align 8
22004 // CHECK25-NEXT:    store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
22005 // CHECK25-NEXT:    [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
22006 // CHECK25-NEXT:    store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_4]], align 4
22007 // CHECK25-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4
22008 // CHECK25-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
22009 // CHECK25-NEXT:    [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]]
22010 // CHECK25-NEXT:    [[SUB6:%.*]] = sub i32 [[SUB]], 1
22011 // CHECK25-NEXT:    [[ADD:%.*]] = add i32 [[SUB6]], 1
22012 // CHECK25-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], 1
22013 // CHECK25-NEXT:    [[SUB7:%.*]] = sub i32 [[DIV]], 1
22014 // CHECK25-NEXT:    store i32 [[SUB7]], i32* [[DOTCAPTURE_EXPR_5]], align 4
22015 // CHECK25-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
22016 // CHECK25-NEXT:    store i32 [[TMP5]], i32* [[I]], align 4
22017 // CHECK25-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
22018 // CHECK25-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4
22019 // CHECK25-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]]
22020 // CHECK25-NEXT:    br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
22021 // CHECK25:       omp.precond.then:
22022 // CHECK25-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
22023 // CHECK25-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4
22024 // CHECK25-NEXT:    store i32 [[TMP8]], i32* [[DOTOMP_UB]], align 4
22025 // CHECK25-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
22026 // CHECK25-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
22027 // CHECK25-NEXT:    [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
22028 // CHECK25-NEXT:    [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
22029 // CHECK25-NEXT:    call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
22030 // CHECK25-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
22031 // CHECK25-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4
22032 // CHECK25-NEXT:    [[CMP9:%.*]] = icmp ugt i32 [[TMP11]], [[TMP12]]
22033 // CHECK25-NEXT:    br i1 [[CMP9]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
22034 // CHECK25:       cond.true:
22035 // CHECK25-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4
22036 // CHECK25-NEXT:    br label [[COND_END:%.*]]
22037 // CHECK25:       cond.false:
22038 // CHECK25-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
22039 // CHECK25-NEXT:    br label [[COND_END]]
22040 // CHECK25:       cond.end:
22041 // CHECK25-NEXT:    [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ]
22042 // CHECK25-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
22043 // CHECK25-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
22044 // CHECK25-NEXT:    store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4
22045 // CHECK25-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
22046 // CHECK25:       omp.inner.for.cond:
22047 // CHECK25-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
22048 // CHECK25-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
22049 // CHECK25-NEXT:    [[ADD10:%.*]] = add i32 [[TMP17]], 1
22050 // CHECK25-NEXT:    [[CMP11:%.*]] = icmp ult i32 [[TMP16]], [[ADD10]]
22051 // CHECK25-NEXT:    br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
22052 // CHECK25:       omp.inner.for.body:
22053 // CHECK25-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
22054 // CHECK25-NEXT:    [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
22055 // CHECK25-NEXT:    [[MUL:%.*]] = mul i32 [[TMP19]], 1
22056 // CHECK25-NEXT:    [[ADD12:%.*]] = add i32 [[TMP18]], [[MUL]]
22057 // CHECK25-NEXT:    store i32 [[ADD12]], i32* [[I8]], align 4
22058 // CHECK25-NEXT:    [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 8
22059 // CHECK25-NEXT:    [[ADD13:%.*]] = add nsw i32 [[TMP20]], 1
22060 // CHECK25-NEXT:    store i32 [[ADD13]], i32* [[CONV1]], align 8
22061 // CHECK25-NEXT:    [[TMP21:%.*]] = load i16, i16* [[CONV2]], align 8
22062 // CHECK25-NEXT:    [[CONV14:%.*]] = sext i16 [[TMP21]] to i32
22063 // CHECK25-NEXT:    [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1
22064 // CHECK25-NEXT:    [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16
22065 // CHECK25-NEXT:    store i16 [[CONV16]], i16* [[CONV2]], align 8
22066 // CHECK25-NEXT:    [[TMP22:%.*]] = load i8, i8* [[CONV3]], align 8
22067 // CHECK25-NEXT:    [[CONV17:%.*]] = sext i8 [[TMP22]] to i32
22068 // CHECK25-NEXT:    [[ADD18:%.*]] = add nsw i32 [[CONV17]], 1
22069 // CHECK25-NEXT:    [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8
22070 // CHECK25-NEXT:    store i8 [[CONV19]], i8* [[CONV3]], align 8
22071 // CHECK25-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
22072 // CHECK25-NEXT:    [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
22073 // CHECK25-NEXT:    [[ADD20:%.*]] = add nsw i32 [[TMP23]], 1
22074 // CHECK25-NEXT:    store i32 [[ADD20]], i32* [[ARRAYIDX]], align 4
22075 // CHECK25-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
22076 // CHECK25:       omp.body.continue:
22077 // CHECK25-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
22078 // CHECK25:       omp.inner.for.inc:
22079 // CHECK25-NEXT:    [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
22080 // CHECK25-NEXT:    [[ADD21:%.*]] = add i32 [[TMP24]], 1
22081 // CHECK25-NEXT:    store i32 [[ADD21]], i32* [[DOTOMP_IV]], align 4
22082 // CHECK25-NEXT:    br label [[OMP_INNER_FOR_COND]]
22083 // CHECK25:       omp.inner.for.end:
22084 // CHECK25-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
22085 // CHECK25:       omp.loop.exit:
22086 // CHECK25-NEXT:    [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
22087 // CHECK25-NEXT:    [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4
22088 // CHECK25-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]])
22089 // CHECK25-NEXT:    br label [[OMP_PRECOND_END]]
22090 // CHECK25:       omp.precond.end:
22091 // CHECK25-NEXT:    ret void
22092 //
22093 //
22094 // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218
22095 // CHECK25-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {
22096 // CHECK25-NEXT:  entry:
22097 // CHECK25-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
22098 // CHECK25-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
22099 // CHECK25-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
22100 // CHECK25-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
22101 // CHECK25-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 8
22102 // CHECK25-NEXT:    [[B_CASTED:%.*]] = alloca i64, align 8
22103 // CHECK25-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
22104 // CHECK25-NEXT:    store i64 [[B]], i64* [[B_ADDR]], align 8
22105 // CHECK25-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
22106 // CHECK25-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
22107 // CHECK25-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 8
22108 // CHECK25-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
22109 // CHECK25-NEXT:    [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
22110 // CHECK25-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
22111 // CHECK25-NEXT:    [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
22112 // CHECK25-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
22113 // CHECK25-NEXT:    [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
22114 // CHECK25-NEXT:    [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32*
22115 // CHECK25-NEXT:    store i32 [[TMP4]], i32* [[CONV3]], align 4
22116 // CHECK25-NEXT:    [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
22117 // CHECK25-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]])
22118 // CHECK25-NEXT:    ret void
22119 //
22120 //
22121 // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..5
22122 // CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {
22123 // CHECK25-NEXT:  entry:
22124 // CHECK25-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
22125 // CHECK25-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
22126 // CHECK25-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
22127 // CHECK25-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
22128 // CHECK25-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
22129 // CHECK25-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
22130 // CHECK25-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 8
22131 // CHECK25-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
22132 // CHECK25-NEXT:    [[TMP:%.*]] = alloca i32, align 4
22133 // CHECK25-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
22134 // CHECK25-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
22135 // CHECK25-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
22136 // CHECK25-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
22137 // CHECK25-NEXT:    [[I:%.*]] = alloca i32, align 4
22138 // CHECK25-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
22139 // CHECK25-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
22140 // CHECK25-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
22141 // CHECK25-NEXT:    store i64 [[B]], i64* [[B_ADDR]], align 8
22142 // CHECK25-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
22143 // CHECK25-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
22144 // CHECK25-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 8
22145 // CHECK25-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
22146 // CHECK25-NEXT:    [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
22147 // CHECK25-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
22148 // CHECK25-NEXT:    [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
22149 // CHECK25-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
22150 // CHECK25-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
22151 // CHECK25-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
22152 // CHECK25-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
22153 // CHECK25-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
22154 // CHECK25-NEXT:    [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
22155 // CHECK25-NEXT:    [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
22156 // CHECK25-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
22157 // CHECK25-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
22158 // CHECK25-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 9
22159 // CHECK25-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
22160 // CHECK25:       cond.true:
22161 // CHECK25-NEXT:    br label [[COND_END:%.*]]
22162 // CHECK25:       cond.false:
22163 // CHECK25-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
22164 // CHECK25-NEXT:    br label [[COND_END]]
22165 // CHECK25:       cond.end:
22166 // CHECK25-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
22167 // CHECK25-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
22168 // CHECK25-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
22169 // CHECK25-NEXT:    store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
22170 // CHECK25-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
22171 // CHECK25:       omp.inner.for.cond:
22172 // CHECK25-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
22173 // CHECK25-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
22174 // CHECK25-NEXT:    [[CMP3:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
22175 // CHECK25-NEXT:    br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
22176 // CHECK25:       omp.inner.for.body:
22177 // CHECK25-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
22178 // CHECK25-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
22179 // CHECK25-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
22180 // CHECK25-NEXT:    store i32 [[ADD]], i32* [[I]], align 4
22181 // CHECK25-NEXT:    [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8
22182 // CHECK25-NEXT:    [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double
22183 // CHECK25-NEXT:    [[ADD5:%.*]] = fadd double [[CONV4]], 1.500000e+00
22184 // CHECK25-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
22185 // CHECK25-NEXT:    store double [[ADD5]], double* [[A]], align 8
22186 // CHECK25-NEXT:    [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
22187 // CHECK25-NEXT:    [[TMP13:%.*]] = load double, double* [[A6]], align 8
22188 // CHECK25-NEXT:    [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00
22189 // CHECK25-NEXT:    store double [[INC]], double* [[A6]], align 8
22190 // CHECK25-NEXT:    [[CONV7:%.*]] = fptosi double [[INC]] to i16
22191 // CHECK25-NEXT:    [[TMP14:%.*]] = mul nsw i64 1, [[TMP2]]
22192 // CHECK25-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP14]]
22193 // CHECK25-NEXT:    [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
22194 // CHECK25-NEXT:    store i16 [[CONV7]], i16* [[ARRAYIDX8]], align 2
22195 // CHECK25-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
22196 // CHECK25:       omp.body.continue:
22197 // CHECK25-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
22198 // CHECK25:       omp.inner.for.inc:
22199 // CHECK25-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
22200 // CHECK25-NEXT:    [[ADD9:%.*]] = add nsw i32 [[TMP15]], 1
22201 // CHECK25-NEXT:    store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4
22202 // CHECK25-NEXT:    br label [[OMP_INNER_FOR_COND]]
22203 // CHECK25:       omp.inner.for.end:
22204 // CHECK25-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
22205 // CHECK25:       omp.loop.exit:
22206 // CHECK25-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
22207 // CHECK25-NEXT:    ret void
22208 //
22209 //
22210 // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183
22211 // CHECK25-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
22212 // CHECK25-NEXT:  entry:
22213 // CHECK25-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
22214 // CHECK25-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
22215 // CHECK25-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
22216 // CHECK25-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
22217 // CHECK25-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
22218 // CHECK25-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
22219 // CHECK25-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
22220 // CHECK25-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
22221 // CHECK25-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
22222 // CHECK25-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
22223 // CHECK25-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
22224 // CHECK25-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
22225 // CHECK25-NEXT:    [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
22226 // CHECK25-NEXT:    store i32 [[TMP1]], i32* [[CONV2]], align 4
22227 // CHECK25-NEXT:    [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
22228 // CHECK25-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
22229 // CHECK25-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
22230 // CHECK25-NEXT:    store i16 [[TMP3]], i16* [[CONV3]], align 2
22231 // CHECK25-NEXT:    [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
22232 // CHECK25-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]])
22233 // CHECK25-NEXT:    ret void
22234 //
22235 //
22236 // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..6
22237 // CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
22238 // CHECK25-NEXT:  entry:
22239 // CHECK25-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
22240 // CHECK25-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
22241 // CHECK25-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
22242 // CHECK25-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
22243 // CHECK25-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
22244 // CHECK25-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
22245 // CHECK25-NEXT:    [[TMP:%.*]] = alloca i32, align 4
22246 // CHECK25-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
22247 // CHECK25-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
22248 // CHECK25-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
22249 // CHECK25-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
22250 // CHECK25-NEXT:    [[I:%.*]] = alloca i32, align 4
22251 // CHECK25-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
22252 // CHECK25-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
22253 // CHECK25-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
22254 // CHECK25-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
22255 // CHECK25-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
22256 // CHECK25-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
22257 // CHECK25-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
22258 // CHECK25-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
22259 // CHECK25-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
22260 // CHECK25-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
22261 // CHECK25-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
22262 // CHECK25-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
22263 // CHECK25-NEXT:    [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
22264 // CHECK25-NEXT:    [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
22265 // CHECK25-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
22266 // CHECK25-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
22267 // CHECK25-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9
22268 // CHECK25-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
22269 // CHECK25:       cond.true:
22270 // CHECK25-NEXT:    br label [[COND_END:%.*]]
22271 // CHECK25:       cond.false:
22272 // CHECK25-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
22273 // CHECK25-NEXT:    br label [[COND_END]]
22274 // CHECK25:       cond.end:
22275 // CHECK25-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
22276 // CHECK25-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
22277 // CHECK25-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
22278 // CHECK25-NEXT:    store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
22279 // CHECK25-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
22280 // CHECK25:       omp.inner.for.cond:
22281 // CHECK25-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
22282 // CHECK25-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
22283 // CHECK25-NEXT:    [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
22284 // CHECK25-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
22285 // CHECK25:       omp.inner.for.body:
22286 // CHECK25-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
22287 // CHECK25-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
22288 // CHECK25-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
22289 // CHECK25-NEXT:    store i32 [[ADD]], i32* [[I]], align 4
22290 // CHECK25-NEXT:    [[TMP9:%.*]] = load i32, i32* [[CONV]], align 8
22291 // CHECK25-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1
22292 // CHECK25-NEXT:    store i32 [[ADD3]], i32* [[CONV]], align 8
22293 // CHECK25-NEXT:    [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 8
22294 // CHECK25-NEXT:    [[CONV4:%.*]] = sext i16 [[TMP10]] to i32
22295 // CHECK25-NEXT:    [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
22296 // CHECK25-NEXT:    [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
22297 // CHECK25-NEXT:    store i16 [[CONV6]], i16* [[CONV1]], align 8
22298 // CHECK25-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
22299 // CHECK25-NEXT:    [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
22300 // CHECK25-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1
22301 // CHECK25-NEXT:    store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4
22302 // CHECK25-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
22303 // CHECK25:       omp.body.continue:
22304 // CHECK25-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
22305 // CHECK25:       omp.inner.for.inc:
22306 // CHECK25-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
22307 // CHECK25-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP12]], 1
22308 // CHECK25-NEXT:    store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4
22309 // CHECK25-NEXT:    br label [[OMP_INNER_FOR_COND]]
22310 // CHECK25:       omp.inner.for.end:
22311 // CHECK25-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
22312 // CHECK25:       omp.loop.exit:
22313 // CHECK25-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
22314 // CHECK25-NEXT:    ret void
22315 //
22316 //
22317 // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103
22318 // CHECK26-SAME: (i64 [[AA:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] {
22319 // CHECK26-NEXT:  entry:
22320 // CHECK26-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
22321 // CHECK26-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
22322 // CHECK26-NEXT:    [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8
22323 // CHECK26-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
22324 // CHECK26-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]])
22325 // CHECK26-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
22326 // CHECK26-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
22327 // CHECK26-NEXT:    store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8
22328 // CHECK26-NEXT:    [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
22329 // CHECK26-NEXT:    [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
22330 // CHECK26-NEXT:    [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32*
22331 // CHECK26-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 8
22332 // CHECK26-NEXT:    [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 8
22333 // CHECK26-NEXT:    call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
22334 // CHECK26-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV]], align 8
22335 // CHECK26-NEXT:    [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
22336 // CHECK26-NEXT:    store i16 [[TMP3]], i16* [[CONV5]], align 2
22337 // CHECK26-NEXT:    [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
22338 // CHECK26-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]])
22339 // CHECK26-NEXT:    ret void
22340 //
22341 //
22342 // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined.
22343 // CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] {
22344 // CHECK26-NEXT:  entry:
22345 // CHECK26-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
22346 // CHECK26-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
22347 // CHECK26-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
22348 // CHECK26-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
22349 // CHECK26-NEXT:    [[TMP:%.*]] = alloca i32, align 4
22350 // CHECK26-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
22351 // CHECK26-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
22352 // CHECK26-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
22353 // CHECK26-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
22354 // CHECK26-NEXT:    [[I:%.*]] = alloca i32, align 4
22355 // CHECK26-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
22356 // CHECK26-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
22357 // CHECK26-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
22358 // CHECK26-NEXT:    [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
22359 // CHECK26-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
22360 // CHECK26-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
22361 // CHECK26-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
22362 // CHECK26-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
22363 // CHECK26-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
22364 // CHECK26-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
22365 // CHECK26-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
22366 // CHECK26-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
22367 // CHECK26-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
22368 // CHECK26-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
22369 // CHECK26:       cond.true:
22370 // CHECK26-NEXT:    br label [[COND_END:%.*]]
22371 // CHECK26:       cond.false:
22372 // CHECK26-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
22373 // CHECK26-NEXT:    br label [[COND_END]]
22374 // CHECK26:       cond.end:
22375 // CHECK26-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
22376 // CHECK26-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
22377 // CHECK26-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
22378 // CHECK26-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
22379 // CHECK26-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
22380 // CHECK26:       omp.inner.for.cond:
22381 // CHECK26-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
22382 // CHECK26-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
22383 // CHECK26-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
22384 // CHECK26-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
22385 // CHECK26:       omp.inner.for.body:
22386 // CHECK26-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
22387 // CHECK26-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
22388 // CHECK26-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
22389 // CHECK26-NEXT:    store i32 [[ADD]], i32* [[I]], align 4
22390 // CHECK26-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
22391 // CHECK26:       omp.body.continue:
22392 // CHECK26-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
22393 // CHECK26:       omp.inner.for.inc:
22394 // CHECK26-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
22395 // CHECK26-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
22396 // CHECK26-NEXT:    store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4
22397 // CHECK26-NEXT:    br label [[OMP_INNER_FOR_COND]]
22398 // CHECK26:       omp.inner.for.end:
22399 // CHECK26-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
22400 // CHECK26:       omp.loop.exit:
22401 // CHECK26-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
22402 // CHECK26-NEXT:    ret void
22403 //
22404 //
22405 // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113
22406 // CHECK26-SAME: (i64 [[AA:%.*]]) #[[ATTR0]] {
22407 // CHECK26-NEXT:  entry:
22408 // CHECK26-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
22409 // CHECK26-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
22410 // CHECK26-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
22411 // CHECK26-NEXT:    [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
22412 // CHECK26-NEXT:    [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8
22413 // CHECK26-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
22414 // CHECK26-NEXT:    store i16 [[TMP0]], i16* [[CONV1]], align 2
22415 // CHECK26-NEXT:    [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
22416 // CHECK26-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]])
22417 // CHECK26-NEXT:    ret void
22418 //
22419 //
22420 // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..1
22421 // CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] {
22422 // CHECK26-NEXT:  entry:
22423 // CHECK26-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
22424 // CHECK26-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
22425 // CHECK26-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
22426 // CHECK26-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
22427 // CHECK26-NEXT:    [[TMP:%.*]] = alloca i32, align 4
22428 // CHECK26-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
22429 // CHECK26-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
22430 // CHECK26-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
22431 // CHECK26-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
22432 // CHECK26-NEXT:    [[I:%.*]] = alloca i32, align 4
22433 // CHECK26-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
22434 // CHECK26-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
22435 // CHECK26-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
22436 // CHECK26-NEXT:    [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
22437 // CHECK26-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
22438 // CHECK26-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
22439 // CHECK26-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
22440 // CHECK26-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
22441 // CHECK26-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
22442 // CHECK26-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
22443 // CHECK26-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
22444 // CHECK26-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
22445 // CHECK26-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
22446 // CHECK26-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
22447 // CHECK26:       cond.true:
22448 // CHECK26-NEXT:    br label [[COND_END:%.*]]
22449 // CHECK26:       cond.false:
22450 // CHECK26-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
22451 // CHECK26-NEXT:    br label [[COND_END]]
22452 // CHECK26:       cond.end:
22453 // CHECK26-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
22454 // CHECK26-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
22455 // CHECK26-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
22456 // CHECK26-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
22457 // CHECK26-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
22458 // CHECK26:       omp.inner.for.cond:
22459 // CHECK26-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
22460 // CHECK26-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
22461 // CHECK26-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
22462 // CHECK26-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
22463 // CHECK26:       omp.inner.for.body:
22464 // CHECK26-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
22465 // CHECK26-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
22466 // CHECK26-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
22467 // CHECK26-NEXT:    store i32 [[ADD]], i32* [[I]], align 4
22468 // CHECK26-NEXT:    [[TMP8:%.*]] = load i16, i16* [[CONV]], align 8
22469 // CHECK26-NEXT:    [[CONV2:%.*]] = sext i16 [[TMP8]] to i32
22470 // CHECK26-NEXT:    [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
22471 // CHECK26-NEXT:    [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
22472 // CHECK26-NEXT:    store i16 [[CONV4]], i16* [[CONV]], align 8
22473 // CHECK26-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
22474 // CHECK26:       omp.body.continue:
22475 // CHECK26-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
22476 // CHECK26:       omp.inner.for.inc:
22477 // CHECK26-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
22478 // CHECK26-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP9]], 1
22479 // CHECK26-NEXT:    store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4
22480 // CHECK26-NEXT:    br label [[OMP_INNER_FOR_COND]]
22481 // CHECK26:       omp.inner.for.end:
22482 // CHECK26-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
22483 // CHECK26:       omp.loop.exit:
22484 // CHECK26-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
22485 // CHECK26-NEXT:    ret void
22486 //
22487 //
22488 // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120
22489 // CHECK26-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] {
22490 // CHECK26-NEXT:  entry:
22491 // CHECK26-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
22492 // CHECK26-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
22493 // CHECK26-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
22494 // CHECK26-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
22495 // CHECK26-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
22496 // CHECK26-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
22497 // CHECK26-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
22498 // CHECK26-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
22499 // CHECK26-NEXT:    [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
22500 // CHECK26-NEXT:    [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
22501 // CHECK26-NEXT:    store i32 [[TMP0]], i32* [[CONV2]], align 4
22502 // CHECK26-NEXT:    [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
22503 // CHECK26-NEXT:    [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
22504 // CHECK26-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
22505 // CHECK26-NEXT:    store i16 [[TMP2]], i16* [[CONV3]], align 2
22506 // CHECK26-NEXT:    [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
22507 // CHECK26-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
22508 // CHECK26-NEXT:    ret void
22509 //
22510 //
22511 // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..2
22512 // CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] {
22513 // CHECK26-NEXT:  entry:
22514 // CHECK26-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
22515 // CHECK26-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
22516 // CHECK26-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
22517 // CHECK26-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
22518 // CHECK26-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
22519 // CHECK26-NEXT:    [[TMP:%.*]] = alloca i32, align 4
22520 // CHECK26-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
22521 // CHECK26-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
22522 // CHECK26-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
22523 // CHECK26-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
22524 // CHECK26-NEXT:    [[I:%.*]] = alloca i32, align 4
22525 // CHECK26-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
22526 // CHECK26-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
22527 // CHECK26-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
22528 // CHECK26-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
22529 // CHECK26-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
22530 // CHECK26-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
22531 // CHECK26-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
22532 // CHECK26-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
22533 // CHECK26-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
22534 // CHECK26-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
22535 // CHECK26-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
22536 // CHECK26-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
22537 // CHECK26-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
22538 // CHECK26-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
22539 // CHECK26-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
22540 // CHECK26-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
22541 // CHECK26:       cond.true:
22542 // CHECK26-NEXT:    br label [[COND_END:%.*]]
22543 // CHECK26:       cond.false:
22544 // CHECK26-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
22545 // CHECK26-NEXT:    br label [[COND_END]]
22546 // CHECK26:       cond.end:
22547 // CHECK26-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
22548 // CHECK26-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
22549 // CHECK26-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
22550 // CHECK26-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
22551 // CHECK26-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
22552 // CHECK26:       omp.inner.for.cond:
22553 // CHECK26-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
22554 // CHECK26-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
22555 // CHECK26-NEXT:    [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
22556 // CHECK26-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
22557 // CHECK26:       omp.inner.for.body:
22558 // CHECK26-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
22559 // CHECK26-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
22560 // CHECK26-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
22561 // CHECK26-NEXT:    store i32 [[ADD]], i32* [[I]], align 4
22562 // CHECK26-NEXT:    [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
22563 // CHECK26-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
22564 // CHECK26-NEXT:    store i32 [[ADD3]], i32* [[CONV]], align 8
22565 // CHECK26-NEXT:    [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 8
22566 // CHECK26-NEXT:    [[CONV4:%.*]] = sext i16 [[TMP9]] to i32
22567 // CHECK26-NEXT:    [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
22568 // CHECK26-NEXT:    [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
22569 // CHECK26-NEXT:    store i16 [[CONV6]], i16* [[CONV1]], align 8
22570 // CHECK26-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
22571 // CHECK26:       omp.body.continue:
22572 // CHECK26-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
22573 // CHECK26:       omp.inner.for.inc:
22574 // CHECK26-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
22575 // CHECK26-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1
22576 // CHECK26-NEXT:    store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4
22577 // CHECK26-NEXT:    br label [[OMP_INNER_FOR_COND]]
22578 // CHECK26:       omp.inner.for.end:
22579 // CHECK26-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
22580 // CHECK26:       omp.loop.exit:
22581 // CHECK26-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
22582 // CHECK26-NEXT:    ret void
22583 //
22584 //
22585 // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145
22586 // CHECK26-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
22587 // CHECK26-NEXT:  entry:
22588 // CHECK26-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
22589 // CHECK26-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
22590 // CHECK26-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
22591 // CHECK26-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 8
22592 // CHECK26-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
22593 // CHECK26-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
22594 // CHECK26-NEXT:    [[VLA_ADDR4:%.*]] = alloca i64, align 8
22595 // CHECK26-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 8
22596 // CHECK26-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
22597 // CHECK26-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
22598 // CHECK26-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
22599 // CHECK26-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
22600 // CHECK26-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
22601 // CHECK26-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
22602 // CHECK26-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
22603 // CHECK26-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 8
22604 // CHECK26-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
22605 // CHECK26-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
22606 // CHECK26-NEXT:    store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
22607 // CHECK26-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 8
22608 // CHECK26-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
22609 // CHECK26-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
22610 // CHECK26-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
22611 // CHECK26-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
22612 // CHECK26-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
22613 // CHECK26-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
22614 // CHECK26-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
22615 // CHECK26-NEXT:    [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
22616 // CHECK26-NEXT:    [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
22617 // CHECK26-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
22618 // CHECK26-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
22619 // CHECK26-NEXT:    [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
22620 // CHECK26-NEXT:    [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
22621 // CHECK26-NEXT:    [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32*
22622 // CHECK26-NEXT:    store i32 [[TMP8]], i32* [[CONV6]], align 4
22623 // CHECK26-NEXT:    [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
22624 // CHECK26-NEXT:    [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 8
22625 // CHECK26-NEXT:    [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
22626 // CHECK26-NEXT:    store i32 [[TMP10]], i32* [[CONV7]], align 4
22627 // CHECK26-NEXT:    [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
22628 // CHECK26-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]])
22629 // CHECK26-NEXT:    ret void
22630 //
22631 //
22632 // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..3
22633 // CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
22634 // CHECK26-NEXT:  entry:
22635 // CHECK26-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
22636 // CHECK26-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
22637 // CHECK26-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
22638 // CHECK26-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
22639 // CHECK26-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
22640 // CHECK26-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 8
22641 // CHECK26-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
22642 // CHECK26-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
22643 // CHECK26-NEXT:    [[VLA_ADDR4:%.*]] = alloca i64, align 8
22644 // CHECK26-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 8
22645 // CHECK26-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
22646 // CHECK26-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
22647 // CHECK26-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
22648 // CHECK26-NEXT:    [[TMP:%.*]] = alloca i32, align 4
22649 // CHECK26-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
22650 // CHECK26-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
22651 // CHECK26-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
22652 // CHECK26-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
22653 // CHECK26-NEXT:    [[I:%.*]] = alloca i32, align 4
22654 // CHECK26-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
22655 // CHECK26-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
22656 // CHECK26-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
22657 // CHECK26-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
22658 // CHECK26-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
22659 // CHECK26-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 8
22660 // CHECK26-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
22661 // CHECK26-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
22662 // CHECK26-NEXT:    store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
22663 // CHECK26-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 8
22664 // CHECK26-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
22665 // CHECK26-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
22666 // CHECK26-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
22667 // CHECK26-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
22668 // CHECK26-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
22669 // CHECK26-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
22670 // CHECK26-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
22671 // CHECK26-NEXT:    [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
22672 // CHECK26-NEXT:    [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
22673 // CHECK26-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
22674 // CHECK26-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
22675 // CHECK26-NEXT:    [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
22676 // CHECK26-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
22677 // CHECK26-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
22678 // CHECK26-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
22679 // CHECK26-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
22680 // CHECK26-NEXT:    [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 8
22681 // CHECK26-NEXT:    [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
22682 // CHECK26-NEXT:    [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
22683 // CHECK26-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
22684 // CHECK26-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
22685 // CHECK26:       omp.dispatch.cond:
22686 // CHECK26-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
22687 // CHECK26-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 9
22688 // CHECK26-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
22689 // CHECK26:       cond.true:
22690 // CHECK26-NEXT:    br label [[COND_END:%.*]]
22691 // CHECK26:       cond.false:
22692 // CHECK26-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
22693 // CHECK26-NEXT:    br label [[COND_END]]
22694 // CHECK26:       cond.end:
22695 // CHECK26-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
22696 // CHECK26-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
22697 // CHECK26-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
22698 // CHECK26-NEXT:    store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
22699 // CHECK26-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
22700 // CHECK26-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
22701 // CHECK26-NEXT:    [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
22702 // CHECK26-NEXT:    br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
22703 // CHECK26:       omp.dispatch.body:
22704 // CHECK26-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
22705 // CHECK26:       omp.inner.for.cond:
22706 // CHECK26-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
22707 // CHECK26-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !11
22708 // CHECK26-NEXT:    [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
22709 // CHECK26-NEXT:    br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
22710 // CHECK26:       omp.inner.for.body:
22711 // CHECK26-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
22712 // CHECK26-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
22713 // CHECK26-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
22714 // CHECK26-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11
22715 // CHECK26-NEXT:    [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8, !llvm.access.group !11
22716 // CHECK26-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP19]], 1
22717 // CHECK26-NEXT:    store i32 [[ADD8]], i32* [[CONV]], align 8, !llvm.access.group !11
22718 // CHECK26-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
22719 // CHECK26-NEXT:    [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !11
22720 // CHECK26-NEXT:    [[CONV9:%.*]] = fpext float [[TMP20]] to double
22721 // CHECK26-NEXT:    [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00
22722 // CHECK26-NEXT:    [[CONV11:%.*]] = fptrunc double [[ADD10]] to float
22723 // CHECK26-NEXT:    store float [[CONV11]], float* [[ARRAYIDX]], align 4, !llvm.access.group !11
22724 // CHECK26-NEXT:    [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3
22725 // CHECK26-NEXT:    [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4, !llvm.access.group !11
22726 // CHECK26-NEXT:    [[CONV13:%.*]] = fpext float [[TMP21]] to double
22727 // CHECK26-NEXT:    [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00
22728 // CHECK26-NEXT:    [[CONV15:%.*]] = fptrunc double [[ADD14]] to float
22729 // CHECK26-NEXT:    store float [[CONV15]], float* [[ARRAYIDX12]], align 4, !llvm.access.group !11
22730 // CHECK26-NEXT:    [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1
22731 // CHECK26-NEXT:    [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i64 0, i64 2
22732 // CHECK26-NEXT:    [[TMP22:%.*]] = load double, double* [[ARRAYIDX17]], align 8, !llvm.access.group !11
22733 // CHECK26-NEXT:    [[ADD18:%.*]] = fadd double [[TMP22]], 1.000000e+00
22734 // CHECK26-NEXT:    store double [[ADD18]], double* [[ARRAYIDX17]], align 8, !llvm.access.group !11
22735 // CHECK26-NEXT:    [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]]
22736 // CHECK26-NEXT:    [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP23]]
22737 // CHECK26-NEXT:    [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i64 3
22738 // CHECK26-NEXT:    [[TMP24:%.*]] = load double, double* [[ARRAYIDX20]], align 8, !llvm.access.group !11
22739 // CHECK26-NEXT:    [[ADD21:%.*]] = fadd double [[TMP24]], 1.000000e+00
22740 // CHECK26-NEXT:    store double [[ADD21]], double* [[ARRAYIDX20]], align 8, !llvm.access.group !11
22741 // CHECK26-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0
22742 // CHECK26-NEXT:    [[TMP25:%.*]] = load i64, i64* [[X]], align 8, !llvm.access.group !11
22743 // CHECK26-NEXT:    [[ADD22:%.*]] = add nsw i64 [[TMP25]], 1
22744 // CHECK26-NEXT:    store i64 [[ADD22]], i64* [[X]], align 8, !llvm.access.group !11
22745 // CHECK26-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1
22746 // CHECK26-NEXT:    [[TMP26:%.*]] = load i8, i8* [[Y]], align 8, !llvm.access.group !11
22747 // CHECK26-NEXT:    [[CONV23:%.*]] = sext i8 [[TMP26]] to i32
22748 // CHECK26-NEXT:    [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1
22749 // CHECK26-NEXT:    [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8
22750 // CHECK26-NEXT:    store i8 [[CONV25]], i8* [[Y]], align 8, !llvm.access.group !11
22751 // CHECK26-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
22752 // CHECK26:       omp.body.continue:
22753 // CHECK26-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
22754 // CHECK26:       omp.inner.for.inc:
22755 // CHECK26-NEXT:    [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
22756 // CHECK26-NEXT:    [[ADD26:%.*]] = add nsw i32 [[TMP27]], 1
22757 // CHECK26-NEXT:    store i32 [[ADD26]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
22758 // CHECK26-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]
22759 // CHECK26:       omp.inner.for.end:
22760 // CHECK26-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
22761 // CHECK26:       omp.dispatch.inc:
22762 // CHECK26-NEXT:    [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
22763 // CHECK26-NEXT:    [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
22764 // CHECK26-NEXT:    [[ADD27:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]
22765 // CHECK26-NEXT:    store i32 [[ADD27]], i32* [[DOTOMP_LB]], align 4
22766 // CHECK26-NEXT:    [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
22767 // CHECK26-NEXT:    [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
22768 // CHECK26-NEXT:    [[ADD28:%.*]] = add nsw i32 [[TMP30]], [[TMP31]]
22769 // CHECK26-NEXT:    store i32 [[ADD28]], i32* [[DOTOMP_UB]], align 4
22770 // CHECK26-NEXT:    br label [[OMP_DISPATCH_COND]]
22771 // CHECK26:       omp.dispatch.end:
22772 // CHECK26-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]])
22773 // CHECK26-NEXT:    ret void
22774 //
22775 //
22776 // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200
22777 // CHECK26-SAME: (i64 [[N:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
22778 // CHECK26-NEXT:  entry:
22779 // CHECK26-NEXT:    [[N_ADDR:%.*]] = alloca i64, align 8
22780 // CHECK26-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
22781 // CHECK26-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
22782 // CHECK26-NEXT:    [[AAA_ADDR:%.*]] = alloca i64, align 8
22783 // CHECK26-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
22784 // CHECK26-NEXT:    [[N_CASTED:%.*]] = alloca i64, align 8
22785 // CHECK26-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
22786 // CHECK26-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
22787 // CHECK26-NEXT:    [[AAA_CASTED:%.*]] = alloca i64, align 8
22788 // CHECK26-NEXT:    store i64 [[N]], i64* [[N_ADDR]], align 8
22789 // CHECK26-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
22790 // CHECK26-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
22791 // CHECK26-NEXT:    store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
22792 // CHECK26-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
22793 // CHECK26-NEXT:    [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
22794 // CHECK26-NEXT:    [[CONV1:%.*]] = bitcast i64* [[A_ADDR]] to i32*
22795 // CHECK26-NEXT:    [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
22796 // CHECK26-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
22797 // CHECK26-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
22798 // CHECK26-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
22799 // CHECK26-NEXT:    [[CONV4:%.*]] = bitcast i64* [[N_CASTED]] to i32*
22800 // CHECK26-NEXT:    store i32 [[TMP1]], i32* [[CONV4]], align 4
22801 // CHECK26-NEXT:    [[TMP2:%.*]] = load i64, i64* [[N_CASTED]], align 8
22802 // CHECK26-NEXT:    [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 8
22803 // CHECK26-NEXT:    [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
22804 // CHECK26-NEXT:    store i32 [[TMP3]], i32* [[CONV5]], align 4
22805 // CHECK26-NEXT:    [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8
22806 // CHECK26-NEXT:    [[TMP5:%.*]] = load i16, i16* [[CONV2]], align 8
22807 // CHECK26-NEXT:    [[CONV6:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
22808 // CHECK26-NEXT:    store i16 [[TMP5]], i16* [[CONV6]], align 2
22809 // CHECK26-NEXT:    [[TMP6:%.*]] = load i64, i64* [[AA_CASTED]], align 8
22810 // CHECK26-NEXT:    [[TMP7:%.*]] = load i8, i8* [[CONV3]], align 8
22811 // CHECK26-NEXT:    [[CONV7:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
22812 // CHECK26-NEXT:    store i8 [[TMP7]], i8* [[CONV7]], align 1
22813 // CHECK26-NEXT:    [[TMP8:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
22814 // CHECK26-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]], [10 x i32]* [[TMP0]])
22815 // CHECK26-NEXT:    ret void
22816 //
22817 //
22818 // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..4
22819 // CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
22820 // CHECK26-NEXT:  entry:
22821 // CHECK26-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
22822 // CHECK26-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
22823 // CHECK26-NEXT:    [[N_ADDR:%.*]] = alloca i64, align 8
22824 // CHECK26-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
22825 // CHECK26-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
22826 // CHECK26-NEXT:    [[AAA_ADDR:%.*]] = alloca i64, align 8
22827 // CHECK26-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
22828 // CHECK26-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
22829 // CHECK26-NEXT:    [[TMP:%.*]] = alloca i32, align 4
22830 // CHECK26-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
22831 // CHECK26-NEXT:    [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4
22832 // CHECK26-NEXT:    [[DOTCAPTURE_EXPR_5:%.*]] = alloca i32, align 4
22833 // CHECK26-NEXT:    [[I:%.*]] = alloca i32, align 4
22834 // CHECK26-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
22835 // CHECK26-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
22836 // CHECK26-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
22837 // CHECK26-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
22838 // CHECK26-NEXT:    [[I8:%.*]] = alloca i32, align 4
22839 // CHECK26-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
22840 // CHECK26-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
22841 // CHECK26-NEXT:    store i64 [[N]], i64* [[N_ADDR]], align 8
22842 // CHECK26-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
22843 // CHECK26-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
22844 // CHECK26-NEXT:    store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
22845 // CHECK26-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
22846 // CHECK26-NEXT:    [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*
22847 // CHECK26-NEXT:    [[CONV1:%.*]] = bitcast i64* [[A_ADDR]] to i32*
22848 // CHECK26-NEXT:    [[CONV2:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
22849 // CHECK26-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
22850 // CHECK26-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
22851 // CHECK26-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV1]], align 8
22852 // CHECK26-NEXT:    store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
22853 // CHECK26-NEXT:    [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
22854 // CHECK26-NEXT:    store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_4]], align 4
22855 // CHECK26-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4
22856 // CHECK26-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
22857 // CHECK26-NEXT:    [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]]
22858 // CHECK26-NEXT:    [[SUB6:%.*]] = sub i32 [[SUB]], 1
22859 // CHECK26-NEXT:    [[ADD:%.*]] = add i32 [[SUB6]], 1
22860 // CHECK26-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], 1
22861 // CHECK26-NEXT:    [[SUB7:%.*]] = sub i32 [[DIV]], 1
22862 // CHECK26-NEXT:    store i32 [[SUB7]], i32* [[DOTCAPTURE_EXPR_5]], align 4
22863 // CHECK26-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
22864 // CHECK26-NEXT:    store i32 [[TMP5]], i32* [[I]], align 4
22865 // CHECK26-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
22866 // CHECK26-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4
22867 // CHECK26-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]]
22868 // CHECK26-NEXT:    br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
22869 // CHECK26:       omp.precond.then:
22870 // CHECK26-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
22871 // CHECK26-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4
22872 // CHECK26-NEXT:    store i32 [[TMP8]], i32* [[DOTOMP_UB]], align 4
22873 // CHECK26-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
22874 // CHECK26-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
22875 // CHECK26-NEXT:    [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
22876 // CHECK26-NEXT:    [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
22877 // CHECK26-NEXT:    call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
22878 // CHECK26-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
22879 // CHECK26-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4
22880 // CHECK26-NEXT:    [[CMP9:%.*]] = icmp ugt i32 [[TMP11]], [[TMP12]]
22881 // CHECK26-NEXT:    br i1 [[CMP9]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
22882 // CHECK26:       cond.true:
22883 // CHECK26-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4
22884 // CHECK26-NEXT:    br label [[COND_END:%.*]]
22885 // CHECK26:       cond.false:
22886 // CHECK26-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
22887 // CHECK26-NEXT:    br label [[COND_END]]
22888 // CHECK26:       cond.end:
22889 // CHECK26-NEXT:    [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ]
22890 // CHECK26-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
22891 // CHECK26-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
22892 // CHECK26-NEXT:    store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4
22893 // CHECK26-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
22894 // CHECK26:       omp.inner.for.cond:
22895 // CHECK26-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
22896 // CHECK26-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
22897 // CHECK26-NEXT:    [[ADD10:%.*]] = add i32 [[TMP17]], 1
22898 // CHECK26-NEXT:    [[CMP11:%.*]] = icmp ult i32 [[TMP16]], [[ADD10]]
22899 // CHECK26-NEXT:    br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
22900 // CHECK26:       omp.inner.for.body:
22901 // CHECK26-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
22902 // CHECK26-NEXT:    [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
22903 // CHECK26-NEXT:    [[MUL:%.*]] = mul i32 [[TMP19]], 1
22904 // CHECK26-NEXT:    [[ADD12:%.*]] = add i32 [[TMP18]], [[MUL]]
22905 // CHECK26-NEXT:    store i32 [[ADD12]], i32* [[I8]], align 4
22906 // CHECK26-NEXT:    [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 8
22907 // CHECK26-NEXT:    [[ADD13:%.*]] = add nsw i32 [[TMP20]], 1
22908 // CHECK26-NEXT:    store i32 [[ADD13]], i32* [[CONV1]], align 8
22909 // CHECK26-NEXT:    [[TMP21:%.*]] = load i16, i16* [[CONV2]], align 8
22910 // CHECK26-NEXT:    [[CONV14:%.*]] = sext i16 [[TMP21]] to i32
22911 // CHECK26-NEXT:    [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1
22912 // CHECK26-NEXT:    [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16
22913 // CHECK26-NEXT:    store i16 [[CONV16]], i16* [[CONV2]], align 8
22914 // CHECK26-NEXT:    [[TMP22:%.*]] = load i8, i8* [[CONV3]], align 8
22915 // CHECK26-NEXT:    [[CONV17:%.*]] = sext i8 [[TMP22]] to i32
22916 // CHECK26-NEXT:    [[ADD18:%.*]] = add nsw i32 [[CONV17]], 1
22917 // CHECK26-NEXT:    [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8
22918 // CHECK26-NEXT:    store i8 [[CONV19]], i8* [[CONV3]], align 8
22919 // CHECK26-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
22920 // CHECK26-NEXT:    [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
22921 // CHECK26-NEXT:    [[ADD20:%.*]] = add nsw i32 [[TMP23]], 1
22922 // CHECK26-NEXT:    store i32 [[ADD20]], i32* [[ARRAYIDX]], align 4
22923 // CHECK26-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
22924 // CHECK26:       omp.body.continue:
22925 // CHECK26-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
22926 // CHECK26:       omp.inner.for.inc:
22927 // CHECK26-NEXT:    [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
22928 // CHECK26-NEXT:    [[ADD21:%.*]] = add i32 [[TMP24]], 1
22929 // CHECK26-NEXT:    store i32 [[ADD21]], i32* [[DOTOMP_IV]], align 4
22930 // CHECK26-NEXT:    br label [[OMP_INNER_FOR_COND]]
22931 // CHECK26:       omp.inner.for.end:
22932 // CHECK26-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
22933 // CHECK26:       omp.loop.exit:
22934 // CHECK26-NEXT:    [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
22935 // CHECK26-NEXT:    [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4
22936 // CHECK26-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]])
22937 // CHECK26-NEXT:    br label [[OMP_PRECOND_END]]
22938 // CHECK26:       omp.precond.end:
22939 // CHECK26-NEXT:    ret void
22940 //
22941 //
22942 // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218
22943 // CHECK26-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {
22944 // CHECK26-NEXT:  entry:
22945 // CHECK26-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
22946 // CHECK26-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
22947 // CHECK26-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
22948 // CHECK26-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
22949 // CHECK26-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 8
22950 // CHECK26-NEXT:    [[B_CASTED:%.*]] = alloca i64, align 8
22951 // CHECK26-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
22952 // CHECK26-NEXT:    store i64 [[B]], i64* [[B_ADDR]], align 8
22953 // CHECK26-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
22954 // CHECK26-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
22955 // CHECK26-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 8
22956 // CHECK26-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
22957 // CHECK26-NEXT:    [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
22958 // CHECK26-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
22959 // CHECK26-NEXT:    [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
22960 // CHECK26-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
22961 // CHECK26-NEXT:    [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
22962 // CHECK26-NEXT:    [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32*
22963 // CHECK26-NEXT:    store i32 [[TMP4]], i32* [[CONV3]], align 4
22964 // CHECK26-NEXT:    [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
22965 // CHECK26-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]])
22966 // CHECK26-NEXT:    ret void
22967 //
22968 //
22969 // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..5
22970 // CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {
22971 // CHECK26-NEXT:  entry:
22972 // CHECK26-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
22973 // CHECK26-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
22974 // CHECK26-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
22975 // CHECK26-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
22976 // CHECK26-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
22977 // CHECK26-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
22978 // CHECK26-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 8
22979 // CHECK26-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
22980 // CHECK26-NEXT:    [[TMP:%.*]] = alloca i32, align 4
22981 // CHECK26-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
22982 // CHECK26-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
22983 // CHECK26-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
22984 // CHECK26-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
22985 // CHECK26-NEXT:    [[I:%.*]] = alloca i32, align 4
22986 // CHECK26-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
22987 // CHECK26-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
22988 // CHECK26-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
22989 // CHECK26-NEXT:    store i64 [[B]], i64* [[B_ADDR]], align 8
22990 // CHECK26-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
22991 // CHECK26-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
22992 // CHECK26-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 8
22993 // CHECK26-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
22994 // CHECK26-NEXT:    [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
22995 // CHECK26-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
22996 // CHECK26-NEXT:    [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
22997 // CHECK26-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
22998 // CHECK26-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
22999 // CHECK26-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
23000 // CHECK26-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
23001 // CHECK26-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
23002 // CHECK26-NEXT:    [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
23003 // CHECK26-NEXT:    [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
23004 // CHECK26-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
23005 // CHECK26-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
23006 // CHECK26-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 9
23007 // CHECK26-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
23008 // CHECK26:       cond.true:
23009 // CHECK26-NEXT:    br label [[COND_END:%.*]]
23010 // CHECK26:       cond.false:
23011 // CHECK26-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
23012 // CHECK26-NEXT:    br label [[COND_END]]
23013 // CHECK26:       cond.end:
23014 // CHECK26-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
23015 // CHECK26-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
23016 // CHECK26-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
23017 // CHECK26-NEXT:    store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
23018 // CHECK26-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
23019 // CHECK26:       omp.inner.for.cond:
23020 // CHECK26-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
23021 // CHECK26-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
23022 // CHECK26-NEXT:    [[CMP3:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
23023 // CHECK26-NEXT:    br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
23024 // CHECK26:       omp.inner.for.body:
23025 // CHECK26-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
23026 // CHECK26-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
23027 // CHECK26-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
23028 // CHECK26-NEXT:    store i32 [[ADD]], i32* [[I]], align 4
23029 // CHECK26-NEXT:    [[TMP12:%.*]] = load i32, i32* [[CONV]], align 8
23030 // CHECK26-NEXT:    [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double
23031 // CHECK26-NEXT:    [[ADD5:%.*]] = fadd double [[CONV4]], 1.500000e+00
23032 // CHECK26-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
23033 // CHECK26-NEXT:    store double [[ADD5]], double* [[A]], align 8
23034 // CHECK26-NEXT:    [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
23035 // CHECK26-NEXT:    [[TMP13:%.*]] = load double, double* [[A6]], align 8
23036 // CHECK26-NEXT:    [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00
23037 // CHECK26-NEXT:    store double [[INC]], double* [[A6]], align 8
23038 // CHECK26-NEXT:    [[CONV7:%.*]] = fptosi double [[INC]] to i16
23039 // CHECK26-NEXT:    [[TMP14:%.*]] = mul nsw i64 1, [[TMP2]]
23040 // CHECK26-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP14]]
23041 // CHECK26-NEXT:    [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
23042 // CHECK26-NEXT:    store i16 [[CONV7]], i16* [[ARRAYIDX8]], align 2
23043 // CHECK26-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
23044 // CHECK26:       omp.body.continue:
23045 // CHECK26-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
23046 // CHECK26:       omp.inner.for.inc:
23047 // CHECK26-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
23048 // CHECK26-NEXT:    [[ADD9:%.*]] = add nsw i32 [[TMP15]], 1
23049 // CHECK26-NEXT:    store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4
23050 // CHECK26-NEXT:    br label [[OMP_INNER_FOR_COND]]
23051 // CHECK26:       omp.inner.for.end:
23052 // CHECK26-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
23053 // CHECK26:       omp.loop.exit:
23054 // CHECK26-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
23055 // CHECK26-NEXT:    ret void
23056 //
23057 //
23058 // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183
23059 // CHECK26-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
23060 // CHECK26-NEXT:  entry:
23061 // CHECK26-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
23062 // CHECK26-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
23063 // CHECK26-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
23064 // CHECK26-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
23065 // CHECK26-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
23066 // CHECK26-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
23067 // CHECK26-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
23068 // CHECK26-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
23069 // CHECK26-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
23070 // CHECK26-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
23071 // CHECK26-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
23072 // CHECK26-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
23073 // CHECK26-NEXT:    [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
23074 // CHECK26-NEXT:    store i32 [[TMP1]], i32* [[CONV2]], align 4
23075 // CHECK26-NEXT:    [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
23076 // CHECK26-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
23077 // CHECK26-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
23078 // CHECK26-NEXT:    store i16 [[TMP3]], i16* [[CONV3]], align 2
23079 // CHECK26-NEXT:    [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
23080 // CHECK26-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]])
23081 // CHECK26-NEXT:    ret void
23082 //
23083 //
23084 // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..6
23085 // CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
23086 // CHECK26-NEXT:  entry:
23087 // CHECK26-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
23088 // CHECK26-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
23089 // CHECK26-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
23090 // CHECK26-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
23091 // CHECK26-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
23092 // CHECK26-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
23093 // CHECK26-NEXT:    [[TMP:%.*]] = alloca i32, align 4
23094 // CHECK26-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
23095 // CHECK26-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
23096 // CHECK26-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
23097 // CHECK26-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
23098 // CHECK26-NEXT:    [[I:%.*]] = alloca i32, align 4
23099 // CHECK26-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
23100 // CHECK26-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
23101 // CHECK26-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
23102 // CHECK26-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
23103 // CHECK26-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
23104 // CHECK26-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
23105 // CHECK26-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
23106 // CHECK26-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
23107 // CHECK26-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
23108 // CHECK26-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
23109 // CHECK26-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
23110 // CHECK26-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
23111 // CHECK26-NEXT:    [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
23112 // CHECK26-NEXT:    [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
23113 // CHECK26-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
23114 // CHECK26-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
23115 // CHECK26-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9
23116 // CHECK26-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
23117 // CHECK26:       cond.true:
23118 // CHECK26-NEXT:    br label [[COND_END:%.*]]
23119 // CHECK26:       cond.false:
23120 // CHECK26-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
23121 // CHECK26-NEXT:    br label [[COND_END]]
23122 // CHECK26:       cond.end:
23123 // CHECK26-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
23124 // CHECK26-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
23125 // CHECK26-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
23126 // CHECK26-NEXT:    store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
23127 // CHECK26-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
23128 // CHECK26:       omp.inner.for.cond:
23129 // CHECK26-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
23130 // CHECK26-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
23131 // CHECK26-NEXT:    [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
23132 // CHECK26-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
23133 // CHECK26:       omp.inner.for.body:
23134 // CHECK26-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
23135 // CHECK26-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
23136 // CHECK26-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
23137 // CHECK26-NEXT:    store i32 [[ADD]], i32* [[I]], align 4
23138 // CHECK26-NEXT:    [[TMP9:%.*]] = load i32, i32* [[CONV]], align 8
23139 // CHECK26-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1
23140 // CHECK26-NEXT:    store i32 [[ADD3]], i32* [[CONV]], align 8
23141 // CHECK26-NEXT:    [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 8
23142 // CHECK26-NEXT:    [[CONV4:%.*]] = sext i16 [[TMP10]] to i32
23143 // CHECK26-NEXT:    [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
23144 // CHECK26-NEXT:    [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
23145 // CHECK26-NEXT:    store i16 [[CONV6]], i16* [[CONV1]], align 8
23146 // CHECK26-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
23147 // CHECK26-NEXT:    [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
23148 // CHECK26-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1
23149 // CHECK26-NEXT:    store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4
23150 // CHECK26-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
23151 // CHECK26:       omp.body.continue:
23152 // CHECK26-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
23153 // CHECK26:       omp.inner.for.inc:
23154 // CHECK26-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
23155 // CHECK26-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP12]], 1
23156 // CHECK26-NEXT:    store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4
23157 // CHECK26-NEXT:    br label [[OMP_INNER_FOR_COND]]
23158 // CHECK26:       omp.inner.for.end:
23159 // CHECK26-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
23160 // CHECK26:       omp.loop.exit:
23161 // CHECK26-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
23162 // CHECK26-NEXT:    ret void
23163 //
23164 //
23165 // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103
23166 // CHECK27-SAME: (i32 [[AA:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]], i32 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] {
23167 // CHECK27-NEXT:  entry:
23168 // CHECK27-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
23169 // CHECK27-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
23170 // CHECK27-NEXT:    [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4
23171 // CHECK27-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
23172 // CHECK27-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]])
23173 // CHECK27-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
23174 // CHECK27-NEXT:    store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
23175 // CHECK27-NEXT:    store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4
23176 // CHECK27-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
23177 // CHECK27-NEXT:    [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
23178 // CHECK27-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4
23179 // CHECK27-NEXT:    call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
23180 // CHECK27-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
23181 // CHECK27-NEXT:    [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
23182 // CHECK27-NEXT:    store i16 [[TMP3]], i16* [[CONV3]], align 2
23183 // CHECK27-NEXT:    [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
23184 // CHECK27-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]])
23185 // CHECK27-NEXT:    ret void
23186 //
23187 //
23188 // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined.
23189 // CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] {
23190 // CHECK27-NEXT:  entry:
23191 // CHECK27-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
23192 // CHECK27-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
23193 // CHECK27-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
23194 // CHECK27-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
23195 // CHECK27-NEXT:    [[TMP:%.*]] = alloca i32, align 4
23196 // CHECK27-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
23197 // CHECK27-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
23198 // CHECK27-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
23199 // CHECK27-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
23200 // CHECK27-NEXT:    [[I:%.*]] = alloca i32, align 4
23201 // CHECK27-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
23202 // CHECK27-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
23203 // CHECK27-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
23204 // CHECK27-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
23205 // CHECK27-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
23206 // CHECK27-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
23207 // CHECK27-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
23208 // CHECK27-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
23209 // CHECK27-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
23210 // CHECK27-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
23211 // CHECK27-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
23212 // CHECK27-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
23213 // CHECK27-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
23214 // CHECK27-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
23215 // CHECK27:       cond.true:
23216 // CHECK27-NEXT:    br label [[COND_END:%.*]]
23217 // CHECK27:       cond.false:
23218 // CHECK27-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
23219 // CHECK27-NEXT:    br label [[COND_END]]
23220 // CHECK27:       cond.end:
23221 // CHECK27-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
23222 // CHECK27-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
23223 // CHECK27-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
23224 // CHECK27-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
23225 // CHECK27-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
23226 // CHECK27:       omp.inner.for.cond:
23227 // CHECK27-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
23228 // CHECK27-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
23229 // CHECK27-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
23230 // CHECK27-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
23231 // CHECK27:       omp.inner.for.body:
23232 // CHECK27-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
23233 // CHECK27-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
23234 // CHECK27-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
23235 // CHECK27-NEXT:    store i32 [[ADD]], i32* [[I]], align 4
23236 // CHECK27-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
23237 // CHECK27:       omp.body.continue:
23238 // CHECK27-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
23239 // CHECK27:       omp.inner.for.inc:
23240 // CHECK27-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
23241 // CHECK27-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
23242 // CHECK27-NEXT:    store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4
23243 // CHECK27-NEXT:    br label [[OMP_INNER_FOR_COND]]
23244 // CHECK27:       omp.inner.for.end:
23245 // CHECK27-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
23246 // CHECK27:       omp.loop.exit:
23247 // CHECK27-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
23248 // CHECK27-NEXT:    ret void
23249 //
23250 //
23251 // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113
23252 // CHECK27-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] {
23253 // CHECK27-NEXT:  entry:
23254 // CHECK27-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
23255 // CHECK27-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
23256 // CHECK27-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
23257 // CHECK27-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
23258 // CHECK27-NEXT:    [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
23259 // CHECK27-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
23260 // CHECK27-NEXT:    store i16 [[TMP0]], i16* [[CONV1]], align 2
23261 // CHECK27-NEXT:    [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
23262 // CHECK27-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]])
23263 // CHECK27-NEXT:    ret void
23264 //
23265 //
23266 // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..1
23267 // CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] {
23268 // CHECK27-NEXT:  entry:
23269 // CHECK27-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
23270 // CHECK27-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
23271 // CHECK27-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
23272 // CHECK27-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
23273 // CHECK27-NEXT:    [[TMP:%.*]] = alloca i32, align 4
23274 // CHECK27-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
23275 // CHECK27-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
23276 // CHECK27-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
23277 // CHECK27-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
23278 // CHECK27-NEXT:    [[I:%.*]] = alloca i32, align 4
23279 // CHECK27-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
23280 // CHECK27-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
23281 // CHECK27-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
23282 // CHECK27-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
23283 // CHECK27-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
23284 // CHECK27-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
23285 // CHECK27-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
23286 // CHECK27-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
23287 // CHECK27-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
23288 // CHECK27-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
23289 // CHECK27-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
23290 // CHECK27-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
23291 // CHECK27-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
23292 // CHECK27-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
23293 // CHECK27:       cond.true:
23294 // CHECK27-NEXT:    br label [[COND_END:%.*]]
23295 // CHECK27:       cond.false:
23296 // CHECK27-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
23297 // CHECK27-NEXT:    br label [[COND_END]]
23298 // CHECK27:       cond.end:
23299 // CHECK27-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
23300 // CHECK27-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
23301 // CHECK27-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
23302 // CHECK27-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
23303 // CHECK27-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
23304 // CHECK27:       omp.inner.for.cond:
23305 // CHECK27-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
23306 // CHECK27-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
23307 // CHECK27-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
23308 // CHECK27-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
23309 // CHECK27:       omp.inner.for.body:
23310 // CHECK27-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
23311 // CHECK27-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
23312 // CHECK27-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
23313 // CHECK27-NEXT:    store i32 [[ADD]], i32* [[I]], align 4
23314 // CHECK27-NEXT:    [[TMP8:%.*]] = load i16, i16* [[CONV]], align 4
23315 // CHECK27-NEXT:    [[CONV2:%.*]] = sext i16 [[TMP8]] to i32
23316 // CHECK27-NEXT:    [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
23317 // CHECK27-NEXT:    [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
23318 // CHECK27-NEXT:    store i16 [[CONV4]], i16* [[CONV]], align 4
23319 // CHECK27-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
23320 // CHECK27:       omp.body.continue:
23321 // CHECK27-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
23322 // CHECK27:       omp.inner.for.inc:
23323 // CHECK27-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
23324 // CHECK27-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP9]], 1
23325 // CHECK27-NEXT:    store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4
23326 // CHECK27-NEXT:    br label [[OMP_INNER_FOR_COND]]
23327 // CHECK27:       omp.inner.for.end:
23328 // CHECK27-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
23329 // CHECK27:       omp.loop.exit:
23330 // CHECK27-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
23331 // CHECK27-NEXT:    ret void
23332 //
23333 //
23334 // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120
23335 // CHECK27-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] {
23336 // CHECK27-NEXT:  entry:
23337 // CHECK27-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
23338 // CHECK27-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
23339 // CHECK27-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
23340 // CHECK27-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
23341 // CHECK27-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
23342 // CHECK27-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
23343 // CHECK27-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
23344 // CHECK27-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
23345 // CHECK27-NEXT:    store i32 [[TMP0]], i32* [[A_CASTED]], align 4
23346 // CHECK27-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
23347 // CHECK27-NEXT:    [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
23348 // CHECK27-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
23349 // CHECK27-NEXT:    store i16 [[TMP2]], i16* [[CONV1]], align 2
23350 // CHECK27-NEXT:    [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
23351 // CHECK27-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]])
23352 // CHECK27-NEXT:    ret void
23353 //
23354 //
23355 // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..2
23356 // CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] {
23357 // CHECK27-NEXT:  entry:
23358 // CHECK27-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
23359 // CHECK27-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
23360 // CHECK27-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
23361 // CHECK27-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
23362 // CHECK27-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
23363 // CHECK27-NEXT:    [[TMP:%.*]] = alloca i32, align 4
23364 // CHECK27-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
23365 // CHECK27-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
23366 // CHECK27-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
23367 // CHECK27-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
23368 // CHECK27-NEXT:    [[I:%.*]] = alloca i32, align 4
23369 // CHECK27-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
23370 // CHECK27-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
23371 // CHECK27-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
23372 // CHECK27-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
23373 // CHECK27-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
23374 // CHECK27-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
23375 // CHECK27-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
23376 // CHECK27-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
23377 // CHECK27-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
23378 // CHECK27-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
23379 // CHECK27-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
23380 // CHECK27-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
23381 // CHECK27-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
23382 // CHECK27-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
23383 // CHECK27-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
23384 // CHECK27:       cond.true:
23385 // CHECK27-NEXT:    br label [[COND_END:%.*]]
23386 // CHECK27:       cond.false:
23387 // CHECK27-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
23388 // CHECK27-NEXT:    br label [[COND_END]]
23389 // CHECK27:       cond.end:
23390 // CHECK27-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
23391 // CHECK27-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
23392 // CHECK27-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
23393 // CHECK27-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
23394 // CHECK27-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
23395 // CHECK27:       omp.inner.for.cond:
23396 // CHECK27-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
23397 // CHECK27-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
23398 // CHECK27-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
23399 // CHECK27-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
23400 // CHECK27:       omp.inner.for.body:
23401 // CHECK27-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
23402 // CHECK27-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
23403 // CHECK27-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
23404 // CHECK27-NEXT:    store i32 [[ADD]], i32* [[I]], align 4
23405 // CHECK27-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
23406 // CHECK27-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
23407 // CHECK27-NEXT:    store i32 [[ADD2]], i32* [[A_ADDR]], align 4
23408 // CHECK27-NEXT:    [[TMP9:%.*]] = load i16, i16* [[CONV]], align 4
23409 // CHECK27-NEXT:    [[CONV3:%.*]] = sext i16 [[TMP9]] to i32
23410 // CHECK27-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
23411 // CHECK27-NEXT:    [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
23412 // CHECK27-NEXT:    store i16 [[CONV5]], i16* [[CONV]], align 4
23413 // CHECK27-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
23414 // CHECK27:       omp.body.continue:
23415 // CHECK27-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
23416 // CHECK27:       omp.inner.for.inc:
23417 // CHECK27-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
23418 // CHECK27-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP10]], 1
23419 // CHECK27-NEXT:    store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4
23420 // CHECK27-NEXT:    br label [[OMP_INNER_FOR_COND]]
23421 // CHECK27:       omp.inner.for.end:
23422 // CHECK27-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
23423 // CHECK27:       omp.loop.exit:
23424 // CHECK27-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
23425 // CHECK27-NEXT:    ret void
23426 //
23427 //
23428 // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145
23429 // CHECK27-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
23430 // CHECK27-NEXT:  entry:
23431 // CHECK27-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
23432 // CHECK27-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
23433 // CHECK27-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
23434 // CHECK27-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 4
23435 // CHECK27-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
23436 // CHECK27-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
23437 // CHECK27-NEXT:    [[VLA_ADDR4:%.*]] = alloca i32, align 4
23438 // CHECK27-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 4
23439 // CHECK27-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
23440 // CHECK27-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
23441 // CHECK27-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
23442 // CHECK27-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
23443 // CHECK27-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
23444 // CHECK27-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
23445 // CHECK27-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
23446 // CHECK27-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 4
23447 // CHECK27-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
23448 // CHECK27-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
23449 // CHECK27-NEXT:    store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
23450 // CHECK27-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 4
23451 // CHECK27-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
23452 // CHECK27-NEXT:    store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
23453 // CHECK27-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
23454 // CHECK27-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
23455 // CHECK27-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
23456 // CHECK27-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
23457 // CHECK27-NEXT:    [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
23458 // CHECK27-NEXT:    [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
23459 // CHECK27-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
23460 // CHECK27-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
23461 // CHECK27-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
23462 // CHECK27-NEXT:    store i32 [[TMP8]], i32* [[A_CASTED]], align 4
23463 // CHECK27-NEXT:    [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4
23464 // CHECK27-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
23465 // CHECK27-NEXT:    store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
23466 // CHECK27-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
23467 // CHECK27-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i32 [[TMP11]])
23468 // CHECK27-NEXT:    ret void
23469 //
23470 //
23471 // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..3
23472 // CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
23473 // CHECK27-NEXT:  entry:
23474 // CHECK27-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
23475 // CHECK27-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
23476 // CHECK27-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
23477 // CHECK27-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
23478 // CHECK27-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
23479 // CHECK27-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 4
23480 // CHECK27-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
23481 // CHECK27-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
23482 // CHECK27-NEXT:    [[VLA_ADDR4:%.*]] = alloca i32, align 4
23483 // CHECK27-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 4
23484 // CHECK27-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
23485 // CHECK27-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
23486 // CHECK27-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
23487 // CHECK27-NEXT:    [[TMP:%.*]] = alloca i32, align 4
23488 // CHECK27-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
23489 // CHECK27-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
23490 // CHECK27-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
23491 // CHECK27-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
23492 // CHECK27-NEXT:    [[I:%.*]] = alloca i32, align 4
23493 // CHECK27-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
23494 // CHECK27-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
23495 // CHECK27-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
23496 // CHECK27-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
23497 // CHECK27-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
23498 // CHECK27-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 4
23499 // CHECK27-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
23500 // CHECK27-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
23501 // CHECK27-NEXT:    store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
23502 // CHECK27-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 4
23503 // CHECK27-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
23504 // CHECK27-NEXT:    store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
23505 // CHECK27-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
23506 // CHECK27-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
23507 // CHECK27-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
23508 // CHECK27-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
23509 // CHECK27-NEXT:    [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
23510 // CHECK27-NEXT:    [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
23511 // CHECK27-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
23512 // CHECK27-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
23513 // CHECK27-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
23514 // CHECK27-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
23515 // CHECK27-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
23516 // CHECK27-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
23517 // CHECK27-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
23518 // CHECK27-NEXT:    [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
23519 // CHECK27-NEXT:    [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
23520 // CHECK27-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
23521 // CHECK27-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
23522 // CHECK27:       omp.dispatch.cond:
23523 // CHECK27-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
23524 // CHECK27-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 9
23525 // CHECK27-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
23526 // CHECK27:       cond.true:
23527 // CHECK27-NEXT:    br label [[COND_END:%.*]]
23528 // CHECK27:       cond.false:
23529 // CHECK27-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
23530 // CHECK27-NEXT:    br label [[COND_END]]
23531 // CHECK27:       cond.end:
23532 // CHECK27-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
23533 // CHECK27-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
23534 // CHECK27-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
23535 // CHECK27-NEXT:    store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
23536 // CHECK27-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
23537 // CHECK27-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
23538 // CHECK27-NEXT:    [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
23539 // CHECK27-NEXT:    br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
23540 // CHECK27:       omp.dispatch.body:
23541 // CHECK27-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
23542 // CHECK27:       omp.inner.for.cond:
23543 // CHECK27-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
23544 // CHECK27-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !12
23545 // CHECK27-NEXT:    [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
23546 // CHECK27-NEXT:    br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
23547 // CHECK27:       omp.inner.for.body:
23548 // CHECK27-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
23549 // CHECK27-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
23550 // CHECK27-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
23551 // CHECK27-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !12
23552 // CHECK27-NEXT:    [[TMP19:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !12
23553 // CHECK27-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP19]], 1
23554 // CHECK27-NEXT:    store i32 [[ADD7]], i32* [[A_ADDR]], align 4, !llvm.access.group !12
23555 // CHECK27-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2
23556 // CHECK27-NEXT:    [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !12
23557 // CHECK27-NEXT:    [[CONV:%.*]] = fpext float [[TMP20]] to double
23558 // CHECK27-NEXT:    [[ADD8:%.*]] = fadd double [[CONV]], 1.000000e+00
23559 // CHECK27-NEXT:    [[CONV9:%.*]] = fptrunc double [[ADD8]] to float
23560 // CHECK27-NEXT:    store float [[CONV9]], float* [[ARRAYIDX]], align 4, !llvm.access.group !12
23561 // CHECK27-NEXT:    [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3
23562 // CHECK27-NEXT:    [[TMP21:%.*]] = load float, float* [[ARRAYIDX10]], align 4, !llvm.access.group !12
23563 // CHECK27-NEXT:    [[CONV11:%.*]] = fpext float [[TMP21]] to double
23564 // CHECK27-NEXT:    [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00
23565 // CHECK27-NEXT:    [[CONV13:%.*]] = fptrunc double [[ADD12]] to float
23566 // CHECK27-NEXT:    store float [[CONV13]], float* [[ARRAYIDX10]], align 4, !llvm.access.group !12
23567 // CHECK27-NEXT:    [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1
23568 // CHECK27-NEXT:    [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX14]], i32 0, i32 2
23569 // CHECK27-NEXT:    [[TMP22:%.*]] = load double, double* [[ARRAYIDX15]], align 8, !llvm.access.group !12
23570 // CHECK27-NEXT:    [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00
23571 // CHECK27-NEXT:    store double [[ADD16]], double* [[ARRAYIDX15]], align 8, !llvm.access.group !12
23572 // CHECK27-NEXT:    [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]]
23573 // CHECK27-NEXT:    [[ARRAYIDX17:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP23]]
23574 // CHECK27-NEXT:    [[ARRAYIDX18:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX17]], i32 3
23575 // CHECK27-NEXT:    [[TMP24:%.*]] = load double, double* [[ARRAYIDX18]], align 8, !llvm.access.group !12
23576 // CHECK27-NEXT:    [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00
23577 // CHECK27-NEXT:    store double [[ADD19]], double* [[ARRAYIDX18]], align 8, !llvm.access.group !12
23578 // CHECK27-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0
23579 // CHECK27-NEXT:    [[TMP25:%.*]] = load i64, i64* [[X]], align 4, !llvm.access.group !12
23580 // CHECK27-NEXT:    [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1
23581 // CHECK27-NEXT:    store i64 [[ADD20]], i64* [[X]], align 4, !llvm.access.group !12
23582 // CHECK27-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1
23583 // CHECK27-NEXT:    [[TMP26:%.*]] = load i8, i8* [[Y]], align 4, !llvm.access.group !12
23584 // CHECK27-NEXT:    [[CONV21:%.*]] = sext i8 [[TMP26]] to i32
23585 // CHECK27-NEXT:    [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1
23586 // CHECK27-NEXT:    [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8
23587 // CHECK27-NEXT:    store i8 [[CONV23]], i8* [[Y]], align 4, !llvm.access.group !12
23588 // CHECK27-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
23589 // CHECK27:       omp.body.continue:
23590 // CHECK27-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
23591 // CHECK27:       omp.inner.for.inc:
23592 // CHECK27-NEXT:    [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
23593 // CHECK27-NEXT:    [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1
23594 // CHECK27-NEXT:    store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
23595 // CHECK27-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]
23596 // CHECK27:       omp.inner.for.end:
23597 // CHECK27-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
23598 // CHECK27:       omp.dispatch.inc:
23599 // CHECK27-NEXT:    [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
23600 // CHECK27-NEXT:    [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
23601 // CHECK27-NEXT:    [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]
23602 // CHECK27-NEXT:    store i32 [[ADD25]], i32* [[DOTOMP_LB]], align 4
23603 // CHECK27-NEXT:    [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
23604 // CHECK27-NEXT:    [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
23605 // CHECK27-NEXT:    [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]]
23606 // CHECK27-NEXT:    store i32 [[ADD26]], i32* [[DOTOMP_UB]], align 4
23607 // CHECK27-NEXT:    br label [[OMP_DISPATCH_COND]]
23608 // CHECK27:       omp.dispatch.end:
23609 // CHECK27-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]])
23610 // CHECK27-NEXT:    ret void
23611 //
23612 //
23613 // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200
23614 // CHECK27-SAME: (i32 [[N:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
23615 // CHECK27-NEXT:  entry:
23616 // CHECK27-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
23617 // CHECK27-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
23618 // CHECK27-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
23619 // CHECK27-NEXT:    [[AAA_ADDR:%.*]] = alloca i32, align 4
23620 // CHECK27-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
23621 // CHECK27-NEXT:    [[N_CASTED:%.*]] = alloca i32, align 4
23622 // CHECK27-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
23623 // CHECK27-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
23624 // CHECK27-NEXT:    [[AAA_CASTED:%.*]] = alloca i32, align 4
23625 // CHECK27-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
23626 // CHECK27-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
23627 // CHECK27-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
23628 // CHECK27-NEXT:    store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
23629 // CHECK27-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
23630 // CHECK27-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
23631 // CHECK27-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
23632 // CHECK27-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
23633 // CHECK27-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
23634 // CHECK27-NEXT:    store i32 [[TMP1]], i32* [[N_CASTED]], align 4
23635 // CHECK27-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_CASTED]], align 4
23636 // CHECK27-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4
23637 // CHECK27-NEXT:    store i32 [[TMP3]], i32* [[A_CASTED]], align 4
23638 // CHECK27-NEXT:    [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4
23639 // CHECK27-NEXT:    [[TMP5:%.*]] = load i16, i16* [[CONV]], align 4
23640 // CHECK27-NEXT:    [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
23641 // CHECK27-NEXT:    store i16 [[TMP5]], i16* [[CONV2]], align 2
23642 // CHECK27-NEXT:    [[TMP6:%.*]] = load i32, i32* [[AA_CASTED]], align 4
23643 // CHECK27-NEXT:    [[TMP7:%.*]] = load i8, i8* [[CONV1]], align 4
23644 // CHECK27-NEXT:    [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
23645 // CHECK27-NEXT:    store i8 [[TMP7]], i8* [[CONV3]], align 1
23646 // CHECK27-NEXT:    [[TMP8:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
23647 // CHECK27-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP8]], [10 x i32]* [[TMP0]])
23648 // CHECK27-NEXT:    ret void
23649 //
23650 //
23651 // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..4
23652 // CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
23653 // CHECK27-NEXT:  entry:
23654 // CHECK27-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
23655 // CHECK27-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
23656 // CHECK27-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
23657 // CHECK27-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
23658 // CHECK27-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
23659 // CHECK27-NEXT:    [[AAA_ADDR:%.*]] = alloca i32, align 4
23660 // CHECK27-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
23661 // CHECK27-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
23662 // CHECK27-NEXT:    [[TMP:%.*]] = alloca i32, align 4
23663 // CHECK27-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
23664 // CHECK27-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
23665 // CHECK27-NEXT:    [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4
23666 // CHECK27-NEXT:    [[I:%.*]] = alloca i32, align 4
23667 // CHECK27-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
23668 // CHECK27-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
23669 // CHECK27-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
23670 // CHECK27-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
23671 // CHECK27-NEXT:    [[I6:%.*]] = alloca i32, align 4
23672 // CHECK27-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
23673 // CHECK27-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
23674 // CHECK27-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
23675 // CHECK27-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
23676 // CHECK27-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
23677 // CHECK27-NEXT:    store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
23678 // CHECK27-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
23679 // CHECK27-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
23680 // CHECK27-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
23681 // CHECK27-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
23682 // CHECK27-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
23683 // CHECK27-NEXT:    store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
23684 // CHECK27-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
23685 // CHECK27-NEXT:    store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4
23686 // CHECK27-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
23687 // CHECK27-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
23688 // CHECK27-NEXT:    [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]]
23689 // CHECK27-NEXT:    [[SUB4:%.*]] = sub i32 [[SUB]], 1
23690 // CHECK27-NEXT:    [[ADD:%.*]] = add i32 [[SUB4]], 1
23691 // CHECK27-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], 1
23692 // CHECK27-NEXT:    [[SUB5:%.*]] = sub i32 [[DIV]], 1
23693 // CHECK27-NEXT:    store i32 [[SUB5]], i32* [[DOTCAPTURE_EXPR_3]], align 4
23694 // CHECK27-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
23695 // CHECK27-NEXT:    store i32 [[TMP5]], i32* [[I]], align 4
23696 // CHECK27-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
23697 // CHECK27-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
23698 // CHECK27-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]]
23699 // CHECK27-NEXT:    br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
23700 // CHECK27:       omp.precond.then:
23701 // CHECK27-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
23702 // CHECK27-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
23703 // CHECK27-NEXT:    store i32 [[TMP8]], i32* [[DOTOMP_UB]], align 4
23704 // CHECK27-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
23705 // CHECK27-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
23706 // CHECK27-NEXT:    [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
23707 // CHECK27-NEXT:    [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
23708 // CHECK27-NEXT:    call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
23709 // CHECK27-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
23710 // CHECK27-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
23711 // CHECK27-NEXT:    [[CMP7:%.*]] = icmp ugt i32 [[TMP11]], [[TMP12]]
23712 // CHECK27-NEXT:    br i1 [[CMP7]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
23713 // CHECK27:       cond.true:
23714 // CHECK27-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
23715 // CHECK27-NEXT:    br label [[COND_END:%.*]]
23716 // CHECK27:       cond.false:
23717 // CHECK27-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
23718 // CHECK27-NEXT:    br label [[COND_END]]
23719 // CHECK27:       cond.end:
23720 // CHECK27-NEXT:    [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ]
23721 // CHECK27-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
23722 // CHECK27-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
23723 // CHECK27-NEXT:    store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4
23724 // CHECK27-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
23725 // CHECK27:       omp.inner.for.cond:
23726 // CHECK27-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
23727 // CHECK27-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
23728 // CHECK27-NEXT:    [[ADD8:%.*]] = add i32 [[TMP17]], 1
23729 // CHECK27-NEXT:    [[CMP9:%.*]] = icmp ult i32 [[TMP16]], [[ADD8]]
23730 // CHECK27-NEXT:    br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
23731 // CHECK27:       omp.inner.for.body:
23732 // CHECK27-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
23733 // CHECK27-NEXT:    [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
23734 // CHECK27-NEXT:    [[MUL:%.*]] = mul i32 [[TMP19]], 1
23735 // CHECK27-NEXT:    [[ADD10:%.*]] = add i32 [[TMP18]], [[MUL]]
23736 // CHECK27-NEXT:    store i32 [[ADD10]], i32* [[I6]], align 4
23737 // CHECK27-NEXT:    [[TMP20:%.*]] = load i32, i32* [[A_ADDR]], align 4
23738 // CHECK27-NEXT:    [[ADD11:%.*]] = add nsw i32 [[TMP20]], 1
23739 // CHECK27-NEXT:    store i32 [[ADD11]], i32* [[A_ADDR]], align 4
23740 // CHECK27-NEXT:    [[TMP21:%.*]] = load i16, i16* [[CONV]], align 4
23741 // CHECK27-NEXT:    [[CONV12:%.*]] = sext i16 [[TMP21]] to i32
23742 // CHECK27-NEXT:    [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1
23743 // CHECK27-NEXT:    [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16
23744 // CHECK27-NEXT:    store i16 [[CONV14]], i16* [[CONV]], align 4
23745 // CHECK27-NEXT:    [[TMP22:%.*]] = load i8, i8* [[CONV1]], align 4
23746 // CHECK27-NEXT:    [[CONV15:%.*]] = sext i8 [[TMP22]] to i32
23747 // CHECK27-NEXT:    [[ADD16:%.*]] = add nsw i32 [[CONV15]], 1
23748 // CHECK27-NEXT:    [[CONV17:%.*]] = trunc i32 [[ADD16]] to i8
23749 // CHECK27-NEXT:    store i8 [[CONV17]], i8* [[CONV1]], align 4
23750 // CHECK27-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
23751 // CHECK27-NEXT:    [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
23752 // CHECK27-NEXT:    [[ADD18:%.*]] = add nsw i32 [[TMP23]], 1
23753 // CHECK27-NEXT:    store i32 [[ADD18]], i32* [[ARRAYIDX]], align 4
23754 // CHECK27-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
23755 // CHECK27:       omp.body.continue:
23756 // CHECK27-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
23757 // CHECK27:       omp.inner.for.inc:
23758 // CHECK27-NEXT:    [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
23759 // CHECK27-NEXT:    [[ADD19:%.*]] = add i32 [[TMP24]], 1
23760 // CHECK27-NEXT:    store i32 [[ADD19]], i32* [[DOTOMP_IV]], align 4
23761 // CHECK27-NEXT:    br label [[OMP_INNER_FOR_COND]]
23762 // CHECK27:       omp.inner.for.end:
23763 // CHECK27-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
23764 // CHECK27:       omp.loop.exit:
23765 // CHECK27-NEXT:    [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
23766 // CHECK27-NEXT:    [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4
23767 // CHECK27-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]])
23768 // CHECK27-NEXT:    br label [[OMP_PRECOND_END]]
23769 // CHECK27:       omp.precond.end:
23770 // CHECK27-NEXT:    ret void
23771 //
23772 //
23773 // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218
23774 // CHECK27-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {
23775 // CHECK27-NEXT:  entry:
23776 // CHECK27-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
23777 // CHECK27-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
23778 // CHECK27-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
23779 // CHECK27-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
23780 // CHECK27-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 4
23781 // CHECK27-NEXT:    [[B_CASTED:%.*]] = alloca i32, align 4
23782 // CHECK27-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
23783 // CHECK27-NEXT:    store i32 [[B]], i32* [[B_ADDR]], align 4
23784 // CHECK27-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
23785 // CHECK27-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
23786 // CHECK27-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 4
23787 // CHECK27-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
23788 // CHECK27-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
23789 // CHECK27-NEXT:    [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
23790 // CHECK27-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
23791 // CHECK27-NEXT:    [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4
23792 // CHECK27-NEXT:    store i32 [[TMP4]], i32* [[B_CASTED]], align 4
23793 // CHECK27-NEXT:    [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4
23794 // CHECK27-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]])
23795 // CHECK27-NEXT:    ret void
23796 //
23797 //
23798 // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..5
23799 // CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {
23800 // CHECK27-NEXT:  entry:
23801 // CHECK27-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
23802 // CHECK27-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
23803 // CHECK27-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
23804 // CHECK27-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
23805 // CHECK27-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
23806 // CHECK27-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
23807 // CHECK27-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 4
23808 // CHECK27-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
23809 // CHECK27-NEXT:    [[TMP:%.*]] = alloca i32, align 4
23810 // CHECK27-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
23811 // CHECK27-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
23812 // CHECK27-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
23813 // CHECK27-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
23814 // CHECK27-NEXT:    [[I:%.*]] = alloca i32, align 4
23815 // CHECK27-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
23816 // CHECK27-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
23817 // CHECK27-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
23818 // CHECK27-NEXT:    store i32 [[B]], i32* [[B_ADDR]], align 4
23819 // CHECK27-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
23820 // CHECK27-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
23821 // CHECK27-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 4
23822 // CHECK27-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
23823 // CHECK27-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
23824 // CHECK27-NEXT:    [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
23825 // CHECK27-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
23826 // CHECK27-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
23827 // CHECK27-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
23828 // CHECK27-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
23829 // CHECK27-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
23830 // CHECK27-NEXT:    [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
23831 // CHECK27-NEXT:    [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
23832 // CHECK27-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
23833 // CHECK27-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
23834 // CHECK27-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 9
23835 // CHECK27-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
23836 // CHECK27:       cond.true:
23837 // CHECK27-NEXT:    br label [[COND_END:%.*]]
23838 // CHECK27:       cond.false:
23839 // CHECK27-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
23840 // CHECK27-NEXT:    br label [[COND_END]]
23841 // CHECK27:       cond.end:
23842 // CHECK27-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
23843 // CHECK27-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
23844 // CHECK27-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
23845 // CHECK27-NEXT:    store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
23846 // CHECK27-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
23847 // CHECK27:       omp.inner.for.cond:
23848 // CHECK27-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
23849 // CHECK27-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
23850 // CHECK27-NEXT:    [[CMP3:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
23851 // CHECK27-NEXT:    br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
23852 // CHECK27:       omp.inner.for.body:
23853 // CHECK27-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
23854 // CHECK27-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
23855 // CHECK27-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
23856 // CHECK27-NEXT:    store i32 [[ADD]], i32* [[I]], align 4
23857 // CHECK27-NEXT:    [[TMP12:%.*]] = load i32, i32* [[B_ADDR]], align 4
23858 // CHECK27-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP12]] to double
23859 // CHECK27-NEXT:    [[ADD4:%.*]] = fadd double [[CONV]], 1.500000e+00
23860 // CHECK27-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
23861 // CHECK27-NEXT:    store double [[ADD4]], double* [[A]], align 4
23862 // CHECK27-NEXT:    [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
23863 // CHECK27-NEXT:    [[TMP13:%.*]] = load double, double* [[A5]], align 4
23864 // CHECK27-NEXT:    [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00
23865 // CHECK27-NEXT:    store double [[INC]], double* [[A5]], align 4
23866 // CHECK27-NEXT:    [[CONV6:%.*]] = fptosi double [[INC]] to i16
23867 // CHECK27-NEXT:    [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]]
23868 // CHECK27-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP14]]
23869 // CHECK27-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
23870 // CHECK27-NEXT:    store i16 [[CONV6]], i16* [[ARRAYIDX7]], align 2
23871 // CHECK27-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
23872 // CHECK27:       omp.body.continue:
23873 // CHECK27-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
23874 // CHECK27:       omp.inner.for.inc:
23875 // CHECK27-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
23876 // CHECK27-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP15]], 1
23877 // CHECK27-NEXT:    store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4
23878 // CHECK27-NEXT:    br label [[OMP_INNER_FOR_COND]]
23879 // CHECK27:       omp.inner.for.end:
23880 // CHECK27-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
23881 // CHECK27:       omp.loop.exit:
23882 // CHECK27-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
23883 // CHECK27-NEXT:    ret void
23884 //
23885 //
23886 // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183
23887 // CHECK27-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
23888 // CHECK27-NEXT:  entry:
23889 // CHECK27-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
23890 // CHECK27-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
23891 // CHECK27-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
23892 // CHECK27-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
23893 // CHECK27-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
23894 // CHECK27-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
23895 // CHECK27-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
23896 // CHECK27-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
23897 // CHECK27-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
23898 // CHECK27-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
23899 // CHECK27-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
23900 // CHECK27-NEXT:    store i32 [[TMP1]], i32* [[A_CASTED]], align 4
23901 // CHECK27-NEXT:    [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
23902 // CHECK27-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
23903 // CHECK27-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
23904 // CHECK27-NEXT:    store i16 [[TMP3]], i16* [[CONV1]], align 2
23905 // CHECK27-NEXT:    [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
23906 // CHECK27-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]])
23907 // CHECK27-NEXT:    ret void
23908 //
23909 //
23910 // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..6
23911 // CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
23912 // CHECK27-NEXT:  entry:
23913 // CHECK27-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
23914 // CHECK27-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
23915 // CHECK27-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
23916 // CHECK27-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
23917 // CHECK27-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
23918 // CHECK27-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
23919 // CHECK27-NEXT:    [[TMP:%.*]] = alloca i32, align 4
23920 // CHECK27-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
23921 // CHECK27-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
23922 // CHECK27-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
23923 // CHECK27-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
23924 // CHECK27-NEXT:    [[I:%.*]] = alloca i32, align 4
23925 // CHECK27-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
23926 // CHECK27-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
23927 // CHECK27-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
23928 // CHECK27-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
23929 // CHECK27-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
23930 // CHECK27-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
23931 // CHECK27-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
23932 // CHECK27-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
23933 // CHECK27-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
23934 // CHECK27-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
23935 // CHECK27-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
23936 // CHECK27-NEXT:    [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
23937 // CHECK27-NEXT:    [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
23938 // CHECK27-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
23939 // CHECK27-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
23940 // CHECK27-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9
23941 // CHECK27-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
23942 // CHECK27:       cond.true:
23943 // CHECK27-NEXT:    br label [[COND_END:%.*]]
23944 // CHECK27:       cond.false:
23945 // CHECK27-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
23946 // CHECK27-NEXT:    br label [[COND_END]]
23947 // CHECK27:       cond.end:
23948 // CHECK27-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
23949 // CHECK27-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
23950 // CHECK27-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
23951 // CHECK27-NEXT:    store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
23952 // CHECK27-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
23953 // CHECK27:       omp.inner.for.cond:
23954 // CHECK27-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
23955 // CHECK27-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
23956 // CHECK27-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
23957 // CHECK27-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
23958 // CHECK27:       omp.inner.for.body:
23959 // CHECK27-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
23960 // CHECK27-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
23961 // CHECK27-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
23962 // CHECK27-NEXT:    store i32 [[ADD]], i32* [[I]], align 4
23963 // CHECK27-NEXT:    [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4
23964 // CHECK27-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
23965 // CHECK27-NEXT:    store i32 [[ADD2]], i32* [[A_ADDR]], align 4
23966 // CHECK27-NEXT:    [[TMP10:%.*]] = load i16, i16* [[CONV]], align 4
23967 // CHECK27-NEXT:    [[CONV3:%.*]] = sext i16 [[TMP10]] to i32
23968 // CHECK27-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
23969 // CHECK27-NEXT:    [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
23970 // CHECK27-NEXT:    store i16 [[CONV5]], i16* [[CONV]], align 4
23971 // CHECK27-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
23972 // CHECK27-NEXT:    [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
23973 // CHECK27-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1
23974 // CHECK27-NEXT:    store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4
23975 // CHECK27-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
23976 // CHECK27:       omp.body.continue:
23977 // CHECK27-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
23978 // CHECK27:       omp.inner.for.inc:
23979 // CHECK27-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
23980 // CHECK27-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP12]], 1
23981 // CHECK27-NEXT:    store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4
23982 // CHECK27-NEXT:    br label [[OMP_INNER_FOR_COND]]
23983 // CHECK27:       omp.inner.for.end:
23984 // CHECK27-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
23985 // CHECK27:       omp.loop.exit:
23986 // CHECK27-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
23987 // CHECK27-NEXT:    ret void
23988 //
23989 //
23990 // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103
23991 // CHECK28-SAME: (i32 [[AA:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]], i32 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] {
23992 // CHECK28-NEXT:  entry:
23993 // CHECK28-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
23994 // CHECK28-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
23995 // CHECK28-NEXT:    [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4
23996 // CHECK28-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
23997 // CHECK28-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]])
23998 // CHECK28-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
23999 // CHECK28-NEXT:    store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
24000 // CHECK28-NEXT:    store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4
24001 // CHECK28-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
24002 // CHECK28-NEXT:    [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
24003 // CHECK28-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4
24004 // CHECK28-NEXT:    call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
24005 // CHECK28-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
24006 // CHECK28-NEXT:    [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
24007 // CHECK28-NEXT:    store i16 [[TMP3]], i16* [[CONV3]], align 2
24008 // CHECK28-NEXT:    [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
24009 // CHECK28-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]])
24010 // CHECK28-NEXT:    ret void
24011 //
24012 //
24013 // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined.
24014 // CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] {
24015 // CHECK28-NEXT:  entry:
24016 // CHECK28-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
24017 // CHECK28-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
24018 // CHECK28-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
24019 // CHECK28-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
24020 // CHECK28-NEXT:    [[TMP:%.*]] = alloca i32, align 4
24021 // CHECK28-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
24022 // CHECK28-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
24023 // CHECK28-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
24024 // CHECK28-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
24025 // CHECK28-NEXT:    [[I:%.*]] = alloca i32, align 4
24026 // CHECK28-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
24027 // CHECK28-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
24028 // CHECK28-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
24029 // CHECK28-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
24030 // CHECK28-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
24031 // CHECK28-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
24032 // CHECK28-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
24033 // CHECK28-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
24034 // CHECK28-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
24035 // CHECK28-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
24036 // CHECK28-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
24037 // CHECK28-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
24038 // CHECK28-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
24039 // CHECK28-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
24040 // CHECK28:       cond.true:
24041 // CHECK28-NEXT:    br label [[COND_END:%.*]]
24042 // CHECK28:       cond.false:
24043 // CHECK28-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
24044 // CHECK28-NEXT:    br label [[COND_END]]
24045 // CHECK28:       cond.end:
24046 // CHECK28-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
24047 // CHECK28-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
24048 // CHECK28-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
24049 // CHECK28-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
24050 // CHECK28-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
24051 // CHECK28:       omp.inner.for.cond:
24052 // CHECK28-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
24053 // CHECK28-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
24054 // CHECK28-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
24055 // CHECK28-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
24056 // CHECK28:       omp.inner.for.body:
24057 // CHECK28-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
24058 // CHECK28-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
24059 // CHECK28-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
24060 // CHECK28-NEXT:    store i32 [[ADD]], i32* [[I]], align 4
24061 // CHECK28-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
24062 // CHECK28:       omp.body.continue:
24063 // CHECK28-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
24064 // CHECK28:       omp.inner.for.inc:
24065 // CHECK28-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
24066 // CHECK28-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
24067 // CHECK28-NEXT:    store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4
24068 // CHECK28-NEXT:    br label [[OMP_INNER_FOR_COND]]
24069 // CHECK28:       omp.inner.for.end:
24070 // CHECK28-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
24071 // CHECK28:       omp.loop.exit:
24072 // CHECK28-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
24073 // CHECK28-NEXT:    ret void
24074 //
24075 //
24076 // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113
24077 // CHECK28-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] {
24078 // CHECK28-NEXT:  entry:
24079 // CHECK28-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
24080 // CHECK28-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
24081 // CHECK28-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
24082 // CHECK28-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
24083 // CHECK28-NEXT:    [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
24084 // CHECK28-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
24085 // CHECK28-NEXT:    store i16 [[TMP0]], i16* [[CONV1]], align 2
24086 // CHECK28-NEXT:    [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
24087 // CHECK28-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]])
24088 // CHECK28-NEXT:    ret void
24089 //
24090 //
24091 // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..1
24092 // CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] {
24093 // CHECK28-NEXT:  entry:
24094 // CHECK28-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
24095 // CHECK28-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
24096 // CHECK28-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
24097 // CHECK28-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
24098 // CHECK28-NEXT:    [[TMP:%.*]] = alloca i32, align 4
24099 // CHECK28-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
24100 // CHECK28-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
24101 // CHECK28-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
24102 // CHECK28-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
24103 // CHECK28-NEXT:    [[I:%.*]] = alloca i32, align 4
24104 // CHECK28-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
24105 // CHECK28-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
24106 // CHECK28-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
24107 // CHECK28-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
24108 // CHECK28-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
24109 // CHECK28-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
24110 // CHECK28-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
24111 // CHECK28-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
24112 // CHECK28-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
24113 // CHECK28-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
24114 // CHECK28-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
24115 // CHECK28-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
24116 // CHECK28-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
24117 // CHECK28-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
24118 // CHECK28:       cond.true:
24119 // CHECK28-NEXT:    br label [[COND_END:%.*]]
24120 // CHECK28:       cond.false:
24121 // CHECK28-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
24122 // CHECK28-NEXT:    br label [[COND_END]]
24123 // CHECK28:       cond.end:
24124 // CHECK28-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
24125 // CHECK28-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
24126 // CHECK28-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
24127 // CHECK28-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
24128 // CHECK28-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
24129 // CHECK28:       omp.inner.for.cond:
24130 // CHECK28-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
24131 // CHECK28-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
24132 // CHECK28-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
24133 // CHECK28-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
24134 // CHECK28:       omp.inner.for.body:
24135 // CHECK28-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
24136 // CHECK28-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
24137 // CHECK28-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
24138 // CHECK28-NEXT:    store i32 [[ADD]], i32* [[I]], align 4
24139 // CHECK28-NEXT:    [[TMP8:%.*]] = load i16, i16* [[CONV]], align 4
24140 // CHECK28-NEXT:    [[CONV2:%.*]] = sext i16 [[TMP8]] to i32
24141 // CHECK28-NEXT:    [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
24142 // CHECK28-NEXT:    [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
24143 // CHECK28-NEXT:    store i16 [[CONV4]], i16* [[CONV]], align 4
24144 // CHECK28-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
24145 // CHECK28:       omp.body.continue:
24146 // CHECK28-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
24147 // CHECK28:       omp.inner.for.inc:
24148 // CHECK28-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
24149 // CHECK28-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP9]], 1
24150 // CHECK28-NEXT:    store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4
24151 // CHECK28-NEXT:    br label [[OMP_INNER_FOR_COND]]
24152 // CHECK28:       omp.inner.for.end:
24153 // CHECK28-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
24154 // CHECK28:       omp.loop.exit:
24155 // CHECK28-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
24156 // CHECK28-NEXT:    ret void
24157 //
24158 //
24159 // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120
24160 // CHECK28-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] {
24161 // CHECK28-NEXT:  entry:
24162 // CHECK28-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
24163 // CHECK28-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
24164 // CHECK28-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
24165 // CHECK28-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
24166 // CHECK28-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
24167 // CHECK28-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
24168 // CHECK28-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
24169 // CHECK28-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
24170 // CHECK28-NEXT:    store i32 [[TMP0]], i32* [[A_CASTED]], align 4
24171 // CHECK28-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
24172 // CHECK28-NEXT:    [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
24173 // CHECK28-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
24174 // CHECK28-NEXT:    store i16 [[TMP2]], i16* [[CONV1]], align 2
24175 // CHECK28-NEXT:    [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
24176 // CHECK28-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]])
24177 // CHECK28-NEXT:    ret void
24178 //
24179 //
24180 // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..2
24181 // CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] {
24182 // CHECK28-NEXT:  entry:
24183 // CHECK28-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
24184 // CHECK28-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
24185 // CHECK28-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
24186 // CHECK28-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
24187 // CHECK28-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
24188 // CHECK28-NEXT:    [[TMP:%.*]] = alloca i32, align 4
24189 // CHECK28-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
24190 // CHECK28-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
24191 // CHECK28-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
24192 // CHECK28-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
24193 // CHECK28-NEXT:    [[I:%.*]] = alloca i32, align 4
24194 // CHECK28-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
24195 // CHECK28-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
24196 // CHECK28-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
24197 // CHECK28-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
24198 // CHECK28-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
24199 // CHECK28-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
24200 // CHECK28-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
24201 // CHECK28-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
24202 // CHECK28-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
24203 // CHECK28-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
24204 // CHECK28-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
24205 // CHECK28-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
24206 // CHECK28-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
24207 // CHECK28-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
24208 // CHECK28-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
24209 // CHECK28:       cond.true:
24210 // CHECK28-NEXT:    br label [[COND_END:%.*]]
24211 // CHECK28:       cond.false:
24212 // CHECK28-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
24213 // CHECK28-NEXT:    br label [[COND_END]]
24214 // CHECK28:       cond.end:
24215 // CHECK28-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
24216 // CHECK28-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
24217 // CHECK28-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
24218 // CHECK28-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
24219 // CHECK28-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
24220 // CHECK28:       omp.inner.for.cond:
24221 // CHECK28-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
24222 // CHECK28-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
24223 // CHECK28-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
24224 // CHECK28-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
24225 // CHECK28:       omp.inner.for.body:
24226 // CHECK28-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
24227 // CHECK28-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
24228 // CHECK28-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
24229 // CHECK28-NEXT:    store i32 [[ADD]], i32* [[I]], align 4
24230 // CHECK28-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
24231 // CHECK28-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
24232 // CHECK28-NEXT:    store i32 [[ADD2]], i32* [[A_ADDR]], align 4
24233 // CHECK28-NEXT:    [[TMP9:%.*]] = load i16, i16* [[CONV]], align 4
24234 // CHECK28-NEXT:    [[CONV3:%.*]] = sext i16 [[TMP9]] to i32
24235 // CHECK28-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
24236 // CHECK28-NEXT:    [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
24237 // CHECK28-NEXT:    store i16 [[CONV5]], i16* [[CONV]], align 4
24238 // CHECK28-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
24239 // CHECK28:       omp.body.continue:
24240 // CHECK28-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
24241 // CHECK28:       omp.inner.for.inc:
24242 // CHECK28-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
24243 // CHECK28-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP10]], 1
24244 // CHECK28-NEXT:    store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4
24245 // CHECK28-NEXT:    br label [[OMP_INNER_FOR_COND]]
24246 // CHECK28:       omp.inner.for.end:
24247 // CHECK28-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
24248 // CHECK28:       omp.loop.exit:
24249 // CHECK28-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
24250 // CHECK28-NEXT:    ret void
24251 //
24252 //
24253 // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145
24254 // CHECK28-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
24255 // CHECK28-NEXT:  entry:
24256 // CHECK28-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
24257 // CHECK28-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
24258 // CHECK28-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
24259 // CHECK28-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 4
24260 // CHECK28-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
24261 // CHECK28-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
24262 // CHECK28-NEXT:    [[VLA_ADDR4:%.*]] = alloca i32, align 4
24263 // CHECK28-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 4
24264 // CHECK28-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
24265 // CHECK28-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
24266 // CHECK28-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
24267 // CHECK28-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
24268 // CHECK28-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
24269 // CHECK28-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
24270 // CHECK28-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
24271 // CHECK28-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 4
24272 // CHECK28-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
24273 // CHECK28-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
24274 // CHECK28-NEXT:    store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
24275 // CHECK28-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 4
24276 // CHECK28-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
24277 // CHECK28-NEXT:    store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
24278 // CHECK28-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
24279 // CHECK28-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
24280 // CHECK28-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
24281 // CHECK28-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
24282 // CHECK28-NEXT:    [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
24283 // CHECK28-NEXT:    [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
24284 // CHECK28-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
24285 // CHECK28-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
24286 // CHECK28-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
24287 // CHECK28-NEXT:    store i32 [[TMP8]], i32* [[A_CASTED]], align 4
24288 // CHECK28-NEXT:    [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4
24289 // CHECK28-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
24290 // CHECK28-NEXT:    store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
24291 // CHECK28-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
24292 // CHECK28-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i32 [[TMP11]])
24293 // CHECK28-NEXT:    ret void
24294 //
24295 //
24296 // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..3
24297 // CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
24298 // CHECK28-NEXT:  entry:
24299 // CHECK28-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
24300 // CHECK28-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
24301 // CHECK28-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
24302 // CHECK28-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
24303 // CHECK28-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
24304 // CHECK28-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 4
24305 // CHECK28-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
24306 // CHECK28-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
24307 // CHECK28-NEXT:    [[VLA_ADDR4:%.*]] = alloca i32, align 4
24308 // CHECK28-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 4
24309 // CHECK28-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
24310 // CHECK28-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
24311 // CHECK28-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
24312 // CHECK28-NEXT:    [[TMP:%.*]] = alloca i32, align 4
24313 // CHECK28-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
24314 // CHECK28-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
24315 // CHECK28-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
24316 // CHECK28-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
24317 // CHECK28-NEXT:    [[I:%.*]] = alloca i32, align 4
24318 // CHECK28-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
24319 // CHECK28-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
24320 // CHECK28-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
24321 // CHECK28-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
24322 // CHECK28-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
24323 // CHECK28-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 4
24324 // CHECK28-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
24325 // CHECK28-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
24326 // CHECK28-NEXT:    store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
24327 // CHECK28-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 4
24328 // CHECK28-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
24329 // CHECK28-NEXT:    store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
24330 // CHECK28-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
24331 // CHECK28-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
24332 // CHECK28-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
24333 // CHECK28-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
24334 // CHECK28-NEXT:    [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
24335 // CHECK28-NEXT:    [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
24336 // CHECK28-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
24337 // CHECK28-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
24338 // CHECK28-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
24339 // CHECK28-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
24340 // CHECK28-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
24341 // CHECK28-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
24342 // CHECK28-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
24343 // CHECK28-NEXT:    [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
24344 // CHECK28-NEXT:    [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
24345 // CHECK28-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
24346 // CHECK28-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
24347 // CHECK28:       omp.dispatch.cond:
24348 // CHECK28-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
24349 // CHECK28-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 9
24350 // CHECK28-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
24351 // CHECK28:       cond.true:
24352 // CHECK28-NEXT:    br label [[COND_END:%.*]]
24353 // CHECK28:       cond.false:
24354 // CHECK28-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
24355 // CHECK28-NEXT:    br label [[COND_END]]
24356 // CHECK28:       cond.end:
24357 // CHECK28-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
24358 // CHECK28-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
24359 // CHECK28-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
24360 // CHECK28-NEXT:    store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
24361 // CHECK28-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
24362 // CHECK28-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
24363 // CHECK28-NEXT:    [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
24364 // CHECK28-NEXT:    br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
24365 // CHECK28:       omp.dispatch.body:
24366 // CHECK28-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
24367 // CHECK28:       omp.inner.for.cond:
24368 // CHECK28-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
24369 // CHECK28-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !12
24370 // CHECK28-NEXT:    [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
24371 // CHECK28-NEXT:    br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
24372 // CHECK28:       omp.inner.for.body:
24373 // CHECK28-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
24374 // CHECK28-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
24375 // CHECK28-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
24376 // CHECK28-NEXT:    store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !12
24377 // CHECK28-NEXT:    [[TMP19:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !12
24378 // CHECK28-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP19]], 1
24379 // CHECK28-NEXT:    store i32 [[ADD7]], i32* [[A_ADDR]], align 4, !llvm.access.group !12
24380 // CHECK28-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2
24381 // CHECK28-NEXT:    [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !12
24382 // CHECK28-NEXT:    [[CONV:%.*]] = fpext float [[TMP20]] to double
24383 // CHECK28-NEXT:    [[ADD8:%.*]] = fadd double [[CONV]], 1.000000e+00
24384 // CHECK28-NEXT:    [[CONV9:%.*]] = fptrunc double [[ADD8]] to float
24385 // CHECK28-NEXT:    store float [[CONV9]], float* [[ARRAYIDX]], align 4, !llvm.access.group !12
24386 // CHECK28-NEXT:    [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3
24387 // CHECK28-NEXT:    [[TMP21:%.*]] = load float, float* [[ARRAYIDX10]], align 4, !llvm.access.group !12
24388 // CHECK28-NEXT:    [[CONV11:%.*]] = fpext float [[TMP21]] to double
24389 // CHECK28-NEXT:    [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00
24390 // CHECK28-NEXT:    [[CONV13:%.*]] = fptrunc double [[ADD12]] to float
24391 // CHECK28-NEXT:    store float [[CONV13]], float* [[ARRAYIDX10]], align 4, !llvm.access.group !12
24392 // CHECK28-NEXT:    [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1
24393 // CHECK28-NEXT:    [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX14]], i32 0, i32 2
24394 // CHECK28-NEXT:    [[TMP22:%.*]] = load double, double* [[ARRAYIDX15]], align 8, !llvm.access.group !12
24395 // CHECK28-NEXT:    [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00
24396 // CHECK28-NEXT:    store double [[ADD16]], double* [[ARRAYIDX15]], align 8, !llvm.access.group !12
24397 // CHECK28-NEXT:    [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]]
24398 // CHECK28-NEXT:    [[ARRAYIDX17:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP23]]
24399 // CHECK28-NEXT:    [[ARRAYIDX18:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX17]], i32 3
24400 // CHECK28-NEXT:    [[TMP24:%.*]] = load double, double* [[ARRAYIDX18]], align 8, !llvm.access.group !12
24401 // CHECK28-NEXT:    [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00
24402 // CHECK28-NEXT:    store double [[ADD19]], double* [[ARRAYIDX18]], align 8, !llvm.access.group !12
24403 // CHECK28-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0
24404 // CHECK28-NEXT:    [[TMP25:%.*]] = load i64, i64* [[X]], align 4, !llvm.access.group !12
24405 // CHECK28-NEXT:    [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1
24406 // CHECK28-NEXT:    store i64 [[ADD20]], i64* [[X]], align 4, !llvm.access.group !12
24407 // CHECK28-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1
24408 // CHECK28-NEXT:    [[TMP26:%.*]] = load i8, i8* [[Y]], align 4, !llvm.access.group !12
24409 // CHECK28-NEXT:    [[CONV21:%.*]] = sext i8 [[TMP26]] to i32
24410 // CHECK28-NEXT:    [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1
24411 // CHECK28-NEXT:    [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8
24412 // CHECK28-NEXT:    store i8 [[CONV23]], i8* [[Y]], align 4, !llvm.access.group !12
24413 // CHECK28-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
24414 // CHECK28:       omp.body.continue:
24415 // CHECK28-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
24416 // CHECK28:       omp.inner.for.inc:
24417 // CHECK28-NEXT:    [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
24418 // CHECK28-NEXT:    [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1
24419 // CHECK28-NEXT:    store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
24420 // CHECK28-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]
24421 // CHECK28:       omp.inner.for.end:
24422 // CHECK28-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
24423 // CHECK28:       omp.dispatch.inc:
24424 // CHECK28-NEXT:    [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
24425 // CHECK28-NEXT:    [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
24426 // CHECK28-NEXT:    [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]
24427 // CHECK28-NEXT:    store i32 [[ADD25]], i32* [[DOTOMP_LB]], align 4
24428 // CHECK28-NEXT:    [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
24429 // CHECK28-NEXT:    [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
24430 // CHECK28-NEXT:    [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]]
24431 // CHECK28-NEXT:    store i32 [[ADD26]], i32* [[DOTOMP_UB]], align 4
24432 // CHECK28-NEXT:    br label [[OMP_DISPATCH_COND]]
24433 // CHECK28:       omp.dispatch.end:
24434 // CHECK28-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]])
24435 // CHECK28-NEXT:    ret void
24436 //
24437 //
24438 // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200
24439 // CHECK28-SAME: (i32 [[N:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
24440 // CHECK28-NEXT:  entry:
24441 // CHECK28-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
24442 // CHECK28-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
24443 // CHECK28-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
24444 // CHECK28-NEXT:    [[AAA_ADDR:%.*]] = alloca i32, align 4
24445 // CHECK28-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
24446 // CHECK28-NEXT:    [[N_CASTED:%.*]] = alloca i32, align 4
24447 // CHECK28-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
24448 // CHECK28-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
24449 // CHECK28-NEXT:    [[AAA_CASTED:%.*]] = alloca i32, align 4
24450 // CHECK28-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
24451 // CHECK28-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
24452 // CHECK28-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
24453 // CHECK28-NEXT:    store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
24454 // CHECK28-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
24455 // CHECK28-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
24456 // CHECK28-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
24457 // CHECK28-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
24458 // CHECK28-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
24459 // CHECK28-NEXT:    store i32 [[TMP1]], i32* [[N_CASTED]], align 4
24460 // CHECK28-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_CASTED]], align 4
24461 // CHECK28-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4
24462 // CHECK28-NEXT:    store i32 [[TMP3]], i32* [[A_CASTED]], align 4
24463 // CHECK28-NEXT:    [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4
24464 // CHECK28-NEXT:    [[TMP5:%.*]] = load i16, i16* [[CONV]], align 4
24465 // CHECK28-NEXT:    [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
24466 // CHECK28-NEXT:    store i16 [[TMP5]], i16* [[CONV2]], align 2
24467 // CHECK28-NEXT:    [[TMP6:%.*]] = load i32, i32* [[AA_CASTED]], align 4
24468 // CHECK28-NEXT:    [[TMP7:%.*]] = load i8, i8* [[CONV1]], align 4
24469 // CHECK28-NEXT:    [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
24470 // CHECK28-NEXT:    store i8 [[TMP7]], i8* [[CONV3]], align 1
24471 // CHECK28-NEXT:    [[TMP8:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
24472 // CHECK28-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP8]], [10 x i32]* [[TMP0]])
24473 // CHECK28-NEXT:    ret void
24474 //
24475 //
24476 // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..4
24477 // CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
24478 // CHECK28-NEXT:  entry:
24479 // CHECK28-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
24480 // CHECK28-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
24481 // CHECK28-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
24482 // CHECK28-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
24483 // CHECK28-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
24484 // CHECK28-NEXT:    [[AAA_ADDR:%.*]] = alloca i32, align 4
24485 // CHECK28-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
24486 // CHECK28-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
24487 // CHECK28-NEXT:    [[TMP:%.*]] = alloca i32, align 4
24488 // CHECK28-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
24489 // CHECK28-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
24490 // CHECK28-NEXT:    [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4
24491 // CHECK28-NEXT:    [[I:%.*]] = alloca i32, align 4
24492 // CHECK28-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
24493 // CHECK28-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
24494 // CHECK28-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
24495 // CHECK28-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
24496 // CHECK28-NEXT:    [[I6:%.*]] = alloca i32, align 4
24497 // CHECK28-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
24498 // CHECK28-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
24499 // CHECK28-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
24500 // CHECK28-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
24501 // CHECK28-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
24502 // CHECK28-NEXT:    store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
24503 // CHECK28-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
24504 // CHECK28-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
24505 // CHECK28-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
24506 // CHECK28-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
24507 // CHECK28-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
24508 // CHECK28-NEXT:    store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
24509 // CHECK28-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
24510 // CHECK28-NEXT:    store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4
24511 // CHECK28-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
24512 // CHECK28-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
24513 // CHECK28-NEXT:    [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]]
24514 // CHECK28-NEXT:    [[SUB4:%.*]] = sub i32 [[SUB]], 1
24515 // CHECK28-NEXT:    [[ADD:%.*]] = add i32 [[SUB4]], 1
24516 // CHECK28-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], 1
24517 // CHECK28-NEXT:    [[SUB5:%.*]] = sub i32 [[DIV]], 1
24518 // CHECK28-NEXT:    store i32 [[SUB5]], i32* [[DOTCAPTURE_EXPR_3]], align 4
24519 // CHECK28-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
24520 // CHECK28-NEXT:    store i32 [[TMP5]], i32* [[I]], align 4
24521 // CHECK28-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
24522 // CHECK28-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
24523 // CHECK28-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]]
24524 // CHECK28-NEXT:    br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
24525 // CHECK28:       omp.precond.then:
24526 // CHECK28-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
24527 // CHECK28-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
24528 // CHECK28-NEXT:    store i32 [[TMP8]], i32* [[DOTOMP_UB]], align 4
24529 // CHECK28-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
24530 // CHECK28-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
24531 // CHECK28-NEXT:    [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
24532 // CHECK28-NEXT:    [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
24533 // CHECK28-NEXT:    call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
24534 // CHECK28-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
24535 // CHECK28-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
24536 // CHECK28-NEXT:    [[CMP7:%.*]] = icmp ugt i32 [[TMP11]], [[TMP12]]
24537 // CHECK28-NEXT:    br i1 [[CMP7]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
24538 // CHECK28:       cond.true:
24539 // CHECK28-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
24540 // CHECK28-NEXT:    br label [[COND_END:%.*]]
24541 // CHECK28:       cond.false:
24542 // CHECK28-NEXT:    [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
24543 // CHECK28-NEXT:    br label [[COND_END]]
24544 // CHECK28:       cond.end:
24545 // CHECK28-NEXT:    [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ]
24546 // CHECK28-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
24547 // CHECK28-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
24548 // CHECK28-NEXT:    store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4
24549 // CHECK28-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
24550 // CHECK28:       omp.inner.for.cond:
24551 // CHECK28-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
24552 // CHECK28-NEXT:    [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
24553 // CHECK28-NEXT:    [[ADD8:%.*]] = add i32 [[TMP17]], 1
24554 // CHECK28-NEXT:    [[CMP9:%.*]] = icmp ult i32 [[TMP16]], [[ADD8]]
24555 // CHECK28-NEXT:    br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
24556 // CHECK28:       omp.inner.for.body:
24557 // CHECK28-NEXT:    [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
24558 // CHECK28-NEXT:    [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
24559 // CHECK28-NEXT:    [[MUL:%.*]] = mul i32 [[TMP19]], 1
24560 // CHECK28-NEXT:    [[ADD10:%.*]] = add i32 [[TMP18]], [[MUL]]
24561 // CHECK28-NEXT:    store i32 [[ADD10]], i32* [[I6]], align 4
24562 // CHECK28-NEXT:    [[TMP20:%.*]] = load i32, i32* [[A_ADDR]], align 4
24563 // CHECK28-NEXT:    [[ADD11:%.*]] = add nsw i32 [[TMP20]], 1
24564 // CHECK28-NEXT:    store i32 [[ADD11]], i32* [[A_ADDR]], align 4
24565 // CHECK28-NEXT:    [[TMP21:%.*]] = load i16, i16* [[CONV]], align 4
24566 // CHECK28-NEXT:    [[CONV12:%.*]] = sext i16 [[TMP21]] to i32
24567 // CHECK28-NEXT:    [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1
24568 // CHECK28-NEXT:    [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16
24569 // CHECK28-NEXT:    store i16 [[CONV14]], i16* [[CONV]], align 4
24570 // CHECK28-NEXT:    [[TMP22:%.*]] = load i8, i8* [[CONV1]], align 4
24571 // CHECK28-NEXT:    [[CONV15:%.*]] = sext i8 [[TMP22]] to i32
24572 // CHECK28-NEXT:    [[ADD16:%.*]] = add nsw i32 [[CONV15]], 1
24573 // CHECK28-NEXT:    [[CONV17:%.*]] = trunc i32 [[ADD16]] to i8
24574 // CHECK28-NEXT:    store i8 [[CONV17]], i8* [[CONV1]], align 4
24575 // CHECK28-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
24576 // CHECK28-NEXT:    [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
24577 // CHECK28-NEXT:    [[ADD18:%.*]] = add nsw i32 [[TMP23]], 1
24578 // CHECK28-NEXT:    store i32 [[ADD18]], i32* [[ARRAYIDX]], align 4
24579 // CHECK28-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
24580 // CHECK28:       omp.body.continue:
24581 // CHECK28-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
24582 // CHECK28:       omp.inner.for.inc:
24583 // CHECK28-NEXT:    [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
24584 // CHECK28-NEXT:    [[ADD19:%.*]] = add i32 [[TMP24]], 1
24585 // CHECK28-NEXT:    store i32 [[ADD19]], i32* [[DOTOMP_IV]], align 4
24586 // CHECK28-NEXT:    br label [[OMP_INNER_FOR_COND]]
24587 // CHECK28:       omp.inner.for.end:
24588 // CHECK28-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
24589 // CHECK28:       omp.loop.exit:
24590 // CHECK28-NEXT:    [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
24591 // CHECK28-NEXT:    [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4
24592 // CHECK28-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]])
24593 // CHECK28-NEXT:    br label [[OMP_PRECOND_END]]
24594 // CHECK28:       omp.precond.end:
24595 // CHECK28-NEXT:    ret void
24596 //
24597 //
24598 // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218
24599 // CHECK28-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {
24600 // CHECK28-NEXT:  entry:
24601 // CHECK28-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
24602 // CHECK28-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
24603 // CHECK28-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
24604 // CHECK28-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
24605 // CHECK28-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 4
24606 // CHECK28-NEXT:    [[B_CASTED:%.*]] = alloca i32, align 4
24607 // CHECK28-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
24608 // CHECK28-NEXT:    store i32 [[B]], i32* [[B_ADDR]], align 4
24609 // CHECK28-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
24610 // CHECK28-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
24611 // CHECK28-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 4
24612 // CHECK28-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
24613 // CHECK28-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
24614 // CHECK28-NEXT:    [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
24615 // CHECK28-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
24616 // CHECK28-NEXT:    [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4
24617 // CHECK28-NEXT:    store i32 [[TMP4]], i32* [[B_CASTED]], align 4
24618 // CHECK28-NEXT:    [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4
24619 // CHECK28-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]])
24620 // CHECK28-NEXT:    ret void
24621 //
24622 //
24623 // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..5
24624 // CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {
24625 // CHECK28-NEXT:  entry:
24626 // CHECK28-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
24627 // CHECK28-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
24628 // CHECK28-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
24629 // CHECK28-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
24630 // CHECK28-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
24631 // CHECK28-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
24632 // CHECK28-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 4
24633 // CHECK28-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
24634 // CHECK28-NEXT:    [[TMP:%.*]] = alloca i32, align 4
24635 // CHECK28-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
24636 // CHECK28-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
24637 // CHECK28-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
24638 // CHECK28-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
24639 // CHECK28-NEXT:    [[I:%.*]] = alloca i32, align 4
24640 // CHECK28-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
24641 // CHECK28-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
24642 // CHECK28-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
24643 // CHECK28-NEXT:    store i32 [[B]], i32* [[B_ADDR]], align 4
24644 // CHECK28-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
24645 // CHECK28-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
24646 // CHECK28-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 4
24647 // CHECK28-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
24648 // CHECK28-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
24649 // CHECK28-NEXT:    [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
24650 // CHECK28-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
24651 // CHECK28-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
24652 // CHECK28-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
24653 // CHECK28-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
24654 // CHECK28-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
24655 // CHECK28-NEXT:    [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
24656 // CHECK28-NEXT:    [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
24657 // CHECK28-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
24658 // CHECK28-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
24659 // CHECK28-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 9
24660 // CHECK28-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
24661 // CHECK28:       cond.true:
24662 // CHECK28-NEXT:    br label [[COND_END:%.*]]
24663 // CHECK28:       cond.false:
24664 // CHECK28-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
24665 // CHECK28-NEXT:    br label [[COND_END]]
24666 // CHECK28:       cond.end:
24667 // CHECK28-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
24668 // CHECK28-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
24669 // CHECK28-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
24670 // CHECK28-NEXT:    store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
24671 // CHECK28-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
24672 // CHECK28:       omp.inner.for.cond:
24673 // CHECK28-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
24674 // CHECK28-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
24675 // CHECK28-NEXT:    [[CMP3:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
24676 // CHECK28-NEXT:    br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
24677 // CHECK28:       omp.inner.for.body:
24678 // CHECK28-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
24679 // CHECK28-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
24680 // CHECK28-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
24681 // CHECK28-NEXT:    store i32 [[ADD]], i32* [[I]], align 4
24682 // CHECK28-NEXT:    [[TMP12:%.*]] = load i32, i32* [[B_ADDR]], align 4
24683 // CHECK28-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP12]] to double
24684 // CHECK28-NEXT:    [[ADD4:%.*]] = fadd double [[CONV]], 1.500000e+00
24685 // CHECK28-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
24686 // CHECK28-NEXT:    store double [[ADD4]], double* [[A]], align 4
24687 // CHECK28-NEXT:    [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
24688 // CHECK28-NEXT:    [[TMP13:%.*]] = load double, double* [[A5]], align 4
24689 // CHECK28-NEXT:    [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00
24690 // CHECK28-NEXT:    store double [[INC]], double* [[A5]], align 4
24691 // CHECK28-NEXT:    [[CONV6:%.*]] = fptosi double [[INC]] to i16
24692 // CHECK28-NEXT:    [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]]
24693 // CHECK28-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP14]]
24694 // CHECK28-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
24695 // CHECK28-NEXT:    store i16 [[CONV6]], i16* [[ARRAYIDX7]], align 2
24696 // CHECK28-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
24697 // CHECK28:       omp.body.continue:
24698 // CHECK28-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
24699 // CHECK28:       omp.inner.for.inc:
24700 // CHECK28-NEXT:    [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
24701 // CHECK28-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP15]], 1
24702 // CHECK28-NEXT:    store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4
24703 // CHECK28-NEXT:    br label [[OMP_INNER_FOR_COND]]
24704 // CHECK28:       omp.inner.for.end:
24705 // CHECK28-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
24706 // CHECK28:       omp.loop.exit:
24707 // CHECK28-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
24708 // CHECK28-NEXT:    ret void
24709 //
24710 //
24711 // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183
24712 // CHECK28-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
24713 // CHECK28-NEXT:  entry:
24714 // CHECK28-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
24715 // CHECK28-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
24716 // CHECK28-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
24717 // CHECK28-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
24718 // CHECK28-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
24719 // CHECK28-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
24720 // CHECK28-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
24721 // CHECK28-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
24722 // CHECK28-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
24723 // CHECK28-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
24724 // CHECK28-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
24725 // CHECK28-NEXT:    store i32 [[TMP1]], i32* [[A_CASTED]], align 4
24726 // CHECK28-NEXT:    [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
24727 // CHECK28-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
24728 // CHECK28-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
24729 // CHECK28-NEXT:    store i16 [[TMP3]], i16* [[CONV1]], align 2
24730 // CHECK28-NEXT:    [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
24731 // CHECK28-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]])
24732 // CHECK28-NEXT:    ret void
24733 //
24734 //
24735 // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..6
24736 // CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
24737 // CHECK28-NEXT:  entry:
24738 // CHECK28-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
24739 // CHECK28-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
24740 // CHECK28-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
24741 // CHECK28-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
24742 // CHECK28-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
24743 // CHECK28-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
24744 // CHECK28-NEXT:    [[TMP:%.*]] = alloca i32, align 4
24745 // CHECK28-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
24746 // CHECK28-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
24747 // CHECK28-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
24748 // CHECK28-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
24749 // CHECK28-NEXT:    [[I:%.*]] = alloca i32, align 4
24750 // CHECK28-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
24751 // CHECK28-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
24752 // CHECK28-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
24753 // CHECK28-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
24754 // CHECK28-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
24755 // CHECK28-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
24756 // CHECK28-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
24757 // CHECK28-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
24758 // CHECK28-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
24759 // CHECK28-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
24760 // CHECK28-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
24761 // CHECK28-NEXT:    [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
24762 // CHECK28-NEXT:    [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
24763 // CHECK28-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
24764 // CHECK28-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
24765 // CHECK28-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9
24766 // CHECK28-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
24767 // CHECK28:       cond.true:
24768 // CHECK28-NEXT:    br label [[COND_END:%.*]]
24769 // CHECK28:       cond.false:
24770 // CHECK28-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
24771 // CHECK28-NEXT:    br label [[COND_END]]
24772 // CHECK28:       cond.end:
24773 // CHECK28-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
24774 // CHECK28-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
24775 // CHECK28-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
24776 // CHECK28-NEXT:    store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
24777 // CHECK28-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
24778 // CHECK28:       omp.inner.for.cond:
24779 // CHECK28-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
24780 // CHECK28-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
24781 // CHECK28-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
24782 // CHECK28-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
24783 // CHECK28:       omp.inner.for.body:
24784 // CHECK28-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
24785 // CHECK28-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
24786 // CHECK28-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
24787 // CHECK28-NEXT:    store i32 [[ADD]], i32* [[I]], align 4
24788 // CHECK28-NEXT:    [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4
24789 // CHECK28-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
24790 // CHECK28-NEXT:    store i32 [[ADD2]], i32* [[A_ADDR]], align 4
24791 // CHECK28-NEXT:    [[TMP10:%.*]] = load i16, i16* [[CONV]], align 4
24792 // CHECK28-NEXT:    [[CONV3:%.*]] = sext i16 [[TMP10]] to i32
24793 // CHECK28-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
24794 // CHECK28-NEXT:    [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
24795 // CHECK28-NEXT:    store i16 [[CONV5]], i16* [[CONV]], align 4
24796 // CHECK28-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
24797 // CHECK28-NEXT:    [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
24798 // CHECK28-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1
24799 // CHECK28-NEXT:    store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4
24800 // CHECK28-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
24801 // CHECK28:       omp.body.continue:
24802 // CHECK28-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
24803 // CHECK28:       omp.inner.for.inc:
24804 // CHECK28-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
24805 // CHECK28-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP12]], 1
24806 // CHECK28-NEXT:    store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4
24807 // CHECK28-NEXT:    br label [[OMP_INNER_FOR_COND]]
24808 // CHECK28:       omp.inner.for.end:
24809 // CHECK28-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
24810 // CHECK28:       omp.loop.exit:
24811 // CHECK28-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
24812 // CHECK28-NEXT:    ret void
24813 //
24814 //
24815 // CHECK29-LABEL: define {{[^@]+}}@_Z3fooi
24816 // CHECK29-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] {
24817 // CHECK29-NEXT:  entry:
24818 // CHECK29-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
24819 // CHECK29-NEXT:    [[A:%.*]] = alloca i32, align 4
24820 // CHECK29-NEXT:    [[AA:%.*]] = alloca i16, align 2
24821 // CHECK29-NEXT:    [[B:%.*]] = alloca [10 x float], align 4
24822 // CHECK29-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 8
24823 // CHECK29-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
24824 // CHECK29-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 8
24825 // CHECK29-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i64, align 8
24826 // CHECK29-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8
24827 // CHECK29-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
24828 // CHECK29-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
24829 // CHECK29-NEXT:    [[I:%.*]] = alloca i32, align 4
24830 // CHECK29-NEXT:    [[I3:%.*]] = alloca i32, align 4
24831 // CHECK29-NEXT:    [[I10:%.*]] = alloca i32, align 4
24832 // CHECK29-NEXT:    [[I19:%.*]] = alloca i32, align 4
24833 // CHECK29-NEXT:    [[DOTCAPTURE_EXPR_30:%.*]] = alloca i32, align 4
24834 // CHECK29-NEXT:    [[I31:%.*]] = alloca i32, align 4
24835 // CHECK29-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
24836 // CHECK29-NEXT:    store i32 0, i32* [[A]], align 4
24837 // CHECK29-NEXT:    store i16 0, i16* [[AA]], align 2
24838 // CHECK29-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
24839 // CHECK29-NEXT:    [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
24840 // CHECK29-NEXT:    [[TMP2:%.*]] = call i8* @llvm.stacksave()
24841 // CHECK29-NEXT:    store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8
24842 // CHECK29-NEXT:    [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4
24843 // CHECK29-NEXT:    store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8
24844 // CHECK29-NEXT:    [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
24845 // CHECK29-NEXT:    [[TMP4:%.*]] = zext i32 [[TMP3]] to i64
24846 // CHECK29-NEXT:    [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]]
24847 // CHECK29-NEXT:    [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8
24848 // CHECK29-NEXT:    store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8
24849 // CHECK29-NEXT:    [[TMP6:%.*]] = load i32, i32* [[A]], align 4
24850 // CHECK29-NEXT:    store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_]], align 4
24851 // CHECK29-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
24852 // CHECK29-NEXT:    store i32 [[TMP7]], i32* [[DOTCAPTURE_EXPR_2]], align 4
24853 // CHECK29-NEXT:    store i32 0, i32* [[I]], align 4
24854 // CHECK29-NEXT:    br label [[FOR_COND:%.*]]
24855 // CHECK29:       for.cond:
24856 // CHECK29-NEXT:    [[TMP8:%.*]] = load i32, i32* [[I]], align 4
24857 // CHECK29-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP8]], 10
24858 // CHECK29-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
24859 // CHECK29:       for.body:
24860 // CHECK29-NEXT:    br label [[FOR_INC:%.*]]
24861 // CHECK29:       for.inc:
24862 // CHECK29-NEXT:    [[TMP9:%.*]] = load i32, i32* [[I]], align 4
24863 // CHECK29-NEXT:    [[INC:%.*]] = add nsw i32 [[TMP9]], 1
24864 // CHECK29-NEXT:    store i32 [[INC]], i32* [[I]], align 4
24865 // CHECK29-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]]
24866 // CHECK29:       for.end:
24867 // CHECK29-NEXT:    store i32 0, i32* [[I3]], align 4
24868 // CHECK29-NEXT:    br label [[FOR_COND4:%.*]]
24869 // CHECK29:       for.cond4:
24870 // CHECK29-NEXT:    [[TMP10:%.*]] = load i32, i32* [[I3]], align 4
24871 // CHECK29-NEXT:    [[CMP5:%.*]] = icmp slt i32 [[TMP10]], 10
24872 // CHECK29-NEXT:    br i1 [[CMP5]], label [[FOR_BODY6:%.*]], label [[FOR_END9:%.*]]
24873 // CHECK29:       for.body6:
24874 // CHECK29-NEXT:    [[TMP11:%.*]] = load i32, i32* [[A]], align 4
24875 // CHECK29-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP11]], 1
24876 // CHECK29-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
24877 // CHECK29-NEXT:    br label [[FOR_INC7:%.*]]
24878 // CHECK29:       for.inc7:
24879 // CHECK29-NEXT:    [[TMP12:%.*]] = load i32, i32* [[I3]], align 4
24880 // CHECK29-NEXT:    [[INC8:%.*]] = add nsw i32 [[TMP12]], 1
24881 // CHECK29-NEXT:    store i32 [[INC8]], i32* [[I3]], align 4
24882 // CHECK29-NEXT:    br label [[FOR_COND4]], !llvm.loop [[LOOP4:![0-9]+]]
24883 // CHECK29:       for.end9:
24884 // CHECK29-NEXT:    store i32 0, i32* [[I10]], align 4
24885 // CHECK29-NEXT:    br label [[FOR_COND11:%.*]]
24886 // CHECK29:       for.cond11:
24887 // CHECK29-NEXT:    [[TMP13:%.*]] = load i32, i32* [[I10]], align 4
24888 // CHECK29-NEXT:    [[CMP12:%.*]] = icmp slt i32 [[TMP13]], 10
24889 // CHECK29-NEXT:    br i1 [[CMP12]], label [[FOR_BODY13:%.*]], label [[FOR_END18:%.*]]
24890 // CHECK29:       for.body13:
24891 // CHECK29-NEXT:    [[TMP14:%.*]] = load i16, i16* [[AA]], align 2
24892 // CHECK29-NEXT:    [[CONV:%.*]] = sext i16 [[TMP14]] to i32
24893 // CHECK29-NEXT:    [[ADD14:%.*]] = add nsw i32 [[CONV]], 1
24894 // CHECK29-NEXT:    [[CONV15:%.*]] = trunc i32 [[ADD14]] to i16
24895 // CHECK29-NEXT:    store i16 [[CONV15]], i16* [[AA]], align 2
24896 // CHECK29-NEXT:    br label [[FOR_INC16:%.*]]
24897 // CHECK29:       for.inc16:
24898 // CHECK29-NEXT:    [[TMP15:%.*]] = load i32, i32* [[I10]], align 4
24899 // CHECK29-NEXT:    [[INC17:%.*]] = add nsw i32 [[TMP15]], 1
24900 // CHECK29-NEXT:    store i32 [[INC17]], i32* [[I10]], align 4
24901 // CHECK29-NEXT:    br label [[FOR_COND11]], !llvm.loop [[LOOP5:![0-9]+]]
24902 // CHECK29:       for.end18:
24903 // CHECK29-NEXT:    store i32 0, i32* [[I19]], align 4
24904 // CHECK29-NEXT:    br label [[FOR_COND20:%.*]]
24905 // CHECK29:       for.cond20:
24906 // CHECK29-NEXT:    [[TMP16:%.*]] = load i32, i32* [[I19]], align 4
24907 // CHECK29-NEXT:    [[CMP21:%.*]] = icmp slt i32 [[TMP16]], 10
24908 // CHECK29-NEXT:    br i1 [[CMP21]], label [[FOR_BODY22:%.*]], label [[FOR_END29:%.*]]
24909 // CHECK29:       for.body22:
24910 // CHECK29-NEXT:    [[TMP17:%.*]] = load i32, i32* [[A]], align 4
24911 // CHECK29-NEXT:    [[ADD23:%.*]] = add nsw i32 [[TMP17]], 1
24912 // CHECK29-NEXT:    store i32 [[ADD23]], i32* [[A]], align 4
24913 // CHECK29-NEXT:    [[TMP18:%.*]] = load i16, i16* [[AA]], align 2
24914 // CHECK29-NEXT:    [[CONV24:%.*]] = sext i16 [[TMP18]] to i32
24915 // CHECK29-NEXT:    [[ADD25:%.*]] = add nsw i32 [[CONV24]], 1
24916 // CHECK29-NEXT:    [[CONV26:%.*]] = trunc i32 [[ADD25]] to i16
24917 // CHECK29-NEXT:    store i16 [[CONV26]], i16* [[AA]], align 2
24918 // CHECK29-NEXT:    br label [[FOR_INC27:%.*]]
24919 // CHECK29:       for.inc27:
24920 // CHECK29-NEXT:    [[TMP19:%.*]] = load i32, i32* [[I19]], align 4
24921 // CHECK29-NEXT:    [[INC28:%.*]] = add nsw i32 [[TMP19]], 1
24922 // CHECK29-NEXT:    store i32 [[INC28]], i32* [[I19]], align 4
24923 // CHECK29-NEXT:    br label [[FOR_COND20]], !llvm.loop [[LOOP6:![0-9]+]]
24924 // CHECK29:       for.end29:
24925 // CHECK29-NEXT:    [[TMP20:%.*]] = load i32, i32* [[N_ADDR]], align 4
24926 // CHECK29-NEXT:    store i32 [[TMP20]], i32* [[DOTCAPTURE_EXPR_30]], align 4
24927 // CHECK29-NEXT:    store i32 0, i32* [[I31]], align 4
24928 // CHECK29-NEXT:    br label [[FOR_COND32:%.*]]
24929 // CHECK29:       for.cond32:
24930 // CHECK29-NEXT:    [[TMP21:%.*]] = load i32, i32* [[I31]], align 4
24931 // CHECK29-NEXT:    [[CMP33:%.*]] = icmp slt i32 [[TMP21]], 10
24932 // CHECK29-NEXT:    br i1 [[CMP33]], label [[FOR_BODY34:%.*]], label [[FOR_END55:%.*]]
24933 // CHECK29:       for.body34:
24934 // CHECK29-NEXT:    [[TMP22:%.*]] = load i32, i32* [[A]], align 4
24935 // CHECK29-NEXT:    [[ADD35:%.*]] = add nsw i32 [[TMP22]], 1
24936 // CHECK29-NEXT:    store i32 [[ADD35]], i32* [[A]], align 4
24937 // CHECK29-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2
24938 // CHECK29-NEXT:    [[TMP23:%.*]] = load float, float* [[ARRAYIDX]], align 4
24939 // CHECK29-NEXT:    [[CONV36:%.*]] = fpext float [[TMP23]] to double
24940 // CHECK29-NEXT:    [[ADD37:%.*]] = fadd double [[CONV36]], 1.000000e+00
24941 // CHECK29-NEXT:    [[CONV38:%.*]] = fptrunc double [[ADD37]] to float
24942 // CHECK29-NEXT:    store float [[CONV38]], float* [[ARRAYIDX]], align 4
24943 // CHECK29-NEXT:    [[ARRAYIDX39:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3
24944 // CHECK29-NEXT:    [[TMP24:%.*]] = load float, float* [[ARRAYIDX39]], align 4
24945 // CHECK29-NEXT:    [[CONV40:%.*]] = fpext float [[TMP24]] to double
24946 // CHECK29-NEXT:    [[ADD41:%.*]] = fadd double [[CONV40]], 1.000000e+00
24947 // CHECK29-NEXT:    [[CONV42:%.*]] = fptrunc double [[ADD41]] to float
24948 // CHECK29-NEXT:    store float [[CONV42]], float* [[ARRAYIDX39]], align 4
24949 // CHECK29-NEXT:    [[ARRAYIDX43:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1
24950 // CHECK29-NEXT:    [[ARRAYIDX44:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX43]], i64 0, i64 2
24951 // CHECK29-NEXT:    [[TMP25:%.*]] = load double, double* [[ARRAYIDX44]], align 8
24952 // CHECK29-NEXT:    [[ADD45:%.*]] = fadd double [[TMP25]], 1.000000e+00
24953 // CHECK29-NEXT:    store double [[ADD45]], double* [[ARRAYIDX44]], align 8
24954 // CHECK29-NEXT:    [[TMP26:%.*]] = mul nsw i64 1, [[TMP4]]
24955 // CHECK29-NEXT:    [[ARRAYIDX46:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP26]]
24956 // CHECK29-NEXT:    [[ARRAYIDX47:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX46]], i64 3
24957 // CHECK29-NEXT:    [[TMP27:%.*]] = load double, double* [[ARRAYIDX47]], align 8
24958 // CHECK29-NEXT:    [[ADD48:%.*]] = fadd double [[TMP27]], 1.000000e+00
24959 // CHECK29-NEXT:    store double [[ADD48]], double* [[ARRAYIDX47]], align 8
24960 // CHECK29-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0
24961 // CHECK29-NEXT:    [[TMP28:%.*]] = load i64, i64* [[X]], align 8
24962 // CHECK29-NEXT:    [[ADD49:%.*]] = add nsw i64 [[TMP28]], 1
24963 // CHECK29-NEXT:    store i64 [[ADD49]], i64* [[X]], align 8
24964 // CHECK29-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1
24965 // CHECK29-NEXT:    [[TMP29:%.*]] = load i8, i8* [[Y]], align 8
24966 // CHECK29-NEXT:    [[CONV50:%.*]] = sext i8 [[TMP29]] to i32
24967 // CHECK29-NEXT:    [[ADD51:%.*]] = add nsw i32 [[CONV50]], 1
24968 // CHECK29-NEXT:    [[CONV52:%.*]] = trunc i32 [[ADD51]] to i8
24969 // CHECK29-NEXT:    store i8 [[CONV52]], i8* [[Y]], align 8
24970 // CHECK29-NEXT:    br label [[FOR_INC53:%.*]]
24971 // CHECK29:       for.inc53:
24972 // CHECK29-NEXT:    [[TMP30:%.*]] = load i32, i32* [[I31]], align 4
24973 // CHECK29-NEXT:    [[INC54:%.*]] = add nsw i32 [[TMP30]], 1
24974 // CHECK29-NEXT:    store i32 [[INC54]], i32* [[I31]], align 4
24975 // CHECK29-NEXT:    br label [[FOR_COND32]], !llvm.loop [[LOOP7:![0-9]+]]
24976 // CHECK29:       for.end55:
24977 // CHECK29-NEXT:    [[TMP31:%.*]] = load i32, i32* [[A]], align 4
24978 // CHECK29-NEXT:    [[TMP32:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
24979 // CHECK29-NEXT:    call void @llvm.stackrestore(i8* [[TMP32]])
24980 // CHECK29-NEXT:    ret i32 [[TMP31]]
24981 //
24982 //
24983 // CHECK29-LABEL: define {{[^@]+}}@_Z3bari
24984 // CHECK29-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
24985 // CHECK29-NEXT:  entry:
24986 // CHECK29-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
24987 // CHECK29-NEXT:    [[A:%.*]] = alloca i32, align 4
24988 // CHECK29-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8
24989 // CHECK29-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
24990 // CHECK29-NEXT:    store i32 0, i32* [[A]], align 4
24991 // CHECK29-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
24992 // CHECK29-NEXT:    [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]])
24993 // CHECK29-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
24994 // CHECK29-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
24995 // CHECK29-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
24996 // CHECK29-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
24997 // CHECK29-NEXT:    [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]])
24998 // CHECK29-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
24999 // CHECK29-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
25000 // CHECK29-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
25001 // CHECK29-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
25002 // CHECK29-NEXT:    [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]])
25003 // CHECK29-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
25004 // CHECK29-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
25005 // CHECK29-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
25006 // CHECK29-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
25007 // CHECK29-NEXT:    [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]])
25008 // CHECK29-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
25009 // CHECK29-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
25010 // CHECK29-NEXT:    store i32 [[ADD6]], i32* [[A]], align 4
25011 // CHECK29-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
25012 // CHECK29-NEXT:    ret i32 [[TMP8]]
25013 //
25014 //
25015 // CHECK29-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
25016 // CHECK29-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 {
25017 // CHECK29-NEXT:  entry:
25018 // CHECK29-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
25019 // CHECK29-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
25020 // CHECK29-NEXT:    [[B:%.*]] = alloca i32, align 4
25021 // CHECK29-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 8
25022 // CHECK29-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
25023 // CHECK29-NEXT:    [[I:%.*]] = alloca i32, align 4
25024 // CHECK29-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
25025 // CHECK29-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
25026 // CHECK29-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
25027 // CHECK29-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
25028 // CHECK29-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
25029 // CHECK29-NEXT:    store i32 [[ADD]], i32* [[B]], align 4
25030 // CHECK29-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
25031 // CHECK29-NEXT:    [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
25032 // CHECK29-NEXT:    [[TMP3:%.*]] = call i8* @llvm.stacksave()
25033 // CHECK29-NEXT:    store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8
25034 // CHECK29-NEXT:    [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]
25035 // CHECK29-NEXT:    [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2
25036 // CHECK29-NEXT:    store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8
25037 // CHECK29-NEXT:    store i32 0, i32* [[I]], align 4
25038 // CHECK29-NEXT:    br label [[FOR_COND:%.*]]
25039 // CHECK29:       for.cond:
25040 // CHECK29-NEXT:    [[TMP5:%.*]] = load i32, i32* [[I]], align 4
25041 // CHECK29-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP5]], 10
25042 // CHECK29-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
25043 // CHECK29:       for.body:
25044 // CHECK29-NEXT:    [[TMP6:%.*]] = load i32, i32* [[B]], align 4
25045 // CHECK29-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP6]] to double
25046 // CHECK29-NEXT:    [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00
25047 // CHECK29-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
25048 // CHECK29-NEXT:    store double [[ADD2]], double* [[A]], align 8
25049 // CHECK29-NEXT:    [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
25050 // CHECK29-NEXT:    [[TMP7:%.*]] = load double, double* [[A3]], align 8
25051 // CHECK29-NEXT:    [[INC:%.*]] = fadd double [[TMP7]], 1.000000e+00
25052 // CHECK29-NEXT:    store double [[INC]], double* [[A3]], align 8
25053 // CHECK29-NEXT:    [[CONV4:%.*]] = fptosi double [[INC]] to i16
25054 // CHECK29-NEXT:    [[TMP8:%.*]] = mul nsw i64 1, [[TMP2]]
25055 // CHECK29-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP8]]
25056 // CHECK29-NEXT:    [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
25057 // CHECK29-NEXT:    store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2
25058 // CHECK29-NEXT:    br label [[FOR_INC:%.*]]
25059 // CHECK29:       for.inc:
25060 // CHECK29-NEXT:    [[TMP9:%.*]] = load i32, i32* [[I]], align 4
25061 // CHECK29-NEXT:    [[INC6:%.*]] = add nsw i32 [[TMP9]], 1
25062 // CHECK29-NEXT:    store i32 [[INC6]], i32* [[I]], align 4
25063 // CHECK29-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]]
25064 // CHECK29:       for.end:
25065 // CHECK29-NEXT:    [[TMP10:%.*]] = mul nsw i64 1, [[TMP2]]
25066 // CHECK29-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP10]]
25067 // CHECK29-NEXT:    [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX7]], i64 1
25068 // CHECK29-NEXT:    [[TMP11:%.*]] = load i16, i16* [[ARRAYIDX8]], align 2
25069 // CHECK29-NEXT:    [[CONV9:%.*]] = sext i16 [[TMP11]] to i32
25070 // CHECK29-NEXT:    [[TMP12:%.*]] = load i32, i32* [[B]], align 4
25071 // CHECK29-NEXT:    [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[TMP12]]
25072 // CHECK29-NEXT:    [[TMP13:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
25073 // CHECK29-NEXT:    call void @llvm.stackrestore(i8* [[TMP13]])
25074 // CHECK29-NEXT:    ret i32 [[ADD10]]
25075 //
25076 //
25077 // CHECK29-LABEL: define {{[^@]+}}@_ZL7fstatici
25078 // CHECK29-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
25079 // CHECK29-NEXT:  entry:
25080 // CHECK29-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
25081 // CHECK29-NEXT:    [[A:%.*]] = alloca i32, align 4
25082 // CHECK29-NEXT:    [[AA:%.*]] = alloca i16, align 2
25083 // CHECK29-NEXT:    [[AAA:%.*]] = alloca i8, align 1
25084 // CHECK29-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
25085 // CHECK29-NEXT:    [[I:%.*]] = alloca i32, align 4
25086 // CHECK29-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
25087 // CHECK29-NEXT:    store i32 0, i32* [[A]], align 4
25088 // CHECK29-NEXT:    store i16 0, i16* [[AA]], align 2
25089 // CHECK29-NEXT:    store i8 0, i8* [[AAA]], align 1
25090 // CHECK29-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
25091 // CHECK29-NEXT:    store i32 [[TMP0]], i32* [[I]], align 4
25092 // CHECK29-NEXT:    br label [[FOR_COND:%.*]]
25093 // CHECK29:       for.cond:
25094 // CHECK29-NEXT:    [[TMP1:%.*]] = load i32, i32* [[I]], align 4
25095 // CHECK29-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
25096 // CHECK29-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP1]], [[TMP2]]
25097 // CHECK29-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
25098 // CHECK29:       for.body:
25099 // CHECK29-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
25100 // CHECK29-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP3]], 1
25101 // CHECK29-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
25102 // CHECK29-NEXT:    [[TMP4:%.*]] = load i16, i16* [[AA]], align 2
25103 // CHECK29-NEXT:    [[CONV:%.*]] = sext i16 [[TMP4]] to i32
25104 // CHECK29-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
25105 // CHECK29-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
25106 // CHECK29-NEXT:    store i16 [[CONV2]], i16* [[AA]], align 2
25107 // CHECK29-NEXT:    [[TMP5:%.*]] = load i8, i8* [[AAA]], align 1
25108 // CHECK29-NEXT:    [[CONV3:%.*]] = sext i8 [[TMP5]] to i32
25109 // CHECK29-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
25110 // CHECK29-NEXT:    [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8
25111 // CHECK29-NEXT:    store i8 [[CONV5]], i8* [[AAA]], align 1
25112 // CHECK29-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2
25113 // CHECK29-NEXT:    [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
25114 // CHECK29-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP6]], 1
25115 // CHECK29-NEXT:    store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4
25116 // CHECK29-NEXT:    br label [[FOR_INC:%.*]]
25117 // CHECK29:       for.inc:
25118 // CHECK29-NEXT:    [[TMP7:%.*]] = load i32, i32* [[I]], align 4
25119 // CHECK29-NEXT:    [[INC:%.*]] = add nsw i32 [[TMP7]], 1
25120 // CHECK29-NEXT:    store i32 [[INC]], i32* [[I]], align 4
25121 // CHECK29-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]
25122 // CHECK29:       for.end:
25123 // CHECK29-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
25124 // CHECK29-NEXT:    ret i32 [[TMP8]]
25125 //
25126 //
25127 // CHECK29-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
25128 // CHECK29-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat {
25129 // CHECK29-NEXT:  entry:
25130 // CHECK29-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
25131 // CHECK29-NEXT:    [[A:%.*]] = alloca i32, align 4
25132 // CHECK29-NEXT:    [[AA:%.*]] = alloca i16, align 2
25133 // CHECK29-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
25134 // CHECK29-NEXT:    [[I:%.*]] = alloca i32, align 4
25135 // CHECK29-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
25136 // CHECK29-NEXT:    store i32 0, i32* [[A]], align 4
25137 // CHECK29-NEXT:    store i16 0, i16* [[AA]], align 2
25138 // CHECK29-NEXT:    store i32 0, i32* [[I]], align 4
25139 // CHECK29-NEXT:    br label [[FOR_COND:%.*]]
25140 // CHECK29:       for.cond:
25141 // CHECK29-NEXT:    [[TMP0:%.*]] = load i32, i32* [[I]], align 4
25142 // CHECK29-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10
25143 // CHECK29-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
25144 // CHECK29:       for.body:
25145 // CHECK29-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
25146 // CHECK29-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
25147 // CHECK29-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
25148 // CHECK29-NEXT:    [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
25149 // CHECK29-NEXT:    [[CONV:%.*]] = sext i16 [[TMP2]] to i32
25150 // CHECK29-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
25151 // CHECK29-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
25152 // CHECK29-NEXT:    store i16 [[CONV2]], i16* [[AA]], align 2
25153 // CHECK29-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2
25154 // CHECK29-NEXT:    [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
25155 // CHECK29-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1
25156 // CHECK29-NEXT:    store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4
25157 // CHECK29-NEXT:    br label [[FOR_INC:%.*]]
25158 // CHECK29:       for.inc:
25159 // CHECK29-NEXT:    [[TMP4:%.*]] = load i32, i32* [[I]], align 4
25160 // CHECK29-NEXT:    [[INC:%.*]] = add nsw i32 [[TMP4]], 1
25161 // CHECK29-NEXT:    store i32 [[INC]], i32* [[I]], align 4
25162 // CHECK29-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]
25163 // CHECK29:       for.end:
25164 // CHECK29-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
25165 // CHECK29-NEXT:    ret i32 [[TMP5]]
25166 //
25167 //
25168 // CHECK30-LABEL: define {{[^@]+}}@_Z3fooi
25169 // CHECK30-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] {
25170 // CHECK30-NEXT:  entry:
25171 // CHECK30-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
25172 // CHECK30-NEXT:    [[A:%.*]] = alloca i32, align 4
25173 // CHECK30-NEXT:    [[AA:%.*]] = alloca i16, align 2
25174 // CHECK30-NEXT:    [[B:%.*]] = alloca [10 x float], align 4
25175 // CHECK30-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 8
25176 // CHECK30-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
25177 // CHECK30-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 8
25178 // CHECK30-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i64, align 8
25179 // CHECK30-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8
25180 // CHECK30-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
25181 // CHECK30-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
25182 // CHECK30-NEXT:    [[I:%.*]] = alloca i32, align 4
25183 // CHECK30-NEXT:    [[I3:%.*]] = alloca i32, align 4
25184 // CHECK30-NEXT:    [[I10:%.*]] = alloca i32, align 4
25185 // CHECK30-NEXT:    [[I19:%.*]] = alloca i32, align 4
25186 // CHECK30-NEXT:    [[DOTCAPTURE_EXPR_30:%.*]] = alloca i32, align 4
25187 // CHECK30-NEXT:    [[I31:%.*]] = alloca i32, align 4
25188 // CHECK30-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
25189 // CHECK30-NEXT:    store i32 0, i32* [[A]], align 4
25190 // CHECK30-NEXT:    store i16 0, i16* [[AA]], align 2
25191 // CHECK30-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
25192 // CHECK30-NEXT:    [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
25193 // CHECK30-NEXT:    [[TMP2:%.*]] = call i8* @llvm.stacksave()
25194 // CHECK30-NEXT:    store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8
25195 // CHECK30-NEXT:    [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4
25196 // CHECK30-NEXT:    store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8
25197 // CHECK30-NEXT:    [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
25198 // CHECK30-NEXT:    [[TMP4:%.*]] = zext i32 [[TMP3]] to i64
25199 // CHECK30-NEXT:    [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]]
25200 // CHECK30-NEXT:    [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8
25201 // CHECK30-NEXT:    store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8
25202 // CHECK30-NEXT:    [[TMP6:%.*]] = load i32, i32* [[A]], align 4
25203 // CHECK30-NEXT:    store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_]], align 4
25204 // CHECK30-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
25205 // CHECK30-NEXT:    store i32 [[TMP7]], i32* [[DOTCAPTURE_EXPR_2]], align 4
25206 // CHECK30-NEXT:    store i32 0, i32* [[I]], align 4
25207 // CHECK30-NEXT:    br label [[FOR_COND:%.*]]
25208 // CHECK30:       for.cond:
25209 // CHECK30-NEXT:    [[TMP8:%.*]] = load i32, i32* [[I]], align 4
25210 // CHECK30-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP8]], 10
25211 // CHECK30-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
25212 // CHECK30:       for.body:
25213 // CHECK30-NEXT:    br label [[FOR_INC:%.*]]
25214 // CHECK30:       for.inc:
25215 // CHECK30-NEXT:    [[TMP9:%.*]] = load i32, i32* [[I]], align 4
25216 // CHECK30-NEXT:    [[INC:%.*]] = add nsw i32 [[TMP9]], 1
25217 // CHECK30-NEXT:    store i32 [[INC]], i32* [[I]], align 4
25218 // CHECK30-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]]
25219 // CHECK30:       for.end:
25220 // CHECK30-NEXT:    store i32 0, i32* [[I3]], align 4
25221 // CHECK30-NEXT:    br label [[FOR_COND4:%.*]]
25222 // CHECK30:       for.cond4:
25223 // CHECK30-NEXT:    [[TMP10:%.*]] = load i32, i32* [[I3]], align 4
25224 // CHECK30-NEXT:    [[CMP5:%.*]] = icmp slt i32 [[TMP10]], 10
25225 // CHECK30-NEXT:    br i1 [[CMP5]], label [[FOR_BODY6:%.*]], label [[FOR_END9:%.*]]
25226 // CHECK30:       for.body6:
25227 // CHECK30-NEXT:    [[TMP11:%.*]] = load i32, i32* [[A]], align 4
25228 // CHECK30-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP11]], 1
25229 // CHECK30-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
25230 // CHECK30-NEXT:    br label [[FOR_INC7:%.*]]
25231 // CHECK30:       for.inc7:
25232 // CHECK30-NEXT:    [[TMP12:%.*]] = load i32, i32* [[I3]], align 4
25233 // CHECK30-NEXT:    [[INC8:%.*]] = add nsw i32 [[TMP12]], 1
25234 // CHECK30-NEXT:    store i32 [[INC8]], i32* [[I3]], align 4
25235 // CHECK30-NEXT:    br label [[FOR_COND4]], !llvm.loop [[LOOP4:![0-9]+]]
25236 // CHECK30:       for.end9:
25237 // CHECK30-NEXT:    store i32 0, i32* [[I10]], align 4
25238 // CHECK30-NEXT:    br label [[FOR_COND11:%.*]]
25239 // CHECK30:       for.cond11:
25240 // CHECK30-NEXT:    [[TMP13:%.*]] = load i32, i32* [[I10]], align 4
25241 // CHECK30-NEXT:    [[CMP12:%.*]] = icmp slt i32 [[TMP13]], 10
25242 // CHECK30-NEXT:    br i1 [[CMP12]], label [[FOR_BODY13:%.*]], label [[FOR_END18:%.*]]
25243 // CHECK30:       for.body13:
25244 // CHECK30-NEXT:    [[TMP14:%.*]] = load i16, i16* [[AA]], align 2
25245 // CHECK30-NEXT:    [[CONV:%.*]] = sext i16 [[TMP14]] to i32
25246 // CHECK30-NEXT:    [[ADD14:%.*]] = add nsw i32 [[CONV]], 1
25247 // CHECK30-NEXT:    [[CONV15:%.*]] = trunc i32 [[ADD14]] to i16
25248 // CHECK30-NEXT:    store i16 [[CONV15]], i16* [[AA]], align 2
25249 // CHECK30-NEXT:    br label [[FOR_INC16:%.*]]
25250 // CHECK30:       for.inc16:
25251 // CHECK30-NEXT:    [[TMP15:%.*]] = load i32, i32* [[I10]], align 4
25252 // CHECK30-NEXT:    [[INC17:%.*]] = add nsw i32 [[TMP15]], 1
25253 // CHECK30-NEXT:    store i32 [[INC17]], i32* [[I10]], align 4
25254 // CHECK30-NEXT:    br label [[FOR_COND11]], !llvm.loop [[LOOP5:![0-9]+]]
25255 // CHECK30:       for.end18:
25256 // CHECK30-NEXT:    store i32 0, i32* [[I19]], align 4
25257 // CHECK30-NEXT:    br label [[FOR_COND20:%.*]]
25258 // CHECK30:       for.cond20:
25259 // CHECK30-NEXT:    [[TMP16:%.*]] = load i32, i32* [[I19]], align 4
25260 // CHECK30-NEXT:    [[CMP21:%.*]] = icmp slt i32 [[TMP16]], 10
25261 // CHECK30-NEXT:    br i1 [[CMP21]], label [[FOR_BODY22:%.*]], label [[FOR_END29:%.*]]
25262 // CHECK30:       for.body22:
25263 // CHECK30-NEXT:    [[TMP17:%.*]] = load i32, i32* [[A]], align 4
25264 // CHECK30-NEXT:    [[ADD23:%.*]] = add nsw i32 [[TMP17]], 1
25265 // CHECK30-NEXT:    store i32 [[ADD23]], i32* [[A]], align 4
25266 // CHECK30-NEXT:    [[TMP18:%.*]] = load i16, i16* [[AA]], align 2
25267 // CHECK30-NEXT:    [[CONV24:%.*]] = sext i16 [[TMP18]] to i32
25268 // CHECK30-NEXT:    [[ADD25:%.*]] = add nsw i32 [[CONV24]], 1
25269 // CHECK30-NEXT:    [[CONV26:%.*]] = trunc i32 [[ADD25]] to i16
25270 // CHECK30-NEXT:    store i16 [[CONV26]], i16* [[AA]], align 2
25271 // CHECK30-NEXT:    br label [[FOR_INC27:%.*]]
25272 // CHECK30:       for.inc27:
25273 // CHECK30-NEXT:    [[TMP19:%.*]] = load i32, i32* [[I19]], align 4
25274 // CHECK30-NEXT:    [[INC28:%.*]] = add nsw i32 [[TMP19]], 1
25275 // CHECK30-NEXT:    store i32 [[INC28]], i32* [[I19]], align 4
25276 // CHECK30-NEXT:    br label [[FOR_COND20]], !llvm.loop [[LOOP6:![0-9]+]]
25277 // CHECK30:       for.end29:
25278 // CHECK30-NEXT:    [[TMP20:%.*]] = load i32, i32* [[N_ADDR]], align 4
25279 // CHECK30-NEXT:    store i32 [[TMP20]], i32* [[DOTCAPTURE_EXPR_30]], align 4
25280 // CHECK30-NEXT:    store i32 0, i32* [[I31]], align 4
25281 // CHECK30-NEXT:    br label [[FOR_COND32:%.*]]
25282 // CHECK30:       for.cond32:
25283 // CHECK30-NEXT:    [[TMP21:%.*]] = load i32, i32* [[I31]], align 4
25284 // CHECK30-NEXT:    [[CMP33:%.*]] = icmp slt i32 [[TMP21]], 10
25285 // CHECK30-NEXT:    br i1 [[CMP33]], label [[FOR_BODY34:%.*]], label [[FOR_END55:%.*]]
25286 // CHECK30:       for.body34:
25287 // CHECK30-NEXT:    [[TMP22:%.*]] = load i32, i32* [[A]], align 4
25288 // CHECK30-NEXT:    [[ADD35:%.*]] = add nsw i32 [[TMP22]], 1
25289 // CHECK30-NEXT:    store i32 [[ADD35]], i32* [[A]], align 4
25290 // CHECK30-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2
25291 // CHECK30-NEXT:    [[TMP23:%.*]] = load float, float* [[ARRAYIDX]], align 4
25292 // CHECK30-NEXT:    [[CONV36:%.*]] = fpext float [[TMP23]] to double
25293 // CHECK30-NEXT:    [[ADD37:%.*]] = fadd double [[CONV36]], 1.000000e+00
25294 // CHECK30-NEXT:    [[CONV38:%.*]] = fptrunc double [[ADD37]] to float
25295 // CHECK30-NEXT:    store float [[CONV38]], float* [[ARRAYIDX]], align 4
25296 // CHECK30-NEXT:    [[ARRAYIDX39:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3
25297 // CHECK30-NEXT:    [[TMP24:%.*]] = load float, float* [[ARRAYIDX39]], align 4
25298 // CHECK30-NEXT:    [[CONV40:%.*]] = fpext float [[TMP24]] to double
25299 // CHECK30-NEXT:    [[ADD41:%.*]] = fadd double [[CONV40]], 1.000000e+00
25300 // CHECK30-NEXT:    [[CONV42:%.*]] = fptrunc double [[ADD41]] to float
25301 // CHECK30-NEXT:    store float [[CONV42]], float* [[ARRAYIDX39]], align 4
25302 // CHECK30-NEXT:    [[ARRAYIDX43:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1
25303 // CHECK30-NEXT:    [[ARRAYIDX44:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX43]], i64 0, i64 2
25304 // CHECK30-NEXT:    [[TMP25:%.*]] = load double, double* [[ARRAYIDX44]], align 8
25305 // CHECK30-NEXT:    [[ADD45:%.*]] = fadd double [[TMP25]], 1.000000e+00
25306 // CHECK30-NEXT:    store double [[ADD45]], double* [[ARRAYIDX44]], align 8
25307 // CHECK30-NEXT:    [[TMP26:%.*]] = mul nsw i64 1, [[TMP4]]
25308 // CHECK30-NEXT:    [[ARRAYIDX46:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP26]]
25309 // CHECK30-NEXT:    [[ARRAYIDX47:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX46]], i64 3
25310 // CHECK30-NEXT:    [[TMP27:%.*]] = load double, double* [[ARRAYIDX47]], align 8
25311 // CHECK30-NEXT:    [[ADD48:%.*]] = fadd double [[TMP27]], 1.000000e+00
25312 // CHECK30-NEXT:    store double [[ADD48]], double* [[ARRAYIDX47]], align 8
25313 // CHECK30-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0
25314 // CHECK30-NEXT:    [[TMP28:%.*]] = load i64, i64* [[X]], align 8
25315 // CHECK30-NEXT:    [[ADD49:%.*]] = add nsw i64 [[TMP28]], 1
25316 // CHECK30-NEXT:    store i64 [[ADD49]], i64* [[X]], align 8
25317 // CHECK30-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1
25318 // CHECK30-NEXT:    [[TMP29:%.*]] = load i8, i8* [[Y]], align 8
25319 // CHECK30-NEXT:    [[CONV50:%.*]] = sext i8 [[TMP29]] to i32
25320 // CHECK30-NEXT:    [[ADD51:%.*]] = add nsw i32 [[CONV50]], 1
25321 // CHECK30-NEXT:    [[CONV52:%.*]] = trunc i32 [[ADD51]] to i8
25322 // CHECK30-NEXT:    store i8 [[CONV52]], i8* [[Y]], align 8
25323 // CHECK30-NEXT:    br label [[FOR_INC53:%.*]]
25324 // CHECK30:       for.inc53:
25325 // CHECK30-NEXT:    [[TMP30:%.*]] = load i32, i32* [[I31]], align 4
25326 // CHECK30-NEXT:    [[INC54:%.*]] = add nsw i32 [[TMP30]], 1
25327 // CHECK30-NEXT:    store i32 [[INC54]], i32* [[I31]], align 4
25328 // CHECK30-NEXT:    br label [[FOR_COND32]], !llvm.loop [[LOOP7:![0-9]+]]
25329 // CHECK30:       for.end55:
25330 // CHECK30-NEXT:    [[TMP31:%.*]] = load i32, i32* [[A]], align 4
25331 // CHECK30-NEXT:    [[TMP32:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
25332 // CHECK30-NEXT:    call void @llvm.stackrestore(i8* [[TMP32]])
25333 // CHECK30-NEXT:    ret i32 [[TMP31]]
25334 //
25335 //
25336 // CHECK30-LABEL: define {{[^@]+}}@_Z3bari
25337 // CHECK30-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
25338 // CHECK30-NEXT:  entry:
25339 // CHECK30-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
25340 // CHECK30-NEXT:    [[A:%.*]] = alloca i32, align 4
25341 // CHECK30-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8
25342 // CHECK30-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
25343 // CHECK30-NEXT:    store i32 0, i32* [[A]], align 4
25344 // CHECK30-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
25345 // CHECK30-NEXT:    [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]])
25346 // CHECK30-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
25347 // CHECK30-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
25348 // CHECK30-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
25349 // CHECK30-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
25350 // CHECK30-NEXT:    [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]])
25351 // CHECK30-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
25352 // CHECK30-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
25353 // CHECK30-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
25354 // CHECK30-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
25355 // CHECK30-NEXT:    [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]])
25356 // CHECK30-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
25357 // CHECK30-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
25358 // CHECK30-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
25359 // CHECK30-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
25360 // CHECK30-NEXT:    [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]])
25361 // CHECK30-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
25362 // CHECK30-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
25363 // CHECK30-NEXT:    store i32 [[ADD6]], i32* [[A]], align 4
25364 // CHECK30-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
25365 // CHECK30-NEXT:    ret i32 [[TMP8]]
25366 //
25367 //
25368 // CHECK30-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
25369 // CHECK30-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 {
25370 // CHECK30-NEXT:  entry:
25371 // CHECK30-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
25372 // CHECK30-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
25373 // CHECK30-NEXT:    [[B:%.*]] = alloca i32, align 4
25374 // CHECK30-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 8
25375 // CHECK30-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
25376 // CHECK30-NEXT:    [[I:%.*]] = alloca i32, align 4
25377 // CHECK30-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
25378 // CHECK30-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
25379 // CHECK30-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
25380 // CHECK30-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
25381 // CHECK30-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
25382 // CHECK30-NEXT:    store i32 [[ADD]], i32* [[B]], align 4
25383 // CHECK30-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
25384 // CHECK30-NEXT:    [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
25385 // CHECK30-NEXT:    [[TMP3:%.*]] = call i8* @llvm.stacksave()
25386 // CHECK30-NEXT:    store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8
25387 // CHECK30-NEXT:    [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]
25388 // CHECK30-NEXT:    [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2
25389 // CHECK30-NEXT:    store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8
25390 // CHECK30-NEXT:    store i32 0, i32* [[I]], align 4
25391 // CHECK30-NEXT:    br label [[FOR_COND:%.*]]
25392 // CHECK30:       for.cond:
25393 // CHECK30-NEXT:    [[TMP5:%.*]] = load i32, i32* [[I]], align 4
25394 // CHECK30-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP5]], 10
25395 // CHECK30-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
25396 // CHECK30:       for.body:
25397 // CHECK30-NEXT:    [[TMP6:%.*]] = load i32, i32* [[B]], align 4
25398 // CHECK30-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP6]] to double
25399 // CHECK30-NEXT:    [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00
25400 // CHECK30-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
25401 // CHECK30-NEXT:    store double [[ADD2]], double* [[A]], align 8
25402 // CHECK30-NEXT:    [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
25403 // CHECK30-NEXT:    [[TMP7:%.*]] = load double, double* [[A3]], align 8
25404 // CHECK30-NEXT:    [[INC:%.*]] = fadd double [[TMP7]], 1.000000e+00
25405 // CHECK30-NEXT:    store double [[INC]], double* [[A3]], align 8
25406 // CHECK30-NEXT:    [[CONV4:%.*]] = fptosi double [[INC]] to i16
25407 // CHECK30-NEXT:    [[TMP8:%.*]] = mul nsw i64 1, [[TMP2]]
25408 // CHECK30-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP8]]
25409 // CHECK30-NEXT:    [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
25410 // CHECK30-NEXT:    store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2
25411 // CHECK30-NEXT:    br label [[FOR_INC:%.*]]
25412 // CHECK30:       for.inc:
25413 // CHECK30-NEXT:    [[TMP9:%.*]] = load i32, i32* [[I]], align 4
25414 // CHECK30-NEXT:    [[INC6:%.*]] = add nsw i32 [[TMP9]], 1
25415 // CHECK30-NEXT:    store i32 [[INC6]], i32* [[I]], align 4
25416 // CHECK30-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]]
25417 // CHECK30:       for.end:
25418 // CHECK30-NEXT:    [[TMP10:%.*]] = mul nsw i64 1, [[TMP2]]
25419 // CHECK30-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP10]]
25420 // CHECK30-NEXT:    [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX7]], i64 1
25421 // CHECK30-NEXT:    [[TMP11:%.*]] = load i16, i16* [[ARRAYIDX8]], align 2
25422 // CHECK30-NEXT:    [[CONV9:%.*]] = sext i16 [[TMP11]] to i32
25423 // CHECK30-NEXT:    [[TMP12:%.*]] = load i32, i32* [[B]], align 4
25424 // CHECK30-NEXT:    [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[TMP12]]
25425 // CHECK30-NEXT:    [[TMP13:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
25426 // CHECK30-NEXT:    call void @llvm.stackrestore(i8* [[TMP13]])
25427 // CHECK30-NEXT:    ret i32 [[ADD10]]
25428 //
25429 //
25430 // CHECK30-LABEL: define {{[^@]+}}@_ZL7fstatici
25431 // CHECK30-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
25432 // CHECK30-NEXT:  entry:
25433 // CHECK30-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
25434 // CHECK30-NEXT:    [[A:%.*]] = alloca i32, align 4
25435 // CHECK30-NEXT:    [[AA:%.*]] = alloca i16, align 2
25436 // CHECK30-NEXT:    [[AAA:%.*]] = alloca i8, align 1
25437 // CHECK30-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
25438 // CHECK30-NEXT:    [[I:%.*]] = alloca i32, align 4
25439 // CHECK30-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
25440 // CHECK30-NEXT:    store i32 0, i32* [[A]], align 4
25441 // CHECK30-NEXT:    store i16 0, i16* [[AA]], align 2
25442 // CHECK30-NEXT:    store i8 0, i8* [[AAA]], align 1
25443 // CHECK30-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
25444 // CHECK30-NEXT:    store i32 [[TMP0]], i32* [[I]], align 4
25445 // CHECK30-NEXT:    br label [[FOR_COND:%.*]]
25446 // CHECK30:       for.cond:
25447 // CHECK30-NEXT:    [[TMP1:%.*]] = load i32, i32* [[I]], align 4
25448 // CHECK30-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
25449 // CHECK30-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP1]], [[TMP2]]
25450 // CHECK30-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
25451 // CHECK30:       for.body:
25452 // CHECK30-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
25453 // CHECK30-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP3]], 1
25454 // CHECK30-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
25455 // CHECK30-NEXT:    [[TMP4:%.*]] = load i16, i16* [[AA]], align 2
25456 // CHECK30-NEXT:    [[CONV:%.*]] = sext i16 [[TMP4]] to i32
25457 // CHECK30-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
25458 // CHECK30-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
25459 // CHECK30-NEXT:    store i16 [[CONV2]], i16* [[AA]], align 2
25460 // CHECK30-NEXT:    [[TMP5:%.*]] = load i8, i8* [[AAA]], align 1
25461 // CHECK30-NEXT:    [[CONV3:%.*]] = sext i8 [[TMP5]] to i32
25462 // CHECK30-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
25463 // CHECK30-NEXT:    [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8
25464 // CHECK30-NEXT:    store i8 [[CONV5]], i8* [[AAA]], align 1
25465 // CHECK30-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2
25466 // CHECK30-NEXT:    [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
25467 // CHECK30-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP6]], 1
25468 // CHECK30-NEXT:    store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4
25469 // CHECK30-NEXT:    br label [[FOR_INC:%.*]]
25470 // CHECK30:       for.inc:
25471 // CHECK30-NEXT:    [[TMP7:%.*]] = load i32, i32* [[I]], align 4
25472 // CHECK30-NEXT:    [[INC:%.*]] = add nsw i32 [[TMP7]], 1
25473 // CHECK30-NEXT:    store i32 [[INC]], i32* [[I]], align 4
25474 // CHECK30-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]
25475 // CHECK30:       for.end:
25476 // CHECK30-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
25477 // CHECK30-NEXT:    ret i32 [[TMP8]]
25478 //
25479 //
25480 // CHECK30-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
25481 // CHECK30-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat {
25482 // CHECK30-NEXT:  entry:
25483 // CHECK30-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
25484 // CHECK30-NEXT:    [[A:%.*]] = alloca i32, align 4
25485 // CHECK30-NEXT:    [[AA:%.*]] = alloca i16, align 2
25486 // CHECK30-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
25487 // CHECK30-NEXT:    [[I:%.*]] = alloca i32, align 4
25488 // CHECK30-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
25489 // CHECK30-NEXT:    store i32 0, i32* [[A]], align 4
25490 // CHECK30-NEXT:    store i16 0, i16* [[AA]], align 2
25491 // CHECK30-NEXT:    store i32 0, i32* [[I]], align 4
25492 // CHECK30-NEXT:    br label [[FOR_COND:%.*]]
25493 // CHECK30:       for.cond:
25494 // CHECK30-NEXT:    [[TMP0:%.*]] = load i32, i32* [[I]], align 4
25495 // CHECK30-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10
25496 // CHECK30-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
25497 // CHECK30:       for.body:
25498 // CHECK30-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
25499 // CHECK30-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
25500 // CHECK30-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
25501 // CHECK30-NEXT:    [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
25502 // CHECK30-NEXT:    [[CONV:%.*]] = sext i16 [[TMP2]] to i32
25503 // CHECK30-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
25504 // CHECK30-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
25505 // CHECK30-NEXT:    store i16 [[CONV2]], i16* [[AA]], align 2
25506 // CHECK30-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2
25507 // CHECK30-NEXT:    [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
25508 // CHECK30-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1
25509 // CHECK30-NEXT:    store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4
25510 // CHECK30-NEXT:    br label [[FOR_INC:%.*]]
25511 // CHECK30:       for.inc:
25512 // CHECK30-NEXT:    [[TMP4:%.*]] = load i32, i32* [[I]], align 4
25513 // CHECK30-NEXT:    [[INC:%.*]] = add nsw i32 [[TMP4]], 1
25514 // CHECK30-NEXT:    store i32 [[INC]], i32* [[I]], align 4
25515 // CHECK30-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]
25516 // CHECK30:       for.end:
25517 // CHECK30-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
25518 // CHECK30-NEXT:    ret i32 [[TMP5]]
25519 //
25520 //
25521 // CHECK31-LABEL: define {{[^@]+}}@_Z3fooi
25522 // CHECK31-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] {
25523 // CHECK31-NEXT:  entry:
25524 // CHECK31-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
25525 // CHECK31-NEXT:    [[A:%.*]] = alloca i32, align 4
25526 // CHECK31-NEXT:    [[AA:%.*]] = alloca i16, align 2
25527 // CHECK31-NEXT:    [[B:%.*]] = alloca [10 x float], align 4
25528 // CHECK31-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 4
25529 // CHECK31-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 4
25530 // CHECK31-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 8
25531 // CHECK31-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i32, align 4
25532 // CHECK31-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4
25533 // CHECK31-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
25534 // CHECK31-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
25535 // CHECK31-NEXT:    [[I:%.*]] = alloca i32, align 4
25536 // CHECK31-NEXT:    [[I3:%.*]] = alloca i32, align 4
25537 // CHECK31-NEXT:    [[I10:%.*]] = alloca i32, align 4
25538 // CHECK31-NEXT:    [[I19:%.*]] = alloca i32, align 4
25539 // CHECK31-NEXT:    [[DOTCAPTURE_EXPR_30:%.*]] = alloca i32, align 4
25540 // CHECK31-NEXT:    [[I31:%.*]] = alloca i32, align 4
25541 // CHECK31-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
25542 // CHECK31-NEXT:    store i32 0, i32* [[A]], align 4
25543 // CHECK31-NEXT:    store i16 0, i16* [[AA]], align 2
25544 // CHECK31-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
25545 // CHECK31-NEXT:    [[TMP1:%.*]] = call i8* @llvm.stacksave()
25546 // CHECK31-NEXT:    store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4
25547 // CHECK31-NEXT:    [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4
25548 // CHECK31-NEXT:    store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4
25549 // CHECK31-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
25550 // CHECK31-NEXT:    [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]]
25551 // CHECK31-NEXT:    [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8
25552 // CHECK31-NEXT:    store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4
25553 // CHECK31-NEXT:    [[TMP4:%.*]] = load i32, i32* [[A]], align 4
25554 // CHECK31-NEXT:    store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4
25555 // CHECK31-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
25556 // CHECK31-NEXT:    store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_2]], align 4
25557 // CHECK31-NEXT:    store i32 0, i32* [[I]], align 4
25558 // CHECK31-NEXT:    br label [[FOR_COND:%.*]]
25559 // CHECK31:       for.cond:
25560 // CHECK31-NEXT:    [[TMP6:%.*]] = load i32, i32* [[I]], align 4
25561 // CHECK31-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP6]], 10
25562 // CHECK31-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
25563 // CHECK31:       for.body:
25564 // CHECK31-NEXT:    br label [[FOR_INC:%.*]]
25565 // CHECK31:       for.inc:
25566 // CHECK31-NEXT:    [[TMP7:%.*]] = load i32, i32* [[I]], align 4
25567 // CHECK31-NEXT:    [[INC:%.*]] = add nsw i32 [[TMP7]], 1
25568 // CHECK31-NEXT:    store i32 [[INC]], i32* [[I]], align 4
25569 // CHECK31-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]
25570 // CHECK31:       for.end:
25571 // CHECK31-NEXT:    store i32 0, i32* [[I3]], align 4
25572 // CHECK31-NEXT:    br label [[FOR_COND4:%.*]]
25573 // CHECK31:       for.cond4:
25574 // CHECK31-NEXT:    [[TMP8:%.*]] = load i32, i32* [[I3]], align 4
25575 // CHECK31-NEXT:    [[CMP5:%.*]] = icmp slt i32 [[TMP8]], 10
25576 // CHECK31-NEXT:    br i1 [[CMP5]], label [[FOR_BODY6:%.*]], label [[FOR_END9:%.*]]
25577 // CHECK31:       for.body6:
25578 // CHECK31-NEXT:    [[TMP9:%.*]] = load i32, i32* [[A]], align 4
25579 // CHECK31-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP9]], 1
25580 // CHECK31-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
25581 // CHECK31-NEXT:    br label [[FOR_INC7:%.*]]
25582 // CHECK31:       for.inc7:
25583 // CHECK31-NEXT:    [[TMP10:%.*]] = load i32, i32* [[I3]], align 4
25584 // CHECK31-NEXT:    [[INC8:%.*]] = add nsw i32 [[TMP10]], 1
25585 // CHECK31-NEXT:    store i32 [[INC8]], i32* [[I3]], align 4
25586 // CHECK31-NEXT:    br label [[FOR_COND4]], !llvm.loop [[LOOP5:![0-9]+]]
25587 // CHECK31:       for.end9:
25588 // CHECK31-NEXT:    store i32 0, i32* [[I10]], align 4
25589 // CHECK31-NEXT:    br label [[FOR_COND11:%.*]]
25590 // CHECK31:       for.cond11:
25591 // CHECK31-NEXT:    [[TMP11:%.*]] = load i32, i32* [[I10]], align 4
25592 // CHECK31-NEXT:    [[CMP12:%.*]] = icmp slt i32 [[TMP11]], 10
25593 // CHECK31-NEXT:    br i1 [[CMP12]], label [[FOR_BODY13:%.*]], label [[FOR_END18:%.*]]
25594 // CHECK31:       for.body13:
25595 // CHECK31-NEXT:    [[TMP12:%.*]] = load i16, i16* [[AA]], align 2
25596 // CHECK31-NEXT:    [[CONV:%.*]] = sext i16 [[TMP12]] to i32
25597 // CHECK31-NEXT:    [[ADD14:%.*]] = add nsw i32 [[CONV]], 1
25598 // CHECK31-NEXT:    [[CONV15:%.*]] = trunc i32 [[ADD14]] to i16
25599 // CHECK31-NEXT:    store i16 [[CONV15]], i16* [[AA]], align 2
25600 // CHECK31-NEXT:    br label [[FOR_INC16:%.*]]
25601 // CHECK31:       for.inc16:
25602 // CHECK31-NEXT:    [[TMP13:%.*]] = load i32, i32* [[I10]], align 4
25603 // CHECK31-NEXT:    [[INC17:%.*]] = add nsw i32 [[TMP13]], 1
25604 // CHECK31-NEXT:    store i32 [[INC17]], i32* [[I10]], align 4
25605 // CHECK31-NEXT:    br label [[FOR_COND11]], !llvm.loop [[LOOP6:![0-9]+]]
25606 // CHECK31:       for.end18:
25607 // CHECK31-NEXT:    store i32 0, i32* [[I19]], align 4
25608 // CHECK31-NEXT:    br label [[FOR_COND20:%.*]]
25609 // CHECK31:       for.cond20:
25610 // CHECK31-NEXT:    [[TMP14:%.*]] = load i32, i32* [[I19]], align 4
25611 // CHECK31-NEXT:    [[CMP21:%.*]] = icmp slt i32 [[TMP14]], 10
25612 // CHECK31-NEXT:    br i1 [[CMP21]], label [[FOR_BODY22:%.*]], label [[FOR_END29:%.*]]
25613 // CHECK31:       for.body22:
25614 // CHECK31-NEXT:    [[TMP15:%.*]] = load i32, i32* [[A]], align 4
25615 // CHECK31-NEXT:    [[ADD23:%.*]] = add nsw i32 [[TMP15]], 1
25616 // CHECK31-NEXT:    store i32 [[ADD23]], i32* [[A]], align 4
25617 // CHECK31-NEXT:    [[TMP16:%.*]] = load i16, i16* [[AA]], align 2
25618 // CHECK31-NEXT:    [[CONV24:%.*]] = sext i16 [[TMP16]] to i32
25619 // CHECK31-NEXT:    [[ADD25:%.*]] = add nsw i32 [[CONV24]], 1
25620 // CHECK31-NEXT:    [[CONV26:%.*]] = trunc i32 [[ADD25]] to i16
25621 // CHECK31-NEXT:    store i16 [[CONV26]], i16* [[AA]], align 2
25622 // CHECK31-NEXT:    br label [[FOR_INC27:%.*]]
25623 // CHECK31:       for.inc27:
25624 // CHECK31-NEXT:    [[TMP17:%.*]] = load i32, i32* [[I19]], align 4
25625 // CHECK31-NEXT:    [[INC28:%.*]] = add nsw i32 [[TMP17]], 1
25626 // CHECK31-NEXT:    store i32 [[INC28]], i32* [[I19]], align 4
25627 // CHECK31-NEXT:    br label [[FOR_COND20]], !llvm.loop [[LOOP7:![0-9]+]]
25628 // CHECK31:       for.end29:
25629 // CHECK31-NEXT:    [[TMP18:%.*]] = load i32, i32* [[N_ADDR]], align 4
25630 // CHECK31-NEXT:    store i32 [[TMP18]], i32* [[DOTCAPTURE_EXPR_30]], align 4
25631 // CHECK31-NEXT:    store i32 0, i32* [[I31]], align 4
25632 // CHECK31-NEXT:    br label [[FOR_COND32:%.*]]
25633 // CHECK31:       for.cond32:
25634 // CHECK31-NEXT:    [[TMP19:%.*]] = load i32, i32* [[I31]], align 4
25635 // CHECK31-NEXT:    [[CMP33:%.*]] = icmp slt i32 [[TMP19]], 10
25636 // CHECK31-NEXT:    br i1 [[CMP33]], label [[FOR_BODY34:%.*]], label [[FOR_END55:%.*]]
25637 // CHECK31:       for.body34:
25638 // CHECK31-NEXT:    [[TMP20:%.*]] = load i32, i32* [[A]], align 4
25639 // CHECK31-NEXT:    [[ADD35:%.*]] = add nsw i32 [[TMP20]], 1
25640 // CHECK31-NEXT:    store i32 [[ADD35]], i32* [[A]], align 4
25641 // CHECK31-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2
25642 // CHECK31-NEXT:    [[TMP21:%.*]] = load float, float* [[ARRAYIDX]], align 4
25643 // CHECK31-NEXT:    [[CONV36:%.*]] = fpext float [[TMP21]] to double
25644 // CHECK31-NEXT:    [[ADD37:%.*]] = fadd double [[CONV36]], 1.000000e+00
25645 // CHECK31-NEXT:    [[CONV38:%.*]] = fptrunc double [[ADD37]] to float
25646 // CHECK31-NEXT:    store float [[CONV38]], float* [[ARRAYIDX]], align 4
25647 // CHECK31-NEXT:    [[ARRAYIDX39:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3
25648 // CHECK31-NEXT:    [[TMP22:%.*]] = load float, float* [[ARRAYIDX39]], align 4
25649 // CHECK31-NEXT:    [[CONV40:%.*]] = fpext float [[TMP22]] to double
25650 // CHECK31-NEXT:    [[ADD41:%.*]] = fadd double [[CONV40]], 1.000000e+00
25651 // CHECK31-NEXT:    [[CONV42:%.*]] = fptrunc double [[ADD41]] to float
25652 // CHECK31-NEXT:    store float [[CONV42]], float* [[ARRAYIDX39]], align 4
25653 // CHECK31-NEXT:    [[ARRAYIDX43:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1
25654 // CHECK31-NEXT:    [[ARRAYIDX44:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX43]], i32 0, i32 2
25655 // CHECK31-NEXT:    [[TMP23:%.*]] = load double, double* [[ARRAYIDX44]], align 8
25656 // CHECK31-NEXT:    [[ADD45:%.*]] = fadd double [[TMP23]], 1.000000e+00
25657 // CHECK31-NEXT:    store double [[ADD45]], double* [[ARRAYIDX44]], align 8
25658 // CHECK31-NEXT:    [[TMP24:%.*]] = mul nsw i32 1, [[TMP2]]
25659 // CHECK31-NEXT:    [[ARRAYIDX46:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP24]]
25660 // CHECK31-NEXT:    [[ARRAYIDX47:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX46]], i32 3
25661 // CHECK31-NEXT:    [[TMP25:%.*]] = load double, double* [[ARRAYIDX47]], align 8
25662 // CHECK31-NEXT:    [[ADD48:%.*]] = fadd double [[TMP25]], 1.000000e+00
25663 // CHECK31-NEXT:    store double [[ADD48]], double* [[ARRAYIDX47]], align 8
25664 // CHECK31-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0
25665 // CHECK31-NEXT:    [[TMP26:%.*]] = load i64, i64* [[X]], align 4
25666 // CHECK31-NEXT:    [[ADD49:%.*]] = add nsw i64 [[TMP26]], 1
25667 // CHECK31-NEXT:    store i64 [[ADD49]], i64* [[X]], align 4
25668 // CHECK31-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1
25669 // CHECK31-NEXT:    [[TMP27:%.*]] = load i8, i8* [[Y]], align 4
25670 // CHECK31-NEXT:    [[CONV50:%.*]] = sext i8 [[TMP27]] to i32
25671 // CHECK31-NEXT:    [[ADD51:%.*]] = add nsw i32 [[CONV50]], 1
25672 // CHECK31-NEXT:    [[CONV52:%.*]] = trunc i32 [[ADD51]] to i8
25673 // CHECK31-NEXT:    store i8 [[CONV52]], i8* [[Y]], align 4
25674 // CHECK31-NEXT:    br label [[FOR_INC53:%.*]]
25675 // CHECK31:       for.inc53:
25676 // CHECK31-NEXT:    [[TMP28:%.*]] = load i32, i32* [[I31]], align 4
25677 // CHECK31-NEXT:    [[INC54:%.*]] = add nsw i32 [[TMP28]], 1
25678 // CHECK31-NEXT:    store i32 [[INC54]], i32* [[I31]], align 4
25679 // CHECK31-NEXT:    br label [[FOR_COND32]], !llvm.loop [[LOOP8:![0-9]+]]
25680 // CHECK31:       for.end55:
25681 // CHECK31-NEXT:    [[TMP29:%.*]] = load i32, i32* [[A]], align 4
25682 // CHECK31-NEXT:    [[TMP30:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
25683 // CHECK31-NEXT:    call void @llvm.stackrestore(i8* [[TMP30]])
25684 // CHECK31-NEXT:    ret i32 [[TMP29]]
25685 //
25686 //
25687 // CHECK31-LABEL: define {{[^@]+}}@_Z3bari
25688 // CHECK31-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
25689 // CHECK31-NEXT:  entry:
25690 // CHECK31-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
25691 // CHECK31-NEXT:    [[A:%.*]] = alloca i32, align 4
25692 // CHECK31-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4
25693 // CHECK31-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
25694 // CHECK31-NEXT:    store i32 0, i32* [[A]], align 4
25695 // CHECK31-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
25696 // CHECK31-NEXT:    [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]])
25697 // CHECK31-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
25698 // CHECK31-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
25699 // CHECK31-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
25700 // CHECK31-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
25701 // CHECK31-NEXT:    [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]])
25702 // CHECK31-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
25703 // CHECK31-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
25704 // CHECK31-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
25705 // CHECK31-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
25706 // CHECK31-NEXT:    [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]])
25707 // CHECK31-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
25708 // CHECK31-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
25709 // CHECK31-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
25710 // CHECK31-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
25711 // CHECK31-NEXT:    [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]])
25712 // CHECK31-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
25713 // CHECK31-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
25714 // CHECK31-NEXT:    store i32 [[ADD6]], i32* [[A]], align 4
25715 // CHECK31-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
25716 // CHECK31-NEXT:    ret i32 [[TMP8]]
25717 //
25718 //
25719 // CHECK31-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
25720 // CHECK31-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 {
25721 // CHECK31-NEXT:  entry:
25722 // CHECK31-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
25723 // CHECK31-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
25724 // CHECK31-NEXT:    [[B:%.*]] = alloca i32, align 4
25725 // CHECK31-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 4
25726 // CHECK31-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 4
25727 // CHECK31-NEXT:    [[I:%.*]] = alloca i32, align 4
25728 // CHECK31-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
25729 // CHECK31-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
25730 // CHECK31-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
25731 // CHECK31-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
25732 // CHECK31-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
25733 // CHECK31-NEXT:    store i32 [[ADD]], i32* [[B]], align 4
25734 // CHECK31-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
25735 // CHECK31-NEXT:    [[TMP2:%.*]] = call i8* @llvm.stacksave()
25736 // CHECK31-NEXT:    store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4
25737 // CHECK31-NEXT:    [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]
25738 // CHECK31-NEXT:    [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2
25739 // CHECK31-NEXT:    store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
25740 // CHECK31-NEXT:    store i32 0, i32* [[I]], align 4
25741 // CHECK31-NEXT:    br label [[FOR_COND:%.*]]
25742 // CHECK31:       for.cond:
25743 // CHECK31-NEXT:    [[TMP4:%.*]] = load i32, i32* [[I]], align 4
25744 // CHECK31-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP4]], 10
25745 // CHECK31-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
25746 // CHECK31:       for.body:
25747 // CHECK31-NEXT:    [[TMP5:%.*]] = load i32, i32* [[B]], align 4
25748 // CHECK31-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP5]] to double
25749 // CHECK31-NEXT:    [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00
25750 // CHECK31-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
25751 // CHECK31-NEXT:    store double [[ADD2]], double* [[A]], align 4
25752 // CHECK31-NEXT:    [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
25753 // CHECK31-NEXT:    [[TMP6:%.*]] = load double, double* [[A3]], align 4
25754 // CHECK31-NEXT:    [[INC:%.*]] = fadd double [[TMP6]], 1.000000e+00
25755 // CHECK31-NEXT:    store double [[INC]], double* [[A3]], align 4
25756 // CHECK31-NEXT:    [[CONV4:%.*]] = fptosi double [[INC]] to i16
25757 // CHECK31-NEXT:    [[TMP7:%.*]] = mul nsw i32 1, [[TMP1]]
25758 // CHECK31-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP7]]
25759 // CHECK31-NEXT:    [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
25760 // CHECK31-NEXT:    store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2
25761 // CHECK31-NEXT:    br label [[FOR_INC:%.*]]
25762 // CHECK31:       for.inc:
25763 // CHECK31-NEXT:    [[TMP8:%.*]] = load i32, i32* [[I]], align 4
25764 // CHECK31-NEXT:    [[INC6:%.*]] = add nsw i32 [[TMP8]], 1
25765 // CHECK31-NEXT:    store i32 [[INC6]], i32* [[I]], align 4
25766 // CHECK31-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]
25767 // CHECK31:       for.end:
25768 // CHECK31-NEXT:    [[TMP9:%.*]] = mul nsw i32 1, [[TMP1]]
25769 // CHECK31-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP9]]
25770 // CHECK31-NEXT:    [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX7]], i32 1
25771 // CHECK31-NEXT:    [[TMP10:%.*]] = load i16, i16* [[ARRAYIDX8]], align 2
25772 // CHECK31-NEXT:    [[CONV9:%.*]] = sext i16 [[TMP10]] to i32
25773 // CHECK31-NEXT:    [[TMP11:%.*]] = load i32, i32* [[B]], align 4
25774 // CHECK31-NEXT:    [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[TMP11]]
25775 // CHECK31-NEXT:    [[TMP12:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
25776 // CHECK31-NEXT:    call void @llvm.stackrestore(i8* [[TMP12]])
25777 // CHECK31-NEXT:    ret i32 [[ADD10]]
25778 //
25779 //
25780 // CHECK31-LABEL: define {{[^@]+}}@_ZL7fstatici
25781 // CHECK31-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
25782 // CHECK31-NEXT:  entry:
25783 // CHECK31-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
25784 // CHECK31-NEXT:    [[A:%.*]] = alloca i32, align 4
25785 // CHECK31-NEXT:    [[AA:%.*]] = alloca i16, align 2
25786 // CHECK31-NEXT:    [[AAA:%.*]] = alloca i8, align 1
25787 // CHECK31-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
25788 // CHECK31-NEXT:    [[I:%.*]] = alloca i32, align 4
25789 // CHECK31-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
25790 // CHECK31-NEXT:    store i32 0, i32* [[A]], align 4
25791 // CHECK31-NEXT:    store i16 0, i16* [[AA]], align 2
25792 // CHECK31-NEXT:    store i8 0, i8* [[AAA]], align 1
25793 // CHECK31-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
25794 // CHECK31-NEXT:    store i32 [[TMP0]], i32* [[I]], align 4
25795 // CHECK31-NEXT:    br label [[FOR_COND:%.*]]
25796 // CHECK31:       for.cond:
25797 // CHECK31-NEXT:    [[TMP1:%.*]] = load i32, i32* [[I]], align 4
25798 // CHECK31-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
25799 // CHECK31-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP1]], [[TMP2]]
25800 // CHECK31-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
25801 // CHECK31:       for.body:
25802 // CHECK31-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
25803 // CHECK31-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP3]], 1
25804 // CHECK31-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
25805 // CHECK31-NEXT:    [[TMP4:%.*]] = load i16, i16* [[AA]], align 2
25806 // CHECK31-NEXT:    [[CONV:%.*]] = sext i16 [[TMP4]] to i32
25807 // CHECK31-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
25808 // CHECK31-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
25809 // CHECK31-NEXT:    store i16 [[CONV2]], i16* [[AA]], align 2
25810 // CHECK31-NEXT:    [[TMP5:%.*]] = load i8, i8* [[AAA]], align 1
25811 // CHECK31-NEXT:    [[CONV3:%.*]] = sext i8 [[TMP5]] to i32
25812 // CHECK31-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
25813 // CHECK31-NEXT:    [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8
25814 // CHECK31-NEXT:    store i8 [[CONV5]], i8* [[AAA]], align 1
25815 // CHECK31-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2
25816 // CHECK31-NEXT:    [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
25817 // CHECK31-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP6]], 1
25818 // CHECK31-NEXT:    store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4
25819 // CHECK31-NEXT:    br label [[FOR_INC:%.*]]
25820 // CHECK31:       for.inc:
25821 // CHECK31-NEXT:    [[TMP7:%.*]] = load i32, i32* [[I]], align 4
25822 // CHECK31-NEXT:    [[INC:%.*]] = add nsw i32 [[TMP7]], 1
25823 // CHECK31-NEXT:    store i32 [[INC]], i32* [[I]], align 4
25824 // CHECK31-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]
25825 // CHECK31:       for.end:
25826 // CHECK31-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
25827 // CHECK31-NEXT:    ret i32 [[TMP8]]
25828 //
25829 //
25830 // CHECK31-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
25831 // CHECK31-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat {
25832 // CHECK31-NEXT:  entry:
25833 // CHECK31-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
25834 // CHECK31-NEXT:    [[A:%.*]] = alloca i32, align 4
25835 // CHECK31-NEXT:    [[AA:%.*]] = alloca i16, align 2
25836 // CHECK31-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
25837 // CHECK31-NEXT:    [[I:%.*]] = alloca i32, align 4
25838 // CHECK31-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
25839 // CHECK31-NEXT:    store i32 0, i32* [[A]], align 4
25840 // CHECK31-NEXT:    store i16 0, i16* [[AA]], align 2
25841 // CHECK31-NEXT:    store i32 0, i32* [[I]], align 4
25842 // CHECK31-NEXT:    br label [[FOR_COND:%.*]]
25843 // CHECK31:       for.cond:
25844 // CHECK31-NEXT:    [[TMP0:%.*]] = load i32, i32* [[I]], align 4
25845 // CHECK31-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10
25846 // CHECK31-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
25847 // CHECK31:       for.body:
25848 // CHECK31-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
25849 // CHECK31-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
25850 // CHECK31-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
25851 // CHECK31-NEXT:    [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
25852 // CHECK31-NEXT:    [[CONV:%.*]] = sext i16 [[TMP2]] to i32
25853 // CHECK31-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
25854 // CHECK31-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
25855 // CHECK31-NEXT:    store i16 [[CONV2]], i16* [[AA]], align 2
25856 // CHECK31-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2
25857 // CHECK31-NEXT:    [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
25858 // CHECK31-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1
25859 // CHECK31-NEXT:    store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4
25860 // CHECK31-NEXT:    br label [[FOR_INC:%.*]]
25861 // CHECK31:       for.inc:
25862 // CHECK31-NEXT:    [[TMP4:%.*]] = load i32, i32* [[I]], align 4
25863 // CHECK31-NEXT:    [[INC:%.*]] = add nsw i32 [[TMP4]], 1
25864 // CHECK31-NEXT:    store i32 [[INC]], i32* [[I]], align 4
25865 // CHECK31-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]
25866 // CHECK31:       for.end:
25867 // CHECK31-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
25868 // CHECK31-NEXT:    ret i32 [[TMP5]]
25869 //
25870 //
25871 // CHECK32-LABEL: define {{[^@]+}}@_Z3fooi
25872 // CHECK32-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] {
25873 // CHECK32-NEXT:  entry:
25874 // CHECK32-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
25875 // CHECK32-NEXT:    [[A:%.*]] = alloca i32, align 4
25876 // CHECK32-NEXT:    [[AA:%.*]] = alloca i16, align 2
25877 // CHECK32-NEXT:    [[B:%.*]] = alloca [10 x float], align 4
25878 // CHECK32-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 4
25879 // CHECK32-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 4
25880 // CHECK32-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 8
25881 // CHECK32-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i32, align 4
25882 // CHECK32-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4
25883 // CHECK32-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
25884 // CHECK32-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
25885 // CHECK32-NEXT:    [[I:%.*]] = alloca i32, align 4
25886 // CHECK32-NEXT:    [[I3:%.*]] = alloca i32, align 4
25887 // CHECK32-NEXT:    [[I10:%.*]] = alloca i32, align 4
25888 // CHECK32-NEXT:    [[I19:%.*]] = alloca i32, align 4
25889 // CHECK32-NEXT:    [[DOTCAPTURE_EXPR_30:%.*]] = alloca i32, align 4
25890 // CHECK32-NEXT:    [[I31:%.*]] = alloca i32, align 4
25891 // CHECK32-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
25892 // CHECK32-NEXT:    store i32 0, i32* [[A]], align 4
25893 // CHECK32-NEXT:    store i16 0, i16* [[AA]], align 2
25894 // CHECK32-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
25895 // CHECK32-NEXT:    [[TMP1:%.*]] = call i8* @llvm.stacksave()
25896 // CHECK32-NEXT:    store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4
25897 // CHECK32-NEXT:    [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4
25898 // CHECK32-NEXT:    store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4
25899 // CHECK32-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
25900 // CHECK32-NEXT:    [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]]
25901 // CHECK32-NEXT:    [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8
25902 // CHECK32-NEXT:    store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4
25903 // CHECK32-NEXT:    [[TMP4:%.*]] = load i32, i32* [[A]], align 4
25904 // CHECK32-NEXT:    store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4
25905 // CHECK32-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
25906 // CHECK32-NEXT:    store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_2]], align 4
25907 // CHECK32-NEXT:    store i32 0, i32* [[I]], align 4
25908 // CHECK32-NEXT:    br label [[FOR_COND:%.*]]
25909 // CHECK32:       for.cond:
25910 // CHECK32-NEXT:    [[TMP6:%.*]] = load i32, i32* [[I]], align 4
25911 // CHECK32-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP6]], 10
25912 // CHECK32-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
25913 // CHECK32:       for.body:
25914 // CHECK32-NEXT:    br label [[FOR_INC:%.*]]
25915 // CHECK32:       for.inc:
25916 // CHECK32-NEXT:    [[TMP7:%.*]] = load i32, i32* [[I]], align 4
25917 // CHECK32-NEXT:    [[INC:%.*]] = add nsw i32 [[TMP7]], 1
25918 // CHECK32-NEXT:    store i32 [[INC]], i32* [[I]], align 4
25919 // CHECK32-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]
25920 // CHECK32:       for.end:
25921 // CHECK32-NEXT:    store i32 0, i32* [[I3]], align 4
25922 // CHECK32-NEXT:    br label [[FOR_COND4:%.*]]
25923 // CHECK32:       for.cond4:
25924 // CHECK32-NEXT:    [[TMP8:%.*]] = load i32, i32* [[I3]], align 4
25925 // CHECK32-NEXT:    [[CMP5:%.*]] = icmp slt i32 [[TMP8]], 10
25926 // CHECK32-NEXT:    br i1 [[CMP5]], label [[FOR_BODY6:%.*]], label [[FOR_END9:%.*]]
25927 // CHECK32:       for.body6:
25928 // CHECK32-NEXT:    [[TMP9:%.*]] = load i32, i32* [[A]], align 4
25929 // CHECK32-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP9]], 1
25930 // CHECK32-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
25931 // CHECK32-NEXT:    br label [[FOR_INC7:%.*]]
25932 // CHECK32:       for.inc7:
25933 // CHECK32-NEXT:    [[TMP10:%.*]] = load i32, i32* [[I3]], align 4
25934 // CHECK32-NEXT:    [[INC8:%.*]] = add nsw i32 [[TMP10]], 1
25935 // CHECK32-NEXT:    store i32 [[INC8]], i32* [[I3]], align 4
25936 // CHECK32-NEXT:    br label [[FOR_COND4]], !llvm.loop [[LOOP5:![0-9]+]]
25937 // CHECK32:       for.end9:
25938 // CHECK32-NEXT:    store i32 0, i32* [[I10]], align 4
25939 // CHECK32-NEXT:    br label [[FOR_COND11:%.*]]
25940 // CHECK32:       for.cond11:
25941 // CHECK32-NEXT:    [[TMP11:%.*]] = load i32, i32* [[I10]], align 4
25942 // CHECK32-NEXT:    [[CMP12:%.*]] = icmp slt i32 [[TMP11]], 10
25943 // CHECK32-NEXT:    br i1 [[CMP12]], label [[FOR_BODY13:%.*]], label [[FOR_END18:%.*]]
25944 // CHECK32:       for.body13:
25945 // CHECK32-NEXT:    [[TMP12:%.*]] = load i16, i16* [[AA]], align 2
25946 // CHECK32-NEXT:    [[CONV:%.*]] = sext i16 [[TMP12]] to i32
25947 // CHECK32-NEXT:    [[ADD14:%.*]] = add nsw i32 [[CONV]], 1
25948 // CHECK32-NEXT:    [[CONV15:%.*]] = trunc i32 [[ADD14]] to i16
25949 // CHECK32-NEXT:    store i16 [[CONV15]], i16* [[AA]], align 2
25950 // CHECK32-NEXT:    br label [[FOR_INC16:%.*]]
25951 // CHECK32:       for.inc16:
25952 // CHECK32-NEXT:    [[TMP13:%.*]] = load i32, i32* [[I10]], align 4
25953 // CHECK32-NEXT:    [[INC17:%.*]] = add nsw i32 [[TMP13]], 1
25954 // CHECK32-NEXT:    store i32 [[INC17]], i32* [[I10]], align 4
25955 // CHECK32-NEXT:    br label [[FOR_COND11]], !llvm.loop [[LOOP6:![0-9]+]]
25956 // CHECK32:       for.end18:
25957 // CHECK32-NEXT:    store i32 0, i32* [[I19]], align 4
25958 // CHECK32-NEXT:    br label [[FOR_COND20:%.*]]
25959 // CHECK32:       for.cond20:
25960 // CHECK32-NEXT:    [[TMP14:%.*]] = load i32, i32* [[I19]], align 4
25961 // CHECK32-NEXT:    [[CMP21:%.*]] = icmp slt i32 [[TMP14]], 10
25962 // CHECK32-NEXT:    br i1 [[CMP21]], label [[FOR_BODY22:%.*]], label [[FOR_END29:%.*]]
25963 // CHECK32:       for.body22:
25964 // CHECK32-NEXT:    [[TMP15:%.*]] = load i32, i32* [[A]], align 4
25965 // CHECK32-NEXT:    [[ADD23:%.*]] = add nsw i32 [[TMP15]], 1
25966 // CHECK32-NEXT:    store i32 [[ADD23]], i32* [[A]], align 4
25967 // CHECK32-NEXT:    [[TMP16:%.*]] = load i16, i16* [[AA]], align 2
25968 // CHECK32-NEXT:    [[CONV24:%.*]] = sext i16 [[TMP16]] to i32
25969 // CHECK32-NEXT:    [[ADD25:%.*]] = add nsw i32 [[CONV24]], 1
25970 // CHECK32-NEXT:    [[CONV26:%.*]] = trunc i32 [[ADD25]] to i16
25971 // CHECK32-NEXT:    store i16 [[CONV26]], i16* [[AA]], align 2
25972 // CHECK32-NEXT:    br label [[FOR_INC27:%.*]]
25973 // CHECK32:       for.inc27:
25974 // CHECK32-NEXT:    [[TMP17:%.*]] = load i32, i32* [[I19]], align 4
25975 // CHECK32-NEXT:    [[INC28:%.*]] = add nsw i32 [[TMP17]], 1
25976 // CHECK32-NEXT:    store i32 [[INC28]], i32* [[I19]], align 4
25977 // CHECK32-NEXT:    br label [[FOR_COND20]], !llvm.loop [[LOOP7:![0-9]+]]
25978 // CHECK32:       for.end29:
25979 // CHECK32-NEXT:    [[TMP18:%.*]] = load i32, i32* [[N_ADDR]], align 4
25980 // CHECK32-NEXT:    store i32 [[TMP18]], i32* [[DOTCAPTURE_EXPR_30]], align 4
25981 // CHECK32-NEXT:    store i32 0, i32* [[I31]], align 4
25982 // CHECK32-NEXT:    br label [[FOR_COND32:%.*]]
25983 // CHECK32:       for.cond32:
25984 // CHECK32-NEXT:    [[TMP19:%.*]] = load i32, i32* [[I31]], align 4
25985 // CHECK32-NEXT:    [[CMP33:%.*]] = icmp slt i32 [[TMP19]], 10
25986 // CHECK32-NEXT:    br i1 [[CMP33]], label [[FOR_BODY34:%.*]], label [[FOR_END55:%.*]]
25987 // CHECK32:       for.body34:
25988 // CHECK32-NEXT:    [[TMP20:%.*]] = load i32, i32* [[A]], align 4
25989 // CHECK32-NEXT:    [[ADD35:%.*]] = add nsw i32 [[TMP20]], 1
25990 // CHECK32-NEXT:    store i32 [[ADD35]], i32* [[A]], align 4
25991 // CHECK32-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2
25992 // CHECK32-NEXT:    [[TMP21:%.*]] = load float, float* [[ARRAYIDX]], align 4
25993 // CHECK32-NEXT:    [[CONV36:%.*]] = fpext float [[TMP21]] to double
25994 // CHECK32-NEXT:    [[ADD37:%.*]] = fadd double [[CONV36]], 1.000000e+00
25995 // CHECK32-NEXT:    [[CONV38:%.*]] = fptrunc double [[ADD37]] to float
25996 // CHECK32-NEXT:    store float [[CONV38]], float* [[ARRAYIDX]], align 4
25997 // CHECK32-NEXT:    [[ARRAYIDX39:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3
25998 // CHECK32-NEXT:    [[TMP22:%.*]] = load float, float* [[ARRAYIDX39]], align 4
25999 // CHECK32-NEXT:    [[CONV40:%.*]] = fpext float [[TMP22]] to double
26000 // CHECK32-NEXT:    [[ADD41:%.*]] = fadd double [[CONV40]], 1.000000e+00
26001 // CHECK32-NEXT:    [[CONV42:%.*]] = fptrunc double [[ADD41]] to float
26002 // CHECK32-NEXT:    store float [[CONV42]], float* [[ARRAYIDX39]], align 4
26003 // CHECK32-NEXT:    [[ARRAYIDX43:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1
26004 // CHECK32-NEXT:    [[ARRAYIDX44:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX43]], i32 0, i32 2
26005 // CHECK32-NEXT:    [[TMP23:%.*]] = load double, double* [[ARRAYIDX44]], align 8
26006 // CHECK32-NEXT:    [[ADD45:%.*]] = fadd double [[TMP23]], 1.000000e+00
26007 // CHECK32-NEXT:    store double [[ADD45]], double* [[ARRAYIDX44]], align 8
26008 // CHECK32-NEXT:    [[TMP24:%.*]] = mul nsw i32 1, [[TMP2]]
26009 // CHECK32-NEXT:    [[ARRAYIDX46:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP24]]
26010 // CHECK32-NEXT:    [[ARRAYIDX47:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX46]], i32 3
26011 // CHECK32-NEXT:    [[TMP25:%.*]] = load double, double* [[ARRAYIDX47]], align 8
26012 // CHECK32-NEXT:    [[ADD48:%.*]] = fadd double [[TMP25]], 1.000000e+00
26013 // CHECK32-NEXT:    store double [[ADD48]], double* [[ARRAYIDX47]], align 8
26014 // CHECK32-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0
26015 // CHECK32-NEXT:    [[TMP26:%.*]] = load i64, i64* [[X]], align 4
26016 // CHECK32-NEXT:    [[ADD49:%.*]] = add nsw i64 [[TMP26]], 1
26017 // CHECK32-NEXT:    store i64 [[ADD49]], i64* [[X]], align 4
26018 // CHECK32-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1
26019 // CHECK32-NEXT:    [[TMP27:%.*]] = load i8, i8* [[Y]], align 4
26020 // CHECK32-NEXT:    [[CONV50:%.*]] = sext i8 [[TMP27]] to i32
26021 // CHECK32-NEXT:    [[ADD51:%.*]] = add nsw i32 [[CONV50]], 1
26022 // CHECK32-NEXT:    [[CONV52:%.*]] = trunc i32 [[ADD51]] to i8
26023 // CHECK32-NEXT:    store i8 [[CONV52]], i8* [[Y]], align 4
26024 // CHECK32-NEXT:    br label [[FOR_INC53:%.*]]
26025 // CHECK32:       for.inc53:
26026 // CHECK32-NEXT:    [[TMP28:%.*]] = load i32, i32* [[I31]], align 4
26027 // CHECK32-NEXT:    [[INC54:%.*]] = add nsw i32 [[TMP28]], 1
26028 // CHECK32-NEXT:    store i32 [[INC54]], i32* [[I31]], align 4
26029 // CHECK32-NEXT:    br label [[FOR_COND32]], !llvm.loop [[LOOP8:![0-9]+]]
26030 // CHECK32:       for.end55:
26031 // CHECK32-NEXT:    [[TMP29:%.*]] = load i32, i32* [[A]], align 4
26032 // CHECK32-NEXT:    [[TMP30:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
26033 // CHECK32-NEXT:    call void @llvm.stackrestore(i8* [[TMP30]])
26034 // CHECK32-NEXT:    ret i32 [[TMP29]]
26035 //
26036 //
26037 // CHECK32-LABEL: define {{[^@]+}}@_Z3bari
26038 // CHECK32-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
26039 // CHECK32-NEXT:  entry:
26040 // CHECK32-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
26041 // CHECK32-NEXT:    [[A:%.*]] = alloca i32, align 4
26042 // CHECK32-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4
26043 // CHECK32-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
26044 // CHECK32-NEXT:    store i32 0, i32* [[A]], align 4
26045 // CHECK32-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
26046 // CHECK32-NEXT:    [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]])
26047 // CHECK32-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
26048 // CHECK32-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
26049 // CHECK32-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
26050 // CHECK32-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
26051 // CHECK32-NEXT:    [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]])
26052 // CHECK32-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
26053 // CHECK32-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
26054 // CHECK32-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
26055 // CHECK32-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
26056 // CHECK32-NEXT:    [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]])
26057 // CHECK32-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
26058 // CHECK32-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
26059 // CHECK32-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
26060 // CHECK32-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
26061 // CHECK32-NEXT:    [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]])
26062 // CHECK32-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
26063 // CHECK32-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
26064 // CHECK32-NEXT:    store i32 [[ADD6]], i32* [[A]], align 4
26065 // CHECK32-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
26066 // CHECK32-NEXT:    ret i32 [[TMP8]]
26067 //
26068 //
26069 // CHECK32-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
26070 // CHECK32-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 {
26071 // CHECK32-NEXT:  entry:
26072 // CHECK32-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
26073 // CHECK32-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
26074 // CHECK32-NEXT:    [[B:%.*]] = alloca i32, align 4
26075 // CHECK32-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 4
26076 // CHECK32-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 4
26077 // CHECK32-NEXT:    [[I:%.*]] = alloca i32, align 4
26078 // CHECK32-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
26079 // CHECK32-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
26080 // CHECK32-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
26081 // CHECK32-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
26082 // CHECK32-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
26083 // CHECK32-NEXT:    store i32 [[ADD]], i32* [[B]], align 4
26084 // CHECK32-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
26085 // CHECK32-NEXT:    [[TMP2:%.*]] = call i8* @llvm.stacksave()
26086 // CHECK32-NEXT:    store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4
26087 // CHECK32-NEXT:    [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]
26088 // CHECK32-NEXT:    [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2
26089 // CHECK32-NEXT:    store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
26090 // CHECK32-NEXT:    store i32 0, i32* [[I]], align 4
26091 // CHECK32-NEXT:    br label [[FOR_COND:%.*]]
26092 // CHECK32:       for.cond:
26093 // CHECK32-NEXT:    [[TMP4:%.*]] = load i32, i32* [[I]], align 4
26094 // CHECK32-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP4]], 10
26095 // CHECK32-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
26096 // CHECK32:       for.body:
26097 // CHECK32-NEXT:    [[TMP5:%.*]] = load i32, i32* [[B]], align 4
26098 // CHECK32-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP5]] to double
26099 // CHECK32-NEXT:    [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00
26100 // CHECK32-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
26101 // CHECK32-NEXT:    store double [[ADD2]], double* [[A]], align 4
26102 // CHECK32-NEXT:    [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
26103 // CHECK32-NEXT:    [[TMP6:%.*]] = load double, double* [[A3]], align 4
26104 // CHECK32-NEXT:    [[INC:%.*]] = fadd double [[TMP6]], 1.000000e+00
26105 // CHECK32-NEXT:    store double [[INC]], double* [[A3]], align 4
26106 // CHECK32-NEXT:    [[CONV4:%.*]] = fptosi double [[INC]] to i16
26107 // CHECK32-NEXT:    [[TMP7:%.*]] = mul nsw i32 1, [[TMP1]]
26108 // CHECK32-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP7]]
26109 // CHECK32-NEXT:    [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
26110 // CHECK32-NEXT:    store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2
26111 // CHECK32-NEXT:    br label [[FOR_INC:%.*]]
26112 // CHECK32:       for.inc:
26113 // CHECK32-NEXT:    [[TMP8:%.*]] = load i32, i32* [[I]], align 4
26114 // CHECK32-NEXT:    [[INC6:%.*]] = add nsw i32 [[TMP8]], 1
26115 // CHECK32-NEXT:    store i32 [[INC6]], i32* [[I]], align 4
26116 // CHECK32-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]
26117 // CHECK32:       for.end:
26118 // CHECK32-NEXT:    [[TMP9:%.*]] = mul nsw i32 1, [[TMP1]]
26119 // CHECK32-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP9]]
26120 // CHECK32-NEXT:    [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX7]], i32 1
26121 // CHECK32-NEXT:    [[TMP10:%.*]] = load i16, i16* [[ARRAYIDX8]], align 2
26122 // CHECK32-NEXT:    [[CONV9:%.*]] = sext i16 [[TMP10]] to i32
26123 // CHECK32-NEXT:    [[TMP11:%.*]] = load i32, i32* [[B]], align 4
26124 // CHECK32-NEXT:    [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[TMP11]]
26125 // CHECK32-NEXT:    [[TMP12:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
26126 // CHECK32-NEXT:    call void @llvm.stackrestore(i8* [[TMP12]])
26127 // CHECK32-NEXT:    ret i32 [[ADD10]]
26128 //
26129 //
26130 // CHECK32-LABEL: define {{[^@]+}}@_ZL7fstatici
26131 // CHECK32-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
26132 // CHECK32-NEXT:  entry:
26133 // CHECK32-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
26134 // CHECK32-NEXT:    [[A:%.*]] = alloca i32, align 4
26135 // CHECK32-NEXT:    [[AA:%.*]] = alloca i16, align 2
26136 // CHECK32-NEXT:    [[AAA:%.*]] = alloca i8, align 1
26137 // CHECK32-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
26138 // CHECK32-NEXT:    [[I:%.*]] = alloca i32, align 4
26139 // CHECK32-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
26140 // CHECK32-NEXT:    store i32 0, i32* [[A]], align 4
26141 // CHECK32-NEXT:    store i16 0, i16* [[AA]], align 2
26142 // CHECK32-NEXT:    store i8 0, i8* [[AAA]], align 1
26143 // CHECK32-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
26144 // CHECK32-NEXT:    store i32 [[TMP0]], i32* [[I]], align 4
26145 // CHECK32-NEXT:    br label [[FOR_COND:%.*]]
26146 // CHECK32:       for.cond:
26147 // CHECK32-NEXT:    [[TMP1:%.*]] = load i32, i32* [[I]], align 4
26148 // CHECK32-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
26149 // CHECK32-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP1]], [[TMP2]]
26150 // CHECK32-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
26151 // CHECK32:       for.body:
26152 // CHECK32-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
26153 // CHECK32-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP3]], 1
26154 // CHECK32-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
26155 // CHECK32-NEXT:    [[TMP4:%.*]] = load i16, i16* [[AA]], align 2
26156 // CHECK32-NEXT:    [[CONV:%.*]] = sext i16 [[TMP4]] to i32
26157 // CHECK32-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
26158 // CHECK32-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
26159 // CHECK32-NEXT:    store i16 [[CONV2]], i16* [[AA]], align 2
26160 // CHECK32-NEXT:    [[TMP5:%.*]] = load i8, i8* [[AAA]], align 1
26161 // CHECK32-NEXT:    [[CONV3:%.*]] = sext i8 [[TMP5]] to i32
26162 // CHECK32-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
26163 // CHECK32-NEXT:    [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8
26164 // CHECK32-NEXT:    store i8 [[CONV5]], i8* [[AAA]], align 1
26165 // CHECK32-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2
26166 // CHECK32-NEXT:    [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
26167 // CHECK32-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP6]], 1
26168 // CHECK32-NEXT:    store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4
26169 // CHECK32-NEXT:    br label [[FOR_INC:%.*]]
26170 // CHECK32:       for.inc:
26171 // CHECK32-NEXT:    [[TMP7:%.*]] = load i32, i32* [[I]], align 4
26172 // CHECK32-NEXT:    [[INC:%.*]] = add nsw i32 [[TMP7]], 1
26173 // CHECK32-NEXT:    store i32 [[INC]], i32* [[I]], align 4
26174 // CHECK32-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]
26175 // CHECK32:       for.end:
26176 // CHECK32-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
26177 // CHECK32-NEXT:    ret i32 [[TMP8]]
26178 //
26179 //
26180 // CHECK32-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
26181 // CHECK32-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat {
26182 // CHECK32-NEXT:  entry:
26183 // CHECK32-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
26184 // CHECK32-NEXT:    [[A:%.*]] = alloca i32, align 4
26185 // CHECK32-NEXT:    [[AA:%.*]] = alloca i16, align 2
26186 // CHECK32-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
26187 // CHECK32-NEXT:    [[I:%.*]] = alloca i32, align 4
26188 // CHECK32-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
26189 // CHECK32-NEXT:    store i32 0, i32* [[A]], align 4
26190 // CHECK32-NEXT:    store i16 0, i16* [[AA]], align 2
26191 // CHECK32-NEXT:    store i32 0, i32* [[I]], align 4
26192 // CHECK32-NEXT:    br label [[FOR_COND:%.*]]
26193 // CHECK32:       for.cond:
26194 // CHECK32-NEXT:    [[TMP0:%.*]] = load i32, i32* [[I]], align 4
26195 // CHECK32-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10
26196 // CHECK32-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
26197 // CHECK32:       for.body:
26198 // CHECK32-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
26199 // CHECK32-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
26200 // CHECK32-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
26201 // CHECK32-NEXT:    [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
26202 // CHECK32-NEXT:    [[CONV:%.*]] = sext i16 [[TMP2]] to i32
26203 // CHECK32-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
26204 // CHECK32-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
26205 // CHECK32-NEXT:    store i16 [[CONV2]], i16* [[AA]], align 2
26206 // CHECK32-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2
26207 // CHECK32-NEXT:    [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
26208 // CHECK32-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1
26209 // CHECK32-NEXT:    store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4
26210 // CHECK32-NEXT:    br label [[FOR_INC:%.*]]
26211 // CHECK32:       for.inc:
26212 // CHECK32-NEXT:    [[TMP4:%.*]] = load i32, i32* [[I]], align 4
26213 // CHECK32-NEXT:    [[INC:%.*]] = add nsw i32 [[TMP4]], 1
26214 // CHECK32-NEXT:    store i32 [[INC]], i32* [[I]], align 4
26215 // CHECK32-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]
26216 // CHECK32:       for.end:
26217 // CHECK32-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
26218 // CHECK32-NEXT:    ret i32 [[TMP5]]
26219 //
26220