1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ 2 // Test host codegen. 3 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1 4 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 5 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1 6 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK3 7 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 8 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK3 9 10 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 11 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 12 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 13 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 14 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 15 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 16 17 // Test target codegen - host bc file has to be created first. 18 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc 19 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9 20 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s 21 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9 22 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc 23 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11 24 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s 25 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11 26 27 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc 28 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 29 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s 30 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 31 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc 32 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 33 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s 34 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 35 36 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1 37 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 38 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1 39 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK3 40 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 41 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK3 42 43 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 44 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 45 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 46 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 47 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 48 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 49 50 // Test target codegen - host bc file has to be created first. 51 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc 52 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9 53 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s 54 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9 55 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc 56 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11 57 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s 58 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11 59 60 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc 61 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 62 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s 63 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 64 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc 65 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 66 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s 67 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 68 69 // expected-no-diagnostics 70 #ifndef HEADER 71 #define HEADER 72 73 74 75 76 // We have 8 target regions, but only 6 that actually will generate offloading 77 // code and have mapped arguments, and only 4 have all-constant map sizes. 78 79 80 81 // Check target registration is registered as a Ctor. 82 83 84 template<typename tx, typename ty> 85 struct TT{ 86 tx X; 87 ty Y; 88 }; 89 90 int global; 91 92 int foo(int n) { 93 int a = 0; 94 short aa = 0; 95 float b[10]; 96 float bn[n]; 97 double c[5][10]; 98 double cn[5][n]; 99 TT<long long, char> d; 100 101 #pragma omp target teams num_teams(a) thread_limit(a) firstprivate(aa) nowait 102 { 103 } 104 105 #pragma omp target teams if(target: 0) 106 { 107 a += 1; 108 } 109 110 111 #pragma omp target teams if(target: 1) 112 { 113 aa += 1; 114 } 115 116 117 118 #pragma omp target teams if(target: n>10) 119 { 120 a += 1; 121 aa += 1; 122 } 123 124 // We capture 3 VLA sizes in this target region 125 126 127 128 129 130 // The names below are not necessarily consistent with the names used for the 131 // addresses above as some are repeated. 132 133 134 135 136 137 138 139 140 141 142 #pragma omp target teams if(target: n>20) 143 { 144 a += 1; 145 b[2] += 1.0; 146 bn[3] += 1.0; 147 c[1][2] += 1.0; 148 cn[1][3] += 1.0; 149 d.X += 1; 150 d.Y += 1; 151 } 152 153 const int nn = 0; 154 #pragma omp target teams shared(nn) 155 #pragma omp parallel firstprivate(nn) 156 (void)nn; 157 #pragma omp target teams firstprivate(nn) 158 #pragma omp parallel shared(nn) 159 (void)nn; 160 return a; 161 } 162 163 // Check that the offloading functions are emitted and that the arguments are 164 // correct and loaded correctly for the target regions in foo(). 165 166 167 168 // Create stack storage and store argument in there. 169 170 // Create stack storage and store argument in there. 171 172 // Create stack storage and store argument in there. 173 174 // Create local storage for each capture. 175 176 177 178 // To reduce complexity, we're only going as far as validating the signature of the outlined parallel function. 179 180 181 void bazzzz(int n, int f[n]) { 182 #pragma omp target teams private(f) 183 ; 184 } 185 186 template<typename tx> 187 tx ftemplate(int n) { 188 tx a = 0; 189 short aa = 0; 190 tx b[10]; 191 192 #pragma omp target teams if(target: n>40) 193 { 194 a += 1; 195 aa += 1; 196 b[2] += 1; 197 } 198 199 return a; 200 } 201 202 static 203 int fstatic(int n) { 204 int a = 0; 205 short aa = 0; 206 char aaa = 0; 207 int b[10]; 208 209 #pragma omp target teams if(target: n>50) 210 { 211 a += 1; 212 aa += 1; 213 aaa += 1; 214 b[2] += 1; 215 } 216 217 return a; 218 } 219 220 struct S1 { 221 double a; 222 223 int r1(int n){ 224 int b = n+1; 225 short int c[2][n]; 226 227 #pragma omp target teams if(target: n>60) 228 { 229 this->a = (double)b + 1.5; 230 c[1][1] = ++a; 231 } 232 233 return c[1][1] + (int)b; 234 } 235 }; 236 237 int bar(int n){ 238 int a = 0; 239 240 a += foo(n); 241 242 S1 S; 243 a += S.r1(n); 244 245 a += fstatic(n); 246 247 a += ftemplate<int>(n); 248 249 return a; 250 } 251 252 253 254 // We capture 2 VLA sizes in this target region 255 256 257 // The names below are not necessarily consistent with the names used for the 258 // addresses above as some are repeated. 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 // Check that the offloading functions are emitted and that the arguments are 280 // correct and loaded correctly for the target regions of the callees of bar(). 281 282 // Create local storage for each capture. 283 // Store captures in the context. 284 285 286 // To reduce complexity, we're only going as far as validating the signature of the outlined parallel function. 287 288 289 // Create local storage for each capture. 290 // Store captures in the context. 291 292 293 294 295 // To reduce complexity, we're only going as far as validating the signature of the outlined parallel function. 296 297 // Create local storage for each capture. 298 // Store captures in the context. 299 300 301 302 // To reduce complexity, we're only going as far as validating the signature of the outlined parallel function. 303 304 #endif 305 // CHECK1-LABEL: define {{[^@]+}}@_Z3fooi 306 // CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { 307 // CHECK1-NEXT: entry: 308 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 309 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4 310 // CHECK1-NEXT: [[AA:%.*]] = alloca i16, align 2 311 // CHECK1-NEXT: [[B:%.*]] = alloca [10 x float], align 4 312 // CHECK1-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 313 // CHECK1-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 314 // CHECK1-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 315 // CHECK1-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 316 // CHECK1-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 317 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 318 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 319 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 320 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 321 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED4:%.*]] = alloca i64, align 8 322 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 323 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 324 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 325 // CHECK1-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4 326 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 327 // CHECK1-NEXT: [[AA_CASTED7:%.*]] = alloca i64, align 8 328 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS9:%.*]] = alloca [1 x i8*], align 8 329 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS10:%.*]] = alloca [1 x i8*], align 8 330 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS11:%.*]] = alloca [1 x i8*], align 8 331 // CHECK1-NEXT: [[A_CASTED12:%.*]] = alloca i64, align 8 332 // CHECK1-NEXT: [[AA_CASTED14:%.*]] = alloca i64, align 8 333 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS16:%.*]] = alloca [2 x i8*], align 8 334 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS17:%.*]] = alloca [2 x i8*], align 8 335 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS18:%.*]] = alloca [2 x i8*], align 8 336 // CHECK1-NEXT: [[A_CASTED21:%.*]] = alloca i64, align 8 337 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS25:%.*]] = alloca [9 x i8*], align 8 338 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS26:%.*]] = alloca [9 x i8*], align 8 339 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS27:%.*]] = alloca [9 x i8*], align 8 340 // CHECK1-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [9 x i64], align 8 341 // CHECK1-NEXT: [[NN:%.*]] = alloca i32, align 4 342 // CHECK1-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 343 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS33:%.*]] = alloca [1 x i8*], align 8 344 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS34:%.*]] = alloca [1 x i8*], align 8 345 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS35:%.*]] = alloca [1 x i8*], align 8 346 // CHECK1-NEXT: [[NN_CASTED38:%.*]] = alloca i64, align 8 347 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS40:%.*]] = alloca [1 x i8*], align 8 348 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS41:%.*]] = alloca [1 x i8*], align 8 349 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS42:%.*]] = alloca [1 x i8*], align 8 350 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) 351 // CHECK1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 352 // CHECK1-NEXT: store i32 0, i32* [[A]], align 4 353 // CHECK1-NEXT: store i16 0, i16* [[AA]], align 2 354 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 355 // CHECK1-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 356 // CHECK1-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() 357 // CHECK1-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 358 // CHECK1-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP2]], align 4 359 // CHECK1-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 360 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 361 // CHECK1-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64 362 // CHECK1-NEXT: [[TMP6:%.*]] = mul nuw i64 5, [[TMP5]] 363 // CHECK1-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP6]], align 8 364 // CHECK1-NEXT: store i64 [[TMP5]], i64* [[__VLA_EXPR1]], align 8 365 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 366 // CHECK1-NEXT: store i32 [[TMP7]], i32* [[DOTCAPTURE_EXPR_]], align 4 367 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 368 // CHECK1-NEXT: store i32 [[TMP8]], i32* [[DOTCAPTURE_EXPR_2]], align 4 369 // CHECK1-NEXT: [[TMP9:%.*]] = load i16, i16* [[AA]], align 2 370 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 371 // CHECK1-NEXT: store i16 [[TMP9]], i16* [[CONV]], align 2 372 // CHECK1-NEXT: [[TMP10:%.*]] = load i64, i64* [[AA_CASTED]], align 8 373 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 374 // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* 375 // CHECK1-NEXT: store i32 [[TMP11]], i32* [[CONV3]], align 4 376 // CHECK1-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 377 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 378 // CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED4]] to i32* 379 // CHECK1-NEXT: store i32 [[TMP13]], i32* [[CONV5]], align 4 380 // CHECK1-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED4]], align 8 381 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 382 // CHECK1-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i64* 383 // CHECK1-NEXT: store i64 [[TMP10]], i64* [[TMP16]], align 8 384 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 385 // CHECK1-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64* 386 // CHECK1-NEXT: store i64 [[TMP10]], i64* [[TMP18]], align 8 387 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 388 // CHECK1-NEXT: store i8* null, i8** [[TMP19]], align 8 389 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 390 // CHECK1-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i64* 391 // CHECK1-NEXT: store i64 [[TMP12]], i64* [[TMP21]], align 8 392 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 393 // CHECK1-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i64* 394 // CHECK1-NEXT: store i64 [[TMP12]], i64* [[TMP23]], align 8 395 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 396 // CHECK1-NEXT: store i8* null, i8** [[TMP24]], align 8 397 // CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 398 // CHECK1-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i64* 399 // CHECK1-NEXT: store i64 [[TMP14]], i64* [[TMP26]], align 8 400 // CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 401 // CHECK1-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i64* 402 // CHECK1-NEXT: store i64 [[TMP14]], i64* [[TMP28]], align 8 403 // CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 404 // CHECK1-NEXT: store i8* null, i8** [[TMP29]], align 8 405 // CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 406 // CHECK1-NEXT: [[TMP31:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 407 // CHECK1-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 0 408 // CHECK1-NEXT: [[TMP33:%.*]] = load i16, i16* [[AA]], align 2 409 // CHECK1-NEXT: store i16 [[TMP33]], i16* [[TMP32]], align 4 410 // CHECK1-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 1 411 // CHECK1-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 412 // CHECK1-NEXT: store i32 [[TMP35]], i32* [[TMP34]], align 4 413 // CHECK1-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 2 414 // CHECK1-NEXT: [[TMP37:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 415 // CHECK1-NEXT: store i32 [[TMP37]], i32* [[TMP36]], align 4 416 // CHECK1-NEXT: [[TMP38:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i64 120, i64 12, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1) 417 // CHECK1-NEXT: [[TMP39:%.*]] = bitcast i8* [[TMP38]] to %struct.kmp_task_t_with_privates* 418 // CHECK1-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP39]], i32 0, i32 0 419 // CHECK1-NEXT: [[TMP41:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP40]], i32 0, i32 0 420 // CHECK1-NEXT: [[TMP42:%.*]] = load i8*, i8** [[TMP41]], align 8 421 // CHECK1-NEXT: [[TMP43:%.*]] = bitcast %struct.anon* [[AGG_CAPTURED]] to i8* 422 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP42]], i8* align 4 [[TMP43]], i64 12, i1 false) 423 // CHECK1-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP39]], i32 0, i32 1 424 // CHECK1-NEXT: [[TMP45:%.*]] = bitcast i8* [[TMP42]] to %struct.anon* 425 // CHECK1-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 0 426 // CHECK1-NEXT: [[TMP47:%.*]] = bitcast [3 x i8*]* [[TMP46]] to i8* 427 // CHECK1-NEXT: [[TMP48:%.*]] = bitcast i8** [[TMP30]] to i8* 428 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP47]], i8* align 8 [[TMP48]], i64 24, i1 false) 429 // CHECK1-NEXT: [[TMP49:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 1 430 // CHECK1-NEXT: [[TMP50:%.*]] = bitcast [3 x i8*]* [[TMP49]] to i8* 431 // CHECK1-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP31]] to i8* 432 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP50]], i8* align 8 [[TMP51]], i64 24, i1 false) 433 // CHECK1-NEXT: [[TMP52:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 2 434 // CHECK1-NEXT: [[TMP53:%.*]] = bitcast [3 x i64]* [[TMP52]] to i8* 435 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP53]], i8* align 8 bitcast ([3 x i64]* @.offload_sizes to i8*), i64 24, i1 false) 436 // CHECK1-NEXT: [[TMP54:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 3 437 // CHECK1-NEXT: [[TMP55:%.*]] = load i16, i16* [[AA]], align 2 438 // CHECK1-NEXT: store i16 [[TMP55]], i16* [[TMP54]], align 8 439 // CHECK1-NEXT: [[TMP56:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP38]]) 440 // CHECK1-NEXT: [[TMP57:%.*]] = load i32, i32* [[A]], align 4 441 // CHECK1-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32* 442 // CHECK1-NEXT: store i32 [[TMP57]], i32* [[CONV6]], align 4 443 // CHECK1-NEXT: [[TMP58:%.*]] = load i64, i64* [[A_CASTED]], align 8 444 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l105(i64 [[TMP58]]) #[[ATTR3:[0-9]+]] 445 // CHECK1-NEXT: [[TMP59:%.*]] = load i16, i16* [[AA]], align 2 446 // CHECK1-NEXT: [[CONV8:%.*]] = bitcast i64* [[AA_CASTED7]] to i16* 447 // CHECK1-NEXT: store i16 [[TMP59]], i16* [[CONV8]], align 2 448 // CHECK1-NEXT: [[TMP60:%.*]] = load i64, i64* [[AA_CASTED7]], align 8 449 // CHECK1-NEXT: [[TMP61:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS9]], i32 0, i32 0 450 // CHECK1-NEXT: [[TMP62:%.*]] = bitcast i8** [[TMP61]] to i64* 451 // CHECK1-NEXT: store i64 [[TMP60]], i64* [[TMP62]], align 8 452 // CHECK1-NEXT: [[TMP63:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS10]], i32 0, i32 0 453 // CHECK1-NEXT: [[TMP64:%.*]] = bitcast i8** [[TMP63]] to i64* 454 // CHECK1-NEXT: store i64 [[TMP60]], i64* [[TMP64]], align 8 455 // CHECK1-NEXT: [[TMP65:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS11]], i64 0, i64 0 456 // CHECK1-NEXT: store i8* null, i8** [[TMP65]], align 8 457 // CHECK1-NEXT: [[TMP66:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS9]], i32 0, i32 0 458 // CHECK1-NEXT: [[TMP67:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS10]], i32 0, i32 0 459 // CHECK1-NEXT: [[TMP68:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.region_id, i32 1, i8** [[TMP66]], i8** [[TMP67]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.4, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.5, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 460 // CHECK1-NEXT: [[TMP69:%.*]] = icmp ne i32 [[TMP68]], 0 461 // CHECK1-NEXT: br i1 [[TMP69]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 462 // CHECK1: omp_offload.failed: 463 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111(i64 [[TMP60]]) #[[ATTR3]] 464 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 465 // CHECK1: omp_offload.cont: 466 // CHECK1-NEXT: [[TMP70:%.*]] = load i32, i32* [[A]], align 4 467 // CHECK1-NEXT: [[CONV13:%.*]] = bitcast i64* [[A_CASTED12]] to i32* 468 // CHECK1-NEXT: store i32 [[TMP70]], i32* [[CONV13]], align 4 469 // CHECK1-NEXT: [[TMP71:%.*]] = load i64, i64* [[A_CASTED12]], align 8 470 // CHECK1-NEXT: [[TMP72:%.*]] = load i16, i16* [[AA]], align 2 471 // CHECK1-NEXT: [[CONV15:%.*]] = bitcast i64* [[AA_CASTED14]] to i16* 472 // CHECK1-NEXT: store i16 [[TMP72]], i16* [[CONV15]], align 2 473 // CHECK1-NEXT: [[TMP73:%.*]] = load i64, i64* [[AA_CASTED14]], align 8 474 // CHECK1-NEXT: [[TMP74:%.*]] = load i32, i32* [[N_ADDR]], align 4 475 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP74]], 10 476 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 477 // CHECK1: omp_if.then: 478 // CHECK1-NEXT: [[TMP75:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 0 479 // CHECK1-NEXT: [[TMP76:%.*]] = bitcast i8** [[TMP75]] to i64* 480 // CHECK1-NEXT: store i64 [[TMP71]], i64* [[TMP76]], align 8 481 // CHECK1-NEXT: [[TMP77:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 0 482 // CHECK1-NEXT: [[TMP78:%.*]] = bitcast i8** [[TMP77]] to i64* 483 // CHECK1-NEXT: store i64 [[TMP71]], i64* [[TMP78]], align 8 484 // CHECK1-NEXT: [[TMP79:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 0 485 // CHECK1-NEXT: store i8* null, i8** [[TMP79]], align 8 486 // CHECK1-NEXT: [[TMP80:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 1 487 // CHECK1-NEXT: [[TMP81:%.*]] = bitcast i8** [[TMP80]] to i64* 488 // CHECK1-NEXT: store i64 [[TMP73]], i64* [[TMP81]], align 8 489 // CHECK1-NEXT: [[TMP82:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 1 490 // CHECK1-NEXT: [[TMP83:%.*]] = bitcast i8** [[TMP82]] to i64* 491 // CHECK1-NEXT: store i64 [[TMP73]], i64* [[TMP83]], align 8 492 // CHECK1-NEXT: [[TMP84:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 1 493 // CHECK1-NEXT: store i8* null, i8** [[TMP84]], align 8 494 // CHECK1-NEXT: [[TMP85:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 0 495 // CHECK1-NEXT: [[TMP86:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 0 496 // CHECK1-NEXT: [[TMP87:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.region_id, i32 2, i8** [[TMP85]], i8** [[TMP86]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.7, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.8, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 497 // CHECK1-NEXT: [[TMP88:%.*]] = icmp ne i32 [[TMP87]], 0 498 // CHECK1-NEXT: br i1 [[TMP88]], label [[OMP_OFFLOAD_FAILED19:%.*]], label [[OMP_OFFLOAD_CONT20:%.*]] 499 // CHECK1: omp_offload.failed19: 500 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i64 [[TMP71]], i64 [[TMP73]]) #[[ATTR3]] 501 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT20]] 502 // CHECK1: omp_offload.cont20: 503 // CHECK1-NEXT: br label [[OMP_IF_END:%.*]] 504 // CHECK1: omp_if.else: 505 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i64 [[TMP71]], i64 [[TMP73]]) #[[ATTR3]] 506 // CHECK1-NEXT: br label [[OMP_IF_END]] 507 // CHECK1: omp_if.end: 508 // CHECK1-NEXT: [[TMP89:%.*]] = load i32, i32* [[A]], align 4 509 // CHECK1-NEXT: [[CONV22:%.*]] = bitcast i64* [[A_CASTED21]] to i32* 510 // CHECK1-NEXT: store i32 [[TMP89]], i32* [[CONV22]], align 4 511 // CHECK1-NEXT: [[TMP90:%.*]] = load i64, i64* [[A_CASTED21]], align 8 512 // CHECK1-NEXT: [[TMP91:%.*]] = load i32, i32* [[N_ADDR]], align 4 513 // CHECK1-NEXT: [[CMP23:%.*]] = icmp sgt i32 [[TMP91]], 20 514 // CHECK1-NEXT: br i1 [[CMP23]], label [[OMP_IF_THEN24:%.*]], label [[OMP_IF_ELSE30:%.*]] 515 // CHECK1: omp_if.then24: 516 // CHECK1-NEXT: [[TMP92:%.*]] = mul nuw i64 [[TMP2]], 4 517 // CHECK1-NEXT: [[TMP93:%.*]] = mul nuw i64 5, [[TMP5]] 518 // CHECK1-NEXT: [[TMP94:%.*]] = mul nuw i64 [[TMP93]], 8 519 // CHECK1-NEXT: [[TMP95:%.*]] = bitcast [9 x i64]* [[DOTOFFLOAD_SIZES]] to i8* 520 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP95]], i8* align 8 bitcast ([9 x i64]* @.offload_sizes.10 to i8*), i64 72, i1 false) 521 // CHECK1-NEXT: [[TMP96:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 0 522 // CHECK1-NEXT: [[TMP97:%.*]] = bitcast i8** [[TMP96]] to i64* 523 // CHECK1-NEXT: store i64 [[TMP90]], i64* [[TMP97]], align 8 524 // CHECK1-NEXT: [[TMP98:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 0 525 // CHECK1-NEXT: [[TMP99:%.*]] = bitcast i8** [[TMP98]] to i64* 526 // CHECK1-NEXT: store i64 [[TMP90]], i64* [[TMP99]], align 8 527 // CHECK1-NEXT: [[TMP100:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 0 528 // CHECK1-NEXT: store i8* null, i8** [[TMP100]], align 8 529 // CHECK1-NEXT: [[TMP101:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 1 530 // CHECK1-NEXT: [[TMP102:%.*]] = bitcast i8** [[TMP101]] to [10 x float]** 531 // CHECK1-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP102]], align 8 532 // CHECK1-NEXT: [[TMP103:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 1 533 // CHECK1-NEXT: [[TMP104:%.*]] = bitcast i8** [[TMP103]] to [10 x float]** 534 // CHECK1-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP104]], align 8 535 // CHECK1-NEXT: [[TMP105:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 1 536 // CHECK1-NEXT: store i8* null, i8** [[TMP105]], align 8 537 // CHECK1-NEXT: [[TMP106:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 2 538 // CHECK1-NEXT: [[TMP107:%.*]] = bitcast i8** [[TMP106]] to i64* 539 // CHECK1-NEXT: store i64 [[TMP2]], i64* [[TMP107]], align 8 540 // CHECK1-NEXT: [[TMP108:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 2 541 // CHECK1-NEXT: [[TMP109:%.*]] = bitcast i8** [[TMP108]] to i64* 542 // CHECK1-NEXT: store i64 [[TMP2]], i64* [[TMP109]], align 8 543 // CHECK1-NEXT: [[TMP110:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 2 544 // CHECK1-NEXT: store i8* null, i8** [[TMP110]], align 8 545 // CHECK1-NEXT: [[TMP111:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 3 546 // CHECK1-NEXT: [[TMP112:%.*]] = bitcast i8** [[TMP111]] to float** 547 // CHECK1-NEXT: store float* [[VLA]], float** [[TMP112]], align 8 548 // CHECK1-NEXT: [[TMP113:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 3 549 // CHECK1-NEXT: [[TMP114:%.*]] = bitcast i8** [[TMP113]] to float** 550 // CHECK1-NEXT: store float* [[VLA]], float** [[TMP114]], align 8 551 // CHECK1-NEXT: [[TMP115:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 552 // CHECK1-NEXT: store i64 [[TMP92]], i64* [[TMP115]], align 8 553 // CHECK1-NEXT: [[TMP116:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 3 554 // CHECK1-NEXT: store i8* null, i8** [[TMP116]], align 8 555 // CHECK1-NEXT: [[TMP117:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 4 556 // CHECK1-NEXT: [[TMP118:%.*]] = bitcast i8** [[TMP117]] to [5 x [10 x double]]** 557 // CHECK1-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP118]], align 8 558 // CHECK1-NEXT: [[TMP119:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 4 559 // CHECK1-NEXT: [[TMP120:%.*]] = bitcast i8** [[TMP119]] to [5 x [10 x double]]** 560 // CHECK1-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP120]], align 8 561 // CHECK1-NEXT: [[TMP121:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 4 562 // CHECK1-NEXT: store i8* null, i8** [[TMP121]], align 8 563 // CHECK1-NEXT: [[TMP122:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 5 564 // CHECK1-NEXT: [[TMP123:%.*]] = bitcast i8** [[TMP122]] to i64* 565 // CHECK1-NEXT: store i64 5, i64* [[TMP123]], align 8 566 // CHECK1-NEXT: [[TMP124:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 5 567 // CHECK1-NEXT: [[TMP125:%.*]] = bitcast i8** [[TMP124]] to i64* 568 // CHECK1-NEXT: store i64 5, i64* [[TMP125]], align 8 569 // CHECK1-NEXT: [[TMP126:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 5 570 // CHECK1-NEXT: store i8* null, i8** [[TMP126]], align 8 571 // CHECK1-NEXT: [[TMP127:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 6 572 // CHECK1-NEXT: [[TMP128:%.*]] = bitcast i8** [[TMP127]] to i64* 573 // CHECK1-NEXT: store i64 [[TMP5]], i64* [[TMP128]], align 8 574 // CHECK1-NEXT: [[TMP129:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 6 575 // CHECK1-NEXT: [[TMP130:%.*]] = bitcast i8** [[TMP129]] to i64* 576 // CHECK1-NEXT: store i64 [[TMP5]], i64* [[TMP130]], align 8 577 // CHECK1-NEXT: [[TMP131:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 6 578 // CHECK1-NEXT: store i8* null, i8** [[TMP131]], align 8 579 // CHECK1-NEXT: [[TMP132:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 7 580 // CHECK1-NEXT: [[TMP133:%.*]] = bitcast i8** [[TMP132]] to double** 581 // CHECK1-NEXT: store double* [[VLA1]], double** [[TMP133]], align 8 582 // CHECK1-NEXT: [[TMP134:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 7 583 // CHECK1-NEXT: [[TMP135:%.*]] = bitcast i8** [[TMP134]] to double** 584 // CHECK1-NEXT: store double* [[VLA1]], double** [[TMP135]], align 8 585 // CHECK1-NEXT: [[TMP136:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 586 // CHECK1-NEXT: store i64 [[TMP94]], i64* [[TMP136]], align 8 587 // CHECK1-NEXT: [[TMP137:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 7 588 // CHECK1-NEXT: store i8* null, i8** [[TMP137]], align 8 589 // CHECK1-NEXT: [[TMP138:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 8 590 // CHECK1-NEXT: [[TMP139:%.*]] = bitcast i8** [[TMP138]] to %struct.TT** 591 // CHECK1-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP139]], align 8 592 // CHECK1-NEXT: [[TMP140:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 8 593 // CHECK1-NEXT: [[TMP141:%.*]] = bitcast i8** [[TMP140]] to %struct.TT** 594 // CHECK1-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP141]], align 8 595 // CHECK1-NEXT: [[TMP142:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 8 596 // CHECK1-NEXT: store i8* null, i8** [[TMP142]], align 8 597 // CHECK1-NEXT: [[TMP143:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 0 598 // CHECK1-NEXT: [[TMP144:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 0 599 // CHECK1-NEXT: [[TMP145:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 600 // CHECK1-NEXT: [[TMP146:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142.region_id, i32 9, i8** [[TMP143]], i8** [[TMP144]], i64* [[TMP145]], i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_maptypes.11, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 601 // CHECK1-NEXT: [[TMP147:%.*]] = icmp ne i32 [[TMP146]], 0 602 // CHECK1-NEXT: br i1 [[TMP147]], label [[OMP_OFFLOAD_FAILED28:%.*]], label [[OMP_OFFLOAD_CONT29:%.*]] 603 // CHECK1: omp_offload.failed28: 604 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i64 [[TMP90]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR3]] 605 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT29]] 606 // CHECK1: omp_offload.cont29: 607 // CHECK1-NEXT: br label [[OMP_IF_END31:%.*]] 608 // CHECK1: omp_if.else30: 609 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i64 [[TMP90]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR3]] 610 // CHECK1-NEXT: br label [[OMP_IF_END31]] 611 // CHECK1: omp_if.end31: 612 // CHECK1-NEXT: store i32 0, i32* [[NN]], align 4 613 // CHECK1-NEXT: [[TMP148:%.*]] = load i32, i32* [[NN]], align 4 614 // CHECK1-NEXT: [[CONV32:%.*]] = bitcast i64* [[NN_CASTED]] to i32* 615 // CHECK1-NEXT: store i32 [[TMP148]], i32* [[CONV32]], align 4 616 // CHECK1-NEXT: [[TMP149:%.*]] = load i64, i64* [[NN_CASTED]], align 8 617 // CHECK1-NEXT: [[TMP150:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS33]], i32 0, i32 0 618 // CHECK1-NEXT: [[TMP151:%.*]] = bitcast i8** [[TMP150]] to i64* 619 // CHECK1-NEXT: store i64 [[TMP149]], i64* [[TMP151]], align 8 620 // CHECK1-NEXT: [[TMP152:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS34]], i32 0, i32 0 621 // CHECK1-NEXT: [[TMP153:%.*]] = bitcast i8** [[TMP152]] to i64* 622 // CHECK1-NEXT: store i64 [[TMP149]], i64* [[TMP153]], align 8 623 // CHECK1-NEXT: [[TMP154:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS35]], i64 0, i64 0 624 // CHECK1-NEXT: store i8* null, i8** [[TMP154]], align 8 625 // CHECK1-NEXT: [[TMP155:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS33]], i32 0, i32 0 626 // CHECK1-NEXT: [[TMP156:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS34]], i32 0, i32 0 627 // CHECK1-NEXT: [[TMP157:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154.region_id, i32 1, i8** [[TMP155]], i8** [[TMP156]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.14, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.15, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 628 // CHECK1-NEXT: [[TMP158:%.*]] = icmp ne i32 [[TMP157]], 0 629 // CHECK1-NEXT: br i1 [[TMP158]], label [[OMP_OFFLOAD_FAILED36:%.*]], label [[OMP_OFFLOAD_CONT37:%.*]] 630 // CHECK1: omp_offload.failed36: 631 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154(i64 [[TMP149]]) #[[ATTR3]] 632 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT37]] 633 // CHECK1: omp_offload.cont37: 634 // CHECK1-NEXT: [[TMP159:%.*]] = load i32, i32* [[NN]], align 4 635 // CHECK1-NEXT: [[CONV39:%.*]] = bitcast i64* [[NN_CASTED38]] to i32* 636 // CHECK1-NEXT: store i32 [[TMP159]], i32* [[CONV39]], align 4 637 // CHECK1-NEXT: [[TMP160:%.*]] = load i64, i64* [[NN_CASTED38]], align 8 638 // CHECK1-NEXT: [[TMP161:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS40]], i32 0, i32 0 639 // CHECK1-NEXT: [[TMP162:%.*]] = bitcast i8** [[TMP161]] to i64* 640 // CHECK1-NEXT: store i64 [[TMP160]], i64* [[TMP162]], align 8 641 // CHECK1-NEXT: [[TMP163:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS41]], i32 0, i32 0 642 // CHECK1-NEXT: [[TMP164:%.*]] = bitcast i8** [[TMP163]] to i64* 643 // CHECK1-NEXT: store i64 [[TMP160]], i64* [[TMP164]], align 8 644 // CHECK1-NEXT: [[TMP165:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS42]], i64 0, i64 0 645 // CHECK1-NEXT: store i8* null, i8** [[TMP165]], align 8 646 // CHECK1-NEXT: [[TMP166:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS40]], i32 0, i32 0 647 // CHECK1-NEXT: [[TMP167:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS41]], i32 0, i32 0 648 // CHECK1-NEXT: [[TMP168:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157.region_id, i32 1, i8** [[TMP166]], i8** [[TMP167]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.18, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.19, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 649 // CHECK1-NEXT: [[TMP169:%.*]] = icmp ne i32 [[TMP168]], 0 650 // CHECK1-NEXT: br i1 [[TMP169]], label [[OMP_OFFLOAD_FAILED43:%.*]], label [[OMP_OFFLOAD_CONT44:%.*]] 651 // CHECK1: omp_offload.failed43: 652 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157(i64 [[TMP160]]) #[[ATTR3]] 653 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT44]] 654 // CHECK1: omp_offload.cont44: 655 // CHECK1-NEXT: [[TMP170:%.*]] = load i32, i32* [[A]], align 4 656 // CHECK1-NEXT: [[TMP171:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 657 // CHECK1-NEXT: call void @llvm.stackrestore(i8* [[TMP171]]) 658 // CHECK1-NEXT: ret i32 [[TMP170]] 659 // 660 // 661 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101 662 // CHECK1-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] { 663 // CHECK1-NEXT: entry: 664 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 665 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 666 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8 667 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 668 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 669 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 670 // CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 671 // CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8 672 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 673 // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* 674 // CHECK1-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32* 675 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 4 676 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 4 677 // CHECK1-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) 678 // CHECK1-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 679 // CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 680 // CHECK1-NEXT: store i16 [[TMP3]], i16* [[CONV5]], align 2 681 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 682 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]]) 683 // CHECK1-NEXT: ret void 684 // 685 // 686 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. 687 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { 688 // CHECK1-NEXT: entry: 689 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 690 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 691 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 692 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 693 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 694 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 695 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 696 // CHECK1-NEXT: ret void 697 // 698 // 699 // CHECK1-LABEL: define {{[^@]+}}@.omp_task_privates_map. 700 // CHECK1-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], i16** noalias noundef [[TMP1:%.*]], [3 x i8*]** noalias noundef [[TMP2:%.*]], [3 x i8*]** noalias noundef [[TMP3:%.*]], [3 x i64]** noalias noundef [[TMP4:%.*]]) #[[ATTR4:[0-9]+]] { 701 // CHECK1-NEXT: entry: 702 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 8 703 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i16**, align 8 704 // CHECK1-NEXT: [[DOTADDR2:%.*]] = alloca [3 x i8*]**, align 8 705 // CHECK1-NEXT: [[DOTADDR3:%.*]] = alloca [3 x i8*]**, align 8 706 // CHECK1-NEXT: [[DOTADDR4:%.*]] = alloca [3 x i64]**, align 8 707 // CHECK1-NEXT: store %struct..kmp_privates.t* [[TMP0]], %struct..kmp_privates.t** [[DOTADDR]], align 8 708 // CHECK1-NEXT: store i16** [[TMP1]], i16*** [[DOTADDR1]], align 8 709 // CHECK1-NEXT: store [3 x i8*]** [[TMP2]], [3 x i8*]*** [[DOTADDR2]], align 8 710 // CHECK1-NEXT: store [3 x i8*]** [[TMP3]], [3 x i8*]*** [[DOTADDR3]], align 8 711 // CHECK1-NEXT: store [3 x i64]** [[TMP4]], [3 x i64]*** [[DOTADDR4]], align 8 712 // CHECK1-NEXT: [[TMP5:%.*]] = load %struct..kmp_privates.t*, %struct..kmp_privates.t** [[DOTADDR]], align 8 713 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 0 714 // CHECK1-NEXT: [[TMP7:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR2]], align 8 715 // CHECK1-NEXT: store [3 x i8*]* [[TMP6]], [3 x i8*]** [[TMP7]], align 8 716 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 1 717 // CHECK1-NEXT: [[TMP9:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR3]], align 8 718 // CHECK1-NEXT: store [3 x i8*]* [[TMP8]], [3 x i8*]** [[TMP9]], align 8 719 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 2 720 // CHECK1-NEXT: [[TMP11:%.*]] = load [3 x i64]**, [3 x i64]*** [[DOTADDR4]], align 8 721 // CHECK1-NEXT: store [3 x i64]* [[TMP10]], [3 x i64]** [[TMP11]], align 8 722 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 3 723 // CHECK1-NEXT: [[TMP13:%.*]] = load i16**, i16*** [[DOTADDR1]], align 8 724 // CHECK1-NEXT: store i16* [[TMP12]], i16** [[TMP13]], align 8 725 // CHECK1-NEXT: ret void 726 // 727 // 728 // CHECK1-LABEL: define {{[^@]+}}@.omp_task_entry. 729 // CHECK1-SAME: (i32 noundef signext [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { 730 // CHECK1-NEXT: entry: 731 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 732 // CHECK1-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 733 // CHECK1-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8 734 // CHECK1-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8 735 // CHECK1-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8 736 // CHECK1-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 8 737 // CHECK1-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca i16*, align 8 738 // CHECK1-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca [3 x i8*]*, align 8 739 // CHECK1-NEXT: [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca [3 x i8*]*, align 8 740 // CHECK1-NEXT: [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca [3 x i64]*, align 8 741 // CHECK1-NEXT: [[AA_CASTED_I:%.*]] = alloca i64, align 8 742 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED_I:%.*]] = alloca i64, align 8 743 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED5_I:%.*]] = alloca i64, align 8 744 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 745 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8 746 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 747 // CHECK1-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 748 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 749 // CHECK1-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 750 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0 751 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 752 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 753 // CHECK1-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 754 // CHECK1-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon* 755 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1 756 // CHECK1-NEXT: [[TMP10:%.*]] = bitcast %struct..kmp_privates.t* [[TMP9]] to i8* 757 // CHECK1-NEXT: [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8* 758 // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]]) 759 // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]]) 760 // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]]) 761 // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META22:![0-9]+]]) 762 // CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !24 763 // CHECK1-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !24 764 // CHECK1-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !24 765 // CHECK1-NEXT: store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* @.omp_task_privates_map. to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !24 766 // CHECK1-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !24 767 // CHECK1-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !24 768 // CHECK1-NEXT: [[TMP12:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !24 769 // CHECK1-NEXT: [[TMP13:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !24 770 // CHECK1-NEXT: [[TMP14:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !24 771 // CHECK1-NEXT: [[TMP15:%.*]] = bitcast void (i8*, ...)* [[TMP13]] to void (i8*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* 772 // CHECK1-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]] 773 // CHECK1-NEXT: [[TMP16:%.*]] = load i16*, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !24 774 // CHECK1-NEXT: [[TMP17:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !24 775 // CHECK1-NEXT: [[TMP18:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 8, !noalias !24 776 // CHECK1-NEXT: [[TMP19:%.*]] = load [3 x i64]*, [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 8, !noalias !24 777 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP17]], i64 0, i64 0 778 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP18]], i64 0, i64 0 779 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[TMP19]], i64 0, i64 0 780 // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP12]], i32 0, i32 1 781 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[TMP12]], i32 0, i32 2 782 // CHECK1-NEXT: [[TMP25:%.*]] = load i32, i32* [[TMP23]], align 4 783 // CHECK1-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP24]], align 4 784 // CHECK1-NEXT: [[TMP27:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 [[TMP25]], i32 [[TMP26]], i32 0, i8* null, i32 0, i8* null) #[[ATTR3]] 785 // CHECK1-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0 786 // CHECK1-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]] 787 // CHECK1: omp_offload.failed.i: 788 // CHECK1-NEXT: [[TMP29:%.*]] = load i16, i16* [[TMP16]], align 2 789 // CHECK1-NEXT: [[CONV_I:%.*]] = bitcast i64* [[AA_CASTED_I]] to i16* 790 // CHECK1-NEXT: store i16 [[TMP29]], i16* [[CONV_I]], align 2, !noalias !24 791 // CHECK1-NEXT: [[TMP30:%.*]] = load i64, i64* [[AA_CASTED_I]], align 8, !noalias !24 792 // CHECK1-NEXT: [[TMP31:%.*]] = load i32, i32* [[TMP23]], align 4 793 // CHECK1-NEXT: [[CONV4_I:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED_I]] to i32* 794 // CHECK1-NEXT: store i32 [[TMP31]], i32* [[CONV4_I]], align 4, !noalias !24 795 // CHECK1-NEXT: [[TMP32:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED_I]], align 8, !noalias !24 796 // CHECK1-NEXT: [[TMP33:%.*]] = load i32, i32* [[TMP24]], align 4 797 // CHECK1-NEXT: [[CONV6_I:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED5_I]] to i32* 798 // CHECK1-NEXT: store i32 [[TMP33]], i32* [[CONV6_I]], align 4, !noalias !24 799 // CHECK1-NEXT: [[TMP34:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED5_I]], align 8, !noalias !24 800 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101(i64 [[TMP30]], i64 [[TMP32]], i64 [[TMP34]]) #[[ATTR3]] 801 // CHECK1-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]] 802 // CHECK1: .omp_outlined..1.exit: 803 // CHECK1-NEXT: ret i32 0 804 // 805 // 806 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l105 807 // CHECK1-SAME: (i64 noundef [[A:%.*]]) #[[ATTR2]] { 808 // CHECK1-NEXT: entry: 809 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 810 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 811 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 812 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 813 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 814 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32* 815 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 816 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 817 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]]) 818 // CHECK1-NEXT: ret void 819 // 820 // 821 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..2 822 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]]) #[[ATTR2]] { 823 // CHECK1-NEXT: entry: 824 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 825 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 826 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 827 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 828 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 829 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 830 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 831 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 832 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 833 // CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 834 // CHECK1-NEXT: ret void 835 // 836 // 837 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 838 // CHECK1-SAME: (i64 noundef [[AA:%.*]]) #[[ATTR2]] { 839 // CHECK1-NEXT: entry: 840 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 841 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 842 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 843 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 844 // CHECK1-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 845 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 846 // CHECK1-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 847 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 848 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP1]]) 849 // CHECK1-NEXT: ret void 850 // 851 // 852 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..3 853 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { 854 // CHECK1-NEXT: entry: 855 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 856 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 857 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 858 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 859 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 860 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 861 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 862 // CHECK1-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 863 // CHECK1-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 864 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 865 // CHECK1-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 866 // CHECK1-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2 867 // CHECK1-NEXT: ret void 868 // 869 // 870 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118 871 // CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { 872 // CHECK1-NEXT: entry: 873 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 874 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 875 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 876 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 877 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 878 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 879 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 880 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 881 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 882 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* 883 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 884 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 885 // CHECK1-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 886 // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 887 // CHECK1-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 888 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 889 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) 890 // CHECK1-NEXT: ret void 891 // 892 // 893 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..6 894 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { 895 // CHECK1-NEXT: entry: 896 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 897 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 898 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 899 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 900 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 901 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 902 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 903 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 904 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 905 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 906 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 907 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 908 // CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 909 // CHECK1-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 2 910 // CHECK1-NEXT: [[CONV2:%.*]] = sext i16 [[TMP1]] to i32 911 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 912 // CHECK1-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 913 // CHECK1-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2 914 // CHECK1-NEXT: ret void 915 // 916 // 917 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142 918 // CHECK1-SAME: (i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] { 919 // CHECK1-NEXT: entry: 920 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 921 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 922 // CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 923 // CHECK1-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 924 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 925 // CHECK1-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 926 // CHECK1-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 927 // CHECK1-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 928 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 929 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 930 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 931 // CHECK1-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 932 // CHECK1-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 933 // CHECK1-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 934 // CHECK1-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 935 // CHECK1-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 936 // CHECK1-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 937 // CHECK1-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 938 // CHECK1-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 939 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 940 // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 941 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 942 // CHECK1-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 943 // CHECK1-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 944 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 945 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 946 // CHECK1-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 947 // CHECK1-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 948 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 949 // CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* 950 // CHECK1-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4 951 // CHECK1-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 952 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) 953 // CHECK1-NEXT: ret void 954 // 955 // 956 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..9 957 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] { 958 // CHECK1-NEXT: entry: 959 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 960 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 961 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 962 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 963 // CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 964 // CHECK1-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 965 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 966 // CHECK1-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 967 // CHECK1-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 968 // CHECK1-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 969 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 970 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 971 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 972 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 973 // CHECK1-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 974 // CHECK1-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 975 // CHECK1-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 976 // CHECK1-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 977 // CHECK1-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 978 // CHECK1-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 979 // CHECK1-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 980 // CHECK1-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 981 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 982 // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 983 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 984 // CHECK1-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 985 // CHECK1-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 986 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 987 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 988 // CHECK1-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 989 // CHECK1-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 990 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 991 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 992 // CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 993 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 994 // CHECK1-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 995 // CHECK1-NEXT: [[CONV5:%.*]] = fpext float [[TMP9]] to double 996 // CHECK1-NEXT: [[ADD6:%.*]] = fadd double [[CONV5]], 1.000000e+00 997 // CHECK1-NEXT: [[CONV7:%.*]] = fptrunc double [[ADD6]] to float 998 // CHECK1-NEXT: store float [[CONV7]], float* [[ARRAYIDX]], align 4 999 // CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 1000 // CHECK1-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX8]], align 4 1001 // CHECK1-NEXT: [[CONV9:%.*]] = fpext float [[TMP10]] to double 1002 // CHECK1-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 1003 // CHECK1-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float 1004 // CHECK1-NEXT: store float [[CONV11]], float* [[ARRAYIDX8]], align 4 1005 // CHECK1-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1 1006 // CHECK1-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX12]], i64 0, i64 2 1007 // CHECK1-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX13]], align 8 1008 // CHECK1-NEXT: [[ADD14:%.*]] = fadd double [[TMP11]], 1.000000e+00 1009 // CHECK1-NEXT: store double [[ADD14]], double* [[ARRAYIDX13]], align 8 1010 // CHECK1-NEXT: [[TMP12:%.*]] = mul nsw i64 1, [[TMP5]] 1011 // CHECK1-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP12]] 1012 // CHECK1-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX15]], i64 3 1013 // CHECK1-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX16]], align 8 1014 // CHECK1-NEXT: [[ADD17:%.*]] = fadd double [[TMP13]], 1.000000e+00 1015 // CHECK1-NEXT: store double [[ADD17]], double* [[ARRAYIDX16]], align 8 1016 // CHECK1-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 1017 // CHECK1-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 8 1018 // CHECK1-NEXT: [[ADD18:%.*]] = add nsw i64 [[TMP14]], 1 1019 // CHECK1-NEXT: store i64 [[ADD18]], i64* [[X]], align 8 1020 // CHECK1-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 1021 // CHECK1-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 8 1022 // CHECK1-NEXT: [[CONV19:%.*]] = sext i8 [[TMP15]] to i32 1023 // CHECK1-NEXT: [[ADD20:%.*]] = add nsw i32 [[CONV19]], 1 1024 // CHECK1-NEXT: [[CONV21:%.*]] = trunc i32 [[ADD20]] to i8 1025 // CHECK1-NEXT: store i8 [[CONV21]], i8* [[Y]], align 8 1026 // CHECK1-NEXT: ret void 1027 // 1028 // 1029 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154 1030 // CHECK1-SAME: (i64 noundef [[NN:%.*]]) #[[ATTR2]] { 1031 // CHECK1-NEXT: entry: 1032 // CHECK1-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 1033 // CHECK1-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 1034 // CHECK1-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 1035 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* 1036 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 1037 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32* 1038 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 1039 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8 1040 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..12 to void (i32*, i32*, ...)*), i64 [[TMP1]]) 1041 // CHECK1-NEXT: ret void 1042 // 1043 // 1044 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..12 1045 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[NN:%.*]]) #[[ATTR2]] { 1046 // CHECK1-NEXT: entry: 1047 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1048 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1049 // CHECK1-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 1050 // CHECK1-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 1051 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1052 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1053 // CHECK1-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 1054 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* 1055 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 1056 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32* 1057 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 1058 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8 1059 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..13 to void (i32*, i32*, ...)*), i64 [[TMP1]]) 1060 // CHECK1-NEXT: ret void 1061 // 1062 // 1063 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..13 1064 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[NN:%.*]]) #[[ATTR2]] { 1065 // CHECK1-NEXT: entry: 1066 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1067 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1068 // CHECK1-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 1069 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1070 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1071 // CHECK1-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 1072 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* 1073 // CHECK1-NEXT: ret void 1074 // 1075 // 1076 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157 1077 // CHECK1-SAME: (i64 noundef [[NN:%.*]]) #[[ATTR2]] { 1078 // CHECK1-NEXT: entry: 1079 // CHECK1-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 1080 // CHECK1-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 1081 // CHECK1-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 1082 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* 1083 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 1084 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32* 1085 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 1086 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8 1087 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i64 [[TMP1]]) 1088 // CHECK1-NEXT: ret void 1089 // 1090 // 1091 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..16 1092 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[NN:%.*]]) #[[ATTR2]] { 1093 // CHECK1-NEXT: entry: 1094 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1095 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1096 // CHECK1-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 1097 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1098 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1099 // CHECK1-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 1100 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* 1101 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..17 to void (i32*, i32*, ...)*), i32* [[CONV]]) 1102 // CHECK1-NEXT: ret void 1103 // 1104 // 1105 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..17 1106 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[NN:%.*]]) #[[ATTR2]] { 1107 // CHECK1-NEXT: entry: 1108 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1109 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1110 // CHECK1-NEXT: [[NN_ADDR:%.*]] = alloca i32*, align 8 1111 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1112 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1113 // CHECK1-NEXT: store i32* [[NN]], i32** [[NN_ADDR]], align 8 1114 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[NN_ADDR]], align 8 1115 // CHECK1-NEXT: ret void 1116 // 1117 // 1118 // CHECK1-LABEL: define {{[^@]+}}@_Z6bazzzziPi 1119 // CHECK1-SAME: (i32 noundef signext [[N:%.*]], i32* noundef [[F:%.*]]) #[[ATTR0]] { 1120 // CHECK1-NEXT: entry: 1121 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 1122 // CHECK1-NEXT: [[F_ADDR:%.*]] = alloca i32*, align 8 1123 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 1124 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 1125 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 1126 // CHECK1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 1127 // CHECK1-NEXT: store i32* [[F]], i32** [[F_ADDR]], align 8 1128 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 1129 // CHECK1-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 1130 // CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1131 // CHECK1-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to i64* 1132 // CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP3]], align 8 1133 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1134 // CHECK1-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i64* 1135 // CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP5]], align 8 1136 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 1137 // CHECK1-NEXT: store i8* null, i8** [[TMP6]], align 8 1138 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1139 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1140 // CHECK1-NEXT: [[TMP9:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182.region_id, i32 1, i8** [[TMP7]], i8** [[TMP8]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.21, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.22, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 1141 // CHECK1-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 1142 // CHECK1-NEXT: br i1 [[TMP10]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1143 // CHECK1: omp_offload.failed: 1144 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182(i64 [[TMP1]]) #[[ATTR3]] 1145 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 1146 // CHECK1: omp_offload.cont: 1147 // CHECK1-NEXT: ret void 1148 // 1149 // 1150 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182 1151 // CHECK1-SAME: (i64 noundef [[VLA:%.*]]) #[[ATTR2]] { 1152 // CHECK1-NEXT: entry: 1153 // CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 1154 // CHECK1-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 1155 // CHECK1-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 1156 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..20 to void (i32*, i32*, ...)*), i64 [[TMP0]]) 1157 // CHECK1-NEXT: ret void 1158 // 1159 // 1160 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..20 1161 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[VLA:%.*]]) #[[ATTR2]] { 1162 // CHECK1-NEXT: entry: 1163 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1164 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1165 // CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 1166 // CHECK1-NEXT: [[F:%.*]] = alloca i32*, align 8 1167 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1168 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1169 // CHECK1-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 1170 // CHECK1-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 1171 // CHECK1-NEXT: ret void 1172 // 1173 // 1174 // CHECK1-LABEL: define {{[^@]+}}@_Z3bari 1175 // CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { 1176 // CHECK1-NEXT: entry: 1177 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 1178 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4 1179 // CHECK1-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 1180 // CHECK1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 1181 // CHECK1-NEXT: store i32 0, i32* [[A]], align 4 1182 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 1183 // CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]]) 1184 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 1185 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 1186 // CHECK1-NEXT: store i32 [[ADD]], i32* [[A]], align 4 1187 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 1188 // CHECK1-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP2]]) 1189 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 1190 // CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 1191 // CHECK1-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 1192 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 1193 // CHECK1-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]]) 1194 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 1195 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 1196 // CHECK1-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 1197 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 1198 // CHECK1-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]]) 1199 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 1200 // CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] 1201 // CHECK1-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 1202 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 1203 // CHECK1-NEXT: ret i32 [[TMP8]] 1204 // 1205 // 1206 // CHECK1-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 1207 // CHECK1-SAME: (%struct.S1* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { 1208 // CHECK1-NEXT: entry: 1209 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 1210 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 1211 // CHECK1-NEXT: [[B:%.*]] = alloca i32, align 4 1212 // CHECK1-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 1213 // CHECK1-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 1214 // CHECK1-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 1215 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8 1216 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8 1217 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8 1218 // CHECK1-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 8 1219 // CHECK1-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 1220 // CHECK1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 1221 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 1222 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 1223 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 1224 // CHECK1-NEXT: store i32 [[ADD]], i32* [[B]], align 4 1225 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 1226 // CHECK1-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 1227 // CHECK1-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() 1228 // CHECK1-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 1229 // CHECK1-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] 1230 // CHECK1-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 1231 // CHECK1-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 1232 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 1233 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32* 1234 // CHECK1-NEXT: store i32 [[TMP5]], i32* [[CONV]], align 4 1235 // CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 1236 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4 1237 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 60 1238 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 1239 // CHECK1: omp_if.then: 1240 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 1241 // CHECK1-NEXT: [[TMP8:%.*]] = mul nuw i64 2, [[TMP2]] 1242 // CHECK1-NEXT: [[TMP9:%.*]] = mul nuw i64 [[TMP8]], 2 1243 // CHECK1-NEXT: [[TMP10:%.*]] = bitcast [5 x i64]* [[DOTOFFLOAD_SIZES]] to i8* 1244 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP10]], i8* align 8 bitcast ([5 x i64]* @.offload_sizes.24 to i8*), i64 40, i1 false) 1245 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1246 // CHECK1-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to %struct.S1** 1247 // CHECK1-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP12]], align 8 1248 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1249 // CHECK1-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to double** 1250 // CHECK1-NEXT: store double* [[A]], double** [[TMP14]], align 8 1251 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 1252 // CHECK1-NEXT: store i8* null, i8** [[TMP15]], align 8 1253 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1254 // CHECK1-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64* 1255 // CHECK1-NEXT: store i64 [[TMP6]], i64* [[TMP17]], align 8 1256 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1257 // CHECK1-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64* 1258 // CHECK1-NEXT: store i64 [[TMP6]], i64* [[TMP19]], align 8 1259 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 1260 // CHECK1-NEXT: store i8* null, i8** [[TMP20]], align 8 1261 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1262 // CHECK1-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i64* 1263 // CHECK1-NEXT: store i64 2, i64* [[TMP22]], align 8 1264 // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1265 // CHECK1-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i64* 1266 // CHECK1-NEXT: store i64 2, i64* [[TMP24]], align 8 1267 // CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 1268 // CHECK1-NEXT: store i8* null, i8** [[TMP25]], align 8 1269 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 1270 // CHECK1-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64* 1271 // CHECK1-NEXT: store i64 [[TMP2]], i64* [[TMP27]], align 8 1272 // CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 1273 // CHECK1-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i64* 1274 // CHECK1-NEXT: store i64 [[TMP2]], i64* [[TMP29]], align 8 1275 // CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 1276 // CHECK1-NEXT: store i8* null, i8** [[TMP30]], align 8 1277 // CHECK1-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 1278 // CHECK1-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i16** 1279 // CHECK1-NEXT: store i16* [[VLA]], i16** [[TMP32]], align 8 1280 // CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 1281 // CHECK1-NEXT: [[TMP34:%.*]] = bitcast i8** [[TMP33]] to i16** 1282 // CHECK1-NEXT: store i16* [[VLA]], i16** [[TMP34]], align 8 1283 // CHECK1-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 1284 // CHECK1-NEXT: store i64 [[TMP9]], i64* [[TMP35]], align 8 1285 // CHECK1-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 1286 // CHECK1-NEXT: store i8* null, i8** [[TMP36]], align 8 1287 // CHECK1-NEXT: [[TMP37:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1288 // CHECK1-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1289 // CHECK1-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 1290 // CHECK1-NEXT: [[TMP40:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227.region_id, i32 5, i8** [[TMP37]], i8** [[TMP38]], i64* [[TMP39]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.25, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 1291 // CHECK1-NEXT: [[TMP41:%.*]] = icmp ne i32 [[TMP40]], 0 1292 // CHECK1-NEXT: br i1 [[TMP41]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1293 // CHECK1: omp_offload.failed: 1294 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR3]] 1295 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 1296 // CHECK1: omp_offload.cont: 1297 // CHECK1-NEXT: br label [[OMP_IF_END:%.*]] 1298 // CHECK1: omp_if.else: 1299 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR3]] 1300 // CHECK1-NEXT: br label [[OMP_IF_END]] 1301 // CHECK1: omp_if.end: 1302 // CHECK1-NEXT: [[TMP42:%.*]] = mul nsw i64 1, [[TMP2]] 1303 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP42]] 1304 // CHECK1-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 1305 // CHECK1-NEXT: [[TMP43:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2 1306 // CHECK1-NEXT: [[CONV3:%.*]] = sext i16 [[TMP43]] to i32 1307 // CHECK1-NEXT: [[TMP44:%.*]] = load i32, i32* [[B]], align 4 1308 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], [[TMP44]] 1309 // CHECK1-NEXT: [[TMP45:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 1310 // CHECK1-NEXT: call void @llvm.stackrestore(i8* [[TMP45]]) 1311 // CHECK1-NEXT: ret i32 [[ADD4]] 1312 // 1313 // 1314 // CHECK1-LABEL: define {{[^@]+}}@_ZL7fstatici 1315 // CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { 1316 // CHECK1-NEXT: entry: 1317 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 1318 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4 1319 // CHECK1-NEXT: [[AA:%.*]] = alloca i16, align 2 1320 // CHECK1-NEXT: [[AAA:%.*]] = alloca i8, align 1 1321 // CHECK1-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 1322 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 1323 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 1324 // CHECK1-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 1325 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8 1326 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 1327 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 1328 // CHECK1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 1329 // CHECK1-NEXT: store i32 0, i32* [[A]], align 4 1330 // CHECK1-NEXT: store i16 0, i16* [[AA]], align 2 1331 // CHECK1-NEXT: store i8 0, i8* [[AAA]], align 1 1332 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 1333 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* 1334 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 1335 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 1336 // CHECK1-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 1337 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 1338 // CHECK1-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 1339 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 1340 // CHECK1-NEXT: [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1 1341 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* 1342 // CHECK1-NEXT: store i8 [[TMP4]], i8* [[CONV2]], align 1 1343 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 1344 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 1345 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50 1346 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 1347 // CHECK1: omp_if.then: 1348 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1349 // CHECK1-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* 1350 // CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8 1351 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1352 // CHECK1-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* 1353 // CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP10]], align 8 1354 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 1355 // CHECK1-NEXT: store i8* null, i8** [[TMP11]], align 8 1356 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1357 // CHECK1-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* 1358 // CHECK1-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8 1359 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1360 // CHECK1-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* 1361 // CHECK1-NEXT: store i64 [[TMP3]], i64* [[TMP15]], align 8 1362 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 1363 // CHECK1-NEXT: store i8* null, i8** [[TMP16]], align 8 1364 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1365 // CHECK1-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64* 1366 // CHECK1-NEXT: store i64 [[TMP5]], i64* [[TMP18]], align 8 1367 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1368 // CHECK1-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64* 1369 // CHECK1-NEXT: store i64 [[TMP5]], i64* [[TMP20]], align 8 1370 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 1371 // CHECK1-NEXT: store i8* null, i8** [[TMP21]], align 8 1372 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 1373 // CHECK1-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]** 1374 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 8 1375 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 1376 // CHECK1-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]** 1377 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 8 1378 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 1379 // CHECK1-NEXT: store i8* null, i8** [[TMP26]], align 8 1380 // CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1381 // CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1382 // CHECK1-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.27, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.28, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 1383 // CHECK1-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 1384 // CHECK1-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1385 // CHECK1: omp_offload.failed: 1386 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR3]] 1387 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 1388 // CHECK1: omp_offload.cont: 1389 // CHECK1-NEXT: br label [[OMP_IF_END:%.*]] 1390 // CHECK1: omp_if.else: 1391 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR3]] 1392 // CHECK1-NEXT: br label [[OMP_IF_END]] 1393 // CHECK1: omp_if.end: 1394 // CHECK1-NEXT: [[TMP31:%.*]] = load i32, i32* [[A]], align 4 1395 // CHECK1-NEXT: ret i32 [[TMP31]] 1396 // 1397 // 1398 // CHECK1-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 1399 // CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat { 1400 // CHECK1-NEXT: entry: 1401 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 1402 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4 1403 // CHECK1-NEXT: [[AA:%.*]] = alloca i16, align 2 1404 // CHECK1-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 1405 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 1406 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 1407 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 1408 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 1409 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 1410 // CHECK1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 1411 // CHECK1-NEXT: store i32 0, i32* [[A]], align 4 1412 // CHECK1-NEXT: store i16 0, i16* [[AA]], align 2 1413 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 1414 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* 1415 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 1416 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 1417 // CHECK1-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 1418 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 1419 // CHECK1-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 1420 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 1421 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 1422 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40 1423 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 1424 // CHECK1: omp_if.then: 1425 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1426 // CHECK1-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64* 1427 // CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP6]], align 8 1428 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1429 // CHECK1-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* 1430 // CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8 1431 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 1432 // CHECK1-NEXT: store i8* null, i8** [[TMP9]], align 8 1433 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1434 // CHECK1-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i64* 1435 // CHECK1-NEXT: store i64 [[TMP3]], i64* [[TMP11]], align 8 1436 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1437 // CHECK1-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* 1438 // CHECK1-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8 1439 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 1440 // CHECK1-NEXT: store i8* null, i8** [[TMP14]], align 8 1441 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1442 // CHECK1-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]** 1443 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 8 1444 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1445 // CHECK1-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]** 1446 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 8 1447 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 1448 // CHECK1-NEXT: store i8* null, i8** [[TMP19]], align 8 1449 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1450 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1451 // CHECK1-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.30, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.31, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 1452 // CHECK1-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 1453 // CHECK1-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1454 // CHECK1: omp_offload.failed: 1455 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]] 1456 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 1457 // CHECK1: omp_offload.cont: 1458 // CHECK1-NEXT: br label [[OMP_IF_END:%.*]] 1459 // CHECK1: omp_if.else: 1460 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]] 1461 // CHECK1-NEXT: br label [[OMP_IF_END]] 1462 // CHECK1: omp_if.end: 1463 // CHECK1-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4 1464 // CHECK1-NEXT: ret i32 [[TMP24]] 1465 // 1466 // 1467 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227 1468 // CHECK1-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { 1469 // CHECK1-NEXT: entry: 1470 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 1471 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 1472 // CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 1473 // CHECK1-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 1474 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 1475 // CHECK1-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 1476 // CHECK1-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 1477 // CHECK1-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 1478 // CHECK1-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 1479 // CHECK1-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 1480 // CHECK1-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 1481 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 1482 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 1483 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 1484 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 1485 // CHECK1-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 1486 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4 1487 // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* 1488 // CHECK1-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 1489 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 1490 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..23 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) 1491 // CHECK1-NEXT: ret void 1492 // 1493 // 1494 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..23 1495 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { 1496 // CHECK1-NEXT: entry: 1497 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1498 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1499 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 1500 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 1501 // CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 1502 // CHECK1-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 1503 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 1504 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1505 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1506 // CHECK1-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 1507 // CHECK1-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 1508 // CHECK1-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 1509 // CHECK1-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 1510 // CHECK1-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 1511 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 1512 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 1513 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 1514 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 1515 // CHECK1-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 1516 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4 1517 // CHECK1-NEXT: [[CONV3:%.*]] = sitofp i32 [[TMP4]] to double 1518 // CHECK1-NEXT: [[ADD:%.*]] = fadd double [[CONV3]], 1.500000e+00 1519 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 1520 // CHECK1-NEXT: store double [[ADD]], double* [[A]], align 8 1521 // CHECK1-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 1522 // CHECK1-NEXT: [[TMP5:%.*]] = load double, double* [[A4]], align 8 1523 // CHECK1-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 1524 // CHECK1-NEXT: store double [[INC]], double* [[A4]], align 8 1525 // CHECK1-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 1526 // CHECK1-NEXT: [[TMP6:%.*]] = mul nsw i64 1, [[TMP2]] 1527 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP6]] 1528 // CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 1529 // CHECK1-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2 1530 // CHECK1-NEXT: ret void 1531 // 1532 // 1533 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209 1534 // CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 1535 // CHECK1-NEXT: entry: 1536 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1537 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 1538 // CHECK1-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 1539 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 1540 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 1541 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 1542 // CHECK1-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 1543 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 1544 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 1545 // CHECK1-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 1546 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 1547 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 1548 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 1549 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 1550 // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 1551 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 1552 // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* 1553 // CHECK1-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 1554 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 1555 // CHECK1-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 1556 // CHECK1-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 1557 // CHECK1-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 1558 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 1559 // CHECK1-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1 1560 // CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* 1561 // CHECK1-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 1562 // CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 1563 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..26 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) 1564 // CHECK1-NEXT: ret void 1565 // 1566 // 1567 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..26 1568 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 1569 // CHECK1-NEXT: entry: 1570 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1571 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1572 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1573 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 1574 // CHECK1-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 1575 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 1576 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1577 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1578 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 1579 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 1580 // CHECK1-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 1581 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 1582 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 1583 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 1584 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 1585 // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 1586 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 1587 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 1588 // CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 1589 // CHECK1-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 1590 // CHECK1-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32 1591 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 1592 // CHECK1-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 1593 // CHECK1-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 2 1594 // CHECK1-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 1 1595 // CHECK1-NEXT: [[CONV6:%.*]] = sext i8 [[TMP3]] to i32 1596 // CHECK1-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 1597 // CHECK1-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i8 1598 // CHECK1-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 1 1599 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 1600 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 1601 // CHECK1-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP4]], 1 1602 // CHECK1-NEXT: store i32 [[ADD9]], i32* [[ARRAYIDX]], align 4 1603 // CHECK1-NEXT: ret void 1604 // 1605 // 1606 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192 1607 // CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 1608 // CHECK1-NEXT: entry: 1609 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1610 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 1611 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 1612 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 1613 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 1614 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 1615 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 1616 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 1617 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 1618 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 1619 // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 1620 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 1621 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* 1622 // CHECK1-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 1623 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 1624 // CHECK1-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 1625 // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 1626 // CHECK1-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 1627 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 1628 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..29 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) 1629 // CHECK1-NEXT: ret void 1630 // 1631 // 1632 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..29 1633 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 1634 // CHECK1-NEXT: entry: 1635 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1636 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1637 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1638 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 1639 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 1640 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1641 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1642 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 1643 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 1644 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 1645 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 1646 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 1647 // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 1648 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 1649 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 1650 // CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 1651 // CHECK1-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 1652 // CHECK1-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 1653 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 1654 // CHECK1-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 1655 // CHECK1-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2 1656 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 1657 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 1658 // CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP3]], 1 1659 // CHECK1-NEXT: store i32 [[ADD5]], i32* [[ARRAYIDX]], align 4 1660 // CHECK1-NEXT: ret void 1661 // 1662 // 1663 // CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 1664 // CHECK1-SAME: () #[[ATTR4]] { 1665 // CHECK1-NEXT: entry: 1666 // CHECK1-NEXT: call void @__tgt_register_requires(i64 1) 1667 // CHECK1-NEXT: ret void 1668 // 1669 // 1670 // CHECK3-LABEL: define {{[^@]+}}@_Z3fooi 1671 // CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0:[0-9]+]] { 1672 // CHECK3-NEXT: entry: 1673 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 1674 // CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4 1675 // CHECK3-NEXT: [[AA:%.*]] = alloca i16, align 2 1676 // CHECK3-NEXT: [[B:%.*]] = alloca [10 x float], align 4 1677 // CHECK3-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 1678 // CHECK3-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 1679 // CHECK3-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 1680 // CHECK3-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 1681 // CHECK3-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 1682 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 1683 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 1684 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 1685 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 1686 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__CASTED3:%.*]] = alloca i32, align 4 1687 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 1688 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 1689 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 1690 // CHECK3-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4 1691 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 1692 // CHECK3-NEXT: [[AA_CASTED4:%.*]] = alloca i32, align 4 1693 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS6:%.*]] = alloca [1 x i8*], align 4 1694 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS7:%.*]] = alloca [1 x i8*], align 4 1695 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS8:%.*]] = alloca [1 x i8*], align 4 1696 // CHECK3-NEXT: [[A_CASTED9:%.*]] = alloca i32, align 4 1697 // CHECK3-NEXT: [[AA_CASTED10:%.*]] = alloca i32, align 4 1698 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS12:%.*]] = alloca [2 x i8*], align 4 1699 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS13:%.*]] = alloca [2 x i8*], align 4 1700 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS14:%.*]] = alloca [2 x i8*], align 4 1701 // CHECK3-NEXT: [[A_CASTED17:%.*]] = alloca i32, align 4 1702 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS20:%.*]] = alloca [9 x i8*], align 4 1703 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS21:%.*]] = alloca [9 x i8*], align 4 1704 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS22:%.*]] = alloca [9 x i8*], align 4 1705 // CHECK3-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [9 x i64], align 4 1706 // CHECK3-NEXT: [[NN:%.*]] = alloca i32, align 4 1707 // CHECK3-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4 1708 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS27:%.*]] = alloca [1 x i8*], align 4 1709 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS28:%.*]] = alloca [1 x i8*], align 4 1710 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS29:%.*]] = alloca [1 x i8*], align 4 1711 // CHECK3-NEXT: [[NN_CASTED32:%.*]] = alloca i32, align 4 1712 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS33:%.*]] = alloca [1 x i8*], align 4 1713 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS34:%.*]] = alloca [1 x i8*], align 4 1714 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS35:%.*]] = alloca [1 x i8*], align 4 1715 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) 1716 // CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 1717 // CHECK3-NEXT: store i32 0, i32* [[A]], align 4 1718 // CHECK3-NEXT: store i16 0, i16* [[AA]], align 2 1719 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 1720 // CHECK3-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() 1721 // CHECK3-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 1722 // CHECK3-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP1]], align 4 1723 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 1724 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 1725 // CHECK3-NEXT: [[TMP4:%.*]] = mul nuw i32 5, [[TMP3]] 1726 // CHECK3-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP4]], align 8 1727 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[__VLA_EXPR1]], align 4 1728 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 1729 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_]], align 4 1730 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 1731 // CHECK3-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_2]], align 4 1732 // CHECK3-NEXT: [[TMP7:%.*]] = load i16, i16* [[AA]], align 2 1733 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 1734 // CHECK3-NEXT: store i16 [[TMP7]], i16* [[CONV]], align 2 1735 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[AA_CASTED]], align 4 1736 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 1737 // CHECK3-NEXT: store i32 [[TMP9]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 1738 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 1739 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 1740 // CHECK3-NEXT: store i32 [[TMP11]], i32* [[DOTCAPTURE_EXPR__CASTED3]], align 4 1741 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED3]], align 4 1742 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1743 // CHECK3-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i32* 1744 // CHECK3-NEXT: store i32 [[TMP8]], i32* [[TMP14]], align 4 1745 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1746 // CHECK3-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i32* 1747 // CHECK3-NEXT: store i32 [[TMP8]], i32* [[TMP16]], align 4 1748 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 1749 // CHECK3-NEXT: store i8* null, i8** [[TMP17]], align 4 1750 // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1751 // CHECK3-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32* 1752 // CHECK3-NEXT: store i32 [[TMP10]], i32* [[TMP19]], align 4 1753 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1754 // CHECK3-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32* 1755 // CHECK3-NEXT: store i32 [[TMP10]], i32* [[TMP21]], align 4 1756 // CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 1757 // CHECK3-NEXT: store i8* null, i8** [[TMP22]], align 4 1758 // CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1759 // CHECK3-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i32* 1760 // CHECK3-NEXT: store i32 [[TMP12]], i32* [[TMP24]], align 4 1761 // CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1762 // CHECK3-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i32* 1763 // CHECK3-NEXT: store i32 [[TMP12]], i32* [[TMP26]], align 4 1764 // CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 1765 // CHECK3-NEXT: store i8* null, i8** [[TMP27]], align 4 1766 // CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1767 // CHECK3-NEXT: [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1768 // CHECK3-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 0 1769 // CHECK3-NEXT: [[TMP31:%.*]] = load i16, i16* [[AA]], align 2 1770 // CHECK3-NEXT: store i16 [[TMP31]], i16* [[TMP30]], align 4 1771 // CHECK3-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 1 1772 // CHECK3-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 1773 // CHECK3-NEXT: store i32 [[TMP33]], i32* [[TMP32]], align 4 1774 // CHECK3-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 2 1775 // CHECK3-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 1776 // CHECK3-NEXT: store i32 [[TMP35]], i32* [[TMP34]], align 4 1777 // CHECK3-NEXT: [[TMP36:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i32 72, i32 12, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1) 1778 // CHECK3-NEXT: [[TMP37:%.*]] = bitcast i8* [[TMP36]] to %struct.kmp_task_t_with_privates* 1779 // CHECK3-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP37]], i32 0, i32 0 1780 // CHECK3-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP38]], i32 0, i32 0 1781 // CHECK3-NEXT: [[TMP40:%.*]] = load i8*, i8** [[TMP39]], align 4 1782 // CHECK3-NEXT: [[TMP41:%.*]] = bitcast %struct.anon* [[AGG_CAPTURED]] to i8* 1783 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP40]], i8* align 4 [[TMP41]], i32 12, i1 false) 1784 // CHECK3-NEXT: [[TMP42:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP37]], i32 0, i32 1 1785 // CHECK3-NEXT: [[TMP43:%.*]] = bitcast i8* [[TMP40]] to %struct.anon* 1786 // CHECK3-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 0 1787 // CHECK3-NEXT: [[TMP45:%.*]] = bitcast [3 x i64]* [[TMP44]] to i8* 1788 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP45]], i8* align 4 bitcast ([3 x i64]* @.offload_sizes to i8*), i32 24, i1 false) 1789 // CHECK3-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 1 1790 // CHECK3-NEXT: [[TMP47:%.*]] = bitcast [3 x i8*]* [[TMP46]] to i8* 1791 // CHECK3-NEXT: [[TMP48:%.*]] = bitcast i8** [[TMP28]] to i8* 1792 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP47]], i8* align 4 [[TMP48]], i32 12, i1 false) 1793 // CHECK3-NEXT: [[TMP49:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 2 1794 // CHECK3-NEXT: [[TMP50:%.*]] = bitcast [3 x i8*]* [[TMP49]] to i8* 1795 // CHECK3-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP29]] to i8* 1796 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP50]], i8* align 4 [[TMP51]], i32 12, i1 false) 1797 // CHECK3-NEXT: [[TMP52:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 3 1798 // CHECK3-NEXT: [[TMP53:%.*]] = load i16, i16* [[AA]], align 2 1799 // CHECK3-NEXT: store i16 [[TMP53]], i16* [[TMP52]], align 4 1800 // CHECK3-NEXT: [[TMP54:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP36]]) 1801 // CHECK3-NEXT: [[TMP55:%.*]] = load i32, i32* [[A]], align 4 1802 // CHECK3-NEXT: store i32 [[TMP55]], i32* [[A_CASTED]], align 4 1803 // CHECK3-NEXT: [[TMP56:%.*]] = load i32, i32* [[A_CASTED]], align 4 1804 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l105(i32 [[TMP56]]) #[[ATTR3:[0-9]+]] 1805 // CHECK3-NEXT: [[TMP57:%.*]] = load i16, i16* [[AA]], align 2 1806 // CHECK3-NEXT: [[CONV5:%.*]] = bitcast i32* [[AA_CASTED4]] to i16* 1807 // CHECK3-NEXT: store i16 [[TMP57]], i16* [[CONV5]], align 2 1808 // CHECK3-NEXT: [[TMP58:%.*]] = load i32, i32* [[AA_CASTED4]], align 4 1809 // CHECK3-NEXT: [[TMP59:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0 1810 // CHECK3-NEXT: [[TMP60:%.*]] = bitcast i8** [[TMP59]] to i32* 1811 // CHECK3-NEXT: store i32 [[TMP58]], i32* [[TMP60]], align 4 1812 // CHECK3-NEXT: [[TMP61:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0 1813 // CHECK3-NEXT: [[TMP62:%.*]] = bitcast i8** [[TMP61]] to i32* 1814 // CHECK3-NEXT: store i32 [[TMP58]], i32* [[TMP62]], align 4 1815 // CHECK3-NEXT: [[TMP63:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS8]], i32 0, i32 0 1816 // CHECK3-NEXT: store i8* null, i8** [[TMP63]], align 4 1817 // CHECK3-NEXT: [[TMP64:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0 1818 // CHECK3-NEXT: [[TMP65:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0 1819 // CHECK3-NEXT: [[TMP66:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.region_id, i32 1, i8** [[TMP64]], i8** [[TMP65]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.4, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.5, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 1820 // CHECK3-NEXT: [[TMP67:%.*]] = icmp ne i32 [[TMP66]], 0 1821 // CHECK3-NEXT: br i1 [[TMP67]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1822 // CHECK3: omp_offload.failed: 1823 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111(i32 [[TMP58]]) #[[ATTR3]] 1824 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 1825 // CHECK3: omp_offload.cont: 1826 // CHECK3-NEXT: [[TMP68:%.*]] = load i32, i32* [[A]], align 4 1827 // CHECK3-NEXT: store i32 [[TMP68]], i32* [[A_CASTED9]], align 4 1828 // CHECK3-NEXT: [[TMP69:%.*]] = load i32, i32* [[A_CASTED9]], align 4 1829 // CHECK3-NEXT: [[TMP70:%.*]] = load i16, i16* [[AA]], align 2 1830 // CHECK3-NEXT: [[CONV11:%.*]] = bitcast i32* [[AA_CASTED10]] to i16* 1831 // CHECK3-NEXT: store i16 [[TMP70]], i16* [[CONV11]], align 2 1832 // CHECK3-NEXT: [[TMP71:%.*]] = load i32, i32* [[AA_CASTED10]], align 4 1833 // CHECK3-NEXT: [[TMP72:%.*]] = load i32, i32* [[N_ADDR]], align 4 1834 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP72]], 10 1835 // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 1836 // CHECK3: omp_if.then: 1837 // CHECK3-NEXT: [[TMP73:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS12]], i32 0, i32 0 1838 // CHECK3-NEXT: [[TMP74:%.*]] = bitcast i8** [[TMP73]] to i32* 1839 // CHECK3-NEXT: store i32 [[TMP69]], i32* [[TMP74]], align 4 1840 // CHECK3-NEXT: [[TMP75:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS13]], i32 0, i32 0 1841 // CHECK3-NEXT: [[TMP76:%.*]] = bitcast i8** [[TMP75]] to i32* 1842 // CHECK3-NEXT: store i32 [[TMP69]], i32* [[TMP76]], align 4 1843 // CHECK3-NEXT: [[TMP77:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS14]], i32 0, i32 0 1844 // CHECK3-NEXT: store i8* null, i8** [[TMP77]], align 4 1845 // CHECK3-NEXT: [[TMP78:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS12]], i32 0, i32 1 1846 // CHECK3-NEXT: [[TMP79:%.*]] = bitcast i8** [[TMP78]] to i32* 1847 // CHECK3-NEXT: store i32 [[TMP71]], i32* [[TMP79]], align 4 1848 // CHECK3-NEXT: [[TMP80:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS13]], i32 0, i32 1 1849 // CHECK3-NEXT: [[TMP81:%.*]] = bitcast i8** [[TMP80]] to i32* 1850 // CHECK3-NEXT: store i32 [[TMP71]], i32* [[TMP81]], align 4 1851 // CHECK3-NEXT: [[TMP82:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS14]], i32 0, i32 1 1852 // CHECK3-NEXT: store i8* null, i8** [[TMP82]], align 4 1853 // CHECK3-NEXT: [[TMP83:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS12]], i32 0, i32 0 1854 // CHECK3-NEXT: [[TMP84:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS13]], i32 0, i32 0 1855 // CHECK3-NEXT: [[TMP85:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.region_id, i32 2, i8** [[TMP83]], i8** [[TMP84]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.7, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.8, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 1856 // CHECK3-NEXT: [[TMP86:%.*]] = icmp ne i32 [[TMP85]], 0 1857 // CHECK3-NEXT: br i1 [[TMP86]], label [[OMP_OFFLOAD_FAILED15:%.*]], label [[OMP_OFFLOAD_CONT16:%.*]] 1858 // CHECK3: omp_offload.failed15: 1859 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i32 [[TMP69]], i32 [[TMP71]]) #[[ATTR3]] 1860 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT16]] 1861 // CHECK3: omp_offload.cont16: 1862 // CHECK3-NEXT: br label [[OMP_IF_END:%.*]] 1863 // CHECK3: omp_if.else: 1864 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i32 [[TMP69]], i32 [[TMP71]]) #[[ATTR3]] 1865 // CHECK3-NEXT: br label [[OMP_IF_END]] 1866 // CHECK3: omp_if.end: 1867 // CHECK3-NEXT: [[TMP87:%.*]] = load i32, i32* [[A]], align 4 1868 // CHECK3-NEXT: store i32 [[TMP87]], i32* [[A_CASTED17]], align 4 1869 // CHECK3-NEXT: [[TMP88:%.*]] = load i32, i32* [[A_CASTED17]], align 4 1870 // CHECK3-NEXT: [[TMP89:%.*]] = load i32, i32* [[N_ADDR]], align 4 1871 // CHECK3-NEXT: [[CMP18:%.*]] = icmp sgt i32 [[TMP89]], 20 1872 // CHECK3-NEXT: br i1 [[CMP18]], label [[OMP_IF_THEN19:%.*]], label [[OMP_IF_ELSE25:%.*]] 1873 // CHECK3: omp_if.then19: 1874 // CHECK3-NEXT: [[TMP90:%.*]] = mul nuw i32 [[TMP1]], 4 1875 // CHECK3-NEXT: [[TMP91:%.*]] = sext i32 [[TMP90]] to i64 1876 // CHECK3-NEXT: [[TMP92:%.*]] = mul nuw i32 5, [[TMP3]] 1877 // CHECK3-NEXT: [[TMP93:%.*]] = mul nuw i32 [[TMP92]], 8 1878 // CHECK3-NEXT: [[TMP94:%.*]] = sext i32 [[TMP93]] to i64 1879 // CHECK3-NEXT: [[TMP95:%.*]] = bitcast [9 x i64]* [[DOTOFFLOAD_SIZES]] to i8* 1880 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP95]], i8* align 4 bitcast ([9 x i64]* @.offload_sizes.10 to i8*), i32 72, i1 false) 1881 // CHECK3-NEXT: [[TMP96:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0 1882 // CHECK3-NEXT: [[TMP97:%.*]] = bitcast i8** [[TMP96]] to i32* 1883 // CHECK3-NEXT: store i32 [[TMP88]], i32* [[TMP97]], align 4 1884 // CHECK3-NEXT: [[TMP98:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 0 1885 // CHECK3-NEXT: [[TMP99:%.*]] = bitcast i8** [[TMP98]] to i32* 1886 // CHECK3-NEXT: store i32 [[TMP88]], i32* [[TMP99]], align 4 1887 // CHECK3-NEXT: [[TMP100:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 0 1888 // CHECK3-NEXT: store i8* null, i8** [[TMP100]], align 4 1889 // CHECK3-NEXT: [[TMP101:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 1 1890 // CHECK3-NEXT: [[TMP102:%.*]] = bitcast i8** [[TMP101]] to [10 x float]** 1891 // CHECK3-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP102]], align 4 1892 // CHECK3-NEXT: [[TMP103:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 1 1893 // CHECK3-NEXT: [[TMP104:%.*]] = bitcast i8** [[TMP103]] to [10 x float]** 1894 // CHECK3-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP104]], align 4 1895 // CHECK3-NEXT: [[TMP105:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 1 1896 // CHECK3-NEXT: store i8* null, i8** [[TMP105]], align 4 1897 // CHECK3-NEXT: [[TMP106:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 2 1898 // CHECK3-NEXT: [[TMP107:%.*]] = bitcast i8** [[TMP106]] to i32* 1899 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP107]], align 4 1900 // CHECK3-NEXT: [[TMP108:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 2 1901 // CHECK3-NEXT: [[TMP109:%.*]] = bitcast i8** [[TMP108]] to i32* 1902 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP109]], align 4 1903 // CHECK3-NEXT: [[TMP110:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 2 1904 // CHECK3-NEXT: store i8* null, i8** [[TMP110]], align 4 1905 // CHECK3-NEXT: [[TMP111:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 3 1906 // CHECK3-NEXT: [[TMP112:%.*]] = bitcast i8** [[TMP111]] to float** 1907 // CHECK3-NEXT: store float* [[VLA]], float** [[TMP112]], align 4 1908 // CHECK3-NEXT: [[TMP113:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 3 1909 // CHECK3-NEXT: [[TMP114:%.*]] = bitcast i8** [[TMP113]] to float** 1910 // CHECK3-NEXT: store float* [[VLA]], float** [[TMP114]], align 4 1911 // CHECK3-NEXT: [[TMP115:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 1912 // CHECK3-NEXT: store i64 [[TMP91]], i64* [[TMP115]], align 4 1913 // CHECK3-NEXT: [[TMP116:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 3 1914 // CHECK3-NEXT: store i8* null, i8** [[TMP116]], align 4 1915 // CHECK3-NEXT: [[TMP117:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 4 1916 // CHECK3-NEXT: [[TMP118:%.*]] = bitcast i8** [[TMP117]] to [5 x [10 x double]]** 1917 // CHECK3-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP118]], align 4 1918 // CHECK3-NEXT: [[TMP119:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 4 1919 // CHECK3-NEXT: [[TMP120:%.*]] = bitcast i8** [[TMP119]] to [5 x [10 x double]]** 1920 // CHECK3-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP120]], align 4 1921 // CHECK3-NEXT: [[TMP121:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 4 1922 // CHECK3-NEXT: store i8* null, i8** [[TMP121]], align 4 1923 // CHECK3-NEXT: [[TMP122:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 5 1924 // CHECK3-NEXT: [[TMP123:%.*]] = bitcast i8** [[TMP122]] to i32* 1925 // CHECK3-NEXT: store i32 5, i32* [[TMP123]], align 4 1926 // CHECK3-NEXT: [[TMP124:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 5 1927 // CHECK3-NEXT: [[TMP125:%.*]] = bitcast i8** [[TMP124]] to i32* 1928 // CHECK3-NEXT: store i32 5, i32* [[TMP125]], align 4 1929 // CHECK3-NEXT: [[TMP126:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 5 1930 // CHECK3-NEXT: store i8* null, i8** [[TMP126]], align 4 1931 // CHECK3-NEXT: [[TMP127:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 6 1932 // CHECK3-NEXT: [[TMP128:%.*]] = bitcast i8** [[TMP127]] to i32* 1933 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP128]], align 4 1934 // CHECK3-NEXT: [[TMP129:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 6 1935 // CHECK3-NEXT: [[TMP130:%.*]] = bitcast i8** [[TMP129]] to i32* 1936 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP130]], align 4 1937 // CHECK3-NEXT: [[TMP131:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 6 1938 // CHECK3-NEXT: store i8* null, i8** [[TMP131]], align 4 1939 // CHECK3-NEXT: [[TMP132:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 7 1940 // CHECK3-NEXT: [[TMP133:%.*]] = bitcast i8** [[TMP132]] to double** 1941 // CHECK3-NEXT: store double* [[VLA1]], double** [[TMP133]], align 4 1942 // CHECK3-NEXT: [[TMP134:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 7 1943 // CHECK3-NEXT: [[TMP135:%.*]] = bitcast i8** [[TMP134]] to double** 1944 // CHECK3-NEXT: store double* [[VLA1]], double** [[TMP135]], align 4 1945 // CHECK3-NEXT: [[TMP136:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 1946 // CHECK3-NEXT: store i64 [[TMP94]], i64* [[TMP136]], align 4 1947 // CHECK3-NEXT: [[TMP137:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 7 1948 // CHECK3-NEXT: store i8* null, i8** [[TMP137]], align 4 1949 // CHECK3-NEXT: [[TMP138:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 8 1950 // CHECK3-NEXT: [[TMP139:%.*]] = bitcast i8** [[TMP138]] to %struct.TT** 1951 // CHECK3-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP139]], align 4 1952 // CHECK3-NEXT: [[TMP140:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 8 1953 // CHECK3-NEXT: [[TMP141:%.*]] = bitcast i8** [[TMP140]] to %struct.TT** 1954 // CHECK3-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP141]], align 4 1955 // CHECK3-NEXT: [[TMP142:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 8 1956 // CHECK3-NEXT: store i8* null, i8** [[TMP142]], align 4 1957 // CHECK3-NEXT: [[TMP143:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0 1958 // CHECK3-NEXT: [[TMP144:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 0 1959 // CHECK3-NEXT: [[TMP145:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 1960 // CHECK3-NEXT: [[TMP146:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142.region_id, i32 9, i8** [[TMP143]], i8** [[TMP144]], i64* [[TMP145]], i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_maptypes.11, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 1961 // CHECK3-NEXT: [[TMP147:%.*]] = icmp ne i32 [[TMP146]], 0 1962 // CHECK3-NEXT: br i1 [[TMP147]], label [[OMP_OFFLOAD_FAILED23:%.*]], label [[OMP_OFFLOAD_CONT24:%.*]] 1963 // CHECK3: omp_offload.failed23: 1964 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i32 [[TMP88]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR3]] 1965 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT24]] 1966 // CHECK3: omp_offload.cont24: 1967 // CHECK3-NEXT: br label [[OMP_IF_END26:%.*]] 1968 // CHECK3: omp_if.else25: 1969 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i32 [[TMP88]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR3]] 1970 // CHECK3-NEXT: br label [[OMP_IF_END26]] 1971 // CHECK3: omp_if.end26: 1972 // CHECK3-NEXT: store i32 0, i32* [[NN]], align 4 1973 // CHECK3-NEXT: [[TMP148:%.*]] = load i32, i32* [[NN]], align 4 1974 // CHECK3-NEXT: store i32 [[TMP148]], i32* [[NN_CASTED]], align 4 1975 // CHECK3-NEXT: [[TMP149:%.*]] = load i32, i32* [[NN_CASTED]], align 4 1976 // CHECK3-NEXT: [[TMP150:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS27]], i32 0, i32 0 1977 // CHECK3-NEXT: [[TMP151:%.*]] = bitcast i8** [[TMP150]] to i32* 1978 // CHECK3-NEXT: store i32 [[TMP149]], i32* [[TMP151]], align 4 1979 // CHECK3-NEXT: [[TMP152:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS28]], i32 0, i32 0 1980 // CHECK3-NEXT: [[TMP153:%.*]] = bitcast i8** [[TMP152]] to i32* 1981 // CHECK3-NEXT: store i32 [[TMP149]], i32* [[TMP153]], align 4 1982 // CHECK3-NEXT: [[TMP154:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS29]], i32 0, i32 0 1983 // CHECK3-NEXT: store i8* null, i8** [[TMP154]], align 4 1984 // CHECK3-NEXT: [[TMP155:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS27]], i32 0, i32 0 1985 // CHECK3-NEXT: [[TMP156:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS28]], i32 0, i32 0 1986 // CHECK3-NEXT: [[TMP157:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154.region_id, i32 1, i8** [[TMP155]], i8** [[TMP156]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.14, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.15, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 1987 // CHECK3-NEXT: [[TMP158:%.*]] = icmp ne i32 [[TMP157]], 0 1988 // CHECK3-NEXT: br i1 [[TMP158]], label [[OMP_OFFLOAD_FAILED30:%.*]], label [[OMP_OFFLOAD_CONT31:%.*]] 1989 // CHECK3: omp_offload.failed30: 1990 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154(i32 [[TMP149]]) #[[ATTR3]] 1991 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT31]] 1992 // CHECK3: omp_offload.cont31: 1993 // CHECK3-NEXT: [[TMP159:%.*]] = load i32, i32* [[NN]], align 4 1994 // CHECK3-NEXT: store i32 [[TMP159]], i32* [[NN_CASTED32]], align 4 1995 // CHECK3-NEXT: [[TMP160:%.*]] = load i32, i32* [[NN_CASTED32]], align 4 1996 // CHECK3-NEXT: [[TMP161:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS33]], i32 0, i32 0 1997 // CHECK3-NEXT: [[TMP162:%.*]] = bitcast i8** [[TMP161]] to i32* 1998 // CHECK3-NEXT: store i32 [[TMP160]], i32* [[TMP162]], align 4 1999 // CHECK3-NEXT: [[TMP163:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS34]], i32 0, i32 0 2000 // CHECK3-NEXT: [[TMP164:%.*]] = bitcast i8** [[TMP163]] to i32* 2001 // CHECK3-NEXT: store i32 [[TMP160]], i32* [[TMP164]], align 4 2002 // CHECK3-NEXT: [[TMP165:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS35]], i32 0, i32 0 2003 // CHECK3-NEXT: store i8* null, i8** [[TMP165]], align 4 2004 // CHECK3-NEXT: [[TMP166:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS33]], i32 0, i32 0 2005 // CHECK3-NEXT: [[TMP167:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS34]], i32 0, i32 0 2006 // CHECK3-NEXT: [[TMP168:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157.region_id, i32 1, i8** [[TMP166]], i8** [[TMP167]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.18, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.19, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 2007 // CHECK3-NEXT: [[TMP169:%.*]] = icmp ne i32 [[TMP168]], 0 2008 // CHECK3-NEXT: br i1 [[TMP169]], label [[OMP_OFFLOAD_FAILED36:%.*]], label [[OMP_OFFLOAD_CONT37:%.*]] 2009 // CHECK3: omp_offload.failed36: 2010 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157(i32 [[TMP160]]) #[[ATTR3]] 2011 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT37]] 2012 // CHECK3: omp_offload.cont37: 2013 // CHECK3-NEXT: [[TMP170:%.*]] = load i32, i32* [[A]], align 4 2014 // CHECK3-NEXT: [[TMP171:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 2015 // CHECK3-NEXT: call void @llvm.stackrestore(i8* [[TMP171]]) 2016 // CHECK3-NEXT: ret i32 [[TMP170]] 2017 // 2018 // 2019 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101 2020 // CHECK3-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]], i32 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] { 2021 // CHECK3-NEXT: entry: 2022 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 2023 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 2024 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4 2025 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 2026 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 2027 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 2028 // CHECK3-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 2029 // CHECK3-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 2030 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 2031 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 2032 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 2033 // CHECK3-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) 2034 // CHECK3-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 2035 // CHECK3-NEXT: [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 2036 // CHECK3-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 2037 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 2038 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]]) 2039 // CHECK3-NEXT: ret void 2040 // 2041 // 2042 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. 2043 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { 2044 // CHECK3-NEXT: entry: 2045 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2046 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2047 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 2048 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2049 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2050 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 2051 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 2052 // CHECK3-NEXT: ret void 2053 // 2054 // 2055 // CHECK3-LABEL: define {{[^@]+}}@.omp_task_privates_map. 2056 // CHECK3-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], i16** noalias noundef [[TMP1:%.*]], [3 x i8*]** noalias noundef [[TMP2:%.*]], [3 x i8*]** noalias noundef [[TMP3:%.*]], [3 x i64]** noalias noundef [[TMP4:%.*]]) #[[ATTR4:[0-9]+]] { 2057 // CHECK3-NEXT: entry: 2058 // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 4 2059 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i16**, align 4 2060 // CHECK3-NEXT: [[DOTADDR2:%.*]] = alloca [3 x i8*]**, align 4 2061 // CHECK3-NEXT: [[DOTADDR3:%.*]] = alloca [3 x i8*]**, align 4 2062 // CHECK3-NEXT: [[DOTADDR4:%.*]] = alloca [3 x i64]**, align 4 2063 // CHECK3-NEXT: store %struct..kmp_privates.t* [[TMP0]], %struct..kmp_privates.t** [[DOTADDR]], align 4 2064 // CHECK3-NEXT: store i16** [[TMP1]], i16*** [[DOTADDR1]], align 4 2065 // CHECK3-NEXT: store [3 x i8*]** [[TMP2]], [3 x i8*]*** [[DOTADDR2]], align 4 2066 // CHECK3-NEXT: store [3 x i8*]** [[TMP3]], [3 x i8*]*** [[DOTADDR3]], align 4 2067 // CHECK3-NEXT: store [3 x i64]** [[TMP4]], [3 x i64]*** [[DOTADDR4]], align 4 2068 // CHECK3-NEXT: [[TMP5:%.*]] = load %struct..kmp_privates.t*, %struct..kmp_privates.t** [[DOTADDR]], align 4 2069 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 0 2070 // CHECK3-NEXT: [[TMP7:%.*]] = load [3 x i64]**, [3 x i64]*** [[DOTADDR4]], align 4 2071 // CHECK3-NEXT: store [3 x i64]* [[TMP6]], [3 x i64]** [[TMP7]], align 4 2072 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 1 2073 // CHECK3-NEXT: [[TMP9:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR2]], align 4 2074 // CHECK3-NEXT: store [3 x i8*]* [[TMP8]], [3 x i8*]** [[TMP9]], align 4 2075 // CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 2 2076 // CHECK3-NEXT: [[TMP11:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR3]], align 4 2077 // CHECK3-NEXT: store [3 x i8*]* [[TMP10]], [3 x i8*]** [[TMP11]], align 4 2078 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 3 2079 // CHECK3-NEXT: [[TMP13:%.*]] = load i16**, i16*** [[DOTADDR1]], align 4 2080 // CHECK3-NEXT: store i16* [[TMP12]], i16** [[TMP13]], align 4 2081 // CHECK3-NEXT: ret void 2082 // 2083 // 2084 // CHECK3-LABEL: define {{[^@]+}}@.omp_task_entry. 2085 // CHECK3-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { 2086 // CHECK3-NEXT: entry: 2087 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 2088 // CHECK3-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 4 2089 // CHECK3-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 4 2090 // CHECK3-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 4 2091 // CHECK3-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 4 2092 // CHECK3-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 4 2093 // CHECK3-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca i16*, align 4 2094 // CHECK3-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca [3 x i8*]*, align 4 2095 // CHECK3-NEXT: [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca [3 x i8*]*, align 4 2096 // CHECK3-NEXT: [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca [3 x i64]*, align 4 2097 // CHECK3-NEXT: [[AA_CASTED_I:%.*]] = alloca i32, align 4 2098 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__CASTED_I:%.*]] = alloca i32, align 4 2099 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__CASTED4_I:%.*]] = alloca i32, align 4 2100 // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 2101 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 4 2102 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 2103 // CHECK3-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4 2104 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 2105 // CHECK3-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4 2106 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0 2107 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 2108 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 2109 // CHECK3-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 4 2110 // CHECK3-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon* 2111 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1 2112 // CHECK3-NEXT: [[TMP10:%.*]] = bitcast %struct..kmp_privates.t* [[TMP9]] to i8* 2113 // CHECK3-NEXT: [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8* 2114 // CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META16:![0-9]+]]) 2115 // CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]]) 2116 // CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META21:![0-9]+]]) 2117 // CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META23:![0-9]+]]) 2118 // CHECK3-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !25 2119 // CHECK3-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 4, !noalias !25 2120 // CHECK3-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !25 2121 // CHECK3-NEXT: store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* @.omp_task_privates_map. to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !25 2122 // CHECK3-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 4, !noalias !25 2123 // CHECK3-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !25 2124 // CHECK3-NEXT: [[TMP12:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !25 2125 // CHECK3-NEXT: [[TMP13:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !25 2126 // CHECK3-NEXT: [[TMP14:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !25 2127 // CHECK3-NEXT: [[TMP15:%.*]] = bitcast void (i8*, ...)* [[TMP13]] to void (i8*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* 2128 // CHECK3-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]] 2129 // CHECK3-NEXT: [[TMP16:%.*]] = load i16*, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 4, !noalias !25 2130 // CHECK3-NEXT: [[TMP17:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 4, !noalias !25 2131 // CHECK3-NEXT: [[TMP18:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 4, !noalias !25 2132 // CHECK3-NEXT: [[TMP19:%.*]] = load [3 x i64]*, [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 4, !noalias !25 2133 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP17]], i32 0, i32 0 2134 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP18]], i32 0, i32 0 2135 // CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[TMP19]], i32 0, i32 0 2136 // CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP12]], i32 0, i32 1 2137 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[TMP12]], i32 0, i32 2 2138 // CHECK3-NEXT: [[TMP25:%.*]] = load i32, i32* [[TMP23]], align 4 2139 // CHECK3-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP24]], align 4 2140 // CHECK3-NEXT: [[TMP27:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 [[TMP25]], i32 [[TMP26]], i32 0, i8* null, i32 0, i8* null) #[[ATTR3]] 2141 // CHECK3-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0 2142 // CHECK3-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]] 2143 // CHECK3: omp_offload.failed.i: 2144 // CHECK3-NEXT: [[TMP29:%.*]] = load i16, i16* [[TMP16]], align 2 2145 // CHECK3-NEXT: [[CONV_I:%.*]] = bitcast i32* [[AA_CASTED_I]] to i16* 2146 // CHECK3-NEXT: store i16 [[TMP29]], i16* [[CONV_I]], align 2, !noalias !25 2147 // CHECK3-NEXT: [[TMP30:%.*]] = load i32, i32* [[AA_CASTED_I]], align 4, !noalias !25 2148 // CHECK3-NEXT: [[TMP31:%.*]] = load i32, i32* [[TMP23]], align 4 2149 // CHECK3-NEXT: store i32 [[TMP31]], i32* [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias !25 2150 // CHECK3-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias !25 2151 // CHECK3-NEXT: [[TMP33:%.*]] = load i32, i32* [[TMP24]], align 4 2152 // CHECK3-NEXT: store i32 [[TMP33]], i32* [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias !25 2153 // CHECK3-NEXT: [[TMP34:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias !25 2154 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101(i32 [[TMP30]], i32 [[TMP32]], i32 [[TMP34]]) #[[ATTR3]] 2155 // CHECK3-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]] 2156 // CHECK3: .omp_outlined..1.exit: 2157 // CHECK3-NEXT: ret i32 0 2158 // 2159 // 2160 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l105 2161 // CHECK3-SAME: (i32 noundef [[A:%.*]]) #[[ATTR2]] { 2162 // CHECK3-NEXT: entry: 2163 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2164 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 2165 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 2166 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 2167 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 2168 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 2169 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]]) 2170 // CHECK3-NEXT: ret void 2171 // 2172 // 2173 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..2 2174 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]]) #[[ATTR2]] { 2175 // CHECK3-NEXT: entry: 2176 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2177 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2178 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2179 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2180 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2181 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 2182 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 2183 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 2184 // CHECK3-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 2185 // CHECK3-NEXT: ret void 2186 // 2187 // 2188 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 2189 // CHECK3-SAME: (i32 noundef [[AA:%.*]]) #[[ATTR2]] { 2190 // CHECK3-NEXT: entry: 2191 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 2192 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 2193 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 2194 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 2195 // CHECK3-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 2196 // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 2197 // CHECK3-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 2198 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 2199 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP1]]) 2200 // CHECK3-NEXT: ret void 2201 // 2202 // 2203 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..3 2204 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { 2205 // CHECK3-NEXT: entry: 2206 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2207 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2208 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 2209 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2210 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2211 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 2212 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 2213 // CHECK3-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 2214 // CHECK3-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 2215 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 2216 // CHECK3-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 2217 // CHECK3-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2 2218 // CHECK3-NEXT: ret void 2219 // 2220 // 2221 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118 2222 // CHECK3-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { 2223 // CHECK3-NEXT: entry: 2224 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2225 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 2226 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 2227 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 2228 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 2229 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 2230 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 2231 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 2232 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 2233 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 2234 // CHECK3-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 2235 // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 2236 // CHECK3-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 2237 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 2238 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) 2239 // CHECK3-NEXT: ret void 2240 // 2241 // 2242 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..6 2243 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { 2244 // CHECK3-NEXT: entry: 2245 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2246 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2247 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2248 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 2249 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2250 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2251 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 2252 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 2253 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 2254 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 2255 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 2256 // CHECK3-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 2257 // CHECK3-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 2 2258 // CHECK3-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32 2259 // CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 2260 // CHECK3-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 2261 // CHECK3-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2 2262 // CHECK3-NEXT: ret void 2263 // 2264 // 2265 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142 2266 // CHECK3-SAME: (i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] { 2267 // CHECK3-NEXT: entry: 2268 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2269 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 2270 // CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 2271 // CHECK3-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 2272 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 2273 // CHECK3-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 2274 // CHECK3-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 2275 // CHECK3-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 2276 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 2277 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 2278 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 2279 // CHECK3-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 2280 // CHECK3-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 2281 // CHECK3-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 2282 // CHECK3-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 2283 // CHECK3-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 2284 // CHECK3-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 2285 // CHECK3-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 2286 // CHECK3-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 2287 // CHECK3-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 2288 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 2289 // CHECK3-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 2290 // CHECK3-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 2291 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 2292 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 2293 // CHECK3-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 2294 // CHECK3-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 2295 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 2296 // CHECK3-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4 2297 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4 2298 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) 2299 // CHECK3-NEXT: ret void 2300 // 2301 // 2302 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..9 2303 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] { 2304 // CHECK3-NEXT: entry: 2305 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2306 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2307 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2308 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 2309 // CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 2310 // CHECK3-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 2311 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 2312 // CHECK3-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 2313 // CHECK3-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 2314 // CHECK3-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 2315 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 2316 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2317 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2318 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 2319 // CHECK3-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 2320 // CHECK3-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 2321 // CHECK3-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 2322 // CHECK3-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 2323 // CHECK3-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 2324 // CHECK3-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 2325 // CHECK3-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 2326 // CHECK3-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 2327 // CHECK3-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 2328 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 2329 // CHECK3-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 2330 // CHECK3-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 2331 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 2332 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 2333 // CHECK3-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 2334 // CHECK3-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 2335 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 2336 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 2337 // CHECK3-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 2338 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2 2339 // CHECK3-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 2340 // CHECK3-NEXT: [[CONV:%.*]] = fpext float [[TMP9]] to double 2341 // CHECK3-NEXT: [[ADD5:%.*]] = fadd double [[CONV]], 1.000000e+00 2342 // CHECK3-NEXT: [[CONV6:%.*]] = fptrunc double [[ADD5]] to float 2343 // CHECK3-NEXT: store float [[CONV6]], float* [[ARRAYIDX]], align 4 2344 // CHECK3-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3 2345 // CHECK3-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX7]], align 4 2346 // CHECK3-NEXT: [[CONV8:%.*]] = fpext float [[TMP10]] to double 2347 // CHECK3-NEXT: [[ADD9:%.*]] = fadd double [[CONV8]], 1.000000e+00 2348 // CHECK3-NEXT: [[CONV10:%.*]] = fptrunc double [[ADD9]] to float 2349 // CHECK3-NEXT: store float [[CONV10]], float* [[ARRAYIDX7]], align 4 2350 // CHECK3-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1 2351 // CHECK3-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX11]], i32 0, i32 2 2352 // CHECK3-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX12]], align 8 2353 // CHECK3-NEXT: [[ADD13:%.*]] = fadd double [[TMP11]], 1.000000e+00 2354 // CHECK3-NEXT: store double [[ADD13]], double* [[ARRAYIDX12]], align 8 2355 // CHECK3-NEXT: [[TMP12:%.*]] = mul nsw i32 1, [[TMP5]] 2356 // CHECK3-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP12]] 2357 // CHECK3-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX14]], i32 3 2358 // CHECK3-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX15]], align 8 2359 // CHECK3-NEXT: [[ADD16:%.*]] = fadd double [[TMP13]], 1.000000e+00 2360 // CHECK3-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8 2361 // CHECK3-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 2362 // CHECK3-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 4 2363 // CHECK3-NEXT: [[ADD17:%.*]] = add nsw i64 [[TMP14]], 1 2364 // CHECK3-NEXT: store i64 [[ADD17]], i64* [[X]], align 4 2365 // CHECK3-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 2366 // CHECK3-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 4 2367 // CHECK3-NEXT: [[CONV18:%.*]] = sext i8 [[TMP15]] to i32 2368 // CHECK3-NEXT: [[ADD19:%.*]] = add nsw i32 [[CONV18]], 1 2369 // CHECK3-NEXT: [[CONV20:%.*]] = trunc i32 [[ADD19]] to i8 2370 // CHECK3-NEXT: store i8 [[CONV20]], i8* [[Y]], align 4 2371 // CHECK3-NEXT: ret void 2372 // 2373 // 2374 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154 2375 // CHECK3-SAME: (i32 noundef [[NN:%.*]]) #[[ATTR2]] { 2376 // CHECK3-NEXT: entry: 2377 // CHECK3-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 2378 // CHECK3-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4 2379 // CHECK3-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 2380 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[NN_ADDR]], align 4 2381 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[NN_CASTED]], align 4 2382 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[NN_CASTED]], align 4 2383 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..12 to void (i32*, i32*, ...)*), i32 [[TMP1]]) 2384 // CHECK3-NEXT: ret void 2385 // 2386 // 2387 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..12 2388 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[NN:%.*]]) #[[ATTR2]] { 2389 // CHECK3-NEXT: entry: 2390 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2391 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2392 // CHECK3-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 2393 // CHECK3-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4 2394 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2395 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2396 // CHECK3-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 2397 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[NN_ADDR]], align 4 2398 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[NN_CASTED]], align 4 2399 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[NN_CASTED]], align 4 2400 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..13 to void (i32*, i32*, ...)*), i32 [[TMP1]]) 2401 // CHECK3-NEXT: ret void 2402 // 2403 // 2404 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..13 2405 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[NN:%.*]]) #[[ATTR2]] { 2406 // CHECK3-NEXT: entry: 2407 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2408 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2409 // CHECK3-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 2410 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2411 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2412 // CHECK3-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 2413 // CHECK3-NEXT: ret void 2414 // 2415 // 2416 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157 2417 // CHECK3-SAME: (i32 noundef [[NN:%.*]]) #[[ATTR2]] { 2418 // CHECK3-NEXT: entry: 2419 // CHECK3-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 2420 // CHECK3-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4 2421 // CHECK3-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 2422 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[NN_ADDR]], align 4 2423 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[NN_CASTED]], align 4 2424 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[NN_CASTED]], align 4 2425 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i32 [[TMP1]]) 2426 // CHECK3-NEXT: ret void 2427 // 2428 // 2429 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..16 2430 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[NN:%.*]]) #[[ATTR2]] { 2431 // CHECK3-NEXT: entry: 2432 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2433 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2434 // CHECK3-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 2435 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2436 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2437 // CHECK3-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 2438 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..17 to void (i32*, i32*, ...)*), i32* [[NN_ADDR]]) 2439 // CHECK3-NEXT: ret void 2440 // 2441 // 2442 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..17 2443 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[NN:%.*]]) #[[ATTR2]] { 2444 // CHECK3-NEXT: entry: 2445 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2446 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2447 // CHECK3-NEXT: [[NN_ADDR:%.*]] = alloca i32*, align 4 2448 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2449 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2450 // CHECK3-NEXT: store i32* [[NN]], i32** [[NN_ADDR]], align 4 2451 // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[NN_ADDR]], align 4 2452 // CHECK3-NEXT: ret void 2453 // 2454 // 2455 // CHECK3-LABEL: define {{[^@]+}}@_Z6bazzzziPi 2456 // CHECK3-SAME: (i32 noundef [[N:%.*]], i32* noundef [[F:%.*]]) #[[ATTR0]] { 2457 // CHECK3-NEXT: entry: 2458 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 2459 // CHECK3-NEXT: [[F_ADDR:%.*]] = alloca i32*, align 4 2460 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 2461 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 2462 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 2463 // CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 2464 // CHECK3-NEXT: store i32* [[F]], i32** [[F_ADDR]], align 4 2465 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 2466 // CHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2467 // CHECK3-NEXT: [[TMP2:%.*]] = bitcast i8** [[TMP1]] to i32* 2468 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[TMP2]], align 4 2469 // CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2470 // CHECK3-NEXT: [[TMP4:%.*]] = bitcast i8** [[TMP3]] to i32* 2471 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[TMP4]], align 4 2472 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 2473 // CHECK3-NEXT: store i8* null, i8** [[TMP5]], align 4 2474 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2475 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2476 // CHECK3-NEXT: [[TMP8:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182.region_id, i32 1, i8** [[TMP6]], i8** [[TMP7]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.21, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.22, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 2477 // CHECK3-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0 2478 // CHECK3-NEXT: br i1 [[TMP9]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 2479 // CHECK3: omp_offload.failed: 2480 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182(i32 [[TMP0]]) #[[ATTR3]] 2481 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 2482 // CHECK3: omp_offload.cont: 2483 // CHECK3-NEXT: ret void 2484 // 2485 // 2486 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182 2487 // CHECK3-SAME: (i32 noundef [[VLA:%.*]]) #[[ATTR2]] { 2488 // CHECK3-NEXT: entry: 2489 // CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 2490 // CHECK3-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 2491 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 2492 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..20 to void (i32*, i32*, ...)*), i32 [[TMP0]]) 2493 // CHECK3-NEXT: ret void 2494 // 2495 // 2496 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..20 2497 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[VLA:%.*]]) #[[ATTR2]] { 2498 // CHECK3-NEXT: entry: 2499 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2500 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2501 // CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 2502 // CHECK3-NEXT: [[F:%.*]] = alloca i32*, align 4 2503 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2504 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2505 // CHECK3-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 2506 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 2507 // CHECK3-NEXT: ret void 2508 // 2509 // 2510 // CHECK3-LABEL: define {{[^@]+}}@_Z3bari 2511 // CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { 2512 // CHECK3-NEXT: entry: 2513 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 2514 // CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4 2515 // CHECK3-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 2516 // CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 2517 // CHECK3-NEXT: store i32 0, i32* [[A]], align 4 2518 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 2519 // CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]]) 2520 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 2521 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 2522 // CHECK3-NEXT: store i32 [[ADD]], i32* [[A]], align 4 2523 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 2524 // CHECK3-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP2]]) 2525 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 2526 // CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 2527 // CHECK3-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 2528 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 2529 // CHECK3-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]]) 2530 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 2531 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 2532 // CHECK3-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 2533 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 2534 // CHECK3-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]]) 2535 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 2536 // CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] 2537 // CHECK3-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 2538 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 2539 // CHECK3-NEXT: ret i32 [[TMP8]] 2540 // 2541 // 2542 // CHECK3-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 2543 // CHECK3-SAME: (%struct.S1* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 { 2544 // CHECK3-NEXT: entry: 2545 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 2546 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 2547 // CHECK3-NEXT: [[B:%.*]] = alloca i32, align 4 2548 // CHECK3-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 2549 // CHECK3-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 2550 // CHECK3-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 2551 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4 2552 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4 2553 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4 2554 // CHECK3-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 4 2555 // CHECK3-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 2556 // CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 2557 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 2558 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 2559 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 2560 // CHECK3-NEXT: store i32 [[ADD]], i32* [[B]], align 4 2561 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 2562 // CHECK3-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() 2563 // CHECK3-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 2564 // CHECK3-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] 2565 // CHECK3-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 2566 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 2567 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[B]], align 4 2568 // CHECK3-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 2569 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 2570 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 2571 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 60 2572 // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 2573 // CHECK3: omp_if.then: 2574 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 2575 // CHECK3-NEXT: [[TMP7:%.*]] = mul nuw i32 2, [[TMP1]] 2576 // CHECK3-NEXT: [[TMP8:%.*]] = mul nuw i32 [[TMP7]], 2 2577 // CHECK3-NEXT: [[TMP9:%.*]] = sext i32 [[TMP8]] to i64 2578 // CHECK3-NEXT: [[TMP10:%.*]] = bitcast [5 x i64]* [[DOTOFFLOAD_SIZES]] to i8* 2579 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP10]], i8* align 4 bitcast ([5 x i64]* @.offload_sizes.24 to i8*), i32 40, i1 false) 2580 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2581 // CHECK3-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to %struct.S1** 2582 // CHECK3-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP12]], align 4 2583 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2584 // CHECK3-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to double** 2585 // CHECK3-NEXT: store double* [[A]], double** [[TMP14]], align 4 2586 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 2587 // CHECK3-NEXT: store i8* null, i8** [[TMP15]], align 4 2588 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 2589 // CHECK3-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32* 2590 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[TMP17]], align 4 2591 // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 2592 // CHECK3-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32* 2593 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[TMP19]], align 4 2594 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 2595 // CHECK3-NEXT: store i8* null, i8** [[TMP20]], align 4 2596 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 2597 // CHECK3-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i32* 2598 // CHECK3-NEXT: store i32 2, i32* [[TMP22]], align 4 2599 // CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 2600 // CHECK3-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i32* 2601 // CHECK3-NEXT: store i32 2, i32* [[TMP24]], align 4 2602 // CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 2603 // CHECK3-NEXT: store i8* null, i8** [[TMP25]], align 4 2604 // CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 2605 // CHECK3-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i32* 2606 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP27]], align 4 2607 // CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 2608 // CHECK3-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i32* 2609 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP29]], align 4 2610 // CHECK3-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 2611 // CHECK3-NEXT: store i8* null, i8** [[TMP30]], align 4 2612 // CHECK3-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 2613 // CHECK3-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i16** 2614 // CHECK3-NEXT: store i16* [[VLA]], i16** [[TMP32]], align 4 2615 // CHECK3-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 2616 // CHECK3-NEXT: [[TMP34:%.*]] = bitcast i8** [[TMP33]] to i16** 2617 // CHECK3-NEXT: store i16* [[VLA]], i16** [[TMP34]], align 4 2618 // CHECK3-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 2619 // CHECK3-NEXT: store i64 [[TMP9]], i64* [[TMP35]], align 4 2620 // CHECK3-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 2621 // CHECK3-NEXT: store i8* null, i8** [[TMP36]], align 4 2622 // CHECK3-NEXT: [[TMP37:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2623 // CHECK3-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2624 // CHECK3-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 2625 // CHECK3-NEXT: [[TMP40:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227.region_id, i32 5, i8** [[TMP37]], i8** [[TMP38]], i64* [[TMP39]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.25, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 2626 // CHECK3-NEXT: [[TMP41:%.*]] = icmp ne i32 [[TMP40]], 0 2627 // CHECK3-NEXT: br i1 [[TMP41]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 2628 // CHECK3: omp_offload.failed: 2629 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR3]] 2630 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 2631 // CHECK3: omp_offload.cont: 2632 // CHECK3-NEXT: br label [[OMP_IF_END:%.*]] 2633 // CHECK3: omp_if.else: 2634 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR3]] 2635 // CHECK3-NEXT: br label [[OMP_IF_END]] 2636 // CHECK3: omp_if.end: 2637 // CHECK3-NEXT: [[TMP42:%.*]] = mul nsw i32 1, [[TMP1]] 2638 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP42]] 2639 // CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 2640 // CHECK3-NEXT: [[TMP43:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2 2641 // CHECK3-NEXT: [[CONV:%.*]] = sext i16 [[TMP43]] to i32 2642 // CHECK3-NEXT: [[TMP44:%.*]] = load i32, i32* [[B]], align 4 2643 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP44]] 2644 // CHECK3-NEXT: [[TMP45:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 2645 // CHECK3-NEXT: call void @llvm.stackrestore(i8* [[TMP45]]) 2646 // CHECK3-NEXT: ret i32 [[ADD3]] 2647 // 2648 // 2649 // CHECK3-LABEL: define {{[^@]+}}@_ZL7fstatici 2650 // CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { 2651 // CHECK3-NEXT: entry: 2652 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 2653 // CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4 2654 // CHECK3-NEXT: [[AA:%.*]] = alloca i16, align 2 2655 // CHECK3-NEXT: [[AAA:%.*]] = alloca i8, align 1 2656 // CHECK3-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 2657 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 2658 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 2659 // CHECK3-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 2660 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4 2661 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 2662 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 2663 // CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 2664 // CHECK3-NEXT: store i32 0, i32* [[A]], align 4 2665 // CHECK3-NEXT: store i16 0, i16* [[AA]], align 2 2666 // CHECK3-NEXT: store i8 0, i8* [[AAA]], align 1 2667 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 2668 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 2669 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 2670 // CHECK3-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 2671 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 2672 // CHECK3-NEXT: store i16 [[TMP2]], i16* [[CONV]], align 2 2673 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 2674 // CHECK3-NEXT: [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1 2675 // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* 2676 // CHECK3-NEXT: store i8 [[TMP4]], i8* [[CONV1]], align 1 2677 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 2678 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 2679 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50 2680 // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 2681 // CHECK3: omp_if.then: 2682 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2683 // CHECK3-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* 2684 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4 2685 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2686 // CHECK3-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* 2687 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP10]], align 4 2688 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 2689 // CHECK3-NEXT: store i8* null, i8** [[TMP11]], align 4 2690 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 2691 // CHECK3-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* 2692 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4 2693 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 2694 // CHECK3-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32* 2695 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP15]], align 4 2696 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 2697 // CHECK3-NEXT: store i8* null, i8** [[TMP16]], align 4 2698 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 2699 // CHECK3-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32* 2700 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[TMP18]], align 4 2701 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 2702 // CHECK3-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32* 2703 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[TMP20]], align 4 2704 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 2705 // CHECK3-NEXT: store i8* null, i8** [[TMP21]], align 4 2706 // CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 2707 // CHECK3-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]** 2708 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 4 2709 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 2710 // CHECK3-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]** 2711 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 4 2712 // CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 2713 // CHECK3-NEXT: store i8* null, i8** [[TMP26]], align 4 2714 // CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2715 // CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2716 // CHECK3-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.27, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.28, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 2717 // CHECK3-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 2718 // CHECK3-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 2719 // CHECK3: omp_offload.failed: 2720 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR3]] 2721 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 2722 // CHECK3: omp_offload.cont: 2723 // CHECK3-NEXT: br label [[OMP_IF_END:%.*]] 2724 // CHECK3: omp_if.else: 2725 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR3]] 2726 // CHECK3-NEXT: br label [[OMP_IF_END]] 2727 // CHECK3: omp_if.end: 2728 // CHECK3-NEXT: [[TMP31:%.*]] = load i32, i32* [[A]], align 4 2729 // CHECK3-NEXT: ret i32 [[TMP31]] 2730 // 2731 // 2732 // CHECK3-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 2733 // CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat { 2734 // CHECK3-NEXT: entry: 2735 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 2736 // CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4 2737 // CHECK3-NEXT: [[AA:%.*]] = alloca i16, align 2 2738 // CHECK3-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 2739 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 2740 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 2741 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 2742 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 2743 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 2744 // CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 2745 // CHECK3-NEXT: store i32 0, i32* [[A]], align 4 2746 // CHECK3-NEXT: store i16 0, i16* [[AA]], align 2 2747 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 2748 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 2749 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 2750 // CHECK3-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 2751 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 2752 // CHECK3-NEXT: store i16 [[TMP2]], i16* [[CONV]], align 2 2753 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 2754 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 2755 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40 2756 // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 2757 // CHECK3: omp_if.then: 2758 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2759 // CHECK3-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i32* 2760 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP6]], align 4 2761 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2762 // CHECK3-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* 2763 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4 2764 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 2765 // CHECK3-NEXT: store i8* null, i8** [[TMP9]], align 4 2766 // CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 2767 // CHECK3-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i32* 2768 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP11]], align 4 2769 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 2770 // CHECK3-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* 2771 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4 2772 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 2773 // CHECK3-NEXT: store i8* null, i8** [[TMP14]], align 4 2774 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 2775 // CHECK3-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]** 2776 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 4 2777 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 2778 // CHECK3-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]** 2779 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 4 2780 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 2781 // CHECK3-NEXT: store i8* null, i8** [[TMP19]], align 4 2782 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2783 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2784 // CHECK3-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.30, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.31, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 2785 // CHECK3-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 2786 // CHECK3-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 2787 // CHECK3: omp_offload.failed: 2788 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]] 2789 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 2790 // CHECK3: omp_offload.cont: 2791 // CHECK3-NEXT: br label [[OMP_IF_END:%.*]] 2792 // CHECK3: omp_if.else: 2793 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]] 2794 // CHECK3-NEXT: br label [[OMP_IF_END]] 2795 // CHECK3: omp_if.end: 2796 // CHECK3-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4 2797 // CHECK3-NEXT: ret i32 [[TMP24]] 2798 // 2799 // 2800 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227 2801 // CHECK3-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { 2802 // CHECK3-NEXT: entry: 2803 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 2804 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 2805 // CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 2806 // CHECK3-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 2807 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 2808 // CHECK3-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 2809 // CHECK3-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 2810 // CHECK3-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 2811 // CHECK3-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 2812 // CHECK3-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 2813 // CHECK3-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 2814 // CHECK3-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 2815 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 2816 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 2817 // CHECK3-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 2818 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 2819 // CHECK3-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 2820 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 2821 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..23 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]]) 2822 // CHECK3-NEXT: ret void 2823 // 2824 // 2825 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..23 2826 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { 2827 // CHECK3-NEXT: entry: 2828 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2829 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2830 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 2831 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 2832 // CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 2833 // CHECK3-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 2834 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 2835 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2836 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2837 // CHECK3-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 2838 // CHECK3-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 2839 // CHECK3-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 2840 // CHECK3-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 2841 // CHECK3-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 2842 // CHECK3-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 2843 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 2844 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 2845 // CHECK3-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 2846 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 2847 // CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP4]] to double 2848 // CHECK3-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 2849 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 2850 // CHECK3-NEXT: store double [[ADD]], double* [[A]], align 4 2851 // CHECK3-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 2852 // CHECK3-NEXT: [[TMP5:%.*]] = load double, double* [[A3]], align 4 2853 // CHECK3-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 2854 // CHECK3-NEXT: store double [[INC]], double* [[A3]], align 4 2855 // CHECK3-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 2856 // CHECK3-NEXT: [[TMP6:%.*]] = mul nsw i32 1, [[TMP2]] 2857 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP6]] 2858 // CHECK3-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 2859 // CHECK3-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 2860 // CHECK3-NEXT: ret void 2861 // 2862 // 2863 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209 2864 // CHECK3-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 2865 // CHECK3-NEXT: entry: 2866 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2867 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 2868 // CHECK3-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 2869 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 2870 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 2871 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 2872 // CHECK3-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 2873 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 2874 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 2875 // CHECK3-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 2876 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 2877 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 2878 // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 2879 // CHECK3-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 2880 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 2881 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 2882 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 2883 // CHECK3-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 2884 // CHECK3-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 2885 // CHECK3-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 2886 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 2887 // CHECK3-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1 2888 // CHECK3-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* 2889 // CHECK3-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 2890 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 2891 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..26 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) 2892 // CHECK3-NEXT: ret void 2893 // 2894 // 2895 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..26 2896 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 2897 // CHECK3-NEXT: entry: 2898 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2899 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2900 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2901 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 2902 // CHECK3-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 2903 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 2904 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2905 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2906 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 2907 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 2908 // CHECK3-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 2909 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 2910 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 2911 // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 2912 // CHECK3-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 2913 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 2914 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 2915 // CHECK3-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 2916 // CHECK3-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 2917 // CHECK3-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 2918 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 2919 // CHECK3-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 2920 // CHECK3-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2 2921 // CHECK3-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 1 2922 // CHECK3-NEXT: [[CONV5:%.*]] = sext i8 [[TMP3]] to i32 2923 // CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 2924 // CHECK3-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i8 2925 // CHECK3-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 1 2926 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 2927 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 2928 // CHECK3-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP4]], 1 2929 // CHECK3-NEXT: store i32 [[ADD8]], i32* [[ARRAYIDX]], align 4 2930 // CHECK3-NEXT: ret void 2931 // 2932 // 2933 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192 2934 // CHECK3-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 2935 // CHECK3-NEXT: entry: 2936 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2937 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 2938 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 2939 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 2940 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 2941 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 2942 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 2943 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 2944 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 2945 // CHECK3-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 2946 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 2947 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 2948 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 2949 // CHECK3-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 2950 // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 2951 // CHECK3-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 2952 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 2953 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..29 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) 2954 // CHECK3-NEXT: ret void 2955 // 2956 // 2957 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..29 2958 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 2959 // CHECK3-NEXT: entry: 2960 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2961 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2962 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2963 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 2964 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 2965 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2966 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2967 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 2968 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 2969 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 2970 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 2971 // CHECK3-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 2972 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 2973 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 2974 // CHECK3-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 2975 // CHECK3-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 2976 // CHECK3-NEXT: [[CONV1:%.*]] = sext i16 [[TMP2]] to i32 2977 // CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 2978 // CHECK3-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 2979 // CHECK3-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2 2980 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 2981 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 2982 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1 2983 // CHECK3-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4 2984 // CHECK3-NEXT: ret void 2985 // 2986 // 2987 // CHECK3-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 2988 // CHECK3-SAME: () #[[ATTR4]] { 2989 // CHECK3-NEXT: entry: 2990 // CHECK3-NEXT: call void @__tgt_register_requires(i64 1) 2991 // CHECK3-NEXT: ret void 2992 // 2993 // 2994 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101 2995 // CHECK9-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { 2996 // CHECK9-NEXT: entry: 2997 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 2998 // CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 2999 // CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8 3000 // CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 3001 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) 3002 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 3003 // CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 3004 // CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8 3005 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 3006 // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* 3007 // CHECK9-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32* 3008 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 4 3009 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 4 3010 // CHECK9-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) 3011 // CHECK9-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 3012 // CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 3013 // CHECK9-NEXT: store i16 [[TMP3]], i16* [[CONV5]], align 2 3014 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 3015 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]]) 3016 // CHECK9-NEXT: ret void 3017 // 3018 // 3019 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. 3020 // CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { 3021 // CHECK9-NEXT: entry: 3022 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 3023 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 3024 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 3025 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 3026 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 3027 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 3028 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 3029 // CHECK9-NEXT: ret void 3030 // 3031 // 3032 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 3033 // CHECK9-SAME: (i64 noundef [[AA:%.*]]) #[[ATTR0]] { 3034 // CHECK9-NEXT: entry: 3035 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 3036 // CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 3037 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 3038 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 3039 // CHECK9-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 3040 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 3041 // CHECK9-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 3042 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 3043 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]]) 3044 // CHECK9-NEXT: ret void 3045 // 3046 // 3047 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 3048 // CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { 3049 // CHECK9-NEXT: entry: 3050 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 3051 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 3052 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 3053 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 3054 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 3055 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 3056 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 3057 // CHECK9-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 3058 // CHECK9-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 3059 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 3060 // CHECK9-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 3061 // CHECK9-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2 3062 // CHECK9-NEXT: ret void 3063 // 3064 // 3065 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118 3066 // CHECK9-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { 3067 // CHECK9-NEXT: entry: 3068 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 3069 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 3070 // CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 3071 // CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 3072 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 3073 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 3074 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 3075 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 3076 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 3077 // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* 3078 // CHECK9-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 3079 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 3080 // CHECK9-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 3081 // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 3082 // CHECK9-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 3083 // CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 3084 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) 3085 // CHECK9-NEXT: ret void 3086 // 3087 // 3088 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..2 3089 // CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { 3090 // CHECK9-NEXT: entry: 3091 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 3092 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 3093 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 3094 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 3095 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 3096 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 3097 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 3098 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 3099 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 3100 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 3101 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 3102 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 3103 // CHECK9-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 3104 // CHECK9-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 2 3105 // CHECK9-NEXT: [[CONV2:%.*]] = sext i16 [[TMP1]] to i32 3106 // CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 3107 // CHECK9-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 3108 // CHECK9-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2 3109 // CHECK9-NEXT: ret void 3110 // 3111 // 3112 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142 3113 // CHECK9-SAME: (i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] { 3114 // CHECK9-NEXT: entry: 3115 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 3116 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 3117 // CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 3118 // CHECK9-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 3119 // CHECK9-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 3120 // CHECK9-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 3121 // CHECK9-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 3122 // CHECK9-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 3123 // CHECK9-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 3124 // CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 3125 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 3126 // CHECK9-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 3127 // CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 3128 // CHECK9-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 3129 // CHECK9-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 3130 // CHECK9-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 3131 // CHECK9-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 3132 // CHECK9-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 3133 // CHECK9-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 3134 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 3135 // CHECK9-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 3136 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 3137 // CHECK9-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 3138 // CHECK9-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 3139 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 3140 // CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 3141 // CHECK9-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 3142 // CHECK9-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 3143 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 3144 // CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* 3145 // CHECK9-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4 3146 // CHECK9-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 3147 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) 3148 // CHECK9-NEXT: ret void 3149 // 3150 // 3151 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..3 3152 // CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] { 3153 // CHECK9-NEXT: entry: 3154 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 3155 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 3156 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 3157 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 3158 // CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 3159 // CHECK9-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 3160 // CHECK9-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 3161 // CHECK9-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 3162 // CHECK9-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 3163 // CHECK9-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 3164 // CHECK9-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 3165 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 3166 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 3167 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 3168 // CHECK9-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 3169 // CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 3170 // CHECK9-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 3171 // CHECK9-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 3172 // CHECK9-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 3173 // CHECK9-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 3174 // CHECK9-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 3175 // CHECK9-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 3176 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 3177 // CHECK9-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 3178 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 3179 // CHECK9-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 3180 // CHECK9-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 3181 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 3182 // CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 3183 // CHECK9-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 3184 // CHECK9-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 3185 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 3186 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 3187 // CHECK9-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 3188 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 3189 // CHECK9-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 3190 // CHECK9-NEXT: [[CONV5:%.*]] = fpext float [[TMP9]] to double 3191 // CHECK9-NEXT: [[ADD6:%.*]] = fadd double [[CONV5]], 1.000000e+00 3192 // CHECK9-NEXT: [[CONV7:%.*]] = fptrunc double [[ADD6]] to float 3193 // CHECK9-NEXT: store float [[CONV7]], float* [[ARRAYIDX]], align 4 3194 // CHECK9-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 3195 // CHECK9-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX8]], align 4 3196 // CHECK9-NEXT: [[CONV9:%.*]] = fpext float [[TMP10]] to double 3197 // CHECK9-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 3198 // CHECK9-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float 3199 // CHECK9-NEXT: store float [[CONV11]], float* [[ARRAYIDX8]], align 4 3200 // CHECK9-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1 3201 // CHECK9-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX12]], i64 0, i64 2 3202 // CHECK9-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX13]], align 8 3203 // CHECK9-NEXT: [[ADD14:%.*]] = fadd double [[TMP11]], 1.000000e+00 3204 // CHECK9-NEXT: store double [[ADD14]], double* [[ARRAYIDX13]], align 8 3205 // CHECK9-NEXT: [[TMP12:%.*]] = mul nsw i64 1, [[TMP5]] 3206 // CHECK9-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP12]] 3207 // CHECK9-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX15]], i64 3 3208 // CHECK9-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX16]], align 8 3209 // CHECK9-NEXT: [[ADD17:%.*]] = fadd double [[TMP13]], 1.000000e+00 3210 // CHECK9-NEXT: store double [[ADD17]], double* [[ARRAYIDX16]], align 8 3211 // CHECK9-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 3212 // CHECK9-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 8 3213 // CHECK9-NEXT: [[ADD18:%.*]] = add nsw i64 [[TMP14]], 1 3214 // CHECK9-NEXT: store i64 [[ADD18]], i64* [[X]], align 8 3215 // CHECK9-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 3216 // CHECK9-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 8 3217 // CHECK9-NEXT: [[CONV19:%.*]] = sext i8 [[TMP15]] to i32 3218 // CHECK9-NEXT: [[ADD20:%.*]] = add nsw i32 [[CONV19]], 1 3219 // CHECK9-NEXT: [[CONV21:%.*]] = trunc i32 [[ADD20]] to i8 3220 // CHECK9-NEXT: store i8 [[CONV21]], i8* [[Y]], align 8 3221 // CHECK9-NEXT: ret void 3222 // 3223 // 3224 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154 3225 // CHECK9-SAME: (i64 noundef [[NN:%.*]]) #[[ATTR0]] { 3226 // CHECK9-NEXT: entry: 3227 // CHECK9-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 3228 // CHECK9-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 3229 // CHECK9-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 3230 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* 3231 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 3232 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32* 3233 // CHECK9-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 3234 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8 3235 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP1]]) 3236 // CHECK9-NEXT: ret void 3237 // 3238 // 3239 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..4 3240 // CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[NN:%.*]]) #[[ATTR0]] { 3241 // CHECK9-NEXT: entry: 3242 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 3243 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 3244 // CHECK9-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 3245 // CHECK9-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 3246 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 3247 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 3248 // CHECK9-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 3249 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* 3250 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 3251 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32* 3252 // CHECK9-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 3253 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8 3254 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP1]]) 3255 // CHECK9-NEXT: ret void 3256 // 3257 // 3258 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..5 3259 // CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[NN:%.*]]) #[[ATTR0]] { 3260 // CHECK9-NEXT: entry: 3261 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 3262 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 3263 // CHECK9-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 3264 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 3265 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 3266 // CHECK9-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 3267 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* 3268 // CHECK9-NEXT: ret void 3269 // 3270 // 3271 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157 3272 // CHECK9-SAME: (i64 noundef [[NN:%.*]]) #[[ATTR0]] { 3273 // CHECK9-NEXT: entry: 3274 // CHECK9-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 3275 // CHECK9-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 3276 // CHECK9-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 3277 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* 3278 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 3279 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32* 3280 // CHECK9-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 3281 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8 3282 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP1]]) 3283 // CHECK9-NEXT: ret void 3284 // 3285 // 3286 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..6 3287 // CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[NN:%.*]]) #[[ATTR0]] { 3288 // CHECK9-NEXT: entry: 3289 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 3290 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 3291 // CHECK9-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 3292 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 3293 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 3294 // CHECK9-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 3295 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* 3296 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32* [[CONV]]) 3297 // CHECK9-NEXT: ret void 3298 // 3299 // 3300 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..7 3301 // CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[NN:%.*]]) #[[ATTR0]] { 3302 // CHECK9-NEXT: entry: 3303 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 3304 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 3305 // CHECK9-NEXT: [[NN_ADDR:%.*]] = alloca i32*, align 8 3306 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 3307 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 3308 // CHECK9-NEXT: store i32* [[NN]], i32** [[NN_ADDR]], align 8 3309 // CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[NN_ADDR]], align 8 3310 // CHECK9-NEXT: ret void 3311 // 3312 // 3313 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182 3314 // CHECK9-SAME: (i64 noundef [[VLA:%.*]]) #[[ATTR0]] { 3315 // CHECK9-NEXT: entry: 3316 // CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 3317 // CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 3318 // CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 3319 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..8 to void (i32*, i32*, ...)*), i64 [[TMP0]]) 3320 // CHECK9-NEXT: ret void 3321 // 3322 // 3323 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..8 3324 // CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[VLA:%.*]]) #[[ATTR0]] { 3325 // CHECK9-NEXT: entry: 3326 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 3327 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 3328 // CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 3329 // CHECK9-NEXT: [[F:%.*]] = alloca i32*, align 8 3330 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 3331 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 3332 // CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 3333 // CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 3334 // CHECK9-NEXT: ret void 3335 // 3336 // 3337 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209 3338 // CHECK9-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 3339 // CHECK9-NEXT: entry: 3340 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 3341 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 3342 // CHECK9-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 3343 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 3344 // CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 3345 // CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 3346 // CHECK9-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 3347 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 3348 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 3349 // CHECK9-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 3350 // CHECK9-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 3351 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 3352 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 3353 // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 3354 // CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 3355 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 3356 // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* 3357 // CHECK9-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 3358 // CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 3359 // CHECK9-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 3360 // CHECK9-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 3361 // CHECK9-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 3362 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 3363 // CHECK9-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1 3364 // CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* 3365 // CHECK9-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 3366 // CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 3367 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) 3368 // CHECK9-NEXT: ret void 3369 // 3370 // 3371 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..9 3372 // CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 3373 // CHECK9-NEXT: entry: 3374 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 3375 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 3376 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 3377 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 3378 // CHECK9-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 3379 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 3380 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 3381 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 3382 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 3383 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 3384 // CHECK9-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 3385 // CHECK9-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 3386 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 3387 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 3388 // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 3389 // CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 3390 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 3391 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 3392 // CHECK9-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 3393 // CHECK9-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 3394 // CHECK9-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32 3395 // CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 3396 // CHECK9-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 3397 // CHECK9-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 2 3398 // CHECK9-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 1 3399 // CHECK9-NEXT: [[CONV6:%.*]] = sext i8 [[TMP3]] to i32 3400 // CHECK9-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 3401 // CHECK9-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i8 3402 // CHECK9-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 1 3403 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 3404 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 3405 // CHECK9-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP4]], 1 3406 // CHECK9-NEXT: store i32 [[ADD9]], i32* [[ARRAYIDX]], align 4 3407 // CHECK9-NEXT: ret void 3408 // 3409 // 3410 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227 3411 // CHECK9-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { 3412 // CHECK9-NEXT: entry: 3413 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 3414 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 3415 // CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 3416 // CHECK9-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 3417 // CHECK9-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 3418 // CHECK9-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 3419 // CHECK9-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 3420 // CHECK9-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 3421 // CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 3422 // CHECK9-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 3423 // CHECK9-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 3424 // CHECK9-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 3425 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 3426 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 3427 // CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 3428 // CHECK9-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 3429 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4 3430 // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* 3431 // CHECK9-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 3432 // CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 3433 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) 3434 // CHECK9-NEXT: ret void 3435 // 3436 // 3437 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..10 3438 // CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { 3439 // CHECK9-NEXT: entry: 3440 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 3441 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 3442 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 3443 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 3444 // CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 3445 // CHECK9-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 3446 // CHECK9-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 3447 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 3448 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 3449 // CHECK9-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 3450 // CHECK9-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 3451 // CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 3452 // CHECK9-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 3453 // CHECK9-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 3454 // CHECK9-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 3455 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 3456 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 3457 // CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 3458 // CHECK9-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 3459 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4 3460 // CHECK9-NEXT: [[CONV3:%.*]] = sitofp i32 [[TMP4]] to double 3461 // CHECK9-NEXT: [[ADD:%.*]] = fadd double [[CONV3]], 1.500000e+00 3462 // CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 3463 // CHECK9-NEXT: store double [[ADD]], double* [[A]], align 8 3464 // CHECK9-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 3465 // CHECK9-NEXT: [[TMP5:%.*]] = load double, double* [[A4]], align 8 3466 // CHECK9-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 3467 // CHECK9-NEXT: store double [[INC]], double* [[A4]], align 8 3468 // CHECK9-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 3469 // CHECK9-NEXT: [[TMP6:%.*]] = mul nsw i64 1, [[TMP2]] 3470 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP6]] 3471 // CHECK9-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 3472 // CHECK9-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2 3473 // CHECK9-NEXT: ret void 3474 // 3475 // 3476 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192 3477 // CHECK9-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 3478 // CHECK9-NEXT: entry: 3479 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 3480 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 3481 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 3482 // CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 3483 // CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 3484 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 3485 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 3486 // CHECK9-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 3487 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 3488 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 3489 // CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 3490 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 3491 // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* 3492 // CHECK9-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 3493 // CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 3494 // CHECK9-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 3495 // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 3496 // CHECK9-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 3497 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 3498 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) 3499 // CHECK9-NEXT: ret void 3500 // 3501 // 3502 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..11 3503 // CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 3504 // CHECK9-NEXT: entry: 3505 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 3506 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 3507 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 3508 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 3509 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 3510 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 3511 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 3512 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 3513 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 3514 // CHECK9-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 3515 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 3516 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 3517 // CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 3518 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 3519 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 3520 // CHECK9-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 3521 // CHECK9-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 3522 // CHECK9-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 3523 // CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 3524 // CHECK9-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 3525 // CHECK9-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2 3526 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 3527 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 3528 // CHECK9-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP3]], 1 3529 // CHECK9-NEXT: store i32 [[ADD5]], i32* [[ARRAYIDX]], align 4 3530 // CHECK9-NEXT: ret void 3531 // 3532 // 3533 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101 3534 // CHECK11-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]], i32 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { 3535 // CHECK11-NEXT: entry: 3536 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 3537 // CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 3538 // CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4 3539 // CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 3540 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) 3541 // CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 3542 // CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 3543 // CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 3544 // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 3545 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 3546 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 3547 // CHECK11-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) 3548 // CHECK11-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 3549 // CHECK11-NEXT: [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 3550 // CHECK11-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 3551 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 3552 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]]) 3553 // CHECK11-NEXT: ret void 3554 // 3555 // 3556 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. 3557 // CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { 3558 // CHECK11-NEXT: entry: 3559 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 3560 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 3561 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 3562 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 3563 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 3564 // CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 3565 // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 3566 // CHECK11-NEXT: ret void 3567 // 3568 // 3569 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 3570 // CHECK11-SAME: (i32 noundef [[AA:%.*]]) #[[ATTR0]] { 3571 // CHECK11-NEXT: entry: 3572 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 3573 // CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 3574 // CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 3575 // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 3576 // CHECK11-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 3577 // CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 3578 // CHECK11-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 3579 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 3580 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]]) 3581 // CHECK11-NEXT: ret void 3582 // 3583 // 3584 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 3585 // CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { 3586 // CHECK11-NEXT: entry: 3587 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 3588 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 3589 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 3590 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 3591 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 3592 // CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 3593 // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 3594 // CHECK11-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 3595 // CHECK11-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 3596 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 3597 // CHECK11-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 3598 // CHECK11-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2 3599 // CHECK11-NEXT: ret void 3600 // 3601 // 3602 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118 3603 // CHECK11-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { 3604 // CHECK11-NEXT: entry: 3605 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3606 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 3607 // CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 3608 // CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 3609 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 3610 // CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 3611 // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 3612 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 3613 // CHECK11-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 3614 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 3615 // CHECK11-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 3616 // CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 3617 // CHECK11-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 3618 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 3619 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) 3620 // CHECK11-NEXT: ret void 3621 // 3622 // 3623 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..2 3624 // CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { 3625 // CHECK11-NEXT: entry: 3626 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 3627 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 3628 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3629 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 3630 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 3631 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 3632 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 3633 // CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 3634 // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 3635 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 3636 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 3637 // CHECK11-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 3638 // CHECK11-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 2 3639 // CHECK11-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32 3640 // CHECK11-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 3641 // CHECK11-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 3642 // CHECK11-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2 3643 // CHECK11-NEXT: ret void 3644 // 3645 // 3646 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142 3647 // CHECK11-SAME: (i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] { 3648 // CHECK11-NEXT: entry: 3649 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3650 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 3651 // CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 3652 // CHECK11-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 3653 // CHECK11-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 3654 // CHECK11-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 3655 // CHECK11-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 3656 // CHECK11-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 3657 // CHECK11-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 3658 // CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 3659 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 3660 // CHECK11-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 3661 // CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 3662 // CHECK11-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 3663 // CHECK11-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 3664 // CHECK11-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 3665 // CHECK11-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 3666 // CHECK11-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 3667 // CHECK11-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 3668 // CHECK11-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 3669 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 3670 // CHECK11-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 3671 // CHECK11-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 3672 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 3673 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 3674 // CHECK11-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 3675 // CHECK11-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 3676 // CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 3677 // CHECK11-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4 3678 // CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4 3679 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) 3680 // CHECK11-NEXT: ret void 3681 // 3682 // 3683 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..3 3684 // CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] { 3685 // CHECK11-NEXT: entry: 3686 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 3687 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 3688 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3689 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 3690 // CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 3691 // CHECK11-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 3692 // CHECK11-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 3693 // CHECK11-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 3694 // CHECK11-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 3695 // CHECK11-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 3696 // CHECK11-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 3697 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 3698 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 3699 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 3700 // CHECK11-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 3701 // CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 3702 // CHECK11-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 3703 // CHECK11-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 3704 // CHECK11-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 3705 // CHECK11-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 3706 // CHECK11-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 3707 // CHECK11-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 3708 // CHECK11-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 3709 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 3710 // CHECK11-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 3711 // CHECK11-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 3712 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 3713 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 3714 // CHECK11-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 3715 // CHECK11-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 3716 // CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 3717 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 3718 // CHECK11-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 3719 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2 3720 // CHECK11-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 3721 // CHECK11-NEXT: [[CONV:%.*]] = fpext float [[TMP9]] to double 3722 // CHECK11-NEXT: [[ADD5:%.*]] = fadd double [[CONV]], 1.000000e+00 3723 // CHECK11-NEXT: [[CONV6:%.*]] = fptrunc double [[ADD5]] to float 3724 // CHECK11-NEXT: store float [[CONV6]], float* [[ARRAYIDX]], align 4 3725 // CHECK11-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3 3726 // CHECK11-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX7]], align 4 3727 // CHECK11-NEXT: [[CONV8:%.*]] = fpext float [[TMP10]] to double 3728 // CHECK11-NEXT: [[ADD9:%.*]] = fadd double [[CONV8]], 1.000000e+00 3729 // CHECK11-NEXT: [[CONV10:%.*]] = fptrunc double [[ADD9]] to float 3730 // CHECK11-NEXT: store float [[CONV10]], float* [[ARRAYIDX7]], align 4 3731 // CHECK11-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1 3732 // CHECK11-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX11]], i32 0, i32 2 3733 // CHECK11-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX12]], align 8 3734 // CHECK11-NEXT: [[ADD13:%.*]] = fadd double [[TMP11]], 1.000000e+00 3735 // CHECK11-NEXT: store double [[ADD13]], double* [[ARRAYIDX12]], align 8 3736 // CHECK11-NEXT: [[TMP12:%.*]] = mul nsw i32 1, [[TMP5]] 3737 // CHECK11-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP12]] 3738 // CHECK11-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX14]], i32 3 3739 // CHECK11-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX15]], align 8 3740 // CHECK11-NEXT: [[ADD16:%.*]] = fadd double [[TMP13]], 1.000000e+00 3741 // CHECK11-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8 3742 // CHECK11-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 3743 // CHECK11-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 4 3744 // CHECK11-NEXT: [[ADD17:%.*]] = add nsw i64 [[TMP14]], 1 3745 // CHECK11-NEXT: store i64 [[ADD17]], i64* [[X]], align 4 3746 // CHECK11-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 3747 // CHECK11-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 4 3748 // CHECK11-NEXT: [[CONV18:%.*]] = sext i8 [[TMP15]] to i32 3749 // CHECK11-NEXT: [[ADD19:%.*]] = add nsw i32 [[CONV18]], 1 3750 // CHECK11-NEXT: [[CONV20:%.*]] = trunc i32 [[ADD19]] to i8 3751 // CHECK11-NEXT: store i8 [[CONV20]], i8* [[Y]], align 4 3752 // CHECK11-NEXT: ret void 3753 // 3754 // 3755 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154 3756 // CHECK11-SAME: (i32 noundef [[NN:%.*]]) #[[ATTR0]] { 3757 // CHECK11-NEXT: entry: 3758 // CHECK11-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 3759 // CHECK11-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4 3760 // CHECK11-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 3761 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[NN_ADDR]], align 4 3762 // CHECK11-NEXT: store i32 [[TMP0]], i32* [[NN_CASTED]], align 4 3763 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[NN_CASTED]], align 4 3764 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP1]]) 3765 // CHECK11-NEXT: ret void 3766 // 3767 // 3768 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..4 3769 // CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[NN:%.*]]) #[[ATTR0]] { 3770 // CHECK11-NEXT: entry: 3771 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 3772 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 3773 // CHECK11-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 3774 // CHECK11-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4 3775 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 3776 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 3777 // CHECK11-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 3778 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[NN_ADDR]], align 4 3779 // CHECK11-NEXT: store i32 [[TMP0]], i32* [[NN_CASTED]], align 4 3780 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[NN_CASTED]], align 4 3781 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP1]]) 3782 // CHECK11-NEXT: ret void 3783 // 3784 // 3785 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..5 3786 // CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[NN:%.*]]) #[[ATTR0]] { 3787 // CHECK11-NEXT: entry: 3788 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 3789 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 3790 // CHECK11-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 3791 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 3792 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 3793 // CHECK11-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 3794 // CHECK11-NEXT: ret void 3795 // 3796 // 3797 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157 3798 // CHECK11-SAME: (i32 noundef [[NN:%.*]]) #[[ATTR0]] { 3799 // CHECK11-NEXT: entry: 3800 // CHECK11-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 3801 // CHECK11-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4 3802 // CHECK11-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 3803 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[NN_ADDR]], align 4 3804 // CHECK11-NEXT: store i32 [[TMP0]], i32* [[NN_CASTED]], align 4 3805 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[NN_CASTED]], align 4 3806 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP1]]) 3807 // CHECK11-NEXT: ret void 3808 // 3809 // 3810 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..6 3811 // CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[NN:%.*]]) #[[ATTR0]] { 3812 // CHECK11-NEXT: entry: 3813 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 3814 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 3815 // CHECK11-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 3816 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 3817 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 3818 // CHECK11-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 3819 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32* [[NN_ADDR]]) 3820 // CHECK11-NEXT: ret void 3821 // 3822 // 3823 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..7 3824 // CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[NN:%.*]]) #[[ATTR0]] { 3825 // CHECK11-NEXT: entry: 3826 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 3827 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 3828 // CHECK11-NEXT: [[NN_ADDR:%.*]] = alloca i32*, align 4 3829 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 3830 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 3831 // CHECK11-NEXT: store i32* [[NN]], i32** [[NN_ADDR]], align 4 3832 // CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[NN_ADDR]], align 4 3833 // CHECK11-NEXT: ret void 3834 // 3835 // 3836 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182 3837 // CHECK11-SAME: (i32 noundef [[VLA:%.*]]) #[[ATTR0]] { 3838 // CHECK11-NEXT: entry: 3839 // CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 3840 // CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 3841 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 3842 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..8 to void (i32*, i32*, ...)*), i32 [[TMP0]]) 3843 // CHECK11-NEXT: ret void 3844 // 3845 // 3846 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..8 3847 // CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[VLA:%.*]]) #[[ATTR0]] { 3848 // CHECK11-NEXT: entry: 3849 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 3850 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 3851 // CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 3852 // CHECK11-NEXT: [[F:%.*]] = alloca i32*, align 4 3853 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 3854 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 3855 // CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 3856 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 3857 // CHECK11-NEXT: ret void 3858 // 3859 // 3860 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209 3861 // CHECK11-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 3862 // CHECK11-NEXT: entry: 3863 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3864 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 3865 // CHECK11-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 3866 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 3867 // CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 3868 // CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 3869 // CHECK11-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 3870 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 3871 // CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 3872 // CHECK11-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 3873 // CHECK11-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 3874 // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 3875 // CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 3876 // CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 3877 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 3878 // CHECK11-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 3879 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 3880 // CHECK11-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 3881 // CHECK11-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 3882 // CHECK11-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 3883 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 3884 // CHECK11-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1 3885 // CHECK11-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* 3886 // CHECK11-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 3887 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 3888 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) 3889 // CHECK11-NEXT: ret void 3890 // 3891 // 3892 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..9 3893 // CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 3894 // CHECK11-NEXT: entry: 3895 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 3896 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 3897 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3898 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 3899 // CHECK11-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 3900 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 3901 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 3902 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 3903 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 3904 // CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 3905 // CHECK11-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 3906 // CHECK11-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 3907 // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 3908 // CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 3909 // CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 3910 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 3911 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 3912 // CHECK11-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 3913 // CHECK11-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 3914 // CHECK11-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 3915 // CHECK11-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 3916 // CHECK11-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 3917 // CHECK11-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2 3918 // CHECK11-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 1 3919 // CHECK11-NEXT: [[CONV5:%.*]] = sext i8 [[TMP3]] to i32 3920 // CHECK11-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 3921 // CHECK11-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i8 3922 // CHECK11-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 1 3923 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 3924 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 3925 // CHECK11-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP4]], 1 3926 // CHECK11-NEXT: store i32 [[ADD8]], i32* [[ARRAYIDX]], align 4 3927 // CHECK11-NEXT: ret void 3928 // 3929 // 3930 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227 3931 // CHECK11-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { 3932 // CHECK11-NEXT: entry: 3933 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 3934 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 3935 // CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 3936 // CHECK11-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 3937 // CHECK11-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 3938 // CHECK11-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 3939 // CHECK11-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 3940 // CHECK11-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 3941 // CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 3942 // CHECK11-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 3943 // CHECK11-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 3944 // CHECK11-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 3945 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 3946 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 3947 // CHECK11-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 3948 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 3949 // CHECK11-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 3950 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 3951 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]]) 3952 // CHECK11-NEXT: ret void 3953 // 3954 // 3955 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..10 3956 // CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { 3957 // CHECK11-NEXT: entry: 3958 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 3959 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 3960 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 3961 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 3962 // CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 3963 // CHECK11-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 3964 // CHECK11-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 3965 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 3966 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 3967 // CHECK11-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 3968 // CHECK11-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 3969 // CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 3970 // CHECK11-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 3971 // CHECK11-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 3972 // CHECK11-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 3973 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 3974 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 3975 // CHECK11-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 3976 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 3977 // CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP4]] to double 3978 // CHECK11-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 3979 // CHECK11-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 3980 // CHECK11-NEXT: store double [[ADD]], double* [[A]], align 4 3981 // CHECK11-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 3982 // CHECK11-NEXT: [[TMP5:%.*]] = load double, double* [[A3]], align 4 3983 // CHECK11-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 3984 // CHECK11-NEXT: store double [[INC]], double* [[A3]], align 4 3985 // CHECK11-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 3986 // CHECK11-NEXT: [[TMP6:%.*]] = mul nsw i32 1, [[TMP2]] 3987 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP6]] 3988 // CHECK11-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 3989 // CHECK11-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 3990 // CHECK11-NEXT: ret void 3991 // 3992 // 3993 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192 3994 // CHECK11-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 3995 // CHECK11-NEXT: entry: 3996 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3997 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 3998 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 3999 // CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 4000 // CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 4001 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 4002 // CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 4003 // CHECK11-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 4004 // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 4005 // CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 4006 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 4007 // CHECK11-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 4008 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 4009 // CHECK11-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 4010 // CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 4011 // CHECK11-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 4012 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 4013 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) 4014 // CHECK11-NEXT: ret void 4015 // 4016 // 4017 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..11 4018 // CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 4019 // CHECK11-NEXT: entry: 4020 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 4021 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 4022 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 4023 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 4024 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 4025 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 4026 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 4027 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 4028 // CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 4029 // CHECK11-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 4030 // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 4031 // CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 4032 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 4033 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 4034 // CHECK11-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 4035 // CHECK11-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 4036 // CHECK11-NEXT: [[CONV1:%.*]] = sext i16 [[TMP2]] to i32 4037 // CHECK11-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 4038 // CHECK11-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 4039 // CHECK11-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2 4040 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 4041 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 4042 // CHECK11-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1 4043 // CHECK11-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4 4044 // CHECK11-NEXT: ret void 4045 // 4046