1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ 2 // Test host codegen. 3 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1 4 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 5 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK2 6 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK3 7 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 8 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK4 9 10 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK5 11 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 12 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK6 13 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK7 14 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 15 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK8 16 17 // Test target codegen - host bc file has to be created first. 18 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc 19 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9 20 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s 21 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK10 22 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc 23 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11 24 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s 25 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK12 26 27 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc 28 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK13 29 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s 30 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK14 31 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc 32 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK15 33 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s 34 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK16 35 36 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK17 37 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 38 // RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK18 39 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK19 40 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 41 // RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK20 42 43 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK21 44 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 45 // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK22 46 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK23 47 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 48 // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK24 49 50 // Test target codegen - host bc file has to be created first. 51 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc 52 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK25 53 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s 54 // RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK26 55 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc 56 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK27 57 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s 58 // RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK28 59 60 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc 61 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK29 62 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s 63 // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK30 64 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc 65 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK31 66 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s 67 // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK32 68 69 // expected-no-diagnostics 70 #ifndef HEADER 71 #define HEADER 72 73 74 75 76 // We have 8 target regions, but only 6 that actually will generate offloading 77 // code and have mapped arguments, and only 4 have all-constant map sizes. 78 79 80 81 // Check target registration is registered as a Ctor. 82 83 84 template<typename tx, typename ty> 85 struct TT{ 86 tx X; 87 ty Y; 88 }; 89 90 int global; 91 92 int foo(int n) { 93 int a = 0; 94 short aa = 0; 95 float b[10]; 96 float bn[n]; 97 double c[5][10]; 98 double cn[5][n]; 99 TT<long long, char> d; 100 101 #pragma omp target teams num_teams(a) thread_limit(a) firstprivate(aa) nowait 102 { 103 } 104 105 #pragma omp target teams if(target: 0) 106 { 107 a += 1; 108 } 109 110 111 #pragma omp target teams if(target: 1) 112 { 113 aa += 1; 114 } 115 116 117 118 #pragma omp target teams if(target: n>10) 119 { 120 a += 1; 121 aa += 1; 122 } 123 124 // We capture 3 VLA sizes in this target region 125 126 127 128 129 130 // The names below are not necessarily consistent with the names used for the 131 // addresses above as some are repeated. 132 133 134 135 136 137 138 139 140 141 142 #pragma omp target teams if(target: n>20) 143 { 144 a += 1; 145 b[2] += 1.0; 146 bn[3] += 1.0; 147 c[1][2] += 1.0; 148 cn[1][3] += 1.0; 149 d.X += 1; 150 d.Y += 1; 151 } 152 153 const int nn = 0; 154 #pragma omp target teams shared(nn) 155 #pragma omp parallel firstprivate(nn) 156 (void)nn; 157 #pragma omp target teams firstprivate(nn) 158 #pragma omp parallel shared(nn) 159 (void)nn; 160 return a; 161 } 162 163 // Check that the offloading functions are emitted and that the arguments are 164 // correct and loaded correctly for the target regions in foo(). 165 166 167 168 // Create stack storage and store argument in there. 169 170 // Create stack storage and store argument in there. 171 172 // Create stack storage and store argument in there. 173 174 // Create local storage for each capture. 175 176 177 178 // To reduce complexity, we're only going as far as validating the signature of the outlined parallel function. 179 180 181 void bazzzz(int n, int f[n]) { 182 #pragma omp target teams private(f) 183 ; 184 } 185 186 template<typename tx> 187 tx ftemplate(int n) { 188 tx a = 0; 189 short aa = 0; 190 tx b[10]; 191 192 #pragma omp target teams if(target: n>40) 193 { 194 a += 1; 195 aa += 1; 196 b[2] += 1; 197 } 198 199 return a; 200 } 201 202 static 203 int fstatic(int n) { 204 int a = 0; 205 short aa = 0; 206 char aaa = 0; 207 int b[10]; 208 209 #pragma omp target teams if(target: n>50) 210 { 211 a += 1; 212 aa += 1; 213 aaa += 1; 214 b[2] += 1; 215 } 216 217 return a; 218 } 219 220 struct S1 { 221 double a; 222 223 int r1(int n){ 224 int b = n+1; 225 short int c[2][n]; 226 227 #pragma omp target teams if(target: n>60) 228 { 229 this->a = (double)b + 1.5; 230 c[1][1] = ++a; 231 } 232 233 return c[1][1] + (int)b; 234 } 235 }; 236 237 int bar(int n){ 238 int a = 0; 239 240 a += foo(n); 241 242 S1 S; 243 a += S.r1(n); 244 245 a += fstatic(n); 246 247 a += ftemplate<int>(n); 248 249 return a; 250 } 251 252 253 254 // We capture 2 VLA sizes in this target region 255 256 257 // The names below are not necessarily consistent with the names used for the 258 // addresses above as some are repeated. 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 // Check that the offloading functions are emitted and that the arguments are 280 // correct and loaded correctly for the target regions of the callees of bar(). 281 282 // Create local storage for each capture. 283 // Store captures in the context. 284 285 286 // To reduce complexity, we're only going as far as validating the signature of the outlined parallel function. 287 288 289 // Create local storage for each capture. 290 // Store captures in the context. 291 292 293 294 295 // To reduce complexity, we're only going as far as validating the signature of the outlined parallel function. 296 297 // Create local storage for each capture. 298 // Store captures in the context. 299 300 301 302 // To reduce complexity, we're only going as far as validating the signature of the outlined parallel function. 303 304 #endif 305 // CHECK1-LABEL: define {{[^@]+}}@_Z3fooi 306 // CHECK1-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { 307 // CHECK1-NEXT: entry: 308 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 309 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4 310 // CHECK1-NEXT: [[AA:%.*]] = alloca i16, align 2 311 // CHECK1-NEXT: [[B:%.*]] = alloca [10 x float], align 4 312 // CHECK1-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 313 // CHECK1-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 314 // CHECK1-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 315 // CHECK1-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 316 // CHECK1-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 317 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 318 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 319 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 320 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 321 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED4:%.*]] = alloca i64, align 8 322 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 323 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 324 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 325 // CHECK1-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4 326 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 327 // CHECK1-NEXT: [[AA_CASTED7:%.*]] = alloca i64, align 8 328 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS9:%.*]] = alloca [1 x i8*], align 8 329 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS10:%.*]] = alloca [1 x i8*], align 8 330 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS11:%.*]] = alloca [1 x i8*], align 8 331 // CHECK1-NEXT: [[A_CASTED12:%.*]] = alloca i64, align 8 332 // CHECK1-NEXT: [[AA_CASTED14:%.*]] = alloca i64, align 8 333 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS16:%.*]] = alloca [2 x i8*], align 8 334 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS17:%.*]] = alloca [2 x i8*], align 8 335 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS18:%.*]] = alloca [2 x i8*], align 8 336 // CHECK1-NEXT: [[A_CASTED21:%.*]] = alloca i64, align 8 337 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS25:%.*]] = alloca [9 x i8*], align 8 338 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS26:%.*]] = alloca [9 x i8*], align 8 339 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS27:%.*]] = alloca [9 x i8*], align 8 340 // CHECK1-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [9 x i64], align 8 341 // CHECK1-NEXT: [[NN:%.*]] = alloca i32, align 4 342 // CHECK1-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 343 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS33:%.*]] = alloca [1 x i8*], align 8 344 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS34:%.*]] = alloca [1 x i8*], align 8 345 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS35:%.*]] = alloca [1 x i8*], align 8 346 // CHECK1-NEXT: [[NN_CASTED38:%.*]] = alloca i64, align 8 347 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS40:%.*]] = alloca [1 x i8*], align 8 348 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS41:%.*]] = alloca [1 x i8*], align 8 349 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS42:%.*]] = alloca [1 x i8*], align 8 350 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) 351 // CHECK1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 352 // CHECK1-NEXT: store i32 0, i32* [[A]], align 4 353 // CHECK1-NEXT: store i16 0, i16* [[AA]], align 2 354 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 355 // CHECK1-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 356 // CHECK1-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() 357 // CHECK1-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 358 // CHECK1-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP2]], align 4 359 // CHECK1-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 360 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 361 // CHECK1-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64 362 // CHECK1-NEXT: [[TMP6:%.*]] = mul nuw i64 5, [[TMP5]] 363 // CHECK1-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP6]], align 8 364 // CHECK1-NEXT: store i64 [[TMP5]], i64* [[__VLA_EXPR1]], align 8 365 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 366 // CHECK1-NEXT: store i32 [[TMP7]], i32* [[DOTCAPTURE_EXPR_]], align 4 367 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 368 // CHECK1-NEXT: store i32 [[TMP8]], i32* [[DOTCAPTURE_EXPR_2]], align 4 369 // CHECK1-NEXT: [[TMP9:%.*]] = load i16, i16* [[AA]], align 2 370 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 371 // CHECK1-NEXT: store i16 [[TMP9]], i16* [[CONV]], align 2 372 // CHECK1-NEXT: [[TMP10:%.*]] = load i64, i64* [[AA_CASTED]], align 8 373 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 374 // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* 375 // CHECK1-NEXT: store i32 [[TMP11]], i32* [[CONV3]], align 4 376 // CHECK1-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 377 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 378 // CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED4]] to i32* 379 // CHECK1-NEXT: store i32 [[TMP13]], i32* [[CONV5]], align 4 380 // CHECK1-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED4]], align 8 381 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 382 // CHECK1-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i64* 383 // CHECK1-NEXT: store i64 [[TMP10]], i64* [[TMP16]], align 8 384 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 385 // CHECK1-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64* 386 // CHECK1-NEXT: store i64 [[TMP10]], i64* [[TMP18]], align 8 387 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 388 // CHECK1-NEXT: store i8* null, i8** [[TMP19]], align 8 389 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 390 // CHECK1-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i64* 391 // CHECK1-NEXT: store i64 [[TMP12]], i64* [[TMP21]], align 8 392 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 393 // CHECK1-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i64* 394 // CHECK1-NEXT: store i64 [[TMP12]], i64* [[TMP23]], align 8 395 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 396 // CHECK1-NEXT: store i8* null, i8** [[TMP24]], align 8 397 // CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 398 // CHECK1-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i64* 399 // CHECK1-NEXT: store i64 [[TMP14]], i64* [[TMP26]], align 8 400 // CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 401 // CHECK1-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i64* 402 // CHECK1-NEXT: store i64 [[TMP14]], i64* [[TMP28]], align 8 403 // CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 404 // CHECK1-NEXT: store i8* null, i8** [[TMP29]], align 8 405 // CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 406 // CHECK1-NEXT: [[TMP31:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 407 // CHECK1-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 0 408 // CHECK1-NEXT: [[TMP33:%.*]] = load i16, i16* [[AA]], align 2 409 // CHECK1-NEXT: store i16 [[TMP33]], i16* [[TMP32]], align 4 410 // CHECK1-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 1 411 // CHECK1-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 412 // CHECK1-NEXT: store i32 [[TMP35]], i32* [[TMP34]], align 4 413 // CHECK1-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 2 414 // CHECK1-NEXT: [[TMP37:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 415 // CHECK1-NEXT: store i32 [[TMP37]], i32* [[TMP36]], align 4 416 // CHECK1-NEXT: [[TMP38:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i64 120, i64 12, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1) 417 // CHECK1-NEXT: [[TMP39:%.*]] = bitcast i8* [[TMP38]] to %struct.kmp_task_t_with_privates* 418 // CHECK1-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP39]], i32 0, i32 0 419 // CHECK1-NEXT: [[TMP41:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP40]], i32 0, i32 0 420 // CHECK1-NEXT: [[TMP42:%.*]] = load i8*, i8** [[TMP41]], align 8 421 // CHECK1-NEXT: [[TMP43:%.*]] = bitcast %struct.anon* [[AGG_CAPTURED]] to i8* 422 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP42]], i8* align 4 [[TMP43]], i64 12, i1 false) 423 // CHECK1-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP39]], i32 0, i32 1 424 // CHECK1-NEXT: [[TMP45:%.*]] = bitcast i8* [[TMP42]] to %struct.anon* 425 // CHECK1-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 0 426 // CHECK1-NEXT: [[TMP47:%.*]] = bitcast [3 x i8*]* [[TMP46]] to i8* 427 // CHECK1-NEXT: [[TMP48:%.*]] = bitcast i8** [[TMP30]] to i8* 428 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP47]], i8* align 8 [[TMP48]], i64 24, i1 false) 429 // CHECK1-NEXT: [[TMP49:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 1 430 // CHECK1-NEXT: [[TMP50:%.*]] = bitcast [3 x i8*]* [[TMP49]] to i8* 431 // CHECK1-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP31]] to i8* 432 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP50]], i8* align 8 [[TMP51]], i64 24, i1 false) 433 // CHECK1-NEXT: [[TMP52:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 2 434 // CHECK1-NEXT: [[TMP53:%.*]] = bitcast [3 x i64]* [[TMP52]] to i8* 435 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP53]], i8* align 8 bitcast ([3 x i64]* @.offload_sizes to i8*), i64 24, i1 false) 436 // CHECK1-NEXT: [[TMP54:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 3 437 // CHECK1-NEXT: [[TMP55:%.*]] = load i16, i16* [[AA]], align 2 438 // CHECK1-NEXT: store i16 [[TMP55]], i16* [[TMP54]], align 8 439 // CHECK1-NEXT: [[TMP56:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP38]]) 440 // CHECK1-NEXT: [[TMP57:%.*]] = load i32, i32* [[A]], align 4 441 // CHECK1-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32* 442 // CHECK1-NEXT: store i32 [[TMP57]], i32* [[CONV6]], align 4 443 // CHECK1-NEXT: [[TMP58:%.*]] = load i64, i64* [[A_CASTED]], align 8 444 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l105(i64 [[TMP58]]) #[[ATTR3:[0-9]+]] 445 // CHECK1-NEXT: [[TMP59:%.*]] = load i16, i16* [[AA]], align 2 446 // CHECK1-NEXT: [[CONV8:%.*]] = bitcast i64* [[AA_CASTED7]] to i16* 447 // CHECK1-NEXT: store i16 [[TMP59]], i16* [[CONV8]], align 2 448 // CHECK1-NEXT: [[TMP60:%.*]] = load i64, i64* [[AA_CASTED7]], align 8 449 // CHECK1-NEXT: [[TMP61:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS9]], i32 0, i32 0 450 // CHECK1-NEXT: [[TMP62:%.*]] = bitcast i8** [[TMP61]] to i64* 451 // CHECK1-NEXT: store i64 [[TMP60]], i64* [[TMP62]], align 8 452 // CHECK1-NEXT: [[TMP63:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS10]], i32 0, i32 0 453 // CHECK1-NEXT: [[TMP64:%.*]] = bitcast i8** [[TMP63]] to i64* 454 // CHECK1-NEXT: store i64 [[TMP60]], i64* [[TMP64]], align 8 455 // CHECK1-NEXT: [[TMP65:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS11]], i64 0, i64 0 456 // CHECK1-NEXT: store i8* null, i8** [[TMP65]], align 8 457 // CHECK1-NEXT: [[TMP66:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS9]], i32 0, i32 0 458 // CHECK1-NEXT: [[TMP67:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS10]], i32 0, i32 0 459 // CHECK1-NEXT: [[TMP68:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.region_id, i32 1, i8** [[TMP66]], i8** [[TMP67]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.4, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.5, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 460 // CHECK1-NEXT: [[TMP69:%.*]] = icmp ne i32 [[TMP68]], 0 461 // CHECK1-NEXT: br i1 [[TMP69]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 462 // CHECK1: omp_offload.failed: 463 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111(i64 [[TMP60]]) #[[ATTR3]] 464 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 465 // CHECK1: omp_offload.cont: 466 // CHECK1-NEXT: [[TMP70:%.*]] = load i32, i32* [[A]], align 4 467 // CHECK1-NEXT: [[CONV13:%.*]] = bitcast i64* [[A_CASTED12]] to i32* 468 // CHECK1-NEXT: store i32 [[TMP70]], i32* [[CONV13]], align 4 469 // CHECK1-NEXT: [[TMP71:%.*]] = load i64, i64* [[A_CASTED12]], align 8 470 // CHECK1-NEXT: [[TMP72:%.*]] = load i16, i16* [[AA]], align 2 471 // CHECK1-NEXT: [[CONV15:%.*]] = bitcast i64* [[AA_CASTED14]] to i16* 472 // CHECK1-NEXT: store i16 [[TMP72]], i16* [[CONV15]], align 2 473 // CHECK1-NEXT: [[TMP73:%.*]] = load i64, i64* [[AA_CASTED14]], align 8 474 // CHECK1-NEXT: [[TMP74:%.*]] = load i32, i32* [[N_ADDR]], align 4 475 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP74]], 10 476 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 477 // CHECK1: omp_if.then: 478 // CHECK1-NEXT: [[TMP75:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 0 479 // CHECK1-NEXT: [[TMP76:%.*]] = bitcast i8** [[TMP75]] to i64* 480 // CHECK1-NEXT: store i64 [[TMP71]], i64* [[TMP76]], align 8 481 // CHECK1-NEXT: [[TMP77:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 0 482 // CHECK1-NEXT: [[TMP78:%.*]] = bitcast i8** [[TMP77]] to i64* 483 // CHECK1-NEXT: store i64 [[TMP71]], i64* [[TMP78]], align 8 484 // CHECK1-NEXT: [[TMP79:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 0 485 // CHECK1-NEXT: store i8* null, i8** [[TMP79]], align 8 486 // CHECK1-NEXT: [[TMP80:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 1 487 // CHECK1-NEXT: [[TMP81:%.*]] = bitcast i8** [[TMP80]] to i64* 488 // CHECK1-NEXT: store i64 [[TMP73]], i64* [[TMP81]], align 8 489 // CHECK1-NEXT: [[TMP82:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 1 490 // CHECK1-NEXT: [[TMP83:%.*]] = bitcast i8** [[TMP82]] to i64* 491 // CHECK1-NEXT: store i64 [[TMP73]], i64* [[TMP83]], align 8 492 // CHECK1-NEXT: [[TMP84:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 1 493 // CHECK1-NEXT: store i8* null, i8** [[TMP84]], align 8 494 // CHECK1-NEXT: [[TMP85:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 0 495 // CHECK1-NEXT: [[TMP86:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 0 496 // CHECK1-NEXT: [[TMP87:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.region_id, i32 2, i8** [[TMP85]], i8** [[TMP86]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.7, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.8, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 497 // CHECK1-NEXT: [[TMP88:%.*]] = icmp ne i32 [[TMP87]], 0 498 // CHECK1-NEXT: br i1 [[TMP88]], label [[OMP_OFFLOAD_FAILED19:%.*]], label [[OMP_OFFLOAD_CONT20:%.*]] 499 // CHECK1: omp_offload.failed19: 500 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i64 [[TMP71]], i64 [[TMP73]]) #[[ATTR3]] 501 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT20]] 502 // CHECK1: omp_offload.cont20: 503 // CHECK1-NEXT: br label [[OMP_IF_END:%.*]] 504 // CHECK1: omp_if.else: 505 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i64 [[TMP71]], i64 [[TMP73]]) #[[ATTR3]] 506 // CHECK1-NEXT: br label [[OMP_IF_END]] 507 // CHECK1: omp_if.end: 508 // CHECK1-NEXT: [[TMP89:%.*]] = load i32, i32* [[A]], align 4 509 // CHECK1-NEXT: [[CONV22:%.*]] = bitcast i64* [[A_CASTED21]] to i32* 510 // CHECK1-NEXT: store i32 [[TMP89]], i32* [[CONV22]], align 4 511 // CHECK1-NEXT: [[TMP90:%.*]] = load i64, i64* [[A_CASTED21]], align 8 512 // CHECK1-NEXT: [[TMP91:%.*]] = load i32, i32* [[N_ADDR]], align 4 513 // CHECK1-NEXT: [[CMP23:%.*]] = icmp sgt i32 [[TMP91]], 20 514 // CHECK1-NEXT: br i1 [[CMP23]], label [[OMP_IF_THEN24:%.*]], label [[OMP_IF_ELSE30:%.*]] 515 // CHECK1: omp_if.then24: 516 // CHECK1-NEXT: [[TMP92:%.*]] = mul nuw i64 [[TMP2]], 4 517 // CHECK1-NEXT: [[TMP93:%.*]] = mul nuw i64 5, [[TMP5]] 518 // CHECK1-NEXT: [[TMP94:%.*]] = mul nuw i64 [[TMP93]], 8 519 // CHECK1-NEXT: [[TMP95:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 0 520 // CHECK1-NEXT: [[TMP96:%.*]] = bitcast i8** [[TMP95]] to i64* 521 // CHECK1-NEXT: store i64 [[TMP90]], i64* [[TMP96]], align 8 522 // CHECK1-NEXT: [[TMP97:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 0 523 // CHECK1-NEXT: [[TMP98:%.*]] = bitcast i8** [[TMP97]] to i64* 524 // CHECK1-NEXT: store i64 [[TMP90]], i64* [[TMP98]], align 8 525 // CHECK1-NEXT: [[TMP99:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 526 // CHECK1-NEXT: store i64 4, i64* [[TMP99]], align 8 527 // CHECK1-NEXT: [[TMP100:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 0 528 // CHECK1-NEXT: store i8* null, i8** [[TMP100]], align 8 529 // CHECK1-NEXT: [[TMP101:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 1 530 // CHECK1-NEXT: [[TMP102:%.*]] = bitcast i8** [[TMP101]] to [10 x float]** 531 // CHECK1-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP102]], align 8 532 // CHECK1-NEXT: [[TMP103:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 1 533 // CHECK1-NEXT: [[TMP104:%.*]] = bitcast i8** [[TMP103]] to [10 x float]** 534 // CHECK1-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP104]], align 8 535 // CHECK1-NEXT: [[TMP105:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 536 // CHECK1-NEXT: store i64 40, i64* [[TMP105]], align 8 537 // CHECK1-NEXT: [[TMP106:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 1 538 // CHECK1-NEXT: store i8* null, i8** [[TMP106]], align 8 539 // CHECK1-NEXT: [[TMP107:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 2 540 // CHECK1-NEXT: [[TMP108:%.*]] = bitcast i8** [[TMP107]] to i64* 541 // CHECK1-NEXT: store i64 [[TMP2]], i64* [[TMP108]], align 8 542 // CHECK1-NEXT: [[TMP109:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 2 543 // CHECK1-NEXT: [[TMP110:%.*]] = bitcast i8** [[TMP109]] to i64* 544 // CHECK1-NEXT: store i64 [[TMP2]], i64* [[TMP110]], align 8 545 // CHECK1-NEXT: [[TMP111:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 546 // CHECK1-NEXT: store i64 8, i64* [[TMP111]], align 8 547 // CHECK1-NEXT: [[TMP112:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 2 548 // CHECK1-NEXT: store i8* null, i8** [[TMP112]], align 8 549 // CHECK1-NEXT: [[TMP113:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 3 550 // CHECK1-NEXT: [[TMP114:%.*]] = bitcast i8** [[TMP113]] to float** 551 // CHECK1-NEXT: store float* [[VLA]], float** [[TMP114]], align 8 552 // CHECK1-NEXT: [[TMP115:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 3 553 // CHECK1-NEXT: [[TMP116:%.*]] = bitcast i8** [[TMP115]] to float** 554 // CHECK1-NEXT: store float* [[VLA]], float** [[TMP116]], align 8 555 // CHECK1-NEXT: [[TMP117:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 556 // CHECK1-NEXT: store i64 [[TMP92]], i64* [[TMP117]], align 8 557 // CHECK1-NEXT: [[TMP118:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 3 558 // CHECK1-NEXT: store i8* null, i8** [[TMP118]], align 8 559 // CHECK1-NEXT: [[TMP119:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 4 560 // CHECK1-NEXT: [[TMP120:%.*]] = bitcast i8** [[TMP119]] to [5 x [10 x double]]** 561 // CHECK1-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP120]], align 8 562 // CHECK1-NEXT: [[TMP121:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 4 563 // CHECK1-NEXT: [[TMP122:%.*]] = bitcast i8** [[TMP121]] to [5 x [10 x double]]** 564 // CHECK1-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP122]], align 8 565 // CHECK1-NEXT: [[TMP123:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 566 // CHECK1-NEXT: store i64 400, i64* [[TMP123]], align 8 567 // CHECK1-NEXT: [[TMP124:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 4 568 // CHECK1-NEXT: store i8* null, i8** [[TMP124]], align 8 569 // CHECK1-NEXT: [[TMP125:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 5 570 // CHECK1-NEXT: [[TMP126:%.*]] = bitcast i8** [[TMP125]] to i64* 571 // CHECK1-NEXT: store i64 5, i64* [[TMP126]], align 8 572 // CHECK1-NEXT: [[TMP127:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 5 573 // CHECK1-NEXT: [[TMP128:%.*]] = bitcast i8** [[TMP127]] to i64* 574 // CHECK1-NEXT: store i64 5, i64* [[TMP128]], align 8 575 // CHECK1-NEXT: [[TMP129:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 5 576 // CHECK1-NEXT: store i64 8, i64* [[TMP129]], align 8 577 // CHECK1-NEXT: [[TMP130:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 5 578 // CHECK1-NEXT: store i8* null, i8** [[TMP130]], align 8 579 // CHECK1-NEXT: [[TMP131:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 6 580 // CHECK1-NEXT: [[TMP132:%.*]] = bitcast i8** [[TMP131]] to i64* 581 // CHECK1-NEXT: store i64 [[TMP5]], i64* [[TMP132]], align 8 582 // CHECK1-NEXT: [[TMP133:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 6 583 // CHECK1-NEXT: [[TMP134:%.*]] = bitcast i8** [[TMP133]] to i64* 584 // CHECK1-NEXT: store i64 [[TMP5]], i64* [[TMP134]], align 8 585 // CHECK1-NEXT: [[TMP135:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 6 586 // CHECK1-NEXT: store i64 8, i64* [[TMP135]], align 8 587 // CHECK1-NEXT: [[TMP136:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 6 588 // CHECK1-NEXT: store i8* null, i8** [[TMP136]], align 8 589 // CHECK1-NEXT: [[TMP137:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 7 590 // CHECK1-NEXT: [[TMP138:%.*]] = bitcast i8** [[TMP137]] to double** 591 // CHECK1-NEXT: store double* [[VLA1]], double** [[TMP138]], align 8 592 // CHECK1-NEXT: [[TMP139:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 7 593 // CHECK1-NEXT: [[TMP140:%.*]] = bitcast i8** [[TMP139]] to double** 594 // CHECK1-NEXT: store double* [[VLA1]], double** [[TMP140]], align 8 595 // CHECK1-NEXT: [[TMP141:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 596 // CHECK1-NEXT: store i64 [[TMP94]], i64* [[TMP141]], align 8 597 // CHECK1-NEXT: [[TMP142:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 7 598 // CHECK1-NEXT: store i8* null, i8** [[TMP142]], align 8 599 // CHECK1-NEXT: [[TMP143:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 8 600 // CHECK1-NEXT: [[TMP144:%.*]] = bitcast i8** [[TMP143]] to %struct.TT** 601 // CHECK1-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP144]], align 8 602 // CHECK1-NEXT: [[TMP145:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 8 603 // CHECK1-NEXT: [[TMP146:%.*]] = bitcast i8** [[TMP145]] to %struct.TT** 604 // CHECK1-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP146]], align 8 605 // CHECK1-NEXT: [[TMP147:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 8 606 // CHECK1-NEXT: store i64 16, i64* [[TMP147]], align 8 607 // CHECK1-NEXT: [[TMP148:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 8 608 // CHECK1-NEXT: store i8* null, i8** [[TMP148]], align 8 609 // CHECK1-NEXT: [[TMP149:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 0 610 // CHECK1-NEXT: [[TMP150:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 0 611 // CHECK1-NEXT: [[TMP151:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 612 // CHECK1-NEXT: [[TMP152:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142.region_id, i32 9, i8** [[TMP149]], i8** [[TMP150]], i64* [[TMP151]], i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 613 // CHECK1-NEXT: [[TMP153:%.*]] = icmp ne i32 [[TMP152]], 0 614 // CHECK1-NEXT: br i1 [[TMP153]], label [[OMP_OFFLOAD_FAILED28:%.*]], label [[OMP_OFFLOAD_CONT29:%.*]] 615 // CHECK1: omp_offload.failed28: 616 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i64 [[TMP90]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR3]] 617 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT29]] 618 // CHECK1: omp_offload.cont29: 619 // CHECK1-NEXT: br label [[OMP_IF_END31:%.*]] 620 // CHECK1: omp_if.else30: 621 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i64 [[TMP90]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR3]] 622 // CHECK1-NEXT: br label [[OMP_IF_END31]] 623 // CHECK1: omp_if.end31: 624 // CHECK1-NEXT: store i32 0, i32* [[NN]], align 4 625 // CHECK1-NEXT: [[TMP154:%.*]] = load i32, i32* [[NN]], align 4 626 // CHECK1-NEXT: [[CONV32:%.*]] = bitcast i64* [[NN_CASTED]] to i32* 627 // CHECK1-NEXT: store i32 [[TMP154]], i32* [[CONV32]], align 4 628 // CHECK1-NEXT: [[TMP155:%.*]] = load i64, i64* [[NN_CASTED]], align 8 629 // CHECK1-NEXT: [[TMP156:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS33]], i32 0, i32 0 630 // CHECK1-NEXT: [[TMP157:%.*]] = bitcast i8** [[TMP156]] to i64* 631 // CHECK1-NEXT: store i64 [[TMP155]], i64* [[TMP157]], align 8 632 // CHECK1-NEXT: [[TMP158:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS34]], i32 0, i32 0 633 // CHECK1-NEXT: [[TMP159:%.*]] = bitcast i8** [[TMP158]] to i64* 634 // CHECK1-NEXT: store i64 [[TMP155]], i64* [[TMP159]], align 8 635 // CHECK1-NEXT: [[TMP160:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS35]], i64 0, i64 0 636 // CHECK1-NEXT: store i8* null, i8** [[TMP160]], align 8 637 // CHECK1-NEXT: [[TMP161:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS33]], i32 0, i32 0 638 // CHECK1-NEXT: [[TMP162:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS34]], i32 0, i32 0 639 // CHECK1-NEXT: [[TMP163:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154.region_id, i32 1, i8** [[TMP161]], i8** [[TMP162]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.13, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.14, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 640 // CHECK1-NEXT: [[TMP164:%.*]] = icmp ne i32 [[TMP163]], 0 641 // CHECK1-NEXT: br i1 [[TMP164]], label [[OMP_OFFLOAD_FAILED36:%.*]], label [[OMP_OFFLOAD_CONT37:%.*]] 642 // CHECK1: omp_offload.failed36: 643 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154(i64 [[TMP155]]) #[[ATTR3]] 644 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT37]] 645 // CHECK1: omp_offload.cont37: 646 // CHECK1-NEXT: [[TMP165:%.*]] = load i32, i32* [[NN]], align 4 647 // CHECK1-NEXT: [[CONV39:%.*]] = bitcast i64* [[NN_CASTED38]] to i32* 648 // CHECK1-NEXT: store i32 [[TMP165]], i32* [[CONV39]], align 4 649 // CHECK1-NEXT: [[TMP166:%.*]] = load i64, i64* [[NN_CASTED38]], align 8 650 // CHECK1-NEXT: [[TMP167:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS40]], i32 0, i32 0 651 // CHECK1-NEXT: [[TMP168:%.*]] = bitcast i8** [[TMP167]] to i64* 652 // CHECK1-NEXT: store i64 [[TMP166]], i64* [[TMP168]], align 8 653 // CHECK1-NEXT: [[TMP169:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS41]], i32 0, i32 0 654 // CHECK1-NEXT: [[TMP170:%.*]] = bitcast i8** [[TMP169]] to i64* 655 // CHECK1-NEXT: store i64 [[TMP166]], i64* [[TMP170]], align 8 656 // CHECK1-NEXT: [[TMP171:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS42]], i64 0, i64 0 657 // CHECK1-NEXT: store i8* null, i8** [[TMP171]], align 8 658 // CHECK1-NEXT: [[TMP172:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS40]], i32 0, i32 0 659 // CHECK1-NEXT: [[TMP173:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS41]], i32 0, i32 0 660 // CHECK1-NEXT: [[TMP174:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157.region_id, i32 1, i8** [[TMP172]], i8** [[TMP173]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.17, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.18, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 661 // CHECK1-NEXT: [[TMP175:%.*]] = icmp ne i32 [[TMP174]], 0 662 // CHECK1-NEXT: br i1 [[TMP175]], label [[OMP_OFFLOAD_FAILED43:%.*]], label [[OMP_OFFLOAD_CONT44:%.*]] 663 // CHECK1: omp_offload.failed43: 664 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157(i64 [[TMP166]]) #[[ATTR3]] 665 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT44]] 666 // CHECK1: omp_offload.cont44: 667 // CHECK1-NEXT: [[TMP176:%.*]] = load i32, i32* [[A]], align 4 668 // CHECK1-NEXT: [[TMP177:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 669 // CHECK1-NEXT: call void @llvm.stackrestore(i8* [[TMP177]]) 670 // CHECK1-NEXT: ret i32 [[TMP176]] 671 // 672 // 673 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101 674 // CHECK1-SAME: (i64 [[AA:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] { 675 // CHECK1-NEXT: entry: 676 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 677 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 678 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8 679 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 680 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 681 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 682 // CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 683 // CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8 684 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 685 // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* 686 // CHECK1-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32* 687 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 8 688 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 8 689 // CHECK1-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) 690 // CHECK1-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 8 691 // CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 692 // CHECK1-NEXT: store i16 [[TMP3]], i16* [[CONV5]], align 2 693 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 694 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]]) 695 // CHECK1-NEXT: ret void 696 // 697 // 698 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. 699 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] { 700 // CHECK1-NEXT: entry: 701 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 702 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 703 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 704 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 705 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 706 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 707 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 708 // CHECK1-NEXT: ret void 709 // 710 // 711 // CHECK1-LABEL: define {{[^@]+}}@.omp_task_privates_map. 712 // CHECK1-SAME: (%struct..kmp_privates.t* noalias [[TMP0:%.*]], i16** noalias [[TMP1:%.*]], [3 x i8*]** noalias [[TMP2:%.*]], [3 x i8*]** noalias [[TMP3:%.*]], [3 x i64]** noalias [[TMP4:%.*]]) #[[ATTR4:[0-9]+]] { 713 // CHECK1-NEXT: entry: 714 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 8 715 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i16**, align 8 716 // CHECK1-NEXT: [[DOTADDR2:%.*]] = alloca [3 x i8*]**, align 8 717 // CHECK1-NEXT: [[DOTADDR3:%.*]] = alloca [3 x i8*]**, align 8 718 // CHECK1-NEXT: [[DOTADDR4:%.*]] = alloca [3 x i64]**, align 8 719 // CHECK1-NEXT: store %struct..kmp_privates.t* [[TMP0]], %struct..kmp_privates.t** [[DOTADDR]], align 8 720 // CHECK1-NEXT: store i16** [[TMP1]], i16*** [[DOTADDR1]], align 8 721 // CHECK1-NEXT: store [3 x i8*]** [[TMP2]], [3 x i8*]*** [[DOTADDR2]], align 8 722 // CHECK1-NEXT: store [3 x i8*]** [[TMP3]], [3 x i8*]*** [[DOTADDR3]], align 8 723 // CHECK1-NEXT: store [3 x i64]** [[TMP4]], [3 x i64]*** [[DOTADDR4]], align 8 724 // CHECK1-NEXT: [[TMP5:%.*]] = load %struct..kmp_privates.t*, %struct..kmp_privates.t** [[DOTADDR]], align 8 725 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 0 726 // CHECK1-NEXT: [[TMP7:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR2]], align 8 727 // CHECK1-NEXT: store [3 x i8*]* [[TMP6]], [3 x i8*]** [[TMP7]], align 8 728 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 1 729 // CHECK1-NEXT: [[TMP9:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR3]], align 8 730 // CHECK1-NEXT: store [3 x i8*]* [[TMP8]], [3 x i8*]** [[TMP9]], align 8 731 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 2 732 // CHECK1-NEXT: [[TMP11:%.*]] = load [3 x i64]**, [3 x i64]*** [[DOTADDR4]], align 8 733 // CHECK1-NEXT: store [3 x i64]* [[TMP10]], [3 x i64]** [[TMP11]], align 8 734 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 3 735 // CHECK1-NEXT: [[TMP13:%.*]] = load i16**, i16*** [[DOTADDR1]], align 8 736 // CHECK1-NEXT: store i16* [[TMP12]], i16** [[TMP13]], align 8 737 // CHECK1-NEXT: ret void 738 // 739 // 740 // CHECK1-LABEL: define {{[^@]+}}@.omp_task_entry. 741 // CHECK1-SAME: (i32 signext [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { 742 // CHECK1-NEXT: entry: 743 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 744 // CHECK1-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 745 // CHECK1-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8 746 // CHECK1-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8 747 // CHECK1-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8 748 // CHECK1-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 8 749 // CHECK1-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca i16*, align 8 750 // CHECK1-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca [3 x i8*]*, align 8 751 // CHECK1-NEXT: [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca [3 x i8*]*, align 8 752 // CHECK1-NEXT: [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca [3 x i64]*, align 8 753 // CHECK1-NEXT: [[AA_CASTED_I:%.*]] = alloca i64, align 8 754 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED_I:%.*]] = alloca i64, align 8 755 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED5_I:%.*]] = alloca i64, align 8 756 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 757 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8 758 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 759 // CHECK1-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 760 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 761 // CHECK1-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 762 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0 763 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 764 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 765 // CHECK1-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 766 // CHECK1-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon* 767 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1 768 // CHECK1-NEXT: [[TMP10:%.*]] = bitcast %struct..kmp_privates.t* [[TMP9]] to i8* 769 // CHECK1-NEXT: [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8* 770 // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META14:![0-9]+]]) 771 // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META17:![0-9]+]]) 772 // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]]) 773 // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META21:![0-9]+]]) 774 // CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !23 775 // CHECK1-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !23 776 // CHECK1-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !23 777 // CHECK1-NEXT: store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* @.omp_task_privates_map. to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !23 778 // CHECK1-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !23 779 // CHECK1-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !23 780 // CHECK1-NEXT: [[TMP12:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !23 781 // CHECK1-NEXT: [[TMP13:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !23 782 // CHECK1-NEXT: [[TMP14:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !23 783 // CHECK1-NEXT: [[TMP15:%.*]] = bitcast void (i8*, ...)* [[TMP13]] to void (i8*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* 784 // CHECK1-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]] 785 // CHECK1-NEXT: [[TMP16:%.*]] = load i16*, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !23 786 // CHECK1-NEXT: [[TMP17:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !23 787 // CHECK1-NEXT: [[TMP18:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 8, !noalias !23 788 // CHECK1-NEXT: [[TMP19:%.*]] = load [3 x i64]*, [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 8, !noalias !23 789 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP17]], i64 0, i64 0 790 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP18]], i64 0, i64 0 791 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[TMP19]], i64 0, i64 0 792 // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP12]], i32 0, i32 1 793 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[TMP12]], i32 0, i32 2 794 // CHECK1-NEXT: [[TMP25:%.*]] = load i32, i32* [[TMP23]], align 4 795 // CHECK1-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP24]], align 4 796 // CHECK1-NEXT: [[TMP27:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 [[TMP25]], i32 [[TMP26]]) #[[ATTR3]] 797 // CHECK1-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0 798 // CHECK1-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]] 799 // CHECK1: omp_offload.failed.i: 800 // CHECK1-NEXT: [[TMP29:%.*]] = load i16, i16* [[TMP16]], align 2 801 // CHECK1-NEXT: [[CONV_I:%.*]] = bitcast i64* [[AA_CASTED_I]] to i16* 802 // CHECK1-NEXT: store i16 [[TMP29]], i16* [[CONV_I]], align 2, !noalias !23 803 // CHECK1-NEXT: [[TMP30:%.*]] = load i64, i64* [[AA_CASTED_I]], align 8, !noalias !23 804 // CHECK1-NEXT: [[TMP31:%.*]] = load i32, i32* [[TMP23]], align 4 805 // CHECK1-NEXT: [[CONV4_I:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED_I]] to i32* 806 // CHECK1-NEXT: store i32 [[TMP31]], i32* [[CONV4_I]], align 4, !noalias !23 807 // CHECK1-NEXT: [[TMP32:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED_I]], align 8, !noalias !23 808 // CHECK1-NEXT: [[TMP33:%.*]] = load i32, i32* [[TMP24]], align 4 809 // CHECK1-NEXT: [[CONV6_I:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED5_I]] to i32* 810 // CHECK1-NEXT: store i32 [[TMP33]], i32* [[CONV6_I]], align 4, !noalias !23 811 // CHECK1-NEXT: [[TMP34:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED5_I]], align 8, !noalias !23 812 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101(i64 [[TMP30]], i64 [[TMP32]], i64 [[TMP34]]) #[[ATTR3]] 813 // CHECK1-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]] 814 // CHECK1: .omp_outlined..1.exit: 815 // CHECK1-NEXT: ret i32 0 816 // 817 // 818 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l105 819 // CHECK1-SAME: (i64 [[A:%.*]]) #[[ATTR2]] { 820 // CHECK1-NEXT: entry: 821 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 822 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 823 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 824 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 825 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 826 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32* 827 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 828 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 829 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]]) 830 // CHECK1-NEXT: ret void 831 // 832 // 833 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..2 834 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]]) #[[ATTR2]] { 835 // CHECK1-NEXT: entry: 836 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 837 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 838 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 839 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 840 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 841 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 842 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 843 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 844 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 845 // CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 846 // CHECK1-NEXT: ret void 847 // 848 // 849 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 850 // CHECK1-SAME: (i64 [[AA:%.*]]) #[[ATTR2]] { 851 // CHECK1-NEXT: entry: 852 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 853 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 854 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 855 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 856 // CHECK1-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8 857 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 858 // CHECK1-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 859 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 860 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP1]]) 861 // CHECK1-NEXT: ret void 862 // 863 // 864 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..3 865 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] { 866 // CHECK1-NEXT: entry: 867 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 868 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 869 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 870 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 871 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 872 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 873 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 874 // CHECK1-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8 875 // CHECK1-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 876 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 877 // CHECK1-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 878 // CHECK1-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 8 879 // CHECK1-NEXT: ret void 880 // 881 // 882 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118 883 // CHECK1-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] { 884 // CHECK1-NEXT: entry: 885 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 886 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 887 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 888 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 889 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 890 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 891 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 892 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 893 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 894 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* 895 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 896 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 897 // CHECK1-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 898 // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 899 // CHECK1-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 900 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 901 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) 902 // CHECK1-NEXT: ret void 903 // 904 // 905 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..6 906 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] { 907 // CHECK1-NEXT: entry: 908 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 909 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 910 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 911 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 912 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 913 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 914 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 915 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 916 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 917 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 918 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 919 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 920 // CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 921 // CHECK1-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 8 922 // CHECK1-NEXT: [[CONV2:%.*]] = sext i16 [[TMP1]] to i32 923 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 924 // CHECK1-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 925 // CHECK1-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 8 926 // CHECK1-NEXT: ret void 927 // 928 // 929 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142 930 // CHECK1-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] { 931 // CHECK1-NEXT: entry: 932 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 933 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 934 // CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 935 // CHECK1-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 936 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 937 // CHECK1-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 938 // CHECK1-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 939 // CHECK1-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 940 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 941 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 942 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 943 // CHECK1-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 944 // CHECK1-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 945 // CHECK1-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 946 // CHECK1-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 947 // CHECK1-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 948 // CHECK1-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 949 // CHECK1-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 950 // CHECK1-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 951 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 952 // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 953 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 954 // CHECK1-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 955 // CHECK1-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 956 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 957 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 958 // CHECK1-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 959 // CHECK1-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 960 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 961 // CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* 962 // CHECK1-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4 963 // CHECK1-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 964 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) 965 // CHECK1-NEXT: ret void 966 // 967 // 968 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..9 969 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] { 970 // CHECK1-NEXT: entry: 971 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 972 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 973 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 974 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 975 // CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 976 // CHECK1-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 977 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 978 // CHECK1-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 979 // CHECK1-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 980 // CHECK1-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 981 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 982 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 983 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 984 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 985 // CHECK1-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 986 // CHECK1-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 987 // CHECK1-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 988 // CHECK1-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 989 // CHECK1-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 990 // CHECK1-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 991 // CHECK1-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 992 // CHECK1-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 993 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 994 // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 995 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 996 // CHECK1-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 997 // CHECK1-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 998 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 999 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 1000 // CHECK1-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 1001 // CHECK1-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 1002 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 1003 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 1004 // CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 1005 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 1006 // CHECK1-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 1007 // CHECK1-NEXT: [[CONV5:%.*]] = fpext float [[TMP9]] to double 1008 // CHECK1-NEXT: [[ADD6:%.*]] = fadd double [[CONV5]], 1.000000e+00 1009 // CHECK1-NEXT: [[CONV7:%.*]] = fptrunc double [[ADD6]] to float 1010 // CHECK1-NEXT: store float [[CONV7]], float* [[ARRAYIDX]], align 4 1011 // CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 1012 // CHECK1-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX8]], align 4 1013 // CHECK1-NEXT: [[CONV9:%.*]] = fpext float [[TMP10]] to double 1014 // CHECK1-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 1015 // CHECK1-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float 1016 // CHECK1-NEXT: store float [[CONV11]], float* [[ARRAYIDX8]], align 4 1017 // CHECK1-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1 1018 // CHECK1-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX12]], i64 0, i64 2 1019 // CHECK1-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX13]], align 8 1020 // CHECK1-NEXT: [[ADD14:%.*]] = fadd double [[TMP11]], 1.000000e+00 1021 // CHECK1-NEXT: store double [[ADD14]], double* [[ARRAYIDX13]], align 8 1022 // CHECK1-NEXT: [[TMP12:%.*]] = mul nsw i64 1, [[TMP5]] 1023 // CHECK1-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP12]] 1024 // CHECK1-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX15]], i64 3 1025 // CHECK1-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX16]], align 8 1026 // CHECK1-NEXT: [[ADD17:%.*]] = fadd double [[TMP13]], 1.000000e+00 1027 // CHECK1-NEXT: store double [[ADD17]], double* [[ARRAYIDX16]], align 8 1028 // CHECK1-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 1029 // CHECK1-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 8 1030 // CHECK1-NEXT: [[ADD18:%.*]] = add nsw i64 [[TMP14]], 1 1031 // CHECK1-NEXT: store i64 [[ADD18]], i64* [[X]], align 8 1032 // CHECK1-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 1033 // CHECK1-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 8 1034 // CHECK1-NEXT: [[CONV19:%.*]] = sext i8 [[TMP15]] to i32 1035 // CHECK1-NEXT: [[ADD20:%.*]] = add nsw i32 [[CONV19]], 1 1036 // CHECK1-NEXT: [[CONV21:%.*]] = trunc i32 [[ADD20]] to i8 1037 // CHECK1-NEXT: store i8 [[CONV21]], i8* [[Y]], align 8 1038 // CHECK1-NEXT: ret void 1039 // 1040 // 1041 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154 1042 // CHECK1-SAME: (i64 [[NN:%.*]]) #[[ATTR2]] { 1043 // CHECK1-NEXT: entry: 1044 // CHECK1-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 1045 // CHECK1-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 1046 // CHECK1-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 1047 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* 1048 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 1049 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32* 1050 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 1051 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8 1052 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP1]]) 1053 // CHECK1-NEXT: ret void 1054 // 1055 // 1056 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..11 1057 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[NN:%.*]]) #[[ATTR2]] { 1058 // CHECK1-NEXT: entry: 1059 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1060 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1061 // CHECK1-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 1062 // CHECK1-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 1063 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1064 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1065 // CHECK1-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 1066 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* 1067 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 1068 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32* 1069 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 1070 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8 1071 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..12 to void (i32*, i32*, ...)*), i64 [[TMP1]]) 1072 // CHECK1-NEXT: ret void 1073 // 1074 // 1075 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..12 1076 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[NN:%.*]]) #[[ATTR2]] { 1077 // CHECK1-NEXT: entry: 1078 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1079 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1080 // CHECK1-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 1081 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1082 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1083 // CHECK1-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 1084 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* 1085 // CHECK1-NEXT: ret void 1086 // 1087 // 1088 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157 1089 // CHECK1-SAME: (i64 [[NN:%.*]]) #[[ATTR2]] { 1090 // CHECK1-NEXT: entry: 1091 // CHECK1-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 1092 // CHECK1-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 1093 // CHECK1-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 1094 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* 1095 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 1096 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32* 1097 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 1098 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8 1099 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i64 [[TMP1]]) 1100 // CHECK1-NEXT: ret void 1101 // 1102 // 1103 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..15 1104 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[NN:%.*]]) #[[ATTR2]] { 1105 // CHECK1-NEXT: entry: 1106 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1107 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1108 // CHECK1-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 1109 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1110 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1111 // CHECK1-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 1112 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* 1113 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i32* [[CONV]]) 1114 // CHECK1-NEXT: ret void 1115 // 1116 // 1117 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..16 1118 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[NN:%.*]]) #[[ATTR2]] { 1119 // CHECK1-NEXT: entry: 1120 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1121 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1122 // CHECK1-NEXT: [[NN_ADDR:%.*]] = alloca i32*, align 8 1123 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1124 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1125 // CHECK1-NEXT: store i32* [[NN]], i32** [[NN_ADDR]], align 8 1126 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[NN_ADDR]], align 8 1127 // CHECK1-NEXT: ret void 1128 // 1129 // 1130 // CHECK1-LABEL: define {{[^@]+}}@_Z6bazzzziPi 1131 // CHECK1-SAME: (i32 signext [[N:%.*]], i32* [[F:%.*]]) #[[ATTR0]] { 1132 // CHECK1-NEXT: entry: 1133 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 1134 // CHECK1-NEXT: [[F_ADDR:%.*]] = alloca i32*, align 8 1135 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 1136 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 1137 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 1138 // CHECK1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 1139 // CHECK1-NEXT: store i32* [[F]], i32** [[F_ADDR]], align 8 1140 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 1141 // CHECK1-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 1142 // CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1143 // CHECK1-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to i64* 1144 // CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP3]], align 8 1145 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1146 // CHECK1-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i64* 1147 // CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP5]], align 8 1148 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 1149 // CHECK1-NEXT: store i8* null, i8** [[TMP6]], align 8 1150 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1151 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1152 // CHECK1-NEXT: [[TMP9:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182.region_id, i32 1, i8** [[TMP7]], i8** [[TMP8]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.20, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.21, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 1153 // CHECK1-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 1154 // CHECK1-NEXT: br i1 [[TMP10]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1155 // CHECK1: omp_offload.failed: 1156 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182(i64 [[TMP1]]) #[[ATTR3]] 1157 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 1158 // CHECK1: omp_offload.cont: 1159 // CHECK1-NEXT: ret void 1160 // 1161 // 1162 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182 1163 // CHECK1-SAME: (i64 [[VLA:%.*]]) #[[ATTR2]] { 1164 // CHECK1-NEXT: entry: 1165 // CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 1166 // CHECK1-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 1167 // CHECK1-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 1168 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..19 to void (i32*, i32*, ...)*), i64 [[TMP0]]) 1169 // CHECK1-NEXT: ret void 1170 // 1171 // 1172 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..19 1173 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[VLA:%.*]]) #[[ATTR2]] { 1174 // CHECK1-NEXT: entry: 1175 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1176 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1177 // CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 1178 // CHECK1-NEXT: [[F:%.*]] = alloca i32*, align 8 1179 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1180 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1181 // CHECK1-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 1182 // CHECK1-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 1183 // CHECK1-NEXT: ret void 1184 // 1185 // 1186 // CHECK1-LABEL: define {{[^@]+}}@_Z3bari 1187 // CHECK1-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { 1188 // CHECK1-NEXT: entry: 1189 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 1190 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4 1191 // CHECK1-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 1192 // CHECK1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 1193 // CHECK1-NEXT: store i32 0, i32* [[A]], align 4 1194 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 1195 // CHECK1-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]]) 1196 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 1197 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 1198 // CHECK1-NEXT: store i32 [[ADD]], i32* [[A]], align 4 1199 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 1200 // CHECK1-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]]) 1201 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 1202 // CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 1203 // CHECK1-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 1204 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 1205 // CHECK1-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]]) 1206 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 1207 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 1208 // CHECK1-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 1209 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 1210 // CHECK1-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]]) 1211 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 1212 // CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] 1213 // CHECK1-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 1214 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 1215 // CHECK1-NEXT: ret i32 [[TMP8]] 1216 // 1217 // 1218 // CHECK1-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 1219 // CHECK1-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { 1220 // CHECK1-NEXT: entry: 1221 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 1222 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 1223 // CHECK1-NEXT: [[B:%.*]] = alloca i32, align 4 1224 // CHECK1-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 1225 // CHECK1-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 1226 // CHECK1-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 1227 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8 1228 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8 1229 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8 1230 // CHECK1-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 8 1231 // CHECK1-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 1232 // CHECK1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 1233 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 1234 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 1235 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 1236 // CHECK1-NEXT: store i32 [[ADD]], i32* [[B]], align 4 1237 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 1238 // CHECK1-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 1239 // CHECK1-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() 1240 // CHECK1-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 1241 // CHECK1-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] 1242 // CHECK1-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 1243 // CHECK1-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 1244 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 1245 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32* 1246 // CHECK1-NEXT: store i32 [[TMP5]], i32* [[CONV]], align 4 1247 // CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 1248 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4 1249 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 60 1250 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 1251 // CHECK1: omp_if.then: 1252 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 1253 // CHECK1-NEXT: [[TMP8:%.*]] = mul nuw i64 2, [[TMP2]] 1254 // CHECK1-NEXT: [[TMP9:%.*]] = mul nuw i64 [[TMP8]], 2 1255 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1256 // CHECK1-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to %struct.S1** 1257 // CHECK1-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP11]], align 8 1258 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1259 // CHECK1-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to double** 1260 // CHECK1-NEXT: store double* [[A]], double** [[TMP13]], align 8 1261 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 1262 // CHECK1-NEXT: store i64 8, i64* [[TMP14]], align 8 1263 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 1264 // CHECK1-NEXT: store i8* null, i8** [[TMP15]], align 8 1265 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1266 // CHECK1-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64* 1267 // CHECK1-NEXT: store i64 [[TMP6]], i64* [[TMP17]], align 8 1268 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1269 // CHECK1-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64* 1270 // CHECK1-NEXT: store i64 [[TMP6]], i64* [[TMP19]], align 8 1271 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 1272 // CHECK1-NEXT: store i64 4, i64* [[TMP20]], align 8 1273 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 1274 // CHECK1-NEXT: store i8* null, i8** [[TMP21]], align 8 1275 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1276 // CHECK1-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i64* 1277 // CHECK1-NEXT: store i64 2, i64* [[TMP23]], align 8 1278 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1279 // CHECK1-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i64* 1280 // CHECK1-NEXT: store i64 2, i64* [[TMP25]], align 8 1281 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 1282 // CHECK1-NEXT: store i64 8, i64* [[TMP26]], align 8 1283 // CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 1284 // CHECK1-NEXT: store i8* null, i8** [[TMP27]], align 8 1285 // CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 1286 // CHECK1-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i64* 1287 // CHECK1-NEXT: store i64 [[TMP2]], i64* [[TMP29]], align 8 1288 // CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 1289 // CHECK1-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i64* 1290 // CHECK1-NEXT: store i64 [[TMP2]], i64* [[TMP31]], align 8 1291 // CHECK1-NEXT: [[TMP32:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 1292 // CHECK1-NEXT: store i64 8, i64* [[TMP32]], align 8 1293 // CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 1294 // CHECK1-NEXT: store i8* null, i8** [[TMP33]], align 8 1295 // CHECK1-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 1296 // CHECK1-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i16** 1297 // CHECK1-NEXT: store i16* [[VLA]], i16** [[TMP35]], align 8 1298 // CHECK1-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 1299 // CHECK1-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i16** 1300 // CHECK1-NEXT: store i16* [[VLA]], i16** [[TMP37]], align 8 1301 // CHECK1-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 1302 // CHECK1-NEXT: store i64 [[TMP9]], i64* [[TMP38]], align 8 1303 // CHECK1-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 1304 // CHECK1-NEXT: store i8* null, i8** [[TMP39]], align 8 1305 // CHECK1-NEXT: [[TMP40:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1306 // CHECK1-NEXT: [[TMP41:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1307 // CHECK1-NEXT: [[TMP42:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 1308 // CHECK1-NEXT: [[TMP43:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227.region_id, i32 5, i8** [[TMP40]], i8** [[TMP41]], i64* [[TMP42]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.23, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 1309 // CHECK1-NEXT: [[TMP44:%.*]] = icmp ne i32 [[TMP43]], 0 1310 // CHECK1-NEXT: br i1 [[TMP44]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1311 // CHECK1: omp_offload.failed: 1312 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR3]] 1313 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 1314 // CHECK1: omp_offload.cont: 1315 // CHECK1-NEXT: br label [[OMP_IF_END:%.*]] 1316 // CHECK1: omp_if.else: 1317 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR3]] 1318 // CHECK1-NEXT: br label [[OMP_IF_END]] 1319 // CHECK1: omp_if.end: 1320 // CHECK1-NEXT: [[TMP45:%.*]] = mul nsw i64 1, [[TMP2]] 1321 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP45]] 1322 // CHECK1-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 1323 // CHECK1-NEXT: [[TMP46:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2 1324 // CHECK1-NEXT: [[CONV3:%.*]] = sext i16 [[TMP46]] to i32 1325 // CHECK1-NEXT: [[TMP47:%.*]] = load i32, i32* [[B]], align 4 1326 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], [[TMP47]] 1327 // CHECK1-NEXT: [[TMP48:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 1328 // CHECK1-NEXT: call void @llvm.stackrestore(i8* [[TMP48]]) 1329 // CHECK1-NEXT: ret i32 [[ADD4]] 1330 // 1331 // 1332 // CHECK1-LABEL: define {{[^@]+}}@_ZL7fstatici 1333 // CHECK1-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { 1334 // CHECK1-NEXT: entry: 1335 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 1336 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4 1337 // CHECK1-NEXT: [[AA:%.*]] = alloca i16, align 2 1338 // CHECK1-NEXT: [[AAA:%.*]] = alloca i8, align 1 1339 // CHECK1-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 1340 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 1341 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 1342 // CHECK1-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 1343 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8 1344 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 1345 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 1346 // CHECK1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 1347 // CHECK1-NEXT: store i32 0, i32* [[A]], align 4 1348 // CHECK1-NEXT: store i16 0, i16* [[AA]], align 2 1349 // CHECK1-NEXT: store i8 0, i8* [[AAA]], align 1 1350 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 1351 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* 1352 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 1353 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 1354 // CHECK1-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 1355 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 1356 // CHECK1-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 1357 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 1358 // CHECK1-NEXT: [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1 1359 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* 1360 // CHECK1-NEXT: store i8 [[TMP4]], i8* [[CONV2]], align 1 1361 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 1362 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 1363 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50 1364 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 1365 // CHECK1: omp_if.then: 1366 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1367 // CHECK1-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* 1368 // CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8 1369 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1370 // CHECK1-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* 1371 // CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP10]], align 8 1372 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 1373 // CHECK1-NEXT: store i8* null, i8** [[TMP11]], align 8 1374 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1375 // CHECK1-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* 1376 // CHECK1-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8 1377 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1378 // CHECK1-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* 1379 // CHECK1-NEXT: store i64 [[TMP3]], i64* [[TMP15]], align 8 1380 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 1381 // CHECK1-NEXT: store i8* null, i8** [[TMP16]], align 8 1382 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1383 // CHECK1-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64* 1384 // CHECK1-NEXT: store i64 [[TMP5]], i64* [[TMP18]], align 8 1385 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1386 // CHECK1-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64* 1387 // CHECK1-NEXT: store i64 [[TMP5]], i64* [[TMP20]], align 8 1388 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 1389 // CHECK1-NEXT: store i8* null, i8** [[TMP21]], align 8 1390 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 1391 // CHECK1-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]** 1392 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 8 1393 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 1394 // CHECK1-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]** 1395 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 8 1396 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 1397 // CHECK1-NEXT: store i8* null, i8** [[TMP26]], align 8 1398 // CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1399 // CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1400 // CHECK1-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.25, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.26, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 1401 // CHECK1-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 1402 // CHECK1-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1403 // CHECK1: omp_offload.failed: 1404 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR3]] 1405 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 1406 // CHECK1: omp_offload.cont: 1407 // CHECK1-NEXT: br label [[OMP_IF_END:%.*]] 1408 // CHECK1: omp_if.else: 1409 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR3]] 1410 // CHECK1-NEXT: br label [[OMP_IF_END]] 1411 // CHECK1: omp_if.end: 1412 // CHECK1-NEXT: [[TMP31:%.*]] = load i32, i32* [[A]], align 4 1413 // CHECK1-NEXT: ret i32 [[TMP31]] 1414 // 1415 // 1416 // CHECK1-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 1417 // CHECK1-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { 1418 // CHECK1-NEXT: entry: 1419 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 1420 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4 1421 // CHECK1-NEXT: [[AA:%.*]] = alloca i16, align 2 1422 // CHECK1-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 1423 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 1424 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 1425 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 1426 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 1427 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 1428 // CHECK1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 1429 // CHECK1-NEXT: store i32 0, i32* [[A]], align 4 1430 // CHECK1-NEXT: store i16 0, i16* [[AA]], align 2 1431 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 1432 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* 1433 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 1434 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 1435 // CHECK1-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 1436 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 1437 // CHECK1-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 1438 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 1439 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 1440 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40 1441 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 1442 // CHECK1: omp_if.then: 1443 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1444 // CHECK1-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64* 1445 // CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP6]], align 8 1446 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1447 // CHECK1-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* 1448 // CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8 1449 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 1450 // CHECK1-NEXT: store i8* null, i8** [[TMP9]], align 8 1451 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1452 // CHECK1-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i64* 1453 // CHECK1-NEXT: store i64 [[TMP3]], i64* [[TMP11]], align 8 1454 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1455 // CHECK1-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* 1456 // CHECK1-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8 1457 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 1458 // CHECK1-NEXT: store i8* null, i8** [[TMP14]], align 8 1459 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1460 // CHECK1-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]** 1461 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 8 1462 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1463 // CHECK1-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]** 1464 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 8 1465 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 1466 // CHECK1-NEXT: store i8* null, i8** [[TMP19]], align 8 1467 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1468 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1469 // CHECK1-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.28, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.29, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 1470 // CHECK1-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 1471 // CHECK1-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1472 // CHECK1: omp_offload.failed: 1473 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]] 1474 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 1475 // CHECK1: omp_offload.cont: 1476 // CHECK1-NEXT: br label [[OMP_IF_END:%.*]] 1477 // CHECK1: omp_if.else: 1478 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]] 1479 // CHECK1-NEXT: br label [[OMP_IF_END]] 1480 // CHECK1: omp_if.end: 1481 // CHECK1-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4 1482 // CHECK1-NEXT: ret i32 [[TMP24]] 1483 // 1484 // 1485 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227 1486 // CHECK1-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { 1487 // CHECK1-NEXT: entry: 1488 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 1489 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 1490 // CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 1491 // CHECK1-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 1492 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 1493 // CHECK1-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 1494 // CHECK1-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 1495 // CHECK1-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 1496 // CHECK1-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 1497 // CHECK1-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 1498 // CHECK1-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 1499 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 1500 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 1501 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 1502 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 1503 // CHECK1-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 1504 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 1505 // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* 1506 // CHECK1-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 1507 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 1508 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..22 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) 1509 // CHECK1-NEXT: ret void 1510 // 1511 // 1512 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..22 1513 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { 1514 // CHECK1-NEXT: entry: 1515 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1516 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1517 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 1518 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 1519 // CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 1520 // CHECK1-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 1521 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 1522 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1523 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1524 // CHECK1-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 1525 // CHECK1-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 1526 // CHECK1-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 1527 // CHECK1-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 1528 // CHECK1-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 1529 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 1530 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 1531 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 1532 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 1533 // CHECK1-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 1534 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 1535 // CHECK1-NEXT: [[CONV3:%.*]] = sitofp i32 [[TMP4]] to double 1536 // CHECK1-NEXT: [[ADD:%.*]] = fadd double [[CONV3]], 1.500000e+00 1537 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 1538 // CHECK1-NEXT: store double [[ADD]], double* [[A]], align 8 1539 // CHECK1-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 1540 // CHECK1-NEXT: [[TMP5:%.*]] = load double, double* [[A4]], align 8 1541 // CHECK1-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 1542 // CHECK1-NEXT: store double [[INC]], double* [[A4]], align 8 1543 // CHECK1-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 1544 // CHECK1-NEXT: [[TMP6:%.*]] = mul nsw i64 1, [[TMP2]] 1545 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP6]] 1546 // CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 1547 // CHECK1-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2 1548 // CHECK1-NEXT: ret void 1549 // 1550 // 1551 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209 1552 // CHECK1-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 1553 // CHECK1-NEXT: entry: 1554 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1555 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 1556 // CHECK1-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 1557 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 1558 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 1559 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 1560 // CHECK1-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 1561 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 1562 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 1563 // CHECK1-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 1564 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 1565 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 1566 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 1567 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 1568 // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 1569 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 1570 // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* 1571 // CHECK1-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 1572 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 1573 // CHECK1-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 1574 // CHECK1-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 1575 // CHECK1-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 1576 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 1577 // CHECK1-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8 1578 // CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* 1579 // CHECK1-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 1580 // CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 1581 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..24 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) 1582 // CHECK1-NEXT: ret void 1583 // 1584 // 1585 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..24 1586 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 1587 // CHECK1-NEXT: entry: 1588 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1589 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1590 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1591 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 1592 // CHECK1-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 1593 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 1594 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1595 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1596 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 1597 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 1598 // CHECK1-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 1599 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 1600 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 1601 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 1602 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 1603 // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 1604 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 1605 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 1606 // CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 1607 // CHECK1-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 1608 // CHECK1-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32 1609 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 1610 // CHECK1-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 1611 // CHECK1-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 8 1612 // CHECK1-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 8 1613 // CHECK1-NEXT: [[CONV6:%.*]] = sext i8 [[TMP3]] to i32 1614 // CHECK1-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 1615 // CHECK1-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i8 1616 // CHECK1-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 8 1617 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 1618 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 1619 // CHECK1-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP4]], 1 1620 // CHECK1-NEXT: store i32 [[ADD9]], i32* [[ARRAYIDX]], align 4 1621 // CHECK1-NEXT: ret void 1622 // 1623 // 1624 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192 1625 // CHECK1-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 1626 // CHECK1-NEXT: entry: 1627 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1628 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 1629 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 1630 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 1631 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 1632 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 1633 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 1634 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 1635 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 1636 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 1637 // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 1638 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 1639 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* 1640 // CHECK1-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 1641 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 1642 // CHECK1-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 1643 // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 1644 // CHECK1-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 1645 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 1646 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..27 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) 1647 // CHECK1-NEXT: ret void 1648 // 1649 // 1650 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..27 1651 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 1652 // CHECK1-NEXT: entry: 1653 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1654 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1655 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1656 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 1657 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 1658 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1659 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1660 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 1661 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 1662 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 1663 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 1664 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 1665 // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 1666 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 1667 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 1668 // CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 1669 // CHECK1-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 1670 // CHECK1-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 1671 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 1672 // CHECK1-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 1673 // CHECK1-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 8 1674 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 1675 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 1676 // CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP3]], 1 1677 // CHECK1-NEXT: store i32 [[ADD5]], i32* [[ARRAYIDX]], align 4 1678 // CHECK1-NEXT: ret void 1679 // 1680 // 1681 // CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 1682 // CHECK1-SAME: () #[[ATTR4]] { 1683 // CHECK1-NEXT: entry: 1684 // CHECK1-NEXT: call void @__tgt_register_requires(i64 1) 1685 // CHECK1-NEXT: ret void 1686 // 1687 // 1688 // CHECK2-LABEL: define {{[^@]+}}@_Z3fooi 1689 // CHECK2-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { 1690 // CHECK2-NEXT: entry: 1691 // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 1692 // CHECK2-NEXT: [[A:%.*]] = alloca i32, align 4 1693 // CHECK2-NEXT: [[AA:%.*]] = alloca i16, align 2 1694 // CHECK2-NEXT: [[B:%.*]] = alloca [10 x float], align 4 1695 // CHECK2-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 1696 // CHECK2-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 1697 // CHECK2-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 1698 // CHECK2-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 1699 // CHECK2-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 1700 // CHECK2-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 1701 // CHECK2-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 1702 // CHECK2-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 1703 // CHECK2-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 1704 // CHECK2-NEXT: [[DOTCAPTURE_EXPR__CASTED4:%.*]] = alloca i64, align 8 1705 // CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 1706 // CHECK2-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 1707 // CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 1708 // CHECK2-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4 1709 // CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 1710 // CHECK2-NEXT: [[AA_CASTED7:%.*]] = alloca i64, align 8 1711 // CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS9:%.*]] = alloca [1 x i8*], align 8 1712 // CHECK2-NEXT: [[DOTOFFLOAD_PTRS10:%.*]] = alloca [1 x i8*], align 8 1713 // CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS11:%.*]] = alloca [1 x i8*], align 8 1714 // CHECK2-NEXT: [[A_CASTED12:%.*]] = alloca i64, align 8 1715 // CHECK2-NEXT: [[AA_CASTED14:%.*]] = alloca i64, align 8 1716 // CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS16:%.*]] = alloca [2 x i8*], align 8 1717 // CHECK2-NEXT: [[DOTOFFLOAD_PTRS17:%.*]] = alloca [2 x i8*], align 8 1718 // CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS18:%.*]] = alloca [2 x i8*], align 8 1719 // CHECK2-NEXT: [[A_CASTED21:%.*]] = alloca i64, align 8 1720 // CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS25:%.*]] = alloca [9 x i8*], align 8 1721 // CHECK2-NEXT: [[DOTOFFLOAD_PTRS26:%.*]] = alloca [9 x i8*], align 8 1722 // CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS27:%.*]] = alloca [9 x i8*], align 8 1723 // CHECK2-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [9 x i64], align 8 1724 // CHECK2-NEXT: [[NN:%.*]] = alloca i32, align 4 1725 // CHECK2-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 1726 // CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS33:%.*]] = alloca [1 x i8*], align 8 1727 // CHECK2-NEXT: [[DOTOFFLOAD_PTRS34:%.*]] = alloca [1 x i8*], align 8 1728 // CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS35:%.*]] = alloca [1 x i8*], align 8 1729 // CHECK2-NEXT: [[NN_CASTED38:%.*]] = alloca i64, align 8 1730 // CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS40:%.*]] = alloca [1 x i8*], align 8 1731 // CHECK2-NEXT: [[DOTOFFLOAD_PTRS41:%.*]] = alloca [1 x i8*], align 8 1732 // CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS42:%.*]] = alloca [1 x i8*], align 8 1733 // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) 1734 // CHECK2-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 1735 // CHECK2-NEXT: store i32 0, i32* [[A]], align 4 1736 // CHECK2-NEXT: store i16 0, i16* [[AA]], align 2 1737 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 1738 // CHECK2-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 1739 // CHECK2-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() 1740 // CHECK2-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 1741 // CHECK2-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP2]], align 4 1742 // CHECK2-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 1743 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 1744 // CHECK2-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64 1745 // CHECK2-NEXT: [[TMP6:%.*]] = mul nuw i64 5, [[TMP5]] 1746 // CHECK2-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP6]], align 8 1747 // CHECK2-NEXT: store i64 [[TMP5]], i64* [[__VLA_EXPR1]], align 8 1748 // CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 1749 // CHECK2-NEXT: store i32 [[TMP7]], i32* [[DOTCAPTURE_EXPR_]], align 4 1750 // CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 1751 // CHECK2-NEXT: store i32 [[TMP8]], i32* [[DOTCAPTURE_EXPR_2]], align 4 1752 // CHECK2-NEXT: [[TMP9:%.*]] = load i16, i16* [[AA]], align 2 1753 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 1754 // CHECK2-NEXT: store i16 [[TMP9]], i16* [[CONV]], align 2 1755 // CHECK2-NEXT: [[TMP10:%.*]] = load i64, i64* [[AA_CASTED]], align 8 1756 // CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 1757 // CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* 1758 // CHECK2-NEXT: store i32 [[TMP11]], i32* [[CONV3]], align 4 1759 // CHECK2-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 1760 // CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 1761 // CHECK2-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED4]] to i32* 1762 // CHECK2-NEXT: store i32 [[TMP13]], i32* [[CONV5]], align 4 1763 // CHECK2-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED4]], align 8 1764 // CHECK2-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1765 // CHECK2-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i64* 1766 // CHECK2-NEXT: store i64 [[TMP10]], i64* [[TMP16]], align 8 1767 // CHECK2-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1768 // CHECK2-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64* 1769 // CHECK2-NEXT: store i64 [[TMP10]], i64* [[TMP18]], align 8 1770 // CHECK2-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 1771 // CHECK2-NEXT: store i8* null, i8** [[TMP19]], align 8 1772 // CHECK2-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1773 // CHECK2-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i64* 1774 // CHECK2-NEXT: store i64 [[TMP12]], i64* [[TMP21]], align 8 1775 // CHECK2-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1776 // CHECK2-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i64* 1777 // CHECK2-NEXT: store i64 [[TMP12]], i64* [[TMP23]], align 8 1778 // CHECK2-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 1779 // CHECK2-NEXT: store i8* null, i8** [[TMP24]], align 8 1780 // CHECK2-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1781 // CHECK2-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i64* 1782 // CHECK2-NEXT: store i64 [[TMP14]], i64* [[TMP26]], align 8 1783 // CHECK2-NEXT: [[TMP27:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1784 // CHECK2-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i64* 1785 // CHECK2-NEXT: store i64 [[TMP14]], i64* [[TMP28]], align 8 1786 // CHECK2-NEXT: [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 1787 // CHECK2-NEXT: store i8* null, i8** [[TMP29]], align 8 1788 // CHECK2-NEXT: [[TMP30:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1789 // CHECK2-NEXT: [[TMP31:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1790 // CHECK2-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 0 1791 // CHECK2-NEXT: [[TMP33:%.*]] = load i16, i16* [[AA]], align 2 1792 // CHECK2-NEXT: store i16 [[TMP33]], i16* [[TMP32]], align 4 1793 // CHECK2-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 1 1794 // CHECK2-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 1795 // CHECK2-NEXT: store i32 [[TMP35]], i32* [[TMP34]], align 4 1796 // CHECK2-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 2 1797 // CHECK2-NEXT: [[TMP37:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 1798 // CHECK2-NEXT: store i32 [[TMP37]], i32* [[TMP36]], align 4 1799 // CHECK2-NEXT: [[TMP38:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i64 120, i64 12, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1) 1800 // CHECK2-NEXT: [[TMP39:%.*]] = bitcast i8* [[TMP38]] to %struct.kmp_task_t_with_privates* 1801 // CHECK2-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP39]], i32 0, i32 0 1802 // CHECK2-NEXT: [[TMP41:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP40]], i32 0, i32 0 1803 // CHECK2-NEXT: [[TMP42:%.*]] = load i8*, i8** [[TMP41]], align 8 1804 // CHECK2-NEXT: [[TMP43:%.*]] = bitcast %struct.anon* [[AGG_CAPTURED]] to i8* 1805 // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP42]], i8* align 4 [[TMP43]], i64 12, i1 false) 1806 // CHECK2-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP39]], i32 0, i32 1 1807 // CHECK2-NEXT: [[TMP45:%.*]] = bitcast i8* [[TMP42]] to %struct.anon* 1808 // CHECK2-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 0 1809 // CHECK2-NEXT: [[TMP47:%.*]] = bitcast [3 x i8*]* [[TMP46]] to i8* 1810 // CHECK2-NEXT: [[TMP48:%.*]] = bitcast i8** [[TMP30]] to i8* 1811 // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP47]], i8* align 8 [[TMP48]], i64 24, i1 false) 1812 // CHECK2-NEXT: [[TMP49:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 1 1813 // CHECK2-NEXT: [[TMP50:%.*]] = bitcast [3 x i8*]* [[TMP49]] to i8* 1814 // CHECK2-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP31]] to i8* 1815 // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP50]], i8* align 8 [[TMP51]], i64 24, i1 false) 1816 // CHECK2-NEXT: [[TMP52:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 2 1817 // CHECK2-NEXT: [[TMP53:%.*]] = bitcast [3 x i64]* [[TMP52]] to i8* 1818 // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP53]], i8* align 8 bitcast ([3 x i64]* @.offload_sizes to i8*), i64 24, i1 false) 1819 // CHECK2-NEXT: [[TMP54:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 3 1820 // CHECK2-NEXT: [[TMP55:%.*]] = load i16, i16* [[AA]], align 2 1821 // CHECK2-NEXT: store i16 [[TMP55]], i16* [[TMP54]], align 8 1822 // CHECK2-NEXT: [[TMP56:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP38]]) 1823 // CHECK2-NEXT: [[TMP57:%.*]] = load i32, i32* [[A]], align 4 1824 // CHECK2-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32* 1825 // CHECK2-NEXT: store i32 [[TMP57]], i32* [[CONV6]], align 4 1826 // CHECK2-NEXT: [[TMP58:%.*]] = load i64, i64* [[A_CASTED]], align 8 1827 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l105(i64 [[TMP58]]) #[[ATTR3:[0-9]+]] 1828 // CHECK2-NEXT: [[TMP59:%.*]] = load i16, i16* [[AA]], align 2 1829 // CHECK2-NEXT: [[CONV8:%.*]] = bitcast i64* [[AA_CASTED7]] to i16* 1830 // CHECK2-NEXT: store i16 [[TMP59]], i16* [[CONV8]], align 2 1831 // CHECK2-NEXT: [[TMP60:%.*]] = load i64, i64* [[AA_CASTED7]], align 8 1832 // CHECK2-NEXT: [[TMP61:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS9]], i32 0, i32 0 1833 // CHECK2-NEXT: [[TMP62:%.*]] = bitcast i8** [[TMP61]] to i64* 1834 // CHECK2-NEXT: store i64 [[TMP60]], i64* [[TMP62]], align 8 1835 // CHECK2-NEXT: [[TMP63:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS10]], i32 0, i32 0 1836 // CHECK2-NEXT: [[TMP64:%.*]] = bitcast i8** [[TMP63]] to i64* 1837 // CHECK2-NEXT: store i64 [[TMP60]], i64* [[TMP64]], align 8 1838 // CHECK2-NEXT: [[TMP65:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS11]], i64 0, i64 0 1839 // CHECK2-NEXT: store i8* null, i8** [[TMP65]], align 8 1840 // CHECK2-NEXT: [[TMP66:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS9]], i32 0, i32 0 1841 // CHECK2-NEXT: [[TMP67:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS10]], i32 0, i32 0 1842 // CHECK2-NEXT: [[TMP68:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.region_id, i32 1, i8** [[TMP66]], i8** [[TMP67]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.4, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.5, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 1843 // CHECK2-NEXT: [[TMP69:%.*]] = icmp ne i32 [[TMP68]], 0 1844 // CHECK2-NEXT: br i1 [[TMP69]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1845 // CHECK2: omp_offload.failed: 1846 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111(i64 [[TMP60]]) #[[ATTR3]] 1847 // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]] 1848 // CHECK2: omp_offload.cont: 1849 // CHECK2-NEXT: [[TMP70:%.*]] = load i32, i32* [[A]], align 4 1850 // CHECK2-NEXT: [[CONV13:%.*]] = bitcast i64* [[A_CASTED12]] to i32* 1851 // CHECK2-NEXT: store i32 [[TMP70]], i32* [[CONV13]], align 4 1852 // CHECK2-NEXT: [[TMP71:%.*]] = load i64, i64* [[A_CASTED12]], align 8 1853 // CHECK2-NEXT: [[TMP72:%.*]] = load i16, i16* [[AA]], align 2 1854 // CHECK2-NEXT: [[CONV15:%.*]] = bitcast i64* [[AA_CASTED14]] to i16* 1855 // CHECK2-NEXT: store i16 [[TMP72]], i16* [[CONV15]], align 2 1856 // CHECK2-NEXT: [[TMP73:%.*]] = load i64, i64* [[AA_CASTED14]], align 8 1857 // CHECK2-NEXT: [[TMP74:%.*]] = load i32, i32* [[N_ADDR]], align 4 1858 // CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP74]], 10 1859 // CHECK2-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 1860 // CHECK2: omp_if.then: 1861 // CHECK2-NEXT: [[TMP75:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 0 1862 // CHECK2-NEXT: [[TMP76:%.*]] = bitcast i8** [[TMP75]] to i64* 1863 // CHECK2-NEXT: store i64 [[TMP71]], i64* [[TMP76]], align 8 1864 // CHECK2-NEXT: [[TMP77:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 0 1865 // CHECK2-NEXT: [[TMP78:%.*]] = bitcast i8** [[TMP77]] to i64* 1866 // CHECK2-NEXT: store i64 [[TMP71]], i64* [[TMP78]], align 8 1867 // CHECK2-NEXT: [[TMP79:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 0 1868 // CHECK2-NEXT: store i8* null, i8** [[TMP79]], align 8 1869 // CHECK2-NEXT: [[TMP80:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 1 1870 // CHECK2-NEXT: [[TMP81:%.*]] = bitcast i8** [[TMP80]] to i64* 1871 // CHECK2-NEXT: store i64 [[TMP73]], i64* [[TMP81]], align 8 1872 // CHECK2-NEXT: [[TMP82:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 1 1873 // CHECK2-NEXT: [[TMP83:%.*]] = bitcast i8** [[TMP82]] to i64* 1874 // CHECK2-NEXT: store i64 [[TMP73]], i64* [[TMP83]], align 8 1875 // CHECK2-NEXT: [[TMP84:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 1 1876 // CHECK2-NEXT: store i8* null, i8** [[TMP84]], align 8 1877 // CHECK2-NEXT: [[TMP85:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 0 1878 // CHECK2-NEXT: [[TMP86:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 0 1879 // CHECK2-NEXT: [[TMP87:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.region_id, i32 2, i8** [[TMP85]], i8** [[TMP86]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.7, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.8, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 1880 // CHECK2-NEXT: [[TMP88:%.*]] = icmp ne i32 [[TMP87]], 0 1881 // CHECK2-NEXT: br i1 [[TMP88]], label [[OMP_OFFLOAD_FAILED19:%.*]], label [[OMP_OFFLOAD_CONT20:%.*]] 1882 // CHECK2: omp_offload.failed19: 1883 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i64 [[TMP71]], i64 [[TMP73]]) #[[ATTR3]] 1884 // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT20]] 1885 // CHECK2: omp_offload.cont20: 1886 // CHECK2-NEXT: br label [[OMP_IF_END:%.*]] 1887 // CHECK2: omp_if.else: 1888 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i64 [[TMP71]], i64 [[TMP73]]) #[[ATTR3]] 1889 // CHECK2-NEXT: br label [[OMP_IF_END]] 1890 // CHECK2: omp_if.end: 1891 // CHECK2-NEXT: [[TMP89:%.*]] = load i32, i32* [[A]], align 4 1892 // CHECK2-NEXT: [[CONV22:%.*]] = bitcast i64* [[A_CASTED21]] to i32* 1893 // CHECK2-NEXT: store i32 [[TMP89]], i32* [[CONV22]], align 4 1894 // CHECK2-NEXT: [[TMP90:%.*]] = load i64, i64* [[A_CASTED21]], align 8 1895 // CHECK2-NEXT: [[TMP91:%.*]] = load i32, i32* [[N_ADDR]], align 4 1896 // CHECK2-NEXT: [[CMP23:%.*]] = icmp sgt i32 [[TMP91]], 20 1897 // CHECK2-NEXT: br i1 [[CMP23]], label [[OMP_IF_THEN24:%.*]], label [[OMP_IF_ELSE30:%.*]] 1898 // CHECK2: omp_if.then24: 1899 // CHECK2-NEXT: [[TMP92:%.*]] = mul nuw i64 [[TMP2]], 4 1900 // CHECK2-NEXT: [[TMP93:%.*]] = mul nuw i64 5, [[TMP5]] 1901 // CHECK2-NEXT: [[TMP94:%.*]] = mul nuw i64 [[TMP93]], 8 1902 // CHECK2-NEXT: [[TMP95:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 0 1903 // CHECK2-NEXT: [[TMP96:%.*]] = bitcast i8** [[TMP95]] to i64* 1904 // CHECK2-NEXT: store i64 [[TMP90]], i64* [[TMP96]], align 8 1905 // CHECK2-NEXT: [[TMP97:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 0 1906 // CHECK2-NEXT: [[TMP98:%.*]] = bitcast i8** [[TMP97]] to i64* 1907 // CHECK2-NEXT: store i64 [[TMP90]], i64* [[TMP98]], align 8 1908 // CHECK2-NEXT: [[TMP99:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 1909 // CHECK2-NEXT: store i64 4, i64* [[TMP99]], align 8 1910 // CHECK2-NEXT: [[TMP100:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 0 1911 // CHECK2-NEXT: store i8* null, i8** [[TMP100]], align 8 1912 // CHECK2-NEXT: [[TMP101:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 1 1913 // CHECK2-NEXT: [[TMP102:%.*]] = bitcast i8** [[TMP101]] to [10 x float]** 1914 // CHECK2-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP102]], align 8 1915 // CHECK2-NEXT: [[TMP103:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 1 1916 // CHECK2-NEXT: [[TMP104:%.*]] = bitcast i8** [[TMP103]] to [10 x float]** 1917 // CHECK2-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP104]], align 8 1918 // CHECK2-NEXT: [[TMP105:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 1919 // CHECK2-NEXT: store i64 40, i64* [[TMP105]], align 8 1920 // CHECK2-NEXT: [[TMP106:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 1 1921 // CHECK2-NEXT: store i8* null, i8** [[TMP106]], align 8 1922 // CHECK2-NEXT: [[TMP107:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 2 1923 // CHECK2-NEXT: [[TMP108:%.*]] = bitcast i8** [[TMP107]] to i64* 1924 // CHECK2-NEXT: store i64 [[TMP2]], i64* [[TMP108]], align 8 1925 // CHECK2-NEXT: [[TMP109:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 2 1926 // CHECK2-NEXT: [[TMP110:%.*]] = bitcast i8** [[TMP109]] to i64* 1927 // CHECK2-NEXT: store i64 [[TMP2]], i64* [[TMP110]], align 8 1928 // CHECK2-NEXT: [[TMP111:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 1929 // CHECK2-NEXT: store i64 8, i64* [[TMP111]], align 8 1930 // CHECK2-NEXT: [[TMP112:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 2 1931 // CHECK2-NEXT: store i8* null, i8** [[TMP112]], align 8 1932 // CHECK2-NEXT: [[TMP113:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 3 1933 // CHECK2-NEXT: [[TMP114:%.*]] = bitcast i8** [[TMP113]] to float** 1934 // CHECK2-NEXT: store float* [[VLA]], float** [[TMP114]], align 8 1935 // CHECK2-NEXT: [[TMP115:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 3 1936 // CHECK2-NEXT: [[TMP116:%.*]] = bitcast i8** [[TMP115]] to float** 1937 // CHECK2-NEXT: store float* [[VLA]], float** [[TMP116]], align 8 1938 // CHECK2-NEXT: [[TMP117:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 1939 // CHECK2-NEXT: store i64 [[TMP92]], i64* [[TMP117]], align 8 1940 // CHECK2-NEXT: [[TMP118:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 3 1941 // CHECK2-NEXT: store i8* null, i8** [[TMP118]], align 8 1942 // CHECK2-NEXT: [[TMP119:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 4 1943 // CHECK2-NEXT: [[TMP120:%.*]] = bitcast i8** [[TMP119]] to [5 x [10 x double]]** 1944 // CHECK2-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP120]], align 8 1945 // CHECK2-NEXT: [[TMP121:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 4 1946 // CHECK2-NEXT: [[TMP122:%.*]] = bitcast i8** [[TMP121]] to [5 x [10 x double]]** 1947 // CHECK2-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP122]], align 8 1948 // CHECK2-NEXT: [[TMP123:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 1949 // CHECK2-NEXT: store i64 400, i64* [[TMP123]], align 8 1950 // CHECK2-NEXT: [[TMP124:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 4 1951 // CHECK2-NEXT: store i8* null, i8** [[TMP124]], align 8 1952 // CHECK2-NEXT: [[TMP125:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 5 1953 // CHECK2-NEXT: [[TMP126:%.*]] = bitcast i8** [[TMP125]] to i64* 1954 // CHECK2-NEXT: store i64 5, i64* [[TMP126]], align 8 1955 // CHECK2-NEXT: [[TMP127:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 5 1956 // CHECK2-NEXT: [[TMP128:%.*]] = bitcast i8** [[TMP127]] to i64* 1957 // CHECK2-NEXT: store i64 5, i64* [[TMP128]], align 8 1958 // CHECK2-NEXT: [[TMP129:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 5 1959 // CHECK2-NEXT: store i64 8, i64* [[TMP129]], align 8 1960 // CHECK2-NEXT: [[TMP130:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 5 1961 // CHECK2-NEXT: store i8* null, i8** [[TMP130]], align 8 1962 // CHECK2-NEXT: [[TMP131:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 6 1963 // CHECK2-NEXT: [[TMP132:%.*]] = bitcast i8** [[TMP131]] to i64* 1964 // CHECK2-NEXT: store i64 [[TMP5]], i64* [[TMP132]], align 8 1965 // CHECK2-NEXT: [[TMP133:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 6 1966 // CHECK2-NEXT: [[TMP134:%.*]] = bitcast i8** [[TMP133]] to i64* 1967 // CHECK2-NEXT: store i64 [[TMP5]], i64* [[TMP134]], align 8 1968 // CHECK2-NEXT: [[TMP135:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 6 1969 // CHECK2-NEXT: store i64 8, i64* [[TMP135]], align 8 1970 // CHECK2-NEXT: [[TMP136:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 6 1971 // CHECK2-NEXT: store i8* null, i8** [[TMP136]], align 8 1972 // CHECK2-NEXT: [[TMP137:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 7 1973 // CHECK2-NEXT: [[TMP138:%.*]] = bitcast i8** [[TMP137]] to double** 1974 // CHECK2-NEXT: store double* [[VLA1]], double** [[TMP138]], align 8 1975 // CHECK2-NEXT: [[TMP139:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 7 1976 // CHECK2-NEXT: [[TMP140:%.*]] = bitcast i8** [[TMP139]] to double** 1977 // CHECK2-NEXT: store double* [[VLA1]], double** [[TMP140]], align 8 1978 // CHECK2-NEXT: [[TMP141:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 1979 // CHECK2-NEXT: store i64 [[TMP94]], i64* [[TMP141]], align 8 1980 // CHECK2-NEXT: [[TMP142:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 7 1981 // CHECK2-NEXT: store i8* null, i8** [[TMP142]], align 8 1982 // CHECK2-NEXT: [[TMP143:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 8 1983 // CHECK2-NEXT: [[TMP144:%.*]] = bitcast i8** [[TMP143]] to %struct.TT** 1984 // CHECK2-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP144]], align 8 1985 // CHECK2-NEXT: [[TMP145:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 8 1986 // CHECK2-NEXT: [[TMP146:%.*]] = bitcast i8** [[TMP145]] to %struct.TT** 1987 // CHECK2-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP146]], align 8 1988 // CHECK2-NEXT: [[TMP147:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 8 1989 // CHECK2-NEXT: store i64 16, i64* [[TMP147]], align 8 1990 // CHECK2-NEXT: [[TMP148:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 8 1991 // CHECK2-NEXT: store i8* null, i8** [[TMP148]], align 8 1992 // CHECK2-NEXT: [[TMP149:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 0 1993 // CHECK2-NEXT: [[TMP150:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 0 1994 // CHECK2-NEXT: [[TMP151:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 1995 // CHECK2-NEXT: [[TMP152:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142.region_id, i32 9, i8** [[TMP149]], i8** [[TMP150]], i64* [[TMP151]], i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 1996 // CHECK2-NEXT: [[TMP153:%.*]] = icmp ne i32 [[TMP152]], 0 1997 // CHECK2-NEXT: br i1 [[TMP153]], label [[OMP_OFFLOAD_FAILED28:%.*]], label [[OMP_OFFLOAD_CONT29:%.*]] 1998 // CHECK2: omp_offload.failed28: 1999 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i64 [[TMP90]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR3]] 2000 // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT29]] 2001 // CHECK2: omp_offload.cont29: 2002 // CHECK2-NEXT: br label [[OMP_IF_END31:%.*]] 2003 // CHECK2: omp_if.else30: 2004 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i64 [[TMP90]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR3]] 2005 // CHECK2-NEXT: br label [[OMP_IF_END31]] 2006 // CHECK2: omp_if.end31: 2007 // CHECK2-NEXT: store i32 0, i32* [[NN]], align 4 2008 // CHECK2-NEXT: [[TMP154:%.*]] = load i32, i32* [[NN]], align 4 2009 // CHECK2-NEXT: [[CONV32:%.*]] = bitcast i64* [[NN_CASTED]] to i32* 2010 // CHECK2-NEXT: store i32 [[TMP154]], i32* [[CONV32]], align 4 2011 // CHECK2-NEXT: [[TMP155:%.*]] = load i64, i64* [[NN_CASTED]], align 8 2012 // CHECK2-NEXT: [[TMP156:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS33]], i32 0, i32 0 2013 // CHECK2-NEXT: [[TMP157:%.*]] = bitcast i8** [[TMP156]] to i64* 2014 // CHECK2-NEXT: store i64 [[TMP155]], i64* [[TMP157]], align 8 2015 // CHECK2-NEXT: [[TMP158:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS34]], i32 0, i32 0 2016 // CHECK2-NEXT: [[TMP159:%.*]] = bitcast i8** [[TMP158]] to i64* 2017 // CHECK2-NEXT: store i64 [[TMP155]], i64* [[TMP159]], align 8 2018 // CHECK2-NEXT: [[TMP160:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS35]], i64 0, i64 0 2019 // CHECK2-NEXT: store i8* null, i8** [[TMP160]], align 8 2020 // CHECK2-NEXT: [[TMP161:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS33]], i32 0, i32 0 2021 // CHECK2-NEXT: [[TMP162:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS34]], i32 0, i32 0 2022 // CHECK2-NEXT: [[TMP163:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154.region_id, i32 1, i8** [[TMP161]], i8** [[TMP162]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.13, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.14, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 2023 // CHECK2-NEXT: [[TMP164:%.*]] = icmp ne i32 [[TMP163]], 0 2024 // CHECK2-NEXT: br i1 [[TMP164]], label [[OMP_OFFLOAD_FAILED36:%.*]], label [[OMP_OFFLOAD_CONT37:%.*]] 2025 // CHECK2: omp_offload.failed36: 2026 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154(i64 [[TMP155]]) #[[ATTR3]] 2027 // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT37]] 2028 // CHECK2: omp_offload.cont37: 2029 // CHECK2-NEXT: [[TMP165:%.*]] = load i32, i32* [[NN]], align 4 2030 // CHECK2-NEXT: [[CONV39:%.*]] = bitcast i64* [[NN_CASTED38]] to i32* 2031 // CHECK2-NEXT: store i32 [[TMP165]], i32* [[CONV39]], align 4 2032 // CHECK2-NEXT: [[TMP166:%.*]] = load i64, i64* [[NN_CASTED38]], align 8 2033 // CHECK2-NEXT: [[TMP167:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS40]], i32 0, i32 0 2034 // CHECK2-NEXT: [[TMP168:%.*]] = bitcast i8** [[TMP167]] to i64* 2035 // CHECK2-NEXT: store i64 [[TMP166]], i64* [[TMP168]], align 8 2036 // CHECK2-NEXT: [[TMP169:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS41]], i32 0, i32 0 2037 // CHECK2-NEXT: [[TMP170:%.*]] = bitcast i8** [[TMP169]] to i64* 2038 // CHECK2-NEXT: store i64 [[TMP166]], i64* [[TMP170]], align 8 2039 // CHECK2-NEXT: [[TMP171:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS42]], i64 0, i64 0 2040 // CHECK2-NEXT: store i8* null, i8** [[TMP171]], align 8 2041 // CHECK2-NEXT: [[TMP172:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS40]], i32 0, i32 0 2042 // CHECK2-NEXT: [[TMP173:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS41]], i32 0, i32 0 2043 // CHECK2-NEXT: [[TMP174:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157.region_id, i32 1, i8** [[TMP172]], i8** [[TMP173]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.17, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.18, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 2044 // CHECK2-NEXT: [[TMP175:%.*]] = icmp ne i32 [[TMP174]], 0 2045 // CHECK2-NEXT: br i1 [[TMP175]], label [[OMP_OFFLOAD_FAILED43:%.*]], label [[OMP_OFFLOAD_CONT44:%.*]] 2046 // CHECK2: omp_offload.failed43: 2047 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157(i64 [[TMP166]]) #[[ATTR3]] 2048 // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT44]] 2049 // CHECK2: omp_offload.cont44: 2050 // CHECK2-NEXT: [[TMP176:%.*]] = load i32, i32* [[A]], align 4 2051 // CHECK2-NEXT: [[TMP177:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 2052 // CHECK2-NEXT: call void @llvm.stackrestore(i8* [[TMP177]]) 2053 // CHECK2-NEXT: ret i32 [[TMP176]] 2054 // 2055 // 2056 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101 2057 // CHECK2-SAME: (i64 [[AA:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] { 2058 // CHECK2-NEXT: entry: 2059 // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 2060 // CHECK2-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 2061 // CHECK2-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8 2062 // CHECK2-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 2063 // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 2064 // CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 2065 // CHECK2-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 2066 // CHECK2-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8 2067 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 2068 // CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* 2069 // CHECK2-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32* 2070 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 8 2071 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 8 2072 // CHECK2-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) 2073 // CHECK2-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 8 2074 // CHECK2-NEXT: [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 2075 // CHECK2-NEXT: store i16 [[TMP3]], i16* [[CONV5]], align 2 2076 // CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 2077 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]]) 2078 // CHECK2-NEXT: ret void 2079 // 2080 // 2081 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. 2082 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] { 2083 // CHECK2-NEXT: entry: 2084 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 2085 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 2086 // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 2087 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 2088 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 2089 // CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 2090 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 2091 // CHECK2-NEXT: ret void 2092 // 2093 // 2094 // CHECK2-LABEL: define {{[^@]+}}@.omp_task_privates_map. 2095 // CHECK2-SAME: (%struct..kmp_privates.t* noalias [[TMP0:%.*]], i16** noalias [[TMP1:%.*]], [3 x i8*]** noalias [[TMP2:%.*]], [3 x i8*]** noalias [[TMP3:%.*]], [3 x i64]** noalias [[TMP4:%.*]]) #[[ATTR4:[0-9]+]] { 2096 // CHECK2-NEXT: entry: 2097 // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 8 2098 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i16**, align 8 2099 // CHECK2-NEXT: [[DOTADDR2:%.*]] = alloca [3 x i8*]**, align 8 2100 // CHECK2-NEXT: [[DOTADDR3:%.*]] = alloca [3 x i8*]**, align 8 2101 // CHECK2-NEXT: [[DOTADDR4:%.*]] = alloca [3 x i64]**, align 8 2102 // CHECK2-NEXT: store %struct..kmp_privates.t* [[TMP0]], %struct..kmp_privates.t** [[DOTADDR]], align 8 2103 // CHECK2-NEXT: store i16** [[TMP1]], i16*** [[DOTADDR1]], align 8 2104 // CHECK2-NEXT: store [3 x i8*]** [[TMP2]], [3 x i8*]*** [[DOTADDR2]], align 8 2105 // CHECK2-NEXT: store [3 x i8*]** [[TMP3]], [3 x i8*]*** [[DOTADDR3]], align 8 2106 // CHECK2-NEXT: store [3 x i64]** [[TMP4]], [3 x i64]*** [[DOTADDR4]], align 8 2107 // CHECK2-NEXT: [[TMP5:%.*]] = load %struct..kmp_privates.t*, %struct..kmp_privates.t** [[DOTADDR]], align 8 2108 // CHECK2-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 0 2109 // CHECK2-NEXT: [[TMP7:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR2]], align 8 2110 // CHECK2-NEXT: store [3 x i8*]* [[TMP6]], [3 x i8*]** [[TMP7]], align 8 2111 // CHECK2-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 1 2112 // CHECK2-NEXT: [[TMP9:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR3]], align 8 2113 // CHECK2-NEXT: store [3 x i8*]* [[TMP8]], [3 x i8*]** [[TMP9]], align 8 2114 // CHECK2-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 2 2115 // CHECK2-NEXT: [[TMP11:%.*]] = load [3 x i64]**, [3 x i64]*** [[DOTADDR4]], align 8 2116 // CHECK2-NEXT: store [3 x i64]* [[TMP10]], [3 x i64]** [[TMP11]], align 8 2117 // CHECK2-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 3 2118 // CHECK2-NEXT: [[TMP13:%.*]] = load i16**, i16*** [[DOTADDR1]], align 8 2119 // CHECK2-NEXT: store i16* [[TMP12]], i16** [[TMP13]], align 8 2120 // CHECK2-NEXT: ret void 2121 // 2122 // 2123 // CHECK2-LABEL: define {{[^@]+}}@.omp_task_entry. 2124 // CHECK2-SAME: (i32 signext [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { 2125 // CHECK2-NEXT: entry: 2126 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 2127 // CHECK2-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 2128 // CHECK2-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8 2129 // CHECK2-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8 2130 // CHECK2-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8 2131 // CHECK2-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 8 2132 // CHECK2-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca i16*, align 8 2133 // CHECK2-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca [3 x i8*]*, align 8 2134 // CHECK2-NEXT: [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca [3 x i8*]*, align 8 2135 // CHECK2-NEXT: [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca [3 x i64]*, align 8 2136 // CHECK2-NEXT: [[AA_CASTED_I:%.*]] = alloca i64, align 8 2137 // CHECK2-NEXT: [[DOTCAPTURE_EXPR__CASTED_I:%.*]] = alloca i64, align 8 2138 // CHECK2-NEXT: [[DOTCAPTURE_EXPR__CASTED5_I:%.*]] = alloca i64, align 8 2139 // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 2140 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8 2141 // CHECK2-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 2142 // CHECK2-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 2143 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 2144 // CHECK2-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 2145 // CHECK2-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0 2146 // CHECK2-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 2147 // CHECK2-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 2148 // CHECK2-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 2149 // CHECK2-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon* 2150 // CHECK2-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1 2151 // CHECK2-NEXT: [[TMP10:%.*]] = bitcast %struct..kmp_privates.t* [[TMP9]] to i8* 2152 // CHECK2-NEXT: [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8* 2153 // CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META14:![0-9]+]]) 2154 // CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META17:![0-9]+]]) 2155 // CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]]) 2156 // CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META21:![0-9]+]]) 2157 // CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !23 2158 // CHECK2-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !23 2159 // CHECK2-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !23 2160 // CHECK2-NEXT: store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* @.omp_task_privates_map. to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !23 2161 // CHECK2-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !23 2162 // CHECK2-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !23 2163 // CHECK2-NEXT: [[TMP12:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !23 2164 // CHECK2-NEXT: [[TMP13:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !23 2165 // CHECK2-NEXT: [[TMP14:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !23 2166 // CHECK2-NEXT: [[TMP15:%.*]] = bitcast void (i8*, ...)* [[TMP13]] to void (i8*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* 2167 // CHECK2-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]] 2168 // CHECK2-NEXT: [[TMP16:%.*]] = load i16*, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !23 2169 // CHECK2-NEXT: [[TMP17:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !23 2170 // CHECK2-NEXT: [[TMP18:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 8, !noalias !23 2171 // CHECK2-NEXT: [[TMP19:%.*]] = load [3 x i64]*, [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 8, !noalias !23 2172 // CHECK2-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP17]], i64 0, i64 0 2173 // CHECK2-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP18]], i64 0, i64 0 2174 // CHECK2-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[TMP19]], i64 0, i64 0 2175 // CHECK2-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP12]], i32 0, i32 1 2176 // CHECK2-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[TMP12]], i32 0, i32 2 2177 // CHECK2-NEXT: [[TMP25:%.*]] = load i32, i32* [[TMP23]], align 4 2178 // CHECK2-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP24]], align 4 2179 // CHECK2-NEXT: [[TMP27:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 [[TMP25]], i32 [[TMP26]]) #[[ATTR3]] 2180 // CHECK2-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0 2181 // CHECK2-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]] 2182 // CHECK2: omp_offload.failed.i: 2183 // CHECK2-NEXT: [[TMP29:%.*]] = load i16, i16* [[TMP16]], align 2 2184 // CHECK2-NEXT: [[CONV_I:%.*]] = bitcast i64* [[AA_CASTED_I]] to i16* 2185 // CHECK2-NEXT: store i16 [[TMP29]], i16* [[CONV_I]], align 2, !noalias !23 2186 // CHECK2-NEXT: [[TMP30:%.*]] = load i64, i64* [[AA_CASTED_I]], align 8, !noalias !23 2187 // CHECK2-NEXT: [[TMP31:%.*]] = load i32, i32* [[TMP23]], align 4 2188 // CHECK2-NEXT: [[CONV4_I:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED_I]] to i32* 2189 // CHECK2-NEXT: store i32 [[TMP31]], i32* [[CONV4_I]], align 4, !noalias !23 2190 // CHECK2-NEXT: [[TMP32:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED_I]], align 8, !noalias !23 2191 // CHECK2-NEXT: [[TMP33:%.*]] = load i32, i32* [[TMP24]], align 4 2192 // CHECK2-NEXT: [[CONV6_I:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED5_I]] to i32* 2193 // CHECK2-NEXT: store i32 [[TMP33]], i32* [[CONV6_I]], align 4, !noalias !23 2194 // CHECK2-NEXT: [[TMP34:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED5_I]], align 8, !noalias !23 2195 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101(i64 [[TMP30]], i64 [[TMP32]], i64 [[TMP34]]) #[[ATTR3]] 2196 // CHECK2-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]] 2197 // CHECK2: .omp_outlined..1.exit: 2198 // CHECK2-NEXT: ret i32 0 2199 // 2200 // 2201 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l105 2202 // CHECK2-SAME: (i64 [[A:%.*]]) #[[ATTR2]] { 2203 // CHECK2-NEXT: entry: 2204 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 2205 // CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 2206 // CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 2207 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 2208 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 2209 // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32* 2210 // CHECK2-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 2211 // CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 2212 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]]) 2213 // CHECK2-NEXT: ret void 2214 // 2215 // 2216 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..2 2217 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]]) #[[ATTR2]] { 2218 // CHECK2-NEXT: entry: 2219 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 2220 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 2221 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 2222 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 2223 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 2224 // CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 2225 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 2226 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 2227 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 2228 // CHECK2-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 2229 // CHECK2-NEXT: ret void 2230 // 2231 // 2232 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 2233 // CHECK2-SAME: (i64 [[AA:%.*]]) #[[ATTR2]] { 2234 // CHECK2-NEXT: entry: 2235 // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 2236 // CHECK2-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 2237 // CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 2238 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 2239 // CHECK2-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8 2240 // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 2241 // CHECK2-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 2242 // CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 2243 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP1]]) 2244 // CHECK2-NEXT: ret void 2245 // 2246 // 2247 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..3 2248 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] { 2249 // CHECK2-NEXT: entry: 2250 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 2251 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 2252 // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 2253 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 2254 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 2255 // CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 2256 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 2257 // CHECK2-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8 2258 // CHECK2-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 2259 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 2260 // CHECK2-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 2261 // CHECK2-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 8 2262 // CHECK2-NEXT: ret void 2263 // 2264 // 2265 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118 2266 // CHECK2-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] { 2267 // CHECK2-NEXT: entry: 2268 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 2269 // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 2270 // CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 2271 // CHECK2-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 2272 // CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 2273 // CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 2274 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 2275 // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 2276 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 2277 // CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* 2278 // CHECK2-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 2279 // CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 2280 // CHECK2-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 2281 // CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 2282 // CHECK2-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 2283 // CHECK2-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 2284 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) 2285 // CHECK2-NEXT: ret void 2286 // 2287 // 2288 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..6 2289 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] { 2290 // CHECK2-NEXT: entry: 2291 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 2292 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 2293 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 2294 // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 2295 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 2296 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 2297 // CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 2298 // CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 2299 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 2300 // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 2301 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 2302 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 2303 // CHECK2-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 2304 // CHECK2-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 8 2305 // CHECK2-NEXT: [[CONV2:%.*]] = sext i16 [[TMP1]] to i32 2306 // CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 2307 // CHECK2-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 2308 // CHECK2-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 8 2309 // CHECK2-NEXT: ret void 2310 // 2311 // 2312 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142 2313 // CHECK2-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] { 2314 // CHECK2-NEXT: entry: 2315 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 2316 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 2317 // CHECK2-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 2318 // CHECK2-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 2319 // CHECK2-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 2320 // CHECK2-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 2321 // CHECK2-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 2322 // CHECK2-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 2323 // CHECK2-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 2324 // CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 2325 // CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 2326 // CHECK2-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 2327 // CHECK2-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 2328 // CHECK2-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 2329 // CHECK2-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 2330 // CHECK2-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 2331 // CHECK2-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 2332 // CHECK2-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 2333 // CHECK2-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 2334 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 2335 // CHECK2-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 2336 // CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 2337 // CHECK2-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 2338 // CHECK2-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 2339 // CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 2340 // CHECK2-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 2341 // CHECK2-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 2342 // CHECK2-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 2343 // CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 2344 // CHECK2-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* 2345 // CHECK2-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4 2346 // CHECK2-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 2347 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) 2348 // CHECK2-NEXT: ret void 2349 // 2350 // 2351 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..9 2352 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] { 2353 // CHECK2-NEXT: entry: 2354 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 2355 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 2356 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 2357 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 2358 // CHECK2-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 2359 // CHECK2-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 2360 // CHECK2-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 2361 // CHECK2-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 2362 // CHECK2-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 2363 // CHECK2-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 2364 // CHECK2-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 2365 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 2366 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 2367 // CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 2368 // CHECK2-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 2369 // CHECK2-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 2370 // CHECK2-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 2371 // CHECK2-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 2372 // CHECK2-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 2373 // CHECK2-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 2374 // CHECK2-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 2375 // CHECK2-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 2376 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 2377 // CHECK2-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 2378 // CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 2379 // CHECK2-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 2380 // CHECK2-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 2381 // CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 2382 // CHECK2-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 2383 // CHECK2-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 2384 // CHECK2-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 2385 // CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 2386 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 2387 // CHECK2-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 2388 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 2389 // CHECK2-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 2390 // CHECK2-NEXT: [[CONV5:%.*]] = fpext float [[TMP9]] to double 2391 // CHECK2-NEXT: [[ADD6:%.*]] = fadd double [[CONV5]], 1.000000e+00 2392 // CHECK2-NEXT: [[CONV7:%.*]] = fptrunc double [[ADD6]] to float 2393 // CHECK2-NEXT: store float [[CONV7]], float* [[ARRAYIDX]], align 4 2394 // CHECK2-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 2395 // CHECK2-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX8]], align 4 2396 // CHECK2-NEXT: [[CONV9:%.*]] = fpext float [[TMP10]] to double 2397 // CHECK2-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 2398 // CHECK2-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float 2399 // CHECK2-NEXT: store float [[CONV11]], float* [[ARRAYIDX8]], align 4 2400 // CHECK2-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1 2401 // CHECK2-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX12]], i64 0, i64 2 2402 // CHECK2-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX13]], align 8 2403 // CHECK2-NEXT: [[ADD14:%.*]] = fadd double [[TMP11]], 1.000000e+00 2404 // CHECK2-NEXT: store double [[ADD14]], double* [[ARRAYIDX13]], align 8 2405 // CHECK2-NEXT: [[TMP12:%.*]] = mul nsw i64 1, [[TMP5]] 2406 // CHECK2-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP12]] 2407 // CHECK2-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX15]], i64 3 2408 // CHECK2-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX16]], align 8 2409 // CHECK2-NEXT: [[ADD17:%.*]] = fadd double [[TMP13]], 1.000000e+00 2410 // CHECK2-NEXT: store double [[ADD17]], double* [[ARRAYIDX16]], align 8 2411 // CHECK2-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 2412 // CHECK2-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 8 2413 // CHECK2-NEXT: [[ADD18:%.*]] = add nsw i64 [[TMP14]], 1 2414 // CHECK2-NEXT: store i64 [[ADD18]], i64* [[X]], align 8 2415 // CHECK2-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 2416 // CHECK2-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 8 2417 // CHECK2-NEXT: [[CONV19:%.*]] = sext i8 [[TMP15]] to i32 2418 // CHECK2-NEXT: [[ADD20:%.*]] = add nsw i32 [[CONV19]], 1 2419 // CHECK2-NEXT: [[CONV21:%.*]] = trunc i32 [[ADD20]] to i8 2420 // CHECK2-NEXT: store i8 [[CONV21]], i8* [[Y]], align 8 2421 // CHECK2-NEXT: ret void 2422 // 2423 // 2424 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154 2425 // CHECK2-SAME: (i64 [[NN:%.*]]) #[[ATTR2]] { 2426 // CHECK2-NEXT: entry: 2427 // CHECK2-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 2428 // CHECK2-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 2429 // CHECK2-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 2430 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* 2431 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 2432 // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32* 2433 // CHECK2-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 2434 // CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8 2435 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP1]]) 2436 // CHECK2-NEXT: ret void 2437 // 2438 // 2439 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..11 2440 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[NN:%.*]]) #[[ATTR2]] { 2441 // CHECK2-NEXT: entry: 2442 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 2443 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 2444 // CHECK2-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 2445 // CHECK2-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 2446 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 2447 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 2448 // CHECK2-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 2449 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* 2450 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 2451 // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32* 2452 // CHECK2-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 2453 // CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8 2454 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..12 to void (i32*, i32*, ...)*), i64 [[TMP1]]) 2455 // CHECK2-NEXT: ret void 2456 // 2457 // 2458 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..12 2459 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[NN:%.*]]) #[[ATTR2]] { 2460 // CHECK2-NEXT: entry: 2461 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 2462 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 2463 // CHECK2-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 2464 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 2465 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 2466 // CHECK2-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 2467 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* 2468 // CHECK2-NEXT: ret void 2469 // 2470 // 2471 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157 2472 // CHECK2-SAME: (i64 [[NN:%.*]]) #[[ATTR2]] { 2473 // CHECK2-NEXT: entry: 2474 // CHECK2-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 2475 // CHECK2-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 2476 // CHECK2-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 2477 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* 2478 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 2479 // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32* 2480 // CHECK2-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 2481 // CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8 2482 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i64 [[TMP1]]) 2483 // CHECK2-NEXT: ret void 2484 // 2485 // 2486 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..15 2487 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[NN:%.*]]) #[[ATTR2]] { 2488 // CHECK2-NEXT: entry: 2489 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 2490 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 2491 // CHECK2-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 2492 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 2493 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 2494 // CHECK2-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 2495 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* 2496 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i32* [[CONV]]) 2497 // CHECK2-NEXT: ret void 2498 // 2499 // 2500 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..16 2501 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[NN:%.*]]) #[[ATTR2]] { 2502 // CHECK2-NEXT: entry: 2503 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 2504 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 2505 // CHECK2-NEXT: [[NN_ADDR:%.*]] = alloca i32*, align 8 2506 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 2507 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 2508 // CHECK2-NEXT: store i32* [[NN]], i32** [[NN_ADDR]], align 8 2509 // CHECK2-NEXT: [[TMP0:%.*]] = load i32*, i32** [[NN_ADDR]], align 8 2510 // CHECK2-NEXT: ret void 2511 // 2512 // 2513 // CHECK2-LABEL: define {{[^@]+}}@_Z6bazzzziPi 2514 // CHECK2-SAME: (i32 signext [[N:%.*]], i32* [[F:%.*]]) #[[ATTR0]] { 2515 // CHECK2-NEXT: entry: 2516 // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 2517 // CHECK2-NEXT: [[F_ADDR:%.*]] = alloca i32*, align 8 2518 // CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 2519 // CHECK2-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 2520 // CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 2521 // CHECK2-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 2522 // CHECK2-NEXT: store i32* [[F]], i32** [[F_ADDR]], align 8 2523 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 2524 // CHECK2-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 2525 // CHECK2-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2526 // CHECK2-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to i64* 2527 // CHECK2-NEXT: store i64 [[TMP1]], i64* [[TMP3]], align 8 2528 // CHECK2-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2529 // CHECK2-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i64* 2530 // CHECK2-NEXT: store i64 [[TMP1]], i64* [[TMP5]], align 8 2531 // CHECK2-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 2532 // CHECK2-NEXT: store i8* null, i8** [[TMP6]], align 8 2533 // CHECK2-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2534 // CHECK2-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2535 // CHECK2-NEXT: [[TMP9:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182.region_id, i32 1, i8** [[TMP7]], i8** [[TMP8]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.20, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.21, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 2536 // CHECK2-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 2537 // CHECK2-NEXT: br i1 [[TMP10]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 2538 // CHECK2: omp_offload.failed: 2539 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182(i64 [[TMP1]]) #[[ATTR3]] 2540 // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]] 2541 // CHECK2: omp_offload.cont: 2542 // CHECK2-NEXT: ret void 2543 // 2544 // 2545 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182 2546 // CHECK2-SAME: (i64 [[VLA:%.*]]) #[[ATTR2]] { 2547 // CHECK2-NEXT: entry: 2548 // CHECK2-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 2549 // CHECK2-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 2550 // CHECK2-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 2551 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..19 to void (i32*, i32*, ...)*), i64 [[TMP0]]) 2552 // CHECK2-NEXT: ret void 2553 // 2554 // 2555 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..19 2556 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[VLA:%.*]]) #[[ATTR2]] { 2557 // CHECK2-NEXT: entry: 2558 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 2559 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 2560 // CHECK2-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 2561 // CHECK2-NEXT: [[F:%.*]] = alloca i32*, align 8 2562 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 2563 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 2564 // CHECK2-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 2565 // CHECK2-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 2566 // CHECK2-NEXT: ret void 2567 // 2568 // 2569 // CHECK2-LABEL: define {{[^@]+}}@_Z3bari 2570 // CHECK2-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { 2571 // CHECK2-NEXT: entry: 2572 // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 2573 // CHECK2-NEXT: [[A:%.*]] = alloca i32, align 4 2574 // CHECK2-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 2575 // CHECK2-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 2576 // CHECK2-NEXT: store i32 0, i32* [[A]], align 4 2577 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 2578 // CHECK2-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]]) 2579 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 2580 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 2581 // CHECK2-NEXT: store i32 [[ADD]], i32* [[A]], align 4 2582 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 2583 // CHECK2-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]]) 2584 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 2585 // CHECK2-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 2586 // CHECK2-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 2587 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 2588 // CHECK2-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]]) 2589 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 2590 // CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 2591 // CHECK2-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 2592 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 2593 // CHECK2-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]]) 2594 // CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 2595 // CHECK2-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] 2596 // CHECK2-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 2597 // CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 2598 // CHECK2-NEXT: ret i32 [[TMP8]] 2599 // 2600 // 2601 // CHECK2-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 2602 // CHECK2-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { 2603 // CHECK2-NEXT: entry: 2604 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 2605 // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 2606 // CHECK2-NEXT: [[B:%.*]] = alloca i32, align 4 2607 // CHECK2-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 2608 // CHECK2-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 2609 // CHECK2-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 2610 // CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8 2611 // CHECK2-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8 2612 // CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8 2613 // CHECK2-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 8 2614 // CHECK2-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 2615 // CHECK2-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 2616 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 2617 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 2618 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 2619 // CHECK2-NEXT: store i32 [[ADD]], i32* [[B]], align 4 2620 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 2621 // CHECK2-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 2622 // CHECK2-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() 2623 // CHECK2-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 2624 // CHECK2-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] 2625 // CHECK2-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 2626 // CHECK2-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 2627 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 2628 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32* 2629 // CHECK2-NEXT: store i32 [[TMP5]], i32* [[CONV]], align 4 2630 // CHECK2-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 2631 // CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4 2632 // CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 60 2633 // CHECK2-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 2634 // CHECK2: omp_if.then: 2635 // CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 2636 // CHECK2-NEXT: [[TMP8:%.*]] = mul nuw i64 2, [[TMP2]] 2637 // CHECK2-NEXT: [[TMP9:%.*]] = mul nuw i64 [[TMP8]], 2 2638 // CHECK2-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2639 // CHECK2-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to %struct.S1** 2640 // CHECK2-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP11]], align 8 2641 // CHECK2-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2642 // CHECK2-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to double** 2643 // CHECK2-NEXT: store double* [[A]], double** [[TMP13]], align 8 2644 // CHECK2-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 2645 // CHECK2-NEXT: store i64 8, i64* [[TMP14]], align 8 2646 // CHECK2-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 2647 // CHECK2-NEXT: store i8* null, i8** [[TMP15]], align 8 2648 // CHECK2-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 2649 // CHECK2-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64* 2650 // CHECK2-NEXT: store i64 [[TMP6]], i64* [[TMP17]], align 8 2651 // CHECK2-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 2652 // CHECK2-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64* 2653 // CHECK2-NEXT: store i64 [[TMP6]], i64* [[TMP19]], align 8 2654 // CHECK2-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 2655 // CHECK2-NEXT: store i64 4, i64* [[TMP20]], align 8 2656 // CHECK2-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 2657 // CHECK2-NEXT: store i8* null, i8** [[TMP21]], align 8 2658 // CHECK2-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 2659 // CHECK2-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i64* 2660 // CHECK2-NEXT: store i64 2, i64* [[TMP23]], align 8 2661 // CHECK2-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 2662 // CHECK2-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i64* 2663 // CHECK2-NEXT: store i64 2, i64* [[TMP25]], align 8 2664 // CHECK2-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 2665 // CHECK2-NEXT: store i64 8, i64* [[TMP26]], align 8 2666 // CHECK2-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 2667 // CHECK2-NEXT: store i8* null, i8** [[TMP27]], align 8 2668 // CHECK2-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 2669 // CHECK2-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i64* 2670 // CHECK2-NEXT: store i64 [[TMP2]], i64* [[TMP29]], align 8 2671 // CHECK2-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 2672 // CHECK2-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i64* 2673 // CHECK2-NEXT: store i64 [[TMP2]], i64* [[TMP31]], align 8 2674 // CHECK2-NEXT: [[TMP32:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 2675 // CHECK2-NEXT: store i64 8, i64* [[TMP32]], align 8 2676 // CHECK2-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 2677 // CHECK2-NEXT: store i8* null, i8** [[TMP33]], align 8 2678 // CHECK2-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 2679 // CHECK2-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i16** 2680 // CHECK2-NEXT: store i16* [[VLA]], i16** [[TMP35]], align 8 2681 // CHECK2-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 2682 // CHECK2-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i16** 2683 // CHECK2-NEXT: store i16* [[VLA]], i16** [[TMP37]], align 8 2684 // CHECK2-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 2685 // CHECK2-NEXT: store i64 [[TMP9]], i64* [[TMP38]], align 8 2686 // CHECK2-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 2687 // CHECK2-NEXT: store i8* null, i8** [[TMP39]], align 8 2688 // CHECK2-NEXT: [[TMP40:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2689 // CHECK2-NEXT: [[TMP41:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2690 // CHECK2-NEXT: [[TMP42:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 2691 // CHECK2-NEXT: [[TMP43:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227.region_id, i32 5, i8** [[TMP40]], i8** [[TMP41]], i64* [[TMP42]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.23, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 2692 // CHECK2-NEXT: [[TMP44:%.*]] = icmp ne i32 [[TMP43]], 0 2693 // CHECK2-NEXT: br i1 [[TMP44]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 2694 // CHECK2: omp_offload.failed: 2695 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR3]] 2696 // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]] 2697 // CHECK2: omp_offload.cont: 2698 // CHECK2-NEXT: br label [[OMP_IF_END:%.*]] 2699 // CHECK2: omp_if.else: 2700 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR3]] 2701 // CHECK2-NEXT: br label [[OMP_IF_END]] 2702 // CHECK2: omp_if.end: 2703 // CHECK2-NEXT: [[TMP45:%.*]] = mul nsw i64 1, [[TMP2]] 2704 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP45]] 2705 // CHECK2-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 2706 // CHECK2-NEXT: [[TMP46:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2 2707 // CHECK2-NEXT: [[CONV3:%.*]] = sext i16 [[TMP46]] to i32 2708 // CHECK2-NEXT: [[TMP47:%.*]] = load i32, i32* [[B]], align 4 2709 // CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], [[TMP47]] 2710 // CHECK2-NEXT: [[TMP48:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 2711 // CHECK2-NEXT: call void @llvm.stackrestore(i8* [[TMP48]]) 2712 // CHECK2-NEXT: ret i32 [[ADD4]] 2713 // 2714 // 2715 // CHECK2-LABEL: define {{[^@]+}}@_ZL7fstatici 2716 // CHECK2-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { 2717 // CHECK2-NEXT: entry: 2718 // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 2719 // CHECK2-NEXT: [[A:%.*]] = alloca i32, align 4 2720 // CHECK2-NEXT: [[AA:%.*]] = alloca i16, align 2 2721 // CHECK2-NEXT: [[AAA:%.*]] = alloca i8, align 1 2722 // CHECK2-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 2723 // CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 2724 // CHECK2-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 2725 // CHECK2-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 2726 // CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8 2727 // CHECK2-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 2728 // CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 2729 // CHECK2-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 2730 // CHECK2-NEXT: store i32 0, i32* [[A]], align 4 2731 // CHECK2-NEXT: store i16 0, i16* [[AA]], align 2 2732 // CHECK2-NEXT: store i8 0, i8* [[AAA]], align 1 2733 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 2734 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* 2735 // CHECK2-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 2736 // CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 2737 // CHECK2-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 2738 // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 2739 // CHECK2-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 2740 // CHECK2-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 2741 // CHECK2-NEXT: [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1 2742 // CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* 2743 // CHECK2-NEXT: store i8 [[TMP4]], i8* [[CONV2]], align 1 2744 // CHECK2-NEXT: [[TMP5:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 2745 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 2746 // CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50 2747 // CHECK2-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 2748 // CHECK2: omp_if.then: 2749 // CHECK2-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2750 // CHECK2-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* 2751 // CHECK2-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8 2752 // CHECK2-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2753 // CHECK2-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* 2754 // CHECK2-NEXT: store i64 [[TMP1]], i64* [[TMP10]], align 8 2755 // CHECK2-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 2756 // CHECK2-NEXT: store i8* null, i8** [[TMP11]], align 8 2757 // CHECK2-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 2758 // CHECK2-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* 2759 // CHECK2-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8 2760 // CHECK2-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 2761 // CHECK2-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* 2762 // CHECK2-NEXT: store i64 [[TMP3]], i64* [[TMP15]], align 8 2763 // CHECK2-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 2764 // CHECK2-NEXT: store i8* null, i8** [[TMP16]], align 8 2765 // CHECK2-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 2766 // CHECK2-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64* 2767 // CHECK2-NEXT: store i64 [[TMP5]], i64* [[TMP18]], align 8 2768 // CHECK2-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 2769 // CHECK2-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64* 2770 // CHECK2-NEXT: store i64 [[TMP5]], i64* [[TMP20]], align 8 2771 // CHECK2-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 2772 // CHECK2-NEXT: store i8* null, i8** [[TMP21]], align 8 2773 // CHECK2-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 2774 // CHECK2-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]** 2775 // CHECK2-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 8 2776 // CHECK2-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 2777 // CHECK2-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]** 2778 // CHECK2-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 8 2779 // CHECK2-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 2780 // CHECK2-NEXT: store i8* null, i8** [[TMP26]], align 8 2781 // CHECK2-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2782 // CHECK2-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2783 // CHECK2-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.25, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.26, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 2784 // CHECK2-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 2785 // CHECK2-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 2786 // CHECK2: omp_offload.failed: 2787 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR3]] 2788 // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]] 2789 // CHECK2: omp_offload.cont: 2790 // CHECK2-NEXT: br label [[OMP_IF_END:%.*]] 2791 // CHECK2: omp_if.else: 2792 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR3]] 2793 // CHECK2-NEXT: br label [[OMP_IF_END]] 2794 // CHECK2: omp_if.end: 2795 // CHECK2-NEXT: [[TMP31:%.*]] = load i32, i32* [[A]], align 4 2796 // CHECK2-NEXT: ret i32 [[TMP31]] 2797 // 2798 // 2799 // CHECK2-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 2800 // CHECK2-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { 2801 // CHECK2-NEXT: entry: 2802 // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 2803 // CHECK2-NEXT: [[A:%.*]] = alloca i32, align 4 2804 // CHECK2-NEXT: [[AA:%.*]] = alloca i16, align 2 2805 // CHECK2-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 2806 // CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 2807 // CHECK2-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 2808 // CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 2809 // CHECK2-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 2810 // CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 2811 // CHECK2-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 2812 // CHECK2-NEXT: store i32 0, i32* [[A]], align 4 2813 // CHECK2-NEXT: store i16 0, i16* [[AA]], align 2 2814 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 2815 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* 2816 // CHECK2-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 2817 // CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 2818 // CHECK2-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 2819 // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 2820 // CHECK2-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 2821 // CHECK2-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 2822 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 2823 // CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40 2824 // CHECK2-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 2825 // CHECK2: omp_if.then: 2826 // CHECK2-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2827 // CHECK2-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64* 2828 // CHECK2-NEXT: store i64 [[TMP1]], i64* [[TMP6]], align 8 2829 // CHECK2-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2830 // CHECK2-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* 2831 // CHECK2-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8 2832 // CHECK2-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 2833 // CHECK2-NEXT: store i8* null, i8** [[TMP9]], align 8 2834 // CHECK2-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 2835 // CHECK2-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i64* 2836 // CHECK2-NEXT: store i64 [[TMP3]], i64* [[TMP11]], align 8 2837 // CHECK2-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 2838 // CHECK2-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* 2839 // CHECK2-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8 2840 // CHECK2-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 2841 // CHECK2-NEXT: store i8* null, i8** [[TMP14]], align 8 2842 // CHECK2-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 2843 // CHECK2-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]** 2844 // CHECK2-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 8 2845 // CHECK2-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 2846 // CHECK2-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]** 2847 // CHECK2-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 8 2848 // CHECK2-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 2849 // CHECK2-NEXT: store i8* null, i8** [[TMP19]], align 8 2850 // CHECK2-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2851 // CHECK2-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2852 // CHECK2-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.28, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.29, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 2853 // CHECK2-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 2854 // CHECK2-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 2855 // CHECK2: omp_offload.failed: 2856 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]] 2857 // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]] 2858 // CHECK2: omp_offload.cont: 2859 // CHECK2-NEXT: br label [[OMP_IF_END:%.*]] 2860 // CHECK2: omp_if.else: 2861 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]] 2862 // CHECK2-NEXT: br label [[OMP_IF_END]] 2863 // CHECK2: omp_if.end: 2864 // CHECK2-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4 2865 // CHECK2-NEXT: ret i32 [[TMP24]] 2866 // 2867 // 2868 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227 2869 // CHECK2-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { 2870 // CHECK2-NEXT: entry: 2871 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 2872 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 2873 // CHECK2-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 2874 // CHECK2-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 2875 // CHECK2-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 2876 // CHECK2-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 2877 // CHECK2-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 2878 // CHECK2-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 2879 // CHECK2-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 2880 // CHECK2-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 2881 // CHECK2-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 2882 // CHECK2-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 2883 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 2884 // CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 2885 // CHECK2-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 2886 // CHECK2-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 2887 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 2888 // CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* 2889 // CHECK2-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 2890 // CHECK2-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 2891 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..22 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) 2892 // CHECK2-NEXT: ret void 2893 // 2894 // 2895 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..22 2896 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { 2897 // CHECK2-NEXT: entry: 2898 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 2899 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 2900 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 2901 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 2902 // CHECK2-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 2903 // CHECK2-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 2904 // CHECK2-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 2905 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 2906 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 2907 // CHECK2-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 2908 // CHECK2-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 2909 // CHECK2-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 2910 // CHECK2-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 2911 // CHECK2-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 2912 // CHECK2-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 2913 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 2914 // CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 2915 // CHECK2-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 2916 // CHECK2-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 2917 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 2918 // CHECK2-NEXT: [[CONV3:%.*]] = sitofp i32 [[TMP4]] to double 2919 // CHECK2-NEXT: [[ADD:%.*]] = fadd double [[CONV3]], 1.500000e+00 2920 // CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 2921 // CHECK2-NEXT: store double [[ADD]], double* [[A]], align 8 2922 // CHECK2-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 2923 // CHECK2-NEXT: [[TMP5:%.*]] = load double, double* [[A4]], align 8 2924 // CHECK2-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 2925 // CHECK2-NEXT: store double [[INC]], double* [[A4]], align 8 2926 // CHECK2-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 2927 // CHECK2-NEXT: [[TMP6:%.*]] = mul nsw i64 1, [[TMP2]] 2928 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP6]] 2929 // CHECK2-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 2930 // CHECK2-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2 2931 // CHECK2-NEXT: ret void 2932 // 2933 // 2934 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209 2935 // CHECK2-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 2936 // CHECK2-NEXT: entry: 2937 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 2938 // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 2939 // CHECK2-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 2940 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 2941 // CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 2942 // CHECK2-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 2943 // CHECK2-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 2944 // CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 2945 // CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 2946 // CHECK2-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 2947 // CHECK2-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 2948 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 2949 // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 2950 // CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 2951 // CHECK2-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 2952 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 2953 // CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* 2954 // CHECK2-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 2955 // CHECK2-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 2956 // CHECK2-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 2957 // CHECK2-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 2958 // CHECK2-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 2959 // CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 2960 // CHECK2-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8 2961 // CHECK2-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* 2962 // CHECK2-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 2963 // CHECK2-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 2964 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..24 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) 2965 // CHECK2-NEXT: ret void 2966 // 2967 // 2968 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..24 2969 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 2970 // CHECK2-NEXT: entry: 2971 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 2972 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 2973 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 2974 // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 2975 // CHECK2-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 2976 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 2977 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 2978 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 2979 // CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 2980 // CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 2981 // CHECK2-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 2982 // CHECK2-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 2983 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 2984 // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 2985 // CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 2986 // CHECK2-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 2987 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 2988 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 2989 // CHECK2-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 2990 // CHECK2-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 2991 // CHECK2-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32 2992 // CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 2993 // CHECK2-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 2994 // CHECK2-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 8 2995 // CHECK2-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 8 2996 // CHECK2-NEXT: [[CONV6:%.*]] = sext i8 [[TMP3]] to i32 2997 // CHECK2-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 2998 // CHECK2-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i8 2999 // CHECK2-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 8 3000 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 3001 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 3002 // CHECK2-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP4]], 1 3003 // CHECK2-NEXT: store i32 [[ADD9]], i32* [[ARRAYIDX]], align 4 3004 // CHECK2-NEXT: ret void 3005 // 3006 // 3007 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192 3008 // CHECK2-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 3009 // CHECK2-NEXT: entry: 3010 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 3011 // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 3012 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 3013 // CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 3014 // CHECK2-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 3015 // CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 3016 // CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 3017 // CHECK2-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 3018 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 3019 // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 3020 // CHECK2-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 3021 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 3022 // CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* 3023 // CHECK2-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 3024 // CHECK2-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 3025 // CHECK2-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 3026 // CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 3027 // CHECK2-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 3028 // CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 3029 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..27 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) 3030 // CHECK2-NEXT: ret void 3031 // 3032 // 3033 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..27 3034 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 3035 // CHECK2-NEXT: entry: 3036 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 3037 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 3038 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 3039 // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 3040 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 3041 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 3042 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 3043 // CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 3044 // CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 3045 // CHECK2-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 3046 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 3047 // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 3048 // CHECK2-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 3049 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 3050 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 3051 // CHECK2-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 3052 // CHECK2-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 3053 // CHECK2-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 3054 // CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 3055 // CHECK2-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 3056 // CHECK2-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 8 3057 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 3058 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 3059 // CHECK2-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP3]], 1 3060 // CHECK2-NEXT: store i32 [[ADD5]], i32* [[ARRAYIDX]], align 4 3061 // CHECK2-NEXT: ret void 3062 // 3063 // 3064 // CHECK2-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 3065 // CHECK2-SAME: () #[[ATTR4]] { 3066 // CHECK2-NEXT: entry: 3067 // CHECK2-NEXT: call void @__tgt_register_requires(i64 1) 3068 // CHECK2-NEXT: ret void 3069 // 3070 // 3071 // CHECK3-LABEL: define {{[^@]+}}@_Z3fooi 3072 // CHECK3-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { 3073 // CHECK3-NEXT: entry: 3074 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 3075 // CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4 3076 // CHECK3-NEXT: [[AA:%.*]] = alloca i16, align 2 3077 // CHECK3-NEXT: [[B:%.*]] = alloca [10 x float], align 4 3078 // CHECK3-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 3079 // CHECK3-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 3080 // CHECK3-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 3081 // CHECK3-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 3082 // CHECK3-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 3083 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 3084 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 3085 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 3086 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 3087 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__CASTED3:%.*]] = alloca i32, align 4 3088 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 3089 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 3090 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 3091 // CHECK3-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4 3092 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 3093 // CHECK3-NEXT: [[AA_CASTED4:%.*]] = alloca i32, align 4 3094 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS6:%.*]] = alloca [1 x i8*], align 4 3095 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS7:%.*]] = alloca [1 x i8*], align 4 3096 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS8:%.*]] = alloca [1 x i8*], align 4 3097 // CHECK3-NEXT: [[A_CASTED9:%.*]] = alloca i32, align 4 3098 // CHECK3-NEXT: [[AA_CASTED10:%.*]] = alloca i32, align 4 3099 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS12:%.*]] = alloca [2 x i8*], align 4 3100 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS13:%.*]] = alloca [2 x i8*], align 4 3101 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS14:%.*]] = alloca [2 x i8*], align 4 3102 // CHECK3-NEXT: [[A_CASTED17:%.*]] = alloca i32, align 4 3103 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS20:%.*]] = alloca [9 x i8*], align 4 3104 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS21:%.*]] = alloca [9 x i8*], align 4 3105 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS22:%.*]] = alloca [9 x i8*], align 4 3106 // CHECK3-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [9 x i64], align 4 3107 // CHECK3-NEXT: [[NN:%.*]] = alloca i32, align 4 3108 // CHECK3-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4 3109 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS27:%.*]] = alloca [1 x i8*], align 4 3110 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS28:%.*]] = alloca [1 x i8*], align 4 3111 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS29:%.*]] = alloca [1 x i8*], align 4 3112 // CHECK3-NEXT: [[NN_CASTED32:%.*]] = alloca i32, align 4 3113 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS33:%.*]] = alloca [1 x i8*], align 4 3114 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS34:%.*]] = alloca [1 x i8*], align 4 3115 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS35:%.*]] = alloca [1 x i8*], align 4 3116 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) 3117 // CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 3118 // CHECK3-NEXT: store i32 0, i32* [[A]], align 4 3119 // CHECK3-NEXT: store i16 0, i16* [[AA]], align 2 3120 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 3121 // CHECK3-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() 3122 // CHECK3-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 3123 // CHECK3-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP1]], align 4 3124 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 3125 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 3126 // CHECK3-NEXT: [[TMP4:%.*]] = mul nuw i32 5, [[TMP3]] 3127 // CHECK3-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP4]], align 8 3128 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[__VLA_EXPR1]], align 4 3129 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 3130 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_]], align 4 3131 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 3132 // CHECK3-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_2]], align 4 3133 // CHECK3-NEXT: [[TMP7:%.*]] = load i16, i16* [[AA]], align 2 3134 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 3135 // CHECK3-NEXT: store i16 [[TMP7]], i16* [[CONV]], align 2 3136 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[AA_CASTED]], align 4 3137 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 3138 // CHECK3-NEXT: store i32 [[TMP9]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 3139 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 3140 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 3141 // CHECK3-NEXT: store i32 [[TMP11]], i32* [[DOTCAPTURE_EXPR__CASTED3]], align 4 3142 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED3]], align 4 3143 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3144 // CHECK3-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i32* 3145 // CHECK3-NEXT: store i32 [[TMP8]], i32* [[TMP14]], align 4 3146 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3147 // CHECK3-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i32* 3148 // CHECK3-NEXT: store i32 [[TMP8]], i32* [[TMP16]], align 4 3149 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 3150 // CHECK3-NEXT: store i8* null, i8** [[TMP17]], align 4 3151 // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 3152 // CHECK3-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32* 3153 // CHECK3-NEXT: store i32 [[TMP10]], i32* [[TMP19]], align 4 3154 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 3155 // CHECK3-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32* 3156 // CHECK3-NEXT: store i32 [[TMP10]], i32* [[TMP21]], align 4 3157 // CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 3158 // CHECK3-NEXT: store i8* null, i8** [[TMP22]], align 4 3159 // CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 3160 // CHECK3-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i32* 3161 // CHECK3-NEXT: store i32 [[TMP12]], i32* [[TMP24]], align 4 3162 // CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 3163 // CHECK3-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i32* 3164 // CHECK3-NEXT: store i32 [[TMP12]], i32* [[TMP26]], align 4 3165 // CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 3166 // CHECK3-NEXT: store i8* null, i8** [[TMP27]], align 4 3167 // CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3168 // CHECK3-NEXT: [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3169 // CHECK3-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 0 3170 // CHECK3-NEXT: [[TMP31:%.*]] = load i16, i16* [[AA]], align 2 3171 // CHECK3-NEXT: store i16 [[TMP31]], i16* [[TMP30]], align 4 3172 // CHECK3-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 1 3173 // CHECK3-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 3174 // CHECK3-NEXT: store i32 [[TMP33]], i32* [[TMP32]], align 4 3175 // CHECK3-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 2 3176 // CHECK3-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 3177 // CHECK3-NEXT: store i32 [[TMP35]], i32* [[TMP34]], align 4 3178 // CHECK3-NEXT: [[TMP36:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i32 72, i32 12, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1) 3179 // CHECK3-NEXT: [[TMP37:%.*]] = bitcast i8* [[TMP36]] to %struct.kmp_task_t_with_privates* 3180 // CHECK3-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP37]], i32 0, i32 0 3181 // CHECK3-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP38]], i32 0, i32 0 3182 // CHECK3-NEXT: [[TMP40:%.*]] = load i8*, i8** [[TMP39]], align 4 3183 // CHECK3-NEXT: [[TMP41:%.*]] = bitcast %struct.anon* [[AGG_CAPTURED]] to i8* 3184 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP40]], i8* align 4 [[TMP41]], i32 12, i1 false) 3185 // CHECK3-NEXT: [[TMP42:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP37]], i32 0, i32 1 3186 // CHECK3-NEXT: [[TMP43:%.*]] = bitcast i8* [[TMP40]] to %struct.anon* 3187 // CHECK3-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 0 3188 // CHECK3-NEXT: [[TMP45:%.*]] = bitcast [3 x i64]* [[TMP44]] to i8* 3189 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP45]], i8* align 4 bitcast ([3 x i64]* @.offload_sizes to i8*), i32 24, i1 false) 3190 // CHECK3-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 1 3191 // CHECK3-NEXT: [[TMP47:%.*]] = bitcast [3 x i8*]* [[TMP46]] to i8* 3192 // CHECK3-NEXT: [[TMP48:%.*]] = bitcast i8** [[TMP28]] to i8* 3193 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP47]], i8* align 4 [[TMP48]], i32 12, i1 false) 3194 // CHECK3-NEXT: [[TMP49:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 2 3195 // CHECK3-NEXT: [[TMP50:%.*]] = bitcast [3 x i8*]* [[TMP49]] to i8* 3196 // CHECK3-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP29]] to i8* 3197 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP50]], i8* align 4 [[TMP51]], i32 12, i1 false) 3198 // CHECK3-NEXT: [[TMP52:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 3 3199 // CHECK3-NEXT: [[TMP53:%.*]] = load i16, i16* [[AA]], align 2 3200 // CHECK3-NEXT: store i16 [[TMP53]], i16* [[TMP52]], align 4 3201 // CHECK3-NEXT: [[TMP54:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP36]]) 3202 // CHECK3-NEXT: [[TMP55:%.*]] = load i32, i32* [[A]], align 4 3203 // CHECK3-NEXT: store i32 [[TMP55]], i32* [[A_CASTED]], align 4 3204 // CHECK3-NEXT: [[TMP56:%.*]] = load i32, i32* [[A_CASTED]], align 4 3205 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l105(i32 [[TMP56]]) #[[ATTR3:[0-9]+]] 3206 // CHECK3-NEXT: [[TMP57:%.*]] = load i16, i16* [[AA]], align 2 3207 // CHECK3-NEXT: [[CONV5:%.*]] = bitcast i32* [[AA_CASTED4]] to i16* 3208 // CHECK3-NEXT: store i16 [[TMP57]], i16* [[CONV5]], align 2 3209 // CHECK3-NEXT: [[TMP58:%.*]] = load i32, i32* [[AA_CASTED4]], align 4 3210 // CHECK3-NEXT: [[TMP59:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0 3211 // CHECK3-NEXT: [[TMP60:%.*]] = bitcast i8** [[TMP59]] to i32* 3212 // CHECK3-NEXT: store i32 [[TMP58]], i32* [[TMP60]], align 4 3213 // CHECK3-NEXT: [[TMP61:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0 3214 // CHECK3-NEXT: [[TMP62:%.*]] = bitcast i8** [[TMP61]] to i32* 3215 // CHECK3-NEXT: store i32 [[TMP58]], i32* [[TMP62]], align 4 3216 // CHECK3-NEXT: [[TMP63:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS8]], i32 0, i32 0 3217 // CHECK3-NEXT: store i8* null, i8** [[TMP63]], align 4 3218 // CHECK3-NEXT: [[TMP64:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0 3219 // CHECK3-NEXT: [[TMP65:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0 3220 // CHECK3-NEXT: [[TMP66:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.region_id, i32 1, i8** [[TMP64]], i8** [[TMP65]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.4, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.5, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 3221 // CHECK3-NEXT: [[TMP67:%.*]] = icmp ne i32 [[TMP66]], 0 3222 // CHECK3-NEXT: br i1 [[TMP67]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 3223 // CHECK3: omp_offload.failed: 3224 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111(i32 [[TMP58]]) #[[ATTR3]] 3225 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 3226 // CHECK3: omp_offload.cont: 3227 // CHECK3-NEXT: [[TMP68:%.*]] = load i32, i32* [[A]], align 4 3228 // CHECK3-NEXT: store i32 [[TMP68]], i32* [[A_CASTED9]], align 4 3229 // CHECK3-NEXT: [[TMP69:%.*]] = load i32, i32* [[A_CASTED9]], align 4 3230 // CHECK3-NEXT: [[TMP70:%.*]] = load i16, i16* [[AA]], align 2 3231 // CHECK3-NEXT: [[CONV11:%.*]] = bitcast i32* [[AA_CASTED10]] to i16* 3232 // CHECK3-NEXT: store i16 [[TMP70]], i16* [[CONV11]], align 2 3233 // CHECK3-NEXT: [[TMP71:%.*]] = load i32, i32* [[AA_CASTED10]], align 4 3234 // CHECK3-NEXT: [[TMP72:%.*]] = load i32, i32* [[N_ADDR]], align 4 3235 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP72]], 10 3236 // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 3237 // CHECK3: omp_if.then: 3238 // CHECK3-NEXT: [[TMP73:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS12]], i32 0, i32 0 3239 // CHECK3-NEXT: [[TMP74:%.*]] = bitcast i8** [[TMP73]] to i32* 3240 // CHECK3-NEXT: store i32 [[TMP69]], i32* [[TMP74]], align 4 3241 // CHECK3-NEXT: [[TMP75:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS13]], i32 0, i32 0 3242 // CHECK3-NEXT: [[TMP76:%.*]] = bitcast i8** [[TMP75]] to i32* 3243 // CHECK3-NEXT: store i32 [[TMP69]], i32* [[TMP76]], align 4 3244 // CHECK3-NEXT: [[TMP77:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS14]], i32 0, i32 0 3245 // CHECK3-NEXT: store i8* null, i8** [[TMP77]], align 4 3246 // CHECK3-NEXT: [[TMP78:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS12]], i32 0, i32 1 3247 // CHECK3-NEXT: [[TMP79:%.*]] = bitcast i8** [[TMP78]] to i32* 3248 // CHECK3-NEXT: store i32 [[TMP71]], i32* [[TMP79]], align 4 3249 // CHECK3-NEXT: [[TMP80:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS13]], i32 0, i32 1 3250 // CHECK3-NEXT: [[TMP81:%.*]] = bitcast i8** [[TMP80]] to i32* 3251 // CHECK3-NEXT: store i32 [[TMP71]], i32* [[TMP81]], align 4 3252 // CHECK3-NEXT: [[TMP82:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS14]], i32 0, i32 1 3253 // CHECK3-NEXT: store i8* null, i8** [[TMP82]], align 4 3254 // CHECK3-NEXT: [[TMP83:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS12]], i32 0, i32 0 3255 // CHECK3-NEXT: [[TMP84:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS13]], i32 0, i32 0 3256 // CHECK3-NEXT: [[TMP85:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.region_id, i32 2, i8** [[TMP83]], i8** [[TMP84]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.7, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.8, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 3257 // CHECK3-NEXT: [[TMP86:%.*]] = icmp ne i32 [[TMP85]], 0 3258 // CHECK3-NEXT: br i1 [[TMP86]], label [[OMP_OFFLOAD_FAILED15:%.*]], label [[OMP_OFFLOAD_CONT16:%.*]] 3259 // CHECK3: omp_offload.failed15: 3260 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i32 [[TMP69]], i32 [[TMP71]]) #[[ATTR3]] 3261 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT16]] 3262 // CHECK3: omp_offload.cont16: 3263 // CHECK3-NEXT: br label [[OMP_IF_END:%.*]] 3264 // CHECK3: omp_if.else: 3265 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i32 [[TMP69]], i32 [[TMP71]]) #[[ATTR3]] 3266 // CHECK3-NEXT: br label [[OMP_IF_END]] 3267 // CHECK3: omp_if.end: 3268 // CHECK3-NEXT: [[TMP87:%.*]] = load i32, i32* [[A]], align 4 3269 // CHECK3-NEXT: store i32 [[TMP87]], i32* [[A_CASTED17]], align 4 3270 // CHECK3-NEXT: [[TMP88:%.*]] = load i32, i32* [[A_CASTED17]], align 4 3271 // CHECK3-NEXT: [[TMP89:%.*]] = load i32, i32* [[N_ADDR]], align 4 3272 // CHECK3-NEXT: [[CMP18:%.*]] = icmp sgt i32 [[TMP89]], 20 3273 // CHECK3-NEXT: br i1 [[CMP18]], label [[OMP_IF_THEN19:%.*]], label [[OMP_IF_ELSE25:%.*]] 3274 // CHECK3: omp_if.then19: 3275 // CHECK3-NEXT: [[TMP90:%.*]] = mul nuw i32 [[TMP1]], 4 3276 // CHECK3-NEXT: [[TMP91:%.*]] = sext i32 [[TMP90]] to i64 3277 // CHECK3-NEXT: [[TMP92:%.*]] = mul nuw i32 5, [[TMP3]] 3278 // CHECK3-NEXT: [[TMP93:%.*]] = mul nuw i32 [[TMP92]], 8 3279 // CHECK3-NEXT: [[TMP94:%.*]] = sext i32 [[TMP93]] to i64 3280 // CHECK3-NEXT: [[TMP95:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0 3281 // CHECK3-NEXT: [[TMP96:%.*]] = bitcast i8** [[TMP95]] to i32* 3282 // CHECK3-NEXT: store i32 [[TMP88]], i32* [[TMP96]], align 4 3283 // CHECK3-NEXT: [[TMP97:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 0 3284 // CHECK3-NEXT: [[TMP98:%.*]] = bitcast i8** [[TMP97]] to i32* 3285 // CHECK3-NEXT: store i32 [[TMP88]], i32* [[TMP98]], align 4 3286 // CHECK3-NEXT: [[TMP99:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 3287 // CHECK3-NEXT: store i64 4, i64* [[TMP99]], align 4 3288 // CHECK3-NEXT: [[TMP100:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 0 3289 // CHECK3-NEXT: store i8* null, i8** [[TMP100]], align 4 3290 // CHECK3-NEXT: [[TMP101:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 1 3291 // CHECK3-NEXT: [[TMP102:%.*]] = bitcast i8** [[TMP101]] to [10 x float]** 3292 // CHECK3-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP102]], align 4 3293 // CHECK3-NEXT: [[TMP103:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 1 3294 // CHECK3-NEXT: [[TMP104:%.*]] = bitcast i8** [[TMP103]] to [10 x float]** 3295 // CHECK3-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP104]], align 4 3296 // CHECK3-NEXT: [[TMP105:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 3297 // CHECK3-NEXT: store i64 40, i64* [[TMP105]], align 4 3298 // CHECK3-NEXT: [[TMP106:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 1 3299 // CHECK3-NEXT: store i8* null, i8** [[TMP106]], align 4 3300 // CHECK3-NEXT: [[TMP107:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 2 3301 // CHECK3-NEXT: [[TMP108:%.*]] = bitcast i8** [[TMP107]] to i32* 3302 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP108]], align 4 3303 // CHECK3-NEXT: [[TMP109:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 2 3304 // CHECK3-NEXT: [[TMP110:%.*]] = bitcast i8** [[TMP109]] to i32* 3305 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP110]], align 4 3306 // CHECK3-NEXT: [[TMP111:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 3307 // CHECK3-NEXT: store i64 4, i64* [[TMP111]], align 4 3308 // CHECK3-NEXT: [[TMP112:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 2 3309 // CHECK3-NEXT: store i8* null, i8** [[TMP112]], align 4 3310 // CHECK3-NEXT: [[TMP113:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 3 3311 // CHECK3-NEXT: [[TMP114:%.*]] = bitcast i8** [[TMP113]] to float** 3312 // CHECK3-NEXT: store float* [[VLA]], float** [[TMP114]], align 4 3313 // CHECK3-NEXT: [[TMP115:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 3 3314 // CHECK3-NEXT: [[TMP116:%.*]] = bitcast i8** [[TMP115]] to float** 3315 // CHECK3-NEXT: store float* [[VLA]], float** [[TMP116]], align 4 3316 // CHECK3-NEXT: [[TMP117:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 3317 // CHECK3-NEXT: store i64 [[TMP91]], i64* [[TMP117]], align 4 3318 // CHECK3-NEXT: [[TMP118:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 3 3319 // CHECK3-NEXT: store i8* null, i8** [[TMP118]], align 4 3320 // CHECK3-NEXT: [[TMP119:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 4 3321 // CHECK3-NEXT: [[TMP120:%.*]] = bitcast i8** [[TMP119]] to [5 x [10 x double]]** 3322 // CHECK3-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP120]], align 4 3323 // CHECK3-NEXT: [[TMP121:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 4 3324 // CHECK3-NEXT: [[TMP122:%.*]] = bitcast i8** [[TMP121]] to [5 x [10 x double]]** 3325 // CHECK3-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP122]], align 4 3326 // CHECK3-NEXT: [[TMP123:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 3327 // CHECK3-NEXT: store i64 400, i64* [[TMP123]], align 4 3328 // CHECK3-NEXT: [[TMP124:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 4 3329 // CHECK3-NEXT: store i8* null, i8** [[TMP124]], align 4 3330 // CHECK3-NEXT: [[TMP125:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 5 3331 // CHECK3-NEXT: [[TMP126:%.*]] = bitcast i8** [[TMP125]] to i32* 3332 // CHECK3-NEXT: store i32 5, i32* [[TMP126]], align 4 3333 // CHECK3-NEXT: [[TMP127:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 5 3334 // CHECK3-NEXT: [[TMP128:%.*]] = bitcast i8** [[TMP127]] to i32* 3335 // CHECK3-NEXT: store i32 5, i32* [[TMP128]], align 4 3336 // CHECK3-NEXT: [[TMP129:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 5 3337 // CHECK3-NEXT: store i64 4, i64* [[TMP129]], align 4 3338 // CHECK3-NEXT: [[TMP130:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 5 3339 // CHECK3-NEXT: store i8* null, i8** [[TMP130]], align 4 3340 // CHECK3-NEXT: [[TMP131:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 6 3341 // CHECK3-NEXT: [[TMP132:%.*]] = bitcast i8** [[TMP131]] to i32* 3342 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP132]], align 4 3343 // CHECK3-NEXT: [[TMP133:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 6 3344 // CHECK3-NEXT: [[TMP134:%.*]] = bitcast i8** [[TMP133]] to i32* 3345 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP134]], align 4 3346 // CHECK3-NEXT: [[TMP135:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 6 3347 // CHECK3-NEXT: store i64 4, i64* [[TMP135]], align 4 3348 // CHECK3-NEXT: [[TMP136:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 6 3349 // CHECK3-NEXT: store i8* null, i8** [[TMP136]], align 4 3350 // CHECK3-NEXT: [[TMP137:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 7 3351 // CHECK3-NEXT: [[TMP138:%.*]] = bitcast i8** [[TMP137]] to double** 3352 // CHECK3-NEXT: store double* [[VLA1]], double** [[TMP138]], align 4 3353 // CHECK3-NEXT: [[TMP139:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 7 3354 // CHECK3-NEXT: [[TMP140:%.*]] = bitcast i8** [[TMP139]] to double** 3355 // CHECK3-NEXT: store double* [[VLA1]], double** [[TMP140]], align 4 3356 // CHECK3-NEXT: [[TMP141:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 3357 // CHECK3-NEXT: store i64 [[TMP94]], i64* [[TMP141]], align 4 3358 // CHECK3-NEXT: [[TMP142:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 7 3359 // CHECK3-NEXT: store i8* null, i8** [[TMP142]], align 4 3360 // CHECK3-NEXT: [[TMP143:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 8 3361 // CHECK3-NEXT: [[TMP144:%.*]] = bitcast i8** [[TMP143]] to %struct.TT** 3362 // CHECK3-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP144]], align 4 3363 // CHECK3-NEXT: [[TMP145:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 8 3364 // CHECK3-NEXT: [[TMP146:%.*]] = bitcast i8** [[TMP145]] to %struct.TT** 3365 // CHECK3-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP146]], align 4 3366 // CHECK3-NEXT: [[TMP147:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 8 3367 // CHECK3-NEXT: store i64 12, i64* [[TMP147]], align 4 3368 // CHECK3-NEXT: [[TMP148:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 8 3369 // CHECK3-NEXT: store i8* null, i8** [[TMP148]], align 4 3370 // CHECK3-NEXT: [[TMP149:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0 3371 // CHECK3-NEXT: [[TMP150:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 0 3372 // CHECK3-NEXT: [[TMP151:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 3373 // CHECK3-NEXT: [[TMP152:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142.region_id, i32 9, i8** [[TMP149]], i8** [[TMP150]], i64* [[TMP151]], i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 3374 // CHECK3-NEXT: [[TMP153:%.*]] = icmp ne i32 [[TMP152]], 0 3375 // CHECK3-NEXT: br i1 [[TMP153]], label [[OMP_OFFLOAD_FAILED23:%.*]], label [[OMP_OFFLOAD_CONT24:%.*]] 3376 // CHECK3: omp_offload.failed23: 3377 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i32 [[TMP88]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR3]] 3378 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT24]] 3379 // CHECK3: omp_offload.cont24: 3380 // CHECK3-NEXT: br label [[OMP_IF_END26:%.*]] 3381 // CHECK3: omp_if.else25: 3382 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i32 [[TMP88]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR3]] 3383 // CHECK3-NEXT: br label [[OMP_IF_END26]] 3384 // CHECK3: omp_if.end26: 3385 // CHECK3-NEXT: store i32 0, i32* [[NN]], align 4 3386 // CHECK3-NEXT: [[TMP154:%.*]] = load i32, i32* [[NN]], align 4 3387 // CHECK3-NEXT: store i32 [[TMP154]], i32* [[NN_CASTED]], align 4 3388 // CHECK3-NEXT: [[TMP155:%.*]] = load i32, i32* [[NN_CASTED]], align 4 3389 // CHECK3-NEXT: [[TMP156:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS27]], i32 0, i32 0 3390 // CHECK3-NEXT: [[TMP157:%.*]] = bitcast i8** [[TMP156]] to i32* 3391 // CHECK3-NEXT: store i32 [[TMP155]], i32* [[TMP157]], align 4 3392 // CHECK3-NEXT: [[TMP158:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS28]], i32 0, i32 0 3393 // CHECK3-NEXT: [[TMP159:%.*]] = bitcast i8** [[TMP158]] to i32* 3394 // CHECK3-NEXT: store i32 [[TMP155]], i32* [[TMP159]], align 4 3395 // CHECK3-NEXT: [[TMP160:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS29]], i32 0, i32 0 3396 // CHECK3-NEXT: store i8* null, i8** [[TMP160]], align 4 3397 // CHECK3-NEXT: [[TMP161:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS27]], i32 0, i32 0 3398 // CHECK3-NEXT: [[TMP162:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS28]], i32 0, i32 0 3399 // CHECK3-NEXT: [[TMP163:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154.region_id, i32 1, i8** [[TMP161]], i8** [[TMP162]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.13, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.14, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 3400 // CHECK3-NEXT: [[TMP164:%.*]] = icmp ne i32 [[TMP163]], 0 3401 // CHECK3-NEXT: br i1 [[TMP164]], label [[OMP_OFFLOAD_FAILED30:%.*]], label [[OMP_OFFLOAD_CONT31:%.*]] 3402 // CHECK3: omp_offload.failed30: 3403 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154(i32 [[TMP155]]) #[[ATTR3]] 3404 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT31]] 3405 // CHECK3: omp_offload.cont31: 3406 // CHECK3-NEXT: [[TMP165:%.*]] = load i32, i32* [[NN]], align 4 3407 // CHECK3-NEXT: store i32 [[TMP165]], i32* [[NN_CASTED32]], align 4 3408 // CHECK3-NEXT: [[TMP166:%.*]] = load i32, i32* [[NN_CASTED32]], align 4 3409 // CHECK3-NEXT: [[TMP167:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS33]], i32 0, i32 0 3410 // CHECK3-NEXT: [[TMP168:%.*]] = bitcast i8** [[TMP167]] to i32* 3411 // CHECK3-NEXT: store i32 [[TMP166]], i32* [[TMP168]], align 4 3412 // CHECK3-NEXT: [[TMP169:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS34]], i32 0, i32 0 3413 // CHECK3-NEXT: [[TMP170:%.*]] = bitcast i8** [[TMP169]] to i32* 3414 // CHECK3-NEXT: store i32 [[TMP166]], i32* [[TMP170]], align 4 3415 // CHECK3-NEXT: [[TMP171:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS35]], i32 0, i32 0 3416 // CHECK3-NEXT: store i8* null, i8** [[TMP171]], align 4 3417 // CHECK3-NEXT: [[TMP172:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS33]], i32 0, i32 0 3418 // CHECK3-NEXT: [[TMP173:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS34]], i32 0, i32 0 3419 // CHECK3-NEXT: [[TMP174:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157.region_id, i32 1, i8** [[TMP172]], i8** [[TMP173]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.17, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.18, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 3420 // CHECK3-NEXT: [[TMP175:%.*]] = icmp ne i32 [[TMP174]], 0 3421 // CHECK3-NEXT: br i1 [[TMP175]], label [[OMP_OFFLOAD_FAILED36:%.*]], label [[OMP_OFFLOAD_CONT37:%.*]] 3422 // CHECK3: omp_offload.failed36: 3423 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157(i32 [[TMP166]]) #[[ATTR3]] 3424 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT37]] 3425 // CHECK3: omp_offload.cont37: 3426 // CHECK3-NEXT: [[TMP176:%.*]] = load i32, i32* [[A]], align 4 3427 // CHECK3-NEXT: [[TMP177:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 3428 // CHECK3-NEXT: call void @llvm.stackrestore(i8* [[TMP177]]) 3429 // CHECK3-NEXT: ret i32 [[TMP176]] 3430 // 3431 // 3432 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101 3433 // CHECK3-SAME: (i32 [[AA:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]], i32 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] { 3434 // CHECK3-NEXT: entry: 3435 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 3436 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 3437 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4 3438 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 3439 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 3440 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 3441 // CHECK3-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 3442 // CHECK3-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 3443 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 3444 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 3445 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 3446 // CHECK3-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) 3447 // CHECK3-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 3448 // CHECK3-NEXT: [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 3449 // CHECK3-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 3450 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 3451 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]]) 3452 // CHECK3-NEXT: ret void 3453 // 3454 // 3455 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. 3456 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] { 3457 // CHECK3-NEXT: entry: 3458 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 3459 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 3460 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 3461 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 3462 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 3463 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 3464 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 3465 // CHECK3-NEXT: ret void 3466 // 3467 // 3468 // CHECK3-LABEL: define {{[^@]+}}@.omp_task_privates_map. 3469 // CHECK3-SAME: (%struct..kmp_privates.t* noalias [[TMP0:%.*]], i16** noalias [[TMP1:%.*]], [3 x i8*]** noalias [[TMP2:%.*]], [3 x i8*]** noalias [[TMP3:%.*]], [3 x i64]** noalias [[TMP4:%.*]]) #[[ATTR4:[0-9]+]] { 3470 // CHECK3-NEXT: entry: 3471 // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 4 3472 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i16**, align 4 3473 // CHECK3-NEXT: [[DOTADDR2:%.*]] = alloca [3 x i8*]**, align 4 3474 // CHECK3-NEXT: [[DOTADDR3:%.*]] = alloca [3 x i8*]**, align 4 3475 // CHECK3-NEXT: [[DOTADDR4:%.*]] = alloca [3 x i64]**, align 4 3476 // CHECK3-NEXT: store %struct..kmp_privates.t* [[TMP0]], %struct..kmp_privates.t** [[DOTADDR]], align 4 3477 // CHECK3-NEXT: store i16** [[TMP1]], i16*** [[DOTADDR1]], align 4 3478 // CHECK3-NEXT: store [3 x i8*]** [[TMP2]], [3 x i8*]*** [[DOTADDR2]], align 4 3479 // CHECK3-NEXT: store [3 x i8*]** [[TMP3]], [3 x i8*]*** [[DOTADDR3]], align 4 3480 // CHECK3-NEXT: store [3 x i64]** [[TMP4]], [3 x i64]*** [[DOTADDR4]], align 4 3481 // CHECK3-NEXT: [[TMP5:%.*]] = load %struct..kmp_privates.t*, %struct..kmp_privates.t** [[DOTADDR]], align 4 3482 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 0 3483 // CHECK3-NEXT: [[TMP7:%.*]] = load [3 x i64]**, [3 x i64]*** [[DOTADDR4]], align 4 3484 // CHECK3-NEXT: store [3 x i64]* [[TMP6]], [3 x i64]** [[TMP7]], align 4 3485 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 1 3486 // CHECK3-NEXT: [[TMP9:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR2]], align 4 3487 // CHECK3-NEXT: store [3 x i8*]* [[TMP8]], [3 x i8*]** [[TMP9]], align 4 3488 // CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 2 3489 // CHECK3-NEXT: [[TMP11:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR3]], align 4 3490 // CHECK3-NEXT: store [3 x i8*]* [[TMP10]], [3 x i8*]** [[TMP11]], align 4 3491 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 3 3492 // CHECK3-NEXT: [[TMP13:%.*]] = load i16**, i16*** [[DOTADDR1]], align 4 3493 // CHECK3-NEXT: store i16* [[TMP12]], i16** [[TMP13]], align 4 3494 // CHECK3-NEXT: ret void 3495 // 3496 // 3497 // CHECK3-LABEL: define {{[^@]+}}@.omp_task_entry. 3498 // CHECK3-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { 3499 // CHECK3-NEXT: entry: 3500 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 3501 // CHECK3-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 4 3502 // CHECK3-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 4 3503 // CHECK3-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 4 3504 // CHECK3-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 4 3505 // CHECK3-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 4 3506 // CHECK3-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca i16*, align 4 3507 // CHECK3-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca [3 x i8*]*, align 4 3508 // CHECK3-NEXT: [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca [3 x i8*]*, align 4 3509 // CHECK3-NEXT: [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca [3 x i64]*, align 4 3510 // CHECK3-NEXT: [[AA_CASTED_I:%.*]] = alloca i32, align 4 3511 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__CASTED_I:%.*]] = alloca i32, align 4 3512 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__CASTED4_I:%.*]] = alloca i32, align 4 3513 // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 3514 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 4 3515 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 3516 // CHECK3-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4 3517 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 3518 // CHECK3-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4 3519 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0 3520 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 3521 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 3522 // CHECK3-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 4 3523 // CHECK3-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon* 3524 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1 3525 // CHECK3-NEXT: [[TMP10:%.*]] = bitcast %struct..kmp_privates.t* [[TMP9]] to i8* 3526 // CHECK3-NEXT: [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8* 3527 // CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]]) 3528 // CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]]) 3529 // CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]]) 3530 // CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META22:![0-9]+]]) 3531 // CHECK3-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !24 3532 // CHECK3-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 4, !noalias !24 3533 // CHECK3-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !24 3534 // CHECK3-NEXT: store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* @.omp_task_privates_map. to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !24 3535 // CHECK3-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 4, !noalias !24 3536 // CHECK3-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !24 3537 // CHECK3-NEXT: [[TMP12:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !24 3538 // CHECK3-NEXT: [[TMP13:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !24 3539 // CHECK3-NEXT: [[TMP14:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !24 3540 // CHECK3-NEXT: [[TMP15:%.*]] = bitcast void (i8*, ...)* [[TMP13]] to void (i8*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* 3541 // CHECK3-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]] 3542 // CHECK3-NEXT: [[TMP16:%.*]] = load i16*, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 4, !noalias !24 3543 // CHECK3-NEXT: [[TMP17:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 4, !noalias !24 3544 // CHECK3-NEXT: [[TMP18:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 4, !noalias !24 3545 // CHECK3-NEXT: [[TMP19:%.*]] = load [3 x i64]*, [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 4, !noalias !24 3546 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP17]], i32 0, i32 0 3547 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP18]], i32 0, i32 0 3548 // CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[TMP19]], i32 0, i32 0 3549 // CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP12]], i32 0, i32 1 3550 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[TMP12]], i32 0, i32 2 3551 // CHECK3-NEXT: [[TMP25:%.*]] = load i32, i32* [[TMP23]], align 4 3552 // CHECK3-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP24]], align 4 3553 // CHECK3-NEXT: [[TMP27:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 [[TMP25]], i32 [[TMP26]]) #[[ATTR3]] 3554 // CHECK3-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0 3555 // CHECK3-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]] 3556 // CHECK3: omp_offload.failed.i: 3557 // CHECK3-NEXT: [[TMP29:%.*]] = load i16, i16* [[TMP16]], align 2 3558 // CHECK3-NEXT: [[CONV_I:%.*]] = bitcast i32* [[AA_CASTED_I]] to i16* 3559 // CHECK3-NEXT: store i16 [[TMP29]], i16* [[CONV_I]], align 2, !noalias !24 3560 // CHECK3-NEXT: [[TMP30:%.*]] = load i32, i32* [[AA_CASTED_I]], align 4, !noalias !24 3561 // CHECK3-NEXT: [[TMP31:%.*]] = load i32, i32* [[TMP23]], align 4 3562 // CHECK3-NEXT: store i32 [[TMP31]], i32* [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias !24 3563 // CHECK3-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias !24 3564 // CHECK3-NEXT: [[TMP33:%.*]] = load i32, i32* [[TMP24]], align 4 3565 // CHECK3-NEXT: store i32 [[TMP33]], i32* [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias !24 3566 // CHECK3-NEXT: [[TMP34:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias !24 3567 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101(i32 [[TMP30]], i32 [[TMP32]], i32 [[TMP34]]) #[[ATTR3]] 3568 // CHECK3-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]] 3569 // CHECK3: .omp_outlined..1.exit: 3570 // CHECK3-NEXT: ret i32 0 3571 // 3572 // 3573 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l105 3574 // CHECK3-SAME: (i32 [[A:%.*]]) #[[ATTR2]] { 3575 // CHECK3-NEXT: entry: 3576 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3577 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 3578 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 3579 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 3580 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 3581 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 3582 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]]) 3583 // CHECK3-NEXT: ret void 3584 // 3585 // 3586 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..2 3587 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]]) #[[ATTR2]] { 3588 // CHECK3-NEXT: entry: 3589 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 3590 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 3591 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3592 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 3593 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 3594 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 3595 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 3596 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 3597 // CHECK3-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 3598 // CHECK3-NEXT: ret void 3599 // 3600 // 3601 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 3602 // CHECK3-SAME: (i32 [[AA:%.*]]) #[[ATTR2]] { 3603 // CHECK3-NEXT: entry: 3604 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 3605 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 3606 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 3607 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 3608 // CHECK3-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 3609 // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 3610 // CHECK3-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 3611 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 3612 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP1]]) 3613 // CHECK3-NEXT: ret void 3614 // 3615 // 3616 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..3 3617 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] { 3618 // CHECK3-NEXT: entry: 3619 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 3620 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 3621 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 3622 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 3623 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 3624 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 3625 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 3626 // CHECK3-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 3627 // CHECK3-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 3628 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 3629 // CHECK3-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 3630 // CHECK3-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 4 3631 // CHECK3-NEXT: ret void 3632 // 3633 // 3634 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118 3635 // CHECK3-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] { 3636 // CHECK3-NEXT: entry: 3637 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3638 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 3639 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 3640 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 3641 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 3642 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 3643 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 3644 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 3645 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 3646 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 3647 // CHECK3-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 3648 // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 3649 // CHECK3-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 3650 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 3651 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) 3652 // CHECK3-NEXT: ret void 3653 // 3654 // 3655 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..6 3656 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] { 3657 // CHECK3-NEXT: entry: 3658 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 3659 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 3660 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3661 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 3662 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 3663 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 3664 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 3665 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 3666 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 3667 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 3668 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 3669 // CHECK3-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 3670 // CHECK3-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 4 3671 // CHECK3-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32 3672 // CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 3673 // CHECK3-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 3674 // CHECK3-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 4 3675 // CHECK3-NEXT: ret void 3676 // 3677 // 3678 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142 3679 // CHECK3-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] { 3680 // CHECK3-NEXT: entry: 3681 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3682 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 3683 // CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 3684 // CHECK3-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 3685 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 3686 // CHECK3-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 3687 // CHECK3-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 3688 // CHECK3-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 3689 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 3690 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 3691 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 3692 // CHECK3-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 3693 // CHECK3-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 3694 // CHECK3-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 3695 // CHECK3-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 3696 // CHECK3-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 3697 // CHECK3-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 3698 // CHECK3-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 3699 // CHECK3-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 3700 // CHECK3-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 3701 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 3702 // CHECK3-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 3703 // CHECK3-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 3704 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 3705 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 3706 // CHECK3-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 3707 // CHECK3-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 3708 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 3709 // CHECK3-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4 3710 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4 3711 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) 3712 // CHECK3-NEXT: ret void 3713 // 3714 // 3715 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..9 3716 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] { 3717 // CHECK3-NEXT: entry: 3718 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 3719 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 3720 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3721 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 3722 // CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 3723 // CHECK3-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 3724 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 3725 // CHECK3-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 3726 // CHECK3-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 3727 // CHECK3-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 3728 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 3729 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 3730 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 3731 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 3732 // CHECK3-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 3733 // CHECK3-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 3734 // CHECK3-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 3735 // CHECK3-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 3736 // CHECK3-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 3737 // CHECK3-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 3738 // CHECK3-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 3739 // CHECK3-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 3740 // CHECK3-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 3741 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 3742 // CHECK3-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 3743 // CHECK3-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 3744 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 3745 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 3746 // CHECK3-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 3747 // CHECK3-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 3748 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 3749 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 3750 // CHECK3-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 3751 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2 3752 // CHECK3-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 3753 // CHECK3-NEXT: [[CONV:%.*]] = fpext float [[TMP9]] to double 3754 // CHECK3-NEXT: [[ADD5:%.*]] = fadd double [[CONV]], 1.000000e+00 3755 // CHECK3-NEXT: [[CONV6:%.*]] = fptrunc double [[ADD5]] to float 3756 // CHECK3-NEXT: store float [[CONV6]], float* [[ARRAYIDX]], align 4 3757 // CHECK3-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3 3758 // CHECK3-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX7]], align 4 3759 // CHECK3-NEXT: [[CONV8:%.*]] = fpext float [[TMP10]] to double 3760 // CHECK3-NEXT: [[ADD9:%.*]] = fadd double [[CONV8]], 1.000000e+00 3761 // CHECK3-NEXT: [[CONV10:%.*]] = fptrunc double [[ADD9]] to float 3762 // CHECK3-NEXT: store float [[CONV10]], float* [[ARRAYIDX7]], align 4 3763 // CHECK3-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1 3764 // CHECK3-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX11]], i32 0, i32 2 3765 // CHECK3-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX12]], align 8 3766 // CHECK3-NEXT: [[ADD13:%.*]] = fadd double [[TMP11]], 1.000000e+00 3767 // CHECK3-NEXT: store double [[ADD13]], double* [[ARRAYIDX12]], align 8 3768 // CHECK3-NEXT: [[TMP12:%.*]] = mul nsw i32 1, [[TMP5]] 3769 // CHECK3-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP12]] 3770 // CHECK3-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX14]], i32 3 3771 // CHECK3-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX15]], align 8 3772 // CHECK3-NEXT: [[ADD16:%.*]] = fadd double [[TMP13]], 1.000000e+00 3773 // CHECK3-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8 3774 // CHECK3-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 3775 // CHECK3-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 4 3776 // CHECK3-NEXT: [[ADD17:%.*]] = add nsw i64 [[TMP14]], 1 3777 // CHECK3-NEXT: store i64 [[ADD17]], i64* [[X]], align 4 3778 // CHECK3-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 3779 // CHECK3-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 4 3780 // CHECK3-NEXT: [[CONV18:%.*]] = sext i8 [[TMP15]] to i32 3781 // CHECK3-NEXT: [[ADD19:%.*]] = add nsw i32 [[CONV18]], 1 3782 // CHECK3-NEXT: [[CONV20:%.*]] = trunc i32 [[ADD19]] to i8 3783 // CHECK3-NEXT: store i8 [[CONV20]], i8* [[Y]], align 4 3784 // CHECK3-NEXT: ret void 3785 // 3786 // 3787 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154 3788 // CHECK3-SAME: (i32 [[NN:%.*]]) #[[ATTR2]] { 3789 // CHECK3-NEXT: entry: 3790 // CHECK3-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 3791 // CHECK3-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4 3792 // CHECK3-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 3793 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[NN_ADDR]], align 4 3794 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[NN_CASTED]], align 4 3795 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[NN_CASTED]], align 4 3796 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP1]]) 3797 // CHECK3-NEXT: ret void 3798 // 3799 // 3800 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..11 3801 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[NN:%.*]]) #[[ATTR2]] { 3802 // CHECK3-NEXT: entry: 3803 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 3804 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 3805 // CHECK3-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 3806 // CHECK3-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4 3807 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 3808 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 3809 // CHECK3-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 3810 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[NN_ADDR]], align 4 3811 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[NN_CASTED]], align 4 3812 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[NN_CASTED]], align 4 3813 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..12 to void (i32*, i32*, ...)*), i32 [[TMP1]]) 3814 // CHECK3-NEXT: ret void 3815 // 3816 // 3817 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..12 3818 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[NN:%.*]]) #[[ATTR2]] { 3819 // CHECK3-NEXT: entry: 3820 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 3821 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 3822 // CHECK3-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 3823 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 3824 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 3825 // CHECK3-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 3826 // CHECK3-NEXT: ret void 3827 // 3828 // 3829 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157 3830 // CHECK3-SAME: (i32 [[NN:%.*]]) #[[ATTR2]] { 3831 // CHECK3-NEXT: entry: 3832 // CHECK3-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 3833 // CHECK3-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4 3834 // CHECK3-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 3835 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[NN_ADDR]], align 4 3836 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[NN_CASTED]], align 4 3837 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[NN_CASTED]], align 4 3838 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i32 [[TMP1]]) 3839 // CHECK3-NEXT: ret void 3840 // 3841 // 3842 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..15 3843 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[NN:%.*]]) #[[ATTR2]] { 3844 // CHECK3-NEXT: entry: 3845 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 3846 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 3847 // CHECK3-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 3848 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 3849 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 3850 // CHECK3-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 3851 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i32* [[NN_ADDR]]) 3852 // CHECK3-NEXT: ret void 3853 // 3854 // 3855 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..16 3856 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[NN:%.*]]) #[[ATTR2]] { 3857 // CHECK3-NEXT: entry: 3858 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 3859 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 3860 // CHECK3-NEXT: [[NN_ADDR:%.*]] = alloca i32*, align 4 3861 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 3862 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 3863 // CHECK3-NEXT: store i32* [[NN]], i32** [[NN_ADDR]], align 4 3864 // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[NN_ADDR]], align 4 3865 // CHECK3-NEXT: ret void 3866 // 3867 // 3868 // CHECK3-LABEL: define {{[^@]+}}@_Z6bazzzziPi 3869 // CHECK3-SAME: (i32 [[N:%.*]], i32* [[F:%.*]]) #[[ATTR0]] { 3870 // CHECK3-NEXT: entry: 3871 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 3872 // CHECK3-NEXT: [[F_ADDR:%.*]] = alloca i32*, align 4 3873 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 3874 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 3875 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 3876 // CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 3877 // CHECK3-NEXT: store i32* [[F]], i32** [[F_ADDR]], align 4 3878 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 3879 // CHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3880 // CHECK3-NEXT: [[TMP2:%.*]] = bitcast i8** [[TMP1]] to i32* 3881 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[TMP2]], align 4 3882 // CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3883 // CHECK3-NEXT: [[TMP4:%.*]] = bitcast i8** [[TMP3]] to i32* 3884 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[TMP4]], align 4 3885 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 3886 // CHECK3-NEXT: store i8* null, i8** [[TMP5]], align 4 3887 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3888 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3889 // CHECK3-NEXT: [[TMP8:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182.region_id, i32 1, i8** [[TMP6]], i8** [[TMP7]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.20, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.21, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 3890 // CHECK3-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0 3891 // CHECK3-NEXT: br i1 [[TMP9]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 3892 // CHECK3: omp_offload.failed: 3893 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182(i32 [[TMP0]]) #[[ATTR3]] 3894 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 3895 // CHECK3: omp_offload.cont: 3896 // CHECK3-NEXT: ret void 3897 // 3898 // 3899 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182 3900 // CHECK3-SAME: (i32 [[VLA:%.*]]) #[[ATTR2]] { 3901 // CHECK3-NEXT: entry: 3902 // CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 3903 // CHECK3-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 3904 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 3905 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..19 to void (i32*, i32*, ...)*), i32 [[TMP0]]) 3906 // CHECK3-NEXT: ret void 3907 // 3908 // 3909 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..19 3910 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[VLA:%.*]]) #[[ATTR2]] { 3911 // CHECK3-NEXT: entry: 3912 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 3913 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 3914 // CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 3915 // CHECK3-NEXT: [[F:%.*]] = alloca i32*, align 4 3916 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 3917 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 3918 // CHECK3-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 3919 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 3920 // CHECK3-NEXT: ret void 3921 // 3922 // 3923 // CHECK3-LABEL: define {{[^@]+}}@_Z3bari 3924 // CHECK3-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { 3925 // CHECK3-NEXT: entry: 3926 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 3927 // CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4 3928 // CHECK3-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 3929 // CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 3930 // CHECK3-NEXT: store i32 0, i32* [[A]], align 4 3931 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 3932 // CHECK3-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]]) 3933 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 3934 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 3935 // CHECK3-NEXT: store i32 [[ADD]], i32* [[A]], align 4 3936 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 3937 // CHECK3-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]]) 3938 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 3939 // CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 3940 // CHECK3-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 3941 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 3942 // CHECK3-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]]) 3943 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 3944 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 3945 // CHECK3-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 3946 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 3947 // CHECK3-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]]) 3948 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 3949 // CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] 3950 // CHECK3-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 3951 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 3952 // CHECK3-NEXT: ret i32 [[TMP8]] 3953 // 3954 // 3955 // CHECK3-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 3956 // CHECK3-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { 3957 // CHECK3-NEXT: entry: 3958 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 3959 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 3960 // CHECK3-NEXT: [[B:%.*]] = alloca i32, align 4 3961 // CHECK3-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 3962 // CHECK3-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 3963 // CHECK3-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 3964 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4 3965 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4 3966 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4 3967 // CHECK3-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 4 3968 // CHECK3-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 3969 // CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 3970 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 3971 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 3972 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 3973 // CHECK3-NEXT: store i32 [[ADD]], i32* [[B]], align 4 3974 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 3975 // CHECK3-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() 3976 // CHECK3-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 3977 // CHECK3-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] 3978 // CHECK3-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 3979 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 3980 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[B]], align 4 3981 // CHECK3-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 3982 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 3983 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 3984 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 60 3985 // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 3986 // CHECK3: omp_if.then: 3987 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 3988 // CHECK3-NEXT: [[TMP7:%.*]] = mul nuw i32 2, [[TMP1]] 3989 // CHECK3-NEXT: [[TMP8:%.*]] = mul nuw i32 [[TMP7]], 2 3990 // CHECK3-NEXT: [[TMP9:%.*]] = sext i32 [[TMP8]] to i64 3991 // CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3992 // CHECK3-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to %struct.S1** 3993 // CHECK3-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP11]], align 4 3994 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3995 // CHECK3-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to double** 3996 // CHECK3-NEXT: store double* [[A]], double** [[TMP13]], align 4 3997 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 3998 // CHECK3-NEXT: store i64 8, i64* [[TMP14]], align 4 3999 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 4000 // CHECK3-NEXT: store i8* null, i8** [[TMP15]], align 4 4001 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 4002 // CHECK3-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32* 4003 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[TMP17]], align 4 4004 // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 4005 // CHECK3-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32* 4006 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[TMP19]], align 4 4007 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 4008 // CHECK3-NEXT: store i64 4, i64* [[TMP20]], align 4 4009 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 4010 // CHECK3-NEXT: store i8* null, i8** [[TMP21]], align 4 4011 // CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 4012 // CHECK3-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i32* 4013 // CHECK3-NEXT: store i32 2, i32* [[TMP23]], align 4 4014 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 4015 // CHECK3-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i32* 4016 // CHECK3-NEXT: store i32 2, i32* [[TMP25]], align 4 4017 // CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 4018 // CHECK3-NEXT: store i64 4, i64* [[TMP26]], align 4 4019 // CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 4020 // CHECK3-NEXT: store i8* null, i8** [[TMP27]], align 4 4021 // CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 4022 // CHECK3-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i32* 4023 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP29]], align 4 4024 // CHECK3-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 4025 // CHECK3-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i32* 4026 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP31]], align 4 4027 // CHECK3-NEXT: [[TMP32:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 4028 // CHECK3-NEXT: store i64 4, i64* [[TMP32]], align 4 4029 // CHECK3-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 4030 // CHECK3-NEXT: store i8* null, i8** [[TMP33]], align 4 4031 // CHECK3-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 4032 // CHECK3-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i16** 4033 // CHECK3-NEXT: store i16* [[VLA]], i16** [[TMP35]], align 4 4034 // CHECK3-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 4035 // CHECK3-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i16** 4036 // CHECK3-NEXT: store i16* [[VLA]], i16** [[TMP37]], align 4 4037 // CHECK3-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 4038 // CHECK3-NEXT: store i64 [[TMP9]], i64* [[TMP38]], align 4 4039 // CHECK3-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 4040 // CHECK3-NEXT: store i8* null, i8** [[TMP39]], align 4 4041 // CHECK3-NEXT: [[TMP40:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 4042 // CHECK3-NEXT: [[TMP41:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 4043 // CHECK3-NEXT: [[TMP42:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 4044 // CHECK3-NEXT: [[TMP43:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227.region_id, i32 5, i8** [[TMP40]], i8** [[TMP41]], i64* [[TMP42]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.23, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 4045 // CHECK3-NEXT: [[TMP44:%.*]] = icmp ne i32 [[TMP43]], 0 4046 // CHECK3-NEXT: br i1 [[TMP44]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 4047 // CHECK3: omp_offload.failed: 4048 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR3]] 4049 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 4050 // CHECK3: omp_offload.cont: 4051 // CHECK3-NEXT: br label [[OMP_IF_END:%.*]] 4052 // CHECK3: omp_if.else: 4053 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR3]] 4054 // CHECK3-NEXT: br label [[OMP_IF_END]] 4055 // CHECK3: omp_if.end: 4056 // CHECK3-NEXT: [[TMP45:%.*]] = mul nsw i32 1, [[TMP1]] 4057 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP45]] 4058 // CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 4059 // CHECK3-NEXT: [[TMP46:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2 4060 // CHECK3-NEXT: [[CONV:%.*]] = sext i16 [[TMP46]] to i32 4061 // CHECK3-NEXT: [[TMP47:%.*]] = load i32, i32* [[B]], align 4 4062 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP47]] 4063 // CHECK3-NEXT: [[TMP48:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 4064 // CHECK3-NEXT: call void @llvm.stackrestore(i8* [[TMP48]]) 4065 // CHECK3-NEXT: ret i32 [[ADD3]] 4066 // 4067 // 4068 // CHECK3-LABEL: define {{[^@]+}}@_ZL7fstatici 4069 // CHECK3-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { 4070 // CHECK3-NEXT: entry: 4071 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 4072 // CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4 4073 // CHECK3-NEXT: [[AA:%.*]] = alloca i16, align 2 4074 // CHECK3-NEXT: [[AAA:%.*]] = alloca i8, align 1 4075 // CHECK3-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 4076 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 4077 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 4078 // CHECK3-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 4079 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4 4080 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 4081 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 4082 // CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 4083 // CHECK3-NEXT: store i32 0, i32* [[A]], align 4 4084 // CHECK3-NEXT: store i16 0, i16* [[AA]], align 2 4085 // CHECK3-NEXT: store i8 0, i8* [[AAA]], align 1 4086 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 4087 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 4088 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 4089 // CHECK3-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 4090 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 4091 // CHECK3-NEXT: store i16 [[TMP2]], i16* [[CONV]], align 2 4092 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 4093 // CHECK3-NEXT: [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1 4094 // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* 4095 // CHECK3-NEXT: store i8 [[TMP4]], i8* [[CONV1]], align 1 4096 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 4097 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 4098 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50 4099 // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 4100 // CHECK3: omp_if.then: 4101 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 4102 // CHECK3-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* 4103 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4 4104 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 4105 // CHECK3-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* 4106 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP10]], align 4 4107 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 4108 // CHECK3-NEXT: store i8* null, i8** [[TMP11]], align 4 4109 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 4110 // CHECK3-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* 4111 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4 4112 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 4113 // CHECK3-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32* 4114 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP15]], align 4 4115 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 4116 // CHECK3-NEXT: store i8* null, i8** [[TMP16]], align 4 4117 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 4118 // CHECK3-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32* 4119 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[TMP18]], align 4 4120 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 4121 // CHECK3-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32* 4122 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[TMP20]], align 4 4123 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 4124 // CHECK3-NEXT: store i8* null, i8** [[TMP21]], align 4 4125 // CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 4126 // CHECK3-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]** 4127 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 4 4128 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 4129 // CHECK3-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]** 4130 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 4 4131 // CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 4132 // CHECK3-NEXT: store i8* null, i8** [[TMP26]], align 4 4133 // CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 4134 // CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 4135 // CHECK3-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.25, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.26, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 4136 // CHECK3-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 4137 // CHECK3-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 4138 // CHECK3: omp_offload.failed: 4139 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR3]] 4140 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 4141 // CHECK3: omp_offload.cont: 4142 // CHECK3-NEXT: br label [[OMP_IF_END:%.*]] 4143 // CHECK3: omp_if.else: 4144 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR3]] 4145 // CHECK3-NEXT: br label [[OMP_IF_END]] 4146 // CHECK3: omp_if.end: 4147 // CHECK3-NEXT: [[TMP31:%.*]] = load i32, i32* [[A]], align 4 4148 // CHECK3-NEXT: ret i32 [[TMP31]] 4149 // 4150 // 4151 // CHECK3-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 4152 // CHECK3-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { 4153 // CHECK3-NEXT: entry: 4154 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 4155 // CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4 4156 // CHECK3-NEXT: [[AA:%.*]] = alloca i16, align 2 4157 // CHECK3-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 4158 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 4159 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 4160 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 4161 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 4162 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 4163 // CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 4164 // CHECK3-NEXT: store i32 0, i32* [[A]], align 4 4165 // CHECK3-NEXT: store i16 0, i16* [[AA]], align 2 4166 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 4167 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 4168 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 4169 // CHECK3-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 4170 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 4171 // CHECK3-NEXT: store i16 [[TMP2]], i16* [[CONV]], align 2 4172 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 4173 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 4174 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40 4175 // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 4176 // CHECK3: omp_if.then: 4177 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 4178 // CHECK3-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i32* 4179 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP6]], align 4 4180 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 4181 // CHECK3-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* 4182 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4 4183 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 4184 // CHECK3-NEXT: store i8* null, i8** [[TMP9]], align 4 4185 // CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 4186 // CHECK3-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i32* 4187 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP11]], align 4 4188 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 4189 // CHECK3-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* 4190 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4 4191 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 4192 // CHECK3-NEXT: store i8* null, i8** [[TMP14]], align 4 4193 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 4194 // CHECK3-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]** 4195 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 4 4196 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 4197 // CHECK3-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]** 4198 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 4 4199 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 4200 // CHECK3-NEXT: store i8* null, i8** [[TMP19]], align 4 4201 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 4202 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 4203 // CHECK3-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.28, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.29, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 4204 // CHECK3-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 4205 // CHECK3-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 4206 // CHECK3: omp_offload.failed: 4207 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]] 4208 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 4209 // CHECK3: omp_offload.cont: 4210 // CHECK3-NEXT: br label [[OMP_IF_END:%.*]] 4211 // CHECK3: omp_if.else: 4212 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]] 4213 // CHECK3-NEXT: br label [[OMP_IF_END]] 4214 // CHECK3: omp_if.end: 4215 // CHECK3-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4 4216 // CHECK3-NEXT: ret i32 [[TMP24]] 4217 // 4218 // 4219 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227 4220 // CHECK3-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { 4221 // CHECK3-NEXT: entry: 4222 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 4223 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 4224 // CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 4225 // CHECK3-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 4226 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 4227 // CHECK3-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 4228 // CHECK3-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 4229 // CHECK3-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 4230 // CHECK3-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 4231 // CHECK3-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 4232 // CHECK3-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 4233 // CHECK3-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 4234 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 4235 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 4236 // CHECK3-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 4237 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 4238 // CHECK3-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 4239 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 4240 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..22 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]]) 4241 // CHECK3-NEXT: ret void 4242 // 4243 // 4244 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..22 4245 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { 4246 // CHECK3-NEXT: entry: 4247 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 4248 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 4249 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 4250 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 4251 // CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 4252 // CHECK3-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 4253 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 4254 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 4255 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 4256 // CHECK3-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 4257 // CHECK3-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 4258 // CHECK3-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 4259 // CHECK3-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 4260 // CHECK3-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 4261 // CHECK3-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 4262 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 4263 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 4264 // CHECK3-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 4265 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 4266 // CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP4]] to double 4267 // CHECK3-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 4268 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 4269 // CHECK3-NEXT: store double [[ADD]], double* [[A]], align 4 4270 // CHECK3-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 4271 // CHECK3-NEXT: [[TMP5:%.*]] = load double, double* [[A3]], align 4 4272 // CHECK3-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 4273 // CHECK3-NEXT: store double [[INC]], double* [[A3]], align 4 4274 // CHECK3-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 4275 // CHECK3-NEXT: [[TMP6:%.*]] = mul nsw i32 1, [[TMP2]] 4276 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP6]] 4277 // CHECK3-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 4278 // CHECK3-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 4279 // CHECK3-NEXT: ret void 4280 // 4281 // 4282 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209 4283 // CHECK3-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 4284 // CHECK3-NEXT: entry: 4285 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 4286 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 4287 // CHECK3-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 4288 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 4289 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 4290 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 4291 // CHECK3-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 4292 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 4293 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 4294 // CHECK3-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 4295 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 4296 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 4297 // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 4298 // CHECK3-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 4299 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 4300 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 4301 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 4302 // CHECK3-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 4303 // CHECK3-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 4304 // CHECK3-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 4305 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 4306 // CHECK3-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 4 4307 // CHECK3-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* 4308 // CHECK3-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 4309 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 4310 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..24 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) 4311 // CHECK3-NEXT: ret void 4312 // 4313 // 4314 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..24 4315 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 4316 // CHECK3-NEXT: entry: 4317 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 4318 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 4319 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 4320 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 4321 // CHECK3-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 4322 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 4323 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 4324 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 4325 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 4326 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 4327 // CHECK3-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 4328 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 4329 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 4330 // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 4331 // CHECK3-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 4332 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 4333 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 4334 // CHECK3-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 4335 // CHECK3-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 4336 // CHECK3-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 4337 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 4338 // CHECK3-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 4339 // CHECK3-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 4 4340 // CHECK3-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 4 4341 // CHECK3-NEXT: [[CONV5:%.*]] = sext i8 [[TMP3]] to i32 4342 // CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 4343 // CHECK3-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i8 4344 // CHECK3-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 4 4345 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 4346 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 4347 // CHECK3-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP4]], 1 4348 // CHECK3-NEXT: store i32 [[ADD8]], i32* [[ARRAYIDX]], align 4 4349 // CHECK3-NEXT: ret void 4350 // 4351 // 4352 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192 4353 // CHECK3-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 4354 // CHECK3-NEXT: entry: 4355 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 4356 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 4357 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 4358 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 4359 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 4360 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 4361 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 4362 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 4363 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 4364 // CHECK3-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 4365 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 4366 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 4367 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 4368 // CHECK3-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 4369 // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 4370 // CHECK3-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 4371 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 4372 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..27 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) 4373 // CHECK3-NEXT: ret void 4374 // 4375 // 4376 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..27 4377 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 4378 // CHECK3-NEXT: entry: 4379 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 4380 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 4381 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 4382 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 4383 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 4384 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 4385 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 4386 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 4387 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 4388 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 4389 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 4390 // CHECK3-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 4391 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 4392 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 4393 // CHECK3-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 4394 // CHECK3-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 4395 // CHECK3-NEXT: [[CONV1:%.*]] = sext i16 [[TMP2]] to i32 4396 // CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 4397 // CHECK3-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 4398 // CHECK3-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 4 4399 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 4400 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 4401 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1 4402 // CHECK3-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4 4403 // CHECK3-NEXT: ret void 4404 // 4405 // 4406 // CHECK3-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 4407 // CHECK3-SAME: () #[[ATTR4]] { 4408 // CHECK3-NEXT: entry: 4409 // CHECK3-NEXT: call void @__tgt_register_requires(i64 1) 4410 // CHECK3-NEXT: ret void 4411 // 4412 // 4413 // CHECK4-LABEL: define {{[^@]+}}@_Z3fooi 4414 // CHECK4-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { 4415 // CHECK4-NEXT: entry: 4416 // CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 4417 // CHECK4-NEXT: [[A:%.*]] = alloca i32, align 4 4418 // CHECK4-NEXT: [[AA:%.*]] = alloca i16, align 2 4419 // CHECK4-NEXT: [[B:%.*]] = alloca [10 x float], align 4 4420 // CHECK4-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 4421 // CHECK4-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 4422 // CHECK4-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 4423 // CHECK4-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 4424 // CHECK4-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 4425 // CHECK4-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 4426 // CHECK4-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 4427 // CHECK4-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 4428 // CHECK4-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 4429 // CHECK4-NEXT: [[DOTCAPTURE_EXPR__CASTED3:%.*]] = alloca i32, align 4 4430 // CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 4431 // CHECK4-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 4432 // CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 4433 // CHECK4-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4 4434 // CHECK4-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 4435 // CHECK4-NEXT: [[AA_CASTED4:%.*]] = alloca i32, align 4 4436 // CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS6:%.*]] = alloca [1 x i8*], align 4 4437 // CHECK4-NEXT: [[DOTOFFLOAD_PTRS7:%.*]] = alloca [1 x i8*], align 4 4438 // CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS8:%.*]] = alloca [1 x i8*], align 4 4439 // CHECK4-NEXT: [[A_CASTED9:%.*]] = alloca i32, align 4 4440 // CHECK4-NEXT: [[AA_CASTED10:%.*]] = alloca i32, align 4 4441 // CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS12:%.*]] = alloca [2 x i8*], align 4 4442 // CHECK4-NEXT: [[DOTOFFLOAD_PTRS13:%.*]] = alloca [2 x i8*], align 4 4443 // CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS14:%.*]] = alloca [2 x i8*], align 4 4444 // CHECK4-NEXT: [[A_CASTED17:%.*]] = alloca i32, align 4 4445 // CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS20:%.*]] = alloca [9 x i8*], align 4 4446 // CHECK4-NEXT: [[DOTOFFLOAD_PTRS21:%.*]] = alloca [9 x i8*], align 4 4447 // CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS22:%.*]] = alloca [9 x i8*], align 4 4448 // CHECK4-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [9 x i64], align 4 4449 // CHECK4-NEXT: [[NN:%.*]] = alloca i32, align 4 4450 // CHECK4-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4 4451 // CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS27:%.*]] = alloca [1 x i8*], align 4 4452 // CHECK4-NEXT: [[DOTOFFLOAD_PTRS28:%.*]] = alloca [1 x i8*], align 4 4453 // CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS29:%.*]] = alloca [1 x i8*], align 4 4454 // CHECK4-NEXT: [[NN_CASTED32:%.*]] = alloca i32, align 4 4455 // CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS33:%.*]] = alloca [1 x i8*], align 4 4456 // CHECK4-NEXT: [[DOTOFFLOAD_PTRS34:%.*]] = alloca [1 x i8*], align 4 4457 // CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS35:%.*]] = alloca [1 x i8*], align 4 4458 // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) 4459 // CHECK4-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 4460 // CHECK4-NEXT: store i32 0, i32* [[A]], align 4 4461 // CHECK4-NEXT: store i16 0, i16* [[AA]], align 2 4462 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 4463 // CHECK4-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() 4464 // CHECK4-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 4465 // CHECK4-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP1]], align 4 4466 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 4467 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 4468 // CHECK4-NEXT: [[TMP4:%.*]] = mul nuw i32 5, [[TMP3]] 4469 // CHECK4-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP4]], align 8 4470 // CHECK4-NEXT: store i32 [[TMP3]], i32* [[__VLA_EXPR1]], align 4 4471 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 4472 // CHECK4-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_]], align 4 4473 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 4474 // CHECK4-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_2]], align 4 4475 // CHECK4-NEXT: [[TMP7:%.*]] = load i16, i16* [[AA]], align 2 4476 // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 4477 // CHECK4-NEXT: store i16 [[TMP7]], i16* [[CONV]], align 2 4478 // CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[AA_CASTED]], align 4 4479 // CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 4480 // CHECK4-NEXT: store i32 [[TMP9]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 4481 // CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 4482 // CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 4483 // CHECK4-NEXT: store i32 [[TMP11]], i32* [[DOTCAPTURE_EXPR__CASTED3]], align 4 4484 // CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED3]], align 4 4485 // CHECK4-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 4486 // CHECK4-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i32* 4487 // CHECK4-NEXT: store i32 [[TMP8]], i32* [[TMP14]], align 4 4488 // CHECK4-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 4489 // CHECK4-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i32* 4490 // CHECK4-NEXT: store i32 [[TMP8]], i32* [[TMP16]], align 4 4491 // CHECK4-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 4492 // CHECK4-NEXT: store i8* null, i8** [[TMP17]], align 4 4493 // CHECK4-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 4494 // CHECK4-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32* 4495 // CHECK4-NEXT: store i32 [[TMP10]], i32* [[TMP19]], align 4 4496 // CHECK4-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 4497 // CHECK4-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32* 4498 // CHECK4-NEXT: store i32 [[TMP10]], i32* [[TMP21]], align 4 4499 // CHECK4-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 4500 // CHECK4-NEXT: store i8* null, i8** [[TMP22]], align 4 4501 // CHECK4-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 4502 // CHECK4-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i32* 4503 // CHECK4-NEXT: store i32 [[TMP12]], i32* [[TMP24]], align 4 4504 // CHECK4-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 4505 // CHECK4-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i32* 4506 // CHECK4-NEXT: store i32 [[TMP12]], i32* [[TMP26]], align 4 4507 // CHECK4-NEXT: [[TMP27:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 4508 // CHECK4-NEXT: store i8* null, i8** [[TMP27]], align 4 4509 // CHECK4-NEXT: [[TMP28:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 4510 // CHECK4-NEXT: [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 4511 // CHECK4-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 0 4512 // CHECK4-NEXT: [[TMP31:%.*]] = load i16, i16* [[AA]], align 2 4513 // CHECK4-NEXT: store i16 [[TMP31]], i16* [[TMP30]], align 4 4514 // CHECK4-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 1 4515 // CHECK4-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 4516 // CHECK4-NEXT: store i32 [[TMP33]], i32* [[TMP32]], align 4 4517 // CHECK4-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 2 4518 // CHECK4-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 4519 // CHECK4-NEXT: store i32 [[TMP35]], i32* [[TMP34]], align 4 4520 // CHECK4-NEXT: [[TMP36:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i32 72, i32 12, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1) 4521 // CHECK4-NEXT: [[TMP37:%.*]] = bitcast i8* [[TMP36]] to %struct.kmp_task_t_with_privates* 4522 // CHECK4-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP37]], i32 0, i32 0 4523 // CHECK4-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP38]], i32 0, i32 0 4524 // CHECK4-NEXT: [[TMP40:%.*]] = load i8*, i8** [[TMP39]], align 4 4525 // CHECK4-NEXT: [[TMP41:%.*]] = bitcast %struct.anon* [[AGG_CAPTURED]] to i8* 4526 // CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP40]], i8* align 4 [[TMP41]], i32 12, i1 false) 4527 // CHECK4-NEXT: [[TMP42:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP37]], i32 0, i32 1 4528 // CHECK4-NEXT: [[TMP43:%.*]] = bitcast i8* [[TMP40]] to %struct.anon* 4529 // CHECK4-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 0 4530 // CHECK4-NEXT: [[TMP45:%.*]] = bitcast [3 x i64]* [[TMP44]] to i8* 4531 // CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP45]], i8* align 4 bitcast ([3 x i64]* @.offload_sizes to i8*), i32 24, i1 false) 4532 // CHECK4-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 1 4533 // CHECK4-NEXT: [[TMP47:%.*]] = bitcast [3 x i8*]* [[TMP46]] to i8* 4534 // CHECK4-NEXT: [[TMP48:%.*]] = bitcast i8** [[TMP28]] to i8* 4535 // CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP47]], i8* align 4 [[TMP48]], i32 12, i1 false) 4536 // CHECK4-NEXT: [[TMP49:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 2 4537 // CHECK4-NEXT: [[TMP50:%.*]] = bitcast [3 x i8*]* [[TMP49]] to i8* 4538 // CHECK4-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP29]] to i8* 4539 // CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP50]], i8* align 4 [[TMP51]], i32 12, i1 false) 4540 // CHECK4-NEXT: [[TMP52:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 3 4541 // CHECK4-NEXT: [[TMP53:%.*]] = load i16, i16* [[AA]], align 2 4542 // CHECK4-NEXT: store i16 [[TMP53]], i16* [[TMP52]], align 4 4543 // CHECK4-NEXT: [[TMP54:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP36]]) 4544 // CHECK4-NEXT: [[TMP55:%.*]] = load i32, i32* [[A]], align 4 4545 // CHECK4-NEXT: store i32 [[TMP55]], i32* [[A_CASTED]], align 4 4546 // CHECK4-NEXT: [[TMP56:%.*]] = load i32, i32* [[A_CASTED]], align 4 4547 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l105(i32 [[TMP56]]) #[[ATTR3:[0-9]+]] 4548 // CHECK4-NEXT: [[TMP57:%.*]] = load i16, i16* [[AA]], align 2 4549 // CHECK4-NEXT: [[CONV5:%.*]] = bitcast i32* [[AA_CASTED4]] to i16* 4550 // CHECK4-NEXT: store i16 [[TMP57]], i16* [[CONV5]], align 2 4551 // CHECK4-NEXT: [[TMP58:%.*]] = load i32, i32* [[AA_CASTED4]], align 4 4552 // CHECK4-NEXT: [[TMP59:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0 4553 // CHECK4-NEXT: [[TMP60:%.*]] = bitcast i8** [[TMP59]] to i32* 4554 // CHECK4-NEXT: store i32 [[TMP58]], i32* [[TMP60]], align 4 4555 // CHECK4-NEXT: [[TMP61:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0 4556 // CHECK4-NEXT: [[TMP62:%.*]] = bitcast i8** [[TMP61]] to i32* 4557 // CHECK4-NEXT: store i32 [[TMP58]], i32* [[TMP62]], align 4 4558 // CHECK4-NEXT: [[TMP63:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS8]], i32 0, i32 0 4559 // CHECK4-NEXT: store i8* null, i8** [[TMP63]], align 4 4560 // CHECK4-NEXT: [[TMP64:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0 4561 // CHECK4-NEXT: [[TMP65:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0 4562 // CHECK4-NEXT: [[TMP66:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.region_id, i32 1, i8** [[TMP64]], i8** [[TMP65]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.4, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.5, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 4563 // CHECK4-NEXT: [[TMP67:%.*]] = icmp ne i32 [[TMP66]], 0 4564 // CHECK4-NEXT: br i1 [[TMP67]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 4565 // CHECK4: omp_offload.failed: 4566 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111(i32 [[TMP58]]) #[[ATTR3]] 4567 // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]] 4568 // CHECK4: omp_offload.cont: 4569 // CHECK4-NEXT: [[TMP68:%.*]] = load i32, i32* [[A]], align 4 4570 // CHECK4-NEXT: store i32 [[TMP68]], i32* [[A_CASTED9]], align 4 4571 // CHECK4-NEXT: [[TMP69:%.*]] = load i32, i32* [[A_CASTED9]], align 4 4572 // CHECK4-NEXT: [[TMP70:%.*]] = load i16, i16* [[AA]], align 2 4573 // CHECK4-NEXT: [[CONV11:%.*]] = bitcast i32* [[AA_CASTED10]] to i16* 4574 // CHECK4-NEXT: store i16 [[TMP70]], i16* [[CONV11]], align 2 4575 // CHECK4-NEXT: [[TMP71:%.*]] = load i32, i32* [[AA_CASTED10]], align 4 4576 // CHECK4-NEXT: [[TMP72:%.*]] = load i32, i32* [[N_ADDR]], align 4 4577 // CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP72]], 10 4578 // CHECK4-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 4579 // CHECK4: omp_if.then: 4580 // CHECK4-NEXT: [[TMP73:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS12]], i32 0, i32 0 4581 // CHECK4-NEXT: [[TMP74:%.*]] = bitcast i8** [[TMP73]] to i32* 4582 // CHECK4-NEXT: store i32 [[TMP69]], i32* [[TMP74]], align 4 4583 // CHECK4-NEXT: [[TMP75:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS13]], i32 0, i32 0 4584 // CHECK4-NEXT: [[TMP76:%.*]] = bitcast i8** [[TMP75]] to i32* 4585 // CHECK4-NEXT: store i32 [[TMP69]], i32* [[TMP76]], align 4 4586 // CHECK4-NEXT: [[TMP77:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS14]], i32 0, i32 0 4587 // CHECK4-NEXT: store i8* null, i8** [[TMP77]], align 4 4588 // CHECK4-NEXT: [[TMP78:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS12]], i32 0, i32 1 4589 // CHECK4-NEXT: [[TMP79:%.*]] = bitcast i8** [[TMP78]] to i32* 4590 // CHECK4-NEXT: store i32 [[TMP71]], i32* [[TMP79]], align 4 4591 // CHECK4-NEXT: [[TMP80:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS13]], i32 0, i32 1 4592 // CHECK4-NEXT: [[TMP81:%.*]] = bitcast i8** [[TMP80]] to i32* 4593 // CHECK4-NEXT: store i32 [[TMP71]], i32* [[TMP81]], align 4 4594 // CHECK4-NEXT: [[TMP82:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS14]], i32 0, i32 1 4595 // CHECK4-NEXT: store i8* null, i8** [[TMP82]], align 4 4596 // CHECK4-NEXT: [[TMP83:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS12]], i32 0, i32 0 4597 // CHECK4-NEXT: [[TMP84:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS13]], i32 0, i32 0 4598 // CHECK4-NEXT: [[TMP85:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.region_id, i32 2, i8** [[TMP83]], i8** [[TMP84]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.7, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.8, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 4599 // CHECK4-NEXT: [[TMP86:%.*]] = icmp ne i32 [[TMP85]], 0 4600 // CHECK4-NEXT: br i1 [[TMP86]], label [[OMP_OFFLOAD_FAILED15:%.*]], label [[OMP_OFFLOAD_CONT16:%.*]] 4601 // CHECK4: omp_offload.failed15: 4602 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i32 [[TMP69]], i32 [[TMP71]]) #[[ATTR3]] 4603 // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT16]] 4604 // CHECK4: omp_offload.cont16: 4605 // CHECK4-NEXT: br label [[OMP_IF_END:%.*]] 4606 // CHECK4: omp_if.else: 4607 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i32 [[TMP69]], i32 [[TMP71]]) #[[ATTR3]] 4608 // CHECK4-NEXT: br label [[OMP_IF_END]] 4609 // CHECK4: omp_if.end: 4610 // CHECK4-NEXT: [[TMP87:%.*]] = load i32, i32* [[A]], align 4 4611 // CHECK4-NEXT: store i32 [[TMP87]], i32* [[A_CASTED17]], align 4 4612 // CHECK4-NEXT: [[TMP88:%.*]] = load i32, i32* [[A_CASTED17]], align 4 4613 // CHECK4-NEXT: [[TMP89:%.*]] = load i32, i32* [[N_ADDR]], align 4 4614 // CHECK4-NEXT: [[CMP18:%.*]] = icmp sgt i32 [[TMP89]], 20 4615 // CHECK4-NEXT: br i1 [[CMP18]], label [[OMP_IF_THEN19:%.*]], label [[OMP_IF_ELSE25:%.*]] 4616 // CHECK4: omp_if.then19: 4617 // CHECK4-NEXT: [[TMP90:%.*]] = mul nuw i32 [[TMP1]], 4 4618 // CHECK4-NEXT: [[TMP91:%.*]] = sext i32 [[TMP90]] to i64 4619 // CHECK4-NEXT: [[TMP92:%.*]] = mul nuw i32 5, [[TMP3]] 4620 // CHECK4-NEXT: [[TMP93:%.*]] = mul nuw i32 [[TMP92]], 8 4621 // CHECK4-NEXT: [[TMP94:%.*]] = sext i32 [[TMP93]] to i64 4622 // CHECK4-NEXT: [[TMP95:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0 4623 // CHECK4-NEXT: [[TMP96:%.*]] = bitcast i8** [[TMP95]] to i32* 4624 // CHECK4-NEXT: store i32 [[TMP88]], i32* [[TMP96]], align 4 4625 // CHECK4-NEXT: [[TMP97:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 0 4626 // CHECK4-NEXT: [[TMP98:%.*]] = bitcast i8** [[TMP97]] to i32* 4627 // CHECK4-NEXT: store i32 [[TMP88]], i32* [[TMP98]], align 4 4628 // CHECK4-NEXT: [[TMP99:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 4629 // CHECK4-NEXT: store i64 4, i64* [[TMP99]], align 4 4630 // CHECK4-NEXT: [[TMP100:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 0 4631 // CHECK4-NEXT: store i8* null, i8** [[TMP100]], align 4 4632 // CHECK4-NEXT: [[TMP101:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 1 4633 // CHECK4-NEXT: [[TMP102:%.*]] = bitcast i8** [[TMP101]] to [10 x float]** 4634 // CHECK4-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP102]], align 4 4635 // CHECK4-NEXT: [[TMP103:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 1 4636 // CHECK4-NEXT: [[TMP104:%.*]] = bitcast i8** [[TMP103]] to [10 x float]** 4637 // CHECK4-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP104]], align 4 4638 // CHECK4-NEXT: [[TMP105:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 4639 // CHECK4-NEXT: store i64 40, i64* [[TMP105]], align 4 4640 // CHECK4-NEXT: [[TMP106:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 1 4641 // CHECK4-NEXT: store i8* null, i8** [[TMP106]], align 4 4642 // CHECK4-NEXT: [[TMP107:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 2 4643 // CHECK4-NEXT: [[TMP108:%.*]] = bitcast i8** [[TMP107]] to i32* 4644 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[TMP108]], align 4 4645 // CHECK4-NEXT: [[TMP109:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 2 4646 // CHECK4-NEXT: [[TMP110:%.*]] = bitcast i8** [[TMP109]] to i32* 4647 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[TMP110]], align 4 4648 // CHECK4-NEXT: [[TMP111:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 4649 // CHECK4-NEXT: store i64 4, i64* [[TMP111]], align 4 4650 // CHECK4-NEXT: [[TMP112:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 2 4651 // CHECK4-NEXT: store i8* null, i8** [[TMP112]], align 4 4652 // CHECK4-NEXT: [[TMP113:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 3 4653 // CHECK4-NEXT: [[TMP114:%.*]] = bitcast i8** [[TMP113]] to float** 4654 // CHECK4-NEXT: store float* [[VLA]], float** [[TMP114]], align 4 4655 // CHECK4-NEXT: [[TMP115:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 3 4656 // CHECK4-NEXT: [[TMP116:%.*]] = bitcast i8** [[TMP115]] to float** 4657 // CHECK4-NEXT: store float* [[VLA]], float** [[TMP116]], align 4 4658 // CHECK4-NEXT: [[TMP117:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 4659 // CHECK4-NEXT: store i64 [[TMP91]], i64* [[TMP117]], align 4 4660 // CHECK4-NEXT: [[TMP118:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 3 4661 // CHECK4-NEXT: store i8* null, i8** [[TMP118]], align 4 4662 // CHECK4-NEXT: [[TMP119:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 4 4663 // CHECK4-NEXT: [[TMP120:%.*]] = bitcast i8** [[TMP119]] to [5 x [10 x double]]** 4664 // CHECK4-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP120]], align 4 4665 // CHECK4-NEXT: [[TMP121:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 4 4666 // CHECK4-NEXT: [[TMP122:%.*]] = bitcast i8** [[TMP121]] to [5 x [10 x double]]** 4667 // CHECK4-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP122]], align 4 4668 // CHECK4-NEXT: [[TMP123:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 4669 // CHECK4-NEXT: store i64 400, i64* [[TMP123]], align 4 4670 // CHECK4-NEXT: [[TMP124:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 4 4671 // CHECK4-NEXT: store i8* null, i8** [[TMP124]], align 4 4672 // CHECK4-NEXT: [[TMP125:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 5 4673 // CHECK4-NEXT: [[TMP126:%.*]] = bitcast i8** [[TMP125]] to i32* 4674 // CHECK4-NEXT: store i32 5, i32* [[TMP126]], align 4 4675 // CHECK4-NEXT: [[TMP127:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 5 4676 // CHECK4-NEXT: [[TMP128:%.*]] = bitcast i8** [[TMP127]] to i32* 4677 // CHECK4-NEXT: store i32 5, i32* [[TMP128]], align 4 4678 // CHECK4-NEXT: [[TMP129:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 5 4679 // CHECK4-NEXT: store i64 4, i64* [[TMP129]], align 4 4680 // CHECK4-NEXT: [[TMP130:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 5 4681 // CHECK4-NEXT: store i8* null, i8** [[TMP130]], align 4 4682 // CHECK4-NEXT: [[TMP131:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 6 4683 // CHECK4-NEXT: [[TMP132:%.*]] = bitcast i8** [[TMP131]] to i32* 4684 // CHECK4-NEXT: store i32 [[TMP3]], i32* [[TMP132]], align 4 4685 // CHECK4-NEXT: [[TMP133:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 6 4686 // CHECK4-NEXT: [[TMP134:%.*]] = bitcast i8** [[TMP133]] to i32* 4687 // CHECK4-NEXT: store i32 [[TMP3]], i32* [[TMP134]], align 4 4688 // CHECK4-NEXT: [[TMP135:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 6 4689 // CHECK4-NEXT: store i64 4, i64* [[TMP135]], align 4 4690 // CHECK4-NEXT: [[TMP136:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 6 4691 // CHECK4-NEXT: store i8* null, i8** [[TMP136]], align 4 4692 // CHECK4-NEXT: [[TMP137:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 7 4693 // CHECK4-NEXT: [[TMP138:%.*]] = bitcast i8** [[TMP137]] to double** 4694 // CHECK4-NEXT: store double* [[VLA1]], double** [[TMP138]], align 4 4695 // CHECK4-NEXT: [[TMP139:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 7 4696 // CHECK4-NEXT: [[TMP140:%.*]] = bitcast i8** [[TMP139]] to double** 4697 // CHECK4-NEXT: store double* [[VLA1]], double** [[TMP140]], align 4 4698 // CHECK4-NEXT: [[TMP141:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 4699 // CHECK4-NEXT: store i64 [[TMP94]], i64* [[TMP141]], align 4 4700 // CHECK4-NEXT: [[TMP142:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 7 4701 // CHECK4-NEXT: store i8* null, i8** [[TMP142]], align 4 4702 // CHECK4-NEXT: [[TMP143:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 8 4703 // CHECK4-NEXT: [[TMP144:%.*]] = bitcast i8** [[TMP143]] to %struct.TT** 4704 // CHECK4-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP144]], align 4 4705 // CHECK4-NEXT: [[TMP145:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 8 4706 // CHECK4-NEXT: [[TMP146:%.*]] = bitcast i8** [[TMP145]] to %struct.TT** 4707 // CHECK4-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP146]], align 4 4708 // CHECK4-NEXT: [[TMP147:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 8 4709 // CHECK4-NEXT: store i64 12, i64* [[TMP147]], align 4 4710 // CHECK4-NEXT: [[TMP148:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 8 4711 // CHECK4-NEXT: store i8* null, i8** [[TMP148]], align 4 4712 // CHECK4-NEXT: [[TMP149:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0 4713 // CHECK4-NEXT: [[TMP150:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 0 4714 // CHECK4-NEXT: [[TMP151:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 4715 // CHECK4-NEXT: [[TMP152:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142.region_id, i32 9, i8** [[TMP149]], i8** [[TMP150]], i64* [[TMP151]], i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 4716 // CHECK4-NEXT: [[TMP153:%.*]] = icmp ne i32 [[TMP152]], 0 4717 // CHECK4-NEXT: br i1 [[TMP153]], label [[OMP_OFFLOAD_FAILED23:%.*]], label [[OMP_OFFLOAD_CONT24:%.*]] 4718 // CHECK4: omp_offload.failed23: 4719 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i32 [[TMP88]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR3]] 4720 // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT24]] 4721 // CHECK4: omp_offload.cont24: 4722 // CHECK4-NEXT: br label [[OMP_IF_END26:%.*]] 4723 // CHECK4: omp_if.else25: 4724 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i32 [[TMP88]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR3]] 4725 // CHECK4-NEXT: br label [[OMP_IF_END26]] 4726 // CHECK4: omp_if.end26: 4727 // CHECK4-NEXT: store i32 0, i32* [[NN]], align 4 4728 // CHECK4-NEXT: [[TMP154:%.*]] = load i32, i32* [[NN]], align 4 4729 // CHECK4-NEXT: store i32 [[TMP154]], i32* [[NN_CASTED]], align 4 4730 // CHECK4-NEXT: [[TMP155:%.*]] = load i32, i32* [[NN_CASTED]], align 4 4731 // CHECK4-NEXT: [[TMP156:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS27]], i32 0, i32 0 4732 // CHECK4-NEXT: [[TMP157:%.*]] = bitcast i8** [[TMP156]] to i32* 4733 // CHECK4-NEXT: store i32 [[TMP155]], i32* [[TMP157]], align 4 4734 // CHECK4-NEXT: [[TMP158:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS28]], i32 0, i32 0 4735 // CHECK4-NEXT: [[TMP159:%.*]] = bitcast i8** [[TMP158]] to i32* 4736 // CHECK4-NEXT: store i32 [[TMP155]], i32* [[TMP159]], align 4 4737 // CHECK4-NEXT: [[TMP160:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS29]], i32 0, i32 0 4738 // CHECK4-NEXT: store i8* null, i8** [[TMP160]], align 4 4739 // CHECK4-NEXT: [[TMP161:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS27]], i32 0, i32 0 4740 // CHECK4-NEXT: [[TMP162:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS28]], i32 0, i32 0 4741 // CHECK4-NEXT: [[TMP163:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154.region_id, i32 1, i8** [[TMP161]], i8** [[TMP162]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.13, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.14, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 4742 // CHECK4-NEXT: [[TMP164:%.*]] = icmp ne i32 [[TMP163]], 0 4743 // CHECK4-NEXT: br i1 [[TMP164]], label [[OMP_OFFLOAD_FAILED30:%.*]], label [[OMP_OFFLOAD_CONT31:%.*]] 4744 // CHECK4: omp_offload.failed30: 4745 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154(i32 [[TMP155]]) #[[ATTR3]] 4746 // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT31]] 4747 // CHECK4: omp_offload.cont31: 4748 // CHECK4-NEXT: [[TMP165:%.*]] = load i32, i32* [[NN]], align 4 4749 // CHECK4-NEXT: store i32 [[TMP165]], i32* [[NN_CASTED32]], align 4 4750 // CHECK4-NEXT: [[TMP166:%.*]] = load i32, i32* [[NN_CASTED32]], align 4 4751 // CHECK4-NEXT: [[TMP167:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS33]], i32 0, i32 0 4752 // CHECK4-NEXT: [[TMP168:%.*]] = bitcast i8** [[TMP167]] to i32* 4753 // CHECK4-NEXT: store i32 [[TMP166]], i32* [[TMP168]], align 4 4754 // CHECK4-NEXT: [[TMP169:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS34]], i32 0, i32 0 4755 // CHECK4-NEXT: [[TMP170:%.*]] = bitcast i8** [[TMP169]] to i32* 4756 // CHECK4-NEXT: store i32 [[TMP166]], i32* [[TMP170]], align 4 4757 // CHECK4-NEXT: [[TMP171:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS35]], i32 0, i32 0 4758 // CHECK4-NEXT: store i8* null, i8** [[TMP171]], align 4 4759 // CHECK4-NEXT: [[TMP172:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS33]], i32 0, i32 0 4760 // CHECK4-NEXT: [[TMP173:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS34]], i32 0, i32 0 4761 // CHECK4-NEXT: [[TMP174:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157.region_id, i32 1, i8** [[TMP172]], i8** [[TMP173]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.17, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.18, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 4762 // CHECK4-NEXT: [[TMP175:%.*]] = icmp ne i32 [[TMP174]], 0 4763 // CHECK4-NEXT: br i1 [[TMP175]], label [[OMP_OFFLOAD_FAILED36:%.*]], label [[OMP_OFFLOAD_CONT37:%.*]] 4764 // CHECK4: omp_offload.failed36: 4765 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157(i32 [[TMP166]]) #[[ATTR3]] 4766 // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT37]] 4767 // CHECK4: omp_offload.cont37: 4768 // CHECK4-NEXT: [[TMP176:%.*]] = load i32, i32* [[A]], align 4 4769 // CHECK4-NEXT: [[TMP177:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 4770 // CHECK4-NEXT: call void @llvm.stackrestore(i8* [[TMP177]]) 4771 // CHECK4-NEXT: ret i32 [[TMP176]] 4772 // 4773 // 4774 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101 4775 // CHECK4-SAME: (i32 [[AA:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]], i32 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] { 4776 // CHECK4-NEXT: entry: 4777 // CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 4778 // CHECK4-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 4779 // CHECK4-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4 4780 // CHECK4-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 4781 // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 4782 // CHECK4-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 4783 // CHECK4-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 4784 // CHECK4-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 4785 // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 4786 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 4787 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 4788 // CHECK4-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) 4789 // CHECK4-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 4790 // CHECK4-NEXT: [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 4791 // CHECK4-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 4792 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 4793 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]]) 4794 // CHECK4-NEXT: ret void 4795 // 4796 // 4797 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. 4798 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] { 4799 // CHECK4-NEXT: entry: 4800 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 4801 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 4802 // CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 4803 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 4804 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 4805 // CHECK4-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 4806 // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 4807 // CHECK4-NEXT: ret void 4808 // 4809 // 4810 // CHECK4-LABEL: define {{[^@]+}}@.omp_task_privates_map. 4811 // CHECK4-SAME: (%struct..kmp_privates.t* noalias [[TMP0:%.*]], i16** noalias [[TMP1:%.*]], [3 x i8*]** noalias [[TMP2:%.*]], [3 x i8*]** noalias [[TMP3:%.*]], [3 x i64]** noalias [[TMP4:%.*]]) #[[ATTR4:[0-9]+]] { 4812 // CHECK4-NEXT: entry: 4813 // CHECK4-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 4 4814 // CHECK4-NEXT: [[DOTADDR1:%.*]] = alloca i16**, align 4 4815 // CHECK4-NEXT: [[DOTADDR2:%.*]] = alloca [3 x i8*]**, align 4 4816 // CHECK4-NEXT: [[DOTADDR3:%.*]] = alloca [3 x i8*]**, align 4 4817 // CHECK4-NEXT: [[DOTADDR4:%.*]] = alloca [3 x i64]**, align 4 4818 // CHECK4-NEXT: store %struct..kmp_privates.t* [[TMP0]], %struct..kmp_privates.t** [[DOTADDR]], align 4 4819 // CHECK4-NEXT: store i16** [[TMP1]], i16*** [[DOTADDR1]], align 4 4820 // CHECK4-NEXT: store [3 x i8*]** [[TMP2]], [3 x i8*]*** [[DOTADDR2]], align 4 4821 // CHECK4-NEXT: store [3 x i8*]** [[TMP3]], [3 x i8*]*** [[DOTADDR3]], align 4 4822 // CHECK4-NEXT: store [3 x i64]** [[TMP4]], [3 x i64]*** [[DOTADDR4]], align 4 4823 // CHECK4-NEXT: [[TMP5:%.*]] = load %struct..kmp_privates.t*, %struct..kmp_privates.t** [[DOTADDR]], align 4 4824 // CHECK4-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 0 4825 // CHECK4-NEXT: [[TMP7:%.*]] = load [3 x i64]**, [3 x i64]*** [[DOTADDR4]], align 4 4826 // CHECK4-NEXT: store [3 x i64]* [[TMP6]], [3 x i64]** [[TMP7]], align 4 4827 // CHECK4-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 1 4828 // CHECK4-NEXT: [[TMP9:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR2]], align 4 4829 // CHECK4-NEXT: store [3 x i8*]* [[TMP8]], [3 x i8*]** [[TMP9]], align 4 4830 // CHECK4-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 2 4831 // CHECK4-NEXT: [[TMP11:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR3]], align 4 4832 // CHECK4-NEXT: store [3 x i8*]* [[TMP10]], [3 x i8*]** [[TMP11]], align 4 4833 // CHECK4-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 3 4834 // CHECK4-NEXT: [[TMP13:%.*]] = load i16**, i16*** [[DOTADDR1]], align 4 4835 // CHECK4-NEXT: store i16* [[TMP12]], i16** [[TMP13]], align 4 4836 // CHECK4-NEXT: ret void 4837 // 4838 // 4839 // CHECK4-LABEL: define {{[^@]+}}@.omp_task_entry. 4840 // CHECK4-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { 4841 // CHECK4-NEXT: entry: 4842 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 4843 // CHECK4-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 4 4844 // CHECK4-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 4 4845 // CHECK4-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 4 4846 // CHECK4-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 4 4847 // CHECK4-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 4 4848 // CHECK4-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca i16*, align 4 4849 // CHECK4-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca [3 x i8*]*, align 4 4850 // CHECK4-NEXT: [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca [3 x i8*]*, align 4 4851 // CHECK4-NEXT: [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca [3 x i64]*, align 4 4852 // CHECK4-NEXT: [[AA_CASTED_I:%.*]] = alloca i32, align 4 4853 // CHECK4-NEXT: [[DOTCAPTURE_EXPR__CASTED_I:%.*]] = alloca i32, align 4 4854 // CHECK4-NEXT: [[DOTCAPTURE_EXPR__CASTED4_I:%.*]] = alloca i32, align 4 4855 // CHECK4-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 4856 // CHECK4-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 4 4857 // CHECK4-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 4858 // CHECK4-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4 4859 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 4860 // CHECK4-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4 4861 // CHECK4-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0 4862 // CHECK4-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 4863 // CHECK4-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 4864 // CHECK4-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 4 4865 // CHECK4-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon* 4866 // CHECK4-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1 4867 // CHECK4-NEXT: [[TMP10:%.*]] = bitcast %struct..kmp_privates.t* [[TMP9]] to i8* 4868 // CHECK4-NEXT: [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8* 4869 // CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]]) 4870 // CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]]) 4871 // CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]]) 4872 // CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META22:![0-9]+]]) 4873 // CHECK4-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !24 4874 // CHECK4-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 4, !noalias !24 4875 // CHECK4-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !24 4876 // CHECK4-NEXT: store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* @.omp_task_privates_map. to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !24 4877 // CHECK4-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 4, !noalias !24 4878 // CHECK4-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !24 4879 // CHECK4-NEXT: [[TMP12:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !24 4880 // CHECK4-NEXT: [[TMP13:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !24 4881 // CHECK4-NEXT: [[TMP14:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !24 4882 // CHECK4-NEXT: [[TMP15:%.*]] = bitcast void (i8*, ...)* [[TMP13]] to void (i8*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* 4883 // CHECK4-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]] 4884 // CHECK4-NEXT: [[TMP16:%.*]] = load i16*, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 4, !noalias !24 4885 // CHECK4-NEXT: [[TMP17:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 4, !noalias !24 4886 // CHECK4-NEXT: [[TMP18:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 4, !noalias !24 4887 // CHECK4-NEXT: [[TMP19:%.*]] = load [3 x i64]*, [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 4, !noalias !24 4888 // CHECK4-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP17]], i32 0, i32 0 4889 // CHECK4-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP18]], i32 0, i32 0 4890 // CHECK4-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[TMP19]], i32 0, i32 0 4891 // CHECK4-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP12]], i32 0, i32 1 4892 // CHECK4-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[TMP12]], i32 0, i32 2 4893 // CHECK4-NEXT: [[TMP25:%.*]] = load i32, i32* [[TMP23]], align 4 4894 // CHECK4-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP24]], align 4 4895 // CHECK4-NEXT: [[TMP27:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 [[TMP25]], i32 [[TMP26]]) #[[ATTR3]] 4896 // CHECK4-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0 4897 // CHECK4-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]] 4898 // CHECK4: omp_offload.failed.i: 4899 // CHECK4-NEXT: [[TMP29:%.*]] = load i16, i16* [[TMP16]], align 2 4900 // CHECK4-NEXT: [[CONV_I:%.*]] = bitcast i32* [[AA_CASTED_I]] to i16* 4901 // CHECK4-NEXT: store i16 [[TMP29]], i16* [[CONV_I]], align 2, !noalias !24 4902 // CHECK4-NEXT: [[TMP30:%.*]] = load i32, i32* [[AA_CASTED_I]], align 4, !noalias !24 4903 // CHECK4-NEXT: [[TMP31:%.*]] = load i32, i32* [[TMP23]], align 4 4904 // CHECK4-NEXT: store i32 [[TMP31]], i32* [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias !24 4905 // CHECK4-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias !24 4906 // CHECK4-NEXT: [[TMP33:%.*]] = load i32, i32* [[TMP24]], align 4 4907 // CHECK4-NEXT: store i32 [[TMP33]], i32* [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias !24 4908 // CHECK4-NEXT: [[TMP34:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias !24 4909 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101(i32 [[TMP30]], i32 [[TMP32]], i32 [[TMP34]]) #[[ATTR3]] 4910 // CHECK4-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]] 4911 // CHECK4: .omp_outlined..1.exit: 4912 // CHECK4-NEXT: ret i32 0 4913 // 4914 // 4915 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l105 4916 // CHECK4-SAME: (i32 [[A:%.*]]) #[[ATTR2]] { 4917 // CHECK4-NEXT: entry: 4918 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 4919 // CHECK4-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 4920 // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 4921 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 4922 // CHECK4-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 4923 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 4924 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]]) 4925 // CHECK4-NEXT: ret void 4926 // 4927 // 4928 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..2 4929 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]]) #[[ATTR2]] { 4930 // CHECK4-NEXT: entry: 4931 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 4932 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 4933 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 4934 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 4935 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 4936 // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 4937 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 4938 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 4939 // CHECK4-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 4940 // CHECK4-NEXT: ret void 4941 // 4942 // 4943 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 4944 // CHECK4-SAME: (i32 [[AA:%.*]]) #[[ATTR2]] { 4945 // CHECK4-NEXT: entry: 4946 // CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 4947 // CHECK4-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 4948 // CHECK4-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 4949 // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 4950 // CHECK4-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 4951 // CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 4952 // CHECK4-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 4953 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 4954 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP1]]) 4955 // CHECK4-NEXT: ret void 4956 // 4957 // 4958 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..3 4959 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] { 4960 // CHECK4-NEXT: entry: 4961 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 4962 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 4963 // CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 4964 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 4965 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 4966 // CHECK4-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 4967 // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 4968 // CHECK4-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 4969 // CHECK4-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 4970 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 4971 // CHECK4-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 4972 // CHECK4-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 4 4973 // CHECK4-NEXT: ret void 4974 // 4975 // 4976 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118 4977 // CHECK4-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] { 4978 // CHECK4-NEXT: entry: 4979 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 4980 // CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 4981 // CHECK4-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 4982 // CHECK4-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 4983 // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 4984 // CHECK4-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 4985 // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 4986 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 4987 // CHECK4-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 4988 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 4989 // CHECK4-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 4990 // CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 4991 // CHECK4-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 4992 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 4993 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) 4994 // CHECK4-NEXT: ret void 4995 // 4996 // 4997 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..6 4998 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] { 4999 // CHECK4-NEXT: entry: 5000 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 5001 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 5002 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 5003 // CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 5004 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 5005 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 5006 // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 5007 // CHECK4-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 5008 // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 5009 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 5010 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 5011 // CHECK4-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 5012 // CHECK4-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 4 5013 // CHECK4-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32 5014 // CHECK4-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 5015 // CHECK4-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 5016 // CHECK4-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 4 5017 // CHECK4-NEXT: ret void 5018 // 5019 // 5020 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142 5021 // CHECK4-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] { 5022 // CHECK4-NEXT: entry: 5023 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 5024 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 5025 // CHECK4-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 5026 // CHECK4-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 5027 // CHECK4-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 5028 // CHECK4-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 5029 // CHECK4-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 5030 // CHECK4-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 5031 // CHECK4-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 5032 // CHECK4-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 5033 // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 5034 // CHECK4-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 5035 // CHECK4-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 5036 // CHECK4-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 5037 // CHECK4-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 5038 // CHECK4-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 5039 // CHECK4-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 5040 // CHECK4-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 5041 // CHECK4-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 5042 // CHECK4-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 5043 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 5044 // CHECK4-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 5045 // CHECK4-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 5046 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 5047 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 5048 // CHECK4-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 5049 // CHECK4-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 5050 // CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 5051 // CHECK4-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4 5052 // CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4 5053 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) 5054 // CHECK4-NEXT: ret void 5055 // 5056 // 5057 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..9 5058 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] { 5059 // CHECK4-NEXT: entry: 5060 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 5061 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 5062 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 5063 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 5064 // CHECK4-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 5065 // CHECK4-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 5066 // CHECK4-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 5067 // CHECK4-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 5068 // CHECK4-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 5069 // CHECK4-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 5070 // CHECK4-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 5071 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 5072 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 5073 // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 5074 // CHECK4-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 5075 // CHECK4-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 5076 // CHECK4-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 5077 // CHECK4-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 5078 // CHECK4-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 5079 // CHECK4-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 5080 // CHECK4-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 5081 // CHECK4-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 5082 // CHECK4-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 5083 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 5084 // CHECK4-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 5085 // CHECK4-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 5086 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 5087 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 5088 // CHECK4-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 5089 // CHECK4-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 5090 // CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 5091 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 5092 // CHECK4-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 5093 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2 5094 // CHECK4-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 5095 // CHECK4-NEXT: [[CONV:%.*]] = fpext float [[TMP9]] to double 5096 // CHECK4-NEXT: [[ADD5:%.*]] = fadd double [[CONV]], 1.000000e+00 5097 // CHECK4-NEXT: [[CONV6:%.*]] = fptrunc double [[ADD5]] to float 5098 // CHECK4-NEXT: store float [[CONV6]], float* [[ARRAYIDX]], align 4 5099 // CHECK4-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3 5100 // CHECK4-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX7]], align 4 5101 // CHECK4-NEXT: [[CONV8:%.*]] = fpext float [[TMP10]] to double 5102 // CHECK4-NEXT: [[ADD9:%.*]] = fadd double [[CONV8]], 1.000000e+00 5103 // CHECK4-NEXT: [[CONV10:%.*]] = fptrunc double [[ADD9]] to float 5104 // CHECK4-NEXT: store float [[CONV10]], float* [[ARRAYIDX7]], align 4 5105 // CHECK4-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1 5106 // CHECK4-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX11]], i32 0, i32 2 5107 // CHECK4-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX12]], align 8 5108 // CHECK4-NEXT: [[ADD13:%.*]] = fadd double [[TMP11]], 1.000000e+00 5109 // CHECK4-NEXT: store double [[ADD13]], double* [[ARRAYIDX12]], align 8 5110 // CHECK4-NEXT: [[TMP12:%.*]] = mul nsw i32 1, [[TMP5]] 5111 // CHECK4-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP12]] 5112 // CHECK4-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX14]], i32 3 5113 // CHECK4-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX15]], align 8 5114 // CHECK4-NEXT: [[ADD16:%.*]] = fadd double [[TMP13]], 1.000000e+00 5115 // CHECK4-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8 5116 // CHECK4-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 5117 // CHECK4-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 4 5118 // CHECK4-NEXT: [[ADD17:%.*]] = add nsw i64 [[TMP14]], 1 5119 // CHECK4-NEXT: store i64 [[ADD17]], i64* [[X]], align 4 5120 // CHECK4-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 5121 // CHECK4-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 4 5122 // CHECK4-NEXT: [[CONV18:%.*]] = sext i8 [[TMP15]] to i32 5123 // CHECK4-NEXT: [[ADD19:%.*]] = add nsw i32 [[CONV18]], 1 5124 // CHECK4-NEXT: [[CONV20:%.*]] = trunc i32 [[ADD19]] to i8 5125 // CHECK4-NEXT: store i8 [[CONV20]], i8* [[Y]], align 4 5126 // CHECK4-NEXT: ret void 5127 // 5128 // 5129 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154 5130 // CHECK4-SAME: (i32 [[NN:%.*]]) #[[ATTR2]] { 5131 // CHECK4-NEXT: entry: 5132 // CHECK4-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 5133 // CHECK4-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4 5134 // CHECK4-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 5135 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[NN_ADDR]], align 4 5136 // CHECK4-NEXT: store i32 [[TMP0]], i32* [[NN_CASTED]], align 4 5137 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[NN_CASTED]], align 4 5138 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP1]]) 5139 // CHECK4-NEXT: ret void 5140 // 5141 // 5142 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..11 5143 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[NN:%.*]]) #[[ATTR2]] { 5144 // CHECK4-NEXT: entry: 5145 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 5146 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 5147 // CHECK4-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 5148 // CHECK4-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4 5149 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 5150 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 5151 // CHECK4-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 5152 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[NN_ADDR]], align 4 5153 // CHECK4-NEXT: store i32 [[TMP0]], i32* [[NN_CASTED]], align 4 5154 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[NN_CASTED]], align 4 5155 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..12 to void (i32*, i32*, ...)*), i32 [[TMP1]]) 5156 // CHECK4-NEXT: ret void 5157 // 5158 // 5159 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..12 5160 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[NN:%.*]]) #[[ATTR2]] { 5161 // CHECK4-NEXT: entry: 5162 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 5163 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 5164 // CHECK4-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 5165 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 5166 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 5167 // CHECK4-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 5168 // CHECK4-NEXT: ret void 5169 // 5170 // 5171 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157 5172 // CHECK4-SAME: (i32 [[NN:%.*]]) #[[ATTR2]] { 5173 // CHECK4-NEXT: entry: 5174 // CHECK4-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 5175 // CHECK4-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4 5176 // CHECK4-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 5177 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[NN_ADDR]], align 4 5178 // CHECK4-NEXT: store i32 [[TMP0]], i32* [[NN_CASTED]], align 4 5179 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[NN_CASTED]], align 4 5180 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i32 [[TMP1]]) 5181 // CHECK4-NEXT: ret void 5182 // 5183 // 5184 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..15 5185 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[NN:%.*]]) #[[ATTR2]] { 5186 // CHECK4-NEXT: entry: 5187 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 5188 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 5189 // CHECK4-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 5190 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 5191 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 5192 // CHECK4-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 5193 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i32* [[NN_ADDR]]) 5194 // CHECK4-NEXT: ret void 5195 // 5196 // 5197 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..16 5198 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[NN:%.*]]) #[[ATTR2]] { 5199 // CHECK4-NEXT: entry: 5200 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 5201 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 5202 // CHECK4-NEXT: [[NN_ADDR:%.*]] = alloca i32*, align 4 5203 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 5204 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 5205 // CHECK4-NEXT: store i32* [[NN]], i32** [[NN_ADDR]], align 4 5206 // CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[NN_ADDR]], align 4 5207 // CHECK4-NEXT: ret void 5208 // 5209 // 5210 // CHECK4-LABEL: define {{[^@]+}}@_Z6bazzzziPi 5211 // CHECK4-SAME: (i32 [[N:%.*]], i32* [[F:%.*]]) #[[ATTR0]] { 5212 // CHECK4-NEXT: entry: 5213 // CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 5214 // CHECK4-NEXT: [[F_ADDR:%.*]] = alloca i32*, align 4 5215 // CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 5216 // CHECK4-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 5217 // CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 5218 // CHECK4-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 5219 // CHECK4-NEXT: store i32* [[F]], i32** [[F_ADDR]], align 4 5220 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 5221 // CHECK4-NEXT: [[TMP1:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 5222 // CHECK4-NEXT: [[TMP2:%.*]] = bitcast i8** [[TMP1]] to i32* 5223 // CHECK4-NEXT: store i32 [[TMP0]], i32* [[TMP2]], align 4 5224 // CHECK4-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 5225 // CHECK4-NEXT: [[TMP4:%.*]] = bitcast i8** [[TMP3]] to i32* 5226 // CHECK4-NEXT: store i32 [[TMP0]], i32* [[TMP4]], align 4 5227 // CHECK4-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 5228 // CHECK4-NEXT: store i8* null, i8** [[TMP5]], align 4 5229 // CHECK4-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 5230 // CHECK4-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 5231 // CHECK4-NEXT: [[TMP8:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182.region_id, i32 1, i8** [[TMP6]], i8** [[TMP7]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.20, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.21, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 5232 // CHECK4-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0 5233 // CHECK4-NEXT: br i1 [[TMP9]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 5234 // CHECK4: omp_offload.failed: 5235 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182(i32 [[TMP0]]) #[[ATTR3]] 5236 // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]] 5237 // CHECK4: omp_offload.cont: 5238 // CHECK4-NEXT: ret void 5239 // 5240 // 5241 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182 5242 // CHECK4-SAME: (i32 [[VLA:%.*]]) #[[ATTR2]] { 5243 // CHECK4-NEXT: entry: 5244 // CHECK4-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 5245 // CHECK4-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 5246 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 5247 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..19 to void (i32*, i32*, ...)*), i32 [[TMP0]]) 5248 // CHECK4-NEXT: ret void 5249 // 5250 // 5251 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..19 5252 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[VLA:%.*]]) #[[ATTR2]] { 5253 // CHECK4-NEXT: entry: 5254 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 5255 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 5256 // CHECK4-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 5257 // CHECK4-NEXT: [[F:%.*]] = alloca i32*, align 4 5258 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 5259 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 5260 // CHECK4-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 5261 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 5262 // CHECK4-NEXT: ret void 5263 // 5264 // 5265 // CHECK4-LABEL: define {{[^@]+}}@_Z3bari 5266 // CHECK4-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { 5267 // CHECK4-NEXT: entry: 5268 // CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 5269 // CHECK4-NEXT: [[A:%.*]] = alloca i32, align 4 5270 // CHECK4-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 5271 // CHECK4-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 5272 // CHECK4-NEXT: store i32 0, i32* [[A]], align 4 5273 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 5274 // CHECK4-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]]) 5275 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 5276 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 5277 // CHECK4-NEXT: store i32 [[ADD]], i32* [[A]], align 4 5278 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 5279 // CHECK4-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]]) 5280 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 5281 // CHECK4-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 5282 // CHECK4-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 5283 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 5284 // CHECK4-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]]) 5285 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 5286 // CHECK4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 5287 // CHECK4-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 5288 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 5289 // CHECK4-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]]) 5290 // CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 5291 // CHECK4-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] 5292 // CHECK4-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 5293 // CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 5294 // CHECK4-NEXT: ret i32 [[TMP8]] 5295 // 5296 // 5297 // CHECK4-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 5298 // CHECK4-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { 5299 // CHECK4-NEXT: entry: 5300 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 5301 // CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 5302 // CHECK4-NEXT: [[B:%.*]] = alloca i32, align 4 5303 // CHECK4-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 5304 // CHECK4-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 5305 // CHECK4-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 5306 // CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4 5307 // CHECK4-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4 5308 // CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4 5309 // CHECK4-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 4 5310 // CHECK4-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 5311 // CHECK4-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 5312 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 5313 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 5314 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 5315 // CHECK4-NEXT: store i32 [[ADD]], i32* [[B]], align 4 5316 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 5317 // CHECK4-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() 5318 // CHECK4-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 5319 // CHECK4-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] 5320 // CHECK4-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 5321 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 5322 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[B]], align 4 5323 // CHECK4-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 5324 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 5325 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 5326 // CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 60 5327 // CHECK4-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 5328 // CHECK4: omp_if.then: 5329 // CHECK4-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 5330 // CHECK4-NEXT: [[TMP7:%.*]] = mul nuw i32 2, [[TMP1]] 5331 // CHECK4-NEXT: [[TMP8:%.*]] = mul nuw i32 [[TMP7]], 2 5332 // CHECK4-NEXT: [[TMP9:%.*]] = sext i32 [[TMP8]] to i64 5333 // CHECK4-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 5334 // CHECK4-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to %struct.S1** 5335 // CHECK4-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP11]], align 4 5336 // CHECK4-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 5337 // CHECK4-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to double** 5338 // CHECK4-NEXT: store double* [[A]], double** [[TMP13]], align 4 5339 // CHECK4-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 5340 // CHECK4-NEXT: store i64 8, i64* [[TMP14]], align 4 5341 // CHECK4-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 5342 // CHECK4-NEXT: store i8* null, i8** [[TMP15]], align 4 5343 // CHECK4-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 5344 // CHECK4-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32* 5345 // CHECK4-NEXT: store i32 [[TMP5]], i32* [[TMP17]], align 4 5346 // CHECK4-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 5347 // CHECK4-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32* 5348 // CHECK4-NEXT: store i32 [[TMP5]], i32* [[TMP19]], align 4 5349 // CHECK4-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 5350 // CHECK4-NEXT: store i64 4, i64* [[TMP20]], align 4 5351 // CHECK4-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 5352 // CHECK4-NEXT: store i8* null, i8** [[TMP21]], align 4 5353 // CHECK4-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 5354 // CHECK4-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i32* 5355 // CHECK4-NEXT: store i32 2, i32* [[TMP23]], align 4 5356 // CHECK4-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 5357 // CHECK4-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i32* 5358 // CHECK4-NEXT: store i32 2, i32* [[TMP25]], align 4 5359 // CHECK4-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 5360 // CHECK4-NEXT: store i64 4, i64* [[TMP26]], align 4 5361 // CHECK4-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 5362 // CHECK4-NEXT: store i8* null, i8** [[TMP27]], align 4 5363 // CHECK4-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 5364 // CHECK4-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i32* 5365 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[TMP29]], align 4 5366 // CHECK4-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 5367 // CHECK4-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i32* 5368 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[TMP31]], align 4 5369 // CHECK4-NEXT: [[TMP32:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 5370 // CHECK4-NEXT: store i64 4, i64* [[TMP32]], align 4 5371 // CHECK4-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 5372 // CHECK4-NEXT: store i8* null, i8** [[TMP33]], align 4 5373 // CHECK4-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 5374 // CHECK4-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i16** 5375 // CHECK4-NEXT: store i16* [[VLA]], i16** [[TMP35]], align 4 5376 // CHECK4-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 5377 // CHECK4-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i16** 5378 // CHECK4-NEXT: store i16* [[VLA]], i16** [[TMP37]], align 4 5379 // CHECK4-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 5380 // CHECK4-NEXT: store i64 [[TMP9]], i64* [[TMP38]], align 4 5381 // CHECK4-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 5382 // CHECK4-NEXT: store i8* null, i8** [[TMP39]], align 4 5383 // CHECK4-NEXT: [[TMP40:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 5384 // CHECK4-NEXT: [[TMP41:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 5385 // CHECK4-NEXT: [[TMP42:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 5386 // CHECK4-NEXT: [[TMP43:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227.region_id, i32 5, i8** [[TMP40]], i8** [[TMP41]], i64* [[TMP42]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.23, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 5387 // CHECK4-NEXT: [[TMP44:%.*]] = icmp ne i32 [[TMP43]], 0 5388 // CHECK4-NEXT: br i1 [[TMP44]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 5389 // CHECK4: omp_offload.failed: 5390 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR3]] 5391 // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]] 5392 // CHECK4: omp_offload.cont: 5393 // CHECK4-NEXT: br label [[OMP_IF_END:%.*]] 5394 // CHECK4: omp_if.else: 5395 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR3]] 5396 // CHECK4-NEXT: br label [[OMP_IF_END]] 5397 // CHECK4: omp_if.end: 5398 // CHECK4-NEXT: [[TMP45:%.*]] = mul nsw i32 1, [[TMP1]] 5399 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP45]] 5400 // CHECK4-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 5401 // CHECK4-NEXT: [[TMP46:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2 5402 // CHECK4-NEXT: [[CONV:%.*]] = sext i16 [[TMP46]] to i32 5403 // CHECK4-NEXT: [[TMP47:%.*]] = load i32, i32* [[B]], align 4 5404 // CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP47]] 5405 // CHECK4-NEXT: [[TMP48:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 5406 // CHECK4-NEXT: call void @llvm.stackrestore(i8* [[TMP48]]) 5407 // CHECK4-NEXT: ret i32 [[ADD3]] 5408 // 5409 // 5410 // CHECK4-LABEL: define {{[^@]+}}@_ZL7fstatici 5411 // CHECK4-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { 5412 // CHECK4-NEXT: entry: 5413 // CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 5414 // CHECK4-NEXT: [[A:%.*]] = alloca i32, align 4 5415 // CHECK4-NEXT: [[AA:%.*]] = alloca i16, align 2 5416 // CHECK4-NEXT: [[AAA:%.*]] = alloca i8, align 1 5417 // CHECK4-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 5418 // CHECK4-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 5419 // CHECK4-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 5420 // CHECK4-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 5421 // CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4 5422 // CHECK4-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 5423 // CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 5424 // CHECK4-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 5425 // CHECK4-NEXT: store i32 0, i32* [[A]], align 4 5426 // CHECK4-NEXT: store i16 0, i16* [[AA]], align 2 5427 // CHECK4-NEXT: store i8 0, i8* [[AAA]], align 1 5428 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 5429 // CHECK4-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 5430 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 5431 // CHECK4-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 5432 // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 5433 // CHECK4-NEXT: store i16 [[TMP2]], i16* [[CONV]], align 2 5434 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 5435 // CHECK4-NEXT: [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1 5436 // CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* 5437 // CHECK4-NEXT: store i8 [[TMP4]], i8* [[CONV1]], align 1 5438 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 5439 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 5440 // CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50 5441 // CHECK4-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 5442 // CHECK4: omp_if.then: 5443 // CHECK4-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 5444 // CHECK4-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* 5445 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4 5446 // CHECK4-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 5447 // CHECK4-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* 5448 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[TMP10]], align 4 5449 // CHECK4-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 5450 // CHECK4-NEXT: store i8* null, i8** [[TMP11]], align 4 5451 // CHECK4-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 5452 // CHECK4-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* 5453 // CHECK4-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4 5454 // CHECK4-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 5455 // CHECK4-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32* 5456 // CHECK4-NEXT: store i32 [[TMP3]], i32* [[TMP15]], align 4 5457 // CHECK4-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 5458 // CHECK4-NEXT: store i8* null, i8** [[TMP16]], align 4 5459 // CHECK4-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 5460 // CHECK4-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32* 5461 // CHECK4-NEXT: store i32 [[TMP5]], i32* [[TMP18]], align 4 5462 // CHECK4-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 5463 // CHECK4-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32* 5464 // CHECK4-NEXT: store i32 [[TMP5]], i32* [[TMP20]], align 4 5465 // CHECK4-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 5466 // CHECK4-NEXT: store i8* null, i8** [[TMP21]], align 4 5467 // CHECK4-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 5468 // CHECK4-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]** 5469 // CHECK4-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 4 5470 // CHECK4-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 5471 // CHECK4-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]** 5472 // CHECK4-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 4 5473 // CHECK4-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 5474 // CHECK4-NEXT: store i8* null, i8** [[TMP26]], align 4 5475 // CHECK4-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 5476 // CHECK4-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 5477 // CHECK4-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.25, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.26, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 5478 // CHECK4-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 5479 // CHECK4-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 5480 // CHECK4: omp_offload.failed: 5481 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR3]] 5482 // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]] 5483 // CHECK4: omp_offload.cont: 5484 // CHECK4-NEXT: br label [[OMP_IF_END:%.*]] 5485 // CHECK4: omp_if.else: 5486 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR3]] 5487 // CHECK4-NEXT: br label [[OMP_IF_END]] 5488 // CHECK4: omp_if.end: 5489 // CHECK4-NEXT: [[TMP31:%.*]] = load i32, i32* [[A]], align 4 5490 // CHECK4-NEXT: ret i32 [[TMP31]] 5491 // 5492 // 5493 // CHECK4-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 5494 // CHECK4-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { 5495 // CHECK4-NEXT: entry: 5496 // CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 5497 // CHECK4-NEXT: [[A:%.*]] = alloca i32, align 4 5498 // CHECK4-NEXT: [[AA:%.*]] = alloca i16, align 2 5499 // CHECK4-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 5500 // CHECK4-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 5501 // CHECK4-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 5502 // CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 5503 // CHECK4-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 5504 // CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 5505 // CHECK4-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 5506 // CHECK4-NEXT: store i32 0, i32* [[A]], align 4 5507 // CHECK4-NEXT: store i16 0, i16* [[AA]], align 2 5508 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 5509 // CHECK4-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 5510 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 5511 // CHECK4-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 5512 // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 5513 // CHECK4-NEXT: store i16 [[TMP2]], i16* [[CONV]], align 2 5514 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 5515 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 5516 // CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40 5517 // CHECK4-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 5518 // CHECK4: omp_if.then: 5519 // CHECK4-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 5520 // CHECK4-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i32* 5521 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[TMP6]], align 4 5522 // CHECK4-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 5523 // CHECK4-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* 5524 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4 5525 // CHECK4-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 5526 // CHECK4-NEXT: store i8* null, i8** [[TMP9]], align 4 5527 // CHECK4-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 5528 // CHECK4-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i32* 5529 // CHECK4-NEXT: store i32 [[TMP3]], i32* [[TMP11]], align 4 5530 // CHECK4-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 5531 // CHECK4-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* 5532 // CHECK4-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4 5533 // CHECK4-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 5534 // CHECK4-NEXT: store i8* null, i8** [[TMP14]], align 4 5535 // CHECK4-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 5536 // CHECK4-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]** 5537 // CHECK4-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 4 5538 // CHECK4-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 5539 // CHECK4-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]** 5540 // CHECK4-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 4 5541 // CHECK4-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 5542 // CHECK4-NEXT: store i8* null, i8** [[TMP19]], align 4 5543 // CHECK4-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 5544 // CHECK4-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 5545 // CHECK4-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.28, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.29, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 5546 // CHECK4-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 5547 // CHECK4-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 5548 // CHECK4: omp_offload.failed: 5549 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]] 5550 // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]] 5551 // CHECK4: omp_offload.cont: 5552 // CHECK4-NEXT: br label [[OMP_IF_END:%.*]] 5553 // CHECK4: omp_if.else: 5554 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]] 5555 // CHECK4-NEXT: br label [[OMP_IF_END]] 5556 // CHECK4: omp_if.end: 5557 // CHECK4-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4 5558 // CHECK4-NEXT: ret i32 [[TMP24]] 5559 // 5560 // 5561 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227 5562 // CHECK4-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { 5563 // CHECK4-NEXT: entry: 5564 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 5565 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 5566 // CHECK4-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 5567 // CHECK4-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 5568 // CHECK4-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 5569 // CHECK4-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 5570 // CHECK4-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 5571 // CHECK4-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 5572 // CHECK4-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 5573 // CHECK4-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 5574 // CHECK4-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 5575 // CHECK4-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 5576 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 5577 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 5578 // CHECK4-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 5579 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 5580 // CHECK4-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 5581 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 5582 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..22 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]]) 5583 // CHECK4-NEXT: ret void 5584 // 5585 // 5586 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..22 5587 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { 5588 // CHECK4-NEXT: entry: 5589 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 5590 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 5591 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 5592 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 5593 // CHECK4-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 5594 // CHECK4-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 5595 // CHECK4-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 5596 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 5597 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 5598 // CHECK4-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 5599 // CHECK4-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 5600 // CHECK4-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 5601 // CHECK4-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 5602 // CHECK4-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 5603 // CHECK4-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 5604 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 5605 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 5606 // CHECK4-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 5607 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 5608 // CHECK4-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP4]] to double 5609 // CHECK4-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 5610 // CHECK4-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 5611 // CHECK4-NEXT: store double [[ADD]], double* [[A]], align 4 5612 // CHECK4-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 5613 // CHECK4-NEXT: [[TMP5:%.*]] = load double, double* [[A3]], align 4 5614 // CHECK4-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 5615 // CHECK4-NEXT: store double [[INC]], double* [[A3]], align 4 5616 // CHECK4-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 5617 // CHECK4-NEXT: [[TMP6:%.*]] = mul nsw i32 1, [[TMP2]] 5618 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP6]] 5619 // CHECK4-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 5620 // CHECK4-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 5621 // CHECK4-NEXT: ret void 5622 // 5623 // 5624 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209 5625 // CHECK4-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 5626 // CHECK4-NEXT: entry: 5627 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 5628 // CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 5629 // CHECK4-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 5630 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 5631 // CHECK4-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 5632 // CHECK4-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 5633 // CHECK4-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 5634 // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 5635 // CHECK4-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 5636 // CHECK4-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 5637 // CHECK4-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 5638 // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 5639 // CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 5640 // CHECK4-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 5641 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 5642 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 5643 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 5644 // CHECK4-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 5645 // CHECK4-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 5646 // CHECK4-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 5647 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 5648 // CHECK4-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 4 5649 // CHECK4-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* 5650 // CHECK4-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 5651 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 5652 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..24 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) 5653 // CHECK4-NEXT: ret void 5654 // 5655 // 5656 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..24 5657 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 5658 // CHECK4-NEXT: entry: 5659 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 5660 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 5661 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 5662 // CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 5663 // CHECK4-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 5664 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 5665 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 5666 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 5667 // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 5668 // CHECK4-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 5669 // CHECK4-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 5670 // CHECK4-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 5671 // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 5672 // CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 5673 // CHECK4-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 5674 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 5675 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 5676 // CHECK4-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 5677 // CHECK4-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 5678 // CHECK4-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 5679 // CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 5680 // CHECK4-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 5681 // CHECK4-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 4 5682 // CHECK4-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 4 5683 // CHECK4-NEXT: [[CONV5:%.*]] = sext i8 [[TMP3]] to i32 5684 // CHECK4-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 5685 // CHECK4-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i8 5686 // CHECK4-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 4 5687 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 5688 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 5689 // CHECK4-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP4]], 1 5690 // CHECK4-NEXT: store i32 [[ADD8]], i32* [[ARRAYIDX]], align 4 5691 // CHECK4-NEXT: ret void 5692 // 5693 // 5694 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192 5695 // CHECK4-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 5696 // CHECK4-NEXT: entry: 5697 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 5698 // CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 5699 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 5700 // CHECK4-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 5701 // CHECK4-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 5702 // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 5703 // CHECK4-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 5704 // CHECK4-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 5705 // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 5706 // CHECK4-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 5707 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 5708 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 5709 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 5710 // CHECK4-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 5711 // CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 5712 // CHECK4-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 5713 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 5714 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..27 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) 5715 // CHECK4-NEXT: ret void 5716 // 5717 // 5718 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..27 5719 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 5720 // CHECK4-NEXT: entry: 5721 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 5722 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 5723 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 5724 // CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 5725 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 5726 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 5727 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 5728 // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 5729 // CHECK4-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 5730 // CHECK4-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 5731 // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 5732 // CHECK4-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 5733 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 5734 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 5735 // CHECK4-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 5736 // CHECK4-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 5737 // CHECK4-NEXT: [[CONV1:%.*]] = sext i16 [[TMP2]] to i32 5738 // CHECK4-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 5739 // CHECK4-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 5740 // CHECK4-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 4 5741 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 5742 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 5743 // CHECK4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1 5744 // CHECK4-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4 5745 // CHECK4-NEXT: ret void 5746 // 5747 // 5748 // CHECK4-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 5749 // CHECK4-SAME: () #[[ATTR4]] { 5750 // CHECK4-NEXT: entry: 5751 // CHECK4-NEXT: call void @__tgt_register_requires(i64 1) 5752 // CHECK4-NEXT: ret void 5753 // 5754 // 5755 // CHECK5-LABEL: define {{[^@]+}}@_Z3fooi 5756 // CHECK5-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { 5757 // CHECK5-NEXT: entry: 5758 // CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 5759 // CHECK5-NEXT: [[A:%.*]] = alloca i32, align 4 5760 // CHECK5-NEXT: [[AA:%.*]] = alloca i16, align 2 5761 // CHECK5-NEXT: [[B:%.*]] = alloca [10 x float], align 4 5762 // CHECK5-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 5763 // CHECK5-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 5764 // CHECK5-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 5765 // CHECK5-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 5766 // CHECK5-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 5767 // CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 5768 // CHECK5-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 5769 // CHECK5-NEXT: [[NN:%.*]] = alloca i32, align 4 5770 // CHECK5-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 5771 // CHECK5-NEXT: store i32 0, i32* [[A]], align 4 5772 // CHECK5-NEXT: store i16 0, i16* [[AA]], align 2 5773 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 5774 // CHECK5-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 5775 // CHECK5-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() 5776 // CHECK5-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 5777 // CHECK5-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4 5778 // CHECK5-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 5779 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 5780 // CHECK5-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64 5781 // CHECK5-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]] 5782 // CHECK5-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8 5783 // CHECK5-NEXT: store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8 5784 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 5785 // CHECK5-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_]], align 4 5786 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 5787 // CHECK5-NEXT: store i32 [[TMP7]], i32* [[DOTCAPTURE_EXPR_2]], align 4 5788 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 5789 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 5790 // CHECK5-NEXT: store i32 [[ADD]], i32* [[A]], align 4 5791 // CHECK5-NEXT: [[TMP9:%.*]] = load i16, i16* [[AA]], align 2 5792 // CHECK5-NEXT: [[CONV:%.*]] = sext i16 [[TMP9]] to i32 5793 // CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1 5794 // CHECK5-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 5795 // CHECK5-NEXT: store i16 [[CONV4]], i16* [[AA]], align 2 5796 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[A]], align 4 5797 // CHECK5-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP10]], 1 5798 // CHECK5-NEXT: store i32 [[ADD5]], i32* [[A]], align 4 5799 // CHECK5-NEXT: [[TMP11:%.*]] = load i16, i16* [[AA]], align 2 5800 // CHECK5-NEXT: [[CONV6:%.*]] = sext i16 [[TMP11]] to i32 5801 // CHECK5-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 5802 // CHECK5-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i16 5803 // CHECK5-NEXT: store i16 [[CONV8]], i16* [[AA]], align 2 5804 // CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[A]], align 4 5805 // CHECK5-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP12]], 1 5806 // CHECK5-NEXT: store i32 [[ADD9]], i32* [[A]], align 4 5807 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2 5808 // CHECK5-NEXT: [[TMP13:%.*]] = load float, float* [[ARRAYIDX]], align 4 5809 // CHECK5-NEXT: [[CONV10:%.*]] = fpext float [[TMP13]] to double 5810 // CHECK5-NEXT: [[ADD11:%.*]] = fadd double [[CONV10]], 1.000000e+00 5811 // CHECK5-NEXT: [[CONV12:%.*]] = fptrunc double [[ADD11]] to float 5812 // CHECK5-NEXT: store float [[CONV12]], float* [[ARRAYIDX]], align 4 5813 // CHECK5-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3 5814 // CHECK5-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX13]], align 4 5815 // CHECK5-NEXT: [[CONV14:%.*]] = fpext float [[TMP14]] to double 5816 // CHECK5-NEXT: [[ADD15:%.*]] = fadd double [[CONV14]], 1.000000e+00 5817 // CHECK5-NEXT: [[CONV16:%.*]] = fptrunc double [[ADD15]] to float 5818 // CHECK5-NEXT: store float [[CONV16]], float* [[ARRAYIDX13]], align 4 5819 // CHECK5-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1 5820 // CHECK5-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX17]], i64 0, i64 2 5821 // CHECK5-NEXT: [[TMP15:%.*]] = load double, double* [[ARRAYIDX18]], align 8 5822 // CHECK5-NEXT: [[ADD19:%.*]] = fadd double [[TMP15]], 1.000000e+00 5823 // CHECK5-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8 5824 // CHECK5-NEXT: [[TMP16:%.*]] = mul nsw i64 1, [[TMP4]] 5825 // CHECK5-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP16]] 5826 // CHECK5-NEXT: [[ARRAYIDX21:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX20]], i64 3 5827 // CHECK5-NEXT: [[TMP17:%.*]] = load double, double* [[ARRAYIDX21]], align 8 5828 // CHECK5-NEXT: [[ADD22:%.*]] = fadd double [[TMP17]], 1.000000e+00 5829 // CHECK5-NEXT: store double [[ADD22]], double* [[ARRAYIDX21]], align 8 5830 // CHECK5-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 5831 // CHECK5-NEXT: [[TMP18:%.*]] = load i64, i64* [[X]], align 8 5832 // CHECK5-NEXT: [[ADD23:%.*]] = add nsw i64 [[TMP18]], 1 5833 // CHECK5-NEXT: store i64 [[ADD23]], i64* [[X]], align 8 5834 // CHECK5-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 5835 // CHECK5-NEXT: [[TMP19:%.*]] = load i8, i8* [[Y]], align 8 5836 // CHECK5-NEXT: [[CONV24:%.*]] = sext i8 [[TMP19]] to i32 5837 // CHECK5-NEXT: [[ADD25:%.*]] = add nsw i32 [[CONV24]], 1 5838 // CHECK5-NEXT: [[CONV26:%.*]] = trunc i32 [[ADD25]] to i8 5839 // CHECK5-NEXT: store i8 [[CONV26]], i8* [[Y]], align 8 5840 // CHECK5-NEXT: store i32 0, i32* [[NN]], align 4 5841 // CHECK5-NEXT: [[TMP20:%.*]] = load i32, i32* [[A]], align 4 5842 // CHECK5-NEXT: [[TMP21:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 5843 // CHECK5-NEXT: call void @llvm.stackrestore(i8* [[TMP21]]) 5844 // CHECK5-NEXT: ret i32 [[TMP20]] 5845 // 5846 // 5847 // CHECK5-LABEL: define {{[^@]+}}@_Z6bazzzziPi 5848 // CHECK5-SAME: (i32 signext [[N:%.*]], i32* [[F:%.*]]) #[[ATTR0]] { 5849 // CHECK5-NEXT: entry: 5850 // CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 5851 // CHECK5-NEXT: [[F_ADDR:%.*]] = alloca i32*, align 8 5852 // CHECK5-NEXT: [[F1:%.*]] = alloca i32*, align 8 5853 // CHECK5-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 5854 // CHECK5-NEXT: store i32* [[F]], i32** [[F_ADDR]], align 8 5855 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 5856 // CHECK5-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 5857 // CHECK5-NEXT: ret void 5858 // 5859 // 5860 // CHECK5-LABEL: define {{[^@]+}}@_Z3bari 5861 // CHECK5-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { 5862 // CHECK5-NEXT: entry: 5863 // CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 5864 // CHECK5-NEXT: [[A:%.*]] = alloca i32, align 4 5865 // CHECK5-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 5866 // CHECK5-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 5867 // CHECK5-NEXT: store i32 0, i32* [[A]], align 4 5868 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 5869 // CHECK5-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]]) 5870 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 5871 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 5872 // CHECK5-NEXT: store i32 [[ADD]], i32* [[A]], align 4 5873 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 5874 // CHECK5-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]]) 5875 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 5876 // CHECK5-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 5877 // CHECK5-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 5878 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 5879 // CHECK5-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]]) 5880 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 5881 // CHECK5-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 5882 // CHECK5-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 5883 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 5884 // CHECK5-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]]) 5885 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 5886 // CHECK5-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] 5887 // CHECK5-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 5888 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 5889 // CHECK5-NEXT: ret i32 [[TMP8]] 5890 // 5891 // 5892 // CHECK5-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 5893 // CHECK5-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { 5894 // CHECK5-NEXT: entry: 5895 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 5896 // CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 5897 // CHECK5-NEXT: [[B:%.*]] = alloca i32, align 4 5898 // CHECK5-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 5899 // CHECK5-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 5900 // CHECK5-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 5901 // CHECK5-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 5902 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 5903 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 5904 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 5905 // CHECK5-NEXT: store i32 [[ADD]], i32* [[B]], align 4 5906 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 5907 // CHECK5-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 5908 // CHECK5-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() 5909 // CHECK5-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 5910 // CHECK5-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] 5911 // CHECK5-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 5912 // CHECK5-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 5913 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 5914 // CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP5]] to double 5915 // CHECK5-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 5916 // CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 5917 // CHECK5-NEXT: store double [[ADD2]], double* [[A]], align 8 5918 // CHECK5-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 5919 // CHECK5-NEXT: [[TMP6:%.*]] = load double, double* [[A3]], align 8 5920 // CHECK5-NEXT: [[INC:%.*]] = fadd double [[TMP6]], 1.000000e+00 5921 // CHECK5-NEXT: store double [[INC]], double* [[A3]], align 8 5922 // CHECK5-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 5923 // CHECK5-NEXT: [[TMP7:%.*]] = mul nsw i64 1, [[TMP2]] 5924 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP7]] 5925 // CHECK5-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 5926 // CHECK5-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 5927 // CHECK5-NEXT: [[TMP8:%.*]] = mul nsw i64 1, [[TMP2]] 5928 // CHECK5-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP8]] 5929 // CHECK5-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i64 1 5930 // CHECK5-NEXT: [[TMP9:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2 5931 // CHECK5-NEXT: [[CONV8:%.*]] = sext i16 [[TMP9]] to i32 5932 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[B]], align 4 5933 // CHECK5-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP10]] 5934 // CHECK5-NEXT: [[TMP11:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 5935 // CHECK5-NEXT: call void @llvm.stackrestore(i8* [[TMP11]]) 5936 // CHECK5-NEXT: ret i32 [[ADD9]] 5937 // 5938 // 5939 // CHECK5-LABEL: define {{[^@]+}}@_ZL7fstatici 5940 // CHECK5-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { 5941 // CHECK5-NEXT: entry: 5942 // CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 5943 // CHECK5-NEXT: [[A:%.*]] = alloca i32, align 4 5944 // CHECK5-NEXT: [[AA:%.*]] = alloca i16, align 2 5945 // CHECK5-NEXT: [[AAA:%.*]] = alloca i8, align 1 5946 // CHECK5-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 5947 // CHECK5-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 5948 // CHECK5-NEXT: store i32 0, i32* [[A]], align 4 5949 // CHECK5-NEXT: store i16 0, i16* [[AA]], align 2 5950 // CHECK5-NEXT: store i8 0, i8* [[AAA]], align 1 5951 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 5952 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 5953 // CHECK5-NEXT: store i32 [[ADD]], i32* [[A]], align 4 5954 // CHECK5-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 5955 // CHECK5-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 5956 // CHECK5-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 5957 // CHECK5-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 5958 // CHECK5-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 5959 // CHECK5-NEXT: [[TMP2:%.*]] = load i8, i8* [[AAA]], align 1 5960 // CHECK5-NEXT: [[CONV3:%.*]] = sext i8 [[TMP2]] to i32 5961 // CHECK5-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 5962 // CHECK5-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 5963 // CHECK5-NEXT: store i8 [[CONV5]], i8* [[AAA]], align 1 5964 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 5965 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 5966 // CHECK5-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP3]], 1 5967 // CHECK5-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 5968 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 5969 // CHECK5-NEXT: ret i32 [[TMP4]] 5970 // 5971 // 5972 // CHECK5-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 5973 // CHECK5-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { 5974 // CHECK5-NEXT: entry: 5975 // CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 5976 // CHECK5-NEXT: [[A:%.*]] = alloca i32, align 4 5977 // CHECK5-NEXT: [[AA:%.*]] = alloca i16, align 2 5978 // CHECK5-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 5979 // CHECK5-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 5980 // CHECK5-NEXT: store i32 0, i32* [[A]], align 4 5981 // CHECK5-NEXT: store i16 0, i16* [[AA]], align 2 5982 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 5983 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 5984 // CHECK5-NEXT: store i32 [[ADD]], i32* [[A]], align 4 5985 // CHECK5-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 5986 // CHECK5-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 5987 // CHECK5-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 5988 // CHECK5-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 5989 // CHECK5-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 5990 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 5991 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 5992 // CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP2]], 1 5993 // CHECK5-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 5994 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 5995 // CHECK5-NEXT: ret i32 [[TMP3]] 5996 // 5997 // 5998 // CHECK6-LABEL: define {{[^@]+}}@_Z3fooi 5999 // CHECK6-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { 6000 // CHECK6-NEXT: entry: 6001 // CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 6002 // CHECK6-NEXT: [[A:%.*]] = alloca i32, align 4 6003 // CHECK6-NEXT: [[AA:%.*]] = alloca i16, align 2 6004 // CHECK6-NEXT: [[B:%.*]] = alloca [10 x float], align 4 6005 // CHECK6-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 6006 // CHECK6-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 6007 // CHECK6-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 6008 // CHECK6-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 6009 // CHECK6-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 6010 // CHECK6-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 6011 // CHECK6-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 6012 // CHECK6-NEXT: [[NN:%.*]] = alloca i32, align 4 6013 // CHECK6-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 6014 // CHECK6-NEXT: store i32 0, i32* [[A]], align 4 6015 // CHECK6-NEXT: store i16 0, i16* [[AA]], align 2 6016 // CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 6017 // CHECK6-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 6018 // CHECK6-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() 6019 // CHECK6-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 6020 // CHECK6-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4 6021 // CHECK6-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 6022 // CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 6023 // CHECK6-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64 6024 // CHECK6-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]] 6025 // CHECK6-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8 6026 // CHECK6-NEXT: store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8 6027 // CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 6028 // CHECK6-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_]], align 4 6029 // CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 6030 // CHECK6-NEXT: store i32 [[TMP7]], i32* [[DOTCAPTURE_EXPR_2]], align 4 6031 // CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 6032 // CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 6033 // CHECK6-NEXT: store i32 [[ADD]], i32* [[A]], align 4 6034 // CHECK6-NEXT: [[TMP9:%.*]] = load i16, i16* [[AA]], align 2 6035 // CHECK6-NEXT: [[CONV:%.*]] = sext i16 [[TMP9]] to i32 6036 // CHECK6-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1 6037 // CHECK6-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 6038 // CHECK6-NEXT: store i16 [[CONV4]], i16* [[AA]], align 2 6039 // CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[A]], align 4 6040 // CHECK6-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP10]], 1 6041 // CHECK6-NEXT: store i32 [[ADD5]], i32* [[A]], align 4 6042 // CHECK6-NEXT: [[TMP11:%.*]] = load i16, i16* [[AA]], align 2 6043 // CHECK6-NEXT: [[CONV6:%.*]] = sext i16 [[TMP11]] to i32 6044 // CHECK6-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 6045 // CHECK6-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i16 6046 // CHECK6-NEXT: store i16 [[CONV8]], i16* [[AA]], align 2 6047 // CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[A]], align 4 6048 // CHECK6-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP12]], 1 6049 // CHECK6-NEXT: store i32 [[ADD9]], i32* [[A]], align 4 6050 // CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2 6051 // CHECK6-NEXT: [[TMP13:%.*]] = load float, float* [[ARRAYIDX]], align 4 6052 // CHECK6-NEXT: [[CONV10:%.*]] = fpext float [[TMP13]] to double 6053 // CHECK6-NEXT: [[ADD11:%.*]] = fadd double [[CONV10]], 1.000000e+00 6054 // CHECK6-NEXT: [[CONV12:%.*]] = fptrunc double [[ADD11]] to float 6055 // CHECK6-NEXT: store float [[CONV12]], float* [[ARRAYIDX]], align 4 6056 // CHECK6-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3 6057 // CHECK6-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX13]], align 4 6058 // CHECK6-NEXT: [[CONV14:%.*]] = fpext float [[TMP14]] to double 6059 // CHECK6-NEXT: [[ADD15:%.*]] = fadd double [[CONV14]], 1.000000e+00 6060 // CHECK6-NEXT: [[CONV16:%.*]] = fptrunc double [[ADD15]] to float 6061 // CHECK6-NEXT: store float [[CONV16]], float* [[ARRAYIDX13]], align 4 6062 // CHECK6-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1 6063 // CHECK6-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX17]], i64 0, i64 2 6064 // CHECK6-NEXT: [[TMP15:%.*]] = load double, double* [[ARRAYIDX18]], align 8 6065 // CHECK6-NEXT: [[ADD19:%.*]] = fadd double [[TMP15]], 1.000000e+00 6066 // CHECK6-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8 6067 // CHECK6-NEXT: [[TMP16:%.*]] = mul nsw i64 1, [[TMP4]] 6068 // CHECK6-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP16]] 6069 // CHECK6-NEXT: [[ARRAYIDX21:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX20]], i64 3 6070 // CHECK6-NEXT: [[TMP17:%.*]] = load double, double* [[ARRAYIDX21]], align 8 6071 // CHECK6-NEXT: [[ADD22:%.*]] = fadd double [[TMP17]], 1.000000e+00 6072 // CHECK6-NEXT: store double [[ADD22]], double* [[ARRAYIDX21]], align 8 6073 // CHECK6-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 6074 // CHECK6-NEXT: [[TMP18:%.*]] = load i64, i64* [[X]], align 8 6075 // CHECK6-NEXT: [[ADD23:%.*]] = add nsw i64 [[TMP18]], 1 6076 // CHECK6-NEXT: store i64 [[ADD23]], i64* [[X]], align 8 6077 // CHECK6-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 6078 // CHECK6-NEXT: [[TMP19:%.*]] = load i8, i8* [[Y]], align 8 6079 // CHECK6-NEXT: [[CONV24:%.*]] = sext i8 [[TMP19]] to i32 6080 // CHECK6-NEXT: [[ADD25:%.*]] = add nsw i32 [[CONV24]], 1 6081 // CHECK6-NEXT: [[CONV26:%.*]] = trunc i32 [[ADD25]] to i8 6082 // CHECK6-NEXT: store i8 [[CONV26]], i8* [[Y]], align 8 6083 // CHECK6-NEXT: store i32 0, i32* [[NN]], align 4 6084 // CHECK6-NEXT: [[TMP20:%.*]] = load i32, i32* [[A]], align 4 6085 // CHECK6-NEXT: [[TMP21:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 6086 // CHECK6-NEXT: call void @llvm.stackrestore(i8* [[TMP21]]) 6087 // CHECK6-NEXT: ret i32 [[TMP20]] 6088 // 6089 // 6090 // CHECK6-LABEL: define {{[^@]+}}@_Z6bazzzziPi 6091 // CHECK6-SAME: (i32 signext [[N:%.*]], i32* [[F:%.*]]) #[[ATTR0]] { 6092 // CHECK6-NEXT: entry: 6093 // CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 6094 // CHECK6-NEXT: [[F_ADDR:%.*]] = alloca i32*, align 8 6095 // CHECK6-NEXT: [[F1:%.*]] = alloca i32*, align 8 6096 // CHECK6-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 6097 // CHECK6-NEXT: store i32* [[F]], i32** [[F_ADDR]], align 8 6098 // CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 6099 // CHECK6-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 6100 // CHECK6-NEXT: ret void 6101 // 6102 // 6103 // CHECK6-LABEL: define {{[^@]+}}@_Z3bari 6104 // CHECK6-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { 6105 // CHECK6-NEXT: entry: 6106 // CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 6107 // CHECK6-NEXT: [[A:%.*]] = alloca i32, align 4 6108 // CHECK6-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 6109 // CHECK6-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 6110 // CHECK6-NEXT: store i32 0, i32* [[A]], align 4 6111 // CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 6112 // CHECK6-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]]) 6113 // CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 6114 // CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 6115 // CHECK6-NEXT: store i32 [[ADD]], i32* [[A]], align 4 6116 // CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 6117 // CHECK6-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]]) 6118 // CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 6119 // CHECK6-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 6120 // CHECK6-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 6121 // CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 6122 // CHECK6-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]]) 6123 // CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 6124 // CHECK6-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 6125 // CHECK6-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 6126 // CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 6127 // CHECK6-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]]) 6128 // CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 6129 // CHECK6-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] 6130 // CHECK6-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 6131 // CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 6132 // CHECK6-NEXT: ret i32 [[TMP8]] 6133 // 6134 // 6135 // CHECK6-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 6136 // CHECK6-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { 6137 // CHECK6-NEXT: entry: 6138 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 6139 // CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 6140 // CHECK6-NEXT: [[B:%.*]] = alloca i32, align 4 6141 // CHECK6-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 6142 // CHECK6-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 6143 // CHECK6-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 6144 // CHECK6-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 6145 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 6146 // CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 6147 // CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 6148 // CHECK6-NEXT: store i32 [[ADD]], i32* [[B]], align 4 6149 // CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 6150 // CHECK6-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 6151 // CHECK6-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() 6152 // CHECK6-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 6153 // CHECK6-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] 6154 // CHECK6-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 6155 // CHECK6-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 6156 // CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 6157 // CHECK6-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP5]] to double 6158 // CHECK6-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 6159 // CHECK6-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 6160 // CHECK6-NEXT: store double [[ADD2]], double* [[A]], align 8 6161 // CHECK6-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 6162 // CHECK6-NEXT: [[TMP6:%.*]] = load double, double* [[A3]], align 8 6163 // CHECK6-NEXT: [[INC:%.*]] = fadd double [[TMP6]], 1.000000e+00 6164 // CHECK6-NEXT: store double [[INC]], double* [[A3]], align 8 6165 // CHECK6-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 6166 // CHECK6-NEXT: [[TMP7:%.*]] = mul nsw i64 1, [[TMP2]] 6167 // CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP7]] 6168 // CHECK6-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 6169 // CHECK6-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 6170 // CHECK6-NEXT: [[TMP8:%.*]] = mul nsw i64 1, [[TMP2]] 6171 // CHECK6-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP8]] 6172 // CHECK6-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i64 1 6173 // CHECK6-NEXT: [[TMP9:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2 6174 // CHECK6-NEXT: [[CONV8:%.*]] = sext i16 [[TMP9]] to i32 6175 // CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[B]], align 4 6176 // CHECK6-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP10]] 6177 // CHECK6-NEXT: [[TMP11:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 6178 // CHECK6-NEXT: call void @llvm.stackrestore(i8* [[TMP11]]) 6179 // CHECK6-NEXT: ret i32 [[ADD9]] 6180 // 6181 // 6182 // CHECK6-LABEL: define {{[^@]+}}@_ZL7fstatici 6183 // CHECK6-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { 6184 // CHECK6-NEXT: entry: 6185 // CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 6186 // CHECK6-NEXT: [[A:%.*]] = alloca i32, align 4 6187 // CHECK6-NEXT: [[AA:%.*]] = alloca i16, align 2 6188 // CHECK6-NEXT: [[AAA:%.*]] = alloca i8, align 1 6189 // CHECK6-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 6190 // CHECK6-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 6191 // CHECK6-NEXT: store i32 0, i32* [[A]], align 4 6192 // CHECK6-NEXT: store i16 0, i16* [[AA]], align 2 6193 // CHECK6-NEXT: store i8 0, i8* [[AAA]], align 1 6194 // CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 6195 // CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 6196 // CHECK6-NEXT: store i32 [[ADD]], i32* [[A]], align 4 6197 // CHECK6-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 6198 // CHECK6-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 6199 // CHECK6-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 6200 // CHECK6-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 6201 // CHECK6-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 6202 // CHECK6-NEXT: [[TMP2:%.*]] = load i8, i8* [[AAA]], align 1 6203 // CHECK6-NEXT: [[CONV3:%.*]] = sext i8 [[TMP2]] to i32 6204 // CHECK6-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 6205 // CHECK6-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 6206 // CHECK6-NEXT: store i8 [[CONV5]], i8* [[AAA]], align 1 6207 // CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 6208 // CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 6209 // CHECK6-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP3]], 1 6210 // CHECK6-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 6211 // CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 6212 // CHECK6-NEXT: ret i32 [[TMP4]] 6213 // 6214 // 6215 // CHECK6-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 6216 // CHECK6-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { 6217 // CHECK6-NEXT: entry: 6218 // CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 6219 // CHECK6-NEXT: [[A:%.*]] = alloca i32, align 4 6220 // CHECK6-NEXT: [[AA:%.*]] = alloca i16, align 2 6221 // CHECK6-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 6222 // CHECK6-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 6223 // CHECK6-NEXT: store i32 0, i32* [[A]], align 4 6224 // CHECK6-NEXT: store i16 0, i16* [[AA]], align 2 6225 // CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 6226 // CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 6227 // CHECK6-NEXT: store i32 [[ADD]], i32* [[A]], align 4 6228 // CHECK6-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 6229 // CHECK6-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 6230 // CHECK6-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 6231 // CHECK6-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 6232 // CHECK6-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 6233 // CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 6234 // CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 6235 // CHECK6-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP2]], 1 6236 // CHECK6-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 6237 // CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 6238 // CHECK6-NEXT: ret i32 [[TMP3]] 6239 // 6240 // 6241 // CHECK7-LABEL: define {{[^@]+}}@_Z3fooi 6242 // CHECK7-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { 6243 // CHECK7-NEXT: entry: 6244 // CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 6245 // CHECK7-NEXT: [[A:%.*]] = alloca i32, align 4 6246 // CHECK7-NEXT: [[AA:%.*]] = alloca i16, align 2 6247 // CHECK7-NEXT: [[B:%.*]] = alloca [10 x float], align 4 6248 // CHECK7-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 6249 // CHECK7-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 6250 // CHECK7-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 6251 // CHECK7-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 6252 // CHECK7-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 6253 // CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 6254 // CHECK7-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 6255 // CHECK7-NEXT: [[NN:%.*]] = alloca i32, align 4 6256 // CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 6257 // CHECK7-NEXT: store i32 0, i32* [[A]], align 4 6258 // CHECK7-NEXT: store i16 0, i16* [[AA]], align 2 6259 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 6260 // CHECK7-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() 6261 // CHECK7-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 6262 // CHECK7-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4 6263 // CHECK7-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 6264 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 6265 // CHECK7-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]] 6266 // CHECK7-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8 6267 // CHECK7-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4 6268 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 6269 // CHECK7-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 6270 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 6271 // CHECK7-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_2]], align 4 6272 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 6273 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], 1 6274 // CHECK7-NEXT: store i32 [[ADD]], i32* [[A]], align 4 6275 // CHECK7-NEXT: [[TMP7:%.*]] = load i16, i16* [[AA]], align 2 6276 // CHECK7-NEXT: [[CONV:%.*]] = sext i16 [[TMP7]] to i32 6277 // CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1 6278 // CHECK7-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 6279 // CHECK7-NEXT: store i16 [[CONV4]], i16* [[AA]], align 2 6280 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 6281 // CHECK7-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP8]], 1 6282 // CHECK7-NEXT: store i32 [[ADD5]], i32* [[A]], align 4 6283 // CHECK7-NEXT: [[TMP9:%.*]] = load i16, i16* [[AA]], align 2 6284 // CHECK7-NEXT: [[CONV6:%.*]] = sext i16 [[TMP9]] to i32 6285 // CHECK7-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 6286 // CHECK7-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i16 6287 // CHECK7-NEXT: store i16 [[CONV8]], i16* [[AA]], align 2 6288 // CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[A]], align 4 6289 // CHECK7-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP10]], 1 6290 // CHECK7-NEXT: store i32 [[ADD9]], i32* [[A]], align 4 6291 // CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2 6292 // CHECK7-NEXT: [[TMP11:%.*]] = load float, float* [[ARRAYIDX]], align 4 6293 // CHECK7-NEXT: [[CONV10:%.*]] = fpext float [[TMP11]] to double 6294 // CHECK7-NEXT: [[ADD11:%.*]] = fadd double [[CONV10]], 1.000000e+00 6295 // CHECK7-NEXT: [[CONV12:%.*]] = fptrunc double [[ADD11]] to float 6296 // CHECK7-NEXT: store float [[CONV12]], float* [[ARRAYIDX]], align 4 6297 // CHECK7-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3 6298 // CHECK7-NEXT: [[TMP12:%.*]] = load float, float* [[ARRAYIDX13]], align 4 6299 // CHECK7-NEXT: [[CONV14:%.*]] = fpext float [[TMP12]] to double 6300 // CHECK7-NEXT: [[ADD15:%.*]] = fadd double [[CONV14]], 1.000000e+00 6301 // CHECK7-NEXT: [[CONV16:%.*]] = fptrunc double [[ADD15]] to float 6302 // CHECK7-NEXT: store float [[CONV16]], float* [[ARRAYIDX13]], align 4 6303 // CHECK7-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1 6304 // CHECK7-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX17]], i32 0, i32 2 6305 // CHECK7-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX18]], align 8 6306 // CHECK7-NEXT: [[ADD19:%.*]] = fadd double [[TMP13]], 1.000000e+00 6307 // CHECK7-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8 6308 // CHECK7-NEXT: [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]] 6309 // CHECK7-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP14]] 6310 // CHECK7-NEXT: [[ARRAYIDX21:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX20]], i32 3 6311 // CHECK7-NEXT: [[TMP15:%.*]] = load double, double* [[ARRAYIDX21]], align 8 6312 // CHECK7-NEXT: [[ADD22:%.*]] = fadd double [[TMP15]], 1.000000e+00 6313 // CHECK7-NEXT: store double [[ADD22]], double* [[ARRAYIDX21]], align 8 6314 // CHECK7-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 6315 // CHECK7-NEXT: [[TMP16:%.*]] = load i64, i64* [[X]], align 4 6316 // CHECK7-NEXT: [[ADD23:%.*]] = add nsw i64 [[TMP16]], 1 6317 // CHECK7-NEXT: store i64 [[ADD23]], i64* [[X]], align 4 6318 // CHECK7-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 6319 // CHECK7-NEXT: [[TMP17:%.*]] = load i8, i8* [[Y]], align 4 6320 // CHECK7-NEXT: [[CONV24:%.*]] = sext i8 [[TMP17]] to i32 6321 // CHECK7-NEXT: [[ADD25:%.*]] = add nsw i32 [[CONV24]], 1 6322 // CHECK7-NEXT: [[CONV26:%.*]] = trunc i32 [[ADD25]] to i8 6323 // CHECK7-NEXT: store i8 [[CONV26]], i8* [[Y]], align 4 6324 // CHECK7-NEXT: store i32 0, i32* [[NN]], align 4 6325 // CHECK7-NEXT: [[TMP18:%.*]] = load i32, i32* [[A]], align 4 6326 // CHECK7-NEXT: [[TMP19:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 6327 // CHECK7-NEXT: call void @llvm.stackrestore(i8* [[TMP19]]) 6328 // CHECK7-NEXT: ret i32 [[TMP18]] 6329 // 6330 // 6331 // CHECK7-LABEL: define {{[^@]+}}@_Z6bazzzziPi 6332 // CHECK7-SAME: (i32 [[N:%.*]], i32* [[F:%.*]]) #[[ATTR0]] { 6333 // CHECK7-NEXT: entry: 6334 // CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 6335 // CHECK7-NEXT: [[F_ADDR:%.*]] = alloca i32*, align 4 6336 // CHECK7-NEXT: [[F1:%.*]] = alloca i32*, align 4 6337 // CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 6338 // CHECK7-NEXT: store i32* [[F]], i32** [[F_ADDR]], align 4 6339 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 6340 // CHECK7-NEXT: ret void 6341 // 6342 // 6343 // CHECK7-LABEL: define {{[^@]+}}@_Z3bari 6344 // CHECK7-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { 6345 // CHECK7-NEXT: entry: 6346 // CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 6347 // CHECK7-NEXT: [[A:%.*]] = alloca i32, align 4 6348 // CHECK7-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 6349 // CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 6350 // CHECK7-NEXT: store i32 0, i32* [[A]], align 4 6351 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 6352 // CHECK7-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]]) 6353 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 6354 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 6355 // CHECK7-NEXT: store i32 [[ADD]], i32* [[A]], align 4 6356 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 6357 // CHECK7-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]]) 6358 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 6359 // CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 6360 // CHECK7-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 6361 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 6362 // CHECK7-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]]) 6363 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 6364 // CHECK7-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 6365 // CHECK7-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 6366 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 6367 // CHECK7-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]]) 6368 // CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 6369 // CHECK7-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] 6370 // CHECK7-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 6371 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 6372 // CHECK7-NEXT: ret i32 [[TMP8]] 6373 // 6374 // 6375 // CHECK7-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 6376 // CHECK7-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { 6377 // CHECK7-NEXT: entry: 6378 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 6379 // CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 6380 // CHECK7-NEXT: [[B:%.*]] = alloca i32, align 4 6381 // CHECK7-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 6382 // CHECK7-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 6383 // CHECK7-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 6384 // CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 6385 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 6386 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 6387 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 6388 // CHECK7-NEXT: store i32 [[ADD]], i32* [[B]], align 4 6389 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 6390 // CHECK7-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() 6391 // CHECK7-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 6392 // CHECK7-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] 6393 // CHECK7-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 6394 // CHECK7-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 6395 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[B]], align 4 6396 // CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP4]] to double 6397 // CHECK7-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 6398 // CHECK7-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 6399 // CHECK7-NEXT: store double [[ADD2]], double* [[A]], align 4 6400 // CHECK7-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 6401 // CHECK7-NEXT: [[TMP5:%.*]] = load double, double* [[A3]], align 4 6402 // CHECK7-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 6403 // CHECK7-NEXT: store double [[INC]], double* [[A3]], align 4 6404 // CHECK7-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 6405 // CHECK7-NEXT: [[TMP6:%.*]] = mul nsw i32 1, [[TMP1]] 6406 // CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP6]] 6407 // CHECK7-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 6408 // CHECK7-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 6409 // CHECK7-NEXT: [[TMP7:%.*]] = mul nsw i32 1, [[TMP1]] 6410 // CHECK7-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP7]] 6411 // CHECK7-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i32 1 6412 // CHECK7-NEXT: [[TMP8:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2 6413 // CHECK7-NEXT: [[CONV8:%.*]] = sext i16 [[TMP8]] to i32 6414 // CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[B]], align 4 6415 // CHECK7-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP9]] 6416 // CHECK7-NEXT: [[TMP10:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 6417 // CHECK7-NEXT: call void @llvm.stackrestore(i8* [[TMP10]]) 6418 // CHECK7-NEXT: ret i32 [[ADD9]] 6419 // 6420 // 6421 // CHECK7-LABEL: define {{[^@]+}}@_ZL7fstatici 6422 // CHECK7-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { 6423 // CHECK7-NEXT: entry: 6424 // CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 6425 // CHECK7-NEXT: [[A:%.*]] = alloca i32, align 4 6426 // CHECK7-NEXT: [[AA:%.*]] = alloca i16, align 2 6427 // CHECK7-NEXT: [[AAA:%.*]] = alloca i8, align 1 6428 // CHECK7-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 6429 // CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 6430 // CHECK7-NEXT: store i32 0, i32* [[A]], align 4 6431 // CHECK7-NEXT: store i16 0, i16* [[AA]], align 2 6432 // CHECK7-NEXT: store i8 0, i8* [[AAA]], align 1 6433 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 6434 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 6435 // CHECK7-NEXT: store i32 [[ADD]], i32* [[A]], align 4 6436 // CHECK7-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 6437 // CHECK7-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 6438 // CHECK7-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 6439 // CHECK7-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 6440 // CHECK7-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 6441 // CHECK7-NEXT: [[TMP2:%.*]] = load i8, i8* [[AAA]], align 1 6442 // CHECK7-NEXT: [[CONV3:%.*]] = sext i8 [[TMP2]] to i32 6443 // CHECK7-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 6444 // CHECK7-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 6445 // CHECK7-NEXT: store i8 [[CONV5]], i8* [[AAA]], align 1 6446 // CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 6447 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 6448 // CHECK7-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP3]], 1 6449 // CHECK7-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 6450 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 6451 // CHECK7-NEXT: ret i32 [[TMP4]] 6452 // 6453 // 6454 // CHECK7-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 6455 // CHECK7-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { 6456 // CHECK7-NEXT: entry: 6457 // CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 6458 // CHECK7-NEXT: [[A:%.*]] = alloca i32, align 4 6459 // CHECK7-NEXT: [[AA:%.*]] = alloca i16, align 2 6460 // CHECK7-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 6461 // CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 6462 // CHECK7-NEXT: store i32 0, i32* [[A]], align 4 6463 // CHECK7-NEXT: store i16 0, i16* [[AA]], align 2 6464 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 6465 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 6466 // CHECK7-NEXT: store i32 [[ADD]], i32* [[A]], align 4 6467 // CHECK7-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 6468 // CHECK7-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 6469 // CHECK7-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 6470 // CHECK7-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 6471 // CHECK7-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 6472 // CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 6473 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 6474 // CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP2]], 1 6475 // CHECK7-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 6476 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 6477 // CHECK7-NEXT: ret i32 [[TMP3]] 6478 // 6479 // 6480 // CHECK8-LABEL: define {{[^@]+}}@_Z3fooi 6481 // CHECK8-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { 6482 // CHECK8-NEXT: entry: 6483 // CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 6484 // CHECK8-NEXT: [[A:%.*]] = alloca i32, align 4 6485 // CHECK8-NEXT: [[AA:%.*]] = alloca i16, align 2 6486 // CHECK8-NEXT: [[B:%.*]] = alloca [10 x float], align 4 6487 // CHECK8-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 6488 // CHECK8-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 6489 // CHECK8-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 6490 // CHECK8-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 6491 // CHECK8-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 6492 // CHECK8-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 6493 // CHECK8-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 6494 // CHECK8-NEXT: [[NN:%.*]] = alloca i32, align 4 6495 // CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 6496 // CHECK8-NEXT: store i32 0, i32* [[A]], align 4 6497 // CHECK8-NEXT: store i16 0, i16* [[AA]], align 2 6498 // CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 6499 // CHECK8-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() 6500 // CHECK8-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 6501 // CHECK8-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4 6502 // CHECK8-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 6503 // CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 6504 // CHECK8-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]] 6505 // CHECK8-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8 6506 // CHECK8-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4 6507 // CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 6508 // CHECK8-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 6509 // CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 6510 // CHECK8-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_2]], align 4 6511 // CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 6512 // CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], 1 6513 // CHECK8-NEXT: store i32 [[ADD]], i32* [[A]], align 4 6514 // CHECK8-NEXT: [[TMP7:%.*]] = load i16, i16* [[AA]], align 2 6515 // CHECK8-NEXT: [[CONV:%.*]] = sext i16 [[TMP7]] to i32 6516 // CHECK8-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1 6517 // CHECK8-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 6518 // CHECK8-NEXT: store i16 [[CONV4]], i16* [[AA]], align 2 6519 // CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 6520 // CHECK8-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP8]], 1 6521 // CHECK8-NEXT: store i32 [[ADD5]], i32* [[A]], align 4 6522 // CHECK8-NEXT: [[TMP9:%.*]] = load i16, i16* [[AA]], align 2 6523 // CHECK8-NEXT: [[CONV6:%.*]] = sext i16 [[TMP9]] to i32 6524 // CHECK8-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 6525 // CHECK8-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i16 6526 // CHECK8-NEXT: store i16 [[CONV8]], i16* [[AA]], align 2 6527 // CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[A]], align 4 6528 // CHECK8-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP10]], 1 6529 // CHECK8-NEXT: store i32 [[ADD9]], i32* [[A]], align 4 6530 // CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2 6531 // CHECK8-NEXT: [[TMP11:%.*]] = load float, float* [[ARRAYIDX]], align 4 6532 // CHECK8-NEXT: [[CONV10:%.*]] = fpext float [[TMP11]] to double 6533 // CHECK8-NEXT: [[ADD11:%.*]] = fadd double [[CONV10]], 1.000000e+00 6534 // CHECK8-NEXT: [[CONV12:%.*]] = fptrunc double [[ADD11]] to float 6535 // CHECK8-NEXT: store float [[CONV12]], float* [[ARRAYIDX]], align 4 6536 // CHECK8-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3 6537 // CHECK8-NEXT: [[TMP12:%.*]] = load float, float* [[ARRAYIDX13]], align 4 6538 // CHECK8-NEXT: [[CONV14:%.*]] = fpext float [[TMP12]] to double 6539 // CHECK8-NEXT: [[ADD15:%.*]] = fadd double [[CONV14]], 1.000000e+00 6540 // CHECK8-NEXT: [[CONV16:%.*]] = fptrunc double [[ADD15]] to float 6541 // CHECK8-NEXT: store float [[CONV16]], float* [[ARRAYIDX13]], align 4 6542 // CHECK8-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1 6543 // CHECK8-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX17]], i32 0, i32 2 6544 // CHECK8-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX18]], align 8 6545 // CHECK8-NEXT: [[ADD19:%.*]] = fadd double [[TMP13]], 1.000000e+00 6546 // CHECK8-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8 6547 // CHECK8-NEXT: [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]] 6548 // CHECK8-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP14]] 6549 // CHECK8-NEXT: [[ARRAYIDX21:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX20]], i32 3 6550 // CHECK8-NEXT: [[TMP15:%.*]] = load double, double* [[ARRAYIDX21]], align 8 6551 // CHECK8-NEXT: [[ADD22:%.*]] = fadd double [[TMP15]], 1.000000e+00 6552 // CHECK8-NEXT: store double [[ADD22]], double* [[ARRAYIDX21]], align 8 6553 // CHECK8-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 6554 // CHECK8-NEXT: [[TMP16:%.*]] = load i64, i64* [[X]], align 4 6555 // CHECK8-NEXT: [[ADD23:%.*]] = add nsw i64 [[TMP16]], 1 6556 // CHECK8-NEXT: store i64 [[ADD23]], i64* [[X]], align 4 6557 // CHECK8-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 6558 // CHECK8-NEXT: [[TMP17:%.*]] = load i8, i8* [[Y]], align 4 6559 // CHECK8-NEXT: [[CONV24:%.*]] = sext i8 [[TMP17]] to i32 6560 // CHECK8-NEXT: [[ADD25:%.*]] = add nsw i32 [[CONV24]], 1 6561 // CHECK8-NEXT: [[CONV26:%.*]] = trunc i32 [[ADD25]] to i8 6562 // CHECK8-NEXT: store i8 [[CONV26]], i8* [[Y]], align 4 6563 // CHECK8-NEXT: store i32 0, i32* [[NN]], align 4 6564 // CHECK8-NEXT: [[TMP18:%.*]] = load i32, i32* [[A]], align 4 6565 // CHECK8-NEXT: [[TMP19:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 6566 // CHECK8-NEXT: call void @llvm.stackrestore(i8* [[TMP19]]) 6567 // CHECK8-NEXT: ret i32 [[TMP18]] 6568 // 6569 // 6570 // CHECK8-LABEL: define {{[^@]+}}@_Z6bazzzziPi 6571 // CHECK8-SAME: (i32 [[N:%.*]], i32* [[F:%.*]]) #[[ATTR0]] { 6572 // CHECK8-NEXT: entry: 6573 // CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 6574 // CHECK8-NEXT: [[F_ADDR:%.*]] = alloca i32*, align 4 6575 // CHECK8-NEXT: [[F1:%.*]] = alloca i32*, align 4 6576 // CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 6577 // CHECK8-NEXT: store i32* [[F]], i32** [[F_ADDR]], align 4 6578 // CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 6579 // CHECK8-NEXT: ret void 6580 // 6581 // 6582 // CHECK8-LABEL: define {{[^@]+}}@_Z3bari 6583 // CHECK8-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { 6584 // CHECK8-NEXT: entry: 6585 // CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 6586 // CHECK8-NEXT: [[A:%.*]] = alloca i32, align 4 6587 // CHECK8-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 6588 // CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 6589 // CHECK8-NEXT: store i32 0, i32* [[A]], align 4 6590 // CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 6591 // CHECK8-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]]) 6592 // CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 6593 // CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 6594 // CHECK8-NEXT: store i32 [[ADD]], i32* [[A]], align 4 6595 // CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 6596 // CHECK8-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]]) 6597 // CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 6598 // CHECK8-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 6599 // CHECK8-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 6600 // CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 6601 // CHECK8-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]]) 6602 // CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 6603 // CHECK8-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 6604 // CHECK8-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 6605 // CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 6606 // CHECK8-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]]) 6607 // CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 6608 // CHECK8-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] 6609 // CHECK8-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 6610 // CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 6611 // CHECK8-NEXT: ret i32 [[TMP8]] 6612 // 6613 // 6614 // CHECK8-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 6615 // CHECK8-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { 6616 // CHECK8-NEXT: entry: 6617 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 6618 // CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 6619 // CHECK8-NEXT: [[B:%.*]] = alloca i32, align 4 6620 // CHECK8-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 6621 // CHECK8-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 6622 // CHECK8-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 6623 // CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 6624 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 6625 // CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 6626 // CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 6627 // CHECK8-NEXT: store i32 [[ADD]], i32* [[B]], align 4 6628 // CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 6629 // CHECK8-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() 6630 // CHECK8-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 6631 // CHECK8-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] 6632 // CHECK8-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 6633 // CHECK8-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 6634 // CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[B]], align 4 6635 // CHECK8-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP4]] to double 6636 // CHECK8-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 6637 // CHECK8-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 6638 // CHECK8-NEXT: store double [[ADD2]], double* [[A]], align 4 6639 // CHECK8-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 6640 // CHECK8-NEXT: [[TMP5:%.*]] = load double, double* [[A3]], align 4 6641 // CHECK8-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 6642 // CHECK8-NEXT: store double [[INC]], double* [[A3]], align 4 6643 // CHECK8-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 6644 // CHECK8-NEXT: [[TMP6:%.*]] = mul nsw i32 1, [[TMP1]] 6645 // CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP6]] 6646 // CHECK8-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 6647 // CHECK8-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 6648 // CHECK8-NEXT: [[TMP7:%.*]] = mul nsw i32 1, [[TMP1]] 6649 // CHECK8-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP7]] 6650 // CHECK8-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i32 1 6651 // CHECK8-NEXT: [[TMP8:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2 6652 // CHECK8-NEXT: [[CONV8:%.*]] = sext i16 [[TMP8]] to i32 6653 // CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[B]], align 4 6654 // CHECK8-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP9]] 6655 // CHECK8-NEXT: [[TMP10:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 6656 // CHECK8-NEXT: call void @llvm.stackrestore(i8* [[TMP10]]) 6657 // CHECK8-NEXT: ret i32 [[ADD9]] 6658 // 6659 // 6660 // CHECK8-LABEL: define {{[^@]+}}@_ZL7fstatici 6661 // CHECK8-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { 6662 // CHECK8-NEXT: entry: 6663 // CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 6664 // CHECK8-NEXT: [[A:%.*]] = alloca i32, align 4 6665 // CHECK8-NEXT: [[AA:%.*]] = alloca i16, align 2 6666 // CHECK8-NEXT: [[AAA:%.*]] = alloca i8, align 1 6667 // CHECK8-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 6668 // CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 6669 // CHECK8-NEXT: store i32 0, i32* [[A]], align 4 6670 // CHECK8-NEXT: store i16 0, i16* [[AA]], align 2 6671 // CHECK8-NEXT: store i8 0, i8* [[AAA]], align 1 6672 // CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 6673 // CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 6674 // CHECK8-NEXT: store i32 [[ADD]], i32* [[A]], align 4 6675 // CHECK8-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 6676 // CHECK8-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 6677 // CHECK8-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 6678 // CHECK8-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 6679 // CHECK8-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 6680 // CHECK8-NEXT: [[TMP2:%.*]] = load i8, i8* [[AAA]], align 1 6681 // CHECK8-NEXT: [[CONV3:%.*]] = sext i8 [[TMP2]] to i32 6682 // CHECK8-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 6683 // CHECK8-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 6684 // CHECK8-NEXT: store i8 [[CONV5]], i8* [[AAA]], align 1 6685 // CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 6686 // CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 6687 // CHECK8-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP3]], 1 6688 // CHECK8-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 6689 // CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 6690 // CHECK8-NEXT: ret i32 [[TMP4]] 6691 // 6692 // 6693 // CHECK8-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 6694 // CHECK8-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { 6695 // CHECK8-NEXT: entry: 6696 // CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 6697 // CHECK8-NEXT: [[A:%.*]] = alloca i32, align 4 6698 // CHECK8-NEXT: [[AA:%.*]] = alloca i16, align 2 6699 // CHECK8-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 6700 // CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 6701 // CHECK8-NEXT: store i32 0, i32* [[A]], align 4 6702 // CHECK8-NEXT: store i16 0, i16* [[AA]], align 2 6703 // CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 6704 // CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 6705 // CHECK8-NEXT: store i32 [[ADD]], i32* [[A]], align 4 6706 // CHECK8-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 6707 // CHECK8-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 6708 // CHECK8-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 6709 // CHECK8-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 6710 // CHECK8-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 6711 // CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 6712 // CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 6713 // CHECK8-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP2]], 1 6714 // CHECK8-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 6715 // CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 6716 // CHECK8-NEXT: ret i32 [[TMP3]] 6717 // 6718 // 6719 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101 6720 // CHECK9-SAME: (i64 [[AA:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { 6721 // CHECK9-NEXT: entry: 6722 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 6723 // CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 6724 // CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8 6725 // CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 6726 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) 6727 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 6728 // CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 6729 // CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8 6730 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 6731 // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* 6732 // CHECK9-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32* 6733 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 8 6734 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 8 6735 // CHECK9-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) 6736 // CHECK9-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 8 6737 // CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 6738 // CHECK9-NEXT: store i16 [[TMP3]], i16* [[CONV5]], align 2 6739 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 6740 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]]) 6741 // CHECK9-NEXT: ret void 6742 // 6743 // 6744 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. 6745 // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { 6746 // CHECK9-NEXT: entry: 6747 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 6748 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 6749 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 6750 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 6751 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 6752 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 6753 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 6754 // CHECK9-NEXT: ret void 6755 // 6756 // 6757 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 6758 // CHECK9-SAME: (i64 [[AA:%.*]]) #[[ATTR0]] { 6759 // CHECK9-NEXT: entry: 6760 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 6761 // CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 6762 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 6763 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 6764 // CHECK9-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8 6765 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 6766 // CHECK9-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 6767 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 6768 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]]) 6769 // CHECK9-NEXT: ret void 6770 // 6771 // 6772 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 6773 // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { 6774 // CHECK9-NEXT: entry: 6775 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 6776 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 6777 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 6778 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 6779 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 6780 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 6781 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 6782 // CHECK9-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8 6783 // CHECK9-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 6784 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 6785 // CHECK9-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 6786 // CHECK9-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 8 6787 // CHECK9-NEXT: ret void 6788 // 6789 // 6790 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118 6791 // CHECK9-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { 6792 // CHECK9-NEXT: entry: 6793 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 6794 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 6795 // CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 6796 // CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 6797 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 6798 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 6799 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 6800 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 6801 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 6802 // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* 6803 // CHECK9-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 6804 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 6805 // CHECK9-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 6806 // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 6807 // CHECK9-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 6808 // CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 6809 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) 6810 // CHECK9-NEXT: ret void 6811 // 6812 // 6813 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..2 6814 // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { 6815 // CHECK9-NEXT: entry: 6816 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 6817 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 6818 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 6819 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 6820 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 6821 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 6822 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 6823 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 6824 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 6825 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 6826 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 6827 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 6828 // CHECK9-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 6829 // CHECK9-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 8 6830 // CHECK9-NEXT: [[CONV2:%.*]] = sext i16 [[TMP1]] to i32 6831 // CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 6832 // CHECK9-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 6833 // CHECK9-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 8 6834 // CHECK9-NEXT: ret void 6835 // 6836 // 6837 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142 6838 // CHECK9-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] { 6839 // CHECK9-NEXT: entry: 6840 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 6841 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 6842 // CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 6843 // CHECK9-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 6844 // CHECK9-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 6845 // CHECK9-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 6846 // CHECK9-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 6847 // CHECK9-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 6848 // CHECK9-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 6849 // CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 6850 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 6851 // CHECK9-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 6852 // CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 6853 // CHECK9-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 6854 // CHECK9-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 6855 // CHECK9-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 6856 // CHECK9-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 6857 // CHECK9-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 6858 // CHECK9-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 6859 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 6860 // CHECK9-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 6861 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 6862 // CHECK9-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 6863 // CHECK9-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 6864 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 6865 // CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 6866 // CHECK9-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 6867 // CHECK9-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 6868 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 6869 // CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* 6870 // CHECK9-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4 6871 // CHECK9-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 6872 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) 6873 // CHECK9-NEXT: ret void 6874 // 6875 // 6876 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..3 6877 // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] { 6878 // CHECK9-NEXT: entry: 6879 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 6880 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 6881 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 6882 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 6883 // CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 6884 // CHECK9-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 6885 // CHECK9-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 6886 // CHECK9-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 6887 // CHECK9-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 6888 // CHECK9-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 6889 // CHECK9-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 6890 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 6891 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 6892 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 6893 // CHECK9-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 6894 // CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 6895 // CHECK9-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 6896 // CHECK9-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 6897 // CHECK9-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 6898 // CHECK9-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 6899 // CHECK9-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 6900 // CHECK9-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 6901 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 6902 // CHECK9-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 6903 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 6904 // CHECK9-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 6905 // CHECK9-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 6906 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 6907 // CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 6908 // CHECK9-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 6909 // CHECK9-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 6910 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 6911 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 6912 // CHECK9-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 6913 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 6914 // CHECK9-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 6915 // CHECK9-NEXT: [[CONV5:%.*]] = fpext float [[TMP9]] to double 6916 // CHECK9-NEXT: [[ADD6:%.*]] = fadd double [[CONV5]], 1.000000e+00 6917 // CHECK9-NEXT: [[CONV7:%.*]] = fptrunc double [[ADD6]] to float 6918 // CHECK9-NEXT: store float [[CONV7]], float* [[ARRAYIDX]], align 4 6919 // CHECK9-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 6920 // CHECK9-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX8]], align 4 6921 // CHECK9-NEXT: [[CONV9:%.*]] = fpext float [[TMP10]] to double 6922 // CHECK9-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 6923 // CHECK9-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float 6924 // CHECK9-NEXT: store float [[CONV11]], float* [[ARRAYIDX8]], align 4 6925 // CHECK9-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1 6926 // CHECK9-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX12]], i64 0, i64 2 6927 // CHECK9-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX13]], align 8 6928 // CHECK9-NEXT: [[ADD14:%.*]] = fadd double [[TMP11]], 1.000000e+00 6929 // CHECK9-NEXT: store double [[ADD14]], double* [[ARRAYIDX13]], align 8 6930 // CHECK9-NEXT: [[TMP12:%.*]] = mul nsw i64 1, [[TMP5]] 6931 // CHECK9-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP12]] 6932 // CHECK9-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX15]], i64 3 6933 // CHECK9-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX16]], align 8 6934 // CHECK9-NEXT: [[ADD17:%.*]] = fadd double [[TMP13]], 1.000000e+00 6935 // CHECK9-NEXT: store double [[ADD17]], double* [[ARRAYIDX16]], align 8 6936 // CHECK9-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 6937 // CHECK9-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 8 6938 // CHECK9-NEXT: [[ADD18:%.*]] = add nsw i64 [[TMP14]], 1 6939 // CHECK9-NEXT: store i64 [[ADD18]], i64* [[X]], align 8 6940 // CHECK9-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 6941 // CHECK9-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 8 6942 // CHECK9-NEXT: [[CONV19:%.*]] = sext i8 [[TMP15]] to i32 6943 // CHECK9-NEXT: [[ADD20:%.*]] = add nsw i32 [[CONV19]], 1 6944 // CHECK9-NEXT: [[CONV21:%.*]] = trunc i32 [[ADD20]] to i8 6945 // CHECK9-NEXT: store i8 [[CONV21]], i8* [[Y]], align 8 6946 // CHECK9-NEXT: ret void 6947 // 6948 // 6949 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154 6950 // CHECK9-SAME: (i64 [[NN:%.*]]) #[[ATTR0]] { 6951 // CHECK9-NEXT: entry: 6952 // CHECK9-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 6953 // CHECK9-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 6954 // CHECK9-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 6955 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* 6956 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 6957 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32* 6958 // CHECK9-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 6959 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8 6960 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP1]]) 6961 // CHECK9-NEXT: ret void 6962 // 6963 // 6964 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..4 6965 // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[NN:%.*]]) #[[ATTR0]] { 6966 // CHECK9-NEXT: entry: 6967 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 6968 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 6969 // CHECK9-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 6970 // CHECK9-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 6971 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 6972 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 6973 // CHECK9-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 6974 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* 6975 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 6976 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32* 6977 // CHECK9-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 6978 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8 6979 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP1]]) 6980 // CHECK9-NEXT: ret void 6981 // 6982 // 6983 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..5 6984 // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[NN:%.*]]) #[[ATTR0]] { 6985 // CHECK9-NEXT: entry: 6986 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 6987 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 6988 // CHECK9-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 6989 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 6990 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 6991 // CHECK9-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 6992 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* 6993 // CHECK9-NEXT: ret void 6994 // 6995 // 6996 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157 6997 // CHECK9-SAME: (i64 [[NN:%.*]]) #[[ATTR0]] { 6998 // CHECK9-NEXT: entry: 6999 // CHECK9-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 7000 // CHECK9-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 7001 // CHECK9-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 7002 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* 7003 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 7004 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32* 7005 // CHECK9-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 7006 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8 7007 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP1]]) 7008 // CHECK9-NEXT: ret void 7009 // 7010 // 7011 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..6 7012 // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[NN:%.*]]) #[[ATTR0]] { 7013 // CHECK9-NEXT: entry: 7014 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 7015 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 7016 // CHECK9-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 7017 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 7018 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 7019 // CHECK9-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 7020 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* 7021 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32* [[CONV]]) 7022 // CHECK9-NEXT: ret void 7023 // 7024 // 7025 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..7 7026 // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[NN:%.*]]) #[[ATTR0]] { 7027 // CHECK9-NEXT: entry: 7028 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 7029 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 7030 // CHECK9-NEXT: [[NN_ADDR:%.*]] = alloca i32*, align 8 7031 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 7032 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 7033 // CHECK9-NEXT: store i32* [[NN]], i32** [[NN_ADDR]], align 8 7034 // CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[NN_ADDR]], align 8 7035 // CHECK9-NEXT: ret void 7036 // 7037 // 7038 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182 7039 // CHECK9-SAME: (i64 [[VLA:%.*]]) #[[ATTR0]] { 7040 // CHECK9-NEXT: entry: 7041 // CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 7042 // CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 7043 // CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 7044 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..8 to void (i32*, i32*, ...)*), i64 [[TMP0]]) 7045 // CHECK9-NEXT: ret void 7046 // 7047 // 7048 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..8 7049 // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[VLA:%.*]]) #[[ATTR0]] { 7050 // CHECK9-NEXT: entry: 7051 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 7052 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 7053 // CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 7054 // CHECK9-NEXT: [[F:%.*]] = alloca i32*, align 8 7055 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 7056 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 7057 // CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 7058 // CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 7059 // CHECK9-NEXT: ret void 7060 // 7061 // 7062 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209 7063 // CHECK9-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 7064 // CHECK9-NEXT: entry: 7065 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 7066 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 7067 // CHECK9-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 7068 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 7069 // CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 7070 // CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 7071 // CHECK9-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 7072 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 7073 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 7074 // CHECK9-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 7075 // CHECK9-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 7076 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 7077 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 7078 // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 7079 // CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 7080 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 7081 // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* 7082 // CHECK9-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 7083 // CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 7084 // CHECK9-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 7085 // CHECK9-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 7086 // CHECK9-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 7087 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 7088 // CHECK9-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8 7089 // CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* 7090 // CHECK9-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 7091 // CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 7092 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) 7093 // CHECK9-NEXT: ret void 7094 // 7095 // 7096 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..9 7097 // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 7098 // CHECK9-NEXT: entry: 7099 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 7100 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 7101 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 7102 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 7103 // CHECK9-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 7104 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 7105 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 7106 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 7107 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 7108 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 7109 // CHECK9-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 7110 // CHECK9-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 7111 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 7112 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 7113 // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 7114 // CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 7115 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 7116 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 7117 // CHECK9-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 7118 // CHECK9-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 7119 // CHECK9-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32 7120 // CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 7121 // CHECK9-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 7122 // CHECK9-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 8 7123 // CHECK9-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 8 7124 // CHECK9-NEXT: [[CONV6:%.*]] = sext i8 [[TMP3]] to i32 7125 // CHECK9-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 7126 // CHECK9-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i8 7127 // CHECK9-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 8 7128 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 7129 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 7130 // CHECK9-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP4]], 1 7131 // CHECK9-NEXT: store i32 [[ADD9]], i32* [[ARRAYIDX]], align 4 7132 // CHECK9-NEXT: ret void 7133 // 7134 // 7135 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227 7136 // CHECK9-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { 7137 // CHECK9-NEXT: entry: 7138 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 7139 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 7140 // CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 7141 // CHECK9-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 7142 // CHECK9-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 7143 // CHECK9-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 7144 // CHECK9-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 7145 // CHECK9-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 7146 // CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 7147 // CHECK9-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 7148 // CHECK9-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 7149 // CHECK9-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 7150 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 7151 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 7152 // CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 7153 // CHECK9-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 7154 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 7155 // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* 7156 // CHECK9-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 7157 // CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 7158 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) 7159 // CHECK9-NEXT: ret void 7160 // 7161 // 7162 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..10 7163 // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { 7164 // CHECK9-NEXT: entry: 7165 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 7166 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 7167 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 7168 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 7169 // CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 7170 // CHECK9-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 7171 // CHECK9-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 7172 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 7173 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 7174 // CHECK9-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 7175 // CHECK9-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 7176 // CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 7177 // CHECK9-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 7178 // CHECK9-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 7179 // CHECK9-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 7180 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 7181 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 7182 // CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 7183 // CHECK9-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 7184 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 7185 // CHECK9-NEXT: [[CONV3:%.*]] = sitofp i32 [[TMP4]] to double 7186 // CHECK9-NEXT: [[ADD:%.*]] = fadd double [[CONV3]], 1.500000e+00 7187 // CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 7188 // CHECK9-NEXT: store double [[ADD]], double* [[A]], align 8 7189 // CHECK9-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 7190 // CHECK9-NEXT: [[TMP5:%.*]] = load double, double* [[A4]], align 8 7191 // CHECK9-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 7192 // CHECK9-NEXT: store double [[INC]], double* [[A4]], align 8 7193 // CHECK9-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 7194 // CHECK9-NEXT: [[TMP6:%.*]] = mul nsw i64 1, [[TMP2]] 7195 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP6]] 7196 // CHECK9-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 7197 // CHECK9-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2 7198 // CHECK9-NEXT: ret void 7199 // 7200 // 7201 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192 7202 // CHECK9-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 7203 // CHECK9-NEXT: entry: 7204 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 7205 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 7206 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 7207 // CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 7208 // CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 7209 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 7210 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 7211 // CHECK9-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 7212 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 7213 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 7214 // CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 7215 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 7216 // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* 7217 // CHECK9-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 7218 // CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 7219 // CHECK9-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 7220 // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 7221 // CHECK9-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 7222 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 7223 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) 7224 // CHECK9-NEXT: ret void 7225 // 7226 // 7227 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..11 7228 // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 7229 // CHECK9-NEXT: entry: 7230 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 7231 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 7232 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 7233 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 7234 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 7235 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 7236 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 7237 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 7238 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 7239 // CHECK9-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 7240 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 7241 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 7242 // CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 7243 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 7244 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 7245 // CHECK9-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 7246 // CHECK9-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 7247 // CHECK9-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 7248 // CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 7249 // CHECK9-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 7250 // CHECK9-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 8 7251 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 7252 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 7253 // CHECK9-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP3]], 1 7254 // CHECK9-NEXT: store i32 [[ADD5]], i32* [[ARRAYIDX]], align 4 7255 // CHECK9-NEXT: ret void 7256 // 7257 // 7258 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101 7259 // CHECK10-SAME: (i64 [[AA:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { 7260 // CHECK10-NEXT: entry: 7261 // CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 7262 // CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 7263 // CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8 7264 // CHECK10-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 7265 // CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) 7266 // CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 7267 // CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 7268 // CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8 7269 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 7270 // CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* 7271 // CHECK10-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32* 7272 // CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 8 7273 // CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 8 7274 // CHECK10-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) 7275 // CHECK10-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 8 7276 // CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 7277 // CHECK10-NEXT: store i16 [[TMP3]], i16* [[CONV5]], align 2 7278 // CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 7279 // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]]) 7280 // CHECK10-NEXT: ret void 7281 // 7282 // 7283 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. 7284 // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { 7285 // CHECK10-NEXT: entry: 7286 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 7287 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 7288 // CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 7289 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 7290 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 7291 // CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 7292 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 7293 // CHECK10-NEXT: ret void 7294 // 7295 // 7296 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 7297 // CHECK10-SAME: (i64 [[AA:%.*]]) #[[ATTR0]] { 7298 // CHECK10-NEXT: entry: 7299 // CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 7300 // CHECK10-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 7301 // CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 7302 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 7303 // CHECK10-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8 7304 // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 7305 // CHECK10-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 7306 // CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 7307 // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]]) 7308 // CHECK10-NEXT: ret void 7309 // 7310 // 7311 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 7312 // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { 7313 // CHECK10-NEXT: entry: 7314 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 7315 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 7316 // CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 7317 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 7318 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 7319 // CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 7320 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 7321 // CHECK10-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8 7322 // CHECK10-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 7323 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 7324 // CHECK10-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 7325 // CHECK10-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 8 7326 // CHECK10-NEXT: ret void 7327 // 7328 // 7329 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118 7330 // CHECK10-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { 7331 // CHECK10-NEXT: entry: 7332 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 7333 // CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 7334 // CHECK10-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 7335 // CHECK10-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 7336 // CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 7337 // CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 7338 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 7339 // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 7340 // CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 7341 // CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* 7342 // CHECK10-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 7343 // CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 7344 // CHECK10-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 7345 // CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 7346 // CHECK10-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 7347 // CHECK10-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 7348 // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) 7349 // CHECK10-NEXT: ret void 7350 // 7351 // 7352 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..2 7353 // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { 7354 // CHECK10-NEXT: entry: 7355 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 7356 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 7357 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 7358 // CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 7359 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 7360 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 7361 // CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 7362 // CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 7363 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 7364 // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 7365 // CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 7366 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 7367 // CHECK10-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 7368 // CHECK10-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 8 7369 // CHECK10-NEXT: [[CONV2:%.*]] = sext i16 [[TMP1]] to i32 7370 // CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 7371 // CHECK10-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 7372 // CHECK10-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 8 7373 // CHECK10-NEXT: ret void 7374 // 7375 // 7376 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142 7377 // CHECK10-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] { 7378 // CHECK10-NEXT: entry: 7379 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 7380 // CHECK10-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 7381 // CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 7382 // CHECK10-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 7383 // CHECK10-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 7384 // CHECK10-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 7385 // CHECK10-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 7386 // CHECK10-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 7387 // CHECK10-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 7388 // CHECK10-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 7389 // CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 7390 // CHECK10-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 7391 // CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 7392 // CHECK10-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 7393 // CHECK10-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 7394 // CHECK10-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 7395 // CHECK10-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 7396 // CHECK10-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 7397 // CHECK10-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 7398 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 7399 // CHECK10-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 7400 // CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 7401 // CHECK10-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 7402 // CHECK10-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 7403 // CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 7404 // CHECK10-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 7405 // CHECK10-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 7406 // CHECK10-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 7407 // CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 7408 // CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* 7409 // CHECK10-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4 7410 // CHECK10-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 7411 // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) 7412 // CHECK10-NEXT: ret void 7413 // 7414 // 7415 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..3 7416 // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] { 7417 // CHECK10-NEXT: entry: 7418 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 7419 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 7420 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 7421 // CHECK10-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 7422 // CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 7423 // CHECK10-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 7424 // CHECK10-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 7425 // CHECK10-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 7426 // CHECK10-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 7427 // CHECK10-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 7428 // CHECK10-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 7429 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 7430 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 7431 // CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 7432 // CHECK10-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 7433 // CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 7434 // CHECK10-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 7435 // CHECK10-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 7436 // CHECK10-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 7437 // CHECK10-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 7438 // CHECK10-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 7439 // CHECK10-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 7440 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 7441 // CHECK10-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 7442 // CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 7443 // CHECK10-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 7444 // CHECK10-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 7445 // CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 7446 // CHECK10-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 7447 // CHECK10-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 7448 // CHECK10-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 7449 // CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 7450 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 7451 // CHECK10-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 7452 // CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 7453 // CHECK10-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 7454 // CHECK10-NEXT: [[CONV5:%.*]] = fpext float [[TMP9]] to double 7455 // CHECK10-NEXT: [[ADD6:%.*]] = fadd double [[CONV5]], 1.000000e+00 7456 // CHECK10-NEXT: [[CONV7:%.*]] = fptrunc double [[ADD6]] to float 7457 // CHECK10-NEXT: store float [[CONV7]], float* [[ARRAYIDX]], align 4 7458 // CHECK10-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 7459 // CHECK10-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX8]], align 4 7460 // CHECK10-NEXT: [[CONV9:%.*]] = fpext float [[TMP10]] to double 7461 // CHECK10-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 7462 // CHECK10-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float 7463 // CHECK10-NEXT: store float [[CONV11]], float* [[ARRAYIDX8]], align 4 7464 // CHECK10-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1 7465 // CHECK10-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX12]], i64 0, i64 2 7466 // CHECK10-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX13]], align 8 7467 // CHECK10-NEXT: [[ADD14:%.*]] = fadd double [[TMP11]], 1.000000e+00 7468 // CHECK10-NEXT: store double [[ADD14]], double* [[ARRAYIDX13]], align 8 7469 // CHECK10-NEXT: [[TMP12:%.*]] = mul nsw i64 1, [[TMP5]] 7470 // CHECK10-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP12]] 7471 // CHECK10-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX15]], i64 3 7472 // CHECK10-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX16]], align 8 7473 // CHECK10-NEXT: [[ADD17:%.*]] = fadd double [[TMP13]], 1.000000e+00 7474 // CHECK10-NEXT: store double [[ADD17]], double* [[ARRAYIDX16]], align 8 7475 // CHECK10-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 7476 // CHECK10-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 8 7477 // CHECK10-NEXT: [[ADD18:%.*]] = add nsw i64 [[TMP14]], 1 7478 // CHECK10-NEXT: store i64 [[ADD18]], i64* [[X]], align 8 7479 // CHECK10-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 7480 // CHECK10-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 8 7481 // CHECK10-NEXT: [[CONV19:%.*]] = sext i8 [[TMP15]] to i32 7482 // CHECK10-NEXT: [[ADD20:%.*]] = add nsw i32 [[CONV19]], 1 7483 // CHECK10-NEXT: [[CONV21:%.*]] = trunc i32 [[ADD20]] to i8 7484 // CHECK10-NEXT: store i8 [[CONV21]], i8* [[Y]], align 8 7485 // CHECK10-NEXT: ret void 7486 // 7487 // 7488 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154 7489 // CHECK10-SAME: (i64 [[NN:%.*]]) #[[ATTR0]] { 7490 // CHECK10-NEXT: entry: 7491 // CHECK10-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 7492 // CHECK10-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 7493 // CHECK10-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 7494 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* 7495 // CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 7496 // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32* 7497 // CHECK10-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 7498 // CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8 7499 // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP1]]) 7500 // CHECK10-NEXT: ret void 7501 // 7502 // 7503 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..4 7504 // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[NN:%.*]]) #[[ATTR0]] { 7505 // CHECK10-NEXT: entry: 7506 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 7507 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 7508 // CHECK10-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 7509 // CHECK10-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 7510 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 7511 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 7512 // CHECK10-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 7513 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* 7514 // CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 7515 // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32* 7516 // CHECK10-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 7517 // CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8 7518 // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP1]]) 7519 // CHECK10-NEXT: ret void 7520 // 7521 // 7522 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..5 7523 // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[NN:%.*]]) #[[ATTR0]] { 7524 // CHECK10-NEXT: entry: 7525 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 7526 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 7527 // CHECK10-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 7528 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 7529 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 7530 // CHECK10-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 7531 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* 7532 // CHECK10-NEXT: ret void 7533 // 7534 // 7535 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157 7536 // CHECK10-SAME: (i64 [[NN:%.*]]) #[[ATTR0]] { 7537 // CHECK10-NEXT: entry: 7538 // CHECK10-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 7539 // CHECK10-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 7540 // CHECK10-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 7541 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* 7542 // CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 7543 // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32* 7544 // CHECK10-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 7545 // CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8 7546 // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP1]]) 7547 // CHECK10-NEXT: ret void 7548 // 7549 // 7550 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..6 7551 // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[NN:%.*]]) #[[ATTR0]] { 7552 // CHECK10-NEXT: entry: 7553 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 7554 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 7555 // CHECK10-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 7556 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 7557 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 7558 // CHECK10-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 7559 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* 7560 // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32* [[CONV]]) 7561 // CHECK10-NEXT: ret void 7562 // 7563 // 7564 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..7 7565 // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[NN:%.*]]) #[[ATTR0]] { 7566 // CHECK10-NEXT: entry: 7567 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 7568 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 7569 // CHECK10-NEXT: [[NN_ADDR:%.*]] = alloca i32*, align 8 7570 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 7571 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 7572 // CHECK10-NEXT: store i32* [[NN]], i32** [[NN_ADDR]], align 8 7573 // CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[NN_ADDR]], align 8 7574 // CHECK10-NEXT: ret void 7575 // 7576 // 7577 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182 7578 // CHECK10-SAME: (i64 [[VLA:%.*]]) #[[ATTR0]] { 7579 // CHECK10-NEXT: entry: 7580 // CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 7581 // CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 7582 // CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 7583 // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..8 to void (i32*, i32*, ...)*), i64 [[TMP0]]) 7584 // CHECK10-NEXT: ret void 7585 // 7586 // 7587 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..8 7588 // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[VLA:%.*]]) #[[ATTR0]] { 7589 // CHECK10-NEXT: entry: 7590 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 7591 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 7592 // CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 7593 // CHECK10-NEXT: [[F:%.*]] = alloca i32*, align 8 7594 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 7595 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 7596 // CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 7597 // CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 7598 // CHECK10-NEXT: ret void 7599 // 7600 // 7601 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209 7602 // CHECK10-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 7603 // CHECK10-NEXT: entry: 7604 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 7605 // CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 7606 // CHECK10-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 7607 // CHECK10-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 7608 // CHECK10-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 7609 // CHECK10-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 7610 // CHECK10-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 7611 // CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 7612 // CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 7613 // CHECK10-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 7614 // CHECK10-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 7615 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 7616 // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 7617 // CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 7618 // CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 7619 // CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 7620 // CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* 7621 // CHECK10-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 7622 // CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 7623 // CHECK10-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 7624 // CHECK10-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 7625 // CHECK10-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 7626 // CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 7627 // CHECK10-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8 7628 // CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* 7629 // CHECK10-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 7630 // CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 7631 // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) 7632 // CHECK10-NEXT: ret void 7633 // 7634 // 7635 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..9 7636 // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 7637 // CHECK10-NEXT: entry: 7638 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 7639 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 7640 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 7641 // CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 7642 // CHECK10-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 7643 // CHECK10-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 7644 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 7645 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 7646 // CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 7647 // CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 7648 // CHECK10-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 7649 // CHECK10-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 7650 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 7651 // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 7652 // CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 7653 // CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 7654 // CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 7655 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 7656 // CHECK10-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 7657 // CHECK10-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 7658 // CHECK10-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32 7659 // CHECK10-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 7660 // CHECK10-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 7661 // CHECK10-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 8 7662 // CHECK10-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 8 7663 // CHECK10-NEXT: [[CONV6:%.*]] = sext i8 [[TMP3]] to i32 7664 // CHECK10-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 7665 // CHECK10-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i8 7666 // CHECK10-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 8 7667 // CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 7668 // CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 7669 // CHECK10-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP4]], 1 7670 // CHECK10-NEXT: store i32 [[ADD9]], i32* [[ARRAYIDX]], align 4 7671 // CHECK10-NEXT: ret void 7672 // 7673 // 7674 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227 7675 // CHECK10-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { 7676 // CHECK10-NEXT: entry: 7677 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 7678 // CHECK10-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 7679 // CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 7680 // CHECK10-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 7681 // CHECK10-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 7682 // CHECK10-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 7683 // CHECK10-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 7684 // CHECK10-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 7685 // CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 7686 // CHECK10-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 7687 // CHECK10-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 7688 // CHECK10-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 7689 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 7690 // CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 7691 // CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 7692 // CHECK10-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 7693 // CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 7694 // CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* 7695 // CHECK10-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 7696 // CHECK10-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 7697 // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) 7698 // CHECK10-NEXT: ret void 7699 // 7700 // 7701 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..10 7702 // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { 7703 // CHECK10-NEXT: entry: 7704 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 7705 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 7706 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 7707 // CHECK10-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 7708 // CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 7709 // CHECK10-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 7710 // CHECK10-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 7711 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 7712 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 7713 // CHECK10-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 7714 // CHECK10-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 7715 // CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 7716 // CHECK10-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 7717 // CHECK10-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 7718 // CHECK10-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 7719 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 7720 // CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 7721 // CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 7722 // CHECK10-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 7723 // CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 7724 // CHECK10-NEXT: [[CONV3:%.*]] = sitofp i32 [[TMP4]] to double 7725 // CHECK10-NEXT: [[ADD:%.*]] = fadd double [[CONV3]], 1.500000e+00 7726 // CHECK10-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 7727 // CHECK10-NEXT: store double [[ADD]], double* [[A]], align 8 7728 // CHECK10-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 7729 // CHECK10-NEXT: [[TMP5:%.*]] = load double, double* [[A4]], align 8 7730 // CHECK10-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 7731 // CHECK10-NEXT: store double [[INC]], double* [[A4]], align 8 7732 // CHECK10-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 7733 // CHECK10-NEXT: [[TMP6:%.*]] = mul nsw i64 1, [[TMP2]] 7734 // CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP6]] 7735 // CHECK10-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 7736 // CHECK10-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2 7737 // CHECK10-NEXT: ret void 7738 // 7739 // 7740 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192 7741 // CHECK10-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 7742 // CHECK10-NEXT: entry: 7743 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 7744 // CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 7745 // CHECK10-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 7746 // CHECK10-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 7747 // CHECK10-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 7748 // CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 7749 // CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 7750 // CHECK10-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 7751 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 7752 // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 7753 // CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 7754 // CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 7755 // CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* 7756 // CHECK10-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 7757 // CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 7758 // CHECK10-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 7759 // CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 7760 // CHECK10-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 7761 // CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 7762 // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) 7763 // CHECK10-NEXT: ret void 7764 // 7765 // 7766 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..11 7767 // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 7768 // CHECK10-NEXT: entry: 7769 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 7770 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 7771 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 7772 // CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 7773 // CHECK10-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 7774 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 7775 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 7776 // CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 7777 // CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 7778 // CHECK10-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 7779 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 7780 // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 7781 // CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 7782 // CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 7783 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 7784 // CHECK10-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 7785 // CHECK10-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 7786 // CHECK10-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 7787 // CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 7788 // CHECK10-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 7789 // CHECK10-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 8 7790 // CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 7791 // CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 7792 // CHECK10-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP3]], 1 7793 // CHECK10-NEXT: store i32 [[ADD5]], i32* [[ARRAYIDX]], align 4 7794 // CHECK10-NEXT: ret void 7795 // 7796 // 7797 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101 7798 // CHECK11-SAME: (i32 [[AA:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]], i32 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { 7799 // CHECK11-NEXT: entry: 7800 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 7801 // CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 7802 // CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4 7803 // CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 7804 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) 7805 // CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 7806 // CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 7807 // CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 7808 // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 7809 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 7810 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 7811 // CHECK11-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) 7812 // CHECK11-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 7813 // CHECK11-NEXT: [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 7814 // CHECK11-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 7815 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 7816 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]]) 7817 // CHECK11-NEXT: ret void 7818 // 7819 // 7820 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. 7821 // CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { 7822 // CHECK11-NEXT: entry: 7823 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 7824 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 7825 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 7826 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 7827 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 7828 // CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 7829 // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 7830 // CHECK11-NEXT: ret void 7831 // 7832 // 7833 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 7834 // CHECK11-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] { 7835 // CHECK11-NEXT: entry: 7836 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 7837 // CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 7838 // CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 7839 // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 7840 // CHECK11-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 7841 // CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 7842 // CHECK11-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 7843 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 7844 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]]) 7845 // CHECK11-NEXT: ret void 7846 // 7847 // 7848 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 7849 // CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { 7850 // CHECK11-NEXT: entry: 7851 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 7852 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 7853 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 7854 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 7855 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 7856 // CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 7857 // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 7858 // CHECK11-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 7859 // CHECK11-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 7860 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 7861 // CHECK11-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 7862 // CHECK11-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 4 7863 // CHECK11-NEXT: ret void 7864 // 7865 // 7866 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118 7867 // CHECK11-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { 7868 // CHECK11-NEXT: entry: 7869 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 7870 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 7871 // CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 7872 // CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 7873 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 7874 // CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 7875 // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 7876 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 7877 // CHECK11-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 7878 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 7879 // CHECK11-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 7880 // CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 7881 // CHECK11-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 7882 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 7883 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) 7884 // CHECK11-NEXT: ret void 7885 // 7886 // 7887 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..2 7888 // CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { 7889 // CHECK11-NEXT: entry: 7890 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 7891 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 7892 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 7893 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 7894 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 7895 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 7896 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 7897 // CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 7898 // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 7899 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 7900 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 7901 // CHECK11-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 7902 // CHECK11-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 4 7903 // CHECK11-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32 7904 // CHECK11-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 7905 // CHECK11-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 7906 // CHECK11-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 4 7907 // CHECK11-NEXT: ret void 7908 // 7909 // 7910 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142 7911 // CHECK11-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] { 7912 // CHECK11-NEXT: entry: 7913 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 7914 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 7915 // CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 7916 // CHECK11-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 7917 // CHECK11-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 7918 // CHECK11-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 7919 // CHECK11-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 7920 // CHECK11-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 7921 // CHECK11-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 7922 // CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 7923 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 7924 // CHECK11-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 7925 // CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 7926 // CHECK11-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 7927 // CHECK11-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 7928 // CHECK11-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 7929 // CHECK11-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 7930 // CHECK11-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 7931 // CHECK11-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 7932 // CHECK11-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 7933 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 7934 // CHECK11-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 7935 // CHECK11-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 7936 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 7937 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 7938 // CHECK11-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 7939 // CHECK11-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 7940 // CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 7941 // CHECK11-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4 7942 // CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4 7943 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) 7944 // CHECK11-NEXT: ret void 7945 // 7946 // 7947 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..3 7948 // CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] { 7949 // CHECK11-NEXT: entry: 7950 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 7951 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 7952 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 7953 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 7954 // CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 7955 // CHECK11-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 7956 // CHECK11-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 7957 // CHECK11-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 7958 // CHECK11-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 7959 // CHECK11-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 7960 // CHECK11-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 7961 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 7962 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 7963 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 7964 // CHECK11-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 7965 // CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 7966 // CHECK11-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 7967 // CHECK11-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 7968 // CHECK11-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 7969 // CHECK11-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 7970 // CHECK11-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 7971 // CHECK11-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 7972 // CHECK11-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 7973 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 7974 // CHECK11-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 7975 // CHECK11-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 7976 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 7977 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 7978 // CHECK11-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 7979 // CHECK11-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 7980 // CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 7981 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 7982 // CHECK11-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 7983 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2 7984 // CHECK11-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 7985 // CHECK11-NEXT: [[CONV:%.*]] = fpext float [[TMP9]] to double 7986 // CHECK11-NEXT: [[ADD5:%.*]] = fadd double [[CONV]], 1.000000e+00 7987 // CHECK11-NEXT: [[CONV6:%.*]] = fptrunc double [[ADD5]] to float 7988 // CHECK11-NEXT: store float [[CONV6]], float* [[ARRAYIDX]], align 4 7989 // CHECK11-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3 7990 // CHECK11-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX7]], align 4 7991 // CHECK11-NEXT: [[CONV8:%.*]] = fpext float [[TMP10]] to double 7992 // CHECK11-NEXT: [[ADD9:%.*]] = fadd double [[CONV8]], 1.000000e+00 7993 // CHECK11-NEXT: [[CONV10:%.*]] = fptrunc double [[ADD9]] to float 7994 // CHECK11-NEXT: store float [[CONV10]], float* [[ARRAYIDX7]], align 4 7995 // CHECK11-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1 7996 // CHECK11-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX11]], i32 0, i32 2 7997 // CHECK11-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX12]], align 8 7998 // CHECK11-NEXT: [[ADD13:%.*]] = fadd double [[TMP11]], 1.000000e+00 7999 // CHECK11-NEXT: store double [[ADD13]], double* [[ARRAYIDX12]], align 8 8000 // CHECK11-NEXT: [[TMP12:%.*]] = mul nsw i32 1, [[TMP5]] 8001 // CHECK11-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP12]] 8002 // CHECK11-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX14]], i32 3 8003 // CHECK11-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX15]], align 8 8004 // CHECK11-NEXT: [[ADD16:%.*]] = fadd double [[TMP13]], 1.000000e+00 8005 // CHECK11-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8 8006 // CHECK11-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 8007 // CHECK11-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 4 8008 // CHECK11-NEXT: [[ADD17:%.*]] = add nsw i64 [[TMP14]], 1 8009 // CHECK11-NEXT: store i64 [[ADD17]], i64* [[X]], align 4 8010 // CHECK11-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 8011 // CHECK11-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 4 8012 // CHECK11-NEXT: [[CONV18:%.*]] = sext i8 [[TMP15]] to i32 8013 // CHECK11-NEXT: [[ADD19:%.*]] = add nsw i32 [[CONV18]], 1 8014 // CHECK11-NEXT: [[CONV20:%.*]] = trunc i32 [[ADD19]] to i8 8015 // CHECK11-NEXT: store i8 [[CONV20]], i8* [[Y]], align 4 8016 // CHECK11-NEXT: ret void 8017 // 8018 // 8019 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154 8020 // CHECK11-SAME: (i32 [[NN:%.*]]) #[[ATTR0]] { 8021 // CHECK11-NEXT: entry: 8022 // CHECK11-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 8023 // CHECK11-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4 8024 // CHECK11-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 8025 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[NN_ADDR]], align 4 8026 // CHECK11-NEXT: store i32 [[TMP0]], i32* [[NN_CASTED]], align 4 8027 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[NN_CASTED]], align 4 8028 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP1]]) 8029 // CHECK11-NEXT: ret void 8030 // 8031 // 8032 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..4 8033 // CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[NN:%.*]]) #[[ATTR0]] { 8034 // CHECK11-NEXT: entry: 8035 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 8036 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 8037 // CHECK11-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 8038 // CHECK11-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4 8039 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 8040 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 8041 // CHECK11-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 8042 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[NN_ADDR]], align 4 8043 // CHECK11-NEXT: store i32 [[TMP0]], i32* [[NN_CASTED]], align 4 8044 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[NN_CASTED]], align 4 8045 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP1]]) 8046 // CHECK11-NEXT: ret void 8047 // 8048 // 8049 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..5 8050 // CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[NN:%.*]]) #[[ATTR0]] { 8051 // CHECK11-NEXT: entry: 8052 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 8053 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 8054 // CHECK11-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 8055 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 8056 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 8057 // CHECK11-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 8058 // CHECK11-NEXT: ret void 8059 // 8060 // 8061 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157 8062 // CHECK11-SAME: (i32 [[NN:%.*]]) #[[ATTR0]] { 8063 // CHECK11-NEXT: entry: 8064 // CHECK11-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 8065 // CHECK11-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4 8066 // CHECK11-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 8067 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[NN_ADDR]], align 4 8068 // CHECK11-NEXT: store i32 [[TMP0]], i32* [[NN_CASTED]], align 4 8069 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[NN_CASTED]], align 4 8070 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP1]]) 8071 // CHECK11-NEXT: ret void 8072 // 8073 // 8074 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..6 8075 // CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[NN:%.*]]) #[[ATTR0]] { 8076 // CHECK11-NEXT: entry: 8077 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 8078 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 8079 // CHECK11-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 8080 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 8081 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 8082 // CHECK11-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 8083 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32* [[NN_ADDR]]) 8084 // CHECK11-NEXT: ret void 8085 // 8086 // 8087 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..7 8088 // CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[NN:%.*]]) #[[ATTR0]] { 8089 // CHECK11-NEXT: entry: 8090 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 8091 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 8092 // CHECK11-NEXT: [[NN_ADDR:%.*]] = alloca i32*, align 4 8093 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 8094 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 8095 // CHECK11-NEXT: store i32* [[NN]], i32** [[NN_ADDR]], align 4 8096 // CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[NN_ADDR]], align 4 8097 // CHECK11-NEXT: ret void 8098 // 8099 // 8100 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182 8101 // CHECK11-SAME: (i32 [[VLA:%.*]]) #[[ATTR0]] { 8102 // CHECK11-NEXT: entry: 8103 // CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 8104 // CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 8105 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 8106 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..8 to void (i32*, i32*, ...)*), i32 [[TMP0]]) 8107 // CHECK11-NEXT: ret void 8108 // 8109 // 8110 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..8 8111 // CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[VLA:%.*]]) #[[ATTR0]] { 8112 // CHECK11-NEXT: entry: 8113 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 8114 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 8115 // CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 8116 // CHECK11-NEXT: [[F:%.*]] = alloca i32*, align 4 8117 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 8118 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 8119 // CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 8120 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 8121 // CHECK11-NEXT: ret void 8122 // 8123 // 8124 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209 8125 // CHECK11-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 8126 // CHECK11-NEXT: entry: 8127 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 8128 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 8129 // CHECK11-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 8130 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 8131 // CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 8132 // CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 8133 // CHECK11-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 8134 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 8135 // CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 8136 // CHECK11-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 8137 // CHECK11-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 8138 // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 8139 // CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 8140 // CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 8141 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 8142 // CHECK11-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 8143 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 8144 // CHECK11-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 8145 // CHECK11-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 8146 // CHECK11-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 8147 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 8148 // CHECK11-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 4 8149 // CHECK11-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* 8150 // CHECK11-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 8151 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 8152 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) 8153 // CHECK11-NEXT: ret void 8154 // 8155 // 8156 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..9 8157 // CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 8158 // CHECK11-NEXT: entry: 8159 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 8160 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 8161 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 8162 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 8163 // CHECK11-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 8164 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 8165 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 8166 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 8167 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 8168 // CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 8169 // CHECK11-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 8170 // CHECK11-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 8171 // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 8172 // CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 8173 // CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 8174 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 8175 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 8176 // CHECK11-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 8177 // CHECK11-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 8178 // CHECK11-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 8179 // CHECK11-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 8180 // CHECK11-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 8181 // CHECK11-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 4 8182 // CHECK11-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 4 8183 // CHECK11-NEXT: [[CONV5:%.*]] = sext i8 [[TMP3]] to i32 8184 // CHECK11-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 8185 // CHECK11-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i8 8186 // CHECK11-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 4 8187 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 8188 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 8189 // CHECK11-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP4]], 1 8190 // CHECK11-NEXT: store i32 [[ADD8]], i32* [[ARRAYIDX]], align 4 8191 // CHECK11-NEXT: ret void 8192 // 8193 // 8194 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227 8195 // CHECK11-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { 8196 // CHECK11-NEXT: entry: 8197 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 8198 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 8199 // CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 8200 // CHECK11-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 8201 // CHECK11-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 8202 // CHECK11-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 8203 // CHECK11-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 8204 // CHECK11-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 8205 // CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 8206 // CHECK11-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 8207 // CHECK11-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 8208 // CHECK11-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 8209 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 8210 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 8211 // CHECK11-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 8212 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 8213 // CHECK11-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 8214 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 8215 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]]) 8216 // CHECK11-NEXT: ret void 8217 // 8218 // 8219 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..10 8220 // CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { 8221 // CHECK11-NEXT: entry: 8222 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 8223 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 8224 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 8225 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 8226 // CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 8227 // CHECK11-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 8228 // CHECK11-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 8229 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 8230 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 8231 // CHECK11-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 8232 // CHECK11-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 8233 // CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 8234 // CHECK11-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 8235 // CHECK11-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 8236 // CHECK11-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 8237 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 8238 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 8239 // CHECK11-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 8240 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 8241 // CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP4]] to double 8242 // CHECK11-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 8243 // CHECK11-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 8244 // CHECK11-NEXT: store double [[ADD]], double* [[A]], align 4 8245 // CHECK11-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 8246 // CHECK11-NEXT: [[TMP5:%.*]] = load double, double* [[A3]], align 4 8247 // CHECK11-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 8248 // CHECK11-NEXT: store double [[INC]], double* [[A3]], align 4 8249 // CHECK11-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 8250 // CHECK11-NEXT: [[TMP6:%.*]] = mul nsw i32 1, [[TMP2]] 8251 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP6]] 8252 // CHECK11-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 8253 // CHECK11-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 8254 // CHECK11-NEXT: ret void 8255 // 8256 // 8257 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192 8258 // CHECK11-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 8259 // CHECK11-NEXT: entry: 8260 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 8261 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 8262 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 8263 // CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 8264 // CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 8265 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 8266 // CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 8267 // CHECK11-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 8268 // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 8269 // CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 8270 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 8271 // CHECK11-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 8272 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 8273 // CHECK11-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 8274 // CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 8275 // CHECK11-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 8276 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 8277 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) 8278 // CHECK11-NEXT: ret void 8279 // 8280 // 8281 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..11 8282 // CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 8283 // CHECK11-NEXT: entry: 8284 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 8285 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 8286 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 8287 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 8288 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 8289 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 8290 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 8291 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 8292 // CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 8293 // CHECK11-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 8294 // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 8295 // CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 8296 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 8297 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 8298 // CHECK11-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 8299 // CHECK11-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 8300 // CHECK11-NEXT: [[CONV1:%.*]] = sext i16 [[TMP2]] to i32 8301 // CHECK11-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 8302 // CHECK11-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 8303 // CHECK11-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 4 8304 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 8305 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 8306 // CHECK11-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1 8307 // CHECK11-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4 8308 // CHECK11-NEXT: ret void 8309 // 8310 // 8311 // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101 8312 // CHECK12-SAME: (i32 [[AA:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]], i32 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { 8313 // CHECK12-NEXT: entry: 8314 // CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 8315 // CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 8316 // CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4 8317 // CHECK12-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 8318 // CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) 8319 // CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 8320 // CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 8321 // CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 8322 // CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 8323 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 8324 // CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 8325 // CHECK12-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) 8326 // CHECK12-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 8327 // CHECK12-NEXT: [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 8328 // CHECK12-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 8329 // CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 8330 // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]]) 8331 // CHECK12-NEXT: ret void 8332 // 8333 // 8334 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined. 8335 // CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { 8336 // CHECK12-NEXT: entry: 8337 // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 8338 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 8339 // CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 8340 // CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 8341 // CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 8342 // CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 8343 // CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 8344 // CHECK12-NEXT: ret void 8345 // 8346 // 8347 // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 8348 // CHECK12-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] { 8349 // CHECK12-NEXT: entry: 8350 // CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 8351 // CHECK12-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 8352 // CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 8353 // CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 8354 // CHECK12-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 8355 // CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 8356 // CHECK12-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 8357 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 8358 // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]]) 8359 // CHECK12-NEXT: ret void 8360 // 8361 // 8362 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..1 8363 // CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { 8364 // CHECK12-NEXT: entry: 8365 // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 8366 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 8367 // CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 8368 // CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 8369 // CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 8370 // CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 8371 // CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 8372 // CHECK12-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 8373 // CHECK12-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 8374 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 8375 // CHECK12-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 8376 // CHECK12-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 4 8377 // CHECK12-NEXT: ret void 8378 // 8379 // 8380 // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118 8381 // CHECK12-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { 8382 // CHECK12-NEXT: entry: 8383 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 8384 // CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 8385 // CHECK12-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 8386 // CHECK12-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 8387 // CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 8388 // CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 8389 // CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 8390 // CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 8391 // CHECK12-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 8392 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 8393 // CHECK12-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 8394 // CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 8395 // CHECK12-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 8396 // CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 8397 // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) 8398 // CHECK12-NEXT: ret void 8399 // 8400 // 8401 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..2 8402 // CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { 8403 // CHECK12-NEXT: entry: 8404 // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 8405 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 8406 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 8407 // CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 8408 // CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 8409 // CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 8410 // CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 8411 // CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 8412 // CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 8413 // CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 8414 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 8415 // CHECK12-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 8416 // CHECK12-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 4 8417 // CHECK12-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32 8418 // CHECK12-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 8419 // CHECK12-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 8420 // CHECK12-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 4 8421 // CHECK12-NEXT: ret void 8422 // 8423 // 8424 // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142 8425 // CHECK12-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] { 8426 // CHECK12-NEXT: entry: 8427 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 8428 // CHECK12-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 8429 // CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 8430 // CHECK12-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 8431 // CHECK12-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 8432 // CHECK12-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 8433 // CHECK12-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 8434 // CHECK12-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 8435 // CHECK12-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 8436 // CHECK12-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 8437 // CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 8438 // CHECK12-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 8439 // CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 8440 // CHECK12-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 8441 // CHECK12-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 8442 // CHECK12-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 8443 // CHECK12-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 8444 // CHECK12-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 8445 // CHECK12-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 8446 // CHECK12-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 8447 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 8448 // CHECK12-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 8449 // CHECK12-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 8450 // CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 8451 // CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 8452 // CHECK12-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 8453 // CHECK12-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 8454 // CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 8455 // CHECK12-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4 8456 // CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4 8457 // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) 8458 // CHECK12-NEXT: ret void 8459 // 8460 // 8461 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..3 8462 // CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] { 8463 // CHECK12-NEXT: entry: 8464 // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 8465 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 8466 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 8467 // CHECK12-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 8468 // CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 8469 // CHECK12-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 8470 // CHECK12-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 8471 // CHECK12-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 8472 // CHECK12-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 8473 // CHECK12-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 8474 // CHECK12-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 8475 // CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 8476 // CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 8477 // CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 8478 // CHECK12-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 8479 // CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 8480 // CHECK12-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 8481 // CHECK12-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 8482 // CHECK12-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 8483 // CHECK12-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 8484 // CHECK12-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 8485 // CHECK12-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 8486 // CHECK12-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 8487 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 8488 // CHECK12-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 8489 // CHECK12-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 8490 // CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 8491 // CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 8492 // CHECK12-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 8493 // CHECK12-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 8494 // CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 8495 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 8496 // CHECK12-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 8497 // CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2 8498 // CHECK12-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 8499 // CHECK12-NEXT: [[CONV:%.*]] = fpext float [[TMP9]] to double 8500 // CHECK12-NEXT: [[ADD5:%.*]] = fadd double [[CONV]], 1.000000e+00 8501 // CHECK12-NEXT: [[CONV6:%.*]] = fptrunc double [[ADD5]] to float 8502 // CHECK12-NEXT: store float [[CONV6]], float* [[ARRAYIDX]], align 4 8503 // CHECK12-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3 8504 // CHECK12-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX7]], align 4 8505 // CHECK12-NEXT: [[CONV8:%.*]] = fpext float [[TMP10]] to double 8506 // CHECK12-NEXT: [[ADD9:%.*]] = fadd double [[CONV8]], 1.000000e+00 8507 // CHECK12-NEXT: [[CONV10:%.*]] = fptrunc double [[ADD9]] to float 8508 // CHECK12-NEXT: store float [[CONV10]], float* [[ARRAYIDX7]], align 4 8509 // CHECK12-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1 8510 // CHECK12-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX11]], i32 0, i32 2 8511 // CHECK12-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX12]], align 8 8512 // CHECK12-NEXT: [[ADD13:%.*]] = fadd double [[TMP11]], 1.000000e+00 8513 // CHECK12-NEXT: store double [[ADD13]], double* [[ARRAYIDX12]], align 8 8514 // CHECK12-NEXT: [[TMP12:%.*]] = mul nsw i32 1, [[TMP5]] 8515 // CHECK12-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP12]] 8516 // CHECK12-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX14]], i32 3 8517 // CHECK12-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX15]], align 8 8518 // CHECK12-NEXT: [[ADD16:%.*]] = fadd double [[TMP13]], 1.000000e+00 8519 // CHECK12-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8 8520 // CHECK12-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 8521 // CHECK12-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 4 8522 // CHECK12-NEXT: [[ADD17:%.*]] = add nsw i64 [[TMP14]], 1 8523 // CHECK12-NEXT: store i64 [[ADD17]], i64* [[X]], align 4 8524 // CHECK12-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 8525 // CHECK12-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 4 8526 // CHECK12-NEXT: [[CONV18:%.*]] = sext i8 [[TMP15]] to i32 8527 // CHECK12-NEXT: [[ADD19:%.*]] = add nsw i32 [[CONV18]], 1 8528 // CHECK12-NEXT: [[CONV20:%.*]] = trunc i32 [[ADD19]] to i8 8529 // CHECK12-NEXT: store i8 [[CONV20]], i8* [[Y]], align 4 8530 // CHECK12-NEXT: ret void 8531 // 8532 // 8533 // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154 8534 // CHECK12-SAME: (i32 [[NN:%.*]]) #[[ATTR0]] { 8535 // CHECK12-NEXT: entry: 8536 // CHECK12-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 8537 // CHECK12-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4 8538 // CHECK12-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 8539 // CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[NN_ADDR]], align 4 8540 // CHECK12-NEXT: store i32 [[TMP0]], i32* [[NN_CASTED]], align 4 8541 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[NN_CASTED]], align 4 8542 // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP1]]) 8543 // CHECK12-NEXT: ret void 8544 // 8545 // 8546 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..4 8547 // CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[NN:%.*]]) #[[ATTR0]] { 8548 // CHECK12-NEXT: entry: 8549 // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 8550 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 8551 // CHECK12-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 8552 // CHECK12-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4 8553 // CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 8554 // CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 8555 // CHECK12-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 8556 // CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[NN_ADDR]], align 4 8557 // CHECK12-NEXT: store i32 [[TMP0]], i32* [[NN_CASTED]], align 4 8558 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[NN_CASTED]], align 4 8559 // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP1]]) 8560 // CHECK12-NEXT: ret void 8561 // 8562 // 8563 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..5 8564 // CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[NN:%.*]]) #[[ATTR0]] { 8565 // CHECK12-NEXT: entry: 8566 // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 8567 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 8568 // CHECK12-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 8569 // CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 8570 // CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 8571 // CHECK12-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 8572 // CHECK12-NEXT: ret void 8573 // 8574 // 8575 // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157 8576 // CHECK12-SAME: (i32 [[NN:%.*]]) #[[ATTR0]] { 8577 // CHECK12-NEXT: entry: 8578 // CHECK12-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 8579 // CHECK12-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4 8580 // CHECK12-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 8581 // CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[NN_ADDR]], align 4 8582 // CHECK12-NEXT: store i32 [[TMP0]], i32* [[NN_CASTED]], align 4 8583 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[NN_CASTED]], align 4 8584 // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP1]]) 8585 // CHECK12-NEXT: ret void 8586 // 8587 // 8588 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..6 8589 // CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[NN:%.*]]) #[[ATTR0]] { 8590 // CHECK12-NEXT: entry: 8591 // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 8592 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 8593 // CHECK12-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 8594 // CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 8595 // CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 8596 // CHECK12-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 8597 // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32* [[NN_ADDR]]) 8598 // CHECK12-NEXT: ret void 8599 // 8600 // 8601 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..7 8602 // CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[NN:%.*]]) #[[ATTR0]] { 8603 // CHECK12-NEXT: entry: 8604 // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 8605 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 8606 // CHECK12-NEXT: [[NN_ADDR:%.*]] = alloca i32*, align 4 8607 // CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 8608 // CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 8609 // CHECK12-NEXT: store i32* [[NN]], i32** [[NN_ADDR]], align 4 8610 // CHECK12-NEXT: [[TMP0:%.*]] = load i32*, i32** [[NN_ADDR]], align 4 8611 // CHECK12-NEXT: ret void 8612 // 8613 // 8614 // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182 8615 // CHECK12-SAME: (i32 [[VLA:%.*]]) #[[ATTR0]] { 8616 // CHECK12-NEXT: entry: 8617 // CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 8618 // CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 8619 // CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 8620 // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..8 to void (i32*, i32*, ...)*), i32 [[TMP0]]) 8621 // CHECK12-NEXT: ret void 8622 // 8623 // 8624 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..8 8625 // CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[VLA:%.*]]) #[[ATTR0]] { 8626 // CHECK12-NEXT: entry: 8627 // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 8628 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 8629 // CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 8630 // CHECK12-NEXT: [[F:%.*]] = alloca i32*, align 4 8631 // CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 8632 // CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 8633 // CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 8634 // CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 8635 // CHECK12-NEXT: ret void 8636 // 8637 // 8638 // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209 8639 // CHECK12-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 8640 // CHECK12-NEXT: entry: 8641 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 8642 // CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 8643 // CHECK12-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 8644 // CHECK12-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 8645 // CHECK12-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 8646 // CHECK12-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 8647 // CHECK12-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 8648 // CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 8649 // CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 8650 // CHECK12-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 8651 // CHECK12-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 8652 // CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 8653 // CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 8654 // CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 8655 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 8656 // CHECK12-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 8657 // CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 8658 // CHECK12-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 8659 // CHECK12-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 8660 // CHECK12-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 8661 // CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 8662 // CHECK12-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 4 8663 // CHECK12-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* 8664 // CHECK12-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 8665 // CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 8666 // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) 8667 // CHECK12-NEXT: ret void 8668 // 8669 // 8670 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..9 8671 // CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 8672 // CHECK12-NEXT: entry: 8673 // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 8674 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 8675 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 8676 // CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 8677 // CHECK12-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 8678 // CHECK12-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 8679 // CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 8680 // CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 8681 // CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 8682 // CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 8683 // CHECK12-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 8684 // CHECK12-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 8685 // CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 8686 // CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 8687 // CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 8688 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 8689 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 8690 // CHECK12-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 8691 // CHECK12-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 8692 // CHECK12-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 8693 // CHECK12-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 8694 // CHECK12-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 8695 // CHECK12-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 4 8696 // CHECK12-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 4 8697 // CHECK12-NEXT: [[CONV5:%.*]] = sext i8 [[TMP3]] to i32 8698 // CHECK12-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 8699 // CHECK12-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i8 8700 // CHECK12-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 4 8701 // CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 8702 // CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 8703 // CHECK12-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP4]], 1 8704 // CHECK12-NEXT: store i32 [[ADD8]], i32* [[ARRAYIDX]], align 4 8705 // CHECK12-NEXT: ret void 8706 // 8707 // 8708 // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227 8709 // CHECK12-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { 8710 // CHECK12-NEXT: entry: 8711 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 8712 // CHECK12-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 8713 // CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 8714 // CHECK12-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 8715 // CHECK12-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 8716 // CHECK12-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 8717 // CHECK12-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 8718 // CHECK12-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 8719 // CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 8720 // CHECK12-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 8721 // CHECK12-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 8722 // CHECK12-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 8723 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 8724 // CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 8725 // CHECK12-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 8726 // CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 8727 // CHECK12-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 8728 // CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 8729 // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]]) 8730 // CHECK12-NEXT: ret void 8731 // 8732 // 8733 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..10 8734 // CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { 8735 // CHECK12-NEXT: entry: 8736 // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 8737 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 8738 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 8739 // CHECK12-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 8740 // CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 8741 // CHECK12-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 8742 // CHECK12-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 8743 // CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 8744 // CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 8745 // CHECK12-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 8746 // CHECK12-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 8747 // CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 8748 // CHECK12-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 8749 // CHECK12-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 8750 // CHECK12-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 8751 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 8752 // CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 8753 // CHECK12-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 8754 // CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 8755 // CHECK12-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP4]] to double 8756 // CHECK12-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 8757 // CHECK12-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 8758 // CHECK12-NEXT: store double [[ADD]], double* [[A]], align 4 8759 // CHECK12-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 8760 // CHECK12-NEXT: [[TMP5:%.*]] = load double, double* [[A3]], align 4 8761 // CHECK12-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 8762 // CHECK12-NEXT: store double [[INC]], double* [[A3]], align 4 8763 // CHECK12-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 8764 // CHECK12-NEXT: [[TMP6:%.*]] = mul nsw i32 1, [[TMP2]] 8765 // CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP6]] 8766 // CHECK12-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 8767 // CHECK12-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 8768 // CHECK12-NEXT: ret void 8769 // 8770 // 8771 // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192 8772 // CHECK12-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 8773 // CHECK12-NEXT: entry: 8774 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 8775 // CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 8776 // CHECK12-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 8777 // CHECK12-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 8778 // CHECK12-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 8779 // CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 8780 // CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 8781 // CHECK12-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 8782 // CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 8783 // CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 8784 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 8785 // CHECK12-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 8786 // CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 8787 // CHECK12-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 8788 // CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 8789 // CHECK12-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 8790 // CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 8791 // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) 8792 // CHECK12-NEXT: ret void 8793 // 8794 // 8795 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..11 8796 // CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 8797 // CHECK12-NEXT: entry: 8798 // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 8799 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 8800 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 8801 // CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 8802 // CHECK12-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 8803 // CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 8804 // CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 8805 // CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 8806 // CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 8807 // CHECK12-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 8808 // CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 8809 // CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 8810 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 8811 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 8812 // CHECK12-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 8813 // CHECK12-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 8814 // CHECK12-NEXT: [[CONV1:%.*]] = sext i16 [[TMP2]] to i32 8815 // CHECK12-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 8816 // CHECK12-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 8817 // CHECK12-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 4 8818 // CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 8819 // CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 8820 // CHECK12-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1 8821 // CHECK12-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4 8822 // CHECK12-NEXT: ret void 8823 // 8824 // 8825 // CHECK13-LABEL: define {{[^@]+}}@_Z3fooi 8826 // CHECK13-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { 8827 // CHECK13-NEXT: entry: 8828 // CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 8829 // CHECK13-NEXT: [[A:%.*]] = alloca i32, align 4 8830 // CHECK13-NEXT: [[AA:%.*]] = alloca i16, align 2 8831 // CHECK13-NEXT: [[B:%.*]] = alloca [10 x float], align 4 8832 // CHECK13-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 8833 // CHECK13-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 8834 // CHECK13-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 8835 // CHECK13-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 8836 // CHECK13-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 8837 // CHECK13-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 8838 // CHECK13-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 8839 // CHECK13-NEXT: [[NN:%.*]] = alloca i32, align 4 8840 // CHECK13-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 8841 // CHECK13-NEXT: store i32 0, i32* [[A]], align 4 8842 // CHECK13-NEXT: store i16 0, i16* [[AA]], align 2 8843 // CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 8844 // CHECK13-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 8845 // CHECK13-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() 8846 // CHECK13-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 8847 // CHECK13-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4 8848 // CHECK13-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 8849 // CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 8850 // CHECK13-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64 8851 // CHECK13-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]] 8852 // CHECK13-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8 8853 // CHECK13-NEXT: store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8 8854 // CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 8855 // CHECK13-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_]], align 4 8856 // CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 8857 // CHECK13-NEXT: store i32 [[TMP7]], i32* [[DOTCAPTURE_EXPR_2]], align 4 8858 // CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 8859 // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 8860 // CHECK13-NEXT: store i32 [[ADD]], i32* [[A]], align 4 8861 // CHECK13-NEXT: [[TMP9:%.*]] = load i16, i16* [[AA]], align 2 8862 // CHECK13-NEXT: [[CONV:%.*]] = sext i16 [[TMP9]] to i32 8863 // CHECK13-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1 8864 // CHECK13-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 8865 // CHECK13-NEXT: store i16 [[CONV4]], i16* [[AA]], align 2 8866 // CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[A]], align 4 8867 // CHECK13-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP10]], 1 8868 // CHECK13-NEXT: store i32 [[ADD5]], i32* [[A]], align 4 8869 // CHECK13-NEXT: [[TMP11:%.*]] = load i16, i16* [[AA]], align 2 8870 // CHECK13-NEXT: [[CONV6:%.*]] = sext i16 [[TMP11]] to i32 8871 // CHECK13-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 8872 // CHECK13-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i16 8873 // CHECK13-NEXT: store i16 [[CONV8]], i16* [[AA]], align 2 8874 // CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[A]], align 4 8875 // CHECK13-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP12]], 1 8876 // CHECK13-NEXT: store i32 [[ADD9]], i32* [[A]], align 4 8877 // CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2 8878 // CHECK13-NEXT: [[TMP13:%.*]] = load float, float* [[ARRAYIDX]], align 4 8879 // CHECK13-NEXT: [[CONV10:%.*]] = fpext float [[TMP13]] to double 8880 // CHECK13-NEXT: [[ADD11:%.*]] = fadd double [[CONV10]], 1.000000e+00 8881 // CHECK13-NEXT: [[CONV12:%.*]] = fptrunc double [[ADD11]] to float 8882 // CHECK13-NEXT: store float [[CONV12]], float* [[ARRAYIDX]], align 4 8883 // CHECK13-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3 8884 // CHECK13-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX13]], align 4 8885 // CHECK13-NEXT: [[CONV14:%.*]] = fpext float [[TMP14]] to double 8886 // CHECK13-NEXT: [[ADD15:%.*]] = fadd double [[CONV14]], 1.000000e+00 8887 // CHECK13-NEXT: [[CONV16:%.*]] = fptrunc double [[ADD15]] to float 8888 // CHECK13-NEXT: store float [[CONV16]], float* [[ARRAYIDX13]], align 4 8889 // CHECK13-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1 8890 // CHECK13-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX17]], i64 0, i64 2 8891 // CHECK13-NEXT: [[TMP15:%.*]] = load double, double* [[ARRAYIDX18]], align 8 8892 // CHECK13-NEXT: [[ADD19:%.*]] = fadd double [[TMP15]], 1.000000e+00 8893 // CHECK13-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8 8894 // CHECK13-NEXT: [[TMP16:%.*]] = mul nsw i64 1, [[TMP4]] 8895 // CHECK13-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP16]] 8896 // CHECK13-NEXT: [[ARRAYIDX21:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX20]], i64 3 8897 // CHECK13-NEXT: [[TMP17:%.*]] = load double, double* [[ARRAYIDX21]], align 8 8898 // CHECK13-NEXT: [[ADD22:%.*]] = fadd double [[TMP17]], 1.000000e+00 8899 // CHECK13-NEXT: store double [[ADD22]], double* [[ARRAYIDX21]], align 8 8900 // CHECK13-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 8901 // CHECK13-NEXT: [[TMP18:%.*]] = load i64, i64* [[X]], align 8 8902 // CHECK13-NEXT: [[ADD23:%.*]] = add nsw i64 [[TMP18]], 1 8903 // CHECK13-NEXT: store i64 [[ADD23]], i64* [[X]], align 8 8904 // CHECK13-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 8905 // CHECK13-NEXT: [[TMP19:%.*]] = load i8, i8* [[Y]], align 8 8906 // CHECK13-NEXT: [[CONV24:%.*]] = sext i8 [[TMP19]] to i32 8907 // CHECK13-NEXT: [[ADD25:%.*]] = add nsw i32 [[CONV24]], 1 8908 // CHECK13-NEXT: [[CONV26:%.*]] = trunc i32 [[ADD25]] to i8 8909 // CHECK13-NEXT: store i8 [[CONV26]], i8* [[Y]], align 8 8910 // CHECK13-NEXT: store i32 0, i32* [[NN]], align 4 8911 // CHECK13-NEXT: [[TMP20:%.*]] = load i32, i32* [[A]], align 4 8912 // CHECK13-NEXT: [[TMP21:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 8913 // CHECK13-NEXT: call void @llvm.stackrestore(i8* [[TMP21]]) 8914 // CHECK13-NEXT: ret i32 [[TMP20]] 8915 // 8916 // 8917 // CHECK13-LABEL: define {{[^@]+}}@_Z6bazzzziPi 8918 // CHECK13-SAME: (i32 signext [[N:%.*]], i32* [[F:%.*]]) #[[ATTR0]] { 8919 // CHECK13-NEXT: entry: 8920 // CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 8921 // CHECK13-NEXT: [[F_ADDR:%.*]] = alloca i32*, align 8 8922 // CHECK13-NEXT: [[F1:%.*]] = alloca i32*, align 8 8923 // CHECK13-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 8924 // CHECK13-NEXT: store i32* [[F]], i32** [[F_ADDR]], align 8 8925 // CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 8926 // CHECK13-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 8927 // CHECK13-NEXT: ret void 8928 // 8929 // 8930 // CHECK13-LABEL: define {{[^@]+}}@_Z3bari 8931 // CHECK13-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { 8932 // CHECK13-NEXT: entry: 8933 // CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 8934 // CHECK13-NEXT: [[A:%.*]] = alloca i32, align 4 8935 // CHECK13-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 8936 // CHECK13-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 8937 // CHECK13-NEXT: store i32 0, i32* [[A]], align 4 8938 // CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 8939 // CHECK13-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]]) 8940 // CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 8941 // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 8942 // CHECK13-NEXT: store i32 [[ADD]], i32* [[A]], align 4 8943 // CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 8944 // CHECK13-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]]) 8945 // CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 8946 // CHECK13-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 8947 // CHECK13-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 8948 // CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 8949 // CHECK13-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]]) 8950 // CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 8951 // CHECK13-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 8952 // CHECK13-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 8953 // CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 8954 // CHECK13-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]]) 8955 // CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 8956 // CHECK13-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] 8957 // CHECK13-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 8958 // CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 8959 // CHECK13-NEXT: ret i32 [[TMP8]] 8960 // 8961 // 8962 // CHECK13-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 8963 // CHECK13-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { 8964 // CHECK13-NEXT: entry: 8965 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 8966 // CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 8967 // CHECK13-NEXT: [[B:%.*]] = alloca i32, align 4 8968 // CHECK13-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 8969 // CHECK13-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 8970 // CHECK13-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 8971 // CHECK13-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 8972 // CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 8973 // CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 8974 // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 8975 // CHECK13-NEXT: store i32 [[ADD]], i32* [[B]], align 4 8976 // CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 8977 // CHECK13-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 8978 // CHECK13-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() 8979 // CHECK13-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 8980 // CHECK13-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] 8981 // CHECK13-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 8982 // CHECK13-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 8983 // CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 8984 // CHECK13-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP5]] to double 8985 // CHECK13-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 8986 // CHECK13-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 8987 // CHECK13-NEXT: store double [[ADD2]], double* [[A]], align 8 8988 // CHECK13-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 8989 // CHECK13-NEXT: [[TMP6:%.*]] = load double, double* [[A3]], align 8 8990 // CHECK13-NEXT: [[INC:%.*]] = fadd double [[TMP6]], 1.000000e+00 8991 // CHECK13-NEXT: store double [[INC]], double* [[A3]], align 8 8992 // CHECK13-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 8993 // CHECK13-NEXT: [[TMP7:%.*]] = mul nsw i64 1, [[TMP2]] 8994 // CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP7]] 8995 // CHECK13-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 8996 // CHECK13-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 8997 // CHECK13-NEXT: [[TMP8:%.*]] = mul nsw i64 1, [[TMP2]] 8998 // CHECK13-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP8]] 8999 // CHECK13-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i64 1 9000 // CHECK13-NEXT: [[TMP9:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2 9001 // CHECK13-NEXT: [[CONV8:%.*]] = sext i16 [[TMP9]] to i32 9002 // CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[B]], align 4 9003 // CHECK13-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP10]] 9004 // CHECK13-NEXT: [[TMP11:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 9005 // CHECK13-NEXT: call void @llvm.stackrestore(i8* [[TMP11]]) 9006 // CHECK13-NEXT: ret i32 [[ADD9]] 9007 // 9008 // 9009 // CHECK13-LABEL: define {{[^@]+}}@_ZL7fstatici 9010 // CHECK13-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { 9011 // CHECK13-NEXT: entry: 9012 // CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 9013 // CHECK13-NEXT: [[A:%.*]] = alloca i32, align 4 9014 // CHECK13-NEXT: [[AA:%.*]] = alloca i16, align 2 9015 // CHECK13-NEXT: [[AAA:%.*]] = alloca i8, align 1 9016 // CHECK13-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 9017 // CHECK13-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 9018 // CHECK13-NEXT: store i32 0, i32* [[A]], align 4 9019 // CHECK13-NEXT: store i16 0, i16* [[AA]], align 2 9020 // CHECK13-NEXT: store i8 0, i8* [[AAA]], align 1 9021 // CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 9022 // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 9023 // CHECK13-NEXT: store i32 [[ADD]], i32* [[A]], align 4 9024 // CHECK13-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 9025 // CHECK13-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 9026 // CHECK13-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 9027 // CHECK13-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 9028 // CHECK13-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 9029 // CHECK13-NEXT: [[TMP2:%.*]] = load i8, i8* [[AAA]], align 1 9030 // CHECK13-NEXT: [[CONV3:%.*]] = sext i8 [[TMP2]] to i32 9031 // CHECK13-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 9032 // CHECK13-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 9033 // CHECK13-NEXT: store i8 [[CONV5]], i8* [[AAA]], align 1 9034 // CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 9035 // CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 9036 // CHECK13-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP3]], 1 9037 // CHECK13-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 9038 // CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 9039 // CHECK13-NEXT: ret i32 [[TMP4]] 9040 // 9041 // 9042 // CHECK13-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 9043 // CHECK13-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { 9044 // CHECK13-NEXT: entry: 9045 // CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 9046 // CHECK13-NEXT: [[A:%.*]] = alloca i32, align 4 9047 // CHECK13-NEXT: [[AA:%.*]] = alloca i16, align 2 9048 // CHECK13-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 9049 // CHECK13-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 9050 // CHECK13-NEXT: store i32 0, i32* [[A]], align 4 9051 // CHECK13-NEXT: store i16 0, i16* [[AA]], align 2 9052 // CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 9053 // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 9054 // CHECK13-NEXT: store i32 [[ADD]], i32* [[A]], align 4 9055 // CHECK13-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 9056 // CHECK13-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 9057 // CHECK13-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 9058 // CHECK13-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 9059 // CHECK13-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 9060 // CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 9061 // CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 9062 // CHECK13-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP2]], 1 9063 // CHECK13-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 9064 // CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 9065 // CHECK13-NEXT: ret i32 [[TMP3]] 9066 // 9067 // 9068 // CHECK14-LABEL: define {{[^@]+}}@_Z3fooi 9069 // CHECK14-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { 9070 // CHECK14-NEXT: entry: 9071 // CHECK14-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 9072 // CHECK14-NEXT: [[A:%.*]] = alloca i32, align 4 9073 // CHECK14-NEXT: [[AA:%.*]] = alloca i16, align 2 9074 // CHECK14-NEXT: [[B:%.*]] = alloca [10 x float], align 4 9075 // CHECK14-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 9076 // CHECK14-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 9077 // CHECK14-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 9078 // CHECK14-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 9079 // CHECK14-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 9080 // CHECK14-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 9081 // CHECK14-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 9082 // CHECK14-NEXT: [[NN:%.*]] = alloca i32, align 4 9083 // CHECK14-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 9084 // CHECK14-NEXT: store i32 0, i32* [[A]], align 4 9085 // CHECK14-NEXT: store i16 0, i16* [[AA]], align 2 9086 // CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 9087 // CHECK14-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 9088 // CHECK14-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() 9089 // CHECK14-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 9090 // CHECK14-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4 9091 // CHECK14-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 9092 // CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 9093 // CHECK14-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64 9094 // CHECK14-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]] 9095 // CHECK14-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8 9096 // CHECK14-NEXT: store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8 9097 // CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 9098 // CHECK14-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_]], align 4 9099 // CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 9100 // CHECK14-NEXT: store i32 [[TMP7]], i32* [[DOTCAPTURE_EXPR_2]], align 4 9101 // CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 9102 // CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 9103 // CHECK14-NEXT: store i32 [[ADD]], i32* [[A]], align 4 9104 // CHECK14-NEXT: [[TMP9:%.*]] = load i16, i16* [[AA]], align 2 9105 // CHECK14-NEXT: [[CONV:%.*]] = sext i16 [[TMP9]] to i32 9106 // CHECK14-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1 9107 // CHECK14-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 9108 // CHECK14-NEXT: store i16 [[CONV4]], i16* [[AA]], align 2 9109 // CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[A]], align 4 9110 // CHECK14-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP10]], 1 9111 // CHECK14-NEXT: store i32 [[ADD5]], i32* [[A]], align 4 9112 // CHECK14-NEXT: [[TMP11:%.*]] = load i16, i16* [[AA]], align 2 9113 // CHECK14-NEXT: [[CONV6:%.*]] = sext i16 [[TMP11]] to i32 9114 // CHECK14-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 9115 // CHECK14-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i16 9116 // CHECK14-NEXT: store i16 [[CONV8]], i16* [[AA]], align 2 9117 // CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[A]], align 4 9118 // CHECK14-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP12]], 1 9119 // CHECK14-NEXT: store i32 [[ADD9]], i32* [[A]], align 4 9120 // CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2 9121 // CHECK14-NEXT: [[TMP13:%.*]] = load float, float* [[ARRAYIDX]], align 4 9122 // CHECK14-NEXT: [[CONV10:%.*]] = fpext float [[TMP13]] to double 9123 // CHECK14-NEXT: [[ADD11:%.*]] = fadd double [[CONV10]], 1.000000e+00 9124 // CHECK14-NEXT: [[CONV12:%.*]] = fptrunc double [[ADD11]] to float 9125 // CHECK14-NEXT: store float [[CONV12]], float* [[ARRAYIDX]], align 4 9126 // CHECK14-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3 9127 // CHECK14-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX13]], align 4 9128 // CHECK14-NEXT: [[CONV14:%.*]] = fpext float [[TMP14]] to double 9129 // CHECK14-NEXT: [[ADD15:%.*]] = fadd double [[CONV14]], 1.000000e+00 9130 // CHECK14-NEXT: [[CONV16:%.*]] = fptrunc double [[ADD15]] to float 9131 // CHECK14-NEXT: store float [[CONV16]], float* [[ARRAYIDX13]], align 4 9132 // CHECK14-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1 9133 // CHECK14-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX17]], i64 0, i64 2 9134 // CHECK14-NEXT: [[TMP15:%.*]] = load double, double* [[ARRAYIDX18]], align 8 9135 // CHECK14-NEXT: [[ADD19:%.*]] = fadd double [[TMP15]], 1.000000e+00 9136 // CHECK14-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8 9137 // CHECK14-NEXT: [[TMP16:%.*]] = mul nsw i64 1, [[TMP4]] 9138 // CHECK14-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP16]] 9139 // CHECK14-NEXT: [[ARRAYIDX21:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX20]], i64 3 9140 // CHECK14-NEXT: [[TMP17:%.*]] = load double, double* [[ARRAYIDX21]], align 8 9141 // CHECK14-NEXT: [[ADD22:%.*]] = fadd double [[TMP17]], 1.000000e+00 9142 // CHECK14-NEXT: store double [[ADD22]], double* [[ARRAYIDX21]], align 8 9143 // CHECK14-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 9144 // CHECK14-NEXT: [[TMP18:%.*]] = load i64, i64* [[X]], align 8 9145 // CHECK14-NEXT: [[ADD23:%.*]] = add nsw i64 [[TMP18]], 1 9146 // CHECK14-NEXT: store i64 [[ADD23]], i64* [[X]], align 8 9147 // CHECK14-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 9148 // CHECK14-NEXT: [[TMP19:%.*]] = load i8, i8* [[Y]], align 8 9149 // CHECK14-NEXT: [[CONV24:%.*]] = sext i8 [[TMP19]] to i32 9150 // CHECK14-NEXT: [[ADD25:%.*]] = add nsw i32 [[CONV24]], 1 9151 // CHECK14-NEXT: [[CONV26:%.*]] = trunc i32 [[ADD25]] to i8 9152 // CHECK14-NEXT: store i8 [[CONV26]], i8* [[Y]], align 8 9153 // CHECK14-NEXT: store i32 0, i32* [[NN]], align 4 9154 // CHECK14-NEXT: [[TMP20:%.*]] = load i32, i32* [[A]], align 4 9155 // CHECK14-NEXT: [[TMP21:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 9156 // CHECK14-NEXT: call void @llvm.stackrestore(i8* [[TMP21]]) 9157 // CHECK14-NEXT: ret i32 [[TMP20]] 9158 // 9159 // 9160 // CHECK14-LABEL: define {{[^@]+}}@_Z6bazzzziPi 9161 // CHECK14-SAME: (i32 signext [[N:%.*]], i32* [[F:%.*]]) #[[ATTR0]] { 9162 // CHECK14-NEXT: entry: 9163 // CHECK14-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 9164 // CHECK14-NEXT: [[F_ADDR:%.*]] = alloca i32*, align 8 9165 // CHECK14-NEXT: [[F1:%.*]] = alloca i32*, align 8 9166 // CHECK14-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 9167 // CHECK14-NEXT: store i32* [[F]], i32** [[F_ADDR]], align 8 9168 // CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 9169 // CHECK14-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 9170 // CHECK14-NEXT: ret void 9171 // 9172 // 9173 // CHECK14-LABEL: define {{[^@]+}}@_Z3bari 9174 // CHECK14-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { 9175 // CHECK14-NEXT: entry: 9176 // CHECK14-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 9177 // CHECK14-NEXT: [[A:%.*]] = alloca i32, align 4 9178 // CHECK14-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 9179 // CHECK14-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 9180 // CHECK14-NEXT: store i32 0, i32* [[A]], align 4 9181 // CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 9182 // CHECK14-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]]) 9183 // CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 9184 // CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 9185 // CHECK14-NEXT: store i32 [[ADD]], i32* [[A]], align 4 9186 // CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 9187 // CHECK14-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]]) 9188 // CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 9189 // CHECK14-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 9190 // CHECK14-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 9191 // CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 9192 // CHECK14-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]]) 9193 // CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 9194 // CHECK14-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 9195 // CHECK14-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 9196 // CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 9197 // CHECK14-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]]) 9198 // CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 9199 // CHECK14-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] 9200 // CHECK14-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 9201 // CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 9202 // CHECK14-NEXT: ret i32 [[TMP8]] 9203 // 9204 // 9205 // CHECK14-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 9206 // CHECK14-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { 9207 // CHECK14-NEXT: entry: 9208 // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 9209 // CHECK14-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 9210 // CHECK14-NEXT: [[B:%.*]] = alloca i32, align 4 9211 // CHECK14-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 9212 // CHECK14-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 9213 // CHECK14-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 9214 // CHECK14-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 9215 // CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 9216 // CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 9217 // CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 9218 // CHECK14-NEXT: store i32 [[ADD]], i32* [[B]], align 4 9219 // CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 9220 // CHECK14-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 9221 // CHECK14-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() 9222 // CHECK14-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 9223 // CHECK14-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] 9224 // CHECK14-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 9225 // CHECK14-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 9226 // CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 9227 // CHECK14-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP5]] to double 9228 // CHECK14-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 9229 // CHECK14-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 9230 // CHECK14-NEXT: store double [[ADD2]], double* [[A]], align 8 9231 // CHECK14-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 9232 // CHECK14-NEXT: [[TMP6:%.*]] = load double, double* [[A3]], align 8 9233 // CHECK14-NEXT: [[INC:%.*]] = fadd double [[TMP6]], 1.000000e+00 9234 // CHECK14-NEXT: store double [[INC]], double* [[A3]], align 8 9235 // CHECK14-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 9236 // CHECK14-NEXT: [[TMP7:%.*]] = mul nsw i64 1, [[TMP2]] 9237 // CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP7]] 9238 // CHECK14-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 9239 // CHECK14-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 9240 // CHECK14-NEXT: [[TMP8:%.*]] = mul nsw i64 1, [[TMP2]] 9241 // CHECK14-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP8]] 9242 // CHECK14-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i64 1 9243 // CHECK14-NEXT: [[TMP9:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2 9244 // CHECK14-NEXT: [[CONV8:%.*]] = sext i16 [[TMP9]] to i32 9245 // CHECK14-NEXT: [[TMP10:%.*]] = load i32, i32* [[B]], align 4 9246 // CHECK14-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP10]] 9247 // CHECK14-NEXT: [[TMP11:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 9248 // CHECK14-NEXT: call void @llvm.stackrestore(i8* [[TMP11]]) 9249 // CHECK14-NEXT: ret i32 [[ADD9]] 9250 // 9251 // 9252 // CHECK14-LABEL: define {{[^@]+}}@_ZL7fstatici 9253 // CHECK14-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { 9254 // CHECK14-NEXT: entry: 9255 // CHECK14-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 9256 // CHECK14-NEXT: [[A:%.*]] = alloca i32, align 4 9257 // CHECK14-NEXT: [[AA:%.*]] = alloca i16, align 2 9258 // CHECK14-NEXT: [[AAA:%.*]] = alloca i8, align 1 9259 // CHECK14-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 9260 // CHECK14-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 9261 // CHECK14-NEXT: store i32 0, i32* [[A]], align 4 9262 // CHECK14-NEXT: store i16 0, i16* [[AA]], align 2 9263 // CHECK14-NEXT: store i8 0, i8* [[AAA]], align 1 9264 // CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 9265 // CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 9266 // CHECK14-NEXT: store i32 [[ADD]], i32* [[A]], align 4 9267 // CHECK14-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 9268 // CHECK14-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 9269 // CHECK14-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 9270 // CHECK14-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 9271 // CHECK14-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 9272 // CHECK14-NEXT: [[TMP2:%.*]] = load i8, i8* [[AAA]], align 1 9273 // CHECK14-NEXT: [[CONV3:%.*]] = sext i8 [[TMP2]] to i32 9274 // CHECK14-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 9275 // CHECK14-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 9276 // CHECK14-NEXT: store i8 [[CONV5]], i8* [[AAA]], align 1 9277 // CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 9278 // CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 9279 // CHECK14-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP3]], 1 9280 // CHECK14-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 9281 // CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 9282 // CHECK14-NEXT: ret i32 [[TMP4]] 9283 // 9284 // 9285 // CHECK14-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 9286 // CHECK14-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { 9287 // CHECK14-NEXT: entry: 9288 // CHECK14-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 9289 // CHECK14-NEXT: [[A:%.*]] = alloca i32, align 4 9290 // CHECK14-NEXT: [[AA:%.*]] = alloca i16, align 2 9291 // CHECK14-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 9292 // CHECK14-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 9293 // CHECK14-NEXT: store i32 0, i32* [[A]], align 4 9294 // CHECK14-NEXT: store i16 0, i16* [[AA]], align 2 9295 // CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 9296 // CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 9297 // CHECK14-NEXT: store i32 [[ADD]], i32* [[A]], align 4 9298 // CHECK14-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 9299 // CHECK14-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 9300 // CHECK14-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 9301 // CHECK14-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 9302 // CHECK14-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 9303 // CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 9304 // CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 9305 // CHECK14-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP2]], 1 9306 // CHECK14-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 9307 // CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 9308 // CHECK14-NEXT: ret i32 [[TMP3]] 9309 // 9310 // 9311 // CHECK15-LABEL: define {{[^@]+}}@_Z3fooi 9312 // CHECK15-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { 9313 // CHECK15-NEXT: entry: 9314 // CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 9315 // CHECK15-NEXT: [[A:%.*]] = alloca i32, align 4 9316 // CHECK15-NEXT: [[AA:%.*]] = alloca i16, align 2 9317 // CHECK15-NEXT: [[B:%.*]] = alloca [10 x float], align 4 9318 // CHECK15-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 9319 // CHECK15-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 9320 // CHECK15-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 9321 // CHECK15-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 9322 // CHECK15-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 9323 // CHECK15-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 9324 // CHECK15-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 9325 // CHECK15-NEXT: [[NN:%.*]] = alloca i32, align 4 9326 // CHECK15-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 9327 // CHECK15-NEXT: store i32 0, i32* [[A]], align 4 9328 // CHECK15-NEXT: store i16 0, i16* [[AA]], align 2 9329 // CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 9330 // CHECK15-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() 9331 // CHECK15-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 9332 // CHECK15-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4 9333 // CHECK15-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 9334 // CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 9335 // CHECK15-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]] 9336 // CHECK15-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8 9337 // CHECK15-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4 9338 // CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 9339 // CHECK15-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 9340 // CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 9341 // CHECK15-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_2]], align 4 9342 // CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 9343 // CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], 1 9344 // CHECK15-NEXT: store i32 [[ADD]], i32* [[A]], align 4 9345 // CHECK15-NEXT: [[TMP7:%.*]] = load i16, i16* [[AA]], align 2 9346 // CHECK15-NEXT: [[CONV:%.*]] = sext i16 [[TMP7]] to i32 9347 // CHECK15-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1 9348 // CHECK15-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 9349 // CHECK15-NEXT: store i16 [[CONV4]], i16* [[AA]], align 2 9350 // CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 9351 // CHECK15-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP8]], 1 9352 // CHECK15-NEXT: store i32 [[ADD5]], i32* [[A]], align 4 9353 // CHECK15-NEXT: [[TMP9:%.*]] = load i16, i16* [[AA]], align 2 9354 // CHECK15-NEXT: [[CONV6:%.*]] = sext i16 [[TMP9]] to i32 9355 // CHECK15-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 9356 // CHECK15-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i16 9357 // CHECK15-NEXT: store i16 [[CONV8]], i16* [[AA]], align 2 9358 // CHECK15-NEXT: [[TMP10:%.*]] = load i32, i32* [[A]], align 4 9359 // CHECK15-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP10]], 1 9360 // CHECK15-NEXT: store i32 [[ADD9]], i32* [[A]], align 4 9361 // CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2 9362 // CHECK15-NEXT: [[TMP11:%.*]] = load float, float* [[ARRAYIDX]], align 4 9363 // CHECK15-NEXT: [[CONV10:%.*]] = fpext float [[TMP11]] to double 9364 // CHECK15-NEXT: [[ADD11:%.*]] = fadd double [[CONV10]], 1.000000e+00 9365 // CHECK15-NEXT: [[CONV12:%.*]] = fptrunc double [[ADD11]] to float 9366 // CHECK15-NEXT: store float [[CONV12]], float* [[ARRAYIDX]], align 4 9367 // CHECK15-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3 9368 // CHECK15-NEXT: [[TMP12:%.*]] = load float, float* [[ARRAYIDX13]], align 4 9369 // CHECK15-NEXT: [[CONV14:%.*]] = fpext float [[TMP12]] to double 9370 // CHECK15-NEXT: [[ADD15:%.*]] = fadd double [[CONV14]], 1.000000e+00 9371 // CHECK15-NEXT: [[CONV16:%.*]] = fptrunc double [[ADD15]] to float 9372 // CHECK15-NEXT: store float [[CONV16]], float* [[ARRAYIDX13]], align 4 9373 // CHECK15-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1 9374 // CHECK15-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX17]], i32 0, i32 2 9375 // CHECK15-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX18]], align 8 9376 // CHECK15-NEXT: [[ADD19:%.*]] = fadd double [[TMP13]], 1.000000e+00 9377 // CHECK15-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8 9378 // CHECK15-NEXT: [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]] 9379 // CHECK15-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP14]] 9380 // CHECK15-NEXT: [[ARRAYIDX21:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX20]], i32 3 9381 // CHECK15-NEXT: [[TMP15:%.*]] = load double, double* [[ARRAYIDX21]], align 8 9382 // CHECK15-NEXT: [[ADD22:%.*]] = fadd double [[TMP15]], 1.000000e+00 9383 // CHECK15-NEXT: store double [[ADD22]], double* [[ARRAYIDX21]], align 8 9384 // CHECK15-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 9385 // CHECK15-NEXT: [[TMP16:%.*]] = load i64, i64* [[X]], align 4 9386 // CHECK15-NEXT: [[ADD23:%.*]] = add nsw i64 [[TMP16]], 1 9387 // CHECK15-NEXT: store i64 [[ADD23]], i64* [[X]], align 4 9388 // CHECK15-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 9389 // CHECK15-NEXT: [[TMP17:%.*]] = load i8, i8* [[Y]], align 4 9390 // CHECK15-NEXT: [[CONV24:%.*]] = sext i8 [[TMP17]] to i32 9391 // CHECK15-NEXT: [[ADD25:%.*]] = add nsw i32 [[CONV24]], 1 9392 // CHECK15-NEXT: [[CONV26:%.*]] = trunc i32 [[ADD25]] to i8 9393 // CHECK15-NEXT: store i8 [[CONV26]], i8* [[Y]], align 4 9394 // CHECK15-NEXT: store i32 0, i32* [[NN]], align 4 9395 // CHECK15-NEXT: [[TMP18:%.*]] = load i32, i32* [[A]], align 4 9396 // CHECK15-NEXT: [[TMP19:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 9397 // CHECK15-NEXT: call void @llvm.stackrestore(i8* [[TMP19]]) 9398 // CHECK15-NEXT: ret i32 [[TMP18]] 9399 // 9400 // 9401 // CHECK15-LABEL: define {{[^@]+}}@_Z6bazzzziPi 9402 // CHECK15-SAME: (i32 [[N:%.*]], i32* [[F:%.*]]) #[[ATTR0]] { 9403 // CHECK15-NEXT: entry: 9404 // CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 9405 // CHECK15-NEXT: [[F_ADDR:%.*]] = alloca i32*, align 4 9406 // CHECK15-NEXT: [[F1:%.*]] = alloca i32*, align 4 9407 // CHECK15-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 9408 // CHECK15-NEXT: store i32* [[F]], i32** [[F_ADDR]], align 4 9409 // CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 9410 // CHECK15-NEXT: ret void 9411 // 9412 // 9413 // CHECK15-LABEL: define {{[^@]+}}@_Z3bari 9414 // CHECK15-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { 9415 // CHECK15-NEXT: entry: 9416 // CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 9417 // CHECK15-NEXT: [[A:%.*]] = alloca i32, align 4 9418 // CHECK15-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 9419 // CHECK15-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 9420 // CHECK15-NEXT: store i32 0, i32* [[A]], align 4 9421 // CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 9422 // CHECK15-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]]) 9423 // CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 9424 // CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 9425 // CHECK15-NEXT: store i32 [[ADD]], i32* [[A]], align 4 9426 // CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 9427 // CHECK15-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]]) 9428 // CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 9429 // CHECK15-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 9430 // CHECK15-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 9431 // CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 9432 // CHECK15-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]]) 9433 // CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 9434 // CHECK15-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 9435 // CHECK15-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 9436 // CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 9437 // CHECK15-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]]) 9438 // CHECK15-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 9439 // CHECK15-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] 9440 // CHECK15-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 9441 // CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 9442 // CHECK15-NEXT: ret i32 [[TMP8]] 9443 // 9444 // 9445 // CHECK15-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 9446 // CHECK15-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { 9447 // CHECK15-NEXT: entry: 9448 // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 9449 // CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 9450 // CHECK15-NEXT: [[B:%.*]] = alloca i32, align 4 9451 // CHECK15-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 9452 // CHECK15-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 9453 // CHECK15-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 9454 // CHECK15-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 9455 // CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 9456 // CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 9457 // CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 9458 // CHECK15-NEXT: store i32 [[ADD]], i32* [[B]], align 4 9459 // CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 9460 // CHECK15-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() 9461 // CHECK15-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 9462 // CHECK15-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] 9463 // CHECK15-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 9464 // CHECK15-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 9465 // CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[B]], align 4 9466 // CHECK15-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP4]] to double 9467 // CHECK15-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 9468 // CHECK15-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 9469 // CHECK15-NEXT: store double [[ADD2]], double* [[A]], align 4 9470 // CHECK15-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 9471 // CHECK15-NEXT: [[TMP5:%.*]] = load double, double* [[A3]], align 4 9472 // CHECK15-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 9473 // CHECK15-NEXT: store double [[INC]], double* [[A3]], align 4 9474 // CHECK15-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 9475 // CHECK15-NEXT: [[TMP6:%.*]] = mul nsw i32 1, [[TMP1]] 9476 // CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP6]] 9477 // CHECK15-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 9478 // CHECK15-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 9479 // CHECK15-NEXT: [[TMP7:%.*]] = mul nsw i32 1, [[TMP1]] 9480 // CHECK15-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP7]] 9481 // CHECK15-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i32 1 9482 // CHECK15-NEXT: [[TMP8:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2 9483 // CHECK15-NEXT: [[CONV8:%.*]] = sext i16 [[TMP8]] to i32 9484 // CHECK15-NEXT: [[TMP9:%.*]] = load i32, i32* [[B]], align 4 9485 // CHECK15-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP9]] 9486 // CHECK15-NEXT: [[TMP10:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 9487 // CHECK15-NEXT: call void @llvm.stackrestore(i8* [[TMP10]]) 9488 // CHECK15-NEXT: ret i32 [[ADD9]] 9489 // 9490 // 9491 // CHECK15-LABEL: define {{[^@]+}}@_ZL7fstatici 9492 // CHECK15-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { 9493 // CHECK15-NEXT: entry: 9494 // CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 9495 // CHECK15-NEXT: [[A:%.*]] = alloca i32, align 4 9496 // CHECK15-NEXT: [[AA:%.*]] = alloca i16, align 2 9497 // CHECK15-NEXT: [[AAA:%.*]] = alloca i8, align 1 9498 // CHECK15-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 9499 // CHECK15-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 9500 // CHECK15-NEXT: store i32 0, i32* [[A]], align 4 9501 // CHECK15-NEXT: store i16 0, i16* [[AA]], align 2 9502 // CHECK15-NEXT: store i8 0, i8* [[AAA]], align 1 9503 // CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 9504 // CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 9505 // CHECK15-NEXT: store i32 [[ADD]], i32* [[A]], align 4 9506 // CHECK15-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 9507 // CHECK15-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 9508 // CHECK15-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 9509 // CHECK15-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 9510 // CHECK15-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 9511 // CHECK15-NEXT: [[TMP2:%.*]] = load i8, i8* [[AAA]], align 1 9512 // CHECK15-NEXT: [[CONV3:%.*]] = sext i8 [[TMP2]] to i32 9513 // CHECK15-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 9514 // CHECK15-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 9515 // CHECK15-NEXT: store i8 [[CONV5]], i8* [[AAA]], align 1 9516 // CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 9517 // CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 9518 // CHECK15-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP3]], 1 9519 // CHECK15-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 9520 // CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 9521 // CHECK15-NEXT: ret i32 [[TMP4]] 9522 // 9523 // 9524 // CHECK15-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 9525 // CHECK15-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { 9526 // CHECK15-NEXT: entry: 9527 // CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 9528 // CHECK15-NEXT: [[A:%.*]] = alloca i32, align 4 9529 // CHECK15-NEXT: [[AA:%.*]] = alloca i16, align 2 9530 // CHECK15-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 9531 // CHECK15-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 9532 // CHECK15-NEXT: store i32 0, i32* [[A]], align 4 9533 // CHECK15-NEXT: store i16 0, i16* [[AA]], align 2 9534 // CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 9535 // CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 9536 // CHECK15-NEXT: store i32 [[ADD]], i32* [[A]], align 4 9537 // CHECK15-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 9538 // CHECK15-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 9539 // CHECK15-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 9540 // CHECK15-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 9541 // CHECK15-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 9542 // CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 9543 // CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 9544 // CHECK15-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP2]], 1 9545 // CHECK15-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 9546 // CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 9547 // CHECK15-NEXT: ret i32 [[TMP3]] 9548 // 9549 // 9550 // CHECK16-LABEL: define {{[^@]+}}@_Z3fooi 9551 // CHECK16-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { 9552 // CHECK16-NEXT: entry: 9553 // CHECK16-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 9554 // CHECK16-NEXT: [[A:%.*]] = alloca i32, align 4 9555 // CHECK16-NEXT: [[AA:%.*]] = alloca i16, align 2 9556 // CHECK16-NEXT: [[B:%.*]] = alloca [10 x float], align 4 9557 // CHECK16-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 9558 // CHECK16-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 9559 // CHECK16-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 9560 // CHECK16-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 9561 // CHECK16-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 9562 // CHECK16-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 9563 // CHECK16-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 9564 // CHECK16-NEXT: [[NN:%.*]] = alloca i32, align 4 9565 // CHECK16-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 9566 // CHECK16-NEXT: store i32 0, i32* [[A]], align 4 9567 // CHECK16-NEXT: store i16 0, i16* [[AA]], align 2 9568 // CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 9569 // CHECK16-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() 9570 // CHECK16-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 9571 // CHECK16-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4 9572 // CHECK16-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 9573 // CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 9574 // CHECK16-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]] 9575 // CHECK16-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8 9576 // CHECK16-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4 9577 // CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 9578 // CHECK16-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 9579 // CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 9580 // CHECK16-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_2]], align 4 9581 // CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 9582 // CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], 1 9583 // CHECK16-NEXT: store i32 [[ADD]], i32* [[A]], align 4 9584 // CHECK16-NEXT: [[TMP7:%.*]] = load i16, i16* [[AA]], align 2 9585 // CHECK16-NEXT: [[CONV:%.*]] = sext i16 [[TMP7]] to i32 9586 // CHECK16-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1 9587 // CHECK16-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 9588 // CHECK16-NEXT: store i16 [[CONV4]], i16* [[AA]], align 2 9589 // CHECK16-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 9590 // CHECK16-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP8]], 1 9591 // CHECK16-NEXT: store i32 [[ADD5]], i32* [[A]], align 4 9592 // CHECK16-NEXT: [[TMP9:%.*]] = load i16, i16* [[AA]], align 2 9593 // CHECK16-NEXT: [[CONV6:%.*]] = sext i16 [[TMP9]] to i32 9594 // CHECK16-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 9595 // CHECK16-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i16 9596 // CHECK16-NEXT: store i16 [[CONV8]], i16* [[AA]], align 2 9597 // CHECK16-NEXT: [[TMP10:%.*]] = load i32, i32* [[A]], align 4 9598 // CHECK16-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP10]], 1 9599 // CHECK16-NEXT: store i32 [[ADD9]], i32* [[A]], align 4 9600 // CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2 9601 // CHECK16-NEXT: [[TMP11:%.*]] = load float, float* [[ARRAYIDX]], align 4 9602 // CHECK16-NEXT: [[CONV10:%.*]] = fpext float [[TMP11]] to double 9603 // CHECK16-NEXT: [[ADD11:%.*]] = fadd double [[CONV10]], 1.000000e+00 9604 // CHECK16-NEXT: [[CONV12:%.*]] = fptrunc double [[ADD11]] to float 9605 // CHECK16-NEXT: store float [[CONV12]], float* [[ARRAYIDX]], align 4 9606 // CHECK16-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3 9607 // CHECK16-NEXT: [[TMP12:%.*]] = load float, float* [[ARRAYIDX13]], align 4 9608 // CHECK16-NEXT: [[CONV14:%.*]] = fpext float [[TMP12]] to double 9609 // CHECK16-NEXT: [[ADD15:%.*]] = fadd double [[CONV14]], 1.000000e+00 9610 // CHECK16-NEXT: [[CONV16:%.*]] = fptrunc double [[ADD15]] to float 9611 // CHECK16-NEXT: store float [[CONV16]], float* [[ARRAYIDX13]], align 4 9612 // CHECK16-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1 9613 // CHECK16-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX17]], i32 0, i32 2 9614 // CHECK16-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX18]], align 8 9615 // CHECK16-NEXT: [[ADD19:%.*]] = fadd double [[TMP13]], 1.000000e+00 9616 // CHECK16-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8 9617 // CHECK16-NEXT: [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]] 9618 // CHECK16-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP14]] 9619 // CHECK16-NEXT: [[ARRAYIDX21:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX20]], i32 3 9620 // CHECK16-NEXT: [[TMP15:%.*]] = load double, double* [[ARRAYIDX21]], align 8 9621 // CHECK16-NEXT: [[ADD22:%.*]] = fadd double [[TMP15]], 1.000000e+00 9622 // CHECK16-NEXT: store double [[ADD22]], double* [[ARRAYIDX21]], align 8 9623 // CHECK16-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 9624 // CHECK16-NEXT: [[TMP16:%.*]] = load i64, i64* [[X]], align 4 9625 // CHECK16-NEXT: [[ADD23:%.*]] = add nsw i64 [[TMP16]], 1 9626 // CHECK16-NEXT: store i64 [[ADD23]], i64* [[X]], align 4 9627 // CHECK16-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 9628 // CHECK16-NEXT: [[TMP17:%.*]] = load i8, i8* [[Y]], align 4 9629 // CHECK16-NEXT: [[CONV24:%.*]] = sext i8 [[TMP17]] to i32 9630 // CHECK16-NEXT: [[ADD25:%.*]] = add nsw i32 [[CONV24]], 1 9631 // CHECK16-NEXT: [[CONV26:%.*]] = trunc i32 [[ADD25]] to i8 9632 // CHECK16-NEXT: store i8 [[CONV26]], i8* [[Y]], align 4 9633 // CHECK16-NEXT: store i32 0, i32* [[NN]], align 4 9634 // CHECK16-NEXT: [[TMP18:%.*]] = load i32, i32* [[A]], align 4 9635 // CHECK16-NEXT: [[TMP19:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 9636 // CHECK16-NEXT: call void @llvm.stackrestore(i8* [[TMP19]]) 9637 // CHECK16-NEXT: ret i32 [[TMP18]] 9638 // 9639 // 9640 // CHECK16-LABEL: define {{[^@]+}}@_Z6bazzzziPi 9641 // CHECK16-SAME: (i32 [[N:%.*]], i32* [[F:%.*]]) #[[ATTR0]] { 9642 // CHECK16-NEXT: entry: 9643 // CHECK16-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 9644 // CHECK16-NEXT: [[F_ADDR:%.*]] = alloca i32*, align 4 9645 // CHECK16-NEXT: [[F1:%.*]] = alloca i32*, align 4 9646 // CHECK16-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 9647 // CHECK16-NEXT: store i32* [[F]], i32** [[F_ADDR]], align 4 9648 // CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 9649 // CHECK16-NEXT: ret void 9650 // 9651 // 9652 // CHECK16-LABEL: define {{[^@]+}}@_Z3bari 9653 // CHECK16-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { 9654 // CHECK16-NEXT: entry: 9655 // CHECK16-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 9656 // CHECK16-NEXT: [[A:%.*]] = alloca i32, align 4 9657 // CHECK16-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 9658 // CHECK16-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 9659 // CHECK16-NEXT: store i32 0, i32* [[A]], align 4 9660 // CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 9661 // CHECK16-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]]) 9662 // CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 9663 // CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 9664 // CHECK16-NEXT: store i32 [[ADD]], i32* [[A]], align 4 9665 // CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 9666 // CHECK16-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]]) 9667 // CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 9668 // CHECK16-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 9669 // CHECK16-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 9670 // CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 9671 // CHECK16-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]]) 9672 // CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 9673 // CHECK16-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 9674 // CHECK16-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 9675 // CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 9676 // CHECK16-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]]) 9677 // CHECK16-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 9678 // CHECK16-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] 9679 // CHECK16-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 9680 // CHECK16-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 9681 // CHECK16-NEXT: ret i32 [[TMP8]] 9682 // 9683 // 9684 // CHECK16-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 9685 // CHECK16-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { 9686 // CHECK16-NEXT: entry: 9687 // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 9688 // CHECK16-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 9689 // CHECK16-NEXT: [[B:%.*]] = alloca i32, align 4 9690 // CHECK16-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 9691 // CHECK16-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 9692 // CHECK16-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 9693 // CHECK16-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 9694 // CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 9695 // CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 9696 // CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 9697 // CHECK16-NEXT: store i32 [[ADD]], i32* [[B]], align 4 9698 // CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 9699 // CHECK16-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() 9700 // CHECK16-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 9701 // CHECK16-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] 9702 // CHECK16-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 9703 // CHECK16-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 9704 // CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[B]], align 4 9705 // CHECK16-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP4]] to double 9706 // CHECK16-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 9707 // CHECK16-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 9708 // CHECK16-NEXT: store double [[ADD2]], double* [[A]], align 4 9709 // CHECK16-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 9710 // CHECK16-NEXT: [[TMP5:%.*]] = load double, double* [[A3]], align 4 9711 // CHECK16-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 9712 // CHECK16-NEXT: store double [[INC]], double* [[A3]], align 4 9713 // CHECK16-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 9714 // CHECK16-NEXT: [[TMP6:%.*]] = mul nsw i32 1, [[TMP1]] 9715 // CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP6]] 9716 // CHECK16-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 9717 // CHECK16-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 9718 // CHECK16-NEXT: [[TMP7:%.*]] = mul nsw i32 1, [[TMP1]] 9719 // CHECK16-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP7]] 9720 // CHECK16-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i32 1 9721 // CHECK16-NEXT: [[TMP8:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2 9722 // CHECK16-NEXT: [[CONV8:%.*]] = sext i16 [[TMP8]] to i32 9723 // CHECK16-NEXT: [[TMP9:%.*]] = load i32, i32* [[B]], align 4 9724 // CHECK16-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP9]] 9725 // CHECK16-NEXT: [[TMP10:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 9726 // CHECK16-NEXT: call void @llvm.stackrestore(i8* [[TMP10]]) 9727 // CHECK16-NEXT: ret i32 [[ADD9]] 9728 // 9729 // 9730 // CHECK16-LABEL: define {{[^@]+}}@_ZL7fstatici 9731 // CHECK16-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { 9732 // CHECK16-NEXT: entry: 9733 // CHECK16-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 9734 // CHECK16-NEXT: [[A:%.*]] = alloca i32, align 4 9735 // CHECK16-NEXT: [[AA:%.*]] = alloca i16, align 2 9736 // CHECK16-NEXT: [[AAA:%.*]] = alloca i8, align 1 9737 // CHECK16-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 9738 // CHECK16-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 9739 // CHECK16-NEXT: store i32 0, i32* [[A]], align 4 9740 // CHECK16-NEXT: store i16 0, i16* [[AA]], align 2 9741 // CHECK16-NEXT: store i8 0, i8* [[AAA]], align 1 9742 // CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 9743 // CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 9744 // CHECK16-NEXT: store i32 [[ADD]], i32* [[A]], align 4 9745 // CHECK16-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 9746 // CHECK16-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 9747 // CHECK16-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 9748 // CHECK16-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 9749 // CHECK16-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 9750 // CHECK16-NEXT: [[TMP2:%.*]] = load i8, i8* [[AAA]], align 1 9751 // CHECK16-NEXT: [[CONV3:%.*]] = sext i8 [[TMP2]] to i32 9752 // CHECK16-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 9753 // CHECK16-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 9754 // CHECK16-NEXT: store i8 [[CONV5]], i8* [[AAA]], align 1 9755 // CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 9756 // CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 9757 // CHECK16-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP3]], 1 9758 // CHECK16-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 9759 // CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 9760 // CHECK16-NEXT: ret i32 [[TMP4]] 9761 // 9762 // 9763 // CHECK16-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 9764 // CHECK16-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { 9765 // CHECK16-NEXT: entry: 9766 // CHECK16-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 9767 // CHECK16-NEXT: [[A:%.*]] = alloca i32, align 4 9768 // CHECK16-NEXT: [[AA:%.*]] = alloca i16, align 2 9769 // CHECK16-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 9770 // CHECK16-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 9771 // CHECK16-NEXT: store i32 0, i32* [[A]], align 4 9772 // CHECK16-NEXT: store i16 0, i16* [[AA]], align 2 9773 // CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 9774 // CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 9775 // CHECK16-NEXT: store i32 [[ADD]], i32* [[A]], align 4 9776 // CHECK16-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 9777 // CHECK16-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 9778 // CHECK16-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 9779 // CHECK16-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 9780 // CHECK16-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 9781 // CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 9782 // CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 9783 // CHECK16-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP2]], 1 9784 // CHECK16-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 9785 // CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 9786 // CHECK16-NEXT: ret i32 [[TMP3]] 9787 // 9788 // 9789 // CHECK17-LABEL: define {{[^@]+}}@_Z3fooi 9790 // CHECK17-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { 9791 // CHECK17-NEXT: entry: 9792 // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 9793 // CHECK17-NEXT: [[A:%.*]] = alloca i32, align 4 9794 // CHECK17-NEXT: [[AA:%.*]] = alloca i16, align 2 9795 // CHECK17-NEXT: [[B:%.*]] = alloca [10 x float], align 4 9796 // CHECK17-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 9797 // CHECK17-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 9798 // CHECK17-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 9799 // CHECK17-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 9800 // CHECK17-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 9801 // CHECK17-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 9802 // CHECK17-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 9803 // CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 9804 // CHECK17-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 9805 // CHECK17-NEXT: [[DOTCAPTURE_EXPR__CASTED4:%.*]] = alloca i64, align 8 9806 // CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 9807 // CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 9808 // CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 9809 // CHECK17-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4 9810 // CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 9811 // CHECK17-NEXT: [[AA_CASTED7:%.*]] = alloca i64, align 8 9812 // CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS9:%.*]] = alloca [1 x i8*], align 8 9813 // CHECK17-NEXT: [[DOTOFFLOAD_PTRS10:%.*]] = alloca [1 x i8*], align 8 9814 // CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS11:%.*]] = alloca [1 x i8*], align 8 9815 // CHECK17-NEXT: [[A_CASTED12:%.*]] = alloca i64, align 8 9816 // CHECK17-NEXT: [[AA_CASTED14:%.*]] = alloca i64, align 8 9817 // CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS16:%.*]] = alloca [2 x i8*], align 8 9818 // CHECK17-NEXT: [[DOTOFFLOAD_PTRS17:%.*]] = alloca [2 x i8*], align 8 9819 // CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS18:%.*]] = alloca [2 x i8*], align 8 9820 // CHECK17-NEXT: [[A_CASTED21:%.*]] = alloca i64, align 8 9821 // CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS25:%.*]] = alloca [9 x i8*], align 8 9822 // CHECK17-NEXT: [[DOTOFFLOAD_PTRS26:%.*]] = alloca [9 x i8*], align 8 9823 // CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS27:%.*]] = alloca [9 x i8*], align 8 9824 // CHECK17-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [9 x i64], align 8 9825 // CHECK17-NEXT: [[NN:%.*]] = alloca i32, align 4 9826 // CHECK17-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 9827 // CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS33:%.*]] = alloca [1 x i8*], align 8 9828 // CHECK17-NEXT: [[DOTOFFLOAD_PTRS34:%.*]] = alloca [1 x i8*], align 8 9829 // CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS35:%.*]] = alloca [1 x i8*], align 8 9830 // CHECK17-NEXT: [[NN_CASTED38:%.*]] = alloca i64, align 8 9831 // CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS40:%.*]] = alloca [1 x i8*], align 8 9832 // CHECK17-NEXT: [[DOTOFFLOAD_PTRS41:%.*]] = alloca [1 x i8*], align 8 9833 // CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS42:%.*]] = alloca [1 x i8*], align 8 9834 // CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) 9835 // CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 9836 // CHECK17-NEXT: store i32 0, i32* [[A]], align 4 9837 // CHECK17-NEXT: store i16 0, i16* [[AA]], align 2 9838 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 9839 // CHECK17-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 9840 // CHECK17-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() 9841 // CHECK17-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 9842 // CHECK17-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP2]], align 4 9843 // CHECK17-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 9844 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 9845 // CHECK17-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64 9846 // CHECK17-NEXT: [[TMP6:%.*]] = mul nuw i64 5, [[TMP5]] 9847 // CHECK17-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP6]], align 8 9848 // CHECK17-NEXT: store i64 [[TMP5]], i64* [[__VLA_EXPR1]], align 8 9849 // CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 9850 // CHECK17-NEXT: store i32 [[TMP7]], i32* [[DOTCAPTURE_EXPR_]], align 4 9851 // CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 9852 // CHECK17-NEXT: store i32 [[TMP8]], i32* [[DOTCAPTURE_EXPR_2]], align 4 9853 // CHECK17-NEXT: [[TMP9:%.*]] = load i16, i16* [[AA]], align 2 9854 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 9855 // CHECK17-NEXT: store i16 [[TMP9]], i16* [[CONV]], align 2 9856 // CHECK17-NEXT: [[TMP10:%.*]] = load i64, i64* [[AA_CASTED]], align 8 9857 // CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 9858 // CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* 9859 // CHECK17-NEXT: store i32 [[TMP11]], i32* [[CONV3]], align 4 9860 // CHECK17-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 9861 // CHECK17-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 9862 // CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED4]] to i32* 9863 // CHECK17-NEXT: store i32 [[TMP13]], i32* [[CONV5]], align 4 9864 // CHECK17-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED4]], align 8 9865 // CHECK17-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 9866 // CHECK17-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i64* 9867 // CHECK17-NEXT: store i64 [[TMP10]], i64* [[TMP16]], align 8 9868 // CHECK17-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 9869 // CHECK17-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64* 9870 // CHECK17-NEXT: store i64 [[TMP10]], i64* [[TMP18]], align 8 9871 // CHECK17-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 9872 // CHECK17-NEXT: store i8* null, i8** [[TMP19]], align 8 9873 // CHECK17-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 9874 // CHECK17-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i64* 9875 // CHECK17-NEXT: store i64 [[TMP12]], i64* [[TMP21]], align 8 9876 // CHECK17-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 9877 // CHECK17-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i64* 9878 // CHECK17-NEXT: store i64 [[TMP12]], i64* [[TMP23]], align 8 9879 // CHECK17-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 9880 // CHECK17-NEXT: store i8* null, i8** [[TMP24]], align 8 9881 // CHECK17-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 9882 // CHECK17-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i64* 9883 // CHECK17-NEXT: store i64 [[TMP14]], i64* [[TMP26]], align 8 9884 // CHECK17-NEXT: [[TMP27:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 9885 // CHECK17-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i64* 9886 // CHECK17-NEXT: store i64 [[TMP14]], i64* [[TMP28]], align 8 9887 // CHECK17-NEXT: [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 9888 // CHECK17-NEXT: store i8* null, i8** [[TMP29]], align 8 9889 // CHECK17-NEXT: [[TMP30:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 9890 // CHECK17-NEXT: [[TMP31:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 9891 // CHECK17-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 0 9892 // CHECK17-NEXT: [[TMP33:%.*]] = load i16, i16* [[AA]], align 2 9893 // CHECK17-NEXT: store i16 [[TMP33]], i16* [[TMP32]], align 4 9894 // CHECK17-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 1 9895 // CHECK17-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 9896 // CHECK17-NEXT: store i32 [[TMP35]], i32* [[TMP34]], align 4 9897 // CHECK17-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 2 9898 // CHECK17-NEXT: [[TMP37:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 9899 // CHECK17-NEXT: store i32 [[TMP37]], i32* [[TMP36]], align 4 9900 // CHECK17-NEXT: [[TMP38:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i64 120, i64 12, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1) 9901 // CHECK17-NEXT: [[TMP39:%.*]] = bitcast i8* [[TMP38]] to %struct.kmp_task_t_with_privates* 9902 // CHECK17-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP39]], i32 0, i32 0 9903 // CHECK17-NEXT: [[TMP41:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP40]], i32 0, i32 0 9904 // CHECK17-NEXT: [[TMP42:%.*]] = load i8*, i8** [[TMP41]], align 8 9905 // CHECK17-NEXT: [[TMP43:%.*]] = bitcast %struct.anon* [[AGG_CAPTURED]] to i8* 9906 // CHECK17-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP42]], i8* align 4 [[TMP43]], i64 12, i1 false) 9907 // CHECK17-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP39]], i32 0, i32 1 9908 // CHECK17-NEXT: [[TMP45:%.*]] = bitcast i8* [[TMP42]] to %struct.anon* 9909 // CHECK17-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 0 9910 // CHECK17-NEXT: [[TMP47:%.*]] = bitcast [3 x i8*]* [[TMP46]] to i8* 9911 // CHECK17-NEXT: [[TMP48:%.*]] = bitcast i8** [[TMP30]] to i8* 9912 // CHECK17-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP47]], i8* align 8 [[TMP48]], i64 24, i1 false) 9913 // CHECK17-NEXT: [[TMP49:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 1 9914 // CHECK17-NEXT: [[TMP50:%.*]] = bitcast [3 x i8*]* [[TMP49]] to i8* 9915 // CHECK17-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP31]] to i8* 9916 // CHECK17-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP50]], i8* align 8 [[TMP51]], i64 24, i1 false) 9917 // CHECK17-NEXT: [[TMP52:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 2 9918 // CHECK17-NEXT: [[TMP53:%.*]] = bitcast [3 x i64]* [[TMP52]] to i8* 9919 // CHECK17-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP53]], i8* align 8 bitcast ([3 x i64]* @.offload_sizes to i8*), i64 24, i1 false) 9920 // CHECK17-NEXT: [[TMP54:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 3 9921 // CHECK17-NEXT: [[TMP55:%.*]] = load i16, i16* [[AA]], align 2 9922 // CHECK17-NEXT: store i16 [[TMP55]], i16* [[TMP54]], align 8 9923 // CHECK17-NEXT: [[TMP56:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP38]]) 9924 // CHECK17-NEXT: [[TMP57:%.*]] = load i32, i32* [[A]], align 4 9925 // CHECK17-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32* 9926 // CHECK17-NEXT: store i32 [[TMP57]], i32* [[CONV6]], align 4 9927 // CHECK17-NEXT: [[TMP58:%.*]] = load i64, i64* [[A_CASTED]], align 8 9928 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l105(i64 [[TMP58]]) #[[ATTR3:[0-9]+]] 9929 // CHECK17-NEXT: [[TMP59:%.*]] = load i16, i16* [[AA]], align 2 9930 // CHECK17-NEXT: [[CONV8:%.*]] = bitcast i64* [[AA_CASTED7]] to i16* 9931 // CHECK17-NEXT: store i16 [[TMP59]], i16* [[CONV8]], align 2 9932 // CHECK17-NEXT: [[TMP60:%.*]] = load i64, i64* [[AA_CASTED7]], align 8 9933 // CHECK17-NEXT: [[TMP61:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS9]], i32 0, i32 0 9934 // CHECK17-NEXT: [[TMP62:%.*]] = bitcast i8** [[TMP61]] to i64* 9935 // CHECK17-NEXT: store i64 [[TMP60]], i64* [[TMP62]], align 8 9936 // CHECK17-NEXT: [[TMP63:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS10]], i32 0, i32 0 9937 // CHECK17-NEXT: [[TMP64:%.*]] = bitcast i8** [[TMP63]] to i64* 9938 // CHECK17-NEXT: store i64 [[TMP60]], i64* [[TMP64]], align 8 9939 // CHECK17-NEXT: [[TMP65:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS11]], i64 0, i64 0 9940 // CHECK17-NEXT: store i8* null, i8** [[TMP65]], align 8 9941 // CHECK17-NEXT: [[TMP66:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS9]], i32 0, i32 0 9942 // CHECK17-NEXT: [[TMP67:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS10]], i32 0, i32 0 9943 // CHECK17-NEXT: [[TMP68:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.region_id, i32 1, i8** [[TMP66]], i8** [[TMP67]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.4, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.5, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 9944 // CHECK17-NEXT: [[TMP69:%.*]] = icmp ne i32 [[TMP68]], 0 9945 // CHECK17-NEXT: br i1 [[TMP69]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 9946 // CHECK17: omp_offload.failed: 9947 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111(i64 [[TMP60]]) #[[ATTR3]] 9948 // CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]] 9949 // CHECK17: omp_offload.cont: 9950 // CHECK17-NEXT: [[TMP70:%.*]] = load i32, i32* [[A]], align 4 9951 // CHECK17-NEXT: [[CONV13:%.*]] = bitcast i64* [[A_CASTED12]] to i32* 9952 // CHECK17-NEXT: store i32 [[TMP70]], i32* [[CONV13]], align 4 9953 // CHECK17-NEXT: [[TMP71:%.*]] = load i64, i64* [[A_CASTED12]], align 8 9954 // CHECK17-NEXT: [[TMP72:%.*]] = load i16, i16* [[AA]], align 2 9955 // CHECK17-NEXT: [[CONV15:%.*]] = bitcast i64* [[AA_CASTED14]] to i16* 9956 // CHECK17-NEXT: store i16 [[TMP72]], i16* [[CONV15]], align 2 9957 // CHECK17-NEXT: [[TMP73:%.*]] = load i64, i64* [[AA_CASTED14]], align 8 9958 // CHECK17-NEXT: [[TMP74:%.*]] = load i32, i32* [[N_ADDR]], align 4 9959 // CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP74]], 10 9960 // CHECK17-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 9961 // CHECK17: omp_if.then: 9962 // CHECK17-NEXT: [[TMP75:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 0 9963 // CHECK17-NEXT: [[TMP76:%.*]] = bitcast i8** [[TMP75]] to i64* 9964 // CHECK17-NEXT: store i64 [[TMP71]], i64* [[TMP76]], align 8 9965 // CHECK17-NEXT: [[TMP77:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 0 9966 // CHECK17-NEXT: [[TMP78:%.*]] = bitcast i8** [[TMP77]] to i64* 9967 // CHECK17-NEXT: store i64 [[TMP71]], i64* [[TMP78]], align 8 9968 // CHECK17-NEXT: [[TMP79:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 0 9969 // CHECK17-NEXT: store i8* null, i8** [[TMP79]], align 8 9970 // CHECK17-NEXT: [[TMP80:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 1 9971 // CHECK17-NEXT: [[TMP81:%.*]] = bitcast i8** [[TMP80]] to i64* 9972 // CHECK17-NEXT: store i64 [[TMP73]], i64* [[TMP81]], align 8 9973 // CHECK17-NEXT: [[TMP82:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 1 9974 // CHECK17-NEXT: [[TMP83:%.*]] = bitcast i8** [[TMP82]] to i64* 9975 // CHECK17-NEXT: store i64 [[TMP73]], i64* [[TMP83]], align 8 9976 // CHECK17-NEXT: [[TMP84:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 1 9977 // CHECK17-NEXT: store i8* null, i8** [[TMP84]], align 8 9978 // CHECK17-NEXT: [[TMP85:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 0 9979 // CHECK17-NEXT: [[TMP86:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 0 9980 // CHECK17-NEXT: [[TMP87:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.region_id, i32 2, i8** [[TMP85]], i8** [[TMP86]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.7, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.8, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 9981 // CHECK17-NEXT: [[TMP88:%.*]] = icmp ne i32 [[TMP87]], 0 9982 // CHECK17-NEXT: br i1 [[TMP88]], label [[OMP_OFFLOAD_FAILED19:%.*]], label [[OMP_OFFLOAD_CONT20:%.*]] 9983 // CHECK17: omp_offload.failed19: 9984 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i64 [[TMP71]], i64 [[TMP73]]) #[[ATTR3]] 9985 // CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT20]] 9986 // CHECK17: omp_offload.cont20: 9987 // CHECK17-NEXT: br label [[OMP_IF_END:%.*]] 9988 // CHECK17: omp_if.else: 9989 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i64 [[TMP71]], i64 [[TMP73]]) #[[ATTR3]] 9990 // CHECK17-NEXT: br label [[OMP_IF_END]] 9991 // CHECK17: omp_if.end: 9992 // CHECK17-NEXT: [[TMP89:%.*]] = load i32, i32* [[A]], align 4 9993 // CHECK17-NEXT: [[CONV22:%.*]] = bitcast i64* [[A_CASTED21]] to i32* 9994 // CHECK17-NEXT: store i32 [[TMP89]], i32* [[CONV22]], align 4 9995 // CHECK17-NEXT: [[TMP90:%.*]] = load i64, i64* [[A_CASTED21]], align 8 9996 // CHECK17-NEXT: [[TMP91:%.*]] = load i32, i32* [[N_ADDR]], align 4 9997 // CHECK17-NEXT: [[CMP23:%.*]] = icmp sgt i32 [[TMP91]], 20 9998 // CHECK17-NEXT: br i1 [[CMP23]], label [[OMP_IF_THEN24:%.*]], label [[OMP_IF_ELSE30:%.*]] 9999 // CHECK17: omp_if.then24: 10000 // CHECK17-NEXT: [[TMP92:%.*]] = mul nuw i64 [[TMP2]], 4 10001 // CHECK17-NEXT: [[TMP93:%.*]] = mul nuw i64 5, [[TMP5]] 10002 // CHECK17-NEXT: [[TMP94:%.*]] = mul nuw i64 [[TMP93]], 8 10003 // CHECK17-NEXT: [[TMP95:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 0 10004 // CHECK17-NEXT: [[TMP96:%.*]] = bitcast i8** [[TMP95]] to i64* 10005 // CHECK17-NEXT: store i64 [[TMP90]], i64* [[TMP96]], align 8 10006 // CHECK17-NEXT: [[TMP97:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 0 10007 // CHECK17-NEXT: [[TMP98:%.*]] = bitcast i8** [[TMP97]] to i64* 10008 // CHECK17-NEXT: store i64 [[TMP90]], i64* [[TMP98]], align 8 10009 // CHECK17-NEXT: [[TMP99:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 10010 // CHECK17-NEXT: store i64 4, i64* [[TMP99]], align 8 10011 // CHECK17-NEXT: [[TMP100:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 0 10012 // CHECK17-NEXT: store i8* null, i8** [[TMP100]], align 8 10013 // CHECK17-NEXT: [[TMP101:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 1 10014 // CHECK17-NEXT: [[TMP102:%.*]] = bitcast i8** [[TMP101]] to [10 x float]** 10015 // CHECK17-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP102]], align 8 10016 // CHECK17-NEXT: [[TMP103:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 1 10017 // CHECK17-NEXT: [[TMP104:%.*]] = bitcast i8** [[TMP103]] to [10 x float]** 10018 // CHECK17-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP104]], align 8 10019 // CHECK17-NEXT: [[TMP105:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 10020 // CHECK17-NEXT: store i64 40, i64* [[TMP105]], align 8 10021 // CHECK17-NEXT: [[TMP106:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 1 10022 // CHECK17-NEXT: store i8* null, i8** [[TMP106]], align 8 10023 // CHECK17-NEXT: [[TMP107:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 2 10024 // CHECK17-NEXT: [[TMP108:%.*]] = bitcast i8** [[TMP107]] to i64* 10025 // CHECK17-NEXT: store i64 [[TMP2]], i64* [[TMP108]], align 8 10026 // CHECK17-NEXT: [[TMP109:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 2 10027 // CHECK17-NEXT: [[TMP110:%.*]] = bitcast i8** [[TMP109]] to i64* 10028 // CHECK17-NEXT: store i64 [[TMP2]], i64* [[TMP110]], align 8 10029 // CHECK17-NEXT: [[TMP111:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 10030 // CHECK17-NEXT: store i64 8, i64* [[TMP111]], align 8 10031 // CHECK17-NEXT: [[TMP112:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 2 10032 // CHECK17-NEXT: store i8* null, i8** [[TMP112]], align 8 10033 // CHECK17-NEXT: [[TMP113:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 3 10034 // CHECK17-NEXT: [[TMP114:%.*]] = bitcast i8** [[TMP113]] to float** 10035 // CHECK17-NEXT: store float* [[VLA]], float** [[TMP114]], align 8 10036 // CHECK17-NEXT: [[TMP115:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 3 10037 // CHECK17-NEXT: [[TMP116:%.*]] = bitcast i8** [[TMP115]] to float** 10038 // CHECK17-NEXT: store float* [[VLA]], float** [[TMP116]], align 8 10039 // CHECK17-NEXT: [[TMP117:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 10040 // CHECK17-NEXT: store i64 [[TMP92]], i64* [[TMP117]], align 8 10041 // CHECK17-NEXT: [[TMP118:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 3 10042 // CHECK17-NEXT: store i8* null, i8** [[TMP118]], align 8 10043 // CHECK17-NEXT: [[TMP119:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 4 10044 // CHECK17-NEXT: [[TMP120:%.*]] = bitcast i8** [[TMP119]] to [5 x [10 x double]]** 10045 // CHECK17-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP120]], align 8 10046 // CHECK17-NEXT: [[TMP121:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 4 10047 // CHECK17-NEXT: [[TMP122:%.*]] = bitcast i8** [[TMP121]] to [5 x [10 x double]]** 10048 // CHECK17-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP122]], align 8 10049 // CHECK17-NEXT: [[TMP123:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 10050 // CHECK17-NEXT: store i64 400, i64* [[TMP123]], align 8 10051 // CHECK17-NEXT: [[TMP124:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 4 10052 // CHECK17-NEXT: store i8* null, i8** [[TMP124]], align 8 10053 // CHECK17-NEXT: [[TMP125:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 5 10054 // CHECK17-NEXT: [[TMP126:%.*]] = bitcast i8** [[TMP125]] to i64* 10055 // CHECK17-NEXT: store i64 5, i64* [[TMP126]], align 8 10056 // CHECK17-NEXT: [[TMP127:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 5 10057 // CHECK17-NEXT: [[TMP128:%.*]] = bitcast i8** [[TMP127]] to i64* 10058 // CHECK17-NEXT: store i64 5, i64* [[TMP128]], align 8 10059 // CHECK17-NEXT: [[TMP129:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 5 10060 // CHECK17-NEXT: store i64 8, i64* [[TMP129]], align 8 10061 // CHECK17-NEXT: [[TMP130:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 5 10062 // CHECK17-NEXT: store i8* null, i8** [[TMP130]], align 8 10063 // CHECK17-NEXT: [[TMP131:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 6 10064 // CHECK17-NEXT: [[TMP132:%.*]] = bitcast i8** [[TMP131]] to i64* 10065 // CHECK17-NEXT: store i64 [[TMP5]], i64* [[TMP132]], align 8 10066 // CHECK17-NEXT: [[TMP133:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 6 10067 // CHECK17-NEXT: [[TMP134:%.*]] = bitcast i8** [[TMP133]] to i64* 10068 // CHECK17-NEXT: store i64 [[TMP5]], i64* [[TMP134]], align 8 10069 // CHECK17-NEXT: [[TMP135:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 6 10070 // CHECK17-NEXT: store i64 8, i64* [[TMP135]], align 8 10071 // CHECK17-NEXT: [[TMP136:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 6 10072 // CHECK17-NEXT: store i8* null, i8** [[TMP136]], align 8 10073 // CHECK17-NEXT: [[TMP137:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 7 10074 // CHECK17-NEXT: [[TMP138:%.*]] = bitcast i8** [[TMP137]] to double** 10075 // CHECK17-NEXT: store double* [[VLA1]], double** [[TMP138]], align 8 10076 // CHECK17-NEXT: [[TMP139:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 7 10077 // CHECK17-NEXT: [[TMP140:%.*]] = bitcast i8** [[TMP139]] to double** 10078 // CHECK17-NEXT: store double* [[VLA1]], double** [[TMP140]], align 8 10079 // CHECK17-NEXT: [[TMP141:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 10080 // CHECK17-NEXT: store i64 [[TMP94]], i64* [[TMP141]], align 8 10081 // CHECK17-NEXT: [[TMP142:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 7 10082 // CHECK17-NEXT: store i8* null, i8** [[TMP142]], align 8 10083 // CHECK17-NEXT: [[TMP143:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 8 10084 // CHECK17-NEXT: [[TMP144:%.*]] = bitcast i8** [[TMP143]] to %struct.TT** 10085 // CHECK17-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP144]], align 8 10086 // CHECK17-NEXT: [[TMP145:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 8 10087 // CHECK17-NEXT: [[TMP146:%.*]] = bitcast i8** [[TMP145]] to %struct.TT** 10088 // CHECK17-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP146]], align 8 10089 // CHECK17-NEXT: [[TMP147:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 8 10090 // CHECK17-NEXT: store i64 16, i64* [[TMP147]], align 8 10091 // CHECK17-NEXT: [[TMP148:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 8 10092 // CHECK17-NEXT: store i8* null, i8** [[TMP148]], align 8 10093 // CHECK17-NEXT: [[TMP149:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 0 10094 // CHECK17-NEXT: [[TMP150:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 0 10095 // CHECK17-NEXT: [[TMP151:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 10096 // CHECK17-NEXT: [[TMP152:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142.region_id, i32 9, i8** [[TMP149]], i8** [[TMP150]], i64* [[TMP151]], i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 10097 // CHECK17-NEXT: [[TMP153:%.*]] = icmp ne i32 [[TMP152]], 0 10098 // CHECK17-NEXT: br i1 [[TMP153]], label [[OMP_OFFLOAD_FAILED28:%.*]], label [[OMP_OFFLOAD_CONT29:%.*]] 10099 // CHECK17: omp_offload.failed28: 10100 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i64 [[TMP90]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR3]] 10101 // CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT29]] 10102 // CHECK17: omp_offload.cont29: 10103 // CHECK17-NEXT: br label [[OMP_IF_END31:%.*]] 10104 // CHECK17: omp_if.else30: 10105 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i64 [[TMP90]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR3]] 10106 // CHECK17-NEXT: br label [[OMP_IF_END31]] 10107 // CHECK17: omp_if.end31: 10108 // CHECK17-NEXT: store i32 0, i32* [[NN]], align 4 10109 // CHECK17-NEXT: [[TMP154:%.*]] = load i32, i32* [[NN]], align 4 10110 // CHECK17-NEXT: [[CONV32:%.*]] = bitcast i64* [[NN_CASTED]] to i32* 10111 // CHECK17-NEXT: store i32 [[TMP154]], i32* [[CONV32]], align 4 10112 // CHECK17-NEXT: [[TMP155:%.*]] = load i64, i64* [[NN_CASTED]], align 8 10113 // CHECK17-NEXT: [[TMP156:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS33]], i32 0, i32 0 10114 // CHECK17-NEXT: [[TMP157:%.*]] = bitcast i8** [[TMP156]] to i64* 10115 // CHECK17-NEXT: store i64 [[TMP155]], i64* [[TMP157]], align 8 10116 // CHECK17-NEXT: [[TMP158:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS34]], i32 0, i32 0 10117 // CHECK17-NEXT: [[TMP159:%.*]] = bitcast i8** [[TMP158]] to i64* 10118 // CHECK17-NEXT: store i64 [[TMP155]], i64* [[TMP159]], align 8 10119 // CHECK17-NEXT: [[TMP160:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS35]], i64 0, i64 0 10120 // CHECK17-NEXT: store i8* null, i8** [[TMP160]], align 8 10121 // CHECK17-NEXT: [[TMP161:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS33]], i32 0, i32 0 10122 // CHECK17-NEXT: [[TMP162:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS34]], i32 0, i32 0 10123 // CHECK17-NEXT: [[TMP163:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154.region_id, i32 1, i8** [[TMP161]], i8** [[TMP162]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.13, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.14, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 10124 // CHECK17-NEXT: [[TMP164:%.*]] = icmp ne i32 [[TMP163]], 0 10125 // CHECK17-NEXT: br i1 [[TMP164]], label [[OMP_OFFLOAD_FAILED36:%.*]], label [[OMP_OFFLOAD_CONT37:%.*]] 10126 // CHECK17: omp_offload.failed36: 10127 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154(i64 [[TMP155]]) #[[ATTR3]] 10128 // CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT37]] 10129 // CHECK17: omp_offload.cont37: 10130 // CHECK17-NEXT: [[TMP165:%.*]] = load i32, i32* [[NN]], align 4 10131 // CHECK17-NEXT: [[CONV39:%.*]] = bitcast i64* [[NN_CASTED38]] to i32* 10132 // CHECK17-NEXT: store i32 [[TMP165]], i32* [[CONV39]], align 4 10133 // CHECK17-NEXT: [[TMP166:%.*]] = load i64, i64* [[NN_CASTED38]], align 8 10134 // CHECK17-NEXT: [[TMP167:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS40]], i32 0, i32 0 10135 // CHECK17-NEXT: [[TMP168:%.*]] = bitcast i8** [[TMP167]] to i64* 10136 // CHECK17-NEXT: store i64 [[TMP166]], i64* [[TMP168]], align 8 10137 // CHECK17-NEXT: [[TMP169:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS41]], i32 0, i32 0 10138 // CHECK17-NEXT: [[TMP170:%.*]] = bitcast i8** [[TMP169]] to i64* 10139 // CHECK17-NEXT: store i64 [[TMP166]], i64* [[TMP170]], align 8 10140 // CHECK17-NEXT: [[TMP171:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS42]], i64 0, i64 0 10141 // CHECK17-NEXT: store i8* null, i8** [[TMP171]], align 8 10142 // CHECK17-NEXT: [[TMP172:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS40]], i32 0, i32 0 10143 // CHECK17-NEXT: [[TMP173:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS41]], i32 0, i32 0 10144 // CHECK17-NEXT: [[TMP174:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157.region_id, i32 1, i8** [[TMP172]], i8** [[TMP173]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.17, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.18, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 10145 // CHECK17-NEXT: [[TMP175:%.*]] = icmp ne i32 [[TMP174]], 0 10146 // CHECK17-NEXT: br i1 [[TMP175]], label [[OMP_OFFLOAD_FAILED43:%.*]], label [[OMP_OFFLOAD_CONT44:%.*]] 10147 // CHECK17: omp_offload.failed43: 10148 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157(i64 [[TMP166]]) #[[ATTR3]] 10149 // CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT44]] 10150 // CHECK17: omp_offload.cont44: 10151 // CHECK17-NEXT: [[TMP176:%.*]] = load i32, i32* [[A]], align 4 10152 // CHECK17-NEXT: [[TMP177:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 10153 // CHECK17-NEXT: call void @llvm.stackrestore(i8* [[TMP177]]) 10154 // CHECK17-NEXT: ret i32 [[TMP176]] 10155 // 10156 // 10157 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101 10158 // CHECK17-SAME: (i64 [[AA:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] { 10159 // CHECK17-NEXT: entry: 10160 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 10161 // CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 10162 // CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8 10163 // CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 10164 // CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 10165 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 10166 // CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 10167 // CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8 10168 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 10169 // CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* 10170 // CHECK17-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32* 10171 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 8 10172 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 8 10173 // CHECK17-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) 10174 // CHECK17-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 8 10175 // CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 10176 // CHECK17-NEXT: store i16 [[TMP3]], i16* [[CONV5]], align 2 10177 // CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 10178 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]]) 10179 // CHECK17-NEXT: ret void 10180 // 10181 // 10182 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined. 10183 // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] { 10184 // CHECK17-NEXT: entry: 10185 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 10186 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 10187 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 10188 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 10189 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 10190 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 10191 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 10192 // CHECK17-NEXT: ret void 10193 // 10194 // 10195 // CHECK17-LABEL: define {{[^@]+}}@.omp_task_privates_map. 10196 // CHECK17-SAME: (%struct..kmp_privates.t* noalias [[TMP0:%.*]], i16** noalias [[TMP1:%.*]], [3 x i8*]** noalias [[TMP2:%.*]], [3 x i8*]** noalias [[TMP3:%.*]], [3 x i64]** noalias [[TMP4:%.*]]) #[[ATTR4:[0-9]+]] { 10197 // CHECK17-NEXT: entry: 10198 // CHECK17-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 8 10199 // CHECK17-NEXT: [[DOTADDR1:%.*]] = alloca i16**, align 8 10200 // CHECK17-NEXT: [[DOTADDR2:%.*]] = alloca [3 x i8*]**, align 8 10201 // CHECK17-NEXT: [[DOTADDR3:%.*]] = alloca [3 x i8*]**, align 8 10202 // CHECK17-NEXT: [[DOTADDR4:%.*]] = alloca [3 x i64]**, align 8 10203 // CHECK17-NEXT: store %struct..kmp_privates.t* [[TMP0]], %struct..kmp_privates.t** [[DOTADDR]], align 8 10204 // CHECK17-NEXT: store i16** [[TMP1]], i16*** [[DOTADDR1]], align 8 10205 // CHECK17-NEXT: store [3 x i8*]** [[TMP2]], [3 x i8*]*** [[DOTADDR2]], align 8 10206 // CHECK17-NEXT: store [3 x i8*]** [[TMP3]], [3 x i8*]*** [[DOTADDR3]], align 8 10207 // CHECK17-NEXT: store [3 x i64]** [[TMP4]], [3 x i64]*** [[DOTADDR4]], align 8 10208 // CHECK17-NEXT: [[TMP5:%.*]] = load %struct..kmp_privates.t*, %struct..kmp_privates.t** [[DOTADDR]], align 8 10209 // CHECK17-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 0 10210 // CHECK17-NEXT: [[TMP7:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR2]], align 8 10211 // CHECK17-NEXT: store [3 x i8*]* [[TMP6]], [3 x i8*]** [[TMP7]], align 8 10212 // CHECK17-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 1 10213 // CHECK17-NEXT: [[TMP9:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR3]], align 8 10214 // CHECK17-NEXT: store [3 x i8*]* [[TMP8]], [3 x i8*]** [[TMP9]], align 8 10215 // CHECK17-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 2 10216 // CHECK17-NEXT: [[TMP11:%.*]] = load [3 x i64]**, [3 x i64]*** [[DOTADDR4]], align 8 10217 // CHECK17-NEXT: store [3 x i64]* [[TMP10]], [3 x i64]** [[TMP11]], align 8 10218 // CHECK17-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 3 10219 // CHECK17-NEXT: [[TMP13:%.*]] = load i16**, i16*** [[DOTADDR1]], align 8 10220 // CHECK17-NEXT: store i16* [[TMP12]], i16** [[TMP13]], align 8 10221 // CHECK17-NEXT: ret void 10222 // 10223 // 10224 // CHECK17-LABEL: define {{[^@]+}}@.omp_task_entry. 10225 // CHECK17-SAME: (i32 signext [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { 10226 // CHECK17-NEXT: entry: 10227 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 10228 // CHECK17-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 10229 // CHECK17-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8 10230 // CHECK17-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8 10231 // CHECK17-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8 10232 // CHECK17-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 8 10233 // CHECK17-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca i16*, align 8 10234 // CHECK17-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca [3 x i8*]*, align 8 10235 // CHECK17-NEXT: [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca [3 x i8*]*, align 8 10236 // CHECK17-NEXT: [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca [3 x i64]*, align 8 10237 // CHECK17-NEXT: [[AA_CASTED_I:%.*]] = alloca i64, align 8 10238 // CHECK17-NEXT: [[DOTCAPTURE_EXPR__CASTED_I:%.*]] = alloca i64, align 8 10239 // CHECK17-NEXT: [[DOTCAPTURE_EXPR__CASTED5_I:%.*]] = alloca i64, align 8 10240 // CHECK17-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 10241 // CHECK17-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8 10242 // CHECK17-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 10243 // CHECK17-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 10244 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 10245 // CHECK17-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 10246 // CHECK17-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0 10247 // CHECK17-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 10248 // CHECK17-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 10249 // CHECK17-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 10250 // CHECK17-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon* 10251 // CHECK17-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1 10252 // CHECK17-NEXT: [[TMP10:%.*]] = bitcast %struct..kmp_privates.t* [[TMP9]] to i8* 10253 // CHECK17-NEXT: [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8* 10254 // CHECK17-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META14:![0-9]+]]) 10255 // CHECK17-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META17:![0-9]+]]) 10256 // CHECK17-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]]) 10257 // CHECK17-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META21:![0-9]+]]) 10258 // CHECK17-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !23 10259 // CHECK17-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !23 10260 // CHECK17-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !23 10261 // CHECK17-NEXT: store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* @.omp_task_privates_map. to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !23 10262 // CHECK17-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !23 10263 // CHECK17-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !23 10264 // CHECK17-NEXT: [[TMP12:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !23 10265 // CHECK17-NEXT: [[TMP13:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !23 10266 // CHECK17-NEXT: [[TMP14:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !23 10267 // CHECK17-NEXT: [[TMP15:%.*]] = bitcast void (i8*, ...)* [[TMP13]] to void (i8*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* 10268 // CHECK17-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]] 10269 // CHECK17-NEXT: [[TMP16:%.*]] = load i16*, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !23 10270 // CHECK17-NEXT: [[TMP17:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !23 10271 // CHECK17-NEXT: [[TMP18:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 8, !noalias !23 10272 // CHECK17-NEXT: [[TMP19:%.*]] = load [3 x i64]*, [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 8, !noalias !23 10273 // CHECK17-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP17]], i64 0, i64 0 10274 // CHECK17-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP18]], i64 0, i64 0 10275 // CHECK17-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[TMP19]], i64 0, i64 0 10276 // CHECK17-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP12]], i32 0, i32 1 10277 // CHECK17-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[TMP12]], i32 0, i32 2 10278 // CHECK17-NEXT: [[TMP25:%.*]] = load i32, i32* [[TMP23]], align 4 10279 // CHECK17-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP24]], align 4 10280 // CHECK17-NEXT: [[TMP27:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 [[TMP25]], i32 [[TMP26]]) #[[ATTR3]] 10281 // CHECK17-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0 10282 // CHECK17-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]] 10283 // CHECK17: omp_offload.failed.i: 10284 // CHECK17-NEXT: [[TMP29:%.*]] = load i16, i16* [[TMP16]], align 2 10285 // CHECK17-NEXT: [[CONV_I:%.*]] = bitcast i64* [[AA_CASTED_I]] to i16* 10286 // CHECK17-NEXT: store i16 [[TMP29]], i16* [[CONV_I]], align 2, !noalias !23 10287 // CHECK17-NEXT: [[TMP30:%.*]] = load i64, i64* [[AA_CASTED_I]], align 8, !noalias !23 10288 // CHECK17-NEXT: [[TMP31:%.*]] = load i32, i32* [[TMP23]], align 4 10289 // CHECK17-NEXT: [[CONV4_I:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED_I]] to i32* 10290 // CHECK17-NEXT: store i32 [[TMP31]], i32* [[CONV4_I]], align 4, !noalias !23 10291 // CHECK17-NEXT: [[TMP32:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED_I]], align 8, !noalias !23 10292 // CHECK17-NEXT: [[TMP33:%.*]] = load i32, i32* [[TMP24]], align 4 10293 // CHECK17-NEXT: [[CONV6_I:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED5_I]] to i32* 10294 // CHECK17-NEXT: store i32 [[TMP33]], i32* [[CONV6_I]], align 4, !noalias !23 10295 // CHECK17-NEXT: [[TMP34:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED5_I]], align 8, !noalias !23 10296 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101(i64 [[TMP30]], i64 [[TMP32]], i64 [[TMP34]]) #[[ATTR3]] 10297 // CHECK17-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]] 10298 // CHECK17: .omp_outlined..1.exit: 10299 // CHECK17-NEXT: ret i32 0 10300 // 10301 // 10302 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l105 10303 // CHECK17-SAME: (i64 [[A:%.*]]) #[[ATTR2]] { 10304 // CHECK17-NEXT: entry: 10305 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 10306 // CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 10307 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 10308 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 10309 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 10310 // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32* 10311 // CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 10312 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 10313 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]]) 10314 // CHECK17-NEXT: ret void 10315 // 10316 // 10317 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..2 10318 // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]]) #[[ATTR2]] { 10319 // CHECK17-NEXT: entry: 10320 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 10321 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 10322 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 10323 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 10324 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 10325 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 10326 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 10327 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 10328 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 10329 // CHECK17-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 10330 // CHECK17-NEXT: ret void 10331 // 10332 // 10333 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 10334 // CHECK17-SAME: (i64 [[AA:%.*]]) #[[ATTR2]] { 10335 // CHECK17-NEXT: entry: 10336 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 10337 // CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 10338 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 10339 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 10340 // CHECK17-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8 10341 // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 10342 // CHECK17-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 10343 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 10344 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP1]]) 10345 // CHECK17-NEXT: ret void 10346 // 10347 // 10348 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..3 10349 // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] { 10350 // CHECK17-NEXT: entry: 10351 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 10352 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 10353 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 10354 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 10355 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 10356 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 10357 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 10358 // CHECK17-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8 10359 // CHECK17-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 10360 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 10361 // CHECK17-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 10362 // CHECK17-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 8 10363 // CHECK17-NEXT: ret void 10364 // 10365 // 10366 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118 10367 // CHECK17-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] { 10368 // CHECK17-NEXT: entry: 10369 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 10370 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 10371 // CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 10372 // CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 10373 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 10374 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 10375 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 10376 // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 10377 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 10378 // CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* 10379 // CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 10380 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 10381 // CHECK17-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 10382 // CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 10383 // CHECK17-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 10384 // CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 10385 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) 10386 // CHECK17-NEXT: ret void 10387 // 10388 // 10389 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..6 10390 // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] { 10391 // CHECK17-NEXT: entry: 10392 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 10393 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 10394 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 10395 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 10396 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 10397 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 10398 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 10399 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 10400 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 10401 // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 10402 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 10403 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 10404 // CHECK17-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 10405 // CHECK17-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 8 10406 // CHECK17-NEXT: [[CONV2:%.*]] = sext i16 [[TMP1]] to i32 10407 // CHECK17-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 10408 // CHECK17-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 10409 // CHECK17-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 8 10410 // CHECK17-NEXT: ret void 10411 // 10412 // 10413 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142 10414 // CHECK17-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] { 10415 // CHECK17-NEXT: entry: 10416 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 10417 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 10418 // CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 10419 // CHECK17-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 10420 // CHECK17-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 10421 // CHECK17-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 10422 // CHECK17-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 10423 // CHECK17-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 10424 // CHECK17-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 10425 // CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 10426 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 10427 // CHECK17-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 10428 // CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 10429 // CHECK17-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 10430 // CHECK17-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 10431 // CHECK17-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 10432 // CHECK17-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 10433 // CHECK17-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 10434 // CHECK17-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 10435 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 10436 // CHECK17-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 10437 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 10438 // CHECK17-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 10439 // CHECK17-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 10440 // CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 10441 // CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 10442 // CHECK17-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 10443 // CHECK17-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 10444 // CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 10445 // CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* 10446 // CHECK17-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4 10447 // CHECK17-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 10448 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) 10449 // CHECK17-NEXT: ret void 10450 // 10451 // 10452 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..9 10453 // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] { 10454 // CHECK17-NEXT: entry: 10455 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 10456 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 10457 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 10458 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 10459 // CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 10460 // CHECK17-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 10461 // CHECK17-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 10462 // CHECK17-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 10463 // CHECK17-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 10464 // CHECK17-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 10465 // CHECK17-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 10466 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 10467 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 10468 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 10469 // CHECK17-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 10470 // CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 10471 // CHECK17-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 10472 // CHECK17-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 10473 // CHECK17-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 10474 // CHECK17-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 10475 // CHECK17-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 10476 // CHECK17-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 10477 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 10478 // CHECK17-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 10479 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 10480 // CHECK17-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 10481 // CHECK17-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 10482 // CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 10483 // CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 10484 // CHECK17-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 10485 // CHECK17-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 10486 // CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 10487 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 10488 // CHECK17-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 10489 // CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 10490 // CHECK17-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 10491 // CHECK17-NEXT: [[CONV5:%.*]] = fpext float [[TMP9]] to double 10492 // CHECK17-NEXT: [[ADD6:%.*]] = fadd double [[CONV5]], 1.000000e+00 10493 // CHECK17-NEXT: [[CONV7:%.*]] = fptrunc double [[ADD6]] to float 10494 // CHECK17-NEXT: store float [[CONV7]], float* [[ARRAYIDX]], align 4 10495 // CHECK17-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 10496 // CHECK17-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX8]], align 4 10497 // CHECK17-NEXT: [[CONV9:%.*]] = fpext float [[TMP10]] to double 10498 // CHECK17-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 10499 // CHECK17-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float 10500 // CHECK17-NEXT: store float [[CONV11]], float* [[ARRAYIDX8]], align 4 10501 // CHECK17-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1 10502 // CHECK17-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX12]], i64 0, i64 2 10503 // CHECK17-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX13]], align 8 10504 // CHECK17-NEXT: [[ADD14:%.*]] = fadd double [[TMP11]], 1.000000e+00 10505 // CHECK17-NEXT: store double [[ADD14]], double* [[ARRAYIDX13]], align 8 10506 // CHECK17-NEXT: [[TMP12:%.*]] = mul nsw i64 1, [[TMP5]] 10507 // CHECK17-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP12]] 10508 // CHECK17-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX15]], i64 3 10509 // CHECK17-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX16]], align 8 10510 // CHECK17-NEXT: [[ADD17:%.*]] = fadd double [[TMP13]], 1.000000e+00 10511 // CHECK17-NEXT: store double [[ADD17]], double* [[ARRAYIDX16]], align 8 10512 // CHECK17-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 10513 // CHECK17-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 8 10514 // CHECK17-NEXT: [[ADD18:%.*]] = add nsw i64 [[TMP14]], 1 10515 // CHECK17-NEXT: store i64 [[ADD18]], i64* [[X]], align 8 10516 // CHECK17-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 10517 // CHECK17-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 8 10518 // CHECK17-NEXT: [[CONV19:%.*]] = sext i8 [[TMP15]] to i32 10519 // CHECK17-NEXT: [[ADD20:%.*]] = add nsw i32 [[CONV19]], 1 10520 // CHECK17-NEXT: [[CONV21:%.*]] = trunc i32 [[ADD20]] to i8 10521 // CHECK17-NEXT: store i8 [[CONV21]], i8* [[Y]], align 8 10522 // CHECK17-NEXT: ret void 10523 // 10524 // 10525 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154 10526 // CHECK17-SAME: (i64 [[NN:%.*]]) #[[ATTR2]] { 10527 // CHECK17-NEXT: entry: 10528 // CHECK17-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 10529 // CHECK17-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 10530 // CHECK17-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 10531 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* 10532 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 10533 // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32* 10534 // CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 10535 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8 10536 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP1]]) 10537 // CHECK17-NEXT: ret void 10538 // 10539 // 10540 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..11 10541 // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[NN:%.*]]) #[[ATTR2]] { 10542 // CHECK17-NEXT: entry: 10543 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 10544 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 10545 // CHECK17-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 10546 // CHECK17-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 10547 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 10548 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 10549 // CHECK17-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 10550 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* 10551 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 10552 // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32* 10553 // CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 10554 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8 10555 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..12 to void (i32*, i32*, ...)*), i64 [[TMP1]]) 10556 // CHECK17-NEXT: ret void 10557 // 10558 // 10559 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..12 10560 // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[NN:%.*]]) #[[ATTR2]] { 10561 // CHECK17-NEXT: entry: 10562 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 10563 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 10564 // CHECK17-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 10565 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 10566 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 10567 // CHECK17-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 10568 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* 10569 // CHECK17-NEXT: ret void 10570 // 10571 // 10572 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157 10573 // CHECK17-SAME: (i64 [[NN:%.*]]) #[[ATTR2]] { 10574 // CHECK17-NEXT: entry: 10575 // CHECK17-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 10576 // CHECK17-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 10577 // CHECK17-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 10578 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* 10579 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 10580 // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32* 10581 // CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 10582 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8 10583 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i64 [[TMP1]]) 10584 // CHECK17-NEXT: ret void 10585 // 10586 // 10587 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..15 10588 // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[NN:%.*]]) #[[ATTR2]] { 10589 // CHECK17-NEXT: entry: 10590 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 10591 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 10592 // CHECK17-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 10593 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 10594 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 10595 // CHECK17-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 10596 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* 10597 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i32* [[CONV]]) 10598 // CHECK17-NEXT: ret void 10599 // 10600 // 10601 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..16 10602 // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[NN:%.*]]) #[[ATTR2]] { 10603 // CHECK17-NEXT: entry: 10604 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 10605 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 10606 // CHECK17-NEXT: [[NN_ADDR:%.*]] = alloca i32*, align 8 10607 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 10608 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 10609 // CHECK17-NEXT: store i32* [[NN]], i32** [[NN_ADDR]], align 8 10610 // CHECK17-NEXT: [[TMP0:%.*]] = load i32*, i32** [[NN_ADDR]], align 8 10611 // CHECK17-NEXT: ret void 10612 // 10613 // 10614 // CHECK17-LABEL: define {{[^@]+}}@_Z6bazzzziPi 10615 // CHECK17-SAME: (i32 signext [[N:%.*]], i32* [[F:%.*]]) #[[ATTR0]] { 10616 // CHECK17-NEXT: entry: 10617 // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 10618 // CHECK17-NEXT: [[F_ADDR:%.*]] = alloca i32*, align 8 10619 // CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 10620 // CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 10621 // CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 10622 // CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 10623 // CHECK17-NEXT: store i32* [[F]], i32** [[F_ADDR]], align 8 10624 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 10625 // CHECK17-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 10626 // CHECK17-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 10627 // CHECK17-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to i64* 10628 // CHECK17-NEXT: store i64 [[TMP1]], i64* [[TMP3]], align 8 10629 // CHECK17-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 10630 // CHECK17-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i64* 10631 // CHECK17-NEXT: store i64 [[TMP1]], i64* [[TMP5]], align 8 10632 // CHECK17-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 10633 // CHECK17-NEXT: store i8* null, i8** [[TMP6]], align 8 10634 // CHECK17-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 10635 // CHECK17-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 10636 // CHECK17-NEXT: [[TMP9:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182.region_id, i32 1, i8** [[TMP7]], i8** [[TMP8]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.20, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.21, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 10637 // CHECK17-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 10638 // CHECK17-NEXT: br i1 [[TMP10]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 10639 // CHECK17: omp_offload.failed: 10640 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182(i64 [[TMP1]]) #[[ATTR3]] 10641 // CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]] 10642 // CHECK17: omp_offload.cont: 10643 // CHECK17-NEXT: ret void 10644 // 10645 // 10646 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182 10647 // CHECK17-SAME: (i64 [[VLA:%.*]]) #[[ATTR2]] { 10648 // CHECK17-NEXT: entry: 10649 // CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 10650 // CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 10651 // CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 10652 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..19 to void (i32*, i32*, ...)*), i64 [[TMP0]]) 10653 // CHECK17-NEXT: ret void 10654 // 10655 // 10656 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..19 10657 // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[VLA:%.*]]) #[[ATTR2]] { 10658 // CHECK17-NEXT: entry: 10659 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 10660 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 10661 // CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 10662 // CHECK17-NEXT: [[F:%.*]] = alloca i32*, align 8 10663 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 10664 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 10665 // CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 10666 // CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 10667 // CHECK17-NEXT: ret void 10668 // 10669 // 10670 // CHECK17-LABEL: define {{[^@]+}}@_Z3bari 10671 // CHECK17-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { 10672 // CHECK17-NEXT: entry: 10673 // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 10674 // CHECK17-NEXT: [[A:%.*]] = alloca i32, align 4 10675 // CHECK17-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 10676 // CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 10677 // CHECK17-NEXT: store i32 0, i32* [[A]], align 4 10678 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 10679 // CHECK17-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]]) 10680 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 10681 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 10682 // CHECK17-NEXT: store i32 [[ADD]], i32* [[A]], align 4 10683 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 10684 // CHECK17-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]]) 10685 // CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 10686 // CHECK17-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 10687 // CHECK17-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 10688 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 10689 // CHECK17-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]]) 10690 // CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 10691 // CHECK17-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 10692 // CHECK17-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 10693 // CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 10694 // CHECK17-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]]) 10695 // CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 10696 // CHECK17-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] 10697 // CHECK17-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 10698 // CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 10699 // CHECK17-NEXT: ret i32 [[TMP8]] 10700 // 10701 // 10702 // CHECK17-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 10703 // CHECK17-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { 10704 // CHECK17-NEXT: entry: 10705 // CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 10706 // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 10707 // CHECK17-NEXT: [[B:%.*]] = alloca i32, align 4 10708 // CHECK17-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 10709 // CHECK17-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 10710 // CHECK17-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 10711 // CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8 10712 // CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8 10713 // CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8 10714 // CHECK17-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 8 10715 // CHECK17-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 10716 // CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 10717 // CHECK17-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 10718 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 10719 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 10720 // CHECK17-NEXT: store i32 [[ADD]], i32* [[B]], align 4 10721 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 10722 // CHECK17-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 10723 // CHECK17-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() 10724 // CHECK17-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 10725 // CHECK17-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] 10726 // CHECK17-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 10727 // CHECK17-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 10728 // CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 10729 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32* 10730 // CHECK17-NEXT: store i32 [[TMP5]], i32* [[CONV]], align 4 10731 // CHECK17-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 10732 // CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4 10733 // CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 60 10734 // CHECK17-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 10735 // CHECK17: omp_if.then: 10736 // CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 10737 // CHECK17-NEXT: [[TMP8:%.*]] = mul nuw i64 2, [[TMP2]] 10738 // CHECK17-NEXT: [[TMP9:%.*]] = mul nuw i64 [[TMP8]], 2 10739 // CHECK17-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 10740 // CHECK17-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to %struct.S1** 10741 // CHECK17-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP11]], align 8 10742 // CHECK17-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 10743 // CHECK17-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to double** 10744 // CHECK17-NEXT: store double* [[A]], double** [[TMP13]], align 8 10745 // CHECK17-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 10746 // CHECK17-NEXT: store i64 8, i64* [[TMP14]], align 8 10747 // CHECK17-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 10748 // CHECK17-NEXT: store i8* null, i8** [[TMP15]], align 8 10749 // CHECK17-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 10750 // CHECK17-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64* 10751 // CHECK17-NEXT: store i64 [[TMP6]], i64* [[TMP17]], align 8 10752 // CHECK17-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 10753 // CHECK17-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64* 10754 // CHECK17-NEXT: store i64 [[TMP6]], i64* [[TMP19]], align 8 10755 // CHECK17-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 10756 // CHECK17-NEXT: store i64 4, i64* [[TMP20]], align 8 10757 // CHECK17-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 10758 // CHECK17-NEXT: store i8* null, i8** [[TMP21]], align 8 10759 // CHECK17-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 10760 // CHECK17-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i64* 10761 // CHECK17-NEXT: store i64 2, i64* [[TMP23]], align 8 10762 // CHECK17-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 10763 // CHECK17-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i64* 10764 // CHECK17-NEXT: store i64 2, i64* [[TMP25]], align 8 10765 // CHECK17-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 10766 // CHECK17-NEXT: store i64 8, i64* [[TMP26]], align 8 10767 // CHECK17-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 10768 // CHECK17-NEXT: store i8* null, i8** [[TMP27]], align 8 10769 // CHECK17-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 10770 // CHECK17-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i64* 10771 // CHECK17-NEXT: store i64 [[TMP2]], i64* [[TMP29]], align 8 10772 // CHECK17-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 10773 // CHECK17-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i64* 10774 // CHECK17-NEXT: store i64 [[TMP2]], i64* [[TMP31]], align 8 10775 // CHECK17-NEXT: [[TMP32:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 10776 // CHECK17-NEXT: store i64 8, i64* [[TMP32]], align 8 10777 // CHECK17-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 10778 // CHECK17-NEXT: store i8* null, i8** [[TMP33]], align 8 10779 // CHECK17-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 10780 // CHECK17-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i16** 10781 // CHECK17-NEXT: store i16* [[VLA]], i16** [[TMP35]], align 8 10782 // CHECK17-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 10783 // CHECK17-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i16** 10784 // CHECK17-NEXT: store i16* [[VLA]], i16** [[TMP37]], align 8 10785 // CHECK17-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 10786 // CHECK17-NEXT: store i64 [[TMP9]], i64* [[TMP38]], align 8 10787 // CHECK17-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 10788 // CHECK17-NEXT: store i8* null, i8** [[TMP39]], align 8 10789 // CHECK17-NEXT: [[TMP40:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 10790 // CHECK17-NEXT: [[TMP41:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 10791 // CHECK17-NEXT: [[TMP42:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 10792 // CHECK17-NEXT: [[TMP43:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227.region_id, i32 5, i8** [[TMP40]], i8** [[TMP41]], i64* [[TMP42]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.23, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 10793 // CHECK17-NEXT: [[TMP44:%.*]] = icmp ne i32 [[TMP43]], 0 10794 // CHECK17-NEXT: br i1 [[TMP44]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 10795 // CHECK17: omp_offload.failed: 10796 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR3]] 10797 // CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]] 10798 // CHECK17: omp_offload.cont: 10799 // CHECK17-NEXT: br label [[OMP_IF_END:%.*]] 10800 // CHECK17: omp_if.else: 10801 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR3]] 10802 // CHECK17-NEXT: br label [[OMP_IF_END]] 10803 // CHECK17: omp_if.end: 10804 // CHECK17-NEXT: [[TMP45:%.*]] = mul nsw i64 1, [[TMP2]] 10805 // CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP45]] 10806 // CHECK17-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 10807 // CHECK17-NEXT: [[TMP46:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2 10808 // CHECK17-NEXT: [[CONV3:%.*]] = sext i16 [[TMP46]] to i32 10809 // CHECK17-NEXT: [[TMP47:%.*]] = load i32, i32* [[B]], align 4 10810 // CHECK17-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], [[TMP47]] 10811 // CHECK17-NEXT: [[TMP48:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 10812 // CHECK17-NEXT: call void @llvm.stackrestore(i8* [[TMP48]]) 10813 // CHECK17-NEXT: ret i32 [[ADD4]] 10814 // 10815 // 10816 // CHECK17-LABEL: define {{[^@]+}}@_ZL7fstatici 10817 // CHECK17-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { 10818 // CHECK17-NEXT: entry: 10819 // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 10820 // CHECK17-NEXT: [[A:%.*]] = alloca i32, align 4 10821 // CHECK17-NEXT: [[AA:%.*]] = alloca i16, align 2 10822 // CHECK17-NEXT: [[AAA:%.*]] = alloca i8, align 1 10823 // CHECK17-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 10824 // CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 10825 // CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 10826 // CHECK17-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 10827 // CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8 10828 // CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 10829 // CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 10830 // CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 10831 // CHECK17-NEXT: store i32 0, i32* [[A]], align 4 10832 // CHECK17-NEXT: store i16 0, i16* [[AA]], align 2 10833 // CHECK17-NEXT: store i8 0, i8* [[AAA]], align 1 10834 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 10835 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* 10836 // CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 10837 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 10838 // CHECK17-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 10839 // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 10840 // CHECK17-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 10841 // CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 10842 // CHECK17-NEXT: [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1 10843 // CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* 10844 // CHECK17-NEXT: store i8 [[TMP4]], i8* [[CONV2]], align 1 10845 // CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 10846 // CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 10847 // CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50 10848 // CHECK17-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 10849 // CHECK17: omp_if.then: 10850 // CHECK17-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 10851 // CHECK17-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* 10852 // CHECK17-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8 10853 // CHECK17-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 10854 // CHECK17-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* 10855 // CHECK17-NEXT: store i64 [[TMP1]], i64* [[TMP10]], align 8 10856 // CHECK17-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 10857 // CHECK17-NEXT: store i8* null, i8** [[TMP11]], align 8 10858 // CHECK17-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 10859 // CHECK17-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* 10860 // CHECK17-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8 10861 // CHECK17-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 10862 // CHECK17-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* 10863 // CHECK17-NEXT: store i64 [[TMP3]], i64* [[TMP15]], align 8 10864 // CHECK17-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 10865 // CHECK17-NEXT: store i8* null, i8** [[TMP16]], align 8 10866 // CHECK17-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 10867 // CHECK17-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64* 10868 // CHECK17-NEXT: store i64 [[TMP5]], i64* [[TMP18]], align 8 10869 // CHECK17-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 10870 // CHECK17-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64* 10871 // CHECK17-NEXT: store i64 [[TMP5]], i64* [[TMP20]], align 8 10872 // CHECK17-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 10873 // CHECK17-NEXT: store i8* null, i8** [[TMP21]], align 8 10874 // CHECK17-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 10875 // CHECK17-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]** 10876 // CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 8 10877 // CHECK17-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 10878 // CHECK17-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]** 10879 // CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 8 10880 // CHECK17-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 10881 // CHECK17-NEXT: store i8* null, i8** [[TMP26]], align 8 10882 // CHECK17-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 10883 // CHECK17-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 10884 // CHECK17-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.25, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.26, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 10885 // CHECK17-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 10886 // CHECK17-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 10887 // CHECK17: omp_offload.failed: 10888 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR3]] 10889 // CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]] 10890 // CHECK17: omp_offload.cont: 10891 // CHECK17-NEXT: br label [[OMP_IF_END:%.*]] 10892 // CHECK17: omp_if.else: 10893 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR3]] 10894 // CHECK17-NEXT: br label [[OMP_IF_END]] 10895 // CHECK17: omp_if.end: 10896 // CHECK17-NEXT: [[TMP31:%.*]] = load i32, i32* [[A]], align 4 10897 // CHECK17-NEXT: ret i32 [[TMP31]] 10898 // 10899 // 10900 // CHECK17-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 10901 // CHECK17-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { 10902 // CHECK17-NEXT: entry: 10903 // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 10904 // CHECK17-NEXT: [[A:%.*]] = alloca i32, align 4 10905 // CHECK17-NEXT: [[AA:%.*]] = alloca i16, align 2 10906 // CHECK17-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 10907 // CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 10908 // CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 10909 // CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 10910 // CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 10911 // CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 10912 // CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 10913 // CHECK17-NEXT: store i32 0, i32* [[A]], align 4 10914 // CHECK17-NEXT: store i16 0, i16* [[AA]], align 2 10915 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 10916 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* 10917 // CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 10918 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 10919 // CHECK17-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 10920 // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 10921 // CHECK17-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 10922 // CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 10923 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 10924 // CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40 10925 // CHECK17-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 10926 // CHECK17: omp_if.then: 10927 // CHECK17-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 10928 // CHECK17-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64* 10929 // CHECK17-NEXT: store i64 [[TMP1]], i64* [[TMP6]], align 8 10930 // CHECK17-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 10931 // CHECK17-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* 10932 // CHECK17-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8 10933 // CHECK17-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 10934 // CHECK17-NEXT: store i8* null, i8** [[TMP9]], align 8 10935 // CHECK17-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 10936 // CHECK17-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i64* 10937 // CHECK17-NEXT: store i64 [[TMP3]], i64* [[TMP11]], align 8 10938 // CHECK17-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 10939 // CHECK17-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* 10940 // CHECK17-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8 10941 // CHECK17-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 10942 // CHECK17-NEXT: store i8* null, i8** [[TMP14]], align 8 10943 // CHECK17-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 10944 // CHECK17-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]** 10945 // CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 8 10946 // CHECK17-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 10947 // CHECK17-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]** 10948 // CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 8 10949 // CHECK17-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 10950 // CHECK17-NEXT: store i8* null, i8** [[TMP19]], align 8 10951 // CHECK17-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 10952 // CHECK17-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 10953 // CHECK17-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.28, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.29, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 10954 // CHECK17-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 10955 // CHECK17-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 10956 // CHECK17: omp_offload.failed: 10957 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]] 10958 // CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]] 10959 // CHECK17: omp_offload.cont: 10960 // CHECK17-NEXT: br label [[OMP_IF_END:%.*]] 10961 // CHECK17: omp_if.else: 10962 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]] 10963 // CHECK17-NEXT: br label [[OMP_IF_END]] 10964 // CHECK17: omp_if.end: 10965 // CHECK17-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4 10966 // CHECK17-NEXT: ret i32 [[TMP24]] 10967 // 10968 // 10969 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227 10970 // CHECK17-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { 10971 // CHECK17-NEXT: entry: 10972 // CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 10973 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 10974 // CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 10975 // CHECK17-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 10976 // CHECK17-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 10977 // CHECK17-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 10978 // CHECK17-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 10979 // CHECK17-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 10980 // CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 10981 // CHECK17-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 10982 // CHECK17-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 10983 // CHECK17-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 10984 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 10985 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 10986 // CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 10987 // CHECK17-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 10988 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 10989 // CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* 10990 // CHECK17-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 10991 // CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 10992 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..22 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) 10993 // CHECK17-NEXT: ret void 10994 // 10995 // 10996 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..22 10997 // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { 10998 // CHECK17-NEXT: entry: 10999 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 11000 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 11001 // CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 11002 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 11003 // CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 11004 // CHECK17-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 11005 // CHECK17-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 11006 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 11007 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 11008 // CHECK17-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 11009 // CHECK17-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 11010 // CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 11011 // CHECK17-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 11012 // CHECK17-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 11013 // CHECK17-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 11014 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 11015 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 11016 // CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 11017 // CHECK17-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 11018 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 11019 // CHECK17-NEXT: [[CONV3:%.*]] = sitofp i32 [[TMP4]] to double 11020 // CHECK17-NEXT: [[ADD:%.*]] = fadd double [[CONV3]], 1.500000e+00 11021 // CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 11022 // CHECK17-NEXT: store double [[ADD]], double* [[A]], align 8 11023 // CHECK17-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 11024 // CHECK17-NEXT: [[TMP5:%.*]] = load double, double* [[A4]], align 8 11025 // CHECK17-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 11026 // CHECK17-NEXT: store double [[INC]], double* [[A4]], align 8 11027 // CHECK17-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 11028 // CHECK17-NEXT: [[TMP6:%.*]] = mul nsw i64 1, [[TMP2]] 11029 // CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP6]] 11030 // CHECK17-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 11031 // CHECK17-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2 11032 // CHECK17-NEXT: ret void 11033 // 11034 // 11035 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209 11036 // CHECK17-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 11037 // CHECK17-NEXT: entry: 11038 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 11039 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 11040 // CHECK17-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 11041 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 11042 // CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 11043 // CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 11044 // CHECK17-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 11045 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 11046 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 11047 // CHECK17-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 11048 // CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 11049 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 11050 // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 11051 // CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 11052 // CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 11053 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 11054 // CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* 11055 // CHECK17-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 11056 // CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 11057 // CHECK17-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 11058 // CHECK17-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 11059 // CHECK17-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 11060 // CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 11061 // CHECK17-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8 11062 // CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* 11063 // CHECK17-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 11064 // CHECK17-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 11065 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..24 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) 11066 // CHECK17-NEXT: ret void 11067 // 11068 // 11069 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..24 11070 // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 11071 // CHECK17-NEXT: entry: 11072 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 11073 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 11074 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 11075 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 11076 // CHECK17-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 11077 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 11078 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 11079 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 11080 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 11081 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 11082 // CHECK17-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 11083 // CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 11084 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 11085 // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 11086 // CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 11087 // CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 11088 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 11089 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 11090 // CHECK17-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 11091 // CHECK17-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 11092 // CHECK17-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32 11093 // CHECK17-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 11094 // CHECK17-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 11095 // CHECK17-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 8 11096 // CHECK17-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 8 11097 // CHECK17-NEXT: [[CONV6:%.*]] = sext i8 [[TMP3]] to i32 11098 // CHECK17-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 11099 // CHECK17-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i8 11100 // CHECK17-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 8 11101 // CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 11102 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 11103 // CHECK17-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP4]], 1 11104 // CHECK17-NEXT: store i32 [[ADD9]], i32* [[ARRAYIDX]], align 4 11105 // CHECK17-NEXT: ret void 11106 // 11107 // 11108 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192 11109 // CHECK17-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 11110 // CHECK17-NEXT: entry: 11111 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 11112 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 11113 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 11114 // CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 11115 // CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 11116 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 11117 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 11118 // CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 11119 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 11120 // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 11121 // CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 11122 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 11123 // CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* 11124 // CHECK17-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 11125 // CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 11126 // CHECK17-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 11127 // CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 11128 // CHECK17-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 11129 // CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 11130 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..27 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) 11131 // CHECK17-NEXT: ret void 11132 // 11133 // 11134 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..27 11135 // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 11136 // CHECK17-NEXT: entry: 11137 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 11138 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 11139 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 11140 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 11141 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 11142 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 11143 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 11144 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 11145 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 11146 // CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 11147 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 11148 // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 11149 // CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 11150 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 11151 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 11152 // CHECK17-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 11153 // CHECK17-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 11154 // CHECK17-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 11155 // CHECK17-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 11156 // CHECK17-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 11157 // CHECK17-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 8 11158 // CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 11159 // CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 11160 // CHECK17-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP3]], 1 11161 // CHECK17-NEXT: store i32 [[ADD5]], i32* [[ARRAYIDX]], align 4 11162 // CHECK17-NEXT: ret void 11163 // 11164 // 11165 // CHECK17-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 11166 // CHECK17-SAME: () #[[ATTR4]] { 11167 // CHECK17-NEXT: entry: 11168 // CHECK17-NEXT: call void @__tgt_register_requires(i64 1) 11169 // CHECK17-NEXT: ret void 11170 // 11171 // 11172 // CHECK18-LABEL: define {{[^@]+}}@_Z3fooi 11173 // CHECK18-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { 11174 // CHECK18-NEXT: entry: 11175 // CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 11176 // CHECK18-NEXT: [[A:%.*]] = alloca i32, align 4 11177 // CHECK18-NEXT: [[AA:%.*]] = alloca i16, align 2 11178 // CHECK18-NEXT: [[B:%.*]] = alloca [10 x float], align 4 11179 // CHECK18-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 11180 // CHECK18-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 11181 // CHECK18-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 11182 // CHECK18-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 11183 // CHECK18-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 11184 // CHECK18-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 11185 // CHECK18-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 11186 // CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 11187 // CHECK18-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 11188 // CHECK18-NEXT: [[DOTCAPTURE_EXPR__CASTED4:%.*]] = alloca i64, align 8 11189 // CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 11190 // CHECK18-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 11191 // CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 11192 // CHECK18-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4 11193 // CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 11194 // CHECK18-NEXT: [[AA_CASTED7:%.*]] = alloca i64, align 8 11195 // CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS9:%.*]] = alloca [1 x i8*], align 8 11196 // CHECK18-NEXT: [[DOTOFFLOAD_PTRS10:%.*]] = alloca [1 x i8*], align 8 11197 // CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS11:%.*]] = alloca [1 x i8*], align 8 11198 // CHECK18-NEXT: [[A_CASTED12:%.*]] = alloca i64, align 8 11199 // CHECK18-NEXT: [[AA_CASTED14:%.*]] = alloca i64, align 8 11200 // CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS16:%.*]] = alloca [2 x i8*], align 8 11201 // CHECK18-NEXT: [[DOTOFFLOAD_PTRS17:%.*]] = alloca [2 x i8*], align 8 11202 // CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS18:%.*]] = alloca [2 x i8*], align 8 11203 // CHECK18-NEXT: [[A_CASTED21:%.*]] = alloca i64, align 8 11204 // CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS25:%.*]] = alloca [9 x i8*], align 8 11205 // CHECK18-NEXT: [[DOTOFFLOAD_PTRS26:%.*]] = alloca [9 x i8*], align 8 11206 // CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS27:%.*]] = alloca [9 x i8*], align 8 11207 // CHECK18-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [9 x i64], align 8 11208 // CHECK18-NEXT: [[NN:%.*]] = alloca i32, align 4 11209 // CHECK18-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 11210 // CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS33:%.*]] = alloca [1 x i8*], align 8 11211 // CHECK18-NEXT: [[DOTOFFLOAD_PTRS34:%.*]] = alloca [1 x i8*], align 8 11212 // CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS35:%.*]] = alloca [1 x i8*], align 8 11213 // CHECK18-NEXT: [[NN_CASTED38:%.*]] = alloca i64, align 8 11214 // CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS40:%.*]] = alloca [1 x i8*], align 8 11215 // CHECK18-NEXT: [[DOTOFFLOAD_PTRS41:%.*]] = alloca [1 x i8*], align 8 11216 // CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS42:%.*]] = alloca [1 x i8*], align 8 11217 // CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) 11218 // CHECK18-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 11219 // CHECK18-NEXT: store i32 0, i32* [[A]], align 4 11220 // CHECK18-NEXT: store i16 0, i16* [[AA]], align 2 11221 // CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 11222 // CHECK18-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 11223 // CHECK18-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() 11224 // CHECK18-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 11225 // CHECK18-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP2]], align 4 11226 // CHECK18-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 11227 // CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 11228 // CHECK18-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64 11229 // CHECK18-NEXT: [[TMP6:%.*]] = mul nuw i64 5, [[TMP5]] 11230 // CHECK18-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP6]], align 8 11231 // CHECK18-NEXT: store i64 [[TMP5]], i64* [[__VLA_EXPR1]], align 8 11232 // CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 11233 // CHECK18-NEXT: store i32 [[TMP7]], i32* [[DOTCAPTURE_EXPR_]], align 4 11234 // CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 11235 // CHECK18-NEXT: store i32 [[TMP8]], i32* [[DOTCAPTURE_EXPR_2]], align 4 11236 // CHECK18-NEXT: [[TMP9:%.*]] = load i16, i16* [[AA]], align 2 11237 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 11238 // CHECK18-NEXT: store i16 [[TMP9]], i16* [[CONV]], align 2 11239 // CHECK18-NEXT: [[TMP10:%.*]] = load i64, i64* [[AA_CASTED]], align 8 11240 // CHECK18-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 11241 // CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* 11242 // CHECK18-NEXT: store i32 [[TMP11]], i32* [[CONV3]], align 4 11243 // CHECK18-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 11244 // CHECK18-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 11245 // CHECK18-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED4]] to i32* 11246 // CHECK18-NEXT: store i32 [[TMP13]], i32* [[CONV5]], align 4 11247 // CHECK18-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED4]], align 8 11248 // CHECK18-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 11249 // CHECK18-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i64* 11250 // CHECK18-NEXT: store i64 [[TMP10]], i64* [[TMP16]], align 8 11251 // CHECK18-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 11252 // CHECK18-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64* 11253 // CHECK18-NEXT: store i64 [[TMP10]], i64* [[TMP18]], align 8 11254 // CHECK18-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 11255 // CHECK18-NEXT: store i8* null, i8** [[TMP19]], align 8 11256 // CHECK18-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 11257 // CHECK18-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i64* 11258 // CHECK18-NEXT: store i64 [[TMP12]], i64* [[TMP21]], align 8 11259 // CHECK18-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 11260 // CHECK18-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i64* 11261 // CHECK18-NEXT: store i64 [[TMP12]], i64* [[TMP23]], align 8 11262 // CHECK18-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 11263 // CHECK18-NEXT: store i8* null, i8** [[TMP24]], align 8 11264 // CHECK18-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 11265 // CHECK18-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i64* 11266 // CHECK18-NEXT: store i64 [[TMP14]], i64* [[TMP26]], align 8 11267 // CHECK18-NEXT: [[TMP27:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 11268 // CHECK18-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i64* 11269 // CHECK18-NEXT: store i64 [[TMP14]], i64* [[TMP28]], align 8 11270 // CHECK18-NEXT: [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 11271 // CHECK18-NEXT: store i8* null, i8** [[TMP29]], align 8 11272 // CHECK18-NEXT: [[TMP30:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 11273 // CHECK18-NEXT: [[TMP31:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 11274 // CHECK18-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 0 11275 // CHECK18-NEXT: [[TMP33:%.*]] = load i16, i16* [[AA]], align 2 11276 // CHECK18-NEXT: store i16 [[TMP33]], i16* [[TMP32]], align 4 11277 // CHECK18-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 1 11278 // CHECK18-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 11279 // CHECK18-NEXT: store i32 [[TMP35]], i32* [[TMP34]], align 4 11280 // CHECK18-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 2 11281 // CHECK18-NEXT: [[TMP37:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 11282 // CHECK18-NEXT: store i32 [[TMP37]], i32* [[TMP36]], align 4 11283 // CHECK18-NEXT: [[TMP38:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i64 120, i64 12, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1) 11284 // CHECK18-NEXT: [[TMP39:%.*]] = bitcast i8* [[TMP38]] to %struct.kmp_task_t_with_privates* 11285 // CHECK18-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP39]], i32 0, i32 0 11286 // CHECK18-NEXT: [[TMP41:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP40]], i32 0, i32 0 11287 // CHECK18-NEXT: [[TMP42:%.*]] = load i8*, i8** [[TMP41]], align 8 11288 // CHECK18-NEXT: [[TMP43:%.*]] = bitcast %struct.anon* [[AGG_CAPTURED]] to i8* 11289 // CHECK18-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP42]], i8* align 4 [[TMP43]], i64 12, i1 false) 11290 // CHECK18-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP39]], i32 0, i32 1 11291 // CHECK18-NEXT: [[TMP45:%.*]] = bitcast i8* [[TMP42]] to %struct.anon* 11292 // CHECK18-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 0 11293 // CHECK18-NEXT: [[TMP47:%.*]] = bitcast [3 x i8*]* [[TMP46]] to i8* 11294 // CHECK18-NEXT: [[TMP48:%.*]] = bitcast i8** [[TMP30]] to i8* 11295 // CHECK18-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP47]], i8* align 8 [[TMP48]], i64 24, i1 false) 11296 // CHECK18-NEXT: [[TMP49:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 1 11297 // CHECK18-NEXT: [[TMP50:%.*]] = bitcast [3 x i8*]* [[TMP49]] to i8* 11298 // CHECK18-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP31]] to i8* 11299 // CHECK18-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP50]], i8* align 8 [[TMP51]], i64 24, i1 false) 11300 // CHECK18-NEXT: [[TMP52:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 2 11301 // CHECK18-NEXT: [[TMP53:%.*]] = bitcast [3 x i64]* [[TMP52]] to i8* 11302 // CHECK18-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP53]], i8* align 8 bitcast ([3 x i64]* @.offload_sizes to i8*), i64 24, i1 false) 11303 // CHECK18-NEXT: [[TMP54:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 3 11304 // CHECK18-NEXT: [[TMP55:%.*]] = load i16, i16* [[AA]], align 2 11305 // CHECK18-NEXT: store i16 [[TMP55]], i16* [[TMP54]], align 8 11306 // CHECK18-NEXT: [[TMP56:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP38]]) 11307 // CHECK18-NEXT: [[TMP57:%.*]] = load i32, i32* [[A]], align 4 11308 // CHECK18-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32* 11309 // CHECK18-NEXT: store i32 [[TMP57]], i32* [[CONV6]], align 4 11310 // CHECK18-NEXT: [[TMP58:%.*]] = load i64, i64* [[A_CASTED]], align 8 11311 // CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l105(i64 [[TMP58]]) #[[ATTR3:[0-9]+]] 11312 // CHECK18-NEXT: [[TMP59:%.*]] = load i16, i16* [[AA]], align 2 11313 // CHECK18-NEXT: [[CONV8:%.*]] = bitcast i64* [[AA_CASTED7]] to i16* 11314 // CHECK18-NEXT: store i16 [[TMP59]], i16* [[CONV8]], align 2 11315 // CHECK18-NEXT: [[TMP60:%.*]] = load i64, i64* [[AA_CASTED7]], align 8 11316 // CHECK18-NEXT: [[TMP61:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS9]], i32 0, i32 0 11317 // CHECK18-NEXT: [[TMP62:%.*]] = bitcast i8** [[TMP61]] to i64* 11318 // CHECK18-NEXT: store i64 [[TMP60]], i64* [[TMP62]], align 8 11319 // CHECK18-NEXT: [[TMP63:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS10]], i32 0, i32 0 11320 // CHECK18-NEXT: [[TMP64:%.*]] = bitcast i8** [[TMP63]] to i64* 11321 // CHECK18-NEXT: store i64 [[TMP60]], i64* [[TMP64]], align 8 11322 // CHECK18-NEXT: [[TMP65:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS11]], i64 0, i64 0 11323 // CHECK18-NEXT: store i8* null, i8** [[TMP65]], align 8 11324 // CHECK18-NEXT: [[TMP66:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS9]], i32 0, i32 0 11325 // CHECK18-NEXT: [[TMP67:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS10]], i32 0, i32 0 11326 // CHECK18-NEXT: [[TMP68:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.region_id, i32 1, i8** [[TMP66]], i8** [[TMP67]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.4, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.5, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 11327 // CHECK18-NEXT: [[TMP69:%.*]] = icmp ne i32 [[TMP68]], 0 11328 // CHECK18-NEXT: br i1 [[TMP69]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 11329 // CHECK18: omp_offload.failed: 11330 // CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111(i64 [[TMP60]]) #[[ATTR3]] 11331 // CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT]] 11332 // CHECK18: omp_offload.cont: 11333 // CHECK18-NEXT: [[TMP70:%.*]] = load i32, i32* [[A]], align 4 11334 // CHECK18-NEXT: [[CONV13:%.*]] = bitcast i64* [[A_CASTED12]] to i32* 11335 // CHECK18-NEXT: store i32 [[TMP70]], i32* [[CONV13]], align 4 11336 // CHECK18-NEXT: [[TMP71:%.*]] = load i64, i64* [[A_CASTED12]], align 8 11337 // CHECK18-NEXT: [[TMP72:%.*]] = load i16, i16* [[AA]], align 2 11338 // CHECK18-NEXT: [[CONV15:%.*]] = bitcast i64* [[AA_CASTED14]] to i16* 11339 // CHECK18-NEXT: store i16 [[TMP72]], i16* [[CONV15]], align 2 11340 // CHECK18-NEXT: [[TMP73:%.*]] = load i64, i64* [[AA_CASTED14]], align 8 11341 // CHECK18-NEXT: [[TMP74:%.*]] = load i32, i32* [[N_ADDR]], align 4 11342 // CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP74]], 10 11343 // CHECK18-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 11344 // CHECK18: omp_if.then: 11345 // CHECK18-NEXT: [[TMP75:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 0 11346 // CHECK18-NEXT: [[TMP76:%.*]] = bitcast i8** [[TMP75]] to i64* 11347 // CHECK18-NEXT: store i64 [[TMP71]], i64* [[TMP76]], align 8 11348 // CHECK18-NEXT: [[TMP77:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 0 11349 // CHECK18-NEXT: [[TMP78:%.*]] = bitcast i8** [[TMP77]] to i64* 11350 // CHECK18-NEXT: store i64 [[TMP71]], i64* [[TMP78]], align 8 11351 // CHECK18-NEXT: [[TMP79:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 0 11352 // CHECK18-NEXT: store i8* null, i8** [[TMP79]], align 8 11353 // CHECK18-NEXT: [[TMP80:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 1 11354 // CHECK18-NEXT: [[TMP81:%.*]] = bitcast i8** [[TMP80]] to i64* 11355 // CHECK18-NEXT: store i64 [[TMP73]], i64* [[TMP81]], align 8 11356 // CHECK18-NEXT: [[TMP82:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 1 11357 // CHECK18-NEXT: [[TMP83:%.*]] = bitcast i8** [[TMP82]] to i64* 11358 // CHECK18-NEXT: store i64 [[TMP73]], i64* [[TMP83]], align 8 11359 // CHECK18-NEXT: [[TMP84:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 1 11360 // CHECK18-NEXT: store i8* null, i8** [[TMP84]], align 8 11361 // CHECK18-NEXT: [[TMP85:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 0 11362 // CHECK18-NEXT: [[TMP86:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 0 11363 // CHECK18-NEXT: [[TMP87:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.region_id, i32 2, i8** [[TMP85]], i8** [[TMP86]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.7, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.8, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 11364 // CHECK18-NEXT: [[TMP88:%.*]] = icmp ne i32 [[TMP87]], 0 11365 // CHECK18-NEXT: br i1 [[TMP88]], label [[OMP_OFFLOAD_FAILED19:%.*]], label [[OMP_OFFLOAD_CONT20:%.*]] 11366 // CHECK18: omp_offload.failed19: 11367 // CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i64 [[TMP71]], i64 [[TMP73]]) #[[ATTR3]] 11368 // CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT20]] 11369 // CHECK18: omp_offload.cont20: 11370 // CHECK18-NEXT: br label [[OMP_IF_END:%.*]] 11371 // CHECK18: omp_if.else: 11372 // CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i64 [[TMP71]], i64 [[TMP73]]) #[[ATTR3]] 11373 // CHECK18-NEXT: br label [[OMP_IF_END]] 11374 // CHECK18: omp_if.end: 11375 // CHECK18-NEXT: [[TMP89:%.*]] = load i32, i32* [[A]], align 4 11376 // CHECK18-NEXT: [[CONV22:%.*]] = bitcast i64* [[A_CASTED21]] to i32* 11377 // CHECK18-NEXT: store i32 [[TMP89]], i32* [[CONV22]], align 4 11378 // CHECK18-NEXT: [[TMP90:%.*]] = load i64, i64* [[A_CASTED21]], align 8 11379 // CHECK18-NEXT: [[TMP91:%.*]] = load i32, i32* [[N_ADDR]], align 4 11380 // CHECK18-NEXT: [[CMP23:%.*]] = icmp sgt i32 [[TMP91]], 20 11381 // CHECK18-NEXT: br i1 [[CMP23]], label [[OMP_IF_THEN24:%.*]], label [[OMP_IF_ELSE30:%.*]] 11382 // CHECK18: omp_if.then24: 11383 // CHECK18-NEXT: [[TMP92:%.*]] = mul nuw i64 [[TMP2]], 4 11384 // CHECK18-NEXT: [[TMP93:%.*]] = mul nuw i64 5, [[TMP5]] 11385 // CHECK18-NEXT: [[TMP94:%.*]] = mul nuw i64 [[TMP93]], 8 11386 // CHECK18-NEXT: [[TMP95:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 0 11387 // CHECK18-NEXT: [[TMP96:%.*]] = bitcast i8** [[TMP95]] to i64* 11388 // CHECK18-NEXT: store i64 [[TMP90]], i64* [[TMP96]], align 8 11389 // CHECK18-NEXT: [[TMP97:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 0 11390 // CHECK18-NEXT: [[TMP98:%.*]] = bitcast i8** [[TMP97]] to i64* 11391 // CHECK18-NEXT: store i64 [[TMP90]], i64* [[TMP98]], align 8 11392 // CHECK18-NEXT: [[TMP99:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 11393 // CHECK18-NEXT: store i64 4, i64* [[TMP99]], align 8 11394 // CHECK18-NEXT: [[TMP100:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 0 11395 // CHECK18-NEXT: store i8* null, i8** [[TMP100]], align 8 11396 // CHECK18-NEXT: [[TMP101:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 1 11397 // CHECK18-NEXT: [[TMP102:%.*]] = bitcast i8** [[TMP101]] to [10 x float]** 11398 // CHECK18-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP102]], align 8 11399 // CHECK18-NEXT: [[TMP103:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 1 11400 // CHECK18-NEXT: [[TMP104:%.*]] = bitcast i8** [[TMP103]] to [10 x float]** 11401 // CHECK18-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP104]], align 8 11402 // CHECK18-NEXT: [[TMP105:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 11403 // CHECK18-NEXT: store i64 40, i64* [[TMP105]], align 8 11404 // CHECK18-NEXT: [[TMP106:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 1 11405 // CHECK18-NEXT: store i8* null, i8** [[TMP106]], align 8 11406 // CHECK18-NEXT: [[TMP107:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 2 11407 // CHECK18-NEXT: [[TMP108:%.*]] = bitcast i8** [[TMP107]] to i64* 11408 // CHECK18-NEXT: store i64 [[TMP2]], i64* [[TMP108]], align 8 11409 // CHECK18-NEXT: [[TMP109:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 2 11410 // CHECK18-NEXT: [[TMP110:%.*]] = bitcast i8** [[TMP109]] to i64* 11411 // CHECK18-NEXT: store i64 [[TMP2]], i64* [[TMP110]], align 8 11412 // CHECK18-NEXT: [[TMP111:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 11413 // CHECK18-NEXT: store i64 8, i64* [[TMP111]], align 8 11414 // CHECK18-NEXT: [[TMP112:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 2 11415 // CHECK18-NEXT: store i8* null, i8** [[TMP112]], align 8 11416 // CHECK18-NEXT: [[TMP113:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 3 11417 // CHECK18-NEXT: [[TMP114:%.*]] = bitcast i8** [[TMP113]] to float** 11418 // CHECK18-NEXT: store float* [[VLA]], float** [[TMP114]], align 8 11419 // CHECK18-NEXT: [[TMP115:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 3 11420 // CHECK18-NEXT: [[TMP116:%.*]] = bitcast i8** [[TMP115]] to float** 11421 // CHECK18-NEXT: store float* [[VLA]], float** [[TMP116]], align 8 11422 // CHECK18-NEXT: [[TMP117:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 11423 // CHECK18-NEXT: store i64 [[TMP92]], i64* [[TMP117]], align 8 11424 // CHECK18-NEXT: [[TMP118:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 3 11425 // CHECK18-NEXT: store i8* null, i8** [[TMP118]], align 8 11426 // CHECK18-NEXT: [[TMP119:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 4 11427 // CHECK18-NEXT: [[TMP120:%.*]] = bitcast i8** [[TMP119]] to [5 x [10 x double]]** 11428 // CHECK18-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP120]], align 8 11429 // CHECK18-NEXT: [[TMP121:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 4 11430 // CHECK18-NEXT: [[TMP122:%.*]] = bitcast i8** [[TMP121]] to [5 x [10 x double]]** 11431 // CHECK18-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP122]], align 8 11432 // CHECK18-NEXT: [[TMP123:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 11433 // CHECK18-NEXT: store i64 400, i64* [[TMP123]], align 8 11434 // CHECK18-NEXT: [[TMP124:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 4 11435 // CHECK18-NEXT: store i8* null, i8** [[TMP124]], align 8 11436 // CHECK18-NEXT: [[TMP125:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 5 11437 // CHECK18-NEXT: [[TMP126:%.*]] = bitcast i8** [[TMP125]] to i64* 11438 // CHECK18-NEXT: store i64 5, i64* [[TMP126]], align 8 11439 // CHECK18-NEXT: [[TMP127:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 5 11440 // CHECK18-NEXT: [[TMP128:%.*]] = bitcast i8** [[TMP127]] to i64* 11441 // CHECK18-NEXT: store i64 5, i64* [[TMP128]], align 8 11442 // CHECK18-NEXT: [[TMP129:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 5 11443 // CHECK18-NEXT: store i64 8, i64* [[TMP129]], align 8 11444 // CHECK18-NEXT: [[TMP130:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 5 11445 // CHECK18-NEXT: store i8* null, i8** [[TMP130]], align 8 11446 // CHECK18-NEXT: [[TMP131:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 6 11447 // CHECK18-NEXT: [[TMP132:%.*]] = bitcast i8** [[TMP131]] to i64* 11448 // CHECK18-NEXT: store i64 [[TMP5]], i64* [[TMP132]], align 8 11449 // CHECK18-NEXT: [[TMP133:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 6 11450 // CHECK18-NEXT: [[TMP134:%.*]] = bitcast i8** [[TMP133]] to i64* 11451 // CHECK18-NEXT: store i64 [[TMP5]], i64* [[TMP134]], align 8 11452 // CHECK18-NEXT: [[TMP135:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 6 11453 // CHECK18-NEXT: store i64 8, i64* [[TMP135]], align 8 11454 // CHECK18-NEXT: [[TMP136:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 6 11455 // CHECK18-NEXT: store i8* null, i8** [[TMP136]], align 8 11456 // CHECK18-NEXT: [[TMP137:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 7 11457 // CHECK18-NEXT: [[TMP138:%.*]] = bitcast i8** [[TMP137]] to double** 11458 // CHECK18-NEXT: store double* [[VLA1]], double** [[TMP138]], align 8 11459 // CHECK18-NEXT: [[TMP139:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 7 11460 // CHECK18-NEXT: [[TMP140:%.*]] = bitcast i8** [[TMP139]] to double** 11461 // CHECK18-NEXT: store double* [[VLA1]], double** [[TMP140]], align 8 11462 // CHECK18-NEXT: [[TMP141:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 11463 // CHECK18-NEXT: store i64 [[TMP94]], i64* [[TMP141]], align 8 11464 // CHECK18-NEXT: [[TMP142:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 7 11465 // CHECK18-NEXT: store i8* null, i8** [[TMP142]], align 8 11466 // CHECK18-NEXT: [[TMP143:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 8 11467 // CHECK18-NEXT: [[TMP144:%.*]] = bitcast i8** [[TMP143]] to %struct.TT** 11468 // CHECK18-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP144]], align 8 11469 // CHECK18-NEXT: [[TMP145:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 8 11470 // CHECK18-NEXT: [[TMP146:%.*]] = bitcast i8** [[TMP145]] to %struct.TT** 11471 // CHECK18-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP146]], align 8 11472 // CHECK18-NEXT: [[TMP147:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 8 11473 // CHECK18-NEXT: store i64 16, i64* [[TMP147]], align 8 11474 // CHECK18-NEXT: [[TMP148:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 8 11475 // CHECK18-NEXT: store i8* null, i8** [[TMP148]], align 8 11476 // CHECK18-NEXT: [[TMP149:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 0 11477 // CHECK18-NEXT: [[TMP150:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 0 11478 // CHECK18-NEXT: [[TMP151:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 11479 // CHECK18-NEXT: [[TMP152:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142.region_id, i32 9, i8** [[TMP149]], i8** [[TMP150]], i64* [[TMP151]], i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 11480 // CHECK18-NEXT: [[TMP153:%.*]] = icmp ne i32 [[TMP152]], 0 11481 // CHECK18-NEXT: br i1 [[TMP153]], label [[OMP_OFFLOAD_FAILED28:%.*]], label [[OMP_OFFLOAD_CONT29:%.*]] 11482 // CHECK18: omp_offload.failed28: 11483 // CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i64 [[TMP90]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR3]] 11484 // CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT29]] 11485 // CHECK18: omp_offload.cont29: 11486 // CHECK18-NEXT: br label [[OMP_IF_END31:%.*]] 11487 // CHECK18: omp_if.else30: 11488 // CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i64 [[TMP90]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR3]] 11489 // CHECK18-NEXT: br label [[OMP_IF_END31]] 11490 // CHECK18: omp_if.end31: 11491 // CHECK18-NEXT: store i32 0, i32* [[NN]], align 4 11492 // CHECK18-NEXT: [[TMP154:%.*]] = load i32, i32* [[NN]], align 4 11493 // CHECK18-NEXT: [[CONV32:%.*]] = bitcast i64* [[NN_CASTED]] to i32* 11494 // CHECK18-NEXT: store i32 [[TMP154]], i32* [[CONV32]], align 4 11495 // CHECK18-NEXT: [[TMP155:%.*]] = load i64, i64* [[NN_CASTED]], align 8 11496 // CHECK18-NEXT: [[TMP156:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS33]], i32 0, i32 0 11497 // CHECK18-NEXT: [[TMP157:%.*]] = bitcast i8** [[TMP156]] to i64* 11498 // CHECK18-NEXT: store i64 [[TMP155]], i64* [[TMP157]], align 8 11499 // CHECK18-NEXT: [[TMP158:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS34]], i32 0, i32 0 11500 // CHECK18-NEXT: [[TMP159:%.*]] = bitcast i8** [[TMP158]] to i64* 11501 // CHECK18-NEXT: store i64 [[TMP155]], i64* [[TMP159]], align 8 11502 // CHECK18-NEXT: [[TMP160:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS35]], i64 0, i64 0 11503 // CHECK18-NEXT: store i8* null, i8** [[TMP160]], align 8 11504 // CHECK18-NEXT: [[TMP161:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS33]], i32 0, i32 0 11505 // CHECK18-NEXT: [[TMP162:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS34]], i32 0, i32 0 11506 // CHECK18-NEXT: [[TMP163:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154.region_id, i32 1, i8** [[TMP161]], i8** [[TMP162]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.13, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.14, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 11507 // CHECK18-NEXT: [[TMP164:%.*]] = icmp ne i32 [[TMP163]], 0 11508 // CHECK18-NEXT: br i1 [[TMP164]], label [[OMP_OFFLOAD_FAILED36:%.*]], label [[OMP_OFFLOAD_CONT37:%.*]] 11509 // CHECK18: omp_offload.failed36: 11510 // CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154(i64 [[TMP155]]) #[[ATTR3]] 11511 // CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT37]] 11512 // CHECK18: omp_offload.cont37: 11513 // CHECK18-NEXT: [[TMP165:%.*]] = load i32, i32* [[NN]], align 4 11514 // CHECK18-NEXT: [[CONV39:%.*]] = bitcast i64* [[NN_CASTED38]] to i32* 11515 // CHECK18-NEXT: store i32 [[TMP165]], i32* [[CONV39]], align 4 11516 // CHECK18-NEXT: [[TMP166:%.*]] = load i64, i64* [[NN_CASTED38]], align 8 11517 // CHECK18-NEXT: [[TMP167:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS40]], i32 0, i32 0 11518 // CHECK18-NEXT: [[TMP168:%.*]] = bitcast i8** [[TMP167]] to i64* 11519 // CHECK18-NEXT: store i64 [[TMP166]], i64* [[TMP168]], align 8 11520 // CHECK18-NEXT: [[TMP169:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS41]], i32 0, i32 0 11521 // CHECK18-NEXT: [[TMP170:%.*]] = bitcast i8** [[TMP169]] to i64* 11522 // CHECK18-NEXT: store i64 [[TMP166]], i64* [[TMP170]], align 8 11523 // CHECK18-NEXT: [[TMP171:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS42]], i64 0, i64 0 11524 // CHECK18-NEXT: store i8* null, i8** [[TMP171]], align 8 11525 // CHECK18-NEXT: [[TMP172:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS40]], i32 0, i32 0 11526 // CHECK18-NEXT: [[TMP173:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS41]], i32 0, i32 0 11527 // CHECK18-NEXT: [[TMP174:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157.region_id, i32 1, i8** [[TMP172]], i8** [[TMP173]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.17, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.18, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 11528 // CHECK18-NEXT: [[TMP175:%.*]] = icmp ne i32 [[TMP174]], 0 11529 // CHECK18-NEXT: br i1 [[TMP175]], label [[OMP_OFFLOAD_FAILED43:%.*]], label [[OMP_OFFLOAD_CONT44:%.*]] 11530 // CHECK18: omp_offload.failed43: 11531 // CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157(i64 [[TMP166]]) #[[ATTR3]] 11532 // CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT44]] 11533 // CHECK18: omp_offload.cont44: 11534 // CHECK18-NEXT: [[TMP176:%.*]] = load i32, i32* [[A]], align 4 11535 // CHECK18-NEXT: [[TMP177:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 11536 // CHECK18-NEXT: call void @llvm.stackrestore(i8* [[TMP177]]) 11537 // CHECK18-NEXT: ret i32 [[TMP176]] 11538 // 11539 // 11540 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101 11541 // CHECK18-SAME: (i64 [[AA:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] { 11542 // CHECK18-NEXT: entry: 11543 // CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 11544 // CHECK18-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 11545 // CHECK18-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8 11546 // CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 11547 // CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 11548 // CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 11549 // CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 11550 // CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8 11551 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 11552 // CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* 11553 // CHECK18-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32* 11554 // CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 8 11555 // CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 8 11556 // CHECK18-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) 11557 // CHECK18-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 8 11558 // CHECK18-NEXT: [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 11559 // CHECK18-NEXT: store i16 [[TMP3]], i16* [[CONV5]], align 2 11560 // CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 11561 // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]]) 11562 // CHECK18-NEXT: ret void 11563 // 11564 // 11565 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined. 11566 // CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] { 11567 // CHECK18-NEXT: entry: 11568 // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 11569 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 11570 // CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 11571 // CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 11572 // CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 11573 // CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 11574 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 11575 // CHECK18-NEXT: ret void 11576 // 11577 // 11578 // CHECK18-LABEL: define {{[^@]+}}@.omp_task_privates_map. 11579 // CHECK18-SAME: (%struct..kmp_privates.t* noalias [[TMP0:%.*]], i16** noalias [[TMP1:%.*]], [3 x i8*]** noalias [[TMP2:%.*]], [3 x i8*]** noalias [[TMP3:%.*]], [3 x i64]** noalias [[TMP4:%.*]]) #[[ATTR4:[0-9]+]] { 11580 // CHECK18-NEXT: entry: 11581 // CHECK18-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 8 11582 // CHECK18-NEXT: [[DOTADDR1:%.*]] = alloca i16**, align 8 11583 // CHECK18-NEXT: [[DOTADDR2:%.*]] = alloca [3 x i8*]**, align 8 11584 // CHECK18-NEXT: [[DOTADDR3:%.*]] = alloca [3 x i8*]**, align 8 11585 // CHECK18-NEXT: [[DOTADDR4:%.*]] = alloca [3 x i64]**, align 8 11586 // CHECK18-NEXT: store %struct..kmp_privates.t* [[TMP0]], %struct..kmp_privates.t** [[DOTADDR]], align 8 11587 // CHECK18-NEXT: store i16** [[TMP1]], i16*** [[DOTADDR1]], align 8 11588 // CHECK18-NEXT: store [3 x i8*]** [[TMP2]], [3 x i8*]*** [[DOTADDR2]], align 8 11589 // CHECK18-NEXT: store [3 x i8*]** [[TMP3]], [3 x i8*]*** [[DOTADDR3]], align 8 11590 // CHECK18-NEXT: store [3 x i64]** [[TMP4]], [3 x i64]*** [[DOTADDR4]], align 8 11591 // CHECK18-NEXT: [[TMP5:%.*]] = load %struct..kmp_privates.t*, %struct..kmp_privates.t** [[DOTADDR]], align 8 11592 // CHECK18-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 0 11593 // CHECK18-NEXT: [[TMP7:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR2]], align 8 11594 // CHECK18-NEXT: store [3 x i8*]* [[TMP6]], [3 x i8*]** [[TMP7]], align 8 11595 // CHECK18-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 1 11596 // CHECK18-NEXT: [[TMP9:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR3]], align 8 11597 // CHECK18-NEXT: store [3 x i8*]* [[TMP8]], [3 x i8*]** [[TMP9]], align 8 11598 // CHECK18-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 2 11599 // CHECK18-NEXT: [[TMP11:%.*]] = load [3 x i64]**, [3 x i64]*** [[DOTADDR4]], align 8 11600 // CHECK18-NEXT: store [3 x i64]* [[TMP10]], [3 x i64]** [[TMP11]], align 8 11601 // CHECK18-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 3 11602 // CHECK18-NEXT: [[TMP13:%.*]] = load i16**, i16*** [[DOTADDR1]], align 8 11603 // CHECK18-NEXT: store i16* [[TMP12]], i16** [[TMP13]], align 8 11604 // CHECK18-NEXT: ret void 11605 // 11606 // 11607 // CHECK18-LABEL: define {{[^@]+}}@.omp_task_entry. 11608 // CHECK18-SAME: (i32 signext [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { 11609 // CHECK18-NEXT: entry: 11610 // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 11611 // CHECK18-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 11612 // CHECK18-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8 11613 // CHECK18-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8 11614 // CHECK18-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8 11615 // CHECK18-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 8 11616 // CHECK18-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca i16*, align 8 11617 // CHECK18-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca [3 x i8*]*, align 8 11618 // CHECK18-NEXT: [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca [3 x i8*]*, align 8 11619 // CHECK18-NEXT: [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca [3 x i64]*, align 8 11620 // CHECK18-NEXT: [[AA_CASTED_I:%.*]] = alloca i64, align 8 11621 // CHECK18-NEXT: [[DOTCAPTURE_EXPR__CASTED_I:%.*]] = alloca i64, align 8 11622 // CHECK18-NEXT: [[DOTCAPTURE_EXPR__CASTED5_I:%.*]] = alloca i64, align 8 11623 // CHECK18-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 11624 // CHECK18-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8 11625 // CHECK18-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 11626 // CHECK18-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 11627 // CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 11628 // CHECK18-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 11629 // CHECK18-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0 11630 // CHECK18-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 11631 // CHECK18-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 11632 // CHECK18-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 11633 // CHECK18-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon* 11634 // CHECK18-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1 11635 // CHECK18-NEXT: [[TMP10:%.*]] = bitcast %struct..kmp_privates.t* [[TMP9]] to i8* 11636 // CHECK18-NEXT: [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8* 11637 // CHECK18-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META14:![0-9]+]]) 11638 // CHECK18-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META17:![0-9]+]]) 11639 // CHECK18-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]]) 11640 // CHECK18-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META21:![0-9]+]]) 11641 // CHECK18-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !23 11642 // CHECK18-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !23 11643 // CHECK18-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !23 11644 // CHECK18-NEXT: store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* @.omp_task_privates_map. to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !23 11645 // CHECK18-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !23 11646 // CHECK18-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !23 11647 // CHECK18-NEXT: [[TMP12:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !23 11648 // CHECK18-NEXT: [[TMP13:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !23 11649 // CHECK18-NEXT: [[TMP14:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !23 11650 // CHECK18-NEXT: [[TMP15:%.*]] = bitcast void (i8*, ...)* [[TMP13]] to void (i8*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* 11651 // CHECK18-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]] 11652 // CHECK18-NEXT: [[TMP16:%.*]] = load i16*, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !23 11653 // CHECK18-NEXT: [[TMP17:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !23 11654 // CHECK18-NEXT: [[TMP18:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 8, !noalias !23 11655 // CHECK18-NEXT: [[TMP19:%.*]] = load [3 x i64]*, [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 8, !noalias !23 11656 // CHECK18-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP17]], i64 0, i64 0 11657 // CHECK18-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP18]], i64 0, i64 0 11658 // CHECK18-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[TMP19]], i64 0, i64 0 11659 // CHECK18-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP12]], i32 0, i32 1 11660 // CHECK18-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[TMP12]], i32 0, i32 2 11661 // CHECK18-NEXT: [[TMP25:%.*]] = load i32, i32* [[TMP23]], align 4 11662 // CHECK18-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP24]], align 4 11663 // CHECK18-NEXT: [[TMP27:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 [[TMP25]], i32 [[TMP26]]) #[[ATTR3]] 11664 // CHECK18-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0 11665 // CHECK18-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]] 11666 // CHECK18: omp_offload.failed.i: 11667 // CHECK18-NEXT: [[TMP29:%.*]] = load i16, i16* [[TMP16]], align 2 11668 // CHECK18-NEXT: [[CONV_I:%.*]] = bitcast i64* [[AA_CASTED_I]] to i16* 11669 // CHECK18-NEXT: store i16 [[TMP29]], i16* [[CONV_I]], align 2, !noalias !23 11670 // CHECK18-NEXT: [[TMP30:%.*]] = load i64, i64* [[AA_CASTED_I]], align 8, !noalias !23 11671 // CHECK18-NEXT: [[TMP31:%.*]] = load i32, i32* [[TMP23]], align 4 11672 // CHECK18-NEXT: [[CONV4_I:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED_I]] to i32* 11673 // CHECK18-NEXT: store i32 [[TMP31]], i32* [[CONV4_I]], align 4, !noalias !23 11674 // CHECK18-NEXT: [[TMP32:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED_I]], align 8, !noalias !23 11675 // CHECK18-NEXT: [[TMP33:%.*]] = load i32, i32* [[TMP24]], align 4 11676 // CHECK18-NEXT: [[CONV6_I:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED5_I]] to i32* 11677 // CHECK18-NEXT: store i32 [[TMP33]], i32* [[CONV6_I]], align 4, !noalias !23 11678 // CHECK18-NEXT: [[TMP34:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED5_I]], align 8, !noalias !23 11679 // CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101(i64 [[TMP30]], i64 [[TMP32]], i64 [[TMP34]]) #[[ATTR3]] 11680 // CHECK18-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]] 11681 // CHECK18: .omp_outlined..1.exit: 11682 // CHECK18-NEXT: ret i32 0 11683 // 11684 // 11685 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l105 11686 // CHECK18-SAME: (i64 [[A:%.*]]) #[[ATTR2]] { 11687 // CHECK18-NEXT: entry: 11688 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 11689 // CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 11690 // CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 11691 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 11692 // CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 11693 // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32* 11694 // CHECK18-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 11695 // CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 11696 // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]]) 11697 // CHECK18-NEXT: ret void 11698 // 11699 // 11700 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..2 11701 // CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]]) #[[ATTR2]] { 11702 // CHECK18-NEXT: entry: 11703 // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 11704 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 11705 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 11706 // CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 11707 // CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 11708 // CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 11709 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 11710 // CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 11711 // CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 11712 // CHECK18-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 11713 // CHECK18-NEXT: ret void 11714 // 11715 // 11716 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 11717 // CHECK18-SAME: (i64 [[AA:%.*]]) #[[ATTR2]] { 11718 // CHECK18-NEXT: entry: 11719 // CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 11720 // CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 11721 // CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 11722 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 11723 // CHECK18-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8 11724 // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 11725 // CHECK18-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 11726 // CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 11727 // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP1]]) 11728 // CHECK18-NEXT: ret void 11729 // 11730 // 11731 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..3 11732 // CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] { 11733 // CHECK18-NEXT: entry: 11734 // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 11735 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 11736 // CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 11737 // CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 11738 // CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 11739 // CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 11740 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 11741 // CHECK18-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8 11742 // CHECK18-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 11743 // CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 11744 // CHECK18-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 11745 // CHECK18-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 8 11746 // CHECK18-NEXT: ret void 11747 // 11748 // 11749 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118 11750 // CHECK18-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] { 11751 // CHECK18-NEXT: entry: 11752 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 11753 // CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 11754 // CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 11755 // CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 11756 // CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 11757 // CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 11758 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 11759 // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 11760 // CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 11761 // CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* 11762 // CHECK18-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 11763 // CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 11764 // CHECK18-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 11765 // CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 11766 // CHECK18-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 11767 // CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 11768 // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) 11769 // CHECK18-NEXT: ret void 11770 // 11771 // 11772 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..6 11773 // CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] { 11774 // CHECK18-NEXT: entry: 11775 // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 11776 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 11777 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 11778 // CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 11779 // CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 11780 // CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 11781 // CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 11782 // CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 11783 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 11784 // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 11785 // CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 11786 // CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 11787 // CHECK18-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 11788 // CHECK18-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 8 11789 // CHECK18-NEXT: [[CONV2:%.*]] = sext i16 [[TMP1]] to i32 11790 // CHECK18-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 11791 // CHECK18-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 11792 // CHECK18-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 8 11793 // CHECK18-NEXT: ret void 11794 // 11795 // 11796 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142 11797 // CHECK18-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] { 11798 // CHECK18-NEXT: entry: 11799 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 11800 // CHECK18-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 11801 // CHECK18-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 11802 // CHECK18-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 11803 // CHECK18-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 11804 // CHECK18-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 11805 // CHECK18-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 11806 // CHECK18-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 11807 // CHECK18-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 11808 // CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 11809 // CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 11810 // CHECK18-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 11811 // CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 11812 // CHECK18-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 11813 // CHECK18-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 11814 // CHECK18-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 11815 // CHECK18-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 11816 // CHECK18-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 11817 // CHECK18-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 11818 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 11819 // CHECK18-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 11820 // CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 11821 // CHECK18-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 11822 // CHECK18-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 11823 // CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 11824 // CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 11825 // CHECK18-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 11826 // CHECK18-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 11827 // CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 11828 // CHECK18-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* 11829 // CHECK18-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4 11830 // CHECK18-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 11831 // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) 11832 // CHECK18-NEXT: ret void 11833 // 11834 // 11835 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..9 11836 // CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] { 11837 // CHECK18-NEXT: entry: 11838 // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 11839 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 11840 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 11841 // CHECK18-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 11842 // CHECK18-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 11843 // CHECK18-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 11844 // CHECK18-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 11845 // CHECK18-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 11846 // CHECK18-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 11847 // CHECK18-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 11848 // CHECK18-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 11849 // CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 11850 // CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 11851 // CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 11852 // CHECK18-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 11853 // CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 11854 // CHECK18-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 11855 // CHECK18-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 11856 // CHECK18-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 11857 // CHECK18-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 11858 // CHECK18-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 11859 // CHECK18-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 11860 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 11861 // CHECK18-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 11862 // CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 11863 // CHECK18-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 11864 // CHECK18-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 11865 // CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 11866 // CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 11867 // CHECK18-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 11868 // CHECK18-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 11869 // CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 11870 // CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 11871 // CHECK18-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 11872 // CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 11873 // CHECK18-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 11874 // CHECK18-NEXT: [[CONV5:%.*]] = fpext float [[TMP9]] to double 11875 // CHECK18-NEXT: [[ADD6:%.*]] = fadd double [[CONV5]], 1.000000e+00 11876 // CHECK18-NEXT: [[CONV7:%.*]] = fptrunc double [[ADD6]] to float 11877 // CHECK18-NEXT: store float [[CONV7]], float* [[ARRAYIDX]], align 4 11878 // CHECK18-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 11879 // CHECK18-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX8]], align 4 11880 // CHECK18-NEXT: [[CONV9:%.*]] = fpext float [[TMP10]] to double 11881 // CHECK18-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 11882 // CHECK18-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float 11883 // CHECK18-NEXT: store float [[CONV11]], float* [[ARRAYIDX8]], align 4 11884 // CHECK18-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1 11885 // CHECK18-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX12]], i64 0, i64 2 11886 // CHECK18-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX13]], align 8 11887 // CHECK18-NEXT: [[ADD14:%.*]] = fadd double [[TMP11]], 1.000000e+00 11888 // CHECK18-NEXT: store double [[ADD14]], double* [[ARRAYIDX13]], align 8 11889 // CHECK18-NEXT: [[TMP12:%.*]] = mul nsw i64 1, [[TMP5]] 11890 // CHECK18-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP12]] 11891 // CHECK18-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX15]], i64 3 11892 // CHECK18-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX16]], align 8 11893 // CHECK18-NEXT: [[ADD17:%.*]] = fadd double [[TMP13]], 1.000000e+00 11894 // CHECK18-NEXT: store double [[ADD17]], double* [[ARRAYIDX16]], align 8 11895 // CHECK18-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 11896 // CHECK18-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 8 11897 // CHECK18-NEXT: [[ADD18:%.*]] = add nsw i64 [[TMP14]], 1 11898 // CHECK18-NEXT: store i64 [[ADD18]], i64* [[X]], align 8 11899 // CHECK18-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 11900 // CHECK18-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 8 11901 // CHECK18-NEXT: [[CONV19:%.*]] = sext i8 [[TMP15]] to i32 11902 // CHECK18-NEXT: [[ADD20:%.*]] = add nsw i32 [[CONV19]], 1 11903 // CHECK18-NEXT: [[CONV21:%.*]] = trunc i32 [[ADD20]] to i8 11904 // CHECK18-NEXT: store i8 [[CONV21]], i8* [[Y]], align 8 11905 // CHECK18-NEXT: ret void 11906 // 11907 // 11908 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154 11909 // CHECK18-SAME: (i64 [[NN:%.*]]) #[[ATTR2]] { 11910 // CHECK18-NEXT: entry: 11911 // CHECK18-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 11912 // CHECK18-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 11913 // CHECK18-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 11914 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* 11915 // CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 11916 // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32* 11917 // CHECK18-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 11918 // CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8 11919 // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP1]]) 11920 // CHECK18-NEXT: ret void 11921 // 11922 // 11923 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..11 11924 // CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[NN:%.*]]) #[[ATTR2]] { 11925 // CHECK18-NEXT: entry: 11926 // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 11927 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 11928 // CHECK18-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 11929 // CHECK18-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 11930 // CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 11931 // CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 11932 // CHECK18-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 11933 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* 11934 // CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 11935 // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32* 11936 // CHECK18-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 11937 // CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8 11938 // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..12 to void (i32*, i32*, ...)*), i64 [[TMP1]]) 11939 // CHECK18-NEXT: ret void 11940 // 11941 // 11942 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..12 11943 // CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[NN:%.*]]) #[[ATTR2]] { 11944 // CHECK18-NEXT: entry: 11945 // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 11946 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 11947 // CHECK18-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 11948 // CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 11949 // CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 11950 // CHECK18-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 11951 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* 11952 // CHECK18-NEXT: ret void 11953 // 11954 // 11955 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157 11956 // CHECK18-SAME: (i64 [[NN:%.*]]) #[[ATTR2]] { 11957 // CHECK18-NEXT: entry: 11958 // CHECK18-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 11959 // CHECK18-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 11960 // CHECK18-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 11961 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* 11962 // CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 11963 // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32* 11964 // CHECK18-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 11965 // CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8 11966 // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i64 [[TMP1]]) 11967 // CHECK18-NEXT: ret void 11968 // 11969 // 11970 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..15 11971 // CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[NN:%.*]]) #[[ATTR2]] { 11972 // CHECK18-NEXT: entry: 11973 // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 11974 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 11975 // CHECK18-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 11976 // CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 11977 // CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 11978 // CHECK18-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 11979 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* 11980 // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i32* [[CONV]]) 11981 // CHECK18-NEXT: ret void 11982 // 11983 // 11984 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..16 11985 // CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[NN:%.*]]) #[[ATTR2]] { 11986 // CHECK18-NEXT: entry: 11987 // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 11988 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 11989 // CHECK18-NEXT: [[NN_ADDR:%.*]] = alloca i32*, align 8 11990 // CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 11991 // CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 11992 // CHECK18-NEXT: store i32* [[NN]], i32** [[NN_ADDR]], align 8 11993 // CHECK18-NEXT: [[TMP0:%.*]] = load i32*, i32** [[NN_ADDR]], align 8 11994 // CHECK18-NEXT: ret void 11995 // 11996 // 11997 // CHECK18-LABEL: define {{[^@]+}}@_Z6bazzzziPi 11998 // CHECK18-SAME: (i32 signext [[N:%.*]], i32* [[F:%.*]]) #[[ATTR0]] { 11999 // CHECK18-NEXT: entry: 12000 // CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 12001 // CHECK18-NEXT: [[F_ADDR:%.*]] = alloca i32*, align 8 12002 // CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 12003 // CHECK18-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 12004 // CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 12005 // CHECK18-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 12006 // CHECK18-NEXT: store i32* [[F]], i32** [[F_ADDR]], align 8 12007 // CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 12008 // CHECK18-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 12009 // CHECK18-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 12010 // CHECK18-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to i64* 12011 // CHECK18-NEXT: store i64 [[TMP1]], i64* [[TMP3]], align 8 12012 // CHECK18-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 12013 // CHECK18-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i64* 12014 // CHECK18-NEXT: store i64 [[TMP1]], i64* [[TMP5]], align 8 12015 // CHECK18-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 12016 // CHECK18-NEXT: store i8* null, i8** [[TMP6]], align 8 12017 // CHECK18-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 12018 // CHECK18-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 12019 // CHECK18-NEXT: [[TMP9:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182.region_id, i32 1, i8** [[TMP7]], i8** [[TMP8]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.20, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.21, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 12020 // CHECK18-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 12021 // CHECK18-NEXT: br i1 [[TMP10]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 12022 // CHECK18: omp_offload.failed: 12023 // CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182(i64 [[TMP1]]) #[[ATTR3]] 12024 // CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT]] 12025 // CHECK18: omp_offload.cont: 12026 // CHECK18-NEXT: ret void 12027 // 12028 // 12029 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182 12030 // CHECK18-SAME: (i64 [[VLA:%.*]]) #[[ATTR2]] { 12031 // CHECK18-NEXT: entry: 12032 // CHECK18-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 12033 // CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 12034 // CHECK18-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 12035 // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..19 to void (i32*, i32*, ...)*), i64 [[TMP0]]) 12036 // CHECK18-NEXT: ret void 12037 // 12038 // 12039 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..19 12040 // CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[VLA:%.*]]) #[[ATTR2]] { 12041 // CHECK18-NEXT: entry: 12042 // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 12043 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 12044 // CHECK18-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 12045 // CHECK18-NEXT: [[F:%.*]] = alloca i32*, align 8 12046 // CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 12047 // CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 12048 // CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 12049 // CHECK18-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 12050 // CHECK18-NEXT: ret void 12051 // 12052 // 12053 // CHECK18-LABEL: define {{[^@]+}}@_Z3bari 12054 // CHECK18-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { 12055 // CHECK18-NEXT: entry: 12056 // CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 12057 // CHECK18-NEXT: [[A:%.*]] = alloca i32, align 4 12058 // CHECK18-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 12059 // CHECK18-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 12060 // CHECK18-NEXT: store i32 0, i32* [[A]], align 4 12061 // CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 12062 // CHECK18-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]]) 12063 // CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 12064 // CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 12065 // CHECK18-NEXT: store i32 [[ADD]], i32* [[A]], align 4 12066 // CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 12067 // CHECK18-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]]) 12068 // CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 12069 // CHECK18-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 12070 // CHECK18-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 12071 // CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 12072 // CHECK18-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]]) 12073 // CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 12074 // CHECK18-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 12075 // CHECK18-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 12076 // CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 12077 // CHECK18-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]]) 12078 // CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 12079 // CHECK18-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] 12080 // CHECK18-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 12081 // CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 12082 // CHECK18-NEXT: ret i32 [[TMP8]] 12083 // 12084 // 12085 // CHECK18-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 12086 // CHECK18-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { 12087 // CHECK18-NEXT: entry: 12088 // CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 12089 // CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 12090 // CHECK18-NEXT: [[B:%.*]] = alloca i32, align 4 12091 // CHECK18-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 12092 // CHECK18-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 12093 // CHECK18-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 12094 // CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8 12095 // CHECK18-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8 12096 // CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8 12097 // CHECK18-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 8 12098 // CHECK18-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 12099 // CHECK18-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 12100 // CHECK18-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 12101 // CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 12102 // CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 12103 // CHECK18-NEXT: store i32 [[ADD]], i32* [[B]], align 4 12104 // CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 12105 // CHECK18-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 12106 // CHECK18-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() 12107 // CHECK18-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 12108 // CHECK18-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] 12109 // CHECK18-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 12110 // CHECK18-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 12111 // CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 12112 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32* 12113 // CHECK18-NEXT: store i32 [[TMP5]], i32* [[CONV]], align 4 12114 // CHECK18-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 12115 // CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4 12116 // CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 60 12117 // CHECK18-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 12118 // CHECK18: omp_if.then: 12119 // CHECK18-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 12120 // CHECK18-NEXT: [[TMP8:%.*]] = mul nuw i64 2, [[TMP2]] 12121 // CHECK18-NEXT: [[TMP9:%.*]] = mul nuw i64 [[TMP8]], 2 12122 // CHECK18-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 12123 // CHECK18-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to %struct.S1** 12124 // CHECK18-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP11]], align 8 12125 // CHECK18-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 12126 // CHECK18-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to double** 12127 // CHECK18-NEXT: store double* [[A]], double** [[TMP13]], align 8 12128 // CHECK18-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 12129 // CHECK18-NEXT: store i64 8, i64* [[TMP14]], align 8 12130 // CHECK18-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 12131 // CHECK18-NEXT: store i8* null, i8** [[TMP15]], align 8 12132 // CHECK18-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 12133 // CHECK18-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64* 12134 // CHECK18-NEXT: store i64 [[TMP6]], i64* [[TMP17]], align 8 12135 // CHECK18-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 12136 // CHECK18-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64* 12137 // CHECK18-NEXT: store i64 [[TMP6]], i64* [[TMP19]], align 8 12138 // CHECK18-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 12139 // CHECK18-NEXT: store i64 4, i64* [[TMP20]], align 8 12140 // CHECK18-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 12141 // CHECK18-NEXT: store i8* null, i8** [[TMP21]], align 8 12142 // CHECK18-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 12143 // CHECK18-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i64* 12144 // CHECK18-NEXT: store i64 2, i64* [[TMP23]], align 8 12145 // CHECK18-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 12146 // CHECK18-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i64* 12147 // CHECK18-NEXT: store i64 2, i64* [[TMP25]], align 8 12148 // CHECK18-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 12149 // CHECK18-NEXT: store i64 8, i64* [[TMP26]], align 8 12150 // CHECK18-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 12151 // CHECK18-NEXT: store i8* null, i8** [[TMP27]], align 8 12152 // CHECK18-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 12153 // CHECK18-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i64* 12154 // CHECK18-NEXT: store i64 [[TMP2]], i64* [[TMP29]], align 8 12155 // CHECK18-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 12156 // CHECK18-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i64* 12157 // CHECK18-NEXT: store i64 [[TMP2]], i64* [[TMP31]], align 8 12158 // CHECK18-NEXT: [[TMP32:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 12159 // CHECK18-NEXT: store i64 8, i64* [[TMP32]], align 8 12160 // CHECK18-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 12161 // CHECK18-NEXT: store i8* null, i8** [[TMP33]], align 8 12162 // CHECK18-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 12163 // CHECK18-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i16** 12164 // CHECK18-NEXT: store i16* [[VLA]], i16** [[TMP35]], align 8 12165 // CHECK18-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 12166 // CHECK18-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i16** 12167 // CHECK18-NEXT: store i16* [[VLA]], i16** [[TMP37]], align 8 12168 // CHECK18-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 12169 // CHECK18-NEXT: store i64 [[TMP9]], i64* [[TMP38]], align 8 12170 // CHECK18-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 12171 // CHECK18-NEXT: store i8* null, i8** [[TMP39]], align 8 12172 // CHECK18-NEXT: [[TMP40:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 12173 // CHECK18-NEXT: [[TMP41:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 12174 // CHECK18-NEXT: [[TMP42:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 12175 // CHECK18-NEXT: [[TMP43:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227.region_id, i32 5, i8** [[TMP40]], i8** [[TMP41]], i64* [[TMP42]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.23, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 12176 // CHECK18-NEXT: [[TMP44:%.*]] = icmp ne i32 [[TMP43]], 0 12177 // CHECK18-NEXT: br i1 [[TMP44]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 12178 // CHECK18: omp_offload.failed: 12179 // CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR3]] 12180 // CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT]] 12181 // CHECK18: omp_offload.cont: 12182 // CHECK18-NEXT: br label [[OMP_IF_END:%.*]] 12183 // CHECK18: omp_if.else: 12184 // CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR3]] 12185 // CHECK18-NEXT: br label [[OMP_IF_END]] 12186 // CHECK18: omp_if.end: 12187 // CHECK18-NEXT: [[TMP45:%.*]] = mul nsw i64 1, [[TMP2]] 12188 // CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP45]] 12189 // CHECK18-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 12190 // CHECK18-NEXT: [[TMP46:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2 12191 // CHECK18-NEXT: [[CONV3:%.*]] = sext i16 [[TMP46]] to i32 12192 // CHECK18-NEXT: [[TMP47:%.*]] = load i32, i32* [[B]], align 4 12193 // CHECK18-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], [[TMP47]] 12194 // CHECK18-NEXT: [[TMP48:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 12195 // CHECK18-NEXT: call void @llvm.stackrestore(i8* [[TMP48]]) 12196 // CHECK18-NEXT: ret i32 [[ADD4]] 12197 // 12198 // 12199 // CHECK18-LABEL: define {{[^@]+}}@_ZL7fstatici 12200 // CHECK18-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { 12201 // CHECK18-NEXT: entry: 12202 // CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 12203 // CHECK18-NEXT: [[A:%.*]] = alloca i32, align 4 12204 // CHECK18-NEXT: [[AA:%.*]] = alloca i16, align 2 12205 // CHECK18-NEXT: [[AAA:%.*]] = alloca i8, align 1 12206 // CHECK18-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 12207 // CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 12208 // CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 12209 // CHECK18-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 12210 // CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8 12211 // CHECK18-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 12212 // CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 12213 // CHECK18-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 12214 // CHECK18-NEXT: store i32 0, i32* [[A]], align 4 12215 // CHECK18-NEXT: store i16 0, i16* [[AA]], align 2 12216 // CHECK18-NEXT: store i8 0, i8* [[AAA]], align 1 12217 // CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 12218 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* 12219 // CHECK18-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 12220 // CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 12221 // CHECK18-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 12222 // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 12223 // CHECK18-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 12224 // CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 12225 // CHECK18-NEXT: [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1 12226 // CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* 12227 // CHECK18-NEXT: store i8 [[TMP4]], i8* [[CONV2]], align 1 12228 // CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 12229 // CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 12230 // CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50 12231 // CHECK18-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 12232 // CHECK18: omp_if.then: 12233 // CHECK18-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 12234 // CHECK18-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* 12235 // CHECK18-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8 12236 // CHECK18-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 12237 // CHECK18-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* 12238 // CHECK18-NEXT: store i64 [[TMP1]], i64* [[TMP10]], align 8 12239 // CHECK18-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 12240 // CHECK18-NEXT: store i8* null, i8** [[TMP11]], align 8 12241 // CHECK18-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 12242 // CHECK18-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* 12243 // CHECK18-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8 12244 // CHECK18-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 12245 // CHECK18-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* 12246 // CHECK18-NEXT: store i64 [[TMP3]], i64* [[TMP15]], align 8 12247 // CHECK18-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 12248 // CHECK18-NEXT: store i8* null, i8** [[TMP16]], align 8 12249 // CHECK18-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 12250 // CHECK18-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64* 12251 // CHECK18-NEXT: store i64 [[TMP5]], i64* [[TMP18]], align 8 12252 // CHECK18-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 12253 // CHECK18-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64* 12254 // CHECK18-NEXT: store i64 [[TMP5]], i64* [[TMP20]], align 8 12255 // CHECK18-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 12256 // CHECK18-NEXT: store i8* null, i8** [[TMP21]], align 8 12257 // CHECK18-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 12258 // CHECK18-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]** 12259 // CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 8 12260 // CHECK18-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 12261 // CHECK18-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]** 12262 // CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 8 12263 // CHECK18-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 12264 // CHECK18-NEXT: store i8* null, i8** [[TMP26]], align 8 12265 // CHECK18-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 12266 // CHECK18-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 12267 // CHECK18-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.25, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.26, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 12268 // CHECK18-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 12269 // CHECK18-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 12270 // CHECK18: omp_offload.failed: 12271 // CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR3]] 12272 // CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT]] 12273 // CHECK18: omp_offload.cont: 12274 // CHECK18-NEXT: br label [[OMP_IF_END:%.*]] 12275 // CHECK18: omp_if.else: 12276 // CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR3]] 12277 // CHECK18-NEXT: br label [[OMP_IF_END]] 12278 // CHECK18: omp_if.end: 12279 // CHECK18-NEXT: [[TMP31:%.*]] = load i32, i32* [[A]], align 4 12280 // CHECK18-NEXT: ret i32 [[TMP31]] 12281 // 12282 // 12283 // CHECK18-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 12284 // CHECK18-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { 12285 // CHECK18-NEXT: entry: 12286 // CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 12287 // CHECK18-NEXT: [[A:%.*]] = alloca i32, align 4 12288 // CHECK18-NEXT: [[AA:%.*]] = alloca i16, align 2 12289 // CHECK18-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 12290 // CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 12291 // CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 12292 // CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 12293 // CHECK18-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 12294 // CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 12295 // CHECK18-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 12296 // CHECK18-NEXT: store i32 0, i32* [[A]], align 4 12297 // CHECK18-NEXT: store i16 0, i16* [[AA]], align 2 12298 // CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 12299 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* 12300 // CHECK18-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 12301 // CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 12302 // CHECK18-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 12303 // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 12304 // CHECK18-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 12305 // CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 12306 // CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 12307 // CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40 12308 // CHECK18-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 12309 // CHECK18: omp_if.then: 12310 // CHECK18-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 12311 // CHECK18-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64* 12312 // CHECK18-NEXT: store i64 [[TMP1]], i64* [[TMP6]], align 8 12313 // CHECK18-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 12314 // CHECK18-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* 12315 // CHECK18-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8 12316 // CHECK18-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 12317 // CHECK18-NEXT: store i8* null, i8** [[TMP9]], align 8 12318 // CHECK18-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 12319 // CHECK18-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i64* 12320 // CHECK18-NEXT: store i64 [[TMP3]], i64* [[TMP11]], align 8 12321 // CHECK18-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 12322 // CHECK18-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* 12323 // CHECK18-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8 12324 // CHECK18-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 12325 // CHECK18-NEXT: store i8* null, i8** [[TMP14]], align 8 12326 // CHECK18-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 12327 // CHECK18-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]** 12328 // CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 8 12329 // CHECK18-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 12330 // CHECK18-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]** 12331 // CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 8 12332 // CHECK18-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 12333 // CHECK18-NEXT: store i8* null, i8** [[TMP19]], align 8 12334 // CHECK18-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 12335 // CHECK18-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 12336 // CHECK18-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.28, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.29, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 12337 // CHECK18-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 12338 // CHECK18-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 12339 // CHECK18: omp_offload.failed: 12340 // CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]] 12341 // CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT]] 12342 // CHECK18: omp_offload.cont: 12343 // CHECK18-NEXT: br label [[OMP_IF_END:%.*]] 12344 // CHECK18: omp_if.else: 12345 // CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]] 12346 // CHECK18-NEXT: br label [[OMP_IF_END]] 12347 // CHECK18: omp_if.end: 12348 // CHECK18-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4 12349 // CHECK18-NEXT: ret i32 [[TMP24]] 12350 // 12351 // 12352 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227 12353 // CHECK18-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { 12354 // CHECK18-NEXT: entry: 12355 // CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 12356 // CHECK18-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 12357 // CHECK18-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 12358 // CHECK18-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 12359 // CHECK18-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 12360 // CHECK18-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 12361 // CHECK18-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 12362 // CHECK18-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 12363 // CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 12364 // CHECK18-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 12365 // CHECK18-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 12366 // CHECK18-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 12367 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 12368 // CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 12369 // CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 12370 // CHECK18-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 12371 // CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 12372 // CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* 12373 // CHECK18-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 12374 // CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 12375 // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..22 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) 12376 // CHECK18-NEXT: ret void 12377 // 12378 // 12379 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..22 12380 // CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { 12381 // CHECK18-NEXT: entry: 12382 // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 12383 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 12384 // CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 12385 // CHECK18-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 12386 // CHECK18-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 12387 // CHECK18-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 12388 // CHECK18-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 12389 // CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 12390 // CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 12391 // CHECK18-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 12392 // CHECK18-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 12393 // CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 12394 // CHECK18-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 12395 // CHECK18-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 12396 // CHECK18-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 12397 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 12398 // CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 12399 // CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 12400 // CHECK18-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 12401 // CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 12402 // CHECK18-NEXT: [[CONV3:%.*]] = sitofp i32 [[TMP4]] to double 12403 // CHECK18-NEXT: [[ADD:%.*]] = fadd double [[CONV3]], 1.500000e+00 12404 // CHECK18-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 12405 // CHECK18-NEXT: store double [[ADD]], double* [[A]], align 8 12406 // CHECK18-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 12407 // CHECK18-NEXT: [[TMP5:%.*]] = load double, double* [[A4]], align 8 12408 // CHECK18-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 12409 // CHECK18-NEXT: store double [[INC]], double* [[A4]], align 8 12410 // CHECK18-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 12411 // CHECK18-NEXT: [[TMP6:%.*]] = mul nsw i64 1, [[TMP2]] 12412 // CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP6]] 12413 // CHECK18-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 12414 // CHECK18-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2 12415 // CHECK18-NEXT: ret void 12416 // 12417 // 12418 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209 12419 // CHECK18-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 12420 // CHECK18-NEXT: entry: 12421 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 12422 // CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 12423 // CHECK18-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 12424 // CHECK18-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 12425 // CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 12426 // CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 12427 // CHECK18-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 12428 // CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 12429 // CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 12430 // CHECK18-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 12431 // CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 12432 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 12433 // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 12434 // CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 12435 // CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 12436 // CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 12437 // CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* 12438 // CHECK18-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 12439 // CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 12440 // CHECK18-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 12441 // CHECK18-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 12442 // CHECK18-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 12443 // CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 12444 // CHECK18-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8 12445 // CHECK18-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* 12446 // CHECK18-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 12447 // CHECK18-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 12448 // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..24 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) 12449 // CHECK18-NEXT: ret void 12450 // 12451 // 12452 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..24 12453 // CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 12454 // CHECK18-NEXT: entry: 12455 // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 12456 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 12457 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 12458 // CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 12459 // CHECK18-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 12460 // CHECK18-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 12461 // CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 12462 // CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 12463 // CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 12464 // CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 12465 // CHECK18-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 12466 // CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 12467 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 12468 // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 12469 // CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 12470 // CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 12471 // CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 12472 // CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 12473 // CHECK18-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 12474 // CHECK18-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 12475 // CHECK18-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32 12476 // CHECK18-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 12477 // CHECK18-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 12478 // CHECK18-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 8 12479 // CHECK18-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 8 12480 // CHECK18-NEXT: [[CONV6:%.*]] = sext i8 [[TMP3]] to i32 12481 // CHECK18-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 12482 // CHECK18-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i8 12483 // CHECK18-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 8 12484 // CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 12485 // CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 12486 // CHECK18-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP4]], 1 12487 // CHECK18-NEXT: store i32 [[ADD9]], i32* [[ARRAYIDX]], align 4 12488 // CHECK18-NEXT: ret void 12489 // 12490 // 12491 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192 12492 // CHECK18-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 12493 // CHECK18-NEXT: entry: 12494 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 12495 // CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 12496 // CHECK18-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 12497 // CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 12498 // CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 12499 // CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 12500 // CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 12501 // CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 12502 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 12503 // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 12504 // CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 12505 // CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 12506 // CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* 12507 // CHECK18-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 12508 // CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 12509 // CHECK18-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 12510 // CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 12511 // CHECK18-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 12512 // CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 12513 // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..27 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) 12514 // CHECK18-NEXT: ret void 12515 // 12516 // 12517 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..27 12518 // CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 12519 // CHECK18-NEXT: entry: 12520 // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 12521 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 12522 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 12523 // CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 12524 // CHECK18-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 12525 // CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 12526 // CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 12527 // CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 12528 // CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 12529 // CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 12530 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 12531 // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 12532 // CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 12533 // CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 12534 // CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 12535 // CHECK18-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 12536 // CHECK18-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 12537 // CHECK18-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 12538 // CHECK18-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 12539 // CHECK18-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 12540 // CHECK18-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 8 12541 // CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 12542 // CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 12543 // CHECK18-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP3]], 1 12544 // CHECK18-NEXT: store i32 [[ADD5]], i32* [[ARRAYIDX]], align 4 12545 // CHECK18-NEXT: ret void 12546 // 12547 // 12548 // CHECK18-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 12549 // CHECK18-SAME: () #[[ATTR4]] { 12550 // CHECK18-NEXT: entry: 12551 // CHECK18-NEXT: call void @__tgt_register_requires(i64 1) 12552 // CHECK18-NEXT: ret void 12553 // 12554 // 12555 // CHECK19-LABEL: define {{[^@]+}}@_Z3fooi 12556 // CHECK19-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { 12557 // CHECK19-NEXT: entry: 12558 // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 12559 // CHECK19-NEXT: [[A:%.*]] = alloca i32, align 4 12560 // CHECK19-NEXT: [[AA:%.*]] = alloca i16, align 2 12561 // CHECK19-NEXT: [[B:%.*]] = alloca [10 x float], align 4 12562 // CHECK19-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 12563 // CHECK19-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 12564 // CHECK19-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 12565 // CHECK19-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 12566 // CHECK19-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 12567 // CHECK19-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 12568 // CHECK19-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 12569 // CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 12570 // CHECK19-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 12571 // CHECK19-NEXT: [[DOTCAPTURE_EXPR__CASTED3:%.*]] = alloca i32, align 4 12572 // CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 12573 // CHECK19-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 12574 // CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 12575 // CHECK19-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4 12576 // CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 12577 // CHECK19-NEXT: [[AA_CASTED4:%.*]] = alloca i32, align 4 12578 // CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS6:%.*]] = alloca [1 x i8*], align 4 12579 // CHECK19-NEXT: [[DOTOFFLOAD_PTRS7:%.*]] = alloca [1 x i8*], align 4 12580 // CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS8:%.*]] = alloca [1 x i8*], align 4 12581 // CHECK19-NEXT: [[A_CASTED9:%.*]] = alloca i32, align 4 12582 // CHECK19-NEXT: [[AA_CASTED10:%.*]] = alloca i32, align 4 12583 // CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS12:%.*]] = alloca [2 x i8*], align 4 12584 // CHECK19-NEXT: [[DOTOFFLOAD_PTRS13:%.*]] = alloca [2 x i8*], align 4 12585 // CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS14:%.*]] = alloca [2 x i8*], align 4 12586 // CHECK19-NEXT: [[A_CASTED17:%.*]] = alloca i32, align 4 12587 // CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS20:%.*]] = alloca [9 x i8*], align 4 12588 // CHECK19-NEXT: [[DOTOFFLOAD_PTRS21:%.*]] = alloca [9 x i8*], align 4 12589 // CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS22:%.*]] = alloca [9 x i8*], align 4 12590 // CHECK19-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [9 x i64], align 4 12591 // CHECK19-NEXT: [[NN:%.*]] = alloca i32, align 4 12592 // CHECK19-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4 12593 // CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS27:%.*]] = alloca [1 x i8*], align 4 12594 // CHECK19-NEXT: [[DOTOFFLOAD_PTRS28:%.*]] = alloca [1 x i8*], align 4 12595 // CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS29:%.*]] = alloca [1 x i8*], align 4 12596 // CHECK19-NEXT: [[NN_CASTED32:%.*]] = alloca i32, align 4 12597 // CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS33:%.*]] = alloca [1 x i8*], align 4 12598 // CHECK19-NEXT: [[DOTOFFLOAD_PTRS34:%.*]] = alloca [1 x i8*], align 4 12599 // CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS35:%.*]] = alloca [1 x i8*], align 4 12600 // CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) 12601 // CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 12602 // CHECK19-NEXT: store i32 0, i32* [[A]], align 4 12603 // CHECK19-NEXT: store i16 0, i16* [[AA]], align 2 12604 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 12605 // CHECK19-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() 12606 // CHECK19-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 12607 // CHECK19-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP1]], align 4 12608 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 12609 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 12610 // CHECK19-NEXT: [[TMP4:%.*]] = mul nuw i32 5, [[TMP3]] 12611 // CHECK19-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP4]], align 8 12612 // CHECK19-NEXT: store i32 [[TMP3]], i32* [[__VLA_EXPR1]], align 4 12613 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 12614 // CHECK19-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_]], align 4 12615 // CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 12616 // CHECK19-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_2]], align 4 12617 // CHECK19-NEXT: [[TMP7:%.*]] = load i16, i16* [[AA]], align 2 12618 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 12619 // CHECK19-NEXT: store i16 [[TMP7]], i16* [[CONV]], align 2 12620 // CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[AA_CASTED]], align 4 12621 // CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 12622 // CHECK19-NEXT: store i32 [[TMP9]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 12623 // CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 12624 // CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 12625 // CHECK19-NEXT: store i32 [[TMP11]], i32* [[DOTCAPTURE_EXPR__CASTED3]], align 4 12626 // CHECK19-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED3]], align 4 12627 // CHECK19-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 12628 // CHECK19-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i32* 12629 // CHECK19-NEXT: store i32 [[TMP8]], i32* [[TMP14]], align 4 12630 // CHECK19-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 12631 // CHECK19-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i32* 12632 // CHECK19-NEXT: store i32 [[TMP8]], i32* [[TMP16]], align 4 12633 // CHECK19-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 12634 // CHECK19-NEXT: store i8* null, i8** [[TMP17]], align 4 12635 // CHECK19-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 12636 // CHECK19-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32* 12637 // CHECK19-NEXT: store i32 [[TMP10]], i32* [[TMP19]], align 4 12638 // CHECK19-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 12639 // CHECK19-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32* 12640 // CHECK19-NEXT: store i32 [[TMP10]], i32* [[TMP21]], align 4 12641 // CHECK19-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 12642 // CHECK19-NEXT: store i8* null, i8** [[TMP22]], align 4 12643 // CHECK19-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 12644 // CHECK19-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i32* 12645 // CHECK19-NEXT: store i32 [[TMP12]], i32* [[TMP24]], align 4 12646 // CHECK19-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 12647 // CHECK19-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i32* 12648 // CHECK19-NEXT: store i32 [[TMP12]], i32* [[TMP26]], align 4 12649 // CHECK19-NEXT: [[TMP27:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 12650 // CHECK19-NEXT: store i8* null, i8** [[TMP27]], align 4 12651 // CHECK19-NEXT: [[TMP28:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 12652 // CHECK19-NEXT: [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 12653 // CHECK19-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 0 12654 // CHECK19-NEXT: [[TMP31:%.*]] = load i16, i16* [[AA]], align 2 12655 // CHECK19-NEXT: store i16 [[TMP31]], i16* [[TMP30]], align 4 12656 // CHECK19-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 1 12657 // CHECK19-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 12658 // CHECK19-NEXT: store i32 [[TMP33]], i32* [[TMP32]], align 4 12659 // CHECK19-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 2 12660 // CHECK19-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 12661 // CHECK19-NEXT: store i32 [[TMP35]], i32* [[TMP34]], align 4 12662 // CHECK19-NEXT: [[TMP36:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i32 72, i32 12, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1) 12663 // CHECK19-NEXT: [[TMP37:%.*]] = bitcast i8* [[TMP36]] to %struct.kmp_task_t_with_privates* 12664 // CHECK19-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP37]], i32 0, i32 0 12665 // CHECK19-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP38]], i32 0, i32 0 12666 // CHECK19-NEXT: [[TMP40:%.*]] = load i8*, i8** [[TMP39]], align 4 12667 // CHECK19-NEXT: [[TMP41:%.*]] = bitcast %struct.anon* [[AGG_CAPTURED]] to i8* 12668 // CHECK19-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP40]], i8* align 4 [[TMP41]], i32 12, i1 false) 12669 // CHECK19-NEXT: [[TMP42:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP37]], i32 0, i32 1 12670 // CHECK19-NEXT: [[TMP43:%.*]] = bitcast i8* [[TMP40]] to %struct.anon* 12671 // CHECK19-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 0 12672 // CHECK19-NEXT: [[TMP45:%.*]] = bitcast [3 x i64]* [[TMP44]] to i8* 12673 // CHECK19-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP45]], i8* align 4 bitcast ([3 x i64]* @.offload_sizes to i8*), i32 24, i1 false) 12674 // CHECK19-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 1 12675 // CHECK19-NEXT: [[TMP47:%.*]] = bitcast [3 x i8*]* [[TMP46]] to i8* 12676 // CHECK19-NEXT: [[TMP48:%.*]] = bitcast i8** [[TMP28]] to i8* 12677 // CHECK19-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP47]], i8* align 4 [[TMP48]], i32 12, i1 false) 12678 // CHECK19-NEXT: [[TMP49:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 2 12679 // CHECK19-NEXT: [[TMP50:%.*]] = bitcast [3 x i8*]* [[TMP49]] to i8* 12680 // CHECK19-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP29]] to i8* 12681 // CHECK19-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP50]], i8* align 4 [[TMP51]], i32 12, i1 false) 12682 // CHECK19-NEXT: [[TMP52:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 3 12683 // CHECK19-NEXT: [[TMP53:%.*]] = load i16, i16* [[AA]], align 2 12684 // CHECK19-NEXT: store i16 [[TMP53]], i16* [[TMP52]], align 4 12685 // CHECK19-NEXT: [[TMP54:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP36]]) 12686 // CHECK19-NEXT: [[TMP55:%.*]] = load i32, i32* [[A]], align 4 12687 // CHECK19-NEXT: store i32 [[TMP55]], i32* [[A_CASTED]], align 4 12688 // CHECK19-NEXT: [[TMP56:%.*]] = load i32, i32* [[A_CASTED]], align 4 12689 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l105(i32 [[TMP56]]) #[[ATTR3:[0-9]+]] 12690 // CHECK19-NEXT: [[TMP57:%.*]] = load i16, i16* [[AA]], align 2 12691 // CHECK19-NEXT: [[CONV5:%.*]] = bitcast i32* [[AA_CASTED4]] to i16* 12692 // CHECK19-NEXT: store i16 [[TMP57]], i16* [[CONV5]], align 2 12693 // CHECK19-NEXT: [[TMP58:%.*]] = load i32, i32* [[AA_CASTED4]], align 4 12694 // CHECK19-NEXT: [[TMP59:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0 12695 // CHECK19-NEXT: [[TMP60:%.*]] = bitcast i8** [[TMP59]] to i32* 12696 // CHECK19-NEXT: store i32 [[TMP58]], i32* [[TMP60]], align 4 12697 // CHECK19-NEXT: [[TMP61:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0 12698 // CHECK19-NEXT: [[TMP62:%.*]] = bitcast i8** [[TMP61]] to i32* 12699 // CHECK19-NEXT: store i32 [[TMP58]], i32* [[TMP62]], align 4 12700 // CHECK19-NEXT: [[TMP63:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS8]], i32 0, i32 0 12701 // CHECK19-NEXT: store i8* null, i8** [[TMP63]], align 4 12702 // CHECK19-NEXT: [[TMP64:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0 12703 // CHECK19-NEXT: [[TMP65:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0 12704 // CHECK19-NEXT: [[TMP66:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.region_id, i32 1, i8** [[TMP64]], i8** [[TMP65]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.4, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.5, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 12705 // CHECK19-NEXT: [[TMP67:%.*]] = icmp ne i32 [[TMP66]], 0 12706 // CHECK19-NEXT: br i1 [[TMP67]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 12707 // CHECK19: omp_offload.failed: 12708 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111(i32 [[TMP58]]) #[[ATTR3]] 12709 // CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]] 12710 // CHECK19: omp_offload.cont: 12711 // CHECK19-NEXT: [[TMP68:%.*]] = load i32, i32* [[A]], align 4 12712 // CHECK19-NEXT: store i32 [[TMP68]], i32* [[A_CASTED9]], align 4 12713 // CHECK19-NEXT: [[TMP69:%.*]] = load i32, i32* [[A_CASTED9]], align 4 12714 // CHECK19-NEXT: [[TMP70:%.*]] = load i16, i16* [[AA]], align 2 12715 // CHECK19-NEXT: [[CONV11:%.*]] = bitcast i32* [[AA_CASTED10]] to i16* 12716 // CHECK19-NEXT: store i16 [[TMP70]], i16* [[CONV11]], align 2 12717 // CHECK19-NEXT: [[TMP71:%.*]] = load i32, i32* [[AA_CASTED10]], align 4 12718 // CHECK19-NEXT: [[TMP72:%.*]] = load i32, i32* [[N_ADDR]], align 4 12719 // CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP72]], 10 12720 // CHECK19-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 12721 // CHECK19: omp_if.then: 12722 // CHECK19-NEXT: [[TMP73:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS12]], i32 0, i32 0 12723 // CHECK19-NEXT: [[TMP74:%.*]] = bitcast i8** [[TMP73]] to i32* 12724 // CHECK19-NEXT: store i32 [[TMP69]], i32* [[TMP74]], align 4 12725 // CHECK19-NEXT: [[TMP75:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS13]], i32 0, i32 0 12726 // CHECK19-NEXT: [[TMP76:%.*]] = bitcast i8** [[TMP75]] to i32* 12727 // CHECK19-NEXT: store i32 [[TMP69]], i32* [[TMP76]], align 4 12728 // CHECK19-NEXT: [[TMP77:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS14]], i32 0, i32 0 12729 // CHECK19-NEXT: store i8* null, i8** [[TMP77]], align 4 12730 // CHECK19-NEXT: [[TMP78:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS12]], i32 0, i32 1 12731 // CHECK19-NEXT: [[TMP79:%.*]] = bitcast i8** [[TMP78]] to i32* 12732 // CHECK19-NEXT: store i32 [[TMP71]], i32* [[TMP79]], align 4 12733 // CHECK19-NEXT: [[TMP80:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS13]], i32 0, i32 1 12734 // CHECK19-NEXT: [[TMP81:%.*]] = bitcast i8** [[TMP80]] to i32* 12735 // CHECK19-NEXT: store i32 [[TMP71]], i32* [[TMP81]], align 4 12736 // CHECK19-NEXT: [[TMP82:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS14]], i32 0, i32 1 12737 // CHECK19-NEXT: store i8* null, i8** [[TMP82]], align 4 12738 // CHECK19-NEXT: [[TMP83:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS12]], i32 0, i32 0 12739 // CHECK19-NEXT: [[TMP84:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS13]], i32 0, i32 0 12740 // CHECK19-NEXT: [[TMP85:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.region_id, i32 2, i8** [[TMP83]], i8** [[TMP84]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.7, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.8, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 12741 // CHECK19-NEXT: [[TMP86:%.*]] = icmp ne i32 [[TMP85]], 0 12742 // CHECK19-NEXT: br i1 [[TMP86]], label [[OMP_OFFLOAD_FAILED15:%.*]], label [[OMP_OFFLOAD_CONT16:%.*]] 12743 // CHECK19: omp_offload.failed15: 12744 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i32 [[TMP69]], i32 [[TMP71]]) #[[ATTR3]] 12745 // CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT16]] 12746 // CHECK19: omp_offload.cont16: 12747 // CHECK19-NEXT: br label [[OMP_IF_END:%.*]] 12748 // CHECK19: omp_if.else: 12749 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i32 [[TMP69]], i32 [[TMP71]]) #[[ATTR3]] 12750 // CHECK19-NEXT: br label [[OMP_IF_END]] 12751 // CHECK19: omp_if.end: 12752 // CHECK19-NEXT: [[TMP87:%.*]] = load i32, i32* [[A]], align 4 12753 // CHECK19-NEXT: store i32 [[TMP87]], i32* [[A_CASTED17]], align 4 12754 // CHECK19-NEXT: [[TMP88:%.*]] = load i32, i32* [[A_CASTED17]], align 4 12755 // CHECK19-NEXT: [[TMP89:%.*]] = load i32, i32* [[N_ADDR]], align 4 12756 // CHECK19-NEXT: [[CMP18:%.*]] = icmp sgt i32 [[TMP89]], 20 12757 // CHECK19-NEXT: br i1 [[CMP18]], label [[OMP_IF_THEN19:%.*]], label [[OMP_IF_ELSE25:%.*]] 12758 // CHECK19: omp_if.then19: 12759 // CHECK19-NEXT: [[TMP90:%.*]] = mul nuw i32 [[TMP1]], 4 12760 // CHECK19-NEXT: [[TMP91:%.*]] = sext i32 [[TMP90]] to i64 12761 // CHECK19-NEXT: [[TMP92:%.*]] = mul nuw i32 5, [[TMP3]] 12762 // CHECK19-NEXT: [[TMP93:%.*]] = mul nuw i32 [[TMP92]], 8 12763 // CHECK19-NEXT: [[TMP94:%.*]] = sext i32 [[TMP93]] to i64 12764 // CHECK19-NEXT: [[TMP95:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0 12765 // CHECK19-NEXT: [[TMP96:%.*]] = bitcast i8** [[TMP95]] to i32* 12766 // CHECK19-NEXT: store i32 [[TMP88]], i32* [[TMP96]], align 4 12767 // CHECK19-NEXT: [[TMP97:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 0 12768 // CHECK19-NEXT: [[TMP98:%.*]] = bitcast i8** [[TMP97]] to i32* 12769 // CHECK19-NEXT: store i32 [[TMP88]], i32* [[TMP98]], align 4 12770 // CHECK19-NEXT: [[TMP99:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 12771 // CHECK19-NEXT: store i64 4, i64* [[TMP99]], align 4 12772 // CHECK19-NEXT: [[TMP100:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 0 12773 // CHECK19-NEXT: store i8* null, i8** [[TMP100]], align 4 12774 // CHECK19-NEXT: [[TMP101:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 1 12775 // CHECK19-NEXT: [[TMP102:%.*]] = bitcast i8** [[TMP101]] to [10 x float]** 12776 // CHECK19-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP102]], align 4 12777 // CHECK19-NEXT: [[TMP103:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 1 12778 // CHECK19-NEXT: [[TMP104:%.*]] = bitcast i8** [[TMP103]] to [10 x float]** 12779 // CHECK19-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP104]], align 4 12780 // CHECK19-NEXT: [[TMP105:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 12781 // CHECK19-NEXT: store i64 40, i64* [[TMP105]], align 4 12782 // CHECK19-NEXT: [[TMP106:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 1 12783 // CHECK19-NEXT: store i8* null, i8** [[TMP106]], align 4 12784 // CHECK19-NEXT: [[TMP107:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 2 12785 // CHECK19-NEXT: [[TMP108:%.*]] = bitcast i8** [[TMP107]] to i32* 12786 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP108]], align 4 12787 // CHECK19-NEXT: [[TMP109:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 2 12788 // CHECK19-NEXT: [[TMP110:%.*]] = bitcast i8** [[TMP109]] to i32* 12789 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP110]], align 4 12790 // CHECK19-NEXT: [[TMP111:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 12791 // CHECK19-NEXT: store i64 4, i64* [[TMP111]], align 4 12792 // CHECK19-NEXT: [[TMP112:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 2 12793 // CHECK19-NEXT: store i8* null, i8** [[TMP112]], align 4 12794 // CHECK19-NEXT: [[TMP113:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 3 12795 // CHECK19-NEXT: [[TMP114:%.*]] = bitcast i8** [[TMP113]] to float** 12796 // CHECK19-NEXT: store float* [[VLA]], float** [[TMP114]], align 4 12797 // CHECK19-NEXT: [[TMP115:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 3 12798 // CHECK19-NEXT: [[TMP116:%.*]] = bitcast i8** [[TMP115]] to float** 12799 // CHECK19-NEXT: store float* [[VLA]], float** [[TMP116]], align 4 12800 // CHECK19-NEXT: [[TMP117:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 12801 // CHECK19-NEXT: store i64 [[TMP91]], i64* [[TMP117]], align 4 12802 // CHECK19-NEXT: [[TMP118:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 3 12803 // CHECK19-NEXT: store i8* null, i8** [[TMP118]], align 4 12804 // CHECK19-NEXT: [[TMP119:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 4 12805 // CHECK19-NEXT: [[TMP120:%.*]] = bitcast i8** [[TMP119]] to [5 x [10 x double]]** 12806 // CHECK19-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP120]], align 4 12807 // CHECK19-NEXT: [[TMP121:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 4 12808 // CHECK19-NEXT: [[TMP122:%.*]] = bitcast i8** [[TMP121]] to [5 x [10 x double]]** 12809 // CHECK19-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP122]], align 4 12810 // CHECK19-NEXT: [[TMP123:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 12811 // CHECK19-NEXT: store i64 400, i64* [[TMP123]], align 4 12812 // CHECK19-NEXT: [[TMP124:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 4 12813 // CHECK19-NEXT: store i8* null, i8** [[TMP124]], align 4 12814 // CHECK19-NEXT: [[TMP125:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 5 12815 // CHECK19-NEXT: [[TMP126:%.*]] = bitcast i8** [[TMP125]] to i32* 12816 // CHECK19-NEXT: store i32 5, i32* [[TMP126]], align 4 12817 // CHECK19-NEXT: [[TMP127:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 5 12818 // CHECK19-NEXT: [[TMP128:%.*]] = bitcast i8** [[TMP127]] to i32* 12819 // CHECK19-NEXT: store i32 5, i32* [[TMP128]], align 4 12820 // CHECK19-NEXT: [[TMP129:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 5 12821 // CHECK19-NEXT: store i64 4, i64* [[TMP129]], align 4 12822 // CHECK19-NEXT: [[TMP130:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 5 12823 // CHECK19-NEXT: store i8* null, i8** [[TMP130]], align 4 12824 // CHECK19-NEXT: [[TMP131:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 6 12825 // CHECK19-NEXT: [[TMP132:%.*]] = bitcast i8** [[TMP131]] to i32* 12826 // CHECK19-NEXT: store i32 [[TMP3]], i32* [[TMP132]], align 4 12827 // CHECK19-NEXT: [[TMP133:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 6 12828 // CHECK19-NEXT: [[TMP134:%.*]] = bitcast i8** [[TMP133]] to i32* 12829 // CHECK19-NEXT: store i32 [[TMP3]], i32* [[TMP134]], align 4 12830 // CHECK19-NEXT: [[TMP135:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 6 12831 // CHECK19-NEXT: store i64 4, i64* [[TMP135]], align 4 12832 // CHECK19-NEXT: [[TMP136:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 6 12833 // CHECK19-NEXT: store i8* null, i8** [[TMP136]], align 4 12834 // CHECK19-NEXT: [[TMP137:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 7 12835 // CHECK19-NEXT: [[TMP138:%.*]] = bitcast i8** [[TMP137]] to double** 12836 // CHECK19-NEXT: store double* [[VLA1]], double** [[TMP138]], align 4 12837 // CHECK19-NEXT: [[TMP139:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 7 12838 // CHECK19-NEXT: [[TMP140:%.*]] = bitcast i8** [[TMP139]] to double** 12839 // CHECK19-NEXT: store double* [[VLA1]], double** [[TMP140]], align 4 12840 // CHECK19-NEXT: [[TMP141:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 12841 // CHECK19-NEXT: store i64 [[TMP94]], i64* [[TMP141]], align 4 12842 // CHECK19-NEXT: [[TMP142:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 7 12843 // CHECK19-NEXT: store i8* null, i8** [[TMP142]], align 4 12844 // CHECK19-NEXT: [[TMP143:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 8 12845 // CHECK19-NEXT: [[TMP144:%.*]] = bitcast i8** [[TMP143]] to %struct.TT** 12846 // CHECK19-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP144]], align 4 12847 // CHECK19-NEXT: [[TMP145:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 8 12848 // CHECK19-NEXT: [[TMP146:%.*]] = bitcast i8** [[TMP145]] to %struct.TT** 12849 // CHECK19-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP146]], align 4 12850 // CHECK19-NEXT: [[TMP147:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 8 12851 // CHECK19-NEXT: store i64 12, i64* [[TMP147]], align 4 12852 // CHECK19-NEXT: [[TMP148:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 8 12853 // CHECK19-NEXT: store i8* null, i8** [[TMP148]], align 4 12854 // CHECK19-NEXT: [[TMP149:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0 12855 // CHECK19-NEXT: [[TMP150:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 0 12856 // CHECK19-NEXT: [[TMP151:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 12857 // CHECK19-NEXT: [[TMP152:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142.region_id, i32 9, i8** [[TMP149]], i8** [[TMP150]], i64* [[TMP151]], i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 12858 // CHECK19-NEXT: [[TMP153:%.*]] = icmp ne i32 [[TMP152]], 0 12859 // CHECK19-NEXT: br i1 [[TMP153]], label [[OMP_OFFLOAD_FAILED23:%.*]], label [[OMP_OFFLOAD_CONT24:%.*]] 12860 // CHECK19: omp_offload.failed23: 12861 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i32 [[TMP88]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR3]] 12862 // CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT24]] 12863 // CHECK19: omp_offload.cont24: 12864 // CHECK19-NEXT: br label [[OMP_IF_END26:%.*]] 12865 // CHECK19: omp_if.else25: 12866 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i32 [[TMP88]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR3]] 12867 // CHECK19-NEXT: br label [[OMP_IF_END26]] 12868 // CHECK19: omp_if.end26: 12869 // CHECK19-NEXT: store i32 0, i32* [[NN]], align 4 12870 // CHECK19-NEXT: [[TMP154:%.*]] = load i32, i32* [[NN]], align 4 12871 // CHECK19-NEXT: store i32 [[TMP154]], i32* [[NN_CASTED]], align 4 12872 // CHECK19-NEXT: [[TMP155:%.*]] = load i32, i32* [[NN_CASTED]], align 4 12873 // CHECK19-NEXT: [[TMP156:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS27]], i32 0, i32 0 12874 // CHECK19-NEXT: [[TMP157:%.*]] = bitcast i8** [[TMP156]] to i32* 12875 // CHECK19-NEXT: store i32 [[TMP155]], i32* [[TMP157]], align 4 12876 // CHECK19-NEXT: [[TMP158:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS28]], i32 0, i32 0 12877 // CHECK19-NEXT: [[TMP159:%.*]] = bitcast i8** [[TMP158]] to i32* 12878 // CHECK19-NEXT: store i32 [[TMP155]], i32* [[TMP159]], align 4 12879 // CHECK19-NEXT: [[TMP160:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS29]], i32 0, i32 0 12880 // CHECK19-NEXT: store i8* null, i8** [[TMP160]], align 4 12881 // CHECK19-NEXT: [[TMP161:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS27]], i32 0, i32 0 12882 // CHECK19-NEXT: [[TMP162:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS28]], i32 0, i32 0 12883 // CHECK19-NEXT: [[TMP163:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154.region_id, i32 1, i8** [[TMP161]], i8** [[TMP162]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.13, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.14, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 12884 // CHECK19-NEXT: [[TMP164:%.*]] = icmp ne i32 [[TMP163]], 0 12885 // CHECK19-NEXT: br i1 [[TMP164]], label [[OMP_OFFLOAD_FAILED30:%.*]], label [[OMP_OFFLOAD_CONT31:%.*]] 12886 // CHECK19: omp_offload.failed30: 12887 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154(i32 [[TMP155]]) #[[ATTR3]] 12888 // CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT31]] 12889 // CHECK19: omp_offload.cont31: 12890 // CHECK19-NEXT: [[TMP165:%.*]] = load i32, i32* [[NN]], align 4 12891 // CHECK19-NEXT: store i32 [[TMP165]], i32* [[NN_CASTED32]], align 4 12892 // CHECK19-NEXT: [[TMP166:%.*]] = load i32, i32* [[NN_CASTED32]], align 4 12893 // CHECK19-NEXT: [[TMP167:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS33]], i32 0, i32 0 12894 // CHECK19-NEXT: [[TMP168:%.*]] = bitcast i8** [[TMP167]] to i32* 12895 // CHECK19-NEXT: store i32 [[TMP166]], i32* [[TMP168]], align 4 12896 // CHECK19-NEXT: [[TMP169:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS34]], i32 0, i32 0 12897 // CHECK19-NEXT: [[TMP170:%.*]] = bitcast i8** [[TMP169]] to i32* 12898 // CHECK19-NEXT: store i32 [[TMP166]], i32* [[TMP170]], align 4 12899 // CHECK19-NEXT: [[TMP171:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS35]], i32 0, i32 0 12900 // CHECK19-NEXT: store i8* null, i8** [[TMP171]], align 4 12901 // CHECK19-NEXT: [[TMP172:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS33]], i32 0, i32 0 12902 // CHECK19-NEXT: [[TMP173:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS34]], i32 0, i32 0 12903 // CHECK19-NEXT: [[TMP174:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157.region_id, i32 1, i8** [[TMP172]], i8** [[TMP173]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.17, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.18, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 12904 // CHECK19-NEXT: [[TMP175:%.*]] = icmp ne i32 [[TMP174]], 0 12905 // CHECK19-NEXT: br i1 [[TMP175]], label [[OMP_OFFLOAD_FAILED36:%.*]], label [[OMP_OFFLOAD_CONT37:%.*]] 12906 // CHECK19: omp_offload.failed36: 12907 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157(i32 [[TMP166]]) #[[ATTR3]] 12908 // CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT37]] 12909 // CHECK19: omp_offload.cont37: 12910 // CHECK19-NEXT: [[TMP176:%.*]] = load i32, i32* [[A]], align 4 12911 // CHECK19-NEXT: [[TMP177:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 12912 // CHECK19-NEXT: call void @llvm.stackrestore(i8* [[TMP177]]) 12913 // CHECK19-NEXT: ret i32 [[TMP176]] 12914 // 12915 // 12916 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101 12917 // CHECK19-SAME: (i32 [[AA:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]], i32 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] { 12918 // CHECK19-NEXT: entry: 12919 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 12920 // CHECK19-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 12921 // CHECK19-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4 12922 // CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 12923 // CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 12924 // CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 12925 // CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 12926 // CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 12927 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 12928 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 12929 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 12930 // CHECK19-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) 12931 // CHECK19-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 12932 // CHECK19-NEXT: [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 12933 // CHECK19-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 12934 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 12935 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]]) 12936 // CHECK19-NEXT: ret void 12937 // 12938 // 12939 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined. 12940 // CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] { 12941 // CHECK19-NEXT: entry: 12942 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 12943 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 12944 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 12945 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 12946 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 12947 // CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 12948 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 12949 // CHECK19-NEXT: ret void 12950 // 12951 // 12952 // CHECK19-LABEL: define {{[^@]+}}@.omp_task_privates_map. 12953 // CHECK19-SAME: (%struct..kmp_privates.t* noalias [[TMP0:%.*]], i16** noalias [[TMP1:%.*]], [3 x i8*]** noalias [[TMP2:%.*]], [3 x i8*]** noalias [[TMP3:%.*]], [3 x i64]** noalias [[TMP4:%.*]]) #[[ATTR4:[0-9]+]] { 12954 // CHECK19-NEXT: entry: 12955 // CHECK19-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 4 12956 // CHECK19-NEXT: [[DOTADDR1:%.*]] = alloca i16**, align 4 12957 // CHECK19-NEXT: [[DOTADDR2:%.*]] = alloca [3 x i8*]**, align 4 12958 // CHECK19-NEXT: [[DOTADDR3:%.*]] = alloca [3 x i8*]**, align 4 12959 // CHECK19-NEXT: [[DOTADDR4:%.*]] = alloca [3 x i64]**, align 4 12960 // CHECK19-NEXT: store %struct..kmp_privates.t* [[TMP0]], %struct..kmp_privates.t** [[DOTADDR]], align 4 12961 // CHECK19-NEXT: store i16** [[TMP1]], i16*** [[DOTADDR1]], align 4 12962 // CHECK19-NEXT: store [3 x i8*]** [[TMP2]], [3 x i8*]*** [[DOTADDR2]], align 4 12963 // CHECK19-NEXT: store [3 x i8*]** [[TMP3]], [3 x i8*]*** [[DOTADDR3]], align 4 12964 // CHECK19-NEXT: store [3 x i64]** [[TMP4]], [3 x i64]*** [[DOTADDR4]], align 4 12965 // CHECK19-NEXT: [[TMP5:%.*]] = load %struct..kmp_privates.t*, %struct..kmp_privates.t** [[DOTADDR]], align 4 12966 // CHECK19-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 0 12967 // CHECK19-NEXT: [[TMP7:%.*]] = load [3 x i64]**, [3 x i64]*** [[DOTADDR4]], align 4 12968 // CHECK19-NEXT: store [3 x i64]* [[TMP6]], [3 x i64]** [[TMP7]], align 4 12969 // CHECK19-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 1 12970 // CHECK19-NEXT: [[TMP9:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR2]], align 4 12971 // CHECK19-NEXT: store [3 x i8*]* [[TMP8]], [3 x i8*]** [[TMP9]], align 4 12972 // CHECK19-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 2 12973 // CHECK19-NEXT: [[TMP11:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR3]], align 4 12974 // CHECK19-NEXT: store [3 x i8*]* [[TMP10]], [3 x i8*]** [[TMP11]], align 4 12975 // CHECK19-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 3 12976 // CHECK19-NEXT: [[TMP13:%.*]] = load i16**, i16*** [[DOTADDR1]], align 4 12977 // CHECK19-NEXT: store i16* [[TMP12]], i16** [[TMP13]], align 4 12978 // CHECK19-NEXT: ret void 12979 // 12980 // 12981 // CHECK19-LABEL: define {{[^@]+}}@.omp_task_entry. 12982 // CHECK19-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { 12983 // CHECK19-NEXT: entry: 12984 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 12985 // CHECK19-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 4 12986 // CHECK19-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 4 12987 // CHECK19-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 4 12988 // CHECK19-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 4 12989 // CHECK19-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 4 12990 // CHECK19-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca i16*, align 4 12991 // CHECK19-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca [3 x i8*]*, align 4 12992 // CHECK19-NEXT: [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca [3 x i8*]*, align 4 12993 // CHECK19-NEXT: [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca [3 x i64]*, align 4 12994 // CHECK19-NEXT: [[AA_CASTED_I:%.*]] = alloca i32, align 4 12995 // CHECK19-NEXT: [[DOTCAPTURE_EXPR__CASTED_I:%.*]] = alloca i32, align 4 12996 // CHECK19-NEXT: [[DOTCAPTURE_EXPR__CASTED4_I:%.*]] = alloca i32, align 4 12997 // CHECK19-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 12998 // CHECK19-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 4 12999 // CHECK19-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 13000 // CHECK19-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4 13001 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 13002 // CHECK19-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4 13003 // CHECK19-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0 13004 // CHECK19-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 13005 // CHECK19-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 13006 // CHECK19-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 4 13007 // CHECK19-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon* 13008 // CHECK19-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1 13009 // CHECK19-NEXT: [[TMP10:%.*]] = bitcast %struct..kmp_privates.t* [[TMP9]] to i8* 13010 // CHECK19-NEXT: [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8* 13011 // CHECK19-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]]) 13012 // CHECK19-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]]) 13013 // CHECK19-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]]) 13014 // CHECK19-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META22:![0-9]+]]) 13015 // CHECK19-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !24 13016 // CHECK19-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 4, !noalias !24 13017 // CHECK19-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !24 13018 // CHECK19-NEXT: store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* @.omp_task_privates_map. to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !24 13019 // CHECK19-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 4, !noalias !24 13020 // CHECK19-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !24 13021 // CHECK19-NEXT: [[TMP12:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !24 13022 // CHECK19-NEXT: [[TMP13:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !24 13023 // CHECK19-NEXT: [[TMP14:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !24 13024 // CHECK19-NEXT: [[TMP15:%.*]] = bitcast void (i8*, ...)* [[TMP13]] to void (i8*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* 13025 // CHECK19-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]] 13026 // CHECK19-NEXT: [[TMP16:%.*]] = load i16*, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 4, !noalias !24 13027 // CHECK19-NEXT: [[TMP17:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 4, !noalias !24 13028 // CHECK19-NEXT: [[TMP18:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 4, !noalias !24 13029 // CHECK19-NEXT: [[TMP19:%.*]] = load [3 x i64]*, [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 4, !noalias !24 13030 // CHECK19-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP17]], i32 0, i32 0 13031 // CHECK19-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP18]], i32 0, i32 0 13032 // CHECK19-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[TMP19]], i32 0, i32 0 13033 // CHECK19-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP12]], i32 0, i32 1 13034 // CHECK19-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[TMP12]], i32 0, i32 2 13035 // CHECK19-NEXT: [[TMP25:%.*]] = load i32, i32* [[TMP23]], align 4 13036 // CHECK19-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP24]], align 4 13037 // CHECK19-NEXT: [[TMP27:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 [[TMP25]], i32 [[TMP26]]) #[[ATTR3]] 13038 // CHECK19-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0 13039 // CHECK19-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]] 13040 // CHECK19: omp_offload.failed.i: 13041 // CHECK19-NEXT: [[TMP29:%.*]] = load i16, i16* [[TMP16]], align 2 13042 // CHECK19-NEXT: [[CONV_I:%.*]] = bitcast i32* [[AA_CASTED_I]] to i16* 13043 // CHECK19-NEXT: store i16 [[TMP29]], i16* [[CONV_I]], align 2, !noalias !24 13044 // CHECK19-NEXT: [[TMP30:%.*]] = load i32, i32* [[AA_CASTED_I]], align 4, !noalias !24 13045 // CHECK19-NEXT: [[TMP31:%.*]] = load i32, i32* [[TMP23]], align 4 13046 // CHECK19-NEXT: store i32 [[TMP31]], i32* [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias !24 13047 // CHECK19-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias !24 13048 // CHECK19-NEXT: [[TMP33:%.*]] = load i32, i32* [[TMP24]], align 4 13049 // CHECK19-NEXT: store i32 [[TMP33]], i32* [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias !24 13050 // CHECK19-NEXT: [[TMP34:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias !24 13051 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101(i32 [[TMP30]], i32 [[TMP32]], i32 [[TMP34]]) #[[ATTR3]] 13052 // CHECK19-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]] 13053 // CHECK19: .omp_outlined..1.exit: 13054 // CHECK19-NEXT: ret i32 0 13055 // 13056 // 13057 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l105 13058 // CHECK19-SAME: (i32 [[A:%.*]]) #[[ATTR2]] { 13059 // CHECK19-NEXT: entry: 13060 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 13061 // CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 13062 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 13063 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 13064 // CHECK19-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 13065 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 13066 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]]) 13067 // CHECK19-NEXT: ret void 13068 // 13069 // 13070 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..2 13071 // CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]]) #[[ATTR2]] { 13072 // CHECK19-NEXT: entry: 13073 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 13074 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 13075 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 13076 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 13077 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 13078 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 13079 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 13080 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 13081 // CHECK19-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 13082 // CHECK19-NEXT: ret void 13083 // 13084 // 13085 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 13086 // CHECK19-SAME: (i32 [[AA:%.*]]) #[[ATTR2]] { 13087 // CHECK19-NEXT: entry: 13088 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 13089 // CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 13090 // CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 13091 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 13092 // CHECK19-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 13093 // CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 13094 // CHECK19-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 13095 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 13096 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP1]]) 13097 // CHECK19-NEXT: ret void 13098 // 13099 // 13100 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..3 13101 // CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] { 13102 // CHECK19-NEXT: entry: 13103 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 13104 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 13105 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 13106 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 13107 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 13108 // CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 13109 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 13110 // CHECK19-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 13111 // CHECK19-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 13112 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 13113 // CHECK19-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 13114 // CHECK19-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 4 13115 // CHECK19-NEXT: ret void 13116 // 13117 // 13118 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118 13119 // CHECK19-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] { 13120 // CHECK19-NEXT: entry: 13121 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 13122 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 13123 // CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 13124 // CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 13125 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 13126 // CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 13127 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 13128 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 13129 // CHECK19-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 13130 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 13131 // CHECK19-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 13132 // CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 13133 // CHECK19-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 13134 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 13135 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) 13136 // CHECK19-NEXT: ret void 13137 // 13138 // 13139 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..6 13140 // CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] { 13141 // CHECK19-NEXT: entry: 13142 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 13143 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 13144 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 13145 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 13146 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 13147 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 13148 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 13149 // CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 13150 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 13151 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 13152 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 13153 // CHECK19-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 13154 // CHECK19-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 4 13155 // CHECK19-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32 13156 // CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 13157 // CHECK19-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 13158 // CHECK19-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 4 13159 // CHECK19-NEXT: ret void 13160 // 13161 // 13162 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142 13163 // CHECK19-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] { 13164 // CHECK19-NEXT: entry: 13165 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 13166 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 13167 // CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 13168 // CHECK19-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 13169 // CHECK19-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 13170 // CHECK19-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 13171 // CHECK19-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 13172 // CHECK19-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 13173 // CHECK19-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 13174 // CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 13175 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 13176 // CHECK19-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 13177 // CHECK19-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 13178 // CHECK19-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 13179 // CHECK19-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 13180 // CHECK19-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 13181 // CHECK19-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 13182 // CHECK19-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 13183 // CHECK19-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 13184 // CHECK19-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 13185 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 13186 // CHECK19-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 13187 // CHECK19-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 13188 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 13189 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 13190 // CHECK19-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 13191 // CHECK19-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 13192 // CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 13193 // CHECK19-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4 13194 // CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4 13195 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) 13196 // CHECK19-NEXT: ret void 13197 // 13198 // 13199 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..9 13200 // CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] { 13201 // CHECK19-NEXT: entry: 13202 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 13203 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 13204 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 13205 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 13206 // CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 13207 // CHECK19-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 13208 // CHECK19-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 13209 // CHECK19-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 13210 // CHECK19-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 13211 // CHECK19-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 13212 // CHECK19-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 13213 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 13214 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 13215 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 13216 // CHECK19-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 13217 // CHECK19-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 13218 // CHECK19-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 13219 // CHECK19-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 13220 // CHECK19-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 13221 // CHECK19-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 13222 // CHECK19-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 13223 // CHECK19-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 13224 // CHECK19-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 13225 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 13226 // CHECK19-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 13227 // CHECK19-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 13228 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 13229 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 13230 // CHECK19-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 13231 // CHECK19-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 13232 // CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 13233 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 13234 // CHECK19-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 13235 // CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2 13236 // CHECK19-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 13237 // CHECK19-NEXT: [[CONV:%.*]] = fpext float [[TMP9]] to double 13238 // CHECK19-NEXT: [[ADD5:%.*]] = fadd double [[CONV]], 1.000000e+00 13239 // CHECK19-NEXT: [[CONV6:%.*]] = fptrunc double [[ADD5]] to float 13240 // CHECK19-NEXT: store float [[CONV6]], float* [[ARRAYIDX]], align 4 13241 // CHECK19-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3 13242 // CHECK19-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX7]], align 4 13243 // CHECK19-NEXT: [[CONV8:%.*]] = fpext float [[TMP10]] to double 13244 // CHECK19-NEXT: [[ADD9:%.*]] = fadd double [[CONV8]], 1.000000e+00 13245 // CHECK19-NEXT: [[CONV10:%.*]] = fptrunc double [[ADD9]] to float 13246 // CHECK19-NEXT: store float [[CONV10]], float* [[ARRAYIDX7]], align 4 13247 // CHECK19-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1 13248 // CHECK19-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX11]], i32 0, i32 2 13249 // CHECK19-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX12]], align 8 13250 // CHECK19-NEXT: [[ADD13:%.*]] = fadd double [[TMP11]], 1.000000e+00 13251 // CHECK19-NEXT: store double [[ADD13]], double* [[ARRAYIDX12]], align 8 13252 // CHECK19-NEXT: [[TMP12:%.*]] = mul nsw i32 1, [[TMP5]] 13253 // CHECK19-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP12]] 13254 // CHECK19-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX14]], i32 3 13255 // CHECK19-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX15]], align 8 13256 // CHECK19-NEXT: [[ADD16:%.*]] = fadd double [[TMP13]], 1.000000e+00 13257 // CHECK19-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8 13258 // CHECK19-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 13259 // CHECK19-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 4 13260 // CHECK19-NEXT: [[ADD17:%.*]] = add nsw i64 [[TMP14]], 1 13261 // CHECK19-NEXT: store i64 [[ADD17]], i64* [[X]], align 4 13262 // CHECK19-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 13263 // CHECK19-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 4 13264 // CHECK19-NEXT: [[CONV18:%.*]] = sext i8 [[TMP15]] to i32 13265 // CHECK19-NEXT: [[ADD19:%.*]] = add nsw i32 [[CONV18]], 1 13266 // CHECK19-NEXT: [[CONV20:%.*]] = trunc i32 [[ADD19]] to i8 13267 // CHECK19-NEXT: store i8 [[CONV20]], i8* [[Y]], align 4 13268 // CHECK19-NEXT: ret void 13269 // 13270 // 13271 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154 13272 // CHECK19-SAME: (i32 [[NN:%.*]]) #[[ATTR2]] { 13273 // CHECK19-NEXT: entry: 13274 // CHECK19-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 13275 // CHECK19-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4 13276 // CHECK19-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 13277 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[NN_ADDR]], align 4 13278 // CHECK19-NEXT: store i32 [[TMP0]], i32* [[NN_CASTED]], align 4 13279 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[NN_CASTED]], align 4 13280 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP1]]) 13281 // CHECK19-NEXT: ret void 13282 // 13283 // 13284 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..11 13285 // CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[NN:%.*]]) #[[ATTR2]] { 13286 // CHECK19-NEXT: entry: 13287 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 13288 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 13289 // CHECK19-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 13290 // CHECK19-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4 13291 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 13292 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 13293 // CHECK19-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 13294 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[NN_ADDR]], align 4 13295 // CHECK19-NEXT: store i32 [[TMP0]], i32* [[NN_CASTED]], align 4 13296 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[NN_CASTED]], align 4 13297 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..12 to void (i32*, i32*, ...)*), i32 [[TMP1]]) 13298 // CHECK19-NEXT: ret void 13299 // 13300 // 13301 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..12 13302 // CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[NN:%.*]]) #[[ATTR2]] { 13303 // CHECK19-NEXT: entry: 13304 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 13305 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 13306 // CHECK19-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 13307 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 13308 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 13309 // CHECK19-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 13310 // CHECK19-NEXT: ret void 13311 // 13312 // 13313 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157 13314 // CHECK19-SAME: (i32 [[NN:%.*]]) #[[ATTR2]] { 13315 // CHECK19-NEXT: entry: 13316 // CHECK19-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 13317 // CHECK19-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4 13318 // CHECK19-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 13319 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[NN_ADDR]], align 4 13320 // CHECK19-NEXT: store i32 [[TMP0]], i32* [[NN_CASTED]], align 4 13321 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[NN_CASTED]], align 4 13322 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i32 [[TMP1]]) 13323 // CHECK19-NEXT: ret void 13324 // 13325 // 13326 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..15 13327 // CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[NN:%.*]]) #[[ATTR2]] { 13328 // CHECK19-NEXT: entry: 13329 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 13330 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 13331 // CHECK19-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 13332 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 13333 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 13334 // CHECK19-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 13335 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i32* [[NN_ADDR]]) 13336 // CHECK19-NEXT: ret void 13337 // 13338 // 13339 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..16 13340 // CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[NN:%.*]]) #[[ATTR2]] { 13341 // CHECK19-NEXT: entry: 13342 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 13343 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 13344 // CHECK19-NEXT: [[NN_ADDR:%.*]] = alloca i32*, align 4 13345 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 13346 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 13347 // CHECK19-NEXT: store i32* [[NN]], i32** [[NN_ADDR]], align 4 13348 // CHECK19-NEXT: [[TMP0:%.*]] = load i32*, i32** [[NN_ADDR]], align 4 13349 // CHECK19-NEXT: ret void 13350 // 13351 // 13352 // CHECK19-LABEL: define {{[^@]+}}@_Z6bazzzziPi 13353 // CHECK19-SAME: (i32 [[N:%.*]], i32* [[F:%.*]]) #[[ATTR0]] { 13354 // CHECK19-NEXT: entry: 13355 // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 13356 // CHECK19-NEXT: [[F_ADDR:%.*]] = alloca i32*, align 4 13357 // CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 13358 // CHECK19-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 13359 // CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 13360 // CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 13361 // CHECK19-NEXT: store i32* [[F]], i32** [[F_ADDR]], align 4 13362 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 13363 // CHECK19-NEXT: [[TMP1:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 13364 // CHECK19-NEXT: [[TMP2:%.*]] = bitcast i8** [[TMP1]] to i32* 13365 // CHECK19-NEXT: store i32 [[TMP0]], i32* [[TMP2]], align 4 13366 // CHECK19-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 13367 // CHECK19-NEXT: [[TMP4:%.*]] = bitcast i8** [[TMP3]] to i32* 13368 // CHECK19-NEXT: store i32 [[TMP0]], i32* [[TMP4]], align 4 13369 // CHECK19-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 13370 // CHECK19-NEXT: store i8* null, i8** [[TMP5]], align 4 13371 // CHECK19-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 13372 // CHECK19-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 13373 // CHECK19-NEXT: [[TMP8:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182.region_id, i32 1, i8** [[TMP6]], i8** [[TMP7]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.20, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.21, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 13374 // CHECK19-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0 13375 // CHECK19-NEXT: br i1 [[TMP9]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 13376 // CHECK19: omp_offload.failed: 13377 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182(i32 [[TMP0]]) #[[ATTR3]] 13378 // CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]] 13379 // CHECK19: omp_offload.cont: 13380 // CHECK19-NEXT: ret void 13381 // 13382 // 13383 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182 13384 // CHECK19-SAME: (i32 [[VLA:%.*]]) #[[ATTR2]] { 13385 // CHECK19-NEXT: entry: 13386 // CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 13387 // CHECK19-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 13388 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 13389 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..19 to void (i32*, i32*, ...)*), i32 [[TMP0]]) 13390 // CHECK19-NEXT: ret void 13391 // 13392 // 13393 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..19 13394 // CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[VLA:%.*]]) #[[ATTR2]] { 13395 // CHECK19-NEXT: entry: 13396 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 13397 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 13398 // CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 13399 // CHECK19-NEXT: [[F:%.*]] = alloca i32*, align 4 13400 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 13401 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 13402 // CHECK19-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 13403 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 13404 // CHECK19-NEXT: ret void 13405 // 13406 // 13407 // CHECK19-LABEL: define {{[^@]+}}@_Z3bari 13408 // CHECK19-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { 13409 // CHECK19-NEXT: entry: 13410 // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 13411 // CHECK19-NEXT: [[A:%.*]] = alloca i32, align 4 13412 // CHECK19-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 13413 // CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 13414 // CHECK19-NEXT: store i32 0, i32* [[A]], align 4 13415 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 13416 // CHECK19-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]]) 13417 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 13418 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 13419 // CHECK19-NEXT: store i32 [[ADD]], i32* [[A]], align 4 13420 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 13421 // CHECK19-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]]) 13422 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 13423 // CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 13424 // CHECK19-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 13425 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 13426 // CHECK19-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]]) 13427 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 13428 // CHECK19-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 13429 // CHECK19-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 13430 // CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 13431 // CHECK19-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]]) 13432 // CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 13433 // CHECK19-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] 13434 // CHECK19-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 13435 // CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 13436 // CHECK19-NEXT: ret i32 [[TMP8]] 13437 // 13438 // 13439 // CHECK19-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 13440 // CHECK19-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { 13441 // CHECK19-NEXT: entry: 13442 // CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 13443 // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 13444 // CHECK19-NEXT: [[B:%.*]] = alloca i32, align 4 13445 // CHECK19-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 13446 // CHECK19-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 13447 // CHECK19-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 13448 // CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4 13449 // CHECK19-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4 13450 // CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4 13451 // CHECK19-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 4 13452 // CHECK19-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 13453 // CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 13454 // CHECK19-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 13455 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 13456 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 13457 // CHECK19-NEXT: store i32 [[ADD]], i32* [[B]], align 4 13458 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 13459 // CHECK19-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() 13460 // CHECK19-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 13461 // CHECK19-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] 13462 // CHECK19-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 13463 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 13464 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[B]], align 4 13465 // CHECK19-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 13466 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 13467 // CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 13468 // CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 60 13469 // CHECK19-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 13470 // CHECK19: omp_if.then: 13471 // CHECK19-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 13472 // CHECK19-NEXT: [[TMP7:%.*]] = mul nuw i32 2, [[TMP1]] 13473 // CHECK19-NEXT: [[TMP8:%.*]] = mul nuw i32 [[TMP7]], 2 13474 // CHECK19-NEXT: [[TMP9:%.*]] = sext i32 [[TMP8]] to i64 13475 // CHECK19-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 13476 // CHECK19-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to %struct.S1** 13477 // CHECK19-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP11]], align 4 13478 // CHECK19-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 13479 // CHECK19-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to double** 13480 // CHECK19-NEXT: store double* [[A]], double** [[TMP13]], align 4 13481 // CHECK19-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 13482 // CHECK19-NEXT: store i64 8, i64* [[TMP14]], align 4 13483 // CHECK19-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 13484 // CHECK19-NEXT: store i8* null, i8** [[TMP15]], align 4 13485 // CHECK19-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 13486 // CHECK19-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32* 13487 // CHECK19-NEXT: store i32 [[TMP5]], i32* [[TMP17]], align 4 13488 // CHECK19-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 13489 // CHECK19-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32* 13490 // CHECK19-NEXT: store i32 [[TMP5]], i32* [[TMP19]], align 4 13491 // CHECK19-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 13492 // CHECK19-NEXT: store i64 4, i64* [[TMP20]], align 4 13493 // CHECK19-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 13494 // CHECK19-NEXT: store i8* null, i8** [[TMP21]], align 4 13495 // CHECK19-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 13496 // CHECK19-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i32* 13497 // CHECK19-NEXT: store i32 2, i32* [[TMP23]], align 4 13498 // CHECK19-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 13499 // CHECK19-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i32* 13500 // CHECK19-NEXT: store i32 2, i32* [[TMP25]], align 4 13501 // CHECK19-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 13502 // CHECK19-NEXT: store i64 4, i64* [[TMP26]], align 4 13503 // CHECK19-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 13504 // CHECK19-NEXT: store i8* null, i8** [[TMP27]], align 4 13505 // CHECK19-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 13506 // CHECK19-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i32* 13507 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP29]], align 4 13508 // CHECK19-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 13509 // CHECK19-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i32* 13510 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP31]], align 4 13511 // CHECK19-NEXT: [[TMP32:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 13512 // CHECK19-NEXT: store i64 4, i64* [[TMP32]], align 4 13513 // CHECK19-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 13514 // CHECK19-NEXT: store i8* null, i8** [[TMP33]], align 4 13515 // CHECK19-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 13516 // CHECK19-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i16** 13517 // CHECK19-NEXT: store i16* [[VLA]], i16** [[TMP35]], align 4 13518 // CHECK19-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 13519 // CHECK19-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i16** 13520 // CHECK19-NEXT: store i16* [[VLA]], i16** [[TMP37]], align 4 13521 // CHECK19-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 13522 // CHECK19-NEXT: store i64 [[TMP9]], i64* [[TMP38]], align 4 13523 // CHECK19-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 13524 // CHECK19-NEXT: store i8* null, i8** [[TMP39]], align 4 13525 // CHECK19-NEXT: [[TMP40:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 13526 // CHECK19-NEXT: [[TMP41:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 13527 // CHECK19-NEXT: [[TMP42:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 13528 // CHECK19-NEXT: [[TMP43:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227.region_id, i32 5, i8** [[TMP40]], i8** [[TMP41]], i64* [[TMP42]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.23, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 13529 // CHECK19-NEXT: [[TMP44:%.*]] = icmp ne i32 [[TMP43]], 0 13530 // CHECK19-NEXT: br i1 [[TMP44]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 13531 // CHECK19: omp_offload.failed: 13532 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR3]] 13533 // CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]] 13534 // CHECK19: omp_offload.cont: 13535 // CHECK19-NEXT: br label [[OMP_IF_END:%.*]] 13536 // CHECK19: omp_if.else: 13537 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR3]] 13538 // CHECK19-NEXT: br label [[OMP_IF_END]] 13539 // CHECK19: omp_if.end: 13540 // CHECK19-NEXT: [[TMP45:%.*]] = mul nsw i32 1, [[TMP1]] 13541 // CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP45]] 13542 // CHECK19-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 13543 // CHECK19-NEXT: [[TMP46:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2 13544 // CHECK19-NEXT: [[CONV:%.*]] = sext i16 [[TMP46]] to i32 13545 // CHECK19-NEXT: [[TMP47:%.*]] = load i32, i32* [[B]], align 4 13546 // CHECK19-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP47]] 13547 // CHECK19-NEXT: [[TMP48:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 13548 // CHECK19-NEXT: call void @llvm.stackrestore(i8* [[TMP48]]) 13549 // CHECK19-NEXT: ret i32 [[ADD3]] 13550 // 13551 // 13552 // CHECK19-LABEL: define {{[^@]+}}@_ZL7fstatici 13553 // CHECK19-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { 13554 // CHECK19-NEXT: entry: 13555 // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 13556 // CHECK19-NEXT: [[A:%.*]] = alloca i32, align 4 13557 // CHECK19-NEXT: [[AA:%.*]] = alloca i16, align 2 13558 // CHECK19-NEXT: [[AAA:%.*]] = alloca i8, align 1 13559 // CHECK19-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 13560 // CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 13561 // CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 13562 // CHECK19-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 13563 // CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4 13564 // CHECK19-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 13565 // CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 13566 // CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 13567 // CHECK19-NEXT: store i32 0, i32* [[A]], align 4 13568 // CHECK19-NEXT: store i16 0, i16* [[AA]], align 2 13569 // CHECK19-NEXT: store i8 0, i8* [[AAA]], align 1 13570 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 13571 // CHECK19-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 13572 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 13573 // CHECK19-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 13574 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 13575 // CHECK19-NEXT: store i16 [[TMP2]], i16* [[CONV]], align 2 13576 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 13577 // CHECK19-NEXT: [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1 13578 // CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* 13579 // CHECK19-NEXT: store i8 [[TMP4]], i8* [[CONV1]], align 1 13580 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 13581 // CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 13582 // CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50 13583 // CHECK19-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 13584 // CHECK19: omp_if.then: 13585 // CHECK19-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 13586 // CHECK19-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* 13587 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4 13588 // CHECK19-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 13589 // CHECK19-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* 13590 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP10]], align 4 13591 // CHECK19-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 13592 // CHECK19-NEXT: store i8* null, i8** [[TMP11]], align 4 13593 // CHECK19-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 13594 // CHECK19-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* 13595 // CHECK19-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4 13596 // CHECK19-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 13597 // CHECK19-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32* 13598 // CHECK19-NEXT: store i32 [[TMP3]], i32* [[TMP15]], align 4 13599 // CHECK19-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 13600 // CHECK19-NEXT: store i8* null, i8** [[TMP16]], align 4 13601 // CHECK19-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 13602 // CHECK19-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32* 13603 // CHECK19-NEXT: store i32 [[TMP5]], i32* [[TMP18]], align 4 13604 // CHECK19-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 13605 // CHECK19-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32* 13606 // CHECK19-NEXT: store i32 [[TMP5]], i32* [[TMP20]], align 4 13607 // CHECK19-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 13608 // CHECK19-NEXT: store i8* null, i8** [[TMP21]], align 4 13609 // CHECK19-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 13610 // CHECK19-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]** 13611 // CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 4 13612 // CHECK19-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 13613 // CHECK19-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]** 13614 // CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 4 13615 // CHECK19-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 13616 // CHECK19-NEXT: store i8* null, i8** [[TMP26]], align 4 13617 // CHECK19-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 13618 // CHECK19-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 13619 // CHECK19-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.25, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.26, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 13620 // CHECK19-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 13621 // CHECK19-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 13622 // CHECK19: omp_offload.failed: 13623 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR3]] 13624 // CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]] 13625 // CHECK19: omp_offload.cont: 13626 // CHECK19-NEXT: br label [[OMP_IF_END:%.*]] 13627 // CHECK19: omp_if.else: 13628 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR3]] 13629 // CHECK19-NEXT: br label [[OMP_IF_END]] 13630 // CHECK19: omp_if.end: 13631 // CHECK19-NEXT: [[TMP31:%.*]] = load i32, i32* [[A]], align 4 13632 // CHECK19-NEXT: ret i32 [[TMP31]] 13633 // 13634 // 13635 // CHECK19-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 13636 // CHECK19-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { 13637 // CHECK19-NEXT: entry: 13638 // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 13639 // CHECK19-NEXT: [[A:%.*]] = alloca i32, align 4 13640 // CHECK19-NEXT: [[AA:%.*]] = alloca i16, align 2 13641 // CHECK19-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 13642 // CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 13643 // CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 13644 // CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 13645 // CHECK19-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 13646 // CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 13647 // CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 13648 // CHECK19-NEXT: store i32 0, i32* [[A]], align 4 13649 // CHECK19-NEXT: store i16 0, i16* [[AA]], align 2 13650 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 13651 // CHECK19-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 13652 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 13653 // CHECK19-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 13654 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 13655 // CHECK19-NEXT: store i16 [[TMP2]], i16* [[CONV]], align 2 13656 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 13657 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 13658 // CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40 13659 // CHECK19-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 13660 // CHECK19: omp_if.then: 13661 // CHECK19-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 13662 // CHECK19-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i32* 13663 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP6]], align 4 13664 // CHECK19-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 13665 // CHECK19-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* 13666 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4 13667 // CHECK19-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 13668 // CHECK19-NEXT: store i8* null, i8** [[TMP9]], align 4 13669 // CHECK19-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 13670 // CHECK19-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i32* 13671 // CHECK19-NEXT: store i32 [[TMP3]], i32* [[TMP11]], align 4 13672 // CHECK19-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 13673 // CHECK19-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* 13674 // CHECK19-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4 13675 // CHECK19-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 13676 // CHECK19-NEXT: store i8* null, i8** [[TMP14]], align 4 13677 // CHECK19-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 13678 // CHECK19-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]** 13679 // CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 4 13680 // CHECK19-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 13681 // CHECK19-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]** 13682 // CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 4 13683 // CHECK19-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 13684 // CHECK19-NEXT: store i8* null, i8** [[TMP19]], align 4 13685 // CHECK19-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 13686 // CHECK19-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 13687 // CHECK19-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.28, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.29, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 13688 // CHECK19-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 13689 // CHECK19-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 13690 // CHECK19: omp_offload.failed: 13691 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]] 13692 // CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]] 13693 // CHECK19: omp_offload.cont: 13694 // CHECK19-NEXT: br label [[OMP_IF_END:%.*]] 13695 // CHECK19: omp_if.else: 13696 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]] 13697 // CHECK19-NEXT: br label [[OMP_IF_END]] 13698 // CHECK19: omp_if.end: 13699 // CHECK19-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4 13700 // CHECK19-NEXT: ret i32 [[TMP24]] 13701 // 13702 // 13703 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227 13704 // CHECK19-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { 13705 // CHECK19-NEXT: entry: 13706 // CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 13707 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 13708 // CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 13709 // CHECK19-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 13710 // CHECK19-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 13711 // CHECK19-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 13712 // CHECK19-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 13713 // CHECK19-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 13714 // CHECK19-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 13715 // CHECK19-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 13716 // CHECK19-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 13717 // CHECK19-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 13718 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 13719 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 13720 // CHECK19-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 13721 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 13722 // CHECK19-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 13723 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 13724 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..22 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]]) 13725 // CHECK19-NEXT: ret void 13726 // 13727 // 13728 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..22 13729 // CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { 13730 // CHECK19-NEXT: entry: 13731 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 13732 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 13733 // CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 13734 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 13735 // CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 13736 // CHECK19-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 13737 // CHECK19-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 13738 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 13739 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 13740 // CHECK19-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 13741 // CHECK19-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 13742 // CHECK19-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 13743 // CHECK19-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 13744 // CHECK19-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 13745 // CHECK19-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 13746 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 13747 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 13748 // CHECK19-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 13749 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 13750 // CHECK19-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP4]] to double 13751 // CHECK19-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 13752 // CHECK19-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 13753 // CHECK19-NEXT: store double [[ADD]], double* [[A]], align 4 13754 // CHECK19-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 13755 // CHECK19-NEXT: [[TMP5:%.*]] = load double, double* [[A3]], align 4 13756 // CHECK19-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 13757 // CHECK19-NEXT: store double [[INC]], double* [[A3]], align 4 13758 // CHECK19-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 13759 // CHECK19-NEXT: [[TMP6:%.*]] = mul nsw i32 1, [[TMP2]] 13760 // CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP6]] 13761 // CHECK19-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 13762 // CHECK19-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 13763 // CHECK19-NEXT: ret void 13764 // 13765 // 13766 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209 13767 // CHECK19-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 13768 // CHECK19-NEXT: entry: 13769 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 13770 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 13771 // CHECK19-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 13772 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 13773 // CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 13774 // CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 13775 // CHECK19-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 13776 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 13777 // CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 13778 // CHECK19-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 13779 // CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 13780 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 13781 // CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 13782 // CHECK19-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 13783 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 13784 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 13785 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 13786 // CHECK19-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 13787 // CHECK19-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 13788 // CHECK19-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 13789 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 13790 // CHECK19-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 4 13791 // CHECK19-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* 13792 // CHECK19-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 13793 // CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 13794 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..24 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) 13795 // CHECK19-NEXT: ret void 13796 // 13797 // 13798 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..24 13799 // CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 13800 // CHECK19-NEXT: entry: 13801 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 13802 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 13803 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 13804 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 13805 // CHECK19-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 13806 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 13807 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 13808 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 13809 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 13810 // CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 13811 // CHECK19-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 13812 // CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 13813 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 13814 // CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 13815 // CHECK19-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 13816 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 13817 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 13818 // CHECK19-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 13819 // CHECK19-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 13820 // CHECK19-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 13821 // CHECK19-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 13822 // CHECK19-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 13823 // CHECK19-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 4 13824 // CHECK19-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 4 13825 // CHECK19-NEXT: [[CONV5:%.*]] = sext i8 [[TMP3]] to i32 13826 // CHECK19-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 13827 // CHECK19-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i8 13828 // CHECK19-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 4 13829 // CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 13830 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 13831 // CHECK19-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP4]], 1 13832 // CHECK19-NEXT: store i32 [[ADD8]], i32* [[ARRAYIDX]], align 4 13833 // CHECK19-NEXT: ret void 13834 // 13835 // 13836 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192 13837 // CHECK19-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 13838 // CHECK19-NEXT: entry: 13839 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 13840 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 13841 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 13842 // CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 13843 // CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 13844 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 13845 // CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 13846 // CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 13847 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 13848 // CHECK19-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 13849 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 13850 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 13851 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 13852 // CHECK19-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 13853 // CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 13854 // CHECK19-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 13855 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 13856 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..27 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) 13857 // CHECK19-NEXT: ret void 13858 // 13859 // 13860 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..27 13861 // CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 13862 // CHECK19-NEXT: entry: 13863 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 13864 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 13865 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 13866 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 13867 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 13868 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 13869 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 13870 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 13871 // CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 13872 // CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 13873 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 13874 // CHECK19-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 13875 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 13876 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 13877 // CHECK19-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 13878 // CHECK19-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 13879 // CHECK19-NEXT: [[CONV1:%.*]] = sext i16 [[TMP2]] to i32 13880 // CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 13881 // CHECK19-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 13882 // CHECK19-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 4 13883 // CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 13884 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 13885 // CHECK19-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1 13886 // CHECK19-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4 13887 // CHECK19-NEXT: ret void 13888 // 13889 // 13890 // CHECK19-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 13891 // CHECK19-SAME: () #[[ATTR4]] { 13892 // CHECK19-NEXT: entry: 13893 // CHECK19-NEXT: call void @__tgt_register_requires(i64 1) 13894 // CHECK19-NEXT: ret void 13895 // 13896 // 13897 // CHECK20-LABEL: define {{[^@]+}}@_Z3fooi 13898 // CHECK20-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { 13899 // CHECK20-NEXT: entry: 13900 // CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 13901 // CHECK20-NEXT: [[A:%.*]] = alloca i32, align 4 13902 // CHECK20-NEXT: [[AA:%.*]] = alloca i16, align 2 13903 // CHECK20-NEXT: [[B:%.*]] = alloca [10 x float], align 4 13904 // CHECK20-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 13905 // CHECK20-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 13906 // CHECK20-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 13907 // CHECK20-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 13908 // CHECK20-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 13909 // CHECK20-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 13910 // CHECK20-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 13911 // CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 13912 // CHECK20-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 13913 // CHECK20-NEXT: [[DOTCAPTURE_EXPR__CASTED3:%.*]] = alloca i32, align 4 13914 // CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 13915 // CHECK20-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 13916 // CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 13917 // CHECK20-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4 13918 // CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 13919 // CHECK20-NEXT: [[AA_CASTED4:%.*]] = alloca i32, align 4 13920 // CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS6:%.*]] = alloca [1 x i8*], align 4 13921 // CHECK20-NEXT: [[DOTOFFLOAD_PTRS7:%.*]] = alloca [1 x i8*], align 4 13922 // CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS8:%.*]] = alloca [1 x i8*], align 4 13923 // CHECK20-NEXT: [[A_CASTED9:%.*]] = alloca i32, align 4 13924 // CHECK20-NEXT: [[AA_CASTED10:%.*]] = alloca i32, align 4 13925 // CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS12:%.*]] = alloca [2 x i8*], align 4 13926 // CHECK20-NEXT: [[DOTOFFLOAD_PTRS13:%.*]] = alloca [2 x i8*], align 4 13927 // CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS14:%.*]] = alloca [2 x i8*], align 4 13928 // CHECK20-NEXT: [[A_CASTED17:%.*]] = alloca i32, align 4 13929 // CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS20:%.*]] = alloca [9 x i8*], align 4 13930 // CHECK20-NEXT: [[DOTOFFLOAD_PTRS21:%.*]] = alloca [9 x i8*], align 4 13931 // CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS22:%.*]] = alloca [9 x i8*], align 4 13932 // CHECK20-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [9 x i64], align 4 13933 // CHECK20-NEXT: [[NN:%.*]] = alloca i32, align 4 13934 // CHECK20-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4 13935 // CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS27:%.*]] = alloca [1 x i8*], align 4 13936 // CHECK20-NEXT: [[DOTOFFLOAD_PTRS28:%.*]] = alloca [1 x i8*], align 4 13937 // CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS29:%.*]] = alloca [1 x i8*], align 4 13938 // CHECK20-NEXT: [[NN_CASTED32:%.*]] = alloca i32, align 4 13939 // CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS33:%.*]] = alloca [1 x i8*], align 4 13940 // CHECK20-NEXT: [[DOTOFFLOAD_PTRS34:%.*]] = alloca [1 x i8*], align 4 13941 // CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS35:%.*]] = alloca [1 x i8*], align 4 13942 // CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) 13943 // CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 13944 // CHECK20-NEXT: store i32 0, i32* [[A]], align 4 13945 // CHECK20-NEXT: store i16 0, i16* [[AA]], align 2 13946 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 13947 // CHECK20-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() 13948 // CHECK20-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 13949 // CHECK20-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP1]], align 4 13950 // CHECK20-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 13951 // CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 13952 // CHECK20-NEXT: [[TMP4:%.*]] = mul nuw i32 5, [[TMP3]] 13953 // CHECK20-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP4]], align 8 13954 // CHECK20-NEXT: store i32 [[TMP3]], i32* [[__VLA_EXPR1]], align 4 13955 // CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 13956 // CHECK20-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_]], align 4 13957 // CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 13958 // CHECK20-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_2]], align 4 13959 // CHECK20-NEXT: [[TMP7:%.*]] = load i16, i16* [[AA]], align 2 13960 // CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 13961 // CHECK20-NEXT: store i16 [[TMP7]], i16* [[CONV]], align 2 13962 // CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[AA_CASTED]], align 4 13963 // CHECK20-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 13964 // CHECK20-NEXT: store i32 [[TMP9]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 13965 // CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 13966 // CHECK20-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 13967 // CHECK20-NEXT: store i32 [[TMP11]], i32* [[DOTCAPTURE_EXPR__CASTED3]], align 4 13968 // CHECK20-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED3]], align 4 13969 // CHECK20-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 13970 // CHECK20-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i32* 13971 // CHECK20-NEXT: store i32 [[TMP8]], i32* [[TMP14]], align 4 13972 // CHECK20-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 13973 // CHECK20-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i32* 13974 // CHECK20-NEXT: store i32 [[TMP8]], i32* [[TMP16]], align 4 13975 // CHECK20-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 13976 // CHECK20-NEXT: store i8* null, i8** [[TMP17]], align 4 13977 // CHECK20-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 13978 // CHECK20-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32* 13979 // CHECK20-NEXT: store i32 [[TMP10]], i32* [[TMP19]], align 4 13980 // CHECK20-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 13981 // CHECK20-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32* 13982 // CHECK20-NEXT: store i32 [[TMP10]], i32* [[TMP21]], align 4 13983 // CHECK20-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 13984 // CHECK20-NEXT: store i8* null, i8** [[TMP22]], align 4 13985 // CHECK20-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 13986 // CHECK20-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i32* 13987 // CHECK20-NEXT: store i32 [[TMP12]], i32* [[TMP24]], align 4 13988 // CHECK20-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 13989 // CHECK20-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i32* 13990 // CHECK20-NEXT: store i32 [[TMP12]], i32* [[TMP26]], align 4 13991 // CHECK20-NEXT: [[TMP27:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 13992 // CHECK20-NEXT: store i8* null, i8** [[TMP27]], align 4 13993 // CHECK20-NEXT: [[TMP28:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 13994 // CHECK20-NEXT: [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 13995 // CHECK20-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 0 13996 // CHECK20-NEXT: [[TMP31:%.*]] = load i16, i16* [[AA]], align 2 13997 // CHECK20-NEXT: store i16 [[TMP31]], i16* [[TMP30]], align 4 13998 // CHECK20-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 1 13999 // CHECK20-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 14000 // CHECK20-NEXT: store i32 [[TMP33]], i32* [[TMP32]], align 4 14001 // CHECK20-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 2 14002 // CHECK20-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 14003 // CHECK20-NEXT: store i32 [[TMP35]], i32* [[TMP34]], align 4 14004 // CHECK20-NEXT: [[TMP36:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i32 72, i32 12, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1) 14005 // CHECK20-NEXT: [[TMP37:%.*]] = bitcast i8* [[TMP36]] to %struct.kmp_task_t_with_privates* 14006 // CHECK20-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP37]], i32 0, i32 0 14007 // CHECK20-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP38]], i32 0, i32 0 14008 // CHECK20-NEXT: [[TMP40:%.*]] = load i8*, i8** [[TMP39]], align 4 14009 // CHECK20-NEXT: [[TMP41:%.*]] = bitcast %struct.anon* [[AGG_CAPTURED]] to i8* 14010 // CHECK20-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP40]], i8* align 4 [[TMP41]], i32 12, i1 false) 14011 // CHECK20-NEXT: [[TMP42:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP37]], i32 0, i32 1 14012 // CHECK20-NEXT: [[TMP43:%.*]] = bitcast i8* [[TMP40]] to %struct.anon* 14013 // CHECK20-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 0 14014 // CHECK20-NEXT: [[TMP45:%.*]] = bitcast [3 x i64]* [[TMP44]] to i8* 14015 // CHECK20-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP45]], i8* align 4 bitcast ([3 x i64]* @.offload_sizes to i8*), i32 24, i1 false) 14016 // CHECK20-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 1 14017 // CHECK20-NEXT: [[TMP47:%.*]] = bitcast [3 x i8*]* [[TMP46]] to i8* 14018 // CHECK20-NEXT: [[TMP48:%.*]] = bitcast i8** [[TMP28]] to i8* 14019 // CHECK20-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP47]], i8* align 4 [[TMP48]], i32 12, i1 false) 14020 // CHECK20-NEXT: [[TMP49:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 2 14021 // CHECK20-NEXT: [[TMP50:%.*]] = bitcast [3 x i8*]* [[TMP49]] to i8* 14022 // CHECK20-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP29]] to i8* 14023 // CHECK20-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP50]], i8* align 4 [[TMP51]], i32 12, i1 false) 14024 // CHECK20-NEXT: [[TMP52:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 3 14025 // CHECK20-NEXT: [[TMP53:%.*]] = load i16, i16* [[AA]], align 2 14026 // CHECK20-NEXT: store i16 [[TMP53]], i16* [[TMP52]], align 4 14027 // CHECK20-NEXT: [[TMP54:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP36]]) 14028 // CHECK20-NEXT: [[TMP55:%.*]] = load i32, i32* [[A]], align 4 14029 // CHECK20-NEXT: store i32 [[TMP55]], i32* [[A_CASTED]], align 4 14030 // CHECK20-NEXT: [[TMP56:%.*]] = load i32, i32* [[A_CASTED]], align 4 14031 // CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l105(i32 [[TMP56]]) #[[ATTR3:[0-9]+]] 14032 // CHECK20-NEXT: [[TMP57:%.*]] = load i16, i16* [[AA]], align 2 14033 // CHECK20-NEXT: [[CONV5:%.*]] = bitcast i32* [[AA_CASTED4]] to i16* 14034 // CHECK20-NEXT: store i16 [[TMP57]], i16* [[CONV5]], align 2 14035 // CHECK20-NEXT: [[TMP58:%.*]] = load i32, i32* [[AA_CASTED4]], align 4 14036 // CHECK20-NEXT: [[TMP59:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0 14037 // CHECK20-NEXT: [[TMP60:%.*]] = bitcast i8** [[TMP59]] to i32* 14038 // CHECK20-NEXT: store i32 [[TMP58]], i32* [[TMP60]], align 4 14039 // CHECK20-NEXT: [[TMP61:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0 14040 // CHECK20-NEXT: [[TMP62:%.*]] = bitcast i8** [[TMP61]] to i32* 14041 // CHECK20-NEXT: store i32 [[TMP58]], i32* [[TMP62]], align 4 14042 // CHECK20-NEXT: [[TMP63:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS8]], i32 0, i32 0 14043 // CHECK20-NEXT: store i8* null, i8** [[TMP63]], align 4 14044 // CHECK20-NEXT: [[TMP64:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0 14045 // CHECK20-NEXT: [[TMP65:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0 14046 // CHECK20-NEXT: [[TMP66:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.region_id, i32 1, i8** [[TMP64]], i8** [[TMP65]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.4, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.5, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 14047 // CHECK20-NEXT: [[TMP67:%.*]] = icmp ne i32 [[TMP66]], 0 14048 // CHECK20-NEXT: br i1 [[TMP67]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 14049 // CHECK20: omp_offload.failed: 14050 // CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111(i32 [[TMP58]]) #[[ATTR3]] 14051 // CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT]] 14052 // CHECK20: omp_offload.cont: 14053 // CHECK20-NEXT: [[TMP68:%.*]] = load i32, i32* [[A]], align 4 14054 // CHECK20-NEXT: store i32 [[TMP68]], i32* [[A_CASTED9]], align 4 14055 // CHECK20-NEXT: [[TMP69:%.*]] = load i32, i32* [[A_CASTED9]], align 4 14056 // CHECK20-NEXT: [[TMP70:%.*]] = load i16, i16* [[AA]], align 2 14057 // CHECK20-NEXT: [[CONV11:%.*]] = bitcast i32* [[AA_CASTED10]] to i16* 14058 // CHECK20-NEXT: store i16 [[TMP70]], i16* [[CONV11]], align 2 14059 // CHECK20-NEXT: [[TMP71:%.*]] = load i32, i32* [[AA_CASTED10]], align 4 14060 // CHECK20-NEXT: [[TMP72:%.*]] = load i32, i32* [[N_ADDR]], align 4 14061 // CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP72]], 10 14062 // CHECK20-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 14063 // CHECK20: omp_if.then: 14064 // CHECK20-NEXT: [[TMP73:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS12]], i32 0, i32 0 14065 // CHECK20-NEXT: [[TMP74:%.*]] = bitcast i8** [[TMP73]] to i32* 14066 // CHECK20-NEXT: store i32 [[TMP69]], i32* [[TMP74]], align 4 14067 // CHECK20-NEXT: [[TMP75:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS13]], i32 0, i32 0 14068 // CHECK20-NEXT: [[TMP76:%.*]] = bitcast i8** [[TMP75]] to i32* 14069 // CHECK20-NEXT: store i32 [[TMP69]], i32* [[TMP76]], align 4 14070 // CHECK20-NEXT: [[TMP77:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS14]], i32 0, i32 0 14071 // CHECK20-NEXT: store i8* null, i8** [[TMP77]], align 4 14072 // CHECK20-NEXT: [[TMP78:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS12]], i32 0, i32 1 14073 // CHECK20-NEXT: [[TMP79:%.*]] = bitcast i8** [[TMP78]] to i32* 14074 // CHECK20-NEXT: store i32 [[TMP71]], i32* [[TMP79]], align 4 14075 // CHECK20-NEXT: [[TMP80:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS13]], i32 0, i32 1 14076 // CHECK20-NEXT: [[TMP81:%.*]] = bitcast i8** [[TMP80]] to i32* 14077 // CHECK20-NEXT: store i32 [[TMP71]], i32* [[TMP81]], align 4 14078 // CHECK20-NEXT: [[TMP82:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS14]], i32 0, i32 1 14079 // CHECK20-NEXT: store i8* null, i8** [[TMP82]], align 4 14080 // CHECK20-NEXT: [[TMP83:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS12]], i32 0, i32 0 14081 // CHECK20-NEXT: [[TMP84:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS13]], i32 0, i32 0 14082 // CHECK20-NEXT: [[TMP85:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.region_id, i32 2, i8** [[TMP83]], i8** [[TMP84]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.7, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.8, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 14083 // CHECK20-NEXT: [[TMP86:%.*]] = icmp ne i32 [[TMP85]], 0 14084 // CHECK20-NEXT: br i1 [[TMP86]], label [[OMP_OFFLOAD_FAILED15:%.*]], label [[OMP_OFFLOAD_CONT16:%.*]] 14085 // CHECK20: omp_offload.failed15: 14086 // CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i32 [[TMP69]], i32 [[TMP71]]) #[[ATTR3]] 14087 // CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT16]] 14088 // CHECK20: omp_offload.cont16: 14089 // CHECK20-NEXT: br label [[OMP_IF_END:%.*]] 14090 // CHECK20: omp_if.else: 14091 // CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i32 [[TMP69]], i32 [[TMP71]]) #[[ATTR3]] 14092 // CHECK20-NEXT: br label [[OMP_IF_END]] 14093 // CHECK20: omp_if.end: 14094 // CHECK20-NEXT: [[TMP87:%.*]] = load i32, i32* [[A]], align 4 14095 // CHECK20-NEXT: store i32 [[TMP87]], i32* [[A_CASTED17]], align 4 14096 // CHECK20-NEXT: [[TMP88:%.*]] = load i32, i32* [[A_CASTED17]], align 4 14097 // CHECK20-NEXT: [[TMP89:%.*]] = load i32, i32* [[N_ADDR]], align 4 14098 // CHECK20-NEXT: [[CMP18:%.*]] = icmp sgt i32 [[TMP89]], 20 14099 // CHECK20-NEXT: br i1 [[CMP18]], label [[OMP_IF_THEN19:%.*]], label [[OMP_IF_ELSE25:%.*]] 14100 // CHECK20: omp_if.then19: 14101 // CHECK20-NEXT: [[TMP90:%.*]] = mul nuw i32 [[TMP1]], 4 14102 // CHECK20-NEXT: [[TMP91:%.*]] = sext i32 [[TMP90]] to i64 14103 // CHECK20-NEXT: [[TMP92:%.*]] = mul nuw i32 5, [[TMP3]] 14104 // CHECK20-NEXT: [[TMP93:%.*]] = mul nuw i32 [[TMP92]], 8 14105 // CHECK20-NEXT: [[TMP94:%.*]] = sext i32 [[TMP93]] to i64 14106 // CHECK20-NEXT: [[TMP95:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0 14107 // CHECK20-NEXT: [[TMP96:%.*]] = bitcast i8** [[TMP95]] to i32* 14108 // CHECK20-NEXT: store i32 [[TMP88]], i32* [[TMP96]], align 4 14109 // CHECK20-NEXT: [[TMP97:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 0 14110 // CHECK20-NEXT: [[TMP98:%.*]] = bitcast i8** [[TMP97]] to i32* 14111 // CHECK20-NEXT: store i32 [[TMP88]], i32* [[TMP98]], align 4 14112 // CHECK20-NEXT: [[TMP99:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 14113 // CHECK20-NEXT: store i64 4, i64* [[TMP99]], align 4 14114 // CHECK20-NEXT: [[TMP100:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 0 14115 // CHECK20-NEXT: store i8* null, i8** [[TMP100]], align 4 14116 // CHECK20-NEXT: [[TMP101:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 1 14117 // CHECK20-NEXT: [[TMP102:%.*]] = bitcast i8** [[TMP101]] to [10 x float]** 14118 // CHECK20-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP102]], align 4 14119 // CHECK20-NEXT: [[TMP103:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 1 14120 // CHECK20-NEXT: [[TMP104:%.*]] = bitcast i8** [[TMP103]] to [10 x float]** 14121 // CHECK20-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP104]], align 4 14122 // CHECK20-NEXT: [[TMP105:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 14123 // CHECK20-NEXT: store i64 40, i64* [[TMP105]], align 4 14124 // CHECK20-NEXT: [[TMP106:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 1 14125 // CHECK20-NEXT: store i8* null, i8** [[TMP106]], align 4 14126 // CHECK20-NEXT: [[TMP107:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 2 14127 // CHECK20-NEXT: [[TMP108:%.*]] = bitcast i8** [[TMP107]] to i32* 14128 // CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP108]], align 4 14129 // CHECK20-NEXT: [[TMP109:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 2 14130 // CHECK20-NEXT: [[TMP110:%.*]] = bitcast i8** [[TMP109]] to i32* 14131 // CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP110]], align 4 14132 // CHECK20-NEXT: [[TMP111:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 14133 // CHECK20-NEXT: store i64 4, i64* [[TMP111]], align 4 14134 // CHECK20-NEXT: [[TMP112:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 2 14135 // CHECK20-NEXT: store i8* null, i8** [[TMP112]], align 4 14136 // CHECK20-NEXT: [[TMP113:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 3 14137 // CHECK20-NEXT: [[TMP114:%.*]] = bitcast i8** [[TMP113]] to float** 14138 // CHECK20-NEXT: store float* [[VLA]], float** [[TMP114]], align 4 14139 // CHECK20-NEXT: [[TMP115:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 3 14140 // CHECK20-NEXT: [[TMP116:%.*]] = bitcast i8** [[TMP115]] to float** 14141 // CHECK20-NEXT: store float* [[VLA]], float** [[TMP116]], align 4 14142 // CHECK20-NEXT: [[TMP117:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 14143 // CHECK20-NEXT: store i64 [[TMP91]], i64* [[TMP117]], align 4 14144 // CHECK20-NEXT: [[TMP118:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 3 14145 // CHECK20-NEXT: store i8* null, i8** [[TMP118]], align 4 14146 // CHECK20-NEXT: [[TMP119:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 4 14147 // CHECK20-NEXT: [[TMP120:%.*]] = bitcast i8** [[TMP119]] to [5 x [10 x double]]** 14148 // CHECK20-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP120]], align 4 14149 // CHECK20-NEXT: [[TMP121:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 4 14150 // CHECK20-NEXT: [[TMP122:%.*]] = bitcast i8** [[TMP121]] to [5 x [10 x double]]** 14151 // CHECK20-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP122]], align 4 14152 // CHECK20-NEXT: [[TMP123:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 14153 // CHECK20-NEXT: store i64 400, i64* [[TMP123]], align 4 14154 // CHECK20-NEXT: [[TMP124:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 4 14155 // CHECK20-NEXT: store i8* null, i8** [[TMP124]], align 4 14156 // CHECK20-NEXT: [[TMP125:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 5 14157 // CHECK20-NEXT: [[TMP126:%.*]] = bitcast i8** [[TMP125]] to i32* 14158 // CHECK20-NEXT: store i32 5, i32* [[TMP126]], align 4 14159 // CHECK20-NEXT: [[TMP127:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 5 14160 // CHECK20-NEXT: [[TMP128:%.*]] = bitcast i8** [[TMP127]] to i32* 14161 // CHECK20-NEXT: store i32 5, i32* [[TMP128]], align 4 14162 // CHECK20-NEXT: [[TMP129:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 5 14163 // CHECK20-NEXT: store i64 4, i64* [[TMP129]], align 4 14164 // CHECK20-NEXT: [[TMP130:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 5 14165 // CHECK20-NEXT: store i8* null, i8** [[TMP130]], align 4 14166 // CHECK20-NEXT: [[TMP131:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 6 14167 // CHECK20-NEXT: [[TMP132:%.*]] = bitcast i8** [[TMP131]] to i32* 14168 // CHECK20-NEXT: store i32 [[TMP3]], i32* [[TMP132]], align 4 14169 // CHECK20-NEXT: [[TMP133:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 6 14170 // CHECK20-NEXT: [[TMP134:%.*]] = bitcast i8** [[TMP133]] to i32* 14171 // CHECK20-NEXT: store i32 [[TMP3]], i32* [[TMP134]], align 4 14172 // CHECK20-NEXT: [[TMP135:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 6 14173 // CHECK20-NEXT: store i64 4, i64* [[TMP135]], align 4 14174 // CHECK20-NEXT: [[TMP136:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 6 14175 // CHECK20-NEXT: store i8* null, i8** [[TMP136]], align 4 14176 // CHECK20-NEXT: [[TMP137:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 7 14177 // CHECK20-NEXT: [[TMP138:%.*]] = bitcast i8** [[TMP137]] to double** 14178 // CHECK20-NEXT: store double* [[VLA1]], double** [[TMP138]], align 4 14179 // CHECK20-NEXT: [[TMP139:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 7 14180 // CHECK20-NEXT: [[TMP140:%.*]] = bitcast i8** [[TMP139]] to double** 14181 // CHECK20-NEXT: store double* [[VLA1]], double** [[TMP140]], align 4 14182 // CHECK20-NEXT: [[TMP141:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 14183 // CHECK20-NEXT: store i64 [[TMP94]], i64* [[TMP141]], align 4 14184 // CHECK20-NEXT: [[TMP142:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 7 14185 // CHECK20-NEXT: store i8* null, i8** [[TMP142]], align 4 14186 // CHECK20-NEXT: [[TMP143:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 8 14187 // CHECK20-NEXT: [[TMP144:%.*]] = bitcast i8** [[TMP143]] to %struct.TT** 14188 // CHECK20-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP144]], align 4 14189 // CHECK20-NEXT: [[TMP145:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 8 14190 // CHECK20-NEXT: [[TMP146:%.*]] = bitcast i8** [[TMP145]] to %struct.TT** 14191 // CHECK20-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP146]], align 4 14192 // CHECK20-NEXT: [[TMP147:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 8 14193 // CHECK20-NEXT: store i64 12, i64* [[TMP147]], align 4 14194 // CHECK20-NEXT: [[TMP148:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 8 14195 // CHECK20-NEXT: store i8* null, i8** [[TMP148]], align 4 14196 // CHECK20-NEXT: [[TMP149:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0 14197 // CHECK20-NEXT: [[TMP150:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 0 14198 // CHECK20-NEXT: [[TMP151:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 14199 // CHECK20-NEXT: [[TMP152:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142.region_id, i32 9, i8** [[TMP149]], i8** [[TMP150]], i64* [[TMP151]], i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 14200 // CHECK20-NEXT: [[TMP153:%.*]] = icmp ne i32 [[TMP152]], 0 14201 // CHECK20-NEXT: br i1 [[TMP153]], label [[OMP_OFFLOAD_FAILED23:%.*]], label [[OMP_OFFLOAD_CONT24:%.*]] 14202 // CHECK20: omp_offload.failed23: 14203 // CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i32 [[TMP88]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR3]] 14204 // CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT24]] 14205 // CHECK20: omp_offload.cont24: 14206 // CHECK20-NEXT: br label [[OMP_IF_END26:%.*]] 14207 // CHECK20: omp_if.else25: 14208 // CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i32 [[TMP88]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR3]] 14209 // CHECK20-NEXT: br label [[OMP_IF_END26]] 14210 // CHECK20: omp_if.end26: 14211 // CHECK20-NEXT: store i32 0, i32* [[NN]], align 4 14212 // CHECK20-NEXT: [[TMP154:%.*]] = load i32, i32* [[NN]], align 4 14213 // CHECK20-NEXT: store i32 [[TMP154]], i32* [[NN_CASTED]], align 4 14214 // CHECK20-NEXT: [[TMP155:%.*]] = load i32, i32* [[NN_CASTED]], align 4 14215 // CHECK20-NEXT: [[TMP156:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS27]], i32 0, i32 0 14216 // CHECK20-NEXT: [[TMP157:%.*]] = bitcast i8** [[TMP156]] to i32* 14217 // CHECK20-NEXT: store i32 [[TMP155]], i32* [[TMP157]], align 4 14218 // CHECK20-NEXT: [[TMP158:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS28]], i32 0, i32 0 14219 // CHECK20-NEXT: [[TMP159:%.*]] = bitcast i8** [[TMP158]] to i32* 14220 // CHECK20-NEXT: store i32 [[TMP155]], i32* [[TMP159]], align 4 14221 // CHECK20-NEXT: [[TMP160:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS29]], i32 0, i32 0 14222 // CHECK20-NEXT: store i8* null, i8** [[TMP160]], align 4 14223 // CHECK20-NEXT: [[TMP161:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS27]], i32 0, i32 0 14224 // CHECK20-NEXT: [[TMP162:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS28]], i32 0, i32 0 14225 // CHECK20-NEXT: [[TMP163:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154.region_id, i32 1, i8** [[TMP161]], i8** [[TMP162]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.13, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.14, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 14226 // CHECK20-NEXT: [[TMP164:%.*]] = icmp ne i32 [[TMP163]], 0 14227 // CHECK20-NEXT: br i1 [[TMP164]], label [[OMP_OFFLOAD_FAILED30:%.*]], label [[OMP_OFFLOAD_CONT31:%.*]] 14228 // CHECK20: omp_offload.failed30: 14229 // CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154(i32 [[TMP155]]) #[[ATTR3]] 14230 // CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT31]] 14231 // CHECK20: omp_offload.cont31: 14232 // CHECK20-NEXT: [[TMP165:%.*]] = load i32, i32* [[NN]], align 4 14233 // CHECK20-NEXT: store i32 [[TMP165]], i32* [[NN_CASTED32]], align 4 14234 // CHECK20-NEXT: [[TMP166:%.*]] = load i32, i32* [[NN_CASTED32]], align 4 14235 // CHECK20-NEXT: [[TMP167:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS33]], i32 0, i32 0 14236 // CHECK20-NEXT: [[TMP168:%.*]] = bitcast i8** [[TMP167]] to i32* 14237 // CHECK20-NEXT: store i32 [[TMP166]], i32* [[TMP168]], align 4 14238 // CHECK20-NEXT: [[TMP169:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS34]], i32 0, i32 0 14239 // CHECK20-NEXT: [[TMP170:%.*]] = bitcast i8** [[TMP169]] to i32* 14240 // CHECK20-NEXT: store i32 [[TMP166]], i32* [[TMP170]], align 4 14241 // CHECK20-NEXT: [[TMP171:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS35]], i32 0, i32 0 14242 // CHECK20-NEXT: store i8* null, i8** [[TMP171]], align 4 14243 // CHECK20-NEXT: [[TMP172:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS33]], i32 0, i32 0 14244 // CHECK20-NEXT: [[TMP173:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS34]], i32 0, i32 0 14245 // CHECK20-NEXT: [[TMP174:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157.region_id, i32 1, i8** [[TMP172]], i8** [[TMP173]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.17, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.18, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 14246 // CHECK20-NEXT: [[TMP175:%.*]] = icmp ne i32 [[TMP174]], 0 14247 // CHECK20-NEXT: br i1 [[TMP175]], label [[OMP_OFFLOAD_FAILED36:%.*]], label [[OMP_OFFLOAD_CONT37:%.*]] 14248 // CHECK20: omp_offload.failed36: 14249 // CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157(i32 [[TMP166]]) #[[ATTR3]] 14250 // CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT37]] 14251 // CHECK20: omp_offload.cont37: 14252 // CHECK20-NEXT: [[TMP176:%.*]] = load i32, i32* [[A]], align 4 14253 // CHECK20-NEXT: [[TMP177:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 14254 // CHECK20-NEXT: call void @llvm.stackrestore(i8* [[TMP177]]) 14255 // CHECK20-NEXT: ret i32 [[TMP176]] 14256 // 14257 // 14258 // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101 14259 // CHECK20-SAME: (i32 [[AA:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]], i32 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] { 14260 // CHECK20-NEXT: entry: 14261 // CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 14262 // CHECK20-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 14263 // CHECK20-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4 14264 // CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 14265 // CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 14266 // CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 14267 // CHECK20-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 14268 // CHECK20-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 14269 // CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 14270 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 14271 // CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 14272 // CHECK20-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) 14273 // CHECK20-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 14274 // CHECK20-NEXT: [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 14275 // CHECK20-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 14276 // CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 14277 // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]]) 14278 // CHECK20-NEXT: ret void 14279 // 14280 // 14281 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined. 14282 // CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] { 14283 // CHECK20-NEXT: entry: 14284 // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 14285 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 14286 // CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 14287 // CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 14288 // CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 14289 // CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 14290 // CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 14291 // CHECK20-NEXT: ret void 14292 // 14293 // 14294 // CHECK20-LABEL: define {{[^@]+}}@.omp_task_privates_map. 14295 // CHECK20-SAME: (%struct..kmp_privates.t* noalias [[TMP0:%.*]], i16** noalias [[TMP1:%.*]], [3 x i8*]** noalias [[TMP2:%.*]], [3 x i8*]** noalias [[TMP3:%.*]], [3 x i64]** noalias [[TMP4:%.*]]) #[[ATTR4:[0-9]+]] { 14296 // CHECK20-NEXT: entry: 14297 // CHECK20-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 4 14298 // CHECK20-NEXT: [[DOTADDR1:%.*]] = alloca i16**, align 4 14299 // CHECK20-NEXT: [[DOTADDR2:%.*]] = alloca [3 x i8*]**, align 4 14300 // CHECK20-NEXT: [[DOTADDR3:%.*]] = alloca [3 x i8*]**, align 4 14301 // CHECK20-NEXT: [[DOTADDR4:%.*]] = alloca [3 x i64]**, align 4 14302 // CHECK20-NEXT: store %struct..kmp_privates.t* [[TMP0]], %struct..kmp_privates.t** [[DOTADDR]], align 4 14303 // CHECK20-NEXT: store i16** [[TMP1]], i16*** [[DOTADDR1]], align 4 14304 // CHECK20-NEXT: store [3 x i8*]** [[TMP2]], [3 x i8*]*** [[DOTADDR2]], align 4 14305 // CHECK20-NEXT: store [3 x i8*]** [[TMP3]], [3 x i8*]*** [[DOTADDR3]], align 4 14306 // CHECK20-NEXT: store [3 x i64]** [[TMP4]], [3 x i64]*** [[DOTADDR4]], align 4 14307 // CHECK20-NEXT: [[TMP5:%.*]] = load %struct..kmp_privates.t*, %struct..kmp_privates.t** [[DOTADDR]], align 4 14308 // CHECK20-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 0 14309 // CHECK20-NEXT: [[TMP7:%.*]] = load [3 x i64]**, [3 x i64]*** [[DOTADDR4]], align 4 14310 // CHECK20-NEXT: store [3 x i64]* [[TMP6]], [3 x i64]** [[TMP7]], align 4 14311 // CHECK20-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 1 14312 // CHECK20-NEXT: [[TMP9:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR2]], align 4 14313 // CHECK20-NEXT: store [3 x i8*]* [[TMP8]], [3 x i8*]** [[TMP9]], align 4 14314 // CHECK20-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 2 14315 // CHECK20-NEXT: [[TMP11:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR3]], align 4 14316 // CHECK20-NEXT: store [3 x i8*]* [[TMP10]], [3 x i8*]** [[TMP11]], align 4 14317 // CHECK20-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 3 14318 // CHECK20-NEXT: [[TMP13:%.*]] = load i16**, i16*** [[DOTADDR1]], align 4 14319 // CHECK20-NEXT: store i16* [[TMP12]], i16** [[TMP13]], align 4 14320 // CHECK20-NEXT: ret void 14321 // 14322 // 14323 // CHECK20-LABEL: define {{[^@]+}}@.omp_task_entry. 14324 // CHECK20-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { 14325 // CHECK20-NEXT: entry: 14326 // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 14327 // CHECK20-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 4 14328 // CHECK20-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 4 14329 // CHECK20-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 4 14330 // CHECK20-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 4 14331 // CHECK20-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 4 14332 // CHECK20-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca i16*, align 4 14333 // CHECK20-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca [3 x i8*]*, align 4 14334 // CHECK20-NEXT: [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca [3 x i8*]*, align 4 14335 // CHECK20-NEXT: [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca [3 x i64]*, align 4 14336 // CHECK20-NEXT: [[AA_CASTED_I:%.*]] = alloca i32, align 4 14337 // CHECK20-NEXT: [[DOTCAPTURE_EXPR__CASTED_I:%.*]] = alloca i32, align 4 14338 // CHECK20-NEXT: [[DOTCAPTURE_EXPR__CASTED4_I:%.*]] = alloca i32, align 4 14339 // CHECK20-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 14340 // CHECK20-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 4 14341 // CHECK20-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 14342 // CHECK20-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4 14343 // CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 14344 // CHECK20-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4 14345 // CHECK20-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0 14346 // CHECK20-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 14347 // CHECK20-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 14348 // CHECK20-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 4 14349 // CHECK20-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon* 14350 // CHECK20-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1 14351 // CHECK20-NEXT: [[TMP10:%.*]] = bitcast %struct..kmp_privates.t* [[TMP9]] to i8* 14352 // CHECK20-NEXT: [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8* 14353 // CHECK20-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]]) 14354 // CHECK20-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]]) 14355 // CHECK20-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]]) 14356 // CHECK20-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META22:![0-9]+]]) 14357 // CHECK20-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !24 14358 // CHECK20-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 4, !noalias !24 14359 // CHECK20-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !24 14360 // CHECK20-NEXT: store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* @.omp_task_privates_map. to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !24 14361 // CHECK20-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 4, !noalias !24 14362 // CHECK20-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !24 14363 // CHECK20-NEXT: [[TMP12:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !24 14364 // CHECK20-NEXT: [[TMP13:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !24 14365 // CHECK20-NEXT: [[TMP14:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !24 14366 // CHECK20-NEXT: [[TMP15:%.*]] = bitcast void (i8*, ...)* [[TMP13]] to void (i8*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* 14367 // CHECK20-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]] 14368 // CHECK20-NEXT: [[TMP16:%.*]] = load i16*, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 4, !noalias !24 14369 // CHECK20-NEXT: [[TMP17:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 4, !noalias !24 14370 // CHECK20-NEXT: [[TMP18:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 4, !noalias !24 14371 // CHECK20-NEXT: [[TMP19:%.*]] = load [3 x i64]*, [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 4, !noalias !24 14372 // CHECK20-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP17]], i32 0, i32 0 14373 // CHECK20-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP18]], i32 0, i32 0 14374 // CHECK20-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[TMP19]], i32 0, i32 0 14375 // CHECK20-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP12]], i32 0, i32 1 14376 // CHECK20-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[TMP12]], i32 0, i32 2 14377 // CHECK20-NEXT: [[TMP25:%.*]] = load i32, i32* [[TMP23]], align 4 14378 // CHECK20-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP24]], align 4 14379 // CHECK20-NEXT: [[TMP27:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 [[TMP25]], i32 [[TMP26]]) #[[ATTR3]] 14380 // CHECK20-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0 14381 // CHECK20-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]] 14382 // CHECK20: omp_offload.failed.i: 14383 // CHECK20-NEXT: [[TMP29:%.*]] = load i16, i16* [[TMP16]], align 2 14384 // CHECK20-NEXT: [[CONV_I:%.*]] = bitcast i32* [[AA_CASTED_I]] to i16* 14385 // CHECK20-NEXT: store i16 [[TMP29]], i16* [[CONV_I]], align 2, !noalias !24 14386 // CHECK20-NEXT: [[TMP30:%.*]] = load i32, i32* [[AA_CASTED_I]], align 4, !noalias !24 14387 // CHECK20-NEXT: [[TMP31:%.*]] = load i32, i32* [[TMP23]], align 4 14388 // CHECK20-NEXT: store i32 [[TMP31]], i32* [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias !24 14389 // CHECK20-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias !24 14390 // CHECK20-NEXT: [[TMP33:%.*]] = load i32, i32* [[TMP24]], align 4 14391 // CHECK20-NEXT: store i32 [[TMP33]], i32* [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias !24 14392 // CHECK20-NEXT: [[TMP34:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias !24 14393 // CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101(i32 [[TMP30]], i32 [[TMP32]], i32 [[TMP34]]) #[[ATTR3]] 14394 // CHECK20-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]] 14395 // CHECK20: .omp_outlined..1.exit: 14396 // CHECK20-NEXT: ret i32 0 14397 // 14398 // 14399 // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l105 14400 // CHECK20-SAME: (i32 [[A:%.*]]) #[[ATTR2]] { 14401 // CHECK20-NEXT: entry: 14402 // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 14403 // CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 14404 // CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 14405 // CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 14406 // CHECK20-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 14407 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 14408 // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]]) 14409 // CHECK20-NEXT: ret void 14410 // 14411 // 14412 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..2 14413 // CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]]) #[[ATTR2]] { 14414 // CHECK20-NEXT: entry: 14415 // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 14416 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 14417 // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 14418 // CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 14419 // CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 14420 // CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 14421 // CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 14422 // CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 14423 // CHECK20-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 14424 // CHECK20-NEXT: ret void 14425 // 14426 // 14427 // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 14428 // CHECK20-SAME: (i32 [[AA:%.*]]) #[[ATTR2]] { 14429 // CHECK20-NEXT: entry: 14430 // CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 14431 // CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 14432 // CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 14433 // CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 14434 // CHECK20-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 14435 // CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 14436 // CHECK20-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 14437 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 14438 // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP1]]) 14439 // CHECK20-NEXT: ret void 14440 // 14441 // 14442 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..3 14443 // CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] { 14444 // CHECK20-NEXT: entry: 14445 // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 14446 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 14447 // CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 14448 // CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 14449 // CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 14450 // CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 14451 // CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 14452 // CHECK20-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 14453 // CHECK20-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 14454 // CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 14455 // CHECK20-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 14456 // CHECK20-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 4 14457 // CHECK20-NEXT: ret void 14458 // 14459 // 14460 // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118 14461 // CHECK20-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] { 14462 // CHECK20-NEXT: entry: 14463 // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 14464 // CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 14465 // CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 14466 // CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 14467 // CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 14468 // CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 14469 // CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 14470 // CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 14471 // CHECK20-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 14472 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 14473 // CHECK20-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 14474 // CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 14475 // CHECK20-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 14476 // CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 14477 // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) 14478 // CHECK20-NEXT: ret void 14479 // 14480 // 14481 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..6 14482 // CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] { 14483 // CHECK20-NEXT: entry: 14484 // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 14485 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 14486 // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 14487 // CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 14488 // CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 14489 // CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 14490 // CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 14491 // CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 14492 // CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 14493 // CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 14494 // CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 14495 // CHECK20-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 14496 // CHECK20-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 4 14497 // CHECK20-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32 14498 // CHECK20-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 14499 // CHECK20-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 14500 // CHECK20-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 4 14501 // CHECK20-NEXT: ret void 14502 // 14503 // 14504 // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142 14505 // CHECK20-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] { 14506 // CHECK20-NEXT: entry: 14507 // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 14508 // CHECK20-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 14509 // CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 14510 // CHECK20-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 14511 // CHECK20-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 14512 // CHECK20-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 14513 // CHECK20-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 14514 // CHECK20-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 14515 // CHECK20-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 14516 // CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 14517 // CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 14518 // CHECK20-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 14519 // CHECK20-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 14520 // CHECK20-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 14521 // CHECK20-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 14522 // CHECK20-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 14523 // CHECK20-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 14524 // CHECK20-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 14525 // CHECK20-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 14526 // CHECK20-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 14527 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 14528 // CHECK20-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 14529 // CHECK20-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 14530 // CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 14531 // CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 14532 // CHECK20-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 14533 // CHECK20-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 14534 // CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 14535 // CHECK20-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4 14536 // CHECK20-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4 14537 // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) 14538 // CHECK20-NEXT: ret void 14539 // 14540 // 14541 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..9 14542 // CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] { 14543 // CHECK20-NEXT: entry: 14544 // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 14545 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 14546 // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 14547 // CHECK20-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 14548 // CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 14549 // CHECK20-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 14550 // CHECK20-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 14551 // CHECK20-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 14552 // CHECK20-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 14553 // CHECK20-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 14554 // CHECK20-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 14555 // CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 14556 // CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 14557 // CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 14558 // CHECK20-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 14559 // CHECK20-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 14560 // CHECK20-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 14561 // CHECK20-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 14562 // CHECK20-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 14563 // CHECK20-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 14564 // CHECK20-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 14565 // CHECK20-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 14566 // CHECK20-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 14567 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 14568 // CHECK20-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 14569 // CHECK20-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 14570 // CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 14571 // CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 14572 // CHECK20-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 14573 // CHECK20-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 14574 // CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 14575 // CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 14576 // CHECK20-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 14577 // CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2 14578 // CHECK20-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 14579 // CHECK20-NEXT: [[CONV:%.*]] = fpext float [[TMP9]] to double 14580 // CHECK20-NEXT: [[ADD5:%.*]] = fadd double [[CONV]], 1.000000e+00 14581 // CHECK20-NEXT: [[CONV6:%.*]] = fptrunc double [[ADD5]] to float 14582 // CHECK20-NEXT: store float [[CONV6]], float* [[ARRAYIDX]], align 4 14583 // CHECK20-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3 14584 // CHECK20-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX7]], align 4 14585 // CHECK20-NEXT: [[CONV8:%.*]] = fpext float [[TMP10]] to double 14586 // CHECK20-NEXT: [[ADD9:%.*]] = fadd double [[CONV8]], 1.000000e+00 14587 // CHECK20-NEXT: [[CONV10:%.*]] = fptrunc double [[ADD9]] to float 14588 // CHECK20-NEXT: store float [[CONV10]], float* [[ARRAYIDX7]], align 4 14589 // CHECK20-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1 14590 // CHECK20-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX11]], i32 0, i32 2 14591 // CHECK20-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX12]], align 8 14592 // CHECK20-NEXT: [[ADD13:%.*]] = fadd double [[TMP11]], 1.000000e+00 14593 // CHECK20-NEXT: store double [[ADD13]], double* [[ARRAYIDX12]], align 8 14594 // CHECK20-NEXT: [[TMP12:%.*]] = mul nsw i32 1, [[TMP5]] 14595 // CHECK20-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP12]] 14596 // CHECK20-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX14]], i32 3 14597 // CHECK20-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX15]], align 8 14598 // CHECK20-NEXT: [[ADD16:%.*]] = fadd double [[TMP13]], 1.000000e+00 14599 // CHECK20-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8 14600 // CHECK20-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 14601 // CHECK20-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 4 14602 // CHECK20-NEXT: [[ADD17:%.*]] = add nsw i64 [[TMP14]], 1 14603 // CHECK20-NEXT: store i64 [[ADD17]], i64* [[X]], align 4 14604 // CHECK20-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 14605 // CHECK20-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 4 14606 // CHECK20-NEXT: [[CONV18:%.*]] = sext i8 [[TMP15]] to i32 14607 // CHECK20-NEXT: [[ADD19:%.*]] = add nsw i32 [[CONV18]], 1 14608 // CHECK20-NEXT: [[CONV20:%.*]] = trunc i32 [[ADD19]] to i8 14609 // CHECK20-NEXT: store i8 [[CONV20]], i8* [[Y]], align 4 14610 // CHECK20-NEXT: ret void 14611 // 14612 // 14613 // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154 14614 // CHECK20-SAME: (i32 [[NN:%.*]]) #[[ATTR2]] { 14615 // CHECK20-NEXT: entry: 14616 // CHECK20-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 14617 // CHECK20-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4 14618 // CHECK20-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 14619 // CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[NN_ADDR]], align 4 14620 // CHECK20-NEXT: store i32 [[TMP0]], i32* [[NN_CASTED]], align 4 14621 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[NN_CASTED]], align 4 14622 // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP1]]) 14623 // CHECK20-NEXT: ret void 14624 // 14625 // 14626 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..11 14627 // CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[NN:%.*]]) #[[ATTR2]] { 14628 // CHECK20-NEXT: entry: 14629 // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 14630 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 14631 // CHECK20-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 14632 // CHECK20-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4 14633 // CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 14634 // CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 14635 // CHECK20-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 14636 // CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[NN_ADDR]], align 4 14637 // CHECK20-NEXT: store i32 [[TMP0]], i32* [[NN_CASTED]], align 4 14638 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[NN_CASTED]], align 4 14639 // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..12 to void (i32*, i32*, ...)*), i32 [[TMP1]]) 14640 // CHECK20-NEXT: ret void 14641 // 14642 // 14643 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..12 14644 // CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[NN:%.*]]) #[[ATTR2]] { 14645 // CHECK20-NEXT: entry: 14646 // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 14647 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 14648 // CHECK20-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 14649 // CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 14650 // CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 14651 // CHECK20-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 14652 // CHECK20-NEXT: ret void 14653 // 14654 // 14655 // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157 14656 // CHECK20-SAME: (i32 [[NN:%.*]]) #[[ATTR2]] { 14657 // CHECK20-NEXT: entry: 14658 // CHECK20-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 14659 // CHECK20-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4 14660 // CHECK20-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 14661 // CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[NN_ADDR]], align 4 14662 // CHECK20-NEXT: store i32 [[TMP0]], i32* [[NN_CASTED]], align 4 14663 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[NN_CASTED]], align 4 14664 // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..15 to void (i32*, i32*, ...)*), i32 [[TMP1]]) 14665 // CHECK20-NEXT: ret void 14666 // 14667 // 14668 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..15 14669 // CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[NN:%.*]]) #[[ATTR2]] { 14670 // CHECK20-NEXT: entry: 14671 // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 14672 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 14673 // CHECK20-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 14674 // CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 14675 // CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 14676 // CHECK20-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 14677 // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i32* [[NN_ADDR]]) 14678 // CHECK20-NEXT: ret void 14679 // 14680 // 14681 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..16 14682 // CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[NN:%.*]]) #[[ATTR2]] { 14683 // CHECK20-NEXT: entry: 14684 // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 14685 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 14686 // CHECK20-NEXT: [[NN_ADDR:%.*]] = alloca i32*, align 4 14687 // CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 14688 // CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 14689 // CHECK20-NEXT: store i32* [[NN]], i32** [[NN_ADDR]], align 4 14690 // CHECK20-NEXT: [[TMP0:%.*]] = load i32*, i32** [[NN_ADDR]], align 4 14691 // CHECK20-NEXT: ret void 14692 // 14693 // 14694 // CHECK20-LABEL: define {{[^@]+}}@_Z6bazzzziPi 14695 // CHECK20-SAME: (i32 [[N:%.*]], i32* [[F:%.*]]) #[[ATTR0]] { 14696 // CHECK20-NEXT: entry: 14697 // CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 14698 // CHECK20-NEXT: [[F_ADDR:%.*]] = alloca i32*, align 4 14699 // CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 14700 // CHECK20-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 14701 // CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 14702 // CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 14703 // CHECK20-NEXT: store i32* [[F]], i32** [[F_ADDR]], align 4 14704 // CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 14705 // CHECK20-NEXT: [[TMP1:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 14706 // CHECK20-NEXT: [[TMP2:%.*]] = bitcast i8** [[TMP1]] to i32* 14707 // CHECK20-NEXT: store i32 [[TMP0]], i32* [[TMP2]], align 4 14708 // CHECK20-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 14709 // CHECK20-NEXT: [[TMP4:%.*]] = bitcast i8** [[TMP3]] to i32* 14710 // CHECK20-NEXT: store i32 [[TMP0]], i32* [[TMP4]], align 4 14711 // CHECK20-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 14712 // CHECK20-NEXT: store i8* null, i8** [[TMP5]], align 4 14713 // CHECK20-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 14714 // CHECK20-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 14715 // CHECK20-NEXT: [[TMP8:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182.region_id, i32 1, i8** [[TMP6]], i8** [[TMP7]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.20, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.21, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 14716 // CHECK20-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0 14717 // CHECK20-NEXT: br i1 [[TMP9]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 14718 // CHECK20: omp_offload.failed: 14719 // CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182(i32 [[TMP0]]) #[[ATTR3]] 14720 // CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT]] 14721 // CHECK20: omp_offload.cont: 14722 // CHECK20-NEXT: ret void 14723 // 14724 // 14725 // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182 14726 // CHECK20-SAME: (i32 [[VLA:%.*]]) #[[ATTR2]] { 14727 // CHECK20-NEXT: entry: 14728 // CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 14729 // CHECK20-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 14730 // CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 14731 // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..19 to void (i32*, i32*, ...)*), i32 [[TMP0]]) 14732 // CHECK20-NEXT: ret void 14733 // 14734 // 14735 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..19 14736 // CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[VLA:%.*]]) #[[ATTR2]] { 14737 // CHECK20-NEXT: entry: 14738 // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 14739 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 14740 // CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 14741 // CHECK20-NEXT: [[F:%.*]] = alloca i32*, align 4 14742 // CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 14743 // CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 14744 // CHECK20-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 14745 // CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 14746 // CHECK20-NEXT: ret void 14747 // 14748 // 14749 // CHECK20-LABEL: define {{[^@]+}}@_Z3bari 14750 // CHECK20-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { 14751 // CHECK20-NEXT: entry: 14752 // CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 14753 // CHECK20-NEXT: [[A:%.*]] = alloca i32, align 4 14754 // CHECK20-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 14755 // CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 14756 // CHECK20-NEXT: store i32 0, i32* [[A]], align 4 14757 // CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 14758 // CHECK20-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]]) 14759 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 14760 // CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 14761 // CHECK20-NEXT: store i32 [[ADD]], i32* [[A]], align 4 14762 // CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 14763 // CHECK20-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]]) 14764 // CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 14765 // CHECK20-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 14766 // CHECK20-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 14767 // CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 14768 // CHECK20-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]]) 14769 // CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 14770 // CHECK20-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 14771 // CHECK20-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 14772 // CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 14773 // CHECK20-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]]) 14774 // CHECK20-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 14775 // CHECK20-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] 14776 // CHECK20-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 14777 // CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 14778 // CHECK20-NEXT: ret i32 [[TMP8]] 14779 // 14780 // 14781 // CHECK20-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 14782 // CHECK20-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { 14783 // CHECK20-NEXT: entry: 14784 // CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 14785 // CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 14786 // CHECK20-NEXT: [[B:%.*]] = alloca i32, align 4 14787 // CHECK20-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 14788 // CHECK20-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 14789 // CHECK20-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 14790 // CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4 14791 // CHECK20-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4 14792 // CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4 14793 // CHECK20-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 4 14794 // CHECK20-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 14795 // CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 14796 // CHECK20-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 14797 // CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 14798 // CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 14799 // CHECK20-NEXT: store i32 [[ADD]], i32* [[B]], align 4 14800 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 14801 // CHECK20-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() 14802 // CHECK20-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 14803 // CHECK20-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] 14804 // CHECK20-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 14805 // CHECK20-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 14806 // CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[B]], align 4 14807 // CHECK20-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 14808 // CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 14809 // CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 14810 // CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 60 14811 // CHECK20-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 14812 // CHECK20: omp_if.then: 14813 // CHECK20-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 14814 // CHECK20-NEXT: [[TMP7:%.*]] = mul nuw i32 2, [[TMP1]] 14815 // CHECK20-NEXT: [[TMP8:%.*]] = mul nuw i32 [[TMP7]], 2 14816 // CHECK20-NEXT: [[TMP9:%.*]] = sext i32 [[TMP8]] to i64 14817 // CHECK20-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 14818 // CHECK20-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to %struct.S1** 14819 // CHECK20-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP11]], align 4 14820 // CHECK20-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 14821 // CHECK20-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to double** 14822 // CHECK20-NEXT: store double* [[A]], double** [[TMP13]], align 4 14823 // CHECK20-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 14824 // CHECK20-NEXT: store i64 8, i64* [[TMP14]], align 4 14825 // CHECK20-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 14826 // CHECK20-NEXT: store i8* null, i8** [[TMP15]], align 4 14827 // CHECK20-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 14828 // CHECK20-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32* 14829 // CHECK20-NEXT: store i32 [[TMP5]], i32* [[TMP17]], align 4 14830 // CHECK20-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 14831 // CHECK20-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32* 14832 // CHECK20-NEXT: store i32 [[TMP5]], i32* [[TMP19]], align 4 14833 // CHECK20-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 14834 // CHECK20-NEXT: store i64 4, i64* [[TMP20]], align 4 14835 // CHECK20-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 14836 // CHECK20-NEXT: store i8* null, i8** [[TMP21]], align 4 14837 // CHECK20-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 14838 // CHECK20-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i32* 14839 // CHECK20-NEXT: store i32 2, i32* [[TMP23]], align 4 14840 // CHECK20-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 14841 // CHECK20-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i32* 14842 // CHECK20-NEXT: store i32 2, i32* [[TMP25]], align 4 14843 // CHECK20-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 14844 // CHECK20-NEXT: store i64 4, i64* [[TMP26]], align 4 14845 // CHECK20-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 14846 // CHECK20-NEXT: store i8* null, i8** [[TMP27]], align 4 14847 // CHECK20-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 14848 // CHECK20-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i32* 14849 // CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP29]], align 4 14850 // CHECK20-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 14851 // CHECK20-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i32* 14852 // CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP31]], align 4 14853 // CHECK20-NEXT: [[TMP32:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 14854 // CHECK20-NEXT: store i64 4, i64* [[TMP32]], align 4 14855 // CHECK20-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 14856 // CHECK20-NEXT: store i8* null, i8** [[TMP33]], align 4 14857 // CHECK20-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 14858 // CHECK20-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i16** 14859 // CHECK20-NEXT: store i16* [[VLA]], i16** [[TMP35]], align 4 14860 // CHECK20-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 14861 // CHECK20-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i16** 14862 // CHECK20-NEXT: store i16* [[VLA]], i16** [[TMP37]], align 4 14863 // CHECK20-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 14864 // CHECK20-NEXT: store i64 [[TMP9]], i64* [[TMP38]], align 4 14865 // CHECK20-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 14866 // CHECK20-NEXT: store i8* null, i8** [[TMP39]], align 4 14867 // CHECK20-NEXT: [[TMP40:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 14868 // CHECK20-NEXT: [[TMP41:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 14869 // CHECK20-NEXT: [[TMP42:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 14870 // CHECK20-NEXT: [[TMP43:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227.region_id, i32 5, i8** [[TMP40]], i8** [[TMP41]], i64* [[TMP42]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.23, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 14871 // CHECK20-NEXT: [[TMP44:%.*]] = icmp ne i32 [[TMP43]], 0 14872 // CHECK20-NEXT: br i1 [[TMP44]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 14873 // CHECK20: omp_offload.failed: 14874 // CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR3]] 14875 // CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT]] 14876 // CHECK20: omp_offload.cont: 14877 // CHECK20-NEXT: br label [[OMP_IF_END:%.*]] 14878 // CHECK20: omp_if.else: 14879 // CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR3]] 14880 // CHECK20-NEXT: br label [[OMP_IF_END]] 14881 // CHECK20: omp_if.end: 14882 // CHECK20-NEXT: [[TMP45:%.*]] = mul nsw i32 1, [[TMP1]] 14883 // CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP45]] 14884 // CHECK20-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 14885 // CHECK20-NEXT: [[TMP46:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2 14886 // CHECK20-NEXT: [[CONV:%.*]] = sext i16 [[TMP46]] to i32 14887 // CHECK20-NEXT: [[TMP47:%.*]] = load i32, i32* [[B]], align 4 14888 // CHECK20-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP47]] 14889 // CHECK20-NEXT: [[TMP48:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 14890 // CHECK20-NEXT: call void @llvm.stackrestore(i8* [[TMP48]]) 14891 // CHECK20-NEXT: ret i32 [[ADD3]] 14892 // 14893 // 14894 // CHECK20-LABEL: define {{[^@]+}}@_ZL7fstatici 14895 // CHECK20-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { 14896 // CHECK20-NEXT: entry: 14897 // CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 14898 // CHECK20-NEXT: [[A:%.*]] = alloca i32, align 4 14899 // CHECK20-NEXT: [[AA:%.*]] = alloca i16, align 2 14900 // CHECK20-NEXT: [[AAA:%.*]] = alloca i8, align 1 14901 // CHECK20-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 14902 // CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 14903 // CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 14904 // CHECK20-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 14905 // CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4 14906 // CHECK20-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 14907 // CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 14908 // CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 14909 // CHECK20-NEXT: store i32 0, i32* [[A]], align 4 14910 // CHECK20-NEXT: store i16 0, i16* [[AA]], align 2 14911 // CHECK20-NEXT: store i8 0, i8* [[AAA]], align 1 14912 // CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 14913 // CHECK20-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 14914 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 14915 // CHECK20-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 14916 // CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 14917 // CHECK20-NEXT: store i16 [[TMP2]], i16* [[CONV]], align 2 14918 // CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 14919 // CHECK20-NEXT: [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1 14920 // CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* 14921 // CHECK20-NEXT: store i8 [[TMP4]], i8* [[CONV1]], align 1 14922 // CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 14923 // CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 14924 // CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50 14925 // CHECK20-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 14926 // CHECK20: omp_if.then: 14927 // CHECK20-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 14928 // CHECK20-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* 14929 // CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4 14930 // CHECK20-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 14931 // CHECK20-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* 14932 // CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP10]], align 4 14933 // CHECK20-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 14934 // CHECK20-NEXT: store i8* null, i8** [[TMP11]], align 4 14935 // CHECK20-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 14936 // CHECK20-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* 14937 // CHECK20-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4 14938 // CHECK20-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 14939 // CHECK20-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32* 14940 // CHECK20-NEXT: store i32 [[TMP3]], i32* [[TMP15]], align 4 14941 // CHECK20-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 14942 // CHECK20-NEXT: store i8* null, i8** [[TMP16]], align 4 14943 // CHECK20-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 14944 // CHECK20-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32* 14945 // CHECK20-NEXT: store i32 [[TMP5]], i32* [[TMP18]], align 4 14946 // CHECK20-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 14947 // CHECK20-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32* 14948 // CHECK20-NEXT: store i32 [[TMP5]], i32* [[TMP20]], align 4 14949 // CHECK20-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 14950 // CHECK20-NEXT: store i8* null, i8** [[TMP21]], align 4 14951 // CHECK20-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 14952 // CHECK20-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]** 14953 // CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 4 14954 // CHECK20-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 14955 // CHECK20-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]** 14956 // CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 4 14957 // CHECK20-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 14958 // CHECK20-NEXT: store i8* null, i8** [[TMP26]], align 4 14959 // CHECK20-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 14960 // CHECK20-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 14961 // CHECK20-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.25, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.26, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 14962 // CHECK20-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 14963 // CHECK20-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 14964 // CHECK20: omp_offload.failed: 14965 // CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR3]] 14966 // CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT]] 14967 // CHECK20: omp_offload.cont: 14968 // CHECK20-NEXT: br label [[OMP_IF_END:%.*]] 14969 // CHECK20: omp_if.else: 14970 // CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR3]] 14971 // CHECK20-NEXT: br label [[OMP_IF_END]] 14972 // CHECK20: omp_if.end: 14973 // CHECK20-NEXT: [[TMP31:%.*]] = load i32, i32* [[A]], align 4 14974 // CHECK20-NEXT: ret i32 [[TMP31]] 14975 // 14976 // 14977 // CHECK20-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 14978 // CHECK20-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { 14979 // CHECK20-NEXT: entry: 14980 // CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 14981 // CHECK20-NEXT: [[A:%.*]] = alloca i32, align 4 14982 // CHECK20-NEXT: [[AA:%.*]] = alloca i16, align 2 14983 // CHECK20-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 14984 // CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 14985 // CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 14986 // CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 14987 // CHECK20-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 14988 // CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 14989 // CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 14990 // CHECK20-NEXT: store i32 0, i32* [[A]], align 4 14991 // CHECK20-NEXT: store i16 0, i16* [[AA]], align 2 14992 // CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 14993 // CHECK20-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 14994 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 14995 // CHECK20-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 14996 // CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 14997 // CHECK20-NEXT: store i16 [[TMP2]], i16* [[CONV]], align 2 14998 // CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 14999 // CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 15000 // CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40 15001 // CHECK20-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 15002 // CHECK20: omp_if.then: 15003 // CHECK20-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 15004 // CHECK20-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i32* 15005 // CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP6]], align 4 15006 // CHECK20-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 15007 // CHECK20-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* 15008 // CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4 15009 // CHECK20-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 15010 // CHECK20-NEXT: store i8* null, i8** [[TMP9]], align 4 15011 // CHECK20-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 15012 // CHECK20-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i32* 15013 // CHECK20-NEXT: store i32 [[TMP3]], i32* [[TMP11]], align 4 15014 // CHECK20-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 15015 // CHECK20-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* 15016 // CHECK20-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4 15017 // CHECK20-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 15018 // CHECK20-NEXT: store i8* null, i8** [[TMP14]], align 4 15019 // CHECK20-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 15020 // CHECK20-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]** 15021 // CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 4 15022 // CHECK20-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 15023 // CHECK20-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]** 15024 // CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 4 15025 // CHECK20-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 15026 // CHECK20-NEXT: store i8* null, i8** [[TMP19]], align 4 15027 // CHECK20-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 15028 // CHECK20-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 15029 // CHECK20-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.28, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.29, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 15030 // CHECK20-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 15031 // CHECK20-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 15032 // CHECK20: omp_offload.failed: 15033 // CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]] 15034 // CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT]] 15035 // CHECK20: omp_offload.cont: 15036 // CHECK20-NEXT: br label [[OMP_IF_END:%.*]] 15037 // CHECK20: omp_if.else: 15038 // CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]] 15039 // CHECK20-NEXT: br label [[OMP_IF_END]] 15040 // CHECK20: omp_if.end: 15041 // CHECK20-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4 15042 // CHECK20-NEXT: ret i32 [[TMP24]] 15043 // 15044 // 15045 // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227 15046 // CHECK20-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { 15047 // CHECK20-NEXT: entry: 15048 // CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 15049 // CHECK20-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 15050 // CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 15051 // CHECK20-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 15052 // CHECK20-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 15053 // CHECK20-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 15054 // CHECK20-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 15055 // CHECK20-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 15056 // CHECK20-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 15057 // CHECK20-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 15058 // CHECK20-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 15059 // CHECK20-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 15060 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 15061 // CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 15062 // CHECK20-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 15063 // CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 15064 // CHECK20-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 15065 // CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 15066 // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..22 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]]) 15067 // CHECK20-NEXT: ret void 15068 // 15069 // 15070 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..22 15071 // CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { 15072 // CHECK20-NEXT: entry: 15073 // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 15074 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 15075 // CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 15076 // CHECK20-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 15077 // CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 15078 // CHECK20-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 15079 // CHECK20-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 15080 // CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 15081 // CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 15082 // CHECK20-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 15083 // CHECK20-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 15084 // CHECK20-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 15085 // CHECK20-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 15086 // CHECK20-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 15087 // CHECK20-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 15088 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 15089 // CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 15090 // CHECK20-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 15091 // CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 15092 // CHECK20-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP4]] to double 15093 // CHECK20-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 15094 // CHECK20-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 15095 // CHECK20-NEXT: store double [[ADD]], double* [[A]], align 4 15096 // CHECK20-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 15097 // CHECK20-NEXT: [[TMP5:%.*]] = load double, double* [[A3]], align 4 15098 // CHECK20-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 15099 // CHECK20-NEXT: store double [[INC]], double* [[A3]], align 4 15100 // CHECK20-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 15101 // CHECK20-NEXT: [[TMP6:%.*]] = mul nsw i32 1, [[TMP2]] 15102 // CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP6]] 15103 // CHECK20-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 15104 // CHECK20-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 15105 // CHECK20-NEXT: ret void 15106 // 15107 // 15108 // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209 15109 // CHECK20-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 15110 // CHECK20-NEXT: entry: 15111 // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 15112 // CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 15113 // CHECK20-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 15114 // CHECK20-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 15115 // CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 15116 // CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 15117 // CHECK20-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 15118 // CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 15119 // CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 15120 // CHECK20-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 15121 // CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 15122 // CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 15123 // CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 15124 // CHECK20-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 15125 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 15126 // CHECK20-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 15127 // CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 15128 // CHECK20-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 15129 // CHECK20-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 15130 // CHECK20-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 15131 // CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 15132 // CHECK20-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 4 15133 // CHECK20-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* 15134 // CHECK20-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 15135 // CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 15136 // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..24 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) 15137 // CHECK20-NEXT: ret void 15138 // 15139 // 15140 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..24 15141 // CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 15142 // CHECK20-NEXT: entry: 15143 // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 15144 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 15145 // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 15146 // CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 15147 // CHECK20-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 15148 // CHECK20-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 15149 // CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 15150 // CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 15151 // CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 15152 // CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 15153 // CHECK20-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 15154 // CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 15155 // CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 15156 // CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 15157 // CHECK20-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 15158 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 15159 // CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 15160 // CHECK20-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 15161 // CHECK20-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 15162 // CHECK20-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 15163 // CHECK20-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 15164 // CHECK20-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 15165 // CHECK20-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 4 15166 // CHECK20-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 4 15167 // CHECK20-NEXT: [[CONV5:%.*]] = sext i8 [[TMP3]] to i32 15168 // CHECK20-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 15169 // CHECK20-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i8 15170 // CHECK20-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 4 15171 // CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 15172 // CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 15173 // CHECK20-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP4]], 1 15174 // CHECK20-NEXT: store i32 [[ADD8]], i32* [[ARRAYIDX]], align 4 15175 // CHECK20-NEXT: ret void 15176 // 15177 // 15178 // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192 15179 // CHECK20-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 15180 // CHECK20-NEXT: entry: 15181 // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 15182 // CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 15183 // CHECK20-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 15184 // CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 15185 // CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 15186 // CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 15187 // CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 15188 // CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 15189 // CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 15190 // CHECK20-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 15191 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 15192 // CHECK20-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 15193 // CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 15194 // CHECK20-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 15195 // CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 15196 // CHECK20-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 15197 // CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 15198 // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..27 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) 15199 // CHECK20-NEXT: ret void 15200 // 15201 // 15202 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..27 15203 // CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 15204 // CHECK20-NEXT: entry: 15205 // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 15206 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 15207 // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 15208 // CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 15209 // CHECK20-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 15210 // CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 15211 // CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 15212 // CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 15213 // CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 15214 // CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 15215 // CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 15216 // CHECK20-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 15217 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 15218 // CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 15219 // CHECK20-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 15220 // CHECK20-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 15221 // CHECK20-NEXT: [[CONV1:%.*]] = sext i16 [[TMP2]] to i32 15222 // CHECK20-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 15223 // CHECK20-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 15224 // CHECK20-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 4 15225 // CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 15226 // CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 15227 // CHECK20-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1 15228 // CHECK20-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4 15229 // CHECK20-NEXT: ret void 15230 // 15231 // 15232 // CHECK20-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 15233 // CHECK20-SAME: () #[[ATTR4]] { 15234 // CHECK20-NEXT: entry: 15235 // CHECK20-NEXT: call void @__tgt_register_requires(i64 1) 15236 // CHECK20-NEXT: ret void 15237 // 15238 // 15239 // CHECK21-LABEL: define {{[^@]+}}@_Z3fooi 15240 // CHECK21-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { 15241 // CHECK21-NEXT: entry: 15242 // CHECK21-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 15243 // CHECK21-NEXT: [[A:%.*]] = alloca i32, align 4 15244 // CHECK21-NEXT: [[AA:%.*]] = alloca i16, align 2 15245 // CHECK21-NEXT: [[B:%.*]] = alloca [10 x float], align 4 15246 // CHECK21-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 15247 // CHECK21-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 15248 // CHECK21-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 15249 // CHECK21-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 15250 // CHECK21-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 15251 // CHECK21-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 15252 // CHECK21-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 15253 // CHECK21-NEXT: [[NN:%.*]] = alloca i32, align 4 15254 // CHECK21-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 15255 // CHECK21-NEXT: store i32 0, i32* [[A]], align 4 15256 // CHECK21-NEXT: store i16 0, i16* [[AA]], align 2 15257 // CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 15258 // CHECK21-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 15259 // CHECK21-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() 15260 // CHECK21-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 15261 // CHECK21-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4 15262 // CHECK21-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 15263 // CHECK21-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 15264 // CHECK21-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64 15265 // CHECK21-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]] 15266 // CHECK21-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8 15267 // CHECK21-NEXT: store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8 15268 // CHECK21-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 15269 // CHECK21-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_]], align 4 15270 // CHECK21-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 15271 // CHECK21-NEXT: store i32 [[TMP7]], i32* [[DOTCAPTURE_EXPR_2]], align 4 15272 // CHECK21-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 15273 // CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 15274 // CHECK21-NEXT: store i32 [[ADD]], i32* [[A]], align 4 15275 // CHECK21-NEXT: [[TMP9:%.*]] = load i16, i16* [[AA]], align 2 15276 // CHECK21-NEXT: [[CONV:%.*]] = sext i16 [[TMP9]] to i32 15277 // CHECK21-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1 15278 // CHECK21-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 15279 // CHECK21-NEXT: store i16 [[CONV4]], i16* [[AA]], align 2 15280 // CHECK21-NEXT: [[TMP10:%.*]] = load i32, i32* [[A]], align 4 15281 // CHECK21-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP10]], 1 15282 // CHECK21-NEXT: store i32 [[ADD5]], i32* [[A]], align 4 15283 // CHECK21-NEXT: [[TMP11:%.*]] = load i16, i16* [[AA]], align 2 15284 // CHECK21-NEXT: [[CONV6:%.*]] = sext i16 [[TMP11]] to i32 15285 // CHECK21-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 15286 // CHECK21-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i16 15287 // CHECK21-NEXT: store i16 [[CONV8]], i16* [[AA]], align 2 15288 // CHECK21-NEXT: [[TMP12:%.*]] = load i32, i32* [[A]], align 4 15289 // CHECK21-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP12]], 1 15290 // CHECK21-NEXT: store i32 [[ADD9]], i32* [[A]], align 4 15291 // CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2 15292 // CHECK21-NEXT: [[TMP13:%.*]] = load float, float* [[ARRAYIDX]], align 4 15293 // CHECK21-NEXT: [[CONV10:%.*]] = fpext float [[TMP13]] to double 15294 // CHECK21-NEXT: [[ADD11:%.*]] = fadd double [[CONV10]], 1.000000e+00 15295 // CHECK21-NEXT: [[CONV12:%.*]] = fptrunc double [[ADD11]] to float 15296 // CHECK21-NEXT: store float [[CONV12]], float* [[ARRAYIDX]], align 4 15297 // CHECK21-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3 15298 // CHECK21-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX13]], align 4 15299 // CHECK21-NEXT: [[CONV14:%.*]] = fpext float [[TMP14]] to double 15300 // CHECK21-NEXT: [[ADD15:%.*]] = fadd double [[CONV14]], 1.000000e+00 15301 // CHECK21-NEXT: [[CONV16:%.*]] = fptrunc double [[ADD15]] to float 15302 // CHECK21-NEXT: store float [[CONV16]], float* [[ARRAYIDX13]], align 4 15303 // CHECK21-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1 15304 // CHECK21-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX17]], i64 0, i64 2 15305 // CHECK21-NEXT: [[TMP15:%.*]] = load double, double* [[ARRAYIDX18]], align 8 15306 // CHECK21-NEXT: [[ADD19:%.*]] = fadd double [[TMP15]], 1.000000e+00 15307 // CHECK21-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8 15308 // CHECK21-NEXT: [[TMP16:%.*]] = mul nsw i64 1, [[TMP4]] 15309 // CHECK21-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP16]] 15310 // CHECK21-NEXT: [[ARRAYIDX21:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX20]], i64 3 15311 // CHECK21-NEXT: [[TMP17:%.*]] = load double, double* [[ARRAYIDX21]], align 8 15312 // CHECK21-NEXT: [[ADD22:%.*]] = fadd double [[TMP17]], 1.000000e+00 15313 // CHECK21-NEXT: store double [[ADD22]], double* [[ARRAYIDX21]], align 8 15314 // CHECK21-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 15315 // CHECK21-NEXT: [[TMP18:%.*]] = load i64, i64* [[X]], align 8 15316 // CHECK21-NEXT: [[ADD23:%.*]] = add nsw i64 [[TMP18]], 1 15317 // CHECK21-NEXT: store i64 [[ADD23]], i64* [[X]], align 8 15318 // CHECK21-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 15319 // CHECK21-NEXT: [[TMP19:%.*]] = load i8, i8* [[Y]], align 8 15320 // CHECK21-NEXT: [[CONV24:%.*]] = sext i8 [[TMP19]] to i32 15321 // CHECK21-NEXT: [[ADD25:%.*]] = add nsw i32 [[CONV24]], 1 15322 // CHECK21-NEXT: [[CONV26:%.*]] = trunc i32 [[ADD25]] to i8 15323 // CHECK21-NEXT: store i8 [[CONV26]], i8* [[Y]], align 8 15324 // CHECK21-NEXT: store i32 0, i32* [[NN]], align 4 15325 // CHECK21-NEXT: [[TMP20:%.*]] = load i32, i32* [[A]], align 4 15326 // CHECK21-NEXT: [[TMP21:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 15327 // CHECK21-NEXT: call void @llvm.stackrestore(i8* [[TMP21]]) 15328 // CHECK21-NEXT: ret i32 [[TMP20]] 15329 // 15330 // 15331 // CHECK21-LABEL: define {{[^@]+}}@_Z6bazzzziPi 15332 // CHECK21-SAME: (i32 signext [[N:%.*]], i32* [[F:%.*]]) #[[ATTR0]] { 15333 // CHECK21-NEXT: entry: 15334 // CHECK21-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 15335 // CHECK21-NEXT: [[F_ADDR:%.*]] = alloca i32*, align 8 15336 // CHECK21-NEXT: [[F1:%.*]] = alloca i32*, align 8 15337 // CHECK21-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 15338 // CHECK21-NEXT: store i32* [[F]], i32** [[F_ADDR]], align 8 15339 // CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 15340 // CHECK21-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 15341 // CHECK21-NEXT: ret void 15342 // 15343 // 15344 // CHECK21-LABEL: define {{[^@]+}}@_Z3bari 15345 // CHECK21-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { 15346 // CHECK21-NEXT: entry: 15347 // CHECK21-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 15348 // CHECK21-NEXT: [[A:%.*]] = alloca i32, align 4 15349 // CHECK21-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 15350 // CHECK21-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 15351 // CHECK21-NEXT: store i32 0, i32* [[A]], align 4 15352 // CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 15353 // CHECK21-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]]) 15354 // CHECK21-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 15355 // CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 15356 // CHECK21-NEXT: store i32 [[ADD]], i32* [[A]], align 4 15357 // CHECK21-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 15358 // CHECK21-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]]) 15359 // CHECK21-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 15360 // CHECK21-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 15361 // CHECK21-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 15362 // CHECK21-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 15363 // CHECK21-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]]) 15364 // CHECK21-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 15365 // CHECK21-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 15366 // CHECK21-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 15367 // CHECK21-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 15368 // CHECK21-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]]) 15369 // CHECK21-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 15370 // CHECK21-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] 15371 // CHECK21-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 15372 // CHECK21-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 15373 // CHECK21-NEXT: ret i32 [[TMP8]] 15374 // 15375 // 15376 // CHECK21-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 15377 // CHECK21-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { 15378 // CHECK21-NEXT: entry: 15379 // CHECK21-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 15380 // CHECK21-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 15381 // CHECK21-NEXT: [[B:%.*]] = alloca i32, align 4 15382 // CHECK21-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 15383 // CHECK21-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 15384 // CHECK21-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 15385 // CHECK21-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 15386 // CHECK21-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 15387 // CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 15388 // CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 15389 // CHECK21-NEXT: store i32 [[ADD]], i32* [[B]], align 4 15390 // CHECK21-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 15391 // CHECK21-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 15392 // CHECK21-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() 15393 // CHECK21-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 15394 // CHECK21-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] 15395 // CHECK21-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 15396 // CHECK21-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 15397 // CHECK21-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 15398 // CHECK21-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP5]] to double 15399 // CHECK21-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 15400 // CHECK21-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 15401 // CHECK21-NEXT: store double [[ADD2]], double* [[A]], align 8 15402 // CHECK21-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 15403 // CHECK21-NEXT: [[TMP6:%.*]] = load double, double* [[A3]], align 8 15404 // CHECK21-NEXT: [[INC:%.*]] = fadd double [[TMP6]], 1.000000e+00 15405 // CHECK21-NEXT: store double [[INC]], double* [[A3]], align 8 15406 // CHECK21-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 15407 // CHECK21-NEXT: [[TMP7:%.*]] = mul nsw i64 1, [[TMP2]] 15408 // CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP7]] 15409 // CHECK21-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 15410 // CHECK21-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 15411 // CHECK21-NEXT: [[TMP8:%.*]] = mul nsw i64 1, [[TMP2]] 15412 // CHECK21-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP8]] 15413 // CHECK21-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i64 1 15414 // CHECK21-NEXT: [[TMP9:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2 15415 // CHECK21-NEXT: [[CONV8:%.*]] = sext i16 [[TMP9]] to i32 15416 // CHECK21-NEXT: [[TMP10:%.*]] = load i32, i32* [[B]], align 4 15417 // CHECK21-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP10]] 15418 // CHECK21-NEXT: [[TMP11:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 15419 // CHECK21-NEXT: call void @llvm.stackrestore(i8* [[TMP11]]) 15420 // CHECK21-NEXT: ret i32 [[ADD9]] 15421 // 15422 // 15423 // CHECK21-LABEL: define {{[^@]+}}@_ZL7fstatici 15424 // CHECK21-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { 15425 // CHECK21-NEXT: entry: 15426 // CHECK21-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 15427 // CHECK21-NEXT: [[A:%.*]] = alloca i32, align 4 15428 // CHECK21-NEXT: [[AA:%.*]] = alloca i16, align 2 15429 // CHECK21-NEXT: [[AAA:%.*]] = alloca i8, align 1 15430 // CHECK21-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 15431 // CHECK21-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 15432 // CHECK21-NEXT: store i32 0, i32* [[A]], align 4 15433 // CHECK21-NEXT: store i16 0, i16* [[AA]], align 2 15434 // CHECK21-NEXT: store i8 0, i8* [[AAA]], align 1 15435 // CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 15436 // CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 15437 // CHECK21-NEXT: store i32 [[ADD]], i32* [[A]], align 4 15438 // CHECK21-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 15439 // CHECK21-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 15440 // CHECK21-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 15441 // CHECK21-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 15442 // CHECK21-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 15443 // CHECK21-NEXT: [[TMP2:%.*]] = load i8, i8* [[AAA]], align 1 15444 // CHECK21-NEXT: [[CONV3:%.*]] = sext i8 [[TMP2]] to i32 15445 // CHECK21-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 15446 // CHECK21-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 15447 // CHECK21-NEXT: store i8 [[CONV5]], i8* [[AAA]], align 1 15448 // CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 15449 // CHECK21-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 15450 // CHECK21-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP3]], 1 15451 // CHECK21-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 15452 // CHECK21-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 15453 // CHECK21-NEXT: ret i32 [[TMP4]] 15454 // 15455 // 15456 // CHECK21-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 15457 // CHECK21-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { 15458 // CHECK21-NEXT: entry: 15459 // CHECK21-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 15460 // CHECK21-NEXT: [[A:%.*]] = alloca i32, align 4 15461 // CHECK21-NEXT: [[AA:%.*]] = alloca i16, align 2 15462 // CHECK21-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 15463 // CHECK21-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 15464 // CHECK21-NEXT: store i32 0, i32* [[A]], align 4 15465 // CHECK21-NEXT: store i16 0, i16* [[AA]], align 2 15466 // CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 15467 // CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 15468 // CHECK21-NEXT: store i32 [[ADD]], i32* [[A]], align 4 15469 // CHECK21-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 15470 // CHECK21-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 15471 // CHECK21-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 15472 // CHECK21-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 15473 // CHECK21-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 15474 // CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 15475 // CHECK21-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 15476 // CHECK21-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP2]], 1 15477 // CHECK21-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 15478 // CHECK21-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 15479 // CHECK21-NEXT: ret i32 [[TMP3]] 15480 // 15481 // 15482 // CHECK22-LABEL: define {{[^@]+}}@_Z3fooi 15483 // CHECK22-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { 15484 // CHECK22-NEXT: entry: 15485 // CHECK22-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 15486 // CHECK22-NEXT: [[A:%.*]] = alloca i32, align 4 15487 // CHECK22-NEXT: [[AA:%.*]] = alloca i16, align 2 15488 // CHECK22-NEXT: [[B:%.*]] = alloca [10 x float], align 4 15489 // CHECK22-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 15490 // CHECK22-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 15491 // CHECK22-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 15492 // CHECK22-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 15493 // CHECK22-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 15494 // CHECK22-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 15495 // CHECK22-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 15496 // CHECK22-NEXT: [[NN:%.*]] = alloca i32, align 4 15497 // CHECK22-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 15498 // CHECK22-NEXT: store i32 0, i32* [[A]], align 4 15499 // CHECK22-NEXT: store i16 0, i16* [[AA]], align 2 15500 // CHECK22-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 15501 // CHECK22-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 15502 // CHECK22-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() 15503 // CHECK22-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 15504 // CHECK22-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4 15505 // CHECK22-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 15506 // CHECK22-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 15507 // CHECK22-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64 15508 // CHECK22-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]] 15509 // CHECK22-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8 15510 // CHECK22-NEXT: store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8 15511 // CHECK22-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 15512 // CHECK22-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_]], align 4 15513 // CHECK22-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 15514 // CHECK22-NEXT: store i32 [[TMP7]], i32* [[DOTCAPTURE_EXPR_2]], align 4 15515 // CHECK22-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 15516 // CHECK22-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 15517 // CHECK22-NEXT: store i32 [[ADD]], i32* [[A]], align 4 15518 // CHECK22-NEXT: [[TMP9:%.*]] = load i16, i16* [[AA]], align 2 15519 // CHECK22-NEXT: [[CONV:%.*]] = sext i16 [[TMP9]] to i32 15520 // CHECK22-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1 15521 // CHECK22-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 15522 // CHECK22-NEXT: store i16 [[CONV4]], i16* [[AA]], align 2 15523 // CHECK22-NEXT: [[TMP10:%.*]] = load i32, i32* [[A]], align 4 15524 // CHECK22-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP10]], 1 15525 // CHECK22-NEXT: store i32 [[ADD5]], i32* [[A]], align 4 15526 // CHECK22-NEXT: [[TMP11:%.*]] = load i16, i16* [[AA]], align 2 15527 // CHECK22-NEXT: [[CONV6:%.*]] = sext i16 [[TMP11]] to i32 15528 // CHECK22-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 15529 // CHECK22-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i16 15530 // CHECK22-NEXT: store i16 [[CONV8]], i16* [[AA]], align 2 15531 // CHECK22-NEXT: [[TMP12:%.*]] = load i32, i32* [[A]], align 4 15532 // CHECK22-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP12]], 1 15533 // CHECK22-NEXT: store i32 [[ADD9]], i32* [[A]], align 4 15534 // CHECK22-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2 15535 // CHECK22-NEXT: [[TMP13:%.*]] = load float, float* [[ARRAYIDX]], align 4 15536 // CHECK22-NEXT: [[CONV10:%.*]] = fpext float [[TMP13]] to double 15537 // CHECK22-NEXT: [[ADD11:%.*]] = fadd double [[CONV10]], 1.000000e+00 15538 // CHECK22-NEXT: [[CONV12:%.*]] = fptrunc double [[ADD11]] to float 15539 // CHECK22-NEXT: store float [[CONV12]], float* [[ARRAYIDX]], align 4 15540 // CHECK22-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3 15541 // CHECK22-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX13]], align 4 15542 // CHECK22-NEXT: [[CONV14:%.*]] = fpext float [[TMP14]] to double 15543 // CHECK22-NEXT: [[ADD15:%.*]] = fadd double [[CONV14]], 1.000000e+00 15544 // CHECK22-NEXT: [[CONV16:%.*]] = fptrunc double [[ADD15]] to float 15545 // CHECK22-NEXT: store float [[CONV16]], float* [[ARRAYIDX13]], align 4 15546 // CHECK22-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1 15547 // CHECK22-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX17]], i64 0, i64 2 15548 // CHECK22-NEXT: [[TMP15:%.*]] = load double, double* [[ARRAYIDX18]], align 8 15549 // CHECK22-NEXT: [[ADD19:%.*]] = fadd double [[TMP15]], 1.000000e+00 15550 // CHECK22-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8 15551 // CHECK22-NEXT: [[TMP16:%.*]] = mul nsw i64 1, [[TMP4]] 15552 // CHECK22-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP16]] 15553 // CHECK22-NEXT: [[ARRAYIDX21:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX20]], i64 3 15554 // CHECK22-NEXT: [[TMP17:%.*]] = load double, double* [[ARRAYIDX21]], align 8 15555 // CHECK22-NEXT: [[ADD22:%.*]] = fadd double [[TMP17]], 1.000000e+00 15556 // CHECK22-NEXT: store double [[ADD22]], double* [[ARRAYIDX21]], align 8 15557 // CHECK22-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 15558 // CHECK22-NEXT: [[TMP18:%.*]] = load i64, i64* [[X]], align 8 15559 // CHECK22-NEXT: [[ADD23:%.*]] = add nsw i64 [[TMP18]], 1 15560 // CHECK22-NEXT: store i64 [[ADD23]], i64* [[X]], align 8 15561 // CHECK22-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 15562 // CHECK22-NEXT: [[TMP19:%.*]] = load i8, i8* [[Y]], align 8 15563 // CHECK22-NEXT: [[CONV24:%.*]] = sext i8 [[TMP19]] to i32 15564 // CHECK22-NEXT: [[ADD25:%.*]] = add nsw i32 [[CONV24]], 1 15565 // CHECK22-NEXT: [[CONV26:%.*]] = trunc i32 [[ADD25]] to i8 15566 // CHECK22-NEXT: store i8 [[CONV26]], i8* [[Y]], align 8 15567 // CHECK22-NEXT: store i32 0, i32* [[NN]], align 4 15568 // CHECK22-NEXT: [[TMP20:%.*]] = load i32, i32* [[A]], align 4 15569 // CHECK22-NEXT: [[TMP21:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 15570 // CHECK22-NEXT: call void @llvm.stackrestore(i8* [[TMP21]]) 15571 // CHECK22-NEXT: ret i32 [[TMP20]] 15572 // 15573 // 15574 // CHECK22-LABEL: define {{[^@]+}}@_Z6bazzzziPi 15575 // CHECK22-SAME: (i32 signext [[N:%.*]], i32* [[F:%.*]]) #[[ATTR0]] { 15576 // CHECK22-NEXT: entry: 15577 // CHECK22-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 15578 // CHECK22-NEXT: [[F_ADDR:%.*]] = alloca i32*, align 8 15579 // CHECK22-NEXT: [[F1:%.*]] = alloca i32*, align 8 15580 // CHECK22-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 15581 // CHECK22-NEXT: store i32* [[F]], i32** [[F_ADDR]], align 8 15582 // CHECK22-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 15583 // CHECK22-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 15584 // CHECK22-NEXT: ret void 15585 // 15586 // 15587 // CHECK22-LABEL: define {{[^@]+}}@_Z3bari 15588 // CHECK22-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { 15589 // CHECK22-NEXT: entry: 15590 // CHECK22-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 15591 // CHECK22-NEXT: [[A:%.*]] = alloca i32, align 4 15592 // CHECK22-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 15593 // CHECK22-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 15594 // CHECK22-NEXT: store i32 0, i32* [[A]], align 4 15595 // CHECK22-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 15596 // CHECK22-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]]) 15597 // CHECK22-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 15598 // CHECK22-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 15599 // CHECK22-NEXT: store i32 [[ADD]], i32* [[A]], align 4 15600 // CHECK22-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 15601 // CHECK22-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]]) 15602 // CHECK22-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 15603 // CHECK22-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 15604 // CHECK22-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 15605 // CHECK22-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 15606 // CHECK22-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]]) 15607 // CHECK22-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 15608 // CHECK22-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 15609 // CHECK22-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 15610 // CHECK22-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 15611 // CHECK22-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]]) 15612 // CHECK22-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 15613 // CHECK22-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] 15614 // CHECK22-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 15615 // CHECK22-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 15616 // CHECK22-NEXT: ret i32 [[TMP8]] 15617 // 15618 // 15619 // CHECK22-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 15620 // CHECK22-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { 15621 // CHECK22-NEXT: entry: 15622 // CHECK22-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 15623 // CHECK22-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 15624 // CHECK22-NEXT: [[B:%.*]] = alloca i32, align 4 15625 // CHECK22-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 15626 // CHECK22-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 15627 // CHECK22-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 15628 // CHECK22-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 15629 // CHECK22-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 15630 // CHECK22-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 15631 // CHECK22-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 15632 // CHECK22-NEXT: store i32 [[ADD]], i32* [[B]], align 4 15633 // CHECK22-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 15634 // CHECK22-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 15635 // CHECK22-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() 15636 // CHECK22-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 15637 // CHECK22-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] 15638 // CHECK22-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 15639 // CHECK22-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 15640 // CHECK22-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 15641 // CHECK22-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP5]] to double 15642 // CHECK22-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 15643 // CHECK22-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 15644 // CHECK22-NEXT: store double [[ADD2]], double* [[A]], align 8 15645 // CHECK22-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 15646 // CHECK22-NEXT: [[TMP6:%.*]] = load double, double* [[A3]], align 8 15647 // CHECK22-NEXT: [[INC:%.*]] = fadd double [[TMP6]], 1.000000e+00 15648 // CHECK22-NEXT: store double [[INC]], double* [[A3]], align 8 15649 // CHECK22-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 15650 // CHECK22-NEXT: [[TMP7:%.*]] = mul nsw i64 1, [[TMP2]] 15651 // CHECK22-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP7]] 15652 // CHECK22-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 15653 // CHECK22-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 15654 // CHECK22-NEXT: [[TMP8:%.*]] = mul nsw i64 1, [[TMP2]] 15655 // CHECK22-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP8]] 15656 // CHECK22-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i64 1 15657 // CHECK22-NEXT: [[TMP9:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2 15658 // CHECK22-NEXT: [[CONV8:%.*]] = sext i16 [[TMP9]] to i32 15659 // CHECK22-NEXT: [[TMP10:%.*]] = load i32, i32* [[B]], align 4 15660 // CHECK22-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP10]] 15661 // CHECK22-NEXT: [[TMP11:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 15662 // CHECK22-NEXT: call void @llvm.stackrestore(i8* [[TMP11]]) 15663 // CHECK22-NEXT: ret i32 [[ADD9]] 15664 // 15665 // 15666 // CHECK22-LABEL: define {{[^@]+}}@_ZL7fstatici 15667 // CHECK22-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { 15668 // CHECK22-NEXT: entry: 15669 // CHECK22-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 15670 // CHECK22-NEXT: [[A:%.*]] = alloca i32, align 4 15671 // CHECK22-NEXT: [[AA:%.*]] = alloca i16, align 2 15672 // CHECK22-NEXT: [[AAA:%.*]] = alloca i8, align 1 15673 // CHECK22-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 15674 // CHECK22-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 15675 // CHECK22-NEXT: store i32 0, i32* [[A]], align 4 15676 // CHECK22-NEXT: store i16 0, i16* [[AA]], align 2 15677 // CHECK22-NEXT: store i8 0, i8* [[AAA]], align 1 15678 // CHECK22-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 15679 // CHECK22-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 15680 // CHECK22-NEXT: store i32 [[ADD]], i32* [[A]], align 4 15681 // CHECK22-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 15682 // CHECK22-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 15683 // CHECK22-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 15684 // CHECK22-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 15685 // CHECK22-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 15686 // CHECK22-NEXT: [[TMP2:%.*]] = load i8, i8* [[AAA]], align 1 15687 // CHECK22-NEXT: [[CONV3:%.*]] = sext i8 [[TMP2]] to i32 15688 // CHECK22-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 15689 // CHECK22-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 15690 // CHECK22-NEXT: store i8 [[CONV5]], i8* [[AAA]], align 1 15691 // CHECK22-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 15692 // CHECK22-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 15693 // CHECK22-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP3]], 1 15694 // CHECK22-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 15695 // CHECK22-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 15696 // CHECK22-NEXT: ret i32 [[TMP4]] 15697 // 15698 // 15699 // CHECK22-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 15700 // CHECK22-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { 15701 // CHECK22-NEXT: entry: 15702 // CHECK22-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 15703 // CHECK22-NEXT: [[A:%.*]] = alloca i32, align 4 15704 // CHECK22-NEXT: [[AA:%.*]] = alloca i16, align 2 15705 // CHECK22-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 15706 // CHECK22-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 15707 // CHECK22-NEXT: store i32 0, i32* [[A]], align 4 15708 // CHECK22-NEXT: store i16 0, i16* [[AA]], align 2 15709 // CHECK22-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 15710 // CHECK22-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 15711 // CHECK22-NEXT: store i32 [[ADD]], i32* [[A]], align 4 15712 // CHECK22-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 15713 // CHECK22-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 15714 // CHECK22-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 15715 // CHECK22-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 15716 // CHECK22-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 15717 // CHECK22-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 15718 // CHECK22-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 15719 // CHECK22-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP2]], 1 15720 // CHECK22-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 15721 // CHECK22-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 15722 // CHECK22-NEXT: ret i32 [[TMP3]] 15723 // 15724 // 15725 // CHECK23-LABEL: define {{[^@]+}}@_Z3fooi 15726 // CHECK23-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { 15727 // CHECK23-NEXT: entry: 15728 // CHECK23-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 15729 // CHECK23-NEXT: [[A:%.*]] = alloca i32, align 4 15730 // CHECK23-NEXT: [[AA:%.*]] = alloca i16, align 2 15731 // CHECK23-NEXT: [[B:%.*]] = alloca [10 x float], align 4 15732 // CHECK23-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 15733 // CHECK23-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 15734 // CHECK23-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 15735 // CHECK23-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 15736 // CHECK23-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 15737 // CHECK23-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 15738 // CHECK23-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 15739 // CHECK23-NEXT: [[NN:%.*]] = alloca i32, align 4 15740 // CHECK23-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 15741 // CHECK23-NEXT: store i32 0, i32* [[A]], align 4 15742 // CHECK23-NEXT: store i16 0, i16* [[AA]], align 2 15743 // CHECK23-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 15744 // CHECK23-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() 15745 // CHECK23-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 15746 // CHECK23-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4 15747 // CHECK23-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 15748 // CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 15749 // CHECK23-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]] 15750 // CHECK23-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8 15751 // CHECK23-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4 15752 // CHECK23-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 15753 // CHECK23-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 15754 // CHECK23-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 15755 // CHECK23-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_2]], align 4 15756 // CHECK23-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 15757 // CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], 1 15758 // CHECK23-NEXT: store i32 [[ADD]], i32* [[A]], align 4 15759 // CHECK23-NEXT: [[TMP7:%.*]] = load i16, i16* [[AA]], align 2 15760 // CHECK23-NEXT: [[CONV:%.*]] = sext i16 [[TMP7]] to i32 15761 // CHECK23-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1 15762 // CHECK23-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 15763 // CHECK23-NEXT: store i16 [[CONV4]], i16* [[AA]], align 2 15764 // CHECK23-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 15765 // CHECK23-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP8]], 1 15766 // CHECK23-NEXT: store i32 [[ADD5]], i32* [[A]], align 4 15767 // CHECK23-NEXT: [[TMP9:%.*]] = load i16, i16* [[AA]], align 2 15768 // CHECK23-NEXT: [[CONV6:%.*]] = sext i16 [[TMP9]] to i32 15769 // CHECK23-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 15770 // CHECK23-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i16 15771 // CHECK23-NEXT: store i16 [[CONV8]], i16* [[AA]], align 2 15772 // CHECK23-NEXT: [[TMP10:%.*]] = load i32, i32* [[A]], align 4 15773 // CHECK23-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP10]], 1 15774 // CHECK23-NEXT: store i32 [[ADD9]], i32* [[A]], align 4 15775 // CHECK23-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2 15776 // CHECK23-NEXT: [[TMP11:%.*]] = load float, float* [[ARRAYIDX]], align 4 15777 // CHECK23-NEXT: [[CONV10:%.*]] = fpext float [[TMP11]] to double 15778 // CHECK23-NEXT: [[ADD11:%.*]] = fadd double [[CONV10]], 1.000000e+00 15779 // CHECK23-NEXT: [[CONV12:%.*]] = fptrunc double [[ADD11]] to float 15780 // CHECK23-NEXT: store float [[CONV12]], float* [[ARRAYIDX]], align 4 15781 // CHECK23-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3 15782 // CHECK23-NEXT: [[TMP12:%.*]] = load float, float* [[ARRAYIDX13]], align 4 15783 // CHECK23-NEXT: [[CONV14:%.*]] = fpext float [[TMP12]] to double 15784 // CHECK23-NEXT: [[ADD15:%.*]] = fadd double [[CONV14]], 1.000000e+00 15785 // CHECK23-NEXT: [[CONV16:%.*]] = fptrunc double [[ADD15]] to float 15786 // CHECK23-NEXT: store float [[CONV16]], float* [[ARRAYIDX13]], align 4 15787 // CHECK23-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1 15788 // CHECK23-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX17]], i32 0, i32 2 15789 // CHECK23-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX18]], align 8 15790 // CHECK23-NEXT: [[ADD19:%.*]] = fadd double [[TMP13]], 1.000000e+00 15791 // CHECK23-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8 15792 // CHECK23-NEXT: [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]] 15793 // CHECK23-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP14]] 15794 // CHECK23-NEXT: [[ARRAYIDX21:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX20]], i32 3 15795 // CHECK23-NEXT: [[TMP15:%.*]] = load double, double* [[ARRAYIDX21]], align 8 15796 // CHECK23-NEXT: [[ADD22:%.*]] = fadd double [[TMP15]], 1.000000e+00 15797 // CHECK23-NEXT: store double [[ADD22]], double* [[ARRAYIDX21]], align 8 15798 // CHECK23-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 15799 // CHECK23-NEXT: [[TMP16:%.*]] = load i64, i64* [[X]], align 4 15800 // CHECK23-NEXT: [[ADD23:%.*]] = add nsw i64 [[TMP16]], 1 15801 // CHECK23-NEXT: store i64 [[ADD23]], i64* [[X]], align 4 15802 // CHECK23-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 15803 // CHECK23-NEXT: [[TMP17:%.*]] = load i8, i8* [[Y]], align 4 15804 // CHECK23-NEXT: [[CONV24:%.*]] = sext i8 [[TMP17]] to i32 15805 // CHECK23-NEXT: [[ADD25:%.*]] = add nsw i32 [[CONV24]], 1 15806 // CHECK23-NEXT: [[CONV26:%.*]] = trunc i32 [[ADD25]] to i8 15807 // CHECK23-NEXT: store i8 [[CONV26]], i8* [[Y]], align 4 15808 // CHECK23-NEXT: store i32 0, i32* [[NN]], align 4 15809 // CHECK23-NEXT: [[TMP18:%.*]] = load i32, i32* [[A]], align 4 15810 // CHECK23-NEXT: [[TMP19:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 15811 // CHECK23-NEXT: call void @llvm.stackrestore(i8* [[TMP19]]) 15812 // CHECK23-NEXT: ret i32 [[TMP18]] 15813 // 15814 // 15815 // CHECK23-LABEL: define {{[^@]+}}@_Z6bazzzziPi 15816 // CHECK23-SAME: (i32 [[N:%.*]], i32* [[F:%.*]]) #[[ATTR0]] { 15817 // CHECK23-NEXT: entry: 15818 // CHECK23-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 15819 // CHECK23-NEXT: [[F_ADDR:%.*]] = alloca i32*, align 4 15820 // CHECK23-NEXT: [[F1:%.*]] = alloca i32*, align 4 15821 // CHECK23-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 15822 // CHECK23-NEXT: store i32* [[F]], i32** [[F_ADDR]], align 4 15823 // CHECK23-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 15824 // CHECK23-NEXT: ret void 15825 // 15826 // 15827 // CHECK23-LABEL: define {{[^@]+}}@_Z3bari 15828 // CHECK23-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { 15829 // CHECK23-NEXT: entry: 15830 // CHECK23-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 15831 // CHECK23-NEXT: [[A:%.*]] = alloca i32, align 4 15832 // CHECK23-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 15833 // CHECK23-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 15834 // CHECK23-NEXT: store i32 0, i32* [[A]], align 4 15835 // CHECK23-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 15836 // CHECK23-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]]) 15837 // CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 15838 // CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 15839 // CHECK23-NEXT: store i32 [[ADD]], i32* [[A]], align 4 15840 // CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 15841 // CHECK23-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]]) 15842 // CHECK23-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 15843 // CHECK23-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 15844 // CHECK23-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 15845 // CHECK23-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 15846 // CHECK23-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]]) 15847 // CHECK23-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 15848 // CHECK23-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 15849 // CHECK23-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 15850 // CHECK23-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 15851 // CHECK23-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]]) 15852 // CHECK23-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 15853 // CHECK23-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] 15854 // CHECK23-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 15855 // CHECK23-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 15856 // CHECK23-NEXT: ret i32 [[TMP8]] 15857 // 15858 // 15859 // CHECK23-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 15860 // CHECK23-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { 15861 // CHECK23-NEXT: entry: 15862 // CHECK23-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 15863 // CHECK23-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 15864 // CHECK23-NEXT: [[B:%.*]] = alloca i32, align 4 15865 // CHECK23-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 15866 // CHECK23-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 15867 // CHECK23-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 15868 // CHECK23-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 15869 // CHECK23-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 15870 // CHECK23-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 15871 // CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 15872 // CHECK23-NEXT: store i32 [[ADD]], i32* [[B]], align 4 15873 // CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 15874 // CHECK23-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() 15875 // CHECK23-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 15876 // CHECK23-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] 15877 // CHECK23-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 15878 // CHECK23-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 15879 // CHECK23-NEXT: [[TMP4:%.*]] = load i32, i32* [[B]], align 4 15880 // CHECK23-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP4]] to double 15881 // CHECK23-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 15882 // CHECK23-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 15883 // CHECK23-NEXT: store double [[ADD2]], double* [[A]], align 4 15884 // CHECK23-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 15885 // CHECK23-NEXT: [[TMP5:%.*]] = load double, double* [[A3]], align 4 15886 // CHECK23-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 15887 // CHECK23-NEXT: store double [[INC]], double* [[A3]], align 4 15888 // CHECK23-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 15889 // CHECK23-NEXT: [[TMP6:%.*]] = mul nsw i32 1, [[TMP1]] 15890 // CHECK23-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP6]] 15891 // CHECK23-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 15892 // CHECK23-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 15893 // CHECK23-NEXT: [[TMP7:%.*]] = mul nsw i32 1, [[TMP1]] 15894 // CHECK23-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP7]] 15895 // CHECK23-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i32 1 15896 // CHECK23-NEXT: [[TMP8:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2 15897 // CHECK23-NEXT: [[CONV8:%.*]] = sext i16 [[TMP8]] to i32 15898 // CHECK23-NEXT: [[TMP9:%.*]] = load i32, i32* [[B]], align 4 15899 // CHECK23-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP9]] 15900 // CHECK23-NEXT: [[TMP10:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 15901 // CHECK23-NEXT: call void @llvm.stackrestore(i8* [[TMP10]]) 15902 // CHECK23-NEXT: ret i32 [[ADD9]] 15903 // 15904 // 15905 // CHECK23-LABEL: define {{[^@]+}}@_ZL7fstatici 15906 // CHECK23-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { 15907 // CHECK23-NEXT: entry: 15908 // CHECK23-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 15909 // CHECK23-NEXT: [[A:%.*]] = alloca i32, align 4 15910 // CHECK23-NEXT: [[AA:%.*]] = alloca i16, align 2 15911 // CHECK23-NEXT: [[AAA:%.*]] = alloca i8, align 1 15912 // CHECK23-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 15913 // CHECK23-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 15914 // CHECK23-NEXT: store i32 0, i32* [[A]], align 4 15915 // CHECK23-NEXT: store i16 0, i16* [[AA]], align 2 15916 // CHECK23-NEXT: store i8 0, i8* [[AAA]], align 1 15917 // CHECK23-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 15918 // CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 15919 // CHECK23-NEXT: store i32 [[ADD]], i32* [[A]], align 4 15920 // CHECK23-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 15921 // CHECK23-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 15922 // CHECK23-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 15923 // CHECK23-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 15924 // CHECK23-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 15925 // CHECK23-NEXT: [[TMP2:%.*]] = load i8, i8* [[AAA]], align 1 15926 // CHECK23-NEXT: [[CONV3:%.*]] = sext i8 [[TMP2]] to i32 15927 // CHECK23-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 15928 // CHECK23-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 15929 // CHECK23-NEXT: store i8 [[CONV5]], i8* [[AAA]], align 1 15930 // CHECK23-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 15931 // CHECK23-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 15932 // CHECK23-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP3]], 1 15933 // CHECK23-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 15934 // CHECK23-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 15935 // CHECK23-NEXT: ret i32 [[TMP4]] 15936 // 15937 // 15938 // CHECK23-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 15939 // CHECK23-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { 15940 // CHECK23-NEXT: entry: 15941 // CHECK23-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 15942 // CHECK23-NEXT: [[A:%.*]] = alloca i32, align 4 15943 // CHECK23-NEXT: [[AA:%.*]] = alloca i16, align 2 15944 // CHECK23-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 15945 // CHECK23-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 15946 // CHECK23-NEXT: store i32 0, i32* [[A]], align 4 15947 // CHECK23-NEXT: store i16 0, i16* [[AA]], align 2 15948 // CHECK23-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 15949 // CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 15950 // CHECK23-NEXT: store i32 [[ADD]], i32* [[A]], align 4 15951 // CHECK23-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 15952 // CHECK23-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 15953 // CHECK23-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 15954 // CHECK23-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 15955 // CHECK23-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 15956 // CHECK23-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 15957 // CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 15958 // CHECK23-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP2]], 1 15959 // CHECK23-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 15960 // CHECK23-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 15961 // CHECK23-NEXT: ret i32 [[TMP3]] 15962 // 15963 // 15964 // CHECK24-LABEL: define {{[^@]+}}@_Z3fooi 15965 // CHECK24-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { 15966 // CHECK24-NEXT: entry: 15967 // CHECK24-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 15968 // CHECK24-NEXT: [[A:%.*]] = alloca i32, align 4 15969 // CHECK24-NEXT: [[AA:%.*]] = alloca i16, align 2 15970 // CHECK24-NEXT: [[B:%.*]] = alloca [10 x float], align 4 15971 // CHECK24-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 15972 // CHECK24-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 15973 // CHECK24-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 15974 // CHECK24-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 15975 // CHECK24-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 15976 // CHECK24-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 15977 // CHECK24-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 15978 // CHECK24-NEXT: [[NN:%.*]] = alloca i32, align 4 15979 // CHECK24-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 15980 // CHECK24-NEXT: store i32 0, i32* [[A]], align 4 15981 // CHECK24-NEXT: store i16 0, i16* [[AA]], align 2 15982 // CHECK24-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 15983 // CHECK24-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() 15984 // CHECK24-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 15985 // CHECK24-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4 15986 // CHECK24-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 15987 // CHECK24-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 15988 // CHECK24-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]] 15989 // CHECK24-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8 15990 // CHECK24-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4 15991 // CHECK24-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 15992 // CHECK24-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 15993 // CHECK24-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 15994 // CHECK24-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_2]], align 4 15995 // CHECK24-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 15996 // CHECK24-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], 1 15997 // CHECK24-NEXT: store i32 [[ADD]], i32* [[A]], align 4 15998 // CHECK24-NEXT: [[TMP7:%.*]] = load i16, i16* [[AA]], align 2 15999 // CHECK24-NEXT: [[CONV:%.*]] = sext i16 [[TMP7]] to i32 16000 // CHECK24-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1 16001 // CHECK24-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 16002 // CHECK24-NEXT: store i16 [[CONV4]], i16* [[AA]], align 2 16003 // CHECK24-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 16004 // CHECK24-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP8]], 1 16005 // CHECK24-NEXT: store i32 [[ADD5]], i32* [[A]], align 4 16006 // CHECK24-NEXT: [[TMP9:%.*]] = load i16, i16* [[AA]], align 2 16007 // CHECK24-NEXT: [[CONV6:%.*]] = sext i16 [[TMP9]] to i32 16008 // CHECK24-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 16009 // CHECK24-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i16 16010 // CHECK24-NEXT: store i16 [[CONV8]], i16* [[AA]], align 2 16011 // CHECK24-NEXT: [[TMP10:%.*]] = load i32, i32* [[A]], align 4 16012 // CHECK24-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP10]], 1 16013 // CHECK24-NEXT: store i32 [[ADD9]], i32* [[A]], align 4 16014 // CHECK24-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2 16015 // CHECK24-NEXT: [[TMP11:%.*]] = load float, float* [[ARRAYIDX]], align 4 16016 // CHECK24-NEXT: [[CONV10:%.*]] = fpext float [[TMP11]] to double 16017 // CHECK24-NEXT: [[ADD11:%.*]] = fadd double [[CONV10]], 1.000000e+00 16018 // CHECK24-NEXT: [[CONV12:%.*]] = fptrunc double [[ADD11]] to float 16019 // CHECK24-NEXT: store float [[CONV12]], float* [[ARRAYIDX]], align 4 16020 // CHECK24-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3 16021 // CHECK24-NEXT: [[TMP12:%.*]] = load float, float* [[ARRAYIDX13]], align 4 16022 // CHECK24-NEXT: [[CONV14:%.*]] = fpext float [[TMP12]] to double 16023 // CHECK24-NEXT: [[ADD15:%.*]] = fadd double [[CONV14]], 1.000000e+00 16024 // CHECK24-NEXT: [[CONV16:%.*]] = fptrunc double [[ADD15]] to float 16025 // CHECK24-NEXT: store float [[CONV16]], float* [[ARRAYIDX13]], align 4 16026 // CHECK24-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1 16027 // CHECK24-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX17]], i32 0, i32 2 16028 // CHECK24-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX18]], align 8 16029 // CHECK24-NEXT: [[ADD19:%.*]] = fadd double [[TMP13]], 1.000000e+00 16030 // CHECK24-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8 16031 // CHECK24-NEXT: [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]] 16032 // CHECK24-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP14]] 16033 // CHECK24-NEXT: [[ARRAYIDX21:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX20]], i32 3 16034 // CHECK24-NEXT: [[TMP15:%.*]] = load double, double* [[ARRAYIDX21]], align 8 16035 // CHECK24-NEXT: [[ADD22:%.*]] = fadd double [[TMP15]], 1.000000e+00 16036 // CHECK24-NEXT: store double [[ADD22]], double* [[ARRAYIDX21]], align 8 16037 // CHECK24-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 16038 // CHECK24-NEXT: [[TMP16:%.*]] = load i64, i64* [[X]], align 4 16039 // CHECK24-NEXT: [[ADD23:%.*]] = add nsw i64 [[TMP16]], 1 16040 // CHECK24-NEXT: store i64 [[ADD23]], i64* [[X]], align 4 16041 // CHECK24-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 16042 // CHECK24-NEXT: [[TMP17:%.*]] = load i8, i8* [[Y]], align 4 16043 // CHECK24-NEXT: [[CONV24:%.*]] = sext i8 [[TMP17]] to i32 16044 // CHECK24-NEXT: [[ADD25:%.*]] = add nsw i32 [[CONV24]], 1 16045 // CHECK24-NEXT: [[CONV26:%.*]] = trunc i32 [[ADD25]] to i8 16046 // CHECK24-NEXT: store i8 [[CONV26]], i8* [[Y]], align 4 16047 // CHECK24-NEXT: store i32 0, i32* [[NN]], align 4 16048 // CHECK24-NEXT: [[TMP18:%.*]] = load i32, i32* [[A]], align 4 16049 // CHECK24-NEXT: [[TMP19:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 16050 // CHECK24-NEXT: call void @llvm.stackrestore(i8* [[TMP19]]) 16051 // CHECK24-NEXT: ret i32 [[TMP18]] 16052 // 16053 // 16054 // CHECK24-LABEL: define {{[^@]+}}@_Z6bazzzziPi 16055 // CHECK24-SAME: (i32 [[N:%.*]], i32* [[F:%.*]]) #[[ATTR0]] { 16056 // CHECK24-NEXT: entry: 16057 // CHECK24-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 16058 // CHECK24-NEXT: [[F_ADDR:%.*]] = alloca i32*, align 4 16059 // CHECK24-NEXT: [[F1:%.*]] = alloca i32*, align 4 16060 // CHECK24-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 16061 // CHECK24-NEXT: store i32* [[F]], i32** [[F_ADDR]], align 4 16062 // CHECK24-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 16063 // CHECK24-NEXT: ret void 16064 // 16065 // 16066 // CHECK24-LABEL: define {{[^@]+}}@_Z3bari 16067 // CHECK24-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { 16068 // CHECK24-NEXT: entry: 16069 // CHECK24-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 16070 // CHECK24-NEXT: [[A:%.*]] = alloca i32, align 4 16071 // CHECK24-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 16072 // CHECK24-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 16073 // CHECK24-NEXT: store i32 0, i32* [[A]], align 4 16074 // CHECK24-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 16075 // CHECK24-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]]) 16076 // CHECK24-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 16077 // CHECK24-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 16078 // CHECK24-NEXT: store i32 [[ADD]], i32* [[A]], align 4 16079 // CHECK24-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 16080 // CHECK24-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]]) 16081 // CHECK24-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 16082 // CHECK24-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 16083 // CHECK24-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 16084 // CHECK24-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 16085 // CHECK24-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]]) 16086 // CHECK24-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 16087 // CHECK24-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 16088 // CHECK24-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 16089 // CHECK24-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 16090 // CHECK24-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]]) 16091 // CHECK24-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 16092 // CHECK24-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] 16093 // CHECK24-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 16094 // CHECK24-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 16095 // CHECK24-NEXT: ret i32 [[TMP8]] 16096 // 16097 // 16098 // CHECK24-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 16099 // CHECK24-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { 16100 // CHECK24-NEXT: entry: 16101 // CHECK24-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 16102 // CHECK24-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 16103 // CHECK24-NEXT: [[B:%.*]] = alloca i32, align 4 16104 // CHECK24-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 16105 // CHECK24-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 16106 // CHECK24-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 16107 // CHECK24-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 16108 // CHECK24-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 16109 // CHECK24-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 16110 // CHECK24-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 16111 // CHECK24-NEXT: store i32 [[ADD]], i32* [[B]], align 4 16112 // CHECK24-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 16113 // CHECK24-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() 16114 // CHECK24-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 16115 // CHECK24-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] 16116 // CHECK24-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 16117 // CHECK24-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 16118 // CHECK24-NEXT: [[TMP4:%.*]] = load i32, i32* [[B]], align 4 16119 // CHECK24-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP4]] to double 16120 // CHECK24-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 16121 // CHECK24-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 16122 // CHECK24-NEXT: store double [[ADD2]], double* [[A]], align 4 16123 // CHECK24-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 16124 // CHECK24-NEXT: [[TMP5:%.*]] = load double, double* [[A3]], align 4 16125 // CHECK24-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 16126 // CHECK24-NEXT: store double [[INC]], double* [[A3]], align 4 16127 // CHECK24-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 16128 // CHECK24-NEXT: [[TMP6:%.*]] = mul nsw i32 1, [[TMP1]] 16129 // CHECK24-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP6]] 16130 // CHECK24-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 16131 // CHECK24-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 16132 // CHECK24-NEXT: [[TMP7:%.*]] = mul nsw i32 1, [[TMP1]] 16133 // CHECK24-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP7]] 16134 // CHECK24-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i32 1 16135 // CHECK24-NEXT: [[TMP8:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2 16136 // CHECK24-NEXT: [[CONV8:%.*]] = sext i16 [[TMP8]] to i32 16137 // CHECK24-NEXT: [[TMP9:%.*]] = load i32, i32* [[B]], align 4 16138 // CHECK24-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP9]] 16139 // CHECK24-NEXT: [[TMP10:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 16140 // CHECK24-NEXT: call void @llvm.stackrestore(i8* [[TMP10]]) 16141 // CHECK24-NEXT: ret i32 [[ADD9]] 16142 // 16143 // 16144 // CHECK24-LABEL: define {{[^@]+}}@_ZL7fstatici 16145 // CHECK24-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { 16146 // CHECK24-NEXT: entry: 16147 // CHECK24-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 16148 // CHECK24-NEXT: [[A:%.*]] = alloca i32, align 4 16149 // CHECK24-NEXT: [[AA:%.*]] = alloca i16, align 2 16150 // CHECK24-NEXT: [[AAA:%.*]] = alloca i8, align 1 16151 // CHECK24-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 16152 // CHECK24-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 16153 // CHECK24-NEXT: store i32 0, i32* [[A]], align 4 16154 // CHECK24-NEXT: store i16 0, i16* [[AA]], align 2 16155 // CHECK24-NEXT: store i8 0, i8* [[AAA]], align 1 16156 // CHECK24-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 16157 // CHECK24-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 16158 // CHECK24-NEXT: store i32 [[ADD]], i32* [[A]], align 4 16159 // CHECK24-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 16160 // CHECK24-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 16161 // CHECK24-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 16162 // CHECK24-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 16163 // CHECK24-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 16164 // CHECK24-NEXT: [[TMP2:%.*]] = load i8, i8* [[AAA]], align 1 16165 // CHECK24-NEXT: [[CONV3:%.*]] = sext i8 [[TMP2]] to i32 16166 // CHECK24-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 16167 // CHECK24-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 16168 // CHECK24-NEXT: store i8 [[CONV5]], i8* [[AAA]], align 1 16169 // CHECK24-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 16170 // CHECK24-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 16171 // CHECK24-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP3]], 1 16172 // CHECK24-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 16173 // CHECK24-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 16174 // CHECK24-NEXT: ret i32 [[TMP4]] 16175 // 16176 // 16177 // CHECK24-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 16178 // CHECK24-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { 16179 // CHECK24-NEXT: entry: 16180 // CHECK24-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 16181 // CHECK24-NEXT: [[A:%.*]] = alloca i32, align 4 16182 // CHECK24-NEXT: [[AA:%.*]] = alloca i16, align 2 16183 // CHECK24-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 16184 // CHECK24-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 16185 // CHECK24-NEXT: store i32 0, i32* [[A]], align 4 16186 // CHECK24-NEXT: store i16 0, i16* [[AA]], align 2 16187 // CHECK24-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 16188 // CHECK24-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 16189 // CHECK24-NEXT: store i32 [[ADD]], i32* [[A]], align 4 16190 // CHECK24-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 16191 // CHECK24-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 16192 // CHECK24-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 16193 // CHECK24-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 16194 // CHECK24-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 16195 // CHECK24-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 16196 // CHECK24-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 16197 // CHECK24-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP2]], 1 16198 // CHECK24-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 16199 // CHECK24-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 16200 // CHECK24-NEXT: ret i32 [[TMP3]] 16201 // 16202 // 16203 // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101 16204 // CHECK25-SAME: (i64 [[AA:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { 16205 // CHECK25-NEXT: entry: 16206 // CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 16207 // CHECK25-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 16208 // CHECK25-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8 16209 // CHECK25-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 16210 // CHECK25-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) 16211 // CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 16212 // CHECK25-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 16213 // CHECK25-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8 16214 // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 16215 // CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* 16216 // CHECK25-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32* 16217 // CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 8 16218 // CHECK25-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 8 16219 // CHECK25-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) 16220 // CHECK25-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 8 16221 // CHECK25-NEXT: [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 16222 // CHECK25-NEXT: store i16 [[TMP3]], i16* [[CONV5]], align 2 16223 // CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 16224 // CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]]) 16225 // CHECK25-NEXT: ret void 16226 // 16227 // 16228 // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined. 16229 // CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { 16230 // CHECK25-NEXT: entry: 16231 // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 16232 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 16233 // CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 16234 // CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 16235 // CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 16236 // CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 16237 // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 16238 // CHECK25-NEXT: ret void 16239 // 16240 // 16241 // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 16242 // CHECK25-SAME: (i64 [[AA:%.*]]) #[[ATTR0]] { 16243 // CHECK25-NEXT: entry: 16244 // CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 16245 // CHECK25-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 16246 // CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 16247 // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 16248 // CHECK25-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8 16249 // CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 16250 // CHECK25-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 16251 // CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 16252 // CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]]) 16253 // CHECK25-NEXT: ret void 16254 // 16255 // 16256 // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..1 16257 // CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { 16258 // CHECK25-NEXT: entry: 16259 // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 16260 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 16261 // CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 16262 // CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 16263 // CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 16264 // CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 16265 // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 16266 // CHECK25-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8 16267 // CHECK25-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 16268 // CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 16269 // CHECK25-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 16270 // CHECK25-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 8 16271 // CHECK25-NEXT: ret void 16272 // 16273 // 16274 // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118 16275 // CHECK25-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { 16276 // CHECK25-NEXT: entry: 16277 // CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 16278 // CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 16279 // CHECK25-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 16280 // CHECK25-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 16281 // CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 16282 // CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 16283 // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 16284 // CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 16285 // CHECK25-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 16286 // CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* 16287 // CHECK25-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 16288 // CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 16289 // CHECK25-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 16290 // CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 16291 // CHECK25-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 16292 // CHECK25-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 16293 // CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) 16294 // CHECK25-NEXT: ret void 16295 // 16296 // 16297 // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..2 16298 // CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { 16299 // CHECK25-NEXT: entry: 16300 // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 16301 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 16302 // CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 16303 // CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 16304 // CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 16305 // CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 16306 // CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 16307 // CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 16308 // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 16309 // CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 16310 // CHECK25-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 16311 // CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 16312 // CHECK25-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 16313 // CHECK25-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 8 16314 // CHECK25-NEXT: [[CONV2:%.*]] = sext i16 [[TMP1]] to i32 16315 // CHECK25-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 16316 // CHECK25-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 16317 // CHECK25-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 8 16318 // CHECK25-NEXT: ret void 16319 // 16320 // 16321 // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142 16322 // CHECK25-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] { 16323 // CHECK25-NEXT: entry: 16324 // CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 16325 // CHECK25-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 16326 // CHECK25-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 16327 // CHECK25-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 16328 // CHECK25-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 16329 // CHECK25-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 16330 // CHECK25-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 16331 // CHECK25-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 16332 // CHECK25-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 16333 // CHECK25-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 16334 // CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 16335 // CHECK25-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 16336 // CHECK25-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 16337 // CHECK25-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 16338 // CHECK25-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 16339 // CHECK25-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 16340 // CHECK25-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 16341 // CHECK25-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 16342 // CHECK25-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 16343 // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 16344 // CHECK25-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 16345 // CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 16346 // CHECK25-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 16347 // CHECK25-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 16348 // CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 16349 // CHECK25-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 16350 // CHECK25-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 16351 // CHECK25-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 16352 // CHECK25-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 16353 // CHECK25-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* 16354 // CHECK25-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4 16355 // CHECK25-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 16356 // CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) 16357 // CHECK25-NEXT: ret void 16358 // 16359 // 16360 // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..3 16361 // CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] { 16362 // CHECK25-NEXT: entry: 16363 // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 16364 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 16365 // CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 16366 // CHECK25-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 16367 // CHECK25-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 16368 // CHECK25-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 16369 // CHECK25-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 16370 // CHECK25-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 16371 // CHECK25-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 16372 // CHECK25-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 16373 // CHECK25-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 16374 // CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 16375 // CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 16376 // CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 16377 // CHECK25-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 16378 // CHECK25-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 16379 // CHECK25-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 16380 // CHECK25-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 16381 // CHECK25-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 16382 // CHECK25-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 16383 // CHECK25-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 16384 // CHECK25-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 16385 // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 16386 // CHECK25-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 16387 // CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 16388 // CHECK25-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 16389 // CHECK25-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 16390 // CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 16391 // CHECK25-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 16392 // CHECK25-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 16393 // CHECK25-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 16394 // CHECK25-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 16395 // CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 16396 // CHECK25-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 16397 // CHECK25-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 16398 // CHECK25-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 16399 // CHECK25-NEXT: [[CONV5:%.*]] = fpext float [[TMP9]] to double 16400 // CHECK25-NEXT: [[ADD6:%.*]] = fadd double [[CONV5]], 1.000000e+00 16401 // CHECK25-NEXT: [[CONV7:%.*]] = fptrunc double [[ADD6]] to float 16402 // CHECK25-NEXT: store float [[CONV7]], float* [[ARRAYIDX]], align 4 16403 // CHECK25-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 16404 // CHECK25-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX8]], align 4 16405 // CHECK25-NEXT: [[CONV9:%.*]] = fpext float [[TMP10]] to double 16406 // CHECK25-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 16407 // CHECK25-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float 16408 // CHECK25-NEXT: store float [[CONV11]], float* [[ARRAYIDX8]], align 4 16409 // CHECK25-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1 16410 // CHECK25-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX12]], i64 0, i64 2 16411 // CHECK25-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX13]], align 8 16412 // CHECK25-NEXT: [[ADD14:%.*]] = fadd double [[TMP11]], 1.000000e+00 16413 // CHECK25-NEXT: store double [[ADD14]], double* [[ARRAYIDX13]], align 8 16414 // CHECK25-NEXT: [[TMP12:%.*]] = mul nsw i64 1, [[TMP5]] 16415 // CHECK25-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP12]] 16416 // CHECK25-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX15]], i64 3 16417 // CHECK25-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX16]], align 8 16418 // CHECK25-NEXT: [[ADD17:%.*]] = fadd double [[TMP13]], 1.000000e+00 16419 // CHECK25-NEXT: store double [[ADD17]], double* [[ARRAYIDX16]], align 8 16420 // CHECK25-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 16421 // CHECK25-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 8 16422 // CHECK25-NEXT: [[ADD18:%.*]] = add nsw i64 [[TMP14]], 1 16423 // CHECK25-NEXT: store i64 [[ADD18]], i64* [[X]], align 8 16424 // CHECK25-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 16425 // CHECK25-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 8 16426 // CHECK25-NEXT: [[CONV19:%.*]] = sext i8 [[TMP15]] to i32 16427 // CHECK25-NEXT: [[ADD20:%.*]] = add nsw i32 [[CONV19]], 1 16428 // CHECK25-NEXT: [[CONV21:%.*]] = trunc i32 [[ADD20]] to i8 16429 // CHECK25-NEXT: store i8 [[CONV21]], i8* [[Y]], align 8 16430 // CHECK25-NEXT: ret void 16431 // 16432 // 16433 // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154 16434 // CHECK25-SAME: (i64 [[NN:%.*]]) #[[ATTR0]] { 16435 // CHECK25-NEXT: entry: 16436 // CHECK25-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 16437 // CHECK25-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 16438 // CHECK25-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 16439 // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* 16440 // CHECK25-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 16441 // CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32* 16442 // CHECK25-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 16443 // CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8 16444 // CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP1]]) 16445 // CHECK25-NEXT: ret void 16446 // 16447 // 16448 // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..4 16449 // CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[NN:%.*]]) #[[ATTR0]] { 16450 // CHECK25-NEXT: entry: 16451 // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 16452 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 16453 // CHECK25-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 16454 // CHECK25-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 16455 // CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 16456 // CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 16457 // CHECK25-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 16458 // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* 16459 // CHECK25-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 16460 // CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32* 16461 // CHECK25-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 16462 // CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8 16463 // CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP1]]) 16464 // CHECK25-NEXT: ret void 16465 // 16466 // 16467 // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..5 16468 // CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[NN:%.*]]) #[[ATTR0]] { 16469 // CHECK25-NEXT: entry: 16470 // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 16471 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 16472 // CHECK25-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 16473 // CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 16474 // CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 16475 // CHECK25-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 16476 // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* 16477 // CHECK25-NEXT: ret void 16478 // 16479 // 16480 // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157 16481 // CHECK25-SAME: (i64 [[NN:%.*]]) #[[ATTR0]] { 16482 // CHECK25-NEXT: entry: 16483 // CHECK25-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 16484 // CHECK25-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 16485 // CHECK25-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 16486 // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* 16487 // CHECK25-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 16488 // CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32* 16489 // CHECK25-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 16490 // CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8 16491 // CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP1]]) 16492 // CHECK25-NEXT: ret void 16493 // 16494 // 16495 // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..6 16496 // CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[NN:%.*]]) #[[ATTR0]] { 16497 // CHECK25-NEXT: entry: 16498 // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 16499 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 16500 // CHECK25-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 16501 // CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 16502 // CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 16503 // CHECK25-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 16504 // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* 16505 // CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32* [[CONV]]) 16506 // CHECK25-NEXT: ret void 16507 // 16508 // 16509 // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..7 16510 // CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[NN:%.*]]) #[[ATTR0]] { 16511 // CHECK25-NEXT: entry: 16512 // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 16513 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 16514 // CHECK25-NEXT: [[NN_ADDR:%.*]] = alloca i32*, align 8 16515 // CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 16516 // CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 16517 // CHECK25-NEXT: store i32* [[NN]], i32** [[NN_ADDR]], align 8 16518 // CHECK25-NEXT: [[TMP0:%.*]] = load i32*, i32** [[NN_ADDR]], align 8 16519 // CHECK25-NEXT: ret void 16520 // 16521 // 16522 // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182 16523 // CHECK25-SAME: (i64 [[VLA:%.*]]) #[[ATTR0]] { 16524 // CHECK25-NEXT: entry: 16525 // CHECK25-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 16526 // CHECK25-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 16527 // CHECK25-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 16528 // CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..8 to void (i32*, i32*, ...)*), i64 [[TMP0]]) 16529 // CHECK25-NEXT: ret void 16530 // 16531 // 16532 // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..8 16533 // CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[VLA:%.*]]) #[[ATTR0]] { 16534 // CHECK25-NEXT: entry: 16535 // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 16536 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 16537 // CHECK25-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 16538 // CHECK25-NEXT: [[F:%.*]] = alloca i32*, align 8 16539 // CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 16540 // CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 16541 // CHECK25-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 16542 // CHECK25-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 16543 // CHECK25-NEXT: ret void 16544 // 16545 // 16546 // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209 16547 // CHECK25-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 16548 // CHECK25-NEXT: entry: 16549 // CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 16550 // CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 16551 // CHECK25-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 16552 // CHECK25-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 16553 // CHECK25-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 16554 // CHECK25-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 16555 // CHECK25-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 16556 // CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 16557 // CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 16558 // CHECK25-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 16559 // CHECK25-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 16560 // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 16561 // CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 16562 // CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 16563 // CHECK25-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 16564 // CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 16565 // CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* 16566 // CHECK25-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 16567 // CHECK25-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 16568 // CHECK25-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 16569 // CHECK25-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 16570 // CHECK25-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 16571 // CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 16572 // CHECK25-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8 16573 // CHECK25-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* 16574 // CHECK25-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 16575 // CHECK25-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 16576 // CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) 16577 // CHECK25-NEXT: ret void 16578 // 16579 // 16580 // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..9 16581 // CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 16582 // CHECK25-NEXT: entry: 16583 // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 16584 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 16585 // CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 16586 // CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 16587 // CHECK25-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 16588 // CHECK25-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 16589 // CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 16590 // CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 16591 // CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 16592 // CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 16593 // CHECK25-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 16594 // CHECK25-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 16595 // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 16596 // CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 16597 // CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 16598 // CHECK25-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 16599 // CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 16600 // CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 16601 // CHECK25-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 16602 // CHECK25-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 16603 // CHECK25-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32 16604 // CHECK25-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 16605 // CHECK25-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 16606 // CHECK25-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 8 16607 // CHECK25-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 8 16608 // CHECK25-NEXT: [[CONV6:%.*]] = sext i8 [[TMP3]] to i32 16609 // CHECK25-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 16610 // CHECK25-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i8 16611 // CHECK25-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 8 16612 // CHECK25-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 16613 // CHECK25-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 16614 // CHECK25-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP4]], 1 16615 // CHECK25-NEXT: store i32 [[ADD9]], i32* [[ARRAYIDX]], align 4 16616 // CHECK25-NEXT: ret void 16617 // 16618 // 16619 // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227 16620 // CHECK25-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { 16621 // CHECK25-NEXT: entry: 16622 // CHECK25-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 16623 // CHECK25-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 16624 // CHECK25-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 16625 // CHECK25-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 16626 // CHECK25-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 16627 // CHECK25-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 16628 // CHECK25-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 16629 // CHECK25-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 16630 // CHECK25-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 16631 // CHECK25-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 16632 // CHECK25-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 16633 // CHECK25-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 16634 // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 16635 // CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 16636 // CHECK25-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 16637 // CHECK25-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 16638 // CHECK25-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 16639 // CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* 16640 // CHECK25-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 16641 // CHECK25-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 16642 // CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) 16643 // CHECK25-NEXT: ret void 16644 // 16645 // 16646 // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..10 16647 // CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { 16648 // CHECK25-NEXT: entry: 16649 // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 16650 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 16651 // CHECK25-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 16652 // CHECK25-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 16653 // CHECK25-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 16654 // CHECK25-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 16655 // CHECK25-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 16656 // CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 16657 // CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 16658 // CHECK25-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 16659 // CHECK25-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 16660 // CHECK25-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 16661 // CHECK25-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 16662 // CHECK25-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 16663 // CHECK25-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 16664 // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 16665 // CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 16666 // CHECK25-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 16667 // CHECK25-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 16668 // CHECK25-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 16669 // CHECK25-NEXT: [[CONV3:%.*]] = sitofp i32 [[TMP4]] to double 16670 // CHECK25-NEXT: [[ADD:%.*]] = fadd double [[CONV3]], 1.500000e+00 16671 // CHECK25-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 16672 // CHECK25-NEXT: store double [[ADD]], double* [[A]], align 8 16673 // CHECK25-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 16674 // CHECK25-NEXT: [[TMP5:%.*]] = load double, double* [[A4]], align 8 16675 // CHECK25-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 16676 // CHECK25-NEXT: store double [[INC]], double* [[A4]], align 8 16677 // CHECK25-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 16678 // CHECK25-NEXT: [[TMP6:%.*]] = mul nsw i64 1, [[TMP2]] 16679 // CHECK25-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP6]] 16680 // CHECK25-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 16681 // CHECK25-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2 16682 // CHECK25-NEXT: ret void 16683 // 16684 // 16685 // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192 16686 // CHECK25-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 16687 // CHECK25-NEXT: entry: 16688 // CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 16689 // CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 16690 // CHECK25-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 16691 // CHECK25-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 16692 // CHECK25-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 16693 // CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 16694 // CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 16695 // CHECK25-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 16696 // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 16697 // CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 16698 // CHECK25-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 16699 // CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 16700 // CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* 16701 // CHECK25-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 16702 // CHECK25-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 16703 // CHECK25-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 16704 // CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 16705 // CHECK25-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 16706 // CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 16707 // CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) 16708 // CHECK25-NEXT: ret void 16709 // 16710 // 16711 // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..11 16712 // CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 16713 // CHECK25-NEXT: entry: 16714 // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 16715 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 16716 // CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 16717 // CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 16718 // CHECK25-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 16719 // CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 16720 // CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 16721 // CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 16722 // CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 16723 // CHECK25-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 16724 // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 16725 // CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 16726 // CHECK25-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 16727 // CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 16728 // CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 16729 // CHECK25-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 16730 // CHECK25-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 16731 // CHECK25-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 16732 // CHECK25-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 16733 // CHECK25-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 16734 // CHECK25-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 8 16735 // CHECK25-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 16736 // CHECK25-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 16737 // CHECK25-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP3]], 1 16738 // CHECK25-NEXT: store i32 [[ADD5]], i32* [[ARRAYIDX]], align 4 16739 // CHECK25-NEXT: ret void 16740 // 16741 // 16742 // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101 16743 // CHECK26-SAME: (i64 [[AA:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { 16744 // CHECK26-NEXT: entry: 16745 // CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 16746 // CHECK26-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 16747 // CHECK26-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8 16748 // CHECK26-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 16749 // CHECK26-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) 16750 // CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 16751 // CHECK26-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 16752 // CHECK26-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8 16753 // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 16754 // CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* 16755 // CHECK26-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32* 16756 // CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 8 16757 // CHECK26-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 8 16758 // CHECK26-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) 16759 // CHECK26-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 8 16760 // CHECK26-NEXT: [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 16761 // CHECK26-NEXT: store i16 [[TMP3]], i16* [[CONV5]], align 2 16762 // CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 16763 // CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]]) 16764 // CHECK26-NEXT: ret void 16765 // 16766 // 16767 // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined. 16768 // CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { 16769 // CHECK26-NEXT: entry: 16770 // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 16771 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 16772 // CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 16773 // CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 16774 // CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 16775 // CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 16776 // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 16777 // CHECK26-NEXT: ret void 16778 // 16779 // 16780 // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 16781 // CHECK26-SAME: (i64 [[AA:%.*]]) #[[ATTR0]] { 16782 // CHECK26-NEXT: entry: 16783 // CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 16784 // CHECK26-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 16785 // CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 16786 // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 16787 // CHECK26-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8 16788 // CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 16789 // CHECK26-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 16790 // CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 16791 // CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]]) 16792 // CHECK26-NEXT: ret void 16793 // 16794 // 16795 // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..1 16796 // CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { 16797 // CHECK26-NEXT: entry: 16798 // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 16799 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 16800 // CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 16801 // CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 16802 // CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 16803 // CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 16804 // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 16805 // CHECK26-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8 16806 // CHECK26-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 16807 // CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 16808 // CHECK26-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 16809 // CHECK26-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 8 16810 // CHECK26-NEXT: ret void 16811 // 16812 // 16813 // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118 16814 // CHECK26-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { 16815 // CHECK26-NEXT: entry: 16816 // CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 16817 // CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 16818 // CHECK26-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 16819 // CHECK26-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 16820 // CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 16821 // CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 16822 // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 16823 // CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 16824 // CHECK26-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 16825 // CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* 16826 // CHECK26-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 16827 // CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 16828 // CHECK26-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 16829 // CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 16830 // CHECK26-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 16831 // CHECK26-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 16832 // CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) 16833 // CHECK26-NEXT: ret void 16834 // 16835 // 16836 // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..2 16837 // CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { 16838 // CHECK26-NEXT: entry: 16839 // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 16840 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 16841 // CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 16842 // CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 16843 // CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 16844 // CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 16845 // CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 16846 // CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 16847 // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 16848 // CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 16849 // CHECK26-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 16850 // CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 16851 // CHECK26-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 16852 // CHECK26-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 8 16853 // CHECK26-NEXT: [[CONV2:%.*]] = sext i16 [[TMP1]] to i32 16854 // CHECK26-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 16855 // CHECK26-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 16856 // CHECK26-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 8 16857 // CHECK26-NEXT: ret void 16858 // 16859 // 16860 // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142 16861 // CHECK26-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] { 16862 // CHECK26-NEXT: entry: 16863 // CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 16864 // CHECK26-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 16865 // CHECK26-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 16866 // CHECK26-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 16867 // CHECK26-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 16868 // CHECK26-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 16869 // CHECK26-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 16870 // CHECK26-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 16871 // CHECK26-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 16872 // CHECK26-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 16873 // CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 16874 // CHECK26-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 16875 // CHECK26-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 16876 // CHECK26-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 16877 // CHECK26-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 16878 // CHECK26-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 16879 // CHECK26-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 16880 // CHECK26-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 16881 // CHECK26-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 16882 // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 16883 // CHECK26-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 16884 // CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 16885 // CHECK26-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 16886 // CHECK26-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 16887 // CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 16888 // CHECK26-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 16889 // CHECK26-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 16890 // CHECK26-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 16891 // CHECK26-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 16892 // CHECK26-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* 16893 // CHECK26-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4 16894 // CHECK26-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 16895 // CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) 16896 // CHECK26-NEXT: ret void 16897 // 16898 // 16899 // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..3 16900 // CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] { 16901 // CHECK26-NEXT: entry: 16902 // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 16903 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 16904 // CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 16905 // CHECK26-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 16906 // CHECK26-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 16907 // CHECK26-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 16908 // CHECK26-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 16909 // CHECK26-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 16910 // CHECK26-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 16911 // CHECK26-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 16912 // CHECK26-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 16913 // CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 16914 // CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 16915 // CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 16916 // CHECK26-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 16917 // CHECK26-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 16918 // CHECK26-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 16919 // CHECK26-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 16920 // CHECK26-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 16921 // CHECK26-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 16922 // CHECK26-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 16923 // CHECK26-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 16924 // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 16925 // CHECK26-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 16926 // CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 16927 // CHECK26-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 16928 // CHECK26-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 16929 // CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 16930 // CHECK26-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 16931 // CHECK26-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 16932 // CHECK26-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 16933 // CHECK26-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8 16934 // CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 16935 // CHECK26-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 16936 // CHECK26-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 16937 // CHECK26-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 16938 // CHECK26-NEXT: [[CONV5:%.*]] = fpext float [[TMP9]] to double 16939 // CHECK26-NEXT: [[ADD6:%.*]] = fadd double [[CONV5]], 1.000000e+00 16940 // CHECK26-NEXT: [[CONV7:%.*]] = fptrunc double [[ADD6]] to float 16941 // CHECK26-NEXT: store float [[CONV7]], float* [[ARRAYIDX]], align 4 16942 // CHECK26-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 16943 // CHECK26-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX8]], align 4 16944 // CHECK26-NEXT: [[CONV9:%.*]] = fpext float [[TMP10]] to double 16945 // CHECK26-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 16946 // CHECK26-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float 16947 // CHECK26-NEXT: store float [[CONV11]], float* [[ARRAYIDX8]], align 4 16948 // CHECK26-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1 16949 // CHECK26-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX12]], i64 0, i64 2 16950 // CHECK26-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX13]], align 8 16951 // CHECK26-NEXT: [[ADD14:%.*]] = fadd double [[TMP11]], 1.000000e+00 16952 // CHECK26-NEXT: store double [[ADD14]], double* [[ARRAYIDX13]], align 8 16953 // CHECK26-NEXT: [[TMP12:%.*]] = mul nsw i64 1, [[TMP5]] 16954 // CHECK26-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP12]] 16955 // CHECK26-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX15]], i64 3 16956 // CHECK26-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX16]], align 8 16957 // CHECK26-NEXT: [[ADD17:%.*]] = fadd double [[TMP13]], 1.000000e+00 16958 // CHECK26-NEXT: store double [[ADD17]], double* [[ARRAYIDX16]], align 8 16959 // CHECK26-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 16960 // CHECK26-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 8 16961 // CHECK26-NEXT: [[ADD18:%.*]] = add nsw i64 [[TMP14]], 1 16962 // CHECK26-NEXT: store i64 [[ADD18]], i64* [[X]], align 8 16963 // CHECK26-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 16964 // CHECK26-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 8 16965 // CHECK26-NEXT: [[CONV19:%.*]] = sext i8 [[TMP15]] to i32 16966 // CHECK26-NEXT: [[ADD20:%.*]] = add nsw i32 [[CONV19]], 1 16967 // CHECK26-NEXT: [[CONV21:%.*]] = trunc i32 [[ADD20]] to i8 16968 // CHECK26-NEXT: store i8 [[CONV21]], i8* [[Y]], align 8 16969 // CHECK26-NEXT: ret void 16970 // 16971 // 16972 // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154 16973 // CHECK26-SAME: (i64 [[NN:%.*]]) #[[ATTR0]] { 16974 // CHECK26-NEXT: entry: 16975 // CHECK26-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 16976 // CHECK26-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 16977 // CHECK26-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 16978 // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* 16979 // CHECK26-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 16980 // CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32* 16981 // CHECK26-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 16982 // CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8 16983 // CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP1]]) 16984 // CHECK26-NEXT: ret void 16985 // 16986 // 16987 // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..4 16988 // CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[NN:%.*]]) #[[ATTR0]] { 16989 // CHECK26-NEXT: entry: 16990 // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 16991 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 16992 // CHECK26-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 16993 // CHECK26-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 16994 // CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 16995 // CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 16996 // CHECK26-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 16997 // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* 16998 // CHECK26-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 16999 // CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32* 17000 // CHECK26-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 17001 // CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8 17002 // CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP1]]) 17003 // CHECK26-NEXT: ret void 17004 // 17005 // 17006 // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..5 17007 // CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[NN:%.*]]) #[[ATTR0]] { 17008 // CHECK26-NEXT: entry: 17009 // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 17010 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 17011 // CHECK26-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 17012 // CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 17013 // CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 17014 // CHECK26-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 17015 // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* 17016 // CHECK26-NEXT: ret void 17017 // 17018 // 17019 // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157 17020 // CHECK26-SAME: (i64 [[NN:%.*]]) #[[ATTR0]] { 17021 // CHECK26-NEXT: entry: 17022 // CHECK26-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 17023 // CHECK26-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 17024 // CHECK26-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 17025 // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* 17026 // CHECK26-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 17027 // CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32* 17028 // CHECK26-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 17029 // CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8 17030 // CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP1]]) 17031 // CHECK26-NEXT: ret void 17032 // 17033 // 17034 // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..6 17035 // CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[NN:%.*]]) #[[ATTR0]] { 17036 // CHECK26-NEXT: entry: 17037 // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 17038 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 17039 // CHECK26-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 17040 // CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 17041 // CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 17042 // CHECK26-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 17043 // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* 17044 // CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32* [[CONV]]) 17045 // CHECK26-NEXT: ret void 17046 // 17047 // 17048 // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..7 17049 // CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[NN:%.*]]) #[[ATTR0]] { 17050 // CHECK26-NEXT: entry: 17051 // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 17052 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 17053 // CHECK26-NEXT: [[NN_ADDR:%.*]] = alloca i32*, align 8 17054 // CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 17055 // CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 17056 // CHECK26-NEXT: store i32* [[NN]], i32** [[NN_ADDR]], align 8 17057 // CHECK26-NEXT: [[TMP0:%.*]] = load i32*, i32** [[NN_ADDR]], align 8 17058 // CHECK26-NEXT: ret void 17059 // 17060 // 17061 // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182 17062 // CHECK26-SAME: (i64 [[VLA:%.*]]) #[[ATTR0]] { 17063 // CHECK26-NEXT: entry: 17064 // CHECK26-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 17065 // CHECK26-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 17066 // CHECK26-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 17067 // CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..8 to void (i32*, i32*, ...)*), i64 [[TMP0]]) 17068 // CHECK26-NEXT: ret void 17069 // 17070 // 17071 // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..8 17072 // CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[VLA:%.*]]) #[[ATTR0]] { 17073 // CHECK26-NEXT: entry: 17074 // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 17075 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 17076 // CHECK26-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 17077 // CHECK26-NEXT: [[F:%.*]] = alloca i32*, align 8 17078 // CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 17079 // CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 17080 // CHECK26-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 17081 // CHECK26-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 17082 // CHECK26-NEXT: ret void 17083 // 17084 // 17085 // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209 17086 // CHECK26-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 17087 // CHECK26-NEXT: entry: 17088 // CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 17089 // CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 17090 // CHECK26-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 17091 // CHECK26-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 17092 // CHECK26-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 17093 // CHECK26-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 17094 // CHECK26-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 17095 // CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 17096 // CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 17097 // CHECK26-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 17098 // CHECK26-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 17099 // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 17100 // CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 17101 // CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 17102 // CHECK26-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 17103 // CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 17104 // CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* 17105 // CHECK26-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 17106 // CHECK26-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 17107 // CHECK26-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 17108 // CHECK26-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 17109 // CHECK26-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 17110 // CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 17111 // CHECK26-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8 17112 // CHECK26-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* 17113 // CHECK26-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 17114 // CHECK26-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 17115 // CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) 17116 // CHECK26-NEXT: ret void 17117 // 17118 // 17119 // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..9 17120 // CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 17121 // CHECK26-NEXT: entry: 17122 // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 17123 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 17124 // CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 17125 // CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 17126 // CHECK26-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 17127 // CHECK26-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 17128 // CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 17129 // CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 17130 // CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 17131 // CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 17132 // CHECK26-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 17133 // CHECK26-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 17134 // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 17135 // CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 17136 // CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 17137 // CHECK26-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 17138 // CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 17139 // CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 17140 // CHECK26-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 17141 // CHECK26-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 17142 // CHECK26-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32 17143 // CHECK26-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 17144 // CHECK26-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 17145 // CHECK26-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 8 17146 // CHECK26-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 8 17147 // CHECK26-NEXT: [[CONV6:%.*]] = sext i8 [[TMP3]] to i32 17148 // CHECK26-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 17149 // CHECK26-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i8 17150 // CHECK26-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 8 17151 // CHECK26-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 17152 // CHECK26-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 17153 // CHECK26-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP4]], 1 17154 // CHECK26-NEXT: store i32 [[ADD9]], i32* [[ARRAYIDX]], align 4 17155 // CHECK26-NEXT: ret void 17156 // 17157 // 17158 // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227 17159 // CHECK26-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { 17160 // CHECK26-NEXT: entry: 17161 // CHECK26-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 17162 // CHECK26-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 17163 // CHECK26-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 17164 // CHECK26-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 17165 // CHECK26-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 17166 // CHECK26-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 17167 // CHECK26-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 17168 // CHECK26-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 17169 // CHECK26-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 17170 // CHECK26-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 17171 // CHECK26-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 17172 // CHECK26-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 17173 // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 17174 // CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 17175 // CHECK26-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 17176 // CHECK26-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 17177 // CHECK26-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 17178 // CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* 17179 // CHECK26-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 17180 // CHECK26-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 17181 // CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) 17182 // CHECK26-NEXT: ret void 17183 // 17184 // 17185 // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..10 17186 // CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { 17187 // CHECK26-NEXT: entry: 17188 // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 17189 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 17190 // CHECK26-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 17191 // CHECK26-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 17192 // CHECK26-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 17193 // CHECK26-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 17194 // CHECK26-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 17195 // CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 17196 // CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 17197 // CHECK26-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 17198 // CHECK26-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 17199 // CHECK26-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 17200 // CHECK26-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 17201 // CHECK26-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 17202 // CHECK26-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 17203 // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 17204 // CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 17205 // CHECK26-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 17206 // CHECK26-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 17207 // CHECK26-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 17208 // CHECK26-NEXT: [[CONV3:%.*]] = sitofp i32 [[TMP4]] to double 17209 // CHECK26-NEXT: [[ADD:%.*]] = fadd double [[CONV3]], 1.500000e+00 17210 // CHECK26-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 17211 // CHECK26-NEXT: store double [[ADD]], double* [[A]], align 8 17212 // CHECK26-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 17213 // CHECK26-NEXT: [[TMP5:%.*]] = load double, double* [[A4]], align 8 17214 // CHECK26-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 17215 // CHECK26-NEXT: store double [[INC]], double* [[A4]], align 8 17216 // CHECK26-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 17217 // CHECK26-NEXT: [[TMP6:%.*]] = mul nsw i64 1, [[TMP2]] 17218 // CHECK26-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP6]] 17219 // CHECK26-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 17220 // CHECK26-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2 17221 // CHECK26-NEXT: ret void 17222 // 17223 // 17224 // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192 17225 // CHECK26-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 17226 // CHECK26-NEXT: entry: 17227 // CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 17228 // CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 17229 // CHECK26-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 17230 // CHECK26-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 17231 // CHECK26-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 17232 // CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 17233 // CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 17234 // CHECK26-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 17235 // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 17236 // CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 17237 // CHECK26-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 17238 // CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 17239 // CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* 17240 // CHECK26-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 17241 // CHECK26-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 17242 // CHECK26-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8 17243 // CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 17244 // CHECK26-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 17245 // CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 17246 // CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) 17247 // CHECK26-NEXT: ret void 17248 // 17249 // 17250 // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..11 17251 // CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 17252 // CHECK26-NEXT: entry: 17253 // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 17254 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 17255 // CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 17256 // CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 17257 // CHECK26-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 17258 // CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 17259 // CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 17260 // CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 17261 // CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 17262 // CHECK26-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 17263 // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 17264 // CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 17265 // CHECK26-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 17266 // CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 17267 // CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 17268 // CHECK26-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 17269 // CHECK26-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 17270 // CHECK26-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 17271 // CHECK26-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 17272 // CHECK26-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 17273 // CHECK26-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 8 17274 // CHECK26-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 17275 // CHECK26-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 17276 // CHECK26-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP3]], 1 17277 // CHECK26-NEXT: store i32 [[ADD5]], i32* [[ARRAYIDX]], align 4 17278 // CHECK26-NEXT: ret void 17279 // 17280 // 17281 // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101 17282 // CHECK27-SAME: (i32 [[AA:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]], i32 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { 17283 // CHECK27-NEXT: entry: 17284 // CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 17285 // CHECK27-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 17286 // CHECK27-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4 17287 // CHECK27-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 17288 // CHECK27-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) 17289 // CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 17290 // CHECK27-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 17291 // CHECK27-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 17292 // CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 17293 // CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 17294 // CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 17295 // CHECK27-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) 17296 // CHECK27-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 17297 // CHECK27-NEXT: [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 17298 // CHECK27-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 17299 // CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 17300 // CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]]) 17301 // CHECK27-NEXT: ret void 17302 // 17303 // 17304 // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined. 17305 // CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { 17306 // CHECK27-NEXT: entry: 17307 // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 17308 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 17309 // CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 17310 // CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 17311 // CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 17312 // CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 17313 // CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 17314 // CHECK27-NEXT: ret void 17315 // 17316 // 17317 // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 17318 // CHECK27-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] { 17319 // CHECK27-NEXT: entry: 17320 // CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 17321 // CHECK27-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 17322 // CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 17323 // CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 17324 // CHECK27-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 17325 // CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 17326 // CHECK27-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 17327 // CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 17328 // CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]]) 17329 // CHECK27-NEXT: ret void 17330 // 17331 // 17332 // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..1 17333 // CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { 17334 // CHECK27-NEXT: entry: 17335 // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 17336 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 17337 // CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 17338 // CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 17339 // CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 17340 // CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 17341 // CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 17342 // CHECK27-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 17343 // CHECK27-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 17344 // CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 17345 // CHECK27-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 17346 // CHECK27-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 4 17347 // CHECK27-NEXT: ret void 17348 // 17349 // 17350 // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118 17351 // CHECK27-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { 17352 // CHECK27-NEXT: entry: 17353 // CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 17354 // CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 17355 // CHECK27-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 17356 // CHECK27-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 17357 // CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 17358 // CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 17359 // CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 17360 // CHECK27-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 17361 // CHECK27-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 17362 // CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 17363 // CHECK27-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 17364 // CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 17365 // CHECK27-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 17366 // CHECK27-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 17367 // CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) 17368 // CHECK27-NEXT: ret void 17369 // 17370 // 17371 // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..2 17372 // CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { 17373 // CHECK27-NEXT: entry: 17374 // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 17375 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 17376 // CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 17377 // CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 17378 // CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 17379 // CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 17380 // CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 17381 // CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 17382 // CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 17383 // CHECK27-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 17384 // CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 17385 // CHECK27-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 17386 // CHECK27-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 4 17387 // CHECK27-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32 17388 // CHECK27-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 17389 // CHECK27-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 17390 // CHECK27-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 4 17391 // CHECK27-NEXT: ret void 17392 // 17393 // 17394 // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142 17395 // CHECK27-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] { 17396 // CHECK27-NEXT: entry: 17397 // CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 17398 // CHECK27-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 17399 // CHECK27-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 17400 // CHECK27-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 17401 // CHECK27-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 17402 // CHECK27-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 17403 // CHECK27-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 17404 // CHECK27-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 17405 // CHECK27-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 17406 // CHECK27-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 17407 // CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 17408 // CHECK27-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 17409 // CHECK27-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 17410 // CHECK27-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 17411 // CHECK27-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 17412 // CHECK27-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 17413 // CHECK27-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 17414 // CHECK27-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 17415 // CHECK27-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 17416 // CHECK27-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 17417 // CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 17418 // CHECK27-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 17419 // CHECK27-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 17420 // CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 17421 // CHECK27-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 17422 // CHECK27-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 17423 // CHECK27-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 17424 // CHECK27-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 17425 // CHECK27-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4 17426 // CHECK27-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4 17427 // CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) 17428 // CHECK27-NEXT: ret void 17429 // 17430 // 17431 // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..3 17432 // CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] { 17433 // CHECK27-NEXT: entry: 17434 // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 17435 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 17436 // CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 17437 // CHECK27-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 17438 // CHECK27-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 17439 // CHECK27-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 17440 // CHECK27-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 17441 // CHECK27-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 17442 // CHECK27-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 17443 // CHECK27-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 17444 // CHECK27-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 17445 // CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 17446 // CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 17447 // CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 17448 // CHECK27-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 17449 // CHECK27-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 17450 // CHECK27-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 17451 // CHECK27-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 17452 // CHECK27-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 17453 // CHECK27-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 17454 // CHECK27-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 17455 // CHECK27-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 17456 // CHECK27-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 17457 // CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 17458 // CHECK27-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 17459 // CHECK27-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 17460 // CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 17461 // CHECK27-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 17462 // CHECK27-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 17463 // CHECK27-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 17464 // CHECK27-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 17465 // CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 17466 // CHECK27-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 17467 // CHECK27-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2 17468 // CHECK27-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 17469 // CHECK27-NEXT: [[CONV:%.*]] = fpext float [[TMP9]] to double 17470 // CHECK27-NEXT: [[ADD5:%.*]] = fadd double [[CONV]], 1.000000e+00 17471 // CHECK27-NEXT: [[CONV6:%.*]] = fptrunc double [[ADD5]] to float 17472 // CHECK27-NEXT: store float [[CONV6]], float* [[ARRAYIDX]], align 4 17473 // CHECK27-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3 17474 // CHECK27-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX7]], align 4 17475 // CHECK27-NEXT: [[CONV8:%.*]] = fpext float [[TMP10]] to double 17476 // CHECK27-NEXT: [[ADD9:%.*]] = fadd double [[CONV8]], 1.000000e+00 17477 // CHECK27-NEXT: [[CONV10:%.*]] = fptrunc double [[ADD9]] to float 17478 // CHECK27-NEXT: store float [[CONV10]], float* [[ARRAYIDX7]], align 4 17479 // CHECK27-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1 17480 // CHECK27-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX11]], i32 0, i32 2 17481 // CHECK27-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX12]], align 8 17482 // CHECK27-NEXT: [[ADD13:%.*]] = fadd double [[TMP11]], 1.000000e+00 17483 // CHECK27-NEXT: store double [[ADD13]], double* [[ARRAYIDX12]], align 8 17484 // CHECK27-NEXT: [[TMP12:%.*]] = mul nsw i32 1, [[TMP5]] 17485 // CHECK27-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP12]] 17486 // CHECK27-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX14]], i32 3 17487 // CHECK27-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX15]], align 8 17488 // CHECK27-NEXT: [[ADD16:%.*]] = fadd double [[TMP13]], 1.000000e+00 17489 // CHECK27-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8 17490 // CHECK27-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 17491 // CHECK27-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 4 17492 // CHECK27-NEXT: [[ADD17:%.*]] = add nsw i64 [[TMP14]], 1 17493 // CHECK27-NEXT: store i64 [[ADD17]], i64* [[X]], align 4 17494 // CHECK27-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 17495 // CHECK27-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 4 17496 // CHECK27-NEXT: [[CONV18:%.*]] = sext i8 [[TMP15]] to i32 17497 // CHECK27-NEXT: [[ADD19:%.*]] = add nsw i32 [[CONV18]], 1 17498 // CHECK27-NEXT: [[CONV20:%.*]] = trunc i32 [[ADD19]] to i8 17499 // CHECK27-NEXT: store i8 [[CONV20]], i8* [[Y]], align 4 17500 // CHECK27-NEXT: ret void 17501 // 17502 // 17503 // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154 17504 // CHECK27-SAME: (i32 [[NN:%.*]]) #[[ATTR0]] { 17505 // CHECK27-NEXT: entry: 17506 // CHECK27-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 17507 // CHECK27-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4 17508 // CHECK27-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 17509 // CHECK27-NEXT: [[TMP0:%.*]] = load i32, i32* [[NN_ADDR]], align 4 17510 // CHECK27-NEXT: store i32 [[TMP0]], i32* [[NN_CASTED]], align 4 17511 // CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[NN_CASTED]], align 4 17512 // CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP1]]) 17513 // CHECK27-NEXT: ret void 17514 // 17515 // 17516 // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..4 17517 // CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[NN:%.*]]) #[[ATTR0]] { 17518 // CHECK27-NEXT: entry: 17519 // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 17520 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 17521 // CHECK27-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 17522 // CHECK27-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4 17523 // CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 17524 // CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 17525 // CHECK27-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 17526 // CHECK27-NEXT: [[TMP0:%.*]] = load i32, i32* [[NN_ADDR]], align 4 17527 // CHECK27-NEXT: store i32 [[TMP0]], i32* [[NN_CASTED]], align 4 17528 // CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[NN_CASTED]], align 4 17529 // CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP1]]) 17530 // CHECK27-NEXT: ret void 17531 // 17532 // 17533 // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..5 17534 // CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[NN:%.*]]) #[[ATTR0]] { 17535 // CHECK27-NEXT: entry: 17536 // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 17537 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 17538 // CHECK27-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 17539 // CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 17540 // CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 17541 // CHECK27-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 17542 // CHECK27-NEXT: ret void 17543 // 17544 // 17545 // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157 17546 // CHECK27-SAME: (i32 [[NN:%.*]]) #[[ATTR0]] { 17547 // CHECK27-NEXT: entry: 17548 // CHECK27-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 17549 // CHECK27-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4 17550 // CHECK27-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 17551 // CHECK27-NEXT: [[TMP0:%.*]] = load i32, i32* [[NN_ADDR]], align 4 17552 // CHECK27-NEXT: store i32 [[TMP0]], i32* [[NN_CASTED]], align 4 17553 // CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[NN_CASTED]], align 4 17554 // CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP1]]) 17555 // CHECK27-NEXT: ret void 17556 // 17557 // 17558 // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..6 17559 // CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[NN:%.*]]) #[[ATTR0]] { 17560 // CHECK27-NEXT: entry: 17561 // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 17562 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 17563 // CHECK27-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 17564 // CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 17565 // CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 17566 // CHECK27-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 17567 // CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32* [[NN_ADDR]]) 17568 // CHECK27-NEXT: ret void 17569 // 17570 // 17571 // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..7 17572 // CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[NN:%.*]]) #[[ATTR0]] { 17573 // CHECK27-NEXT: entry: 17574 // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 17575 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 17576 // CHECK27-NEXT: [[NN_ADDR:%.*]] = alloca i32*, align 4 17577 // CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 17578 // CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 17579 // CHECK27-NEXT: store i32* [[NN]], i32** [[NN_ADDR]], align 4 17580 // CHECK27-NEXT: [[TMP0:%.*]] = load i32*, i32** [[NN_ADDR]], align 4 17581 // CHECK27-NEXT: ret void 17582 // 17583 // 17584 // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182 17585 // CHECK27-SAME: (i32 [[VLA:%.*]]) #[[ATTR0]] { 17586 // CHECK27-NEXT: entry: 17587 // CHECK27-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 17588 // CHECK27-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 17589 // CHECK27-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 17590 // CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..8 to void (i32*, i32*, ...)*), i32 [[TMP0]]) 17591 // CHECK27-NEXT: ret void 17592 // 17593 // 17594 // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..8 17595 // CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[VLA:%.*]]) #[[ATTR0]] { 17596 // CHECK27-NEXT: entry: 17597 // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 17598 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 17599 // CHECK27-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 17600 // CHECK27-NEXT: [[F:%.*]] = alloca i32*, align 4 17601 // CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 17602 // CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 17603 // CHECK27-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 17604 // CHECK27-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 17605 // CHECK27-NEXT: ret void 17606 // 17607 // 17608 // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209 17609 // CHECK27-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 17610 // CHECK27-NEXT: entry: 17611 // CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 17612 // CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 17613 // CHECK27-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 17614 // CHECK27-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 17615 // CHECK27-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 17616 // CHECK27-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 17617 // CHECK27-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 17618 // CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 17619 // CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 17620 // CHECK27-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 17621 // CHECK27-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 17622 // CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 17623 // CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 17624 // CHECK27-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 17625 // CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 17626 // CHECK27-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 17627 // CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 17628 // CHECK27-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 17629 // CHECK27-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 17630 // CHECK27-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 17631 // CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 17632 // CHECK27-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 4 17633 // CHECK27-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* 17634 // CHECK27-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 17635 // CHECK27-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 17636 // CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) 17637 // CHECK27-NEXT: ret void 17638 // 17639 // 17640 // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..9 17641 // CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 17642 // CHECK27-NEXT: entry: 17643 // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 17644 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 17645 // CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 17646 // CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 17647 // CHECK27-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 17648 // CHECK27-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 17649 // CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 17650 // CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 17651 // CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 17652 // CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 17653 // CHECK27-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 17654 // CHECK27-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 17655 // CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 17656 // CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 17657 // CHECK27-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 17658 // CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 17659 // CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 17660 // CHECK27-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 17661 // CHECK27-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 17662 // CHECK27-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 17663 // CHECK27-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 17664 // CHECK27-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 17665 // CHECK27-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 4 17666 // CHECK27-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 4 17667 // CHECK27-NEXT: [[CONV5:%.*]] = sext i8 [[TMP3]] to i32 17668 // CHECK27-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 17669 // CHECK27-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i8 17670 // CHECK27-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 4 17671 // CHECK27-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 17672 // CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 17673 // CHECK27-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP4]], 1 17674 // CHECK27-NEXT: store i32 [[ADD8]], i32* [[ARRAYIDX]], align 4 17675 // CHECK27-NEXT: ret void 17676 // 17677 // 17678 // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227 17679 // CHECK27-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { 17680 // CHECK27-NEXT: entry: 17681 // CHECK27-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 17682 // CHECK27-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 17683 // CHECK27-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 17684 // CHECK27-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 17685 // CHECK27-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 17686 // CHECK27-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 17687 // CHECK27-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 17688 // CHECK27-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 17689 // CHECK27-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 17690 // CHECK27-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 17691 // CHECK27-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 17692 // CHECK27-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 17693 // CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 17694 // CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 17695 // CHECK27-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 17696 // CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 17697 // CHECK27-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 17698 // CHECK27-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 17699 // CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]]) 17700 // CHECK27-NEXT: ret void 17701 // 17702 // 17703 // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..10 17704 // CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { 17705 // CHECK27-NEXT: entry: 17706 // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 17707 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 17708 // CHECK27-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 17709 // CHECK27-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 17710 // CHECK27-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 17711 // CHECK27-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 17712 // CHECK27-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 17713 // CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 17714 // CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 17715 // CHECK27-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 17716 // CHECK27-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 17717 // CHECK27-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 17718 // CHECK27-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 17719 // CHECK27-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 17720 // CHECK27-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 17721 // CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 17722 // CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 17723 // CHECK27-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 17724 // CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 17725 // CHECK27-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP4]] to double 17726 // CHECK27-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 17727 // CHECK27-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 17728 // CHECK27-NEXT: store double [[ADD]], double* [[A]], align 4 17729 // CHECK27-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 17730 // CHECK27-NEXT: [[TMP5:%.*]] = load double, double* [[A3]], align 4 17731 // CHECK27-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 17732 // CHECK27-NEXT: store double [[INC]], double* [[A3]], align 4 17733 // CHECK27-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 17734 // CHECK27-NEXT: [[TMP6:%.*]] = mul nsw i32 1, [[TMP2]] 17735 // CHECK27-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP6]] 17736 // CHECK27-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 17737 // CHECK27-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 17738 // CHECK27-NEXT: ret void 17739 // 17740 // 17741 // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192 17742 // CHECK27-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 17743 // CHECK27-NEXT: entry: 17744 // CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 17745 // CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 17746 // CHECK27-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 17747 // CHECK27-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 17748 // CHECK27-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 17749 // CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 17750 // CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 17751 // CHECK27-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 17752 // CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 17753 // CHECK27-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 17754 // CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 17755 // CHECK27-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 17756 // CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 17757 // CHECK27-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 17758 // CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 17759 // CHECK27-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 17760 // CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 17761 // CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) 17762 // CHECK27-NEXT: ret void 17763 // 17764 // 17765 // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..11 17766 // CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 17767 // CHECK27-NEXT: entry: 17768 // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 17769 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 17770 // CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 17771 // CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 17772 // CHECK27-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 17773 // CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 17774 // CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 17775 // CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 17776 // CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 17777 // CHECK27-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 17778 // CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 17779 // CHECK27-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 17780 // CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 17781 // CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 17782 // CHECK27-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 17783 // CHECK27-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 17784 // CHECK27-NEXT: [[CONV1:%.*]] = sext i16 [[TMP2]] to i32 17785 // CHECK27-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 17786 // CHECK27-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 17787 // CHECK27-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 4 17788 // CHECK27-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 17789 // CHECK27-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 17790 // CHECK27-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1 17791 // CHECK27-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4 17792 // CHECK27-NEXT: ret void 17793 // 17794 // 17795 // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101 17796 // CHECK28-SAME: (i32 [[AA:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]], i32 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { 17797 // CHECK28-NEXT: entry: 17798 // CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 17799 // CHECK28-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 17800 // CHECK28-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4 17801 // CHECK28-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 17802 // CHECK28-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) 17803 // CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 17804 // CHECK28-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 17805 // CHECK28-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 17806 // CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 17807 // CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 17808 // CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 17809 // CHECK28-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) 17810 // CHECK28-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 17811 // CHECK28-NEXT: [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 17812 // CHECK28-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 17813 // CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 17814 // CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]]) 17815 // CHECK28-NEXT: ret void 17816 // 17817 // 17818 // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined. 17819 // CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { 17820 // CHECK28-NEXT: entry: 17821 // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 17822 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 17823 // CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 17824 // CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 17825 // CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 17826 // CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 17827 // CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 17828 // CHECK28-NEXT: ret void 17829 // 17830 // 17831 // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 17832 // CHECK28-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] { 17833 // CHECK28-NEXT: entry: 17834 // CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 17835 // CHECK28-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 17836 // CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 17837 // CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 17838 // CHECK28-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 17839 // CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 17840 // CHECK28-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 17841 // CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 17842 // CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]]) 17843 // CHECK28-NEXT: ret void 17844 // 17845 // 17846 // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..1 17847 // CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { 17848 // CHECK28-NEXT: entry: 17849 // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 17850 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 17851 // CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 17852 // CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 17853 // CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 17854 // CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 17855 // CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 17856 // CHECK28-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 17857 // CHECK28-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 17858 // CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 17859 // CHECK28-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 17860 // CHECK28-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 4 17861 // CHECK28-NEXT: ret void 17862 // 17863 // 17864 // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118 17865 // CHECK28-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { 17866 // CHECK28-NEXT: entry: 17867 // CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 17868 // CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 17869 // CHECK28-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 17870 // CHECK28-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 17871 // CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 17872 // CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 17873 // CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 17874 // CHECK28-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 17875 // CHECK28-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 17876 // CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 17877 // CHECK28-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 17878 // CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 17879 // CHECK28-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 17880 // CHECK28-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 17881 // CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) 17882 // CHECK28-NEXT: ret void 17883 // 17884 // 17885 // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..2 17886 // CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { 17887 // CHECK28-NEXT: entry: 17888 // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 17889 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 17890 // CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 17891 // CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 17892 // CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 17893 // CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 17894 // CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 17895 // CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 17896 // CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 17897 // CHECK28-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 17898 // CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 17899 // CHECK28-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 17900 // CHECK28-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 4 17901 // CHECK28-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32 17902 // CHECK28-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 17903 // CHECK28-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 17904 // CHECK28-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 4 17905 // CHECK28-NEXT: ret void 17906 // 17907 // 17908 // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142 17909 // CHECK28-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] { 17910 // CHECK28-NEXT: entry: 17911 // CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 17912 // CHECK28-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 17913 // CHECK28-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 17914 // CHECK28-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 17915 // CHECK28-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 17916 // CHECK28-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 17917 // CHECK28-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 17918 // CHECK28-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 17919 // CHECK28-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 17920 // CHECK28-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 17921 // CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 17922 // CHECK28-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 17923 // CHECK28-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 17924 // CHECK28-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 17925 // CHECK28-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 17926 // CHECK28-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 17927 // CHECK28-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 17928 // CHECK28-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 17929 // CHECK28-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 17930 // CHECK28-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 17931 // CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 17932 // CHECK28-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 17933 // CHECK28-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 17934 // CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 17935 // CHECK28-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 17936 // CHECK28-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 17937 // CHECK28-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 17938 // CHECK28-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 17939 // CHECK28-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4 17940 // CHECK28-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4 17941 // CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) 17942 // CHECK28-NEXT: ret void 17943 // 17944 // 17945 // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..3 17946 // CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] { 17947 // CHECK28-NEXT: entry: 17948 // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 17949 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 17950 // CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 17951 // CHECK28-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 17952 // CHECK28-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 17953 // CHECK28-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 17954 // CHECK28-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 17955 // CHECK28-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 17956 // CHECK28-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 17957 // CHECK28-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 17958 // CHECK28-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 17959 // CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 17960 // CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 17961 // CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 17962 // CHECK28-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 17963 // CHECK28-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 17964 // CHECK28-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 17965 // CHECK28-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 17966 // CHECK28-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 17967 // CHECK28-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 17968 // CHECK28-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 17969 // CHECK28-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 17970 // CHECK28-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 17971 // CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 17972 // CHECK28-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 17973 // CHECK28-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 17974 // CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 17975 // CHECK28-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 17976 // CHECK28-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 17977 // CHECK28-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 17978 // CHECK28-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 17979 // CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 17980 // CHECK28-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 17981 // CHECK28-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2 17982 // CHECK28-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 17983 // CHECK28-NEXT: [[CONV:%.*]] = fpext float [[TMP9]] to double 17984 // CHECK28-NEXT: [[ADD5:%.*]] = fadd double [[CONV]], 1.000000e+00 17985 // CHECK28-NEXT: [[CONV6:%.*]] = fptrunc double [[ADD5]] to float 17986 // CHECK28-NEXT: store float [[CONV6]], float* [[ARRAYIDX]], align 4 17987 // CHECK28-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3 17988 // CHECK28-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX7]], align 4 17989 // CHECK28-NEXT: [[CONV8:%.*]] = fpext float [[TMP10]] to double 17990 // CHECK28-NEXT: [[ADD9:%.*]] = fadd double [[CONV8]], 1.000000e+00 17991 // CHECK28-NEXT: [[CONV10:%.*]] = fptrunc double [[ADD9]] to float 17992 // CHECK28-NEXT: store float [[CONV10]], float* [[ARRAYIDX7]], align 4 17993 // CHECK28-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1 17994 // CHECK28-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX11]], i32 0, i32 2 17995 // CHECK28-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX12]], align 8 17996 // CHECK28-NEXT: [[ADD13:%.*]] = fadd double [[TMP11]], 1.000000e+00 17997 // CHECK28-NEXT: store double [[ADD13]], double* [[ARRAYIDX12]], align 8 17998 // CHECK28-NEXT: [[TMP12:%.*]] = mul nsw i32 1, [[TMP5]] 17999 // CHECK28-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP12]] 18000 // CHECK28-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX14]], i32 3 18001 // CHECK28-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX15]], align 8 18002 // CHECK28-NEXT: [[ADD16:%.*]] = fadd double [[TMP13]], 1.000000e+00 18003 // CHECK28-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8 18004 // CHECK28-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 18005 // CHECK28-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 4 18006 // CHECK28-NEXT: [[ADD17:%.*]] = add nsw i64 [[TMP14]], 1 18007 // CHECK28-NEXT: store i64 [[ADD17]], i64* [[X]], align 4 18008 // CHECK28-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 18009 // CHECK28-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 4 18010 // CHECK28-NEXT: [[CONV18:%.*]] = sext i8 [[TMP15]] to i32 18011 // CHECK28-NEXT: [[ADD19:%.*]] = add nsw i32 [[CONV18]], 1 18012 // CHECK28-NEXT: [[CONV20:%.*]] = trunc i32 [[ADD19]] to i8 18013 // CHECK28-NEXT: store i8 [[CONV20]], i8* [[Y]], align 4 18014 // CHECK28-NEXT: ret void 18015 // 18016 // 18017 // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154 18018 // CHECK28-SAME: (i32 [[NN:%.*]]) #[[ATTR0]] { 18019 // CHECK28-NEXT: entry: 18020 // CHECK28-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 18021 // CHECK28-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4 18022 // CHECK28-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 18023 // CHECK28-NEXT: [[TMP0:%.*]] = load i32, i32* [[NN_ADDR]], align 4 18024 // CHECK28-NEXT: store i32 [[TMP0]], i32* [[NN_CASTED]], align 4 18025 // CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[NN_CASTED]], align 4 18026 // CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP1]]) 18027 // CHECK28-NEXT: ret void 18028 // 18029 // 18030 // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..4 18031 // CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[NN:%.*]]) #[[ATTR0]] { 18032 // CHECK28-NEXT: entry: 18033 // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 18034 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 18035 // CHECK28-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 18036 // CHECK28-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4 18037 // CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 18038 // CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 18039 // CHECK28-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 18040 // CHECK28-NEXT: [[TMP0:%.*]] = load i32, i32* [[NN_ADDR]], align 4 18041 // CHECK28-NEXT: store i32 [[TMP0]], i32* [[NN_CASTED]], align 4 18042 // CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[NN_CASTED]], align 4 18043 // CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP1]]) 18044 // CHECK28-NEXT: ret void 18045 // 18046 // 18047 // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..5 18048 // CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[NN:%.*]]) #[[ATTR0]] { 18049 // CHECK28-NEXT: entry: 18050 // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 18051 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 18052 // CHECK28-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 18053 // CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 18054 // CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 18055 // CHECK28-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 18056 // CHECK28-NEXT: ret void 18057 // 18058 // 18059 // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157 18060 // CHECK28-SAME: (i32 [[NN:%.*]]) #[[ATTR0]] { 18061 // CHECK28-NEXT: entry: 18062 // CHECK28-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 18063 // CHECK28-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4 18064 // CHECK28-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 18065 // CHECK28-NEXT: [[TMP0:%.*]] = load i32, i32* [[NN_ADDR]], align 4 18066 // CHECK28-NEXT: store i32 [[TMP0]], i32* [[NN_CASTED]], align 4 18067 // CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[NN_CASTED]], align 4 18068 // CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP1]]) 18069 // CHECK28-NEXT: ret void 18070 // 18071 // 18072 // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..6 18073 // CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[NN:%.*]]) #[[ATTR0]] { 18074 // CHECK28-NEXT: entry: 18075 // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 18076 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 18077 // CHECK28-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 18078 // CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 18079 // CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 18080 // CHECK28-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 18081 // CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32* [[NN_ADDR]]) 18082 // CHECK28-NEXT: ret void 18083 // 18084 // 18085 // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..7 18086 // CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[NN:%.*]]) #[[ATTR0]] { 18087 // CHECK28-NEXT: entry: 18088 // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 18089 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 18090 // CHECK28-NEXT: [[NN_ADDR:%.*]] = alloca i32*, align 4 18091 // CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 18092 // CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 18093 // CHECK28-NEXT: store i32* [[NN]], i32** [[NN_ADDR]], align 4 18094 // CHECK28-NEXT: [[TMP0:%.*]] = load i32*, i32** [[NN_ADDR]], align 4 18095 // CHECK28-NEXT: ret void 18096 // 18097 // 18098 // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182 18099 // CHECK28-SAME: (i32 [[VLA:%.*]]) #[[ATTR0]] { 18100 // CHECK28-NEXT: entry: 18101 // CHECK28-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 18102 // CHECK28-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 18103 // CHECK28-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 18104 // CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..8 to void (i32*, i32*, ...)*), i32 [[TMP0]]) 18105 // CHECK28-NEXT: ret void 18106 // 18107 // 18108 // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..8 18109 // CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[VLA:%.*]]) #[[ATTR0]] { 18110 // CHECK28-NEXT: entry: 18111 // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 18112 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 18113 // CHECK28-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 18114 // CHECK28-NEXT: [[F:%.*]] = alloca i32*, align 4 18115 // CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 18116 // CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 18117 // CHECK28-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 18118 // CHECK28-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 18119 // CHECK28-NEXT: ret void 18120 // 18121 // 18122 // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209 18123 // CHECK28-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 18124 // CHECK28-NEXT: entry: 18125 // CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 18126 // CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 18127 // CHECK28-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 18128 // CHECK28-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 18129 // CHECK28-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 18130 // CHECK28-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 18131 // CHECK28-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 18132 // CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 18133 // CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 18134 // CHECK28-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 18135 // CHECK28-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 18136 // CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 18137 // CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 18138 // CHECK28-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 18139 // CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 18140 // CHECK28-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 18141 // CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 18142 // CHECK28-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 18143 // CHECK28-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 18144 // CHECK28-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 18145 // CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 18146 // CHECK28-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 4 18147 // CHECK28-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* 18148 // CHECK28-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 18149 // CHECK28-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 18150 // CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) 18151 // CHECK28-NEXT: ret void 18152 // 18153 // 18154 // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..9 18155 // CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 18156 // CHECK28-NEXT: entry: 18157 // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 18158 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 18159 // CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 18160 // CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 18161 // CHECK28-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 18162 // CHECK28-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 18163 // CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 18164 // CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 18165 // CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 18166 // CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 18167 // CHECK28-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 18168 // CHECK28-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 18169 // CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 18170 // CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 18171 // CHECK28-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 18172 // CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 18173 // CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 18174 // CHECK28-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 18175 // CHECK28-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 18176 // CHECK28-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 18177 // CHECK28-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 18178 // CHECK28-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 18179 // CHECK28-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 4 18180 // CHECK28-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 4 18181 // CHECK28-NEXT: [[CONV5:%.*]] = sext i8 [[TMP3]] to i32 18182 // CHECK28-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 18183 // CHECK28-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i8 18184 // CHECK28-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 4 18185 // CHECK28-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 18186 // CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 18187 // CHECK28-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP4]], 1 18188 // CHECK28-NEXT: store i32 [[ADD8]], i32* [[ARRAYIDX]], align 4 18189 // CHECK28-NEXT: ret void 18190 // 18191 // 18192 // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227 18193 // CHECK28-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { 18194 // CHECK28-NEXT: entry: 18195 // CHECK28-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 18196 // CHECK28-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 18197 // CHECK28-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 18198 // CHECK28-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 18199 // CHECK28-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 18200 // CHECK28-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 18201 // CHECK28-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 18202 // CHECK28-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 18203 // CHECK28-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 18204 // CHECK28-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 18205 // CHECK28-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 18206 // CHECK28-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 18207 // CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 18208 // CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 18209 // CHECK28-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 18210 // CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 18211 // CHECK28-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 18212 // CHECK28-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 18213 // CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]]) 18214 // CHECK28-NEXT: ret void 18215 // 18216 // 18217 // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..10 18218 // CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { 18219 // CHECK28-NEXT: entry: 18220 // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 18221 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 18222 // CHECK28-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 18223 // CHECK28-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 18224 // CHECK28-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 18225 // CHECK28-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 18226 // CHECK28-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 18227 // CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 18228 // CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 18229 // CHECK28-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 18230 // CHECK28-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 18231 // CHECK28-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 18232 // CHECK28-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 18233 // CHECK28-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 18234 // CHECK28-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 18235 // CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 18236 // CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 18237 // CHECK28-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 18238 // CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 18239 // CHECK28-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP4]] to double 18240 // CHECK28-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 18241 // CHECK28-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 18242 // CHECK28-NEXT: store double [[ADD]], double* [[A]], align 4 18243 // CHECK28-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 18244 // CHECK28-NEXT: [[TMP5:%.*]] = load double, double* [[A3]], align 4 18245 // CHECK28-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 18246 // CHECK28-NEXT: store double [[INC]], double* [[A3]], align 4 18247 // CHECK28-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 18248 // CHECK28-NEXT: [[TMP6:%.*]] = mul nsw i32 1, [[TMP2]] 18249 // CHECK28-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP6]] 18250 // CHECK28-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 18251 // CHECK28-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 18252 // CHECK28-NEXT: ret void 18253 // 18254 // 18255 // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192 18256 // CHECK28-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 18257 // CHECK28-NEXT: entry: 18258 // CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 18259 // CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 18260 // CHECK28-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 18261 // CHECK28-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 18262 // CHECK28-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 18263 // CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 18264 // CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 18265 // CHECK28-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 18266 // CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 18267 // CHECK28-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 18268 // CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 18269 // CHECK28-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 18270 // CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 18271 // CHECK28-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4 18272 // CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 18273 // CHECK28-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 18274 // CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 18275 // CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) 18276 // CHECK28-NEXT: ret void 18277 // 18278 // 18279 // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..11 18280 // CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 18281 // CHECK28-NEXT: entry: 18282 // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 18283 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 18284 // CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 18285 // CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 18286 // CHECK28-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 18287 // CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 18288 // CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 18289 // CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 18290 // CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 18291 // CHECK28-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 18292 // CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 18293 // CHECK28-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 18294 // CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 18295 // CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 18296 // CHECK28-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 18297 // CHECK28-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 18298 // CHECK28-NEXT: [[CONV1:%.*]] = sext i16 [[TMP2]] to i32 18299 // CHECK28-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 18300 // CHECK28-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 18301 // CHECK28-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 4 18302 // CHECK28-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 18303 // CHECK28-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 18304 // CHECK28-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1 18305 // CHECK28-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4 18306 // CHECK28-NEXT: ret void 18307 // 18308 // 18309 // CHECK29-LABEL: define {{[^@]+}}@_Z3fooi 18310 // CHECK29-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { 18311 // CHECK29-NEXT: entry: 18312 // CHECK29-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 18313 // CHECK29-NEXT: [[A:%.*]] = alloca i32, align 4 18314 // CHECK29-NEXT: [[AA:%.*]] = alloca i16, align 2 18315 // CHECK29-NEXT: [[B:%.*]] = alloca [10 x float], align 4 18316 // CHECK29-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 18317 // CHECK29-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 18318 // CHECK29-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 18319 // CHECK29-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 18320 // CHECK29-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 18321 // CHECK29-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 18322 // CHECK29-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 18323 // CHECK29-NEXT: [[NN:%.*]] = alloca i32, align 4 18324 // CHECK29-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 18325 // CHECK29-NEXT: store i32 0, i32* [[A]], align 4 18326 // CHECK29-NEXT: store i16 0, i16* [[AA]], align 2 18327 // CHECK29-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 18328 // CHECK29-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 18329 // CHECK29-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() 18330 // CHECK29-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 18331 // CHECK29-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4 18332 // CHECK29-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 18333 // CHECK29-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 18334 // CHECK29-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64 18335 // CHECK29-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]] 18336 // CHECK29-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8 18337 // CHECK29-NEXT: store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8 18338 // CHECK29-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 18339 // CHECK29-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_]], align 4 18340 // CHECK29-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 18341 // CHECK29-NEXT: store i32 [[TMP7]], i32* [[DOTCAPTURE_EXPR_2]], align 4 18342 // CHECK29-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 18343 // CHECK29-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 18344 // CHECK29-NEXT: store i32 [[ADD]], i32* [[A]], align 4 18345 // CHECK29-NEXT: [[TMP9:%.*]] = load i16, i16* [[AA]], align 2 18346 // CHECK29-NEXT: [[CONV:%.*]] = sext i16 [[TMP9]] to i32 18347 // CHECK29-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1 18348 // CHECK29-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 18349 // CHECK29-NEXT: store i16 [[CONV4]], i16* [[AA]], align 2 18350 // CHECK29-NEXT: [[TMP10:%.*]] = load i32, i32* [[A]], align 4 18351 // CHECK29-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP10]], 1 18352 // CHECK29-NEXT: store i32 [[ADD5]], i32* [[A]], align 4 18353 // CHECK29-NEXT: [[TMP11:%.*]] = load i16, i16* [[AA]], align 2 18354 // CHECK29-NEXT: [[CONV6:%.*]] = sext i16 [[TMP11]] to i32 18355 // CHECK29-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 18356 // CHECK29-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i16 18357 // CHECK29-NEXT: store i16 [[CONV8]], i16* [[AA]], align 2 18358 // CHECK29-NEXT: [[TMP12:%.*]] = load i32, i32* [[A]], align 4 18359 // CHECK29-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP12]], 1 18360 // CHECK29-NEXT: store i32 [[ADD9]], i32* [[A]], align 4 18361 // CHECK29-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2 18362 // CHECK29-NEXT: [[TMP13:%.*]] = load float, float* [[ARRAYIDX]], align 4 18363 // CHECK29-NEXT: [[CONV10:%.*]] = fpext float [[TMP13]] to double 18364 // CHECK29-NEXT: [[ADD11:%.*]] = fadd double [[CONV10]], 1.000000e+00 18365 // CHECK29-NEXT: [[CONV12:%.*]] = fptrunc double [[ADD11]] to float 18366 // CHECK29-NEXT: store float [[CONV12]], float* [[ARRAYIDX]], align 4 18367 // CHECK29-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3 18368 // CHECK29-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX13]], align 4 18369 // CHECK29-NEXT: [[CONV14:%.*]] = fpext float [[TMP14]] to double 18370 // CHECK29-NEXT: [[ADD15:%.*]] = fadd double [[CONV14]], 1.000000e+00 18371 // CHECK29-NEXT: [[CONV16:%.*]] = fptrunc double [[ADD15]] to float 18372 // CHECK29-NEXT: store float [[CONV16]], float* [[ARRAYIDX13]], align 4 18373 // CHECK29-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1 18374 // CHECK29-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX17]], i64 0, i64 2 18375 // CHECK29-NEXT: [[TMP15:%.*]] = load double, double* [[ARRAYIDX18]], align 8 18376 // CHECK29-NEXT: [[ADD19:%.*]] = fadd double [[TMP15]], 1.000000e+00 18377 // CHECK29-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8 18378 // CHECK29-NEXT: [[TMP16:%.*]] = mul nsw i64 1, [[TMP4]] 18379 // CHECK29-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP16]] 18380 // CHECK29-NEXT: [[ARRAYIDX21:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX20]], i64 3 18381 // CHECK29-NEXT: [[TMP17:%.*]] = load double, double* [[ARRAYIDX21]], align 8 18382 // CHECK29-NEXT: [[ADD22:%.*]] = fadd double [[TMP17]], 1.000000e+00 18383 // CHECK29-NEXT: store double [[ADD22]], double* [[ARRAYIDX21]], align 8 18384 // CHECK29-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 18385 // CHECK29-NEXT: [[TMP18:%.*]] = load i64, i64* [[X]], align 8 18386 // CHECK29-NEXT: [[ADD23:%.*]] = add nsw i64 [[TMP18]], 1 18387 // CHECK29-NEXT: store i64 [[ADD23]], i64* [[X]], align 8 18388 // CHECK29-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 18389 // CHECK29-NEXT: [[TMP19:%.*]] = load i8, i8* [[Y]], align 8 18390 // CHECK29-NEXT: [[CONV24:%.*]] = sext i8 [[TMP19]] to i32 18391 // CHECK29-NEXT: [[ADD25:%.*]] = add nsw i32 [[CONV24]], 1 18392 // CHECK29-NEXT: [[CONV26:%.*]] = trunc i32 [[ADD25]] to i8 18393 // CHECK29-NEXT: store i8 [[CONV26]], i8* [[Y]], align 8 18394 // CHECK29-NEXT: store i32 0, i32* [[NN]], align 4 18395 // CHECK29-NEXT: [[TMP20:%.*]] = load i32, i32* [[A]], align 4 18396 // CHECK29-NEXT: [[TMP21:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 18397 // CHECK29-NEXT: call void @llvm.stackrestore(i8* [[TMP21]]) 18398 // CHECK29-NEXT: ret i32 [[TMP20]] 18399 // 18400 // 18401 // CHECK29-LABEL: define {{[^@]+}}@_Z6bazzzziPi 18402 // CHECK29-SAME: (i32 signext [[N:%.*]], i32* [[F:%.*]]) #[[ATTR0]] { 18403 // CHECK29-NEXT: entry: 18404 // CHECK29-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 18405 // CHECK29-NEXT: [[F_ADDR:%.*]] = alloca i32*, align 8 18406 // CHECK29-NEXT: [[F1:%.*]] = alloca i32*, align 8 18407 // CHECK29-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 18408 // CHECK29-NEXT: store i32* [[F]], i32** [[F_ADDR]], align 8 18409 // CHECK29-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 18410 // CHECK29-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 18411 // CHECK29-NEXT: ret void 18412 // 18413 // 18414 // CHECK29-LABEL: define {{[^@]+}}@_Z3bari 18415 // CHECK29-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { 18416 // CHECK29-NEXT: entry: 18417 // CHECK29-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 18418 // CHECK29-NEXT: [[A:%.*]] = alloca i32, align 4 18419 // CHECK29-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 18420 // CHECK29-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 18421 // CHECK29-NEXT: store i32 0, i32* [[A]], align 4 18422 // CHECK29-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 18423 // CHECK29-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]]) 18424 // CHECK29-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 18425 // CHECK29-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 18426 // CHECK29-NEXT: store i32 [[ADD]], i32* [[A]], align 4 18427 // CHECK29-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 18428 // CHECK29-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]]) 18429 // CHECK29-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 18430 // CHECK29-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 18431 // CHECK29-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 18432 // CHECK29-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 18433 // CHECK29-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]]) 18434 // CHECK29-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 18435 // CHECK29-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 18436 // CHECK29-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 18437 // CHECK29-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 18438 // CHECK29-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]]) 18439 // CHECK29-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 18440 // CHECK29-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] 18441 // CHECK29-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 18442 // CHECK29-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 18443 // CHECK29-NEXT: ret i32 [[TMP8]] 18444 // 18445 // 18446 // CHECK29-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 18447 // CHECK29-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { 18448 // CHECK29-NEXT: entry: 18449 // CHECK29-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 18450 // CHECK29-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 18451 // CHECK29-NEXT: [[B:%.*]] = alloca i32, align 4 18452 // CHECK29-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 18453 // CHECK29-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 18454 // CHECK29-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 18455 // CHECK29-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 18456 // CHECK29-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 18457 // CHECK29-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 18458 // CHECK29-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 18459 // CHECK29-NEXT: store i32 [[ADD]], i32* [[B]], align 4 18460 // CHECK29-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 18461 // CHECK29-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 18462 // CHECK29-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() 18463 // CHECK29-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 18464 // CHECK29-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] 18465 // CHECK29-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 18466 // CHECK29-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 18467 // CHECK29-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 18468 // CHECK29-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP5]] to double 18469 // CHECK29-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 18470 // CHECK29-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 18471 // CHECK29-NEXT: store double [[ADD2]], double* [[A]], align 8 18472 // CHECK29-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 18473 // CHECK29-NEXT: [[TMP6:%.*]] = load double, double* [[A3]], align 8 18474 // CHECK29-NEXT: [[INC:%.*]] = fadd double [[TMP6]], 1.000000e+00 18475 // CHECK29-NEXT: store double [[INC]], double* [[A3]], align 8 18476 // CHECK29-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 18477 // CHECK29-NEXT: [[TMP7:%.*]] = mul nsw i64 1, [[TMP2]] 18478 // CHECK29-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP7]] 18479 // CHECK29-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 18480 // CHECK29-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 18481 // CHECK29-NEXT: [[TMP8:%.*]] = mul nsw i64 1, [[TMP2]] 18482 // CHECK29-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP8]] 18483 // CHECK29-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i64 1 18484 // CHECK29-NEXT: [[TMP9:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2 18485 // CHECK29-NEXT: [[CONV8:%.*]] = sext i16 [[TMP9]] to i32 18486 // CHECK29-NEXT: [[TMP10:%.*]] = load i32, i32* [[B]], align 4 18487 // CHECK29-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP10]] 18488 // CHECK29-NEXT: [[TMP11:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 18489 // CHECK29-NEXT: call void @llvm.stackrestore(i8* [[TMP11]]) 18490 // CHECK29-NEXT: ret i32 [[ADD9]] 18491 // 18492 // 18493 // CHECK29-LABEL: define {{[^@]+}}@_ZL7fstatici 18494 // CHECK29-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { 18495 // CHECK29-NEXT: entry: 18496 // CHECK29-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 18497 // CHECK29-NEXT: [[A:%.*]] = alloca i32, align 4 18498 // CHECK29-NEXT: [[AA:%.*]] = alloca i16, align 2 18499 // CHECK29-NEXT: [[AAA:%.*]] = alloca i8, align 1 18500 // CHECK29-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 18501 // CHECK29-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 18502 // CHECK29-NEXT: store i32 0, i32* [[A]], align 4 18503 // CHECK29-NEXT: store i16 0, i16* [[AA]], align 2 18504 // CHECK29-NEXT: store i8 0, i8* [[AAA]], align 1 18505 // CHECK29-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 18506 // CHECK29-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 18507 // CHECK29-NEXT: store i32 [[ADD]], i32* [[A]], align 4 18508 // CHECK29-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 18509 // CHECK29-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 18510 // CHECK29-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 18511 // CHECK29-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 18512 // CHECK29-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 18513 // CHECK29-NEXT: [[TMP2:%.*]] = load i8, i8* [[AAA]], align 1 18514 // CHECK29-NEXT: [[CONV3:%.*]] = sext i8 [[TMP2]] to i32 18515 // CHECK29-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 18516 // CHECK29-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 18517 // CHECK29-NEXT: store i8 [[CONV5]], i8* [[AAA]], align 1 18518 // CHECK29-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 18519 // CHECK29-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 18520 // CHECK29-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP3]], 1 18521 // CHECK29-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 18522 // CHECK29-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 18523 // CHECK29-NEXT: ret i32 [[TMP4]] 18524 // 18525 // 18526 // CHECK29-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 18527 // CHECK29-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { 18528 // CHECK29-NEXT: entry: 18529 // CHECK29-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 18530 // CHECK29-NEXT: [[A:%.*]] = alloca i32, align 4 18531 // CHECK29-NEXT: [[AA:%.*]] = alloca i16, align 2 18532 // CHECK29-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 18533 // CHECK29-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 18534 // CHECK29-NEXT: store i32 0, i32* [[A]], align 4 18535 // CHECK29-NEXT: store i16 0, i16* [[AA]], align 2 18536 // CHECK29-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 18537 // CHECK29-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 18538 // CHECK29-NEXT: store i32 [[ADD]], i32* [[A]], align 4 18539 // CHECK29-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 18540 // CHECK29-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 18541 // CHECK29-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 18542 // CHECK29-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 18543 // CHECK29-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 18544 // CHECK29-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 18545 // CHECK29-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 18546 // CHECK29-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP2]], 1 18547 // CHECK29-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 18548 // CHECK29-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 18549 // CHECK29-NEXT: ret i32 [[TMP3]] 18550 // 18551 // 18552 // CHECK30-LABEL: define {{[^@]+}}@_Z3fooi 18553 // CHECK30-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { 18554 // CHECK30-NEXT: entry: 18555 // CHECK30-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 18556 // CHECK30-NEXT: [[A:%.*]] = alloca i32, align 4 18557 // CHECK30-NEXT: [[AA:%.*]] = alloca i16, align 2 18558 // CHECK30-NEXT: [[B:%.*]] = alloca [10 x float], align 4 18559 // CHECK30-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 18560 // CHECK30-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 18561 // CHECK30-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 18562 // CHECK30-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 18563 // CHECK30-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 18564 // CHECK30-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 18565 // CHECK30-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 18566 // CHECK30-NEXT: [[NN:%.*]] = alloca i32, align 4 18567 // CHECK30-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 18568 // CHECK30-NEXT: store i32 0, i32* [[A]], align 4 18569 // CHECK30-NEXT: store i16 0, i16* [[AA]], align 2 18570 // CHECK30-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 18571 // CHECK30-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 18572 // CHECK30-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() 18573 // CHECK30-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 18574 // CHECK30-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4 18575 // CHECK30-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 18576 // CHECK30-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 18577 // CHECK30-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64 18578 // CHECK30-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]] 18579 // CHECK30-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8 18580 // CHECK30-NEXT: store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8 18581 // CHECK30-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 18582 // CHECK30-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_]], align 4 18583 // CHECK30-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 18584 // CHECK30-NEXT: store i32 [[TMP7]], i32* [[DOTCAPTURE_EXPR_2]], align 4 18585 // CHECK30-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 18586 // CHECK30-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 18587 // CHECK30-NEXT: store i32 [[ADD]], i32* [[A]], align 4 18588 // CHECK30-NEXT: [[TMP9:%.*]] = load i16, i16* [[AA]], align 2 18589 // CHECK30-NEXT: [[CONV:%.*]] = sext i16 [[TMP9]] to i32 18590 // CHECK30-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1 18591 // CHECK30-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 18592 // CHECK30-NEXT: store i16 [[CONV4]], i16* [[AA]], align 2 18593 // CHECK30-NEXT: [[TMP10:%.*]] = load i32, i32* [[A]], align 4 18594 // CHECK30-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP10]], 1 18595 // CHECK30-NEXT: store i32 [[ADD5]], i32* [[A]], align 4 18596 // CHECK30-NEXT: [[TMP11:%.*]] = load i16, i16* [[AA]], align 2 18597 // CHECK30-NEXT: [[CONV6:%.*]] = sext i16 [[TMP11]] to i32 18598 // CHECK30-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 18599 // CHECK30-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i16 18600 // CHECK30-NEXT: store i16 [[CONV8]], i16* [[AA]], align 2 18601 // CHECK30-NEXT: [[TMP12:%.*]] = load i32, i32* [[A]], align 4 18602 // CHECK30-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP12]], 1 18603 // CHECK30-NEXT: store i32 [[ADD9]], i32* [[A]], align 4 18604 // CHECK30-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2 18605 // CHECK30-NEXT: [[TMP13:%.*]] = load float, float* [[ARRAYIDX]], align 4 18606 // CHECK30-NEXT: [[CONV10:%.*]] = fpext float [[TMP13]] to double 18607 // CHECK30-NEXT: [[ADD11:%.*]] = fadd double [[CONV10]], 1.000000e+00 18608 // CHECK30-NEXT: [[CONV12:%.*]] = fptrunc double [[ADD11]] to float 18609 // CHECK30-NEXT: store float [[CONV12]], float* [[ARRAYIDX]], align 4 18610 // CHECK30-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3 18611 // CHECK30-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX13]], align 4 18612 // CHECK30-NEXT: [[CONV14:%.*]] = fpext float [[TMP14]] to double 18613 // CHECK30-NEXT: [[ADD15:%.*]] = fadd double [[CONV14]], 1.000000e+00 18614 // CHECK30-NEXT: [[CONV16:%.*]] = fptrunc double [[ADD15]] to float 18615 // CHECK30-NEXT: store float [[CONV16]], float* [[ARRAYIDX13]], align 4 18616 // CHECK30-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1 18617 // CHECK30-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX17]], i64 0, i64 2 18618 // CHECK30-NEXT: [[TMP15:%.*]] = load double, double* [[ARRAYIDX18]], align 8 18619 // CHECK30-NEXT: [[ADD19:%.*]] = fadd double [[TMP15]], 1.000000e+00 18620 // CHECK30-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8 18621 // CHECK30-NEXT: [[TMP16:%.*]] = mul nsw i64 1, [[TMP4]] 18622 // CHECK30-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP16]] 18623 // CHECK30-NEXT: [[ARRAYIDX21:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX20]], i64 3 18624 // CHECK30-NEXT: [[TMP17:%.*]] = load double, double* [[ARRAYIDX21]], align 8 18625 // CHECK30-NEXT: [[ADD22:%.*]] = fadd double [[TMP17]], 1.000000e+00 18626 // CHECK30-NEXT: store double [[ADD22]], double* [[ARRAYIDX21]], align 8 18627 // CHECK30-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 18628 // CHECK30-NEXT: [[TMP18:%.*]] = load i64, i64* [[X]], align 8 18629 // CHECK30-NEXT: [[ADD23:%.*]] = add nsw i64 [[TMP18]], 1 18630 // CHECK30-NEXT: store i64 [[ADD23]], i64* [[X]], align 8 18631 // CHECK30-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 18632 // CHECK30-NEXT: [[TMP19:%.*]] = load i8, i8* [[Y]], align 8 18633 // CHECK30-NEXT: [[CONV24:%.*]] = sext i8 [[TMP19]] to i32 18634 // CHECK30-NEXT: [[ADD25:%.*]] = add nsw i32 [[CONV24]], 1 18635 // CHECK30-NEXT: [[CONV26:%.*]] = trunc i32 [[ADD25]] to i8 18636 // CHECK30-NEXT: store i8 [[CONV26]], i8* [[Y]], align 8 18637 // CHECK30-NEXT: store i32 0, i32* [[NN]], align 4 18638 // CHECK30-NEXT: [[TMP20:%.*]] = load i32, i32* [[A]], align 4 18639 // CHECK30-NEXT: [[TMP21:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 18640 // CHECK30-NEXT: call void @llvm.stackrestore(i8* [[TMP21]]) 18641 // CHECK30-NEXT: ret i32 [[TMP20]] 18642 // 18643 // 18644 // CHECK30-LABEL: define {{[^@]+}}@_Z6bazzzziPi 18645 // CHECK30-SAME: (i32 signext [[N:%.*]], i32* [[F:%.*]]) #[[ATTR0]] { 18646 // CHECK30-NEXT: entry: 18647 // CHECK30-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 18648 // CHECK30-NEXT: [[F_ADDR:%.*]] = alloca i32*, align 8 18649 // CHECK30-NEXT: [[F1:%.*]] = alloca i32*, align 8 18650 // CHECK30-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 18651 // CHECK30-NEXT: store i32* [[F]], i32** [[F_ADDR]], align 8 18652 // CHECK30-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 18653 // CHECK30-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 18654 // CHECK30-NEXT: ret void 18655 // 18656 // 18657 // CHECK30-LABEL: define {{[^@]+}}@_Z3bari 18658 // CHECK30-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { 18659 // CHECK30-NEXT: entry: 18660 // CHECK30-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 18661 // CHECK30-NEXT: [[A:%.*]] = alloca i32, align 4 18662 // CHECK30-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 18663 // CHECK30-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 18664 // CHECK30-NEXT: store i32 0, i32* [[A]], align 4 18665 // CHECK30-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 18666 // CHECK30-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]]) 18667 // CHECK30-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 18668 // CHECK30-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 18669 // CHECK30-NEXT: store i32 [[ADD]], i32* [[A]], align 4 18670 // CHECK30-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 18671 // CHECK30-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]]) 18672 // CHECK30-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 18673 // CHECK30-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 18674 // CHECK30-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 18675 // CHECK30-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 18676 // CHECK30-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]]) 18677 // CHECK30-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 18678 // CHECK30-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 18679 // CHECK30-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 18680 // CHECK30-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 18681 // CHECK30-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]]) 18682 // CHECK30-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 18683 // CHECK30-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] 18684 // CHECK30-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 18685 // CHECK30-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 18686 // CHECK30-NEXT: ret i32 [[TMP8]] 18687 // 18688 // 18689 // CHECK30-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 18690 // CHECK30-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { 18691 // CHECK30-NEXT: entry: 18692 // CHECK30-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 18693 // CHECK30-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 18694 // CHECK30-NEXT: [[B:%.*]] = alloca i32, align 4 18695 // CHECK30-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 18696 // CHECK30-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 18697 // CHECK30-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 18698 // CHECK30-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 18699 // CHECK30-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 18700 // CHECK30-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 18701 // CHECK30-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 18702 // CHECK30-NEXT: store i32 [[ADD]], i32* [[B]], align 4 18703 // CHECK30-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 18704 // CHECK30-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 18705 // CHECK30-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() 18706 // CHECK30-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 18707 // CHECK30-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] 18708 // CHECK30-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 18709 // CHECK30-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 18710 // CHECK30-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 18711 // CHECK30-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP5]] to double 18712 // CHECK30-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 18713 // CHECK30-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 18714 // CHECK30-NEXT: store double [[ADD2]], double* [[A]], align 8 18715 // CHECK30-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 18716 // CHECK30-NEXT: [[TMP6:%.*]] = load double, double* [[A3]], align 8 18717 // CHECK30-NEXT: [[INC:%.*]] = fadd double [[TMP6]], 1.000000e+00 18718 // CHECK30-NEXT: store double [[INC]], double* [[A3]], align 8 18719 // CHECK30-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 18720 // CHECK30-NEXT: [[TMP7:%.*]] = mul nsw i64 1, [[TMP2]] 18721 // CHECK30-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP7]] 18722 // CHECK30-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 18723 // CHECK30-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 18724 // CHECK30-NEXT: [[TMP8:%.*]] = mul nsw i64 1, [[TMP2]] 18725 // CHECK30-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP8]] 18726 // CHECK30-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i64 1 18727 // CHECK30-NEXT: [[TMP9:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2 18728 // CHECK30-NEXT: [[CONV8:%.*]] = sext i16 [[TMP9]] to i32 18729 // CHECK30-NEXT: [[TMP10:%.*]] = load i32, i32* [[B]], align 4 18730 // CHECK30-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP10]] 18731 // CHECK30-NEXT: [[TMP11:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 18732 // CHECK30-NEXT: call void @llvm.stackrestore(i8* [[TMP11]]) 18733 // CHECK30-NEXT: ret i32 [[ADD9]] 18734 // 18735 // 18736 // CHECK30-LABEL: define {{[^@]+}}@_ZL7fstatici 18737 // CHECK30-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { 18738 // CHECK30-NEXT: entry: 18739 // CHECK30-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 18740 // CHECK30-NEXT: [[A:%.*]] = alloca i32, align 4 18741 // CHECK30-NEXT: [[AA:%.*]] = alloca i16, align 2 18742 // CHECK30-NEXT: [[AAA:%.*]] = alloca i8, align 1 18743 // CHECK30-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 18744 // CHECK30-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 18745 // CHECK30-NEXT: store i32 0, i32* [[A]], align 4 18746 // CHECK30-NEXT: store i16 0, i16* [[AA]], align 2 18747 // CHECK30-NEXT: store i8 0, i8* [[AAA]], align 1 18748 // CHECK30-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 18749 // CHECK30-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 18750 // CHECK30-NEXT: store i32 [[ADD]], i32* [[A]], align 4 18751 // CHECK30-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 18752 // CHECK30-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 18753 // CHECK30-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 18754 // CHECK30-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 18755 // CHECK30-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 18756 // CHECK30-NEXT: [[TMP2:%.*]] = load i8, i8* [[AAA]], align 1 18757 // CHECK30-NEXT: [[CONV3:%.*]] = sext i8 [[TMP2]] to i32 18758 // CHECK30-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 18759 // CHECK30-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 18760 // CHECK30-NEXT: store i8 [[CONV5]], i8* [[AAA]], align 1 18761 // CHECK30-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 18762 // CHECK30-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 18763 // CHECK30-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP3]], 1 18764 // CHECK30-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 18765 // CHECK30-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 18766 // CHECK30-NEXT: ret i32 [[TMP4]] 18767 // 18768 // 18769 // CHECK30-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 18770 // CHECK30-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { 18771 // CHECK30-NEXT: entry: 18772 // CHECK30-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 18773 // CHECK30-NEXT: [[A:%.*]] = alloca i32, align 4 18774 // CHECK30-NEXT: [[AA:%.*]] = alloca i16, align 2 18775 // CHECK30-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 18776 // CHECK30-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 18777 // CHECK30-NEXT: store i32 0, i32* [[A]], align 4 18778 // CHECK30-NEXT: store i16 0, i16* [[AA]], align 2 18779 // CHECK30-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 18780 // CHECK30-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 18781 // CHECK30-NEXT: store i32 [[ADD]], i32* [[A]], align 4 18782 // CHECK30-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 18783 // CHECK30-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 18784 // CHECK30-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 18785 // CHECK30-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 18786 // CHECK30-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 18787 // CHECK30-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 18788 // CHECK30-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 18789 // CHECK30-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP2]], 1 18790 // CHECK30-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 18791 // CHECK30-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 18792 // CHECK30-NEXT: ret i32 [[TMP3]] 18793 // 18794 // 18795 // CHECK31-LABEL: define {{[^@]+}}@_Z3fooi 18796 // CHECK31-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { 18797 // CHECK31-NEXT: entry: 18798 // CHECK31-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 18799 // CHECK31-NEXT: [[A:%.*]] = alloca i32, align 4 18800 // CHECK31-NEXT: [[AA:%.*]] = alloca i16, align 2 18801 // CHECK31-NEXT: [[B:%.*]] = alloca [10 x float], align 4 18802 // CHECK31-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 18803 // CHECK31-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 18804 // CHECK31-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 18805 // CHECK31-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 18806 // CHECK31-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 18807 // CHECK31-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 18808 // CHECK31-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 18809 // CHECK31-NEXT: [[NN:%.*]] = alloca i32, align 4 18810 // CHECK31-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 18811 // CHECK31-NEXT: store i32 0, i32* [[A]], align 4 18812 // CHECK31-NEXT: store i16 0, i16* [[AA]], align 2 18813 // CHECK31-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 18814 // CHECK31-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() 18815 // CHECK31-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 18816 // CHECK31-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4 18817 // CHECK31-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 18818 // CHECK31-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 18819 // CHECK31-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]] 18820 // CHECK31-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8 18821 // CHECK31-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4 18822 // CHECK31-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 18823 // CHECK31-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 18824 // CHECK31-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 18825 // CHECK31-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_2]], align 4 18826 // CHECK31-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 18827 // CHECK31-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], 1 18828 // CHECK31-NEXT: store i32 [[ADD]], i32* [[A]], align 4 18829 // CHECK31-NEXT: [[TMP7:%.*]] = load i16, i16* [[AA]], align 2 18830 // CHECK31-NEXT: [[CONV:%.*]] = sext i16 [[TMP7]] to i32 18831 // CHECK31-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1 18832 // CHECK31-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 18833 // CHECK31-NEXT: store i16 [[CONV4]], i16* [[AA]], align 2 18834 // CHECK31-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 18835 // CHECK31-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP8]], 1 18836 // CHECK31-NEXT: store i32 [[ADD5]], i32* [[A]], align 4 18837 // CHECK31-NEXT: [[TMP9:%.*]] = load i16, i16* [[AA]], align 2 18838 // CHECK31-NEXT: [[CONV6:%.*]] = sext i16 [[TMP9]] to i32 18839 // CHECK31-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 18840 // CHECK31-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i16 18841 // CHECK31-NEXT: store i16 [[CONV8]], i16* [[AA]], align 2 18842 // CHECK31-NEXT: [[TMP10:%.*]] = load i32, i32* [[A]], align 4 18843 // CHECK31-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP10]], 1 18844 // CHECK31-NEXT: store i32 [[ADD9]], i32* [[A]], align 4 18845 // CHECK31-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2 18846 // CHECK31-NEXT: [[TMP11:%.*]] = load float, float* [[ARRAYIDX]], align 4 18847 // CHECK31-NEXT: [[CONV10:%.*]] = fpext float [[TMP11]] to double 18848 // CHECK31-NEXT: [[ADD11:%.*]] = fadd double [[CONV10]], 1.000000e+00 18849 // CHECK31-NEXT: [[CONV12:%.*]] = fptrunc double [[ADD11]] to float 18850 // CHECK31-NEXT: store float [[CONV12]], float* [[ARRAYIDX]], align 4 18851 // CHECK31-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3 18852 // CHECK31-NEXT: [[TMP12:%.*]] = load float, float* [[ARRAYIDX13]], align 4 18853 // CHECK31-NEXT: [[CONV14:%.*]] = fpext float [[TMP12]] to double 18854 // CHECK31-NEXT: [[ADD15:%.*]] = fadd double [[CONV14]], 1.000000e+00 18855 // CHECK31-NEXT: [[CONV16:%.*]] = fptrunc double [[ADD15]] to float 18856 // CHECK31-NEXT: store float [[CONV16]], float* [[ARRAYIDX13]], align 4 18857 // CHECK31-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1 18858 // CHECK31-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX17]], i32 0, i32 2 18859 // CHECK31-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX18]], align 8 18860 // CHECK31-NEXT: [[ADD19:%.*]] = fadd double [[TMP13]], 1.000000e+00 18861 // CHECK31-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8 18862 // CHECK31-NEXT: [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]] 18863 // CHECK31-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP14]] 18864 // CHECK31-NEXT: [[ARRAYIDX21:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX20]], i32 3 18865 // CHECK31-NEXT: [[TMP15:%.*]] = load double, double* [[ARRAYIDX21]], align 8 18866 // CHECK31-NEXT: [[ADD22:%.*]] = fadd double [[TMP15]], 1.000000e+00 18867 // CHECK31-NEXT: store double [[ADD22]], double* [[ARRAYIDX21]], align 8 18868 // CHECK31-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 18869 // CHECK31-NEXT: [[TMP16:%.*]] = load i64, i64* [[X]], align 4 18870 // CHECK31-NEXT: [[ADD23:%.*]] = add nsw i64 [[TMP16]], 1 18871 // CHECK31-NEXT: store i64 [[ADD23]], i64* [[X]], align 4 18872 // CHECK31-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 18873 // CHECK31-NEXT: [[TMP17:%.*]] = load i8, i8* [[Y]], align 4 18874 // CHECK31-NEXT: [[CONV24:%.*]] = sext i8 [[TMP17]] to i32 18875 // CHECK31-NEXT: [[ADD25:%.*]] = add nsw i32 [[CONV24]], 1 18876 // CHECK31-NEXT: [[CONV26:%.*]] = trunc i32 [[ADD25]] to i8 18877 // CHECK31-NEXT: store i8 [[CONV26]], i8* [[Y]], align 4 18878 // CHECK31-NEXT: store i32 0, i32* [[NN]], align 4 18879 // CHECK31-NEXT: [[TMP18:%.*]] = load i32, i32* [[A]], align 4 18880 // CHECK31-NEXT: [[TMP19:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 18881 // CHECK31-NEXT: call void @llvm.stackrestore(i8* [[TMP19]]) 18882 // CHECK31-NEXT: ret i32 [[TMP18]] 18883 // 18884 // 18885 // CHECK31-LABEL: define {{[^@]+}}@_Z6bazzzziPi 18886 // CHECK31-SAME: (i32 [[N:%.*]], i32* [[F:%.*]]) #[[ATTR0]] { 18887 // CHECK31-NEXT: entry: 18888 // CHECK31-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 18889 // CHECK31-NEXT: [[F_ADDR:%.*]] = alloca i32*, align 4 18890 // CHECK31-NEXT: [[F1:%.*]] = alloca i32*, align 4 18891 // CHECK31-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 18892 // CHECK31-NEXT: store i32* [[F]], i32** [[F_ADDR]], align 4 18893 // CHECK31-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 18894 // CHECK31-NEXT: ret void 18895 // 18896 // 18897 // CHECK31-LABEL: define {{[^@]+}}@_Z3bari 18898 // CHECK31-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { 18899 // CHECK31-NEXT: entry: 18900 // CHECK31-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 18901 // CHECK31-NEXT: [[A:%.*]] = alloca i32, align 4 18902 // CHECK31-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 18903 // CHECK31-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 18904 // CHECK31-NEXT: store i32 0, i32* [[A]], align 4 18905 // CHECK31-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 18906 // CHECK31-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]]) 18907 // CHECK31-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 18908 // CHECK31-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 18909 // CHECK31-NEXT: store i32 [[ADD]], i32* [[A]], align 4 18910 // CHECK31-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 18911 // CHECK31-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]]) 18912 // CHECK31-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 18913 // CHECK31-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 18914 // CHECK31-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 18915 // CHECK31-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 18916 // CHECK31-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]]) 18917 // CHECK31-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 18918 // CHECK31-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 18919 // CHECK31-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 18920 // CHECK31-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 18921 // CHECK31-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]]) 18922 // CHECK31-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 18923 // CHECK31-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] 18924 // CHECK31-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 18925 // CHECK31-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 18926 // CHECK31-NEXT: ret i32 [[TMP8]] 18927 // 18928 // 18929 // CHECK31-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 18930 // CHECK31-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { 18931 // CHECK31-NEXT: entry: 18932 // CHECK31-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 18933 // CHECK31-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 18934 // CHECK31-NEXT: [[B:%.*]] = alloca i32, align 4 18935 // CHECK31-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 18936 // CHECK31-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 18937 // CHECK31-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 18938 // CHECK31-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 18939 // CHECK31-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 18940 // CHECK31-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 18941 // CHECK31-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 18942 // CHECK31-NEXT: store i32 [[ADD]], i32* [[B]], align 4 18943 // CHECK31-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 18944 // CHECK31-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() 18945 // CHECK31-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 18946 // CHECK31-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] 18947 // CHECK31-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 18948 // CHECK31-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 18949 // CHECK31-NEXT: [[TMP4:%.*]] = load i32, i32* [[B]], align 4 18950 // CHECK31-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP4]] to double 18951 // CHECK31-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 18952 // CHECK31-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 18953 // CHECK31-NEXT: store double [[ADD2]], double* [[A]], align 4 18954 // CHECK31-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 18955 // CHECK31-NEXT: [[TMP5:%.*]] = load double, double* [[A3]], align 4 18956 // CHECK31-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 18957 // CHECK31-NEXT: store double [[INC]], double* [[A3]], align 4 18958 // CHECK31-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 18959 // CHECK31-NEXT: [[TMP6:%.*]] = mul nsw i32 1, [[TMP1]] 18960 // CHECK31-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP6]] 18961 // CHECK31-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 18962 // CHECK31-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 18963 // CHECK31-NEXT: [[TMP7:%.*]] = mul nsw i32 1, [[TMP1]] 18964 // CHECK31-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP7]] 18965 // CHECK31-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i32 1 18966 // CHECK31-NEXT: [[TMP8:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2 18967 // CHECK31-NEXT: [[CONV8:%.*]] = sext i16 [[TMP8]] to i32 18968 // CHECK31-NEXT: [[TMP9:%.*]] = load i32, i32* [[B]], align 4 18969 // CHECK31-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP9]] 18970 // CHECK31-NEXT: [[TMP10:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 18971 // CHECK31-NEXT: call void @llvm.stackrestore(i8* [[TMP10]]) 18972 // CHECK31-NEXT: ret i32 [[ADD9]] 18973 // 18974 // 18975 // CHECK31-LABEL: define {{[^@]+}}@_ZL7fstatici 18976 // CHECK31-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { 18977 // CHECK31-NEXT: entry: 18978 // CHECK31-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 18979 // CHECK31-NEXT: [[A:%.*]] = alloca i32, align 4 18980 // CHECK31-NEXT: [[AA:%.*]] = alloca i16, align 2 18981 // CHECK31-NEXT: [[AAA:%.*]] = alloca i8, align 1 18982 // CHECK31-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 18983 // CHECK31-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 18984 // CHECK31-NEXT: store i32 0, i32* [[A]], align 4 18985 // CHECK31-NEXT: store i16 0, i16* [[AA]], align 2 18986 // CHECK31-NEXT: store i8 0, i8* [[AAA]], align 1 18987 // CHECK31-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 18988 // CHECK31-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 18989 // CHECK31-NEXT: store i32 [[ADD]], i32* [[A]], align 4 18990 // CHECK31-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 18991 // CHECK31-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 18992 // CHECK31-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 18993 // CHECK31-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 18994 // CHECK31-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 18995 // CHECK31-NEXT: [[TMP2:%.*]] = load i8, i8* [[AAA]], align 1 18996 // CHECK31-NEXT: [[CONV3:%.*]] = sext i8 [[TMP2]] to i32 18997 // CHECK31-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 18998 // CHECK31-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 18999 // CHECK31-NEXT: store i8 [[CONV5]], i8* [[AAA]], align 1 19000 // CHECK31-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 19001 // CHECK31-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 19002 // CHECK31-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP3]], 1 19003 // CHECK31-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 19004 // CHECK31-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 19005 // CHECK31-NEXT: ret i32 [[TMP4]] 19006 // 19007 // 19008 // CHECK31-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 19009 // CHECK31-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { 19010 // CHECK31-NEXT: entry: 19011 // CHECK31-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 19012 // CHECK31-NEXT: [[A:%.*]] = alloca i32, align 4 19013 // CHECK31-NEXT: [[AA:%.*]] = alloca i16, align 2 19014 // CHECK31-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 19015 // CHECK31-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 19016 // CHECK31-NEXT: store i32 0, i32* [[A]], align 4 19017 // CHECK31-NEXT: store i16 0, i16* [[AA]], align 2 19018 // CHECK31-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 19019 // CHECK31-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 19020 // CHECK31-NEXT: store i32 [[ADD]], i32* [[A]], align 4 19021 // CHECK31-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 19022 // CHECK31-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 19023 // CHECK31-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 19024 // CHECK31-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 19025 // CHECK31-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 19026 // CHECK31-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 19027 // CHECK31-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 19028 // CHECK31-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP2]], 1 19029 // CHECK31-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 19030 // CHECK31-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 19031 // CHECK31-NEXT: ret i32 [[TMP3]] 19032 // 19033 // 19034 // CHECK32-LABEL: define {{[^@]+}}@_Z3fooi 19035 // CHECK32-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { 19036 // CHECK32-NEXT: entry: 19037 // CHECK32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 19038 // CHECK32-NEXT: [[A:%.*]] = alloca i32, align 4 19039 // CHECK32-NEXT: [[AA:%.*]] = alloca i16, align 2 19040 // CHECK32-NEXT: [[B:%.*]] = alloca [10 x float], align 4 19041 // CHECK32-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 19042 // CHECK32-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 19043 // CHECK32-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 19044 // CHECK32-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 19045 // CHECK32-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 19046 // CHECK32-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 19047 // CHECK32-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 19048 // CHECK32-NEXT: [[NN:%.*]] = alloca i32, align 4 19049 // CHECK32-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 19050 // CHECK32-NEXT: store i32 0, i32* [[A]], align 4 19051 // CHECK32-NEXT: store i16 0, i16* [[AA]], align 2 19052 // CHECK32-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 19053 // CHECK32-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() 19054 // CHECK32-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 19055 // CHECK32-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4 19056 // CHECK32-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 19057 // CHECK32-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 19058 // CHECK32-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]] 19059 // CHECK32-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8 19060 // CHECK32-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4 19061 // CHECK32-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 19062 // CHECK32-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 19063 // CHECK32-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 19064 // CHECK32-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_2]], align 4 19065 // CHECK32-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 19066 // CHECK32-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], 1 19067 // CHECK32-NEXT: store i32 [[ADD]], i32* [[A]], align 4 19068 // CHECK32-NEXT: [[TMP7:%.*]] = load i16, i16* [[AA]], align 2 19069 // CHECK32-NEXT: [[CONV:%.*]] = sext i16 [[TMP7]] to i32 19070 // CHECK32-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1 19071 // CHECK32-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 19072 // CHECK32-NEXT: store i16 [[CONV4]], i16* [[AA]], align 2 19073 // CHECK32-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 19074 // CHECK32-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP8]], 1 19075 // CHECK32-NEXT: store i32 [[ADD5]], i32* [[A]], align 4 19076 // CHECK32-NEXT: [[TMP9:%.*]] = load i16, i16* [[AA]], align 2 19077 // CHECK32-NEXT: [[CONV6:%.*]] = sext i16 [[TMP9]] to i32 19078 // CHECK32-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 19079 // CHECK32-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i16 19080 // CHECK32-NEXT: store i16 [[CONV8]], i16* [[AA]], align 2 19081 // CHECK32-NEXT: [[TMP10:%.*]] = load i32, i32* [[A]], align 4 19082 // CHECK32-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP10]], 1 19083 // CHECK32-NEXT: store i32 [[ADD9]], i32* [[A]], align 4 19084 // CHECK32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2 19085 // CHECK32-NEXT: [[TMP11:%.*]] = load float, float* [[ARRAYIDX]], align 4 19086 // CHECK32-NEXT: [[CONV10:%.*]] = fpext float [[TMP11]] to double 19087 // CHECK32-NEXT: [[ADD11:%.*]] = fadd double [[CONV10]], 1.000000e+00 19088 // CHECK32-NEXT: [[CONV12:%.*]] = fptrunc double [[ADD11]] to float 19089 // CHECK32-NEXT: store float [[CONV12]], float* [[ARRAYIDX]], align 4 19090 // CHECK32-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3 19091 // CHECK32-NEXT: [[TMP12:%.*]] = load float, float* [[ARRAYIDX13]], align 4 19092 // CHECK32-NEXT: [[CONV14:%.*]] = fpext float [[TMP12]] to double 19093 // CHECK32-NEXT: [[ADD15:%.*]] = fadd double [[CONV14]], 1.000000e+00 19094 // CHECK32-NEXT: [[CONV16:%.*]] = fptrunc double [[ADD15]] to float 19095 // CHECK32-NEXT: store float [[CONV16]], float* [[ARRAYIDX13]], align 4 19096 // CHECK32-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1 19097 // CHECK32-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX17]], i32 0, i32 2 19098 // CHECK32-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX18]], align 8 19099 // CHECK32-NEXT: [[ADD19:%.*]] = fadd double [[TMP13]], 1.000000e+00 19100 // CHECK32-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8 19101 // CHECK32-NEXT: [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]] 19102 // CHECK32-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP14]] 19103 // CHECK32-NEXT: [[ARRAYIDX21:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX20]], i32 3 19104 // CHECK32-NEXT: [[TMP15:%.*]] = load double, double* [[ARRAYIDX21]], align 8 19105 // CHECK32-NEXT: [[ADD22:%.*]] = fadd double [[TMP15]], 1.000000e+00 19106 // CHECK32-NEXT: store double [[ADD22]], double* [[ARRAYIDX21]], align 8 19107 // CHECK32-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 19108 // CHECK32-NEXT: [[TMP16:%.*]] = load i64, i64* [[X]], align 4 19109 // CHECK32-NEXT: [[ADD23:%.*]] = add nsw i64 [[TMP16]], 1 19110 // CHECK32-NEXT: store i64 [[ADD23]], i64* [[X]], align 4 19111 // CHECK32-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 19112 // CHECK32-NEXT: [[TMP17:%.*]] = load i8, i8* [[Y]], align 4 19113 // CHECK32-NEXT: [[CONV24:%.*]] = sext i8 [[TMP17]] to i32 19114 // CHECK32-NEXT: [[ADD25:%.*]] = add nsw i32 [[CONV24]], 1 19115 // CHECK32-NEXT: [[CONV26:%.*]] = trunc i32 [[ADD25]] to i8 19116 // CHECK32-NEXT: store i8 [[CONV26]], i8* [[Y]], align 4 19117 // CHECK32-NEXT: store i32 0, i32* [[NN]], align 4 19118 // CHECK32-NEXT: [[TMP18:%.*]] = load i32, i32* [[A]], align 4 19119 // CHECK32-NEXT: [[TMP19:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 19120 // CHECK32-NEXT: call void @llvm.stackrestore(i8* [[TMP19]]) 19121 // CHECK32-NEXT: ret i32 [[TMP18]] 19122 // 19123 // 19124 // CHECK32-LABEL: define {{[^@]+}}@_Z6bazzzziPi 19125 // CHECK32-SAME: (i32 [[N:%.*]], i32* [[F:%.*]]) #[[ATTR0]] { 19126 // CHECK32-NEXT: entry: 19127 // CHECK32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 19128 // CHECK32-NEXT: [[F_ADDR:%.*]] = alloca i32*, align 4 19129 // CHECK32-NEXT: [[F1:%.*]] = alloca i32*, align 4 19130 // CHECK32-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 19131 // CHECK32-NEXT: store i32* [[F]], i32** [[F_ADDR]], align 4 19132 // CHECK32-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 19133 // CHECK32-NEXT: ret void 19134 // 19135 // 19136 // CHECK32-LABEL: define {{[^@]+}}@_Z3bari 19137 // CHECK32-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { 19138 // CHECK32-NEXT: entry: 19139 // CHECK32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 19140 // CHECK32-NEXT: [[A:%.*]] = alloca i32, align 4 19141 // CHECK32-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 19142 // CHECK32-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 19143 // CHECK32-NEXT: store i32 0, i32* [[A]], align 4 19144 // CHECK32-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 19145 // CHECK32-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]]) 19146 // CHECK32-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 19147 // CHECK32-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 19148 // CHECK32-NEXT: store i32 [[ADD]], i32* [[A]], align 4 19149 // CHECK32-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 19150 // CHECK32-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]]) 19151 // CHECK32-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 19152 // CHECK32-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 19153 // CHECK32-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 19154 // CHECK32-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 19155 // CHECK32-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]]) 19156 // CHECK32-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 19157 // CHECK32-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 19158 // CHECK32-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 19159 // CHECK32-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 19160 // CHECK32-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]]) 19161 // CHECK32-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 19162 // CHECK32-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] 19163 // CHECK32-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 19164 // CHECK32-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 19165 // CHECK32-NEXT: ret i32 [[TMP8]] 19166 // 19167 // 19168 // CHECK32-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 19169 // CHECK32-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { 19170 // CHECK32-NEXT: entry: 19171 // CHECK32-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 19172 // CHECK32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 19173 // CHECK32-NEXT: [[B:%.*]] = alloca i32, align 4 19174 // CHECK32-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 19175 // CHECK32-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 19176 // CHECK32-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 19177 // CHECK32-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 19178 // CHECK32-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 19179 // CHECK32-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 19180 // CHECK32-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 19181 // CHECK32-NEXT: store i32 [[ADD]], i32* [[B]], align 4 19182 // CHECK32-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 19183 // CHECK32-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() 19184 // CHECK32-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 19185 // CHECK32-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] 19186 // CHECK32-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 19187 // CHECK32-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 19188 // CHECK32-NEXT: [[TMP4:%.*]] = load i32, i32* [[B]], align 4 19189 // CHECK32-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP4]] to double 19190 // CHECK32-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 19191 // CHECK32-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 19192 // CHECK32-NEXT: store double [[ADD2]], double* [[A]], align 4 19193 // CHECK32-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 19194 // CHECK32-NEXT: [[TMP5:%.*]] = load double, double* [[A3]], align 4 19195 // CHECK32-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 19196 // CHECK32-NEXT: store double [[INC]], double* [[A3]], align 4 19197 // CHECK32-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 19198 // CHECK32-NEXT: [[TMP6:%.*]] = mul nsw i32 1, [[TMP1]] 19199 // CHECK32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP6]] 19200 // CHECK32-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 19201 // CHECK32-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 19202 // CHECK32-NEXT: [[TMP7:%.*]] = mul nsw i32 1, [[TMP1]] 19203 // CHECK32-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP7]] 19204 // CHECK32-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i32 1 19205 // CHECK32-NEXT: [[TMP8:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2 19206 // CHECK32-NEXT: [[CONV8:%.*]] = sext i16 [[TMP8]] to i32 19207 // CHECK32-NEXT: [[TMP9:%.*]] = load i32, i32* [[B]], align 4 19208 // CHECK32-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP9]] 19209 // CHECK32-NEXT: [[TMP10:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 19210 // CHECK32-NEXT: call void @llvm.stackrestore(i8* [[TMP10]]) 19211 // CHECK32-NEXT: ret i32 [[ADD9]] 19212 // 19213 // 19214 // CHECK32-LABEL: define {{[^@]+}}@_ZL7fstatici 19215 // CHECK32-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { 19216 // CHECK32-NEXT: entry: 19217 // CHECK32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 19218 // CHECK32-NEXT: [[A:%.*]] = alloca i32, align 4 19219 // CHECK32-NEXT: [[AA:%.*]] = alloca i16, align 2 19220 // CHECK32-NEXT: [[AAA:%.*]] = alloca i8, align 1 19221 // CHECK32-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 19222 // CHECK32-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 19223 // CHECK32-NEXT: store i32 0, i32* [[A]], align 4 19224 // CHECK32-NEXT: store i16 0, i16* [[AA]], align 2 19225 // CHECK32-NEXT: store i8 0, i8* [[AAA]], align 1 19226 // CHECK32-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 19227 // CHECK32-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 19228 // CHECK32-NEXT: store i32 [[ADD]], i32* [[A]], align 4 19229 // CHECK32-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 19230 // CHECK32-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 19231 // CHECK32-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 19232 // CHECK32-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 19233 // CHECK32-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 19234 // CHECK32-NEXT: [[TMP2:%.*]] = load i8, i8* [[AAA]], align 1 19235 // CHECK32-NEXT: [[CONV3:%.*]] = sext i8 [[TMP2]] to i32 19236 // CHECK32-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 19237 // CHECK32-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 19238 // CHECK32-NEXT: store i8 [[CONV5]], i8* [[AAA]], align 1 19239 // CHECK32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 19240 // CHECK32-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 19241 // CHECK32-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP3]], 1 19242 // CHECK32-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 19243 // CHECK32-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 19244 // CHECK32-NEXT: ret i32 [[TMP4]] 19245 // 19246 // 19247 // CHECK32-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 19248 // CHECK32-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { 19249 // CHECK32-NEXT: entry: 19250 // CHECK32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 19251 // CHECK32-NEXT: [[A:%.*]] = alloca i32, align 4 19252 // CHECK32-NEXT: [[AA:%.*]] = alloca i16, align 2 19253 // CHECK32-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 19254 // CHECK32-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 19255 // CHECK32-NEXT: store i32 0, i32* [[A]], align 4 19256 // CHECK32-NEXT: store i16 0, i16* [[AA]], align 2 19257 // CHECK32-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 19258 // CHECK32-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 19259 // CHECK32-NEXT: store i32 [[ADD]], i32* [[A]], align 4 19260 // CHECK32-NEXT: [[TMP1:%.*]] = load i16, i16* [[AA]], align 2 19261 // CHECK32-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 19262 // CHECK32-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 19263 // CHECK32-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 19264 // CHECK32-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 19265 // CHECK32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 19266 // CHECK32-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 19267 // CHECK32-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP2]], 1 19268 // CHECK32-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 19269 // CHECK32-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 19270 // CHECK32-NEXT: ret i32 [[TMP3]] 19271 // 19272